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 /**
   ******************************************************************************
   * @file    stm32l1xx_hal_cortex.c
   * @author  MCD Application Team
   * @brief   CORTEX HAL module driver.
   *
   *          This file provides firmware functions to manage the following
   *          functionalities of the CORTEX:
   *           + Initialization and de-initialization functions
   *           + Peripheral Control functions
   *
   *  @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
     [..]
     *** How to configure Interrupts using Cortex HAL driver ***
     ===========================================================
     [..]
     This section provide functions allowing to configure the NVIC interrupts (IRQ).
     The Cortex-M3 exceptions are managed by CMSIS functions.
     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
          The pending IRQ priority will be managed only by the sub priority.
      -@- IRQ priority order (sorted by highest to lowest priority):
         (+@) Lowest pre-emption priority
         (+@) Lowest sub priority
         (+@) Lowest hardware priority (IRQ number)
     [..]
     *** How to configure Systick using Cortex HAL driver ***
     ========================================================
     [..]
     Setup SysTick Timer for 1 msec interrupts.
    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
        is a CMSIS function that:
         (++) Configures the SysTick Reload register with value passed as function parameter.
         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
         (++) Resets the SysTick Counter register.
         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
         (++) Enables the SysTick Interrupt.
         (++) Starts the SysTick Counter.
    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
        inside the stm32l1xx_hal_cortex.h file.
    (+) You can change the SysTick IRQ priority by calling the
        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
    (+) To adjust the SysTick time base, use the following formula:
        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
        (++) Reload Value should not exceed 0xFFFFFF
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software is licensed under terms that can be found in the LICENSE file in
-  * the "License"; You may not use this file except in compliance with the
+  * the root directory of this software component.
-  * License. You may obtain a copy of the License at:
+  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *                        opensource.org/licenses/BSD-3-Clause
+  *
-  *
+  ******************************************************************************
-  ******************************************************************************
+  */
-  */
+/*
-/*
+  Additional Tables: CORTEX_NVIC_Priority_Table
-  Additional Tables: CORTEX_NVIC_Priority_Table
+     The table below gives the allowed values of the pre-emption priority and subpriority according
-     The table below gives the allowed values of the pre-emption priority and subpriority according
+     to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
-     to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+       ==========================================================================================================================
-       ==========================================================================================================================
+         NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
-         NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+       ==========================================================================================================================
-       ==========================================================================================================================
+        NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bits for pre-emption priority
-        NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+                              |                                   |                             | 4 bits for subpriority
-                              |                                   |                             | 4 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------
-       --------------------------------------------------------------------------------------------------------------------------
+        NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
-        NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+                              |                                   |                             | 3 bits for subpriority
-                              |                                   |                             | 3 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------
-       --------------------------------------------------------------------------------------------------------------------------
+        NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
-        NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+                              |                                   |                             | 2 bits for subpriority
-                              |                                   |                             | 2 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------
-       --------------------------------------------------------------------------------------------------------------------------
+        NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
-        NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+                              |                                   |                             | 1 bits for subpriority
-                              |                                   |                             | 1 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------
-       --------------------------------------------------------------------------------------------------------------------------
+        NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
-        NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
+                              |                                   |                             | 0 bits for subpriority
-                              |                                   |                             | 0 bits for subpriority
+       ==========================================================================================================================
-       ==========================================================================================================================
+*/
-*/
+/* Includes ------------------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_hal.h"
-#include "stm32l1xx_hal.h"
+/** @addtogroup STM32L1xx_HAL_Driver
-/** @addtogroup STM32L1xx_HAL_Driver
+  * @{
-  * @{
+  */
-  */
+/** @defgroup CORTEX CORTEX
-/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
-  * @brief CORTEX HAL module driver
+  * @{
-  * @{
+  */
-  */
+#ifdef HAL_CORTEX_MODULE_ENABLED
-#ifdef HAL_CORTEX_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
-/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
-  * @{
+  */
-  */
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
- *  @brief    Initialization and Configuration functions
+ *
- *
+@verbatim
-@verbatim
+  ==============================================================================
-  ==============================================================================
+              ##### Initialization and de-initialization functions #####
-              ##### Initialization and de-initialization functions #####
+  ==============================================================================
-  ==============================================================================
+    [..]
-    [..]
+      This section provide the Cortex HAL driver functions allowing to configure Interrupts
-      This section provide the Cortex HAL driver functions allowing to configure Interrupts
+      Systick functionalities
-      Systick functionalities
+@endverbatim
-@endverbatim
+  * @{
-  * @{
+  */
-  */
+/**
-/**
+  * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
-  * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
+  *         using the required unlock sequence.
-  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length.
-  * @param  PriorityGroup The priority grouping bits length.
+  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+  *                                    4 bits for subpriority
-  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+  *                                    3 bits for subpriority
-  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+  *                                    2 bits for subpriority
-  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+  *                                    1 bits for subpriority
-  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+  *                                    0 bits for subpriority
-  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
-  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
-{
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
-  NVIC_SetPriorityGrouping(PriorityGroup);
+}
-}
+/**
-/**
+  * @brief  Sets the priority of an interrupt.
-  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number
-  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
+  * @param  PreemptPriority The pre-emption priority for the IRQn channel.
-  * @param  PreemptPriority The pre-emption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
-  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
-  *         A lower priority value indicates a higher priority
+  * @param  SubPriority the subpriority level for the IRQ channel.
-  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
-  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
-  *         A lower priority value indicates a higher priority.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
-{
+  uint32_t prioritygroup = 0x00;
-  uint32_t prioritygroup = 0x00;
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  prioritygroup = NVIC_GetPriorityGrouping();
-  prioritygroup = NVIC_GetPriorityGrouping();
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
-}
+/**
-/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
-  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
-  *         function should be called before.
+  * @param  IRQn External interrupt number
-  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
-{
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  /* Enable interrupt */
-  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
-  NVIC_EnableIRQ(IRQn);
+}
-}
+/**
-/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
-  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number
-  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
-{
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  /* Disable interrupt */
-  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
-  NVIC_DisableIRQ(IRQn);
+}
-}
+/**
-/**
+  * @brief  Initiates a system reset request to reset the MCU.
-  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_SystemReset(void)
-void HAL_NVIC_SystemReset(void)
+{
-{
+  /* System Reset */
-  /* System Reset */
+  NVIC_SystemReset();
-  NVIC_SystemReset();
+}
-}
+/**
-/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
-  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
-  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
-  *                  - 1  Function failed.
+  */
-  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
-{
+   return SysTick_Config(TicksNumb);
-   return SysTick_Config(TicksNumb);
+}
-}
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief    Cortex control functions
- *  @brief    Cortex control functions
+ *
- *
+@verbatim
-@verbatim
+  ==============================================================================
-  ==============================================================================
+                      ##### Peripheral Control functions #####
-                      ##### Peripheral Control functions #####
+  ==============================================================================
-  ==============================================================================
+    [..]
-    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
-      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
-      (NVIC, SYSTICK, MPU) functionalities.
+@endverbatim
-@endverbatim
+  * @{
-  * @{
+  */
-  */
+#if (__MPU_PRESENT == 1)
-#if (__MPU_PRESENT == 1)
+/**
-/**
+  * @brief  Enable the MPU.
-  * @brief  Enable the MPU.
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
-  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *          NMI, FAULTMASK and privileged accessto the default memory
-  *          NMI, FAULTMASK and privileged accessto the default memory
+  *          This parameter can be one of the following values:
-  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
-  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
-void HAL_MPU_Enable(uint32_t MPU_Control)
+{
-{
+  /* Enable the MPU */
-  /* Enable the MPU */
+  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
-  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+  /* Ensure MPU setting take effects */
-  /* Ensure MPU setting take effects */
+  __DSB();
-  __DSB();
+  __ISB();
-  __ISB();
+}
-}
+/**
-/**
+  * @brief  Disable the MPU.
-  * @brief  Disable the MPU.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_MPU_Disable(void)
-void HAL_MPU_Disable(void)
+{
-{
+  /* Make sure outstanding transfers are done */
-  /* Make sure outstanding transfers are done */
+  __DMB();
-  __DMB();
+  /* Disable the MPU and clear the control register*/
-  /* Disable the MPU and clear the control register*/
+  MPU->CTRL  = 0;
-  MPU->CTRL  = 0;
+}
-}
+/**
-/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
-  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
-  *                the initialization and configuration information.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
-{
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+  /* Set the Region number */
-  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
-  MPU->RNR = MPU_Init->Number;
+  if ((MPU_Init->Enable) != RESET)
-  if ((MPU_Init->Enable) != RESET)
+  {
-  {
+    /* Check the parameters */
-    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
-  }
+  else
-  else
+  {
-  {
+    MPU->RBAR = 0x00;
-    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
-    MPU->RASR = 0x00;
+  }
-  }
+}
-}
+#endif /* __MPU_PRESENT */
-#endif /* __MPU_PRESENT */
+/**
-/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
-  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
-  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
-{
+  /* Get the PRIGROUP[10:8] field value */
-  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
-  return NVIC_GetPriorityGrouping();
+}
-}
+/**
-/**
+  * @brief  Gets the priority of an interrupt.
-  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number
-  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
+  * @param  PriorityGroup the priority grouping bits length.
-  * @param  PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+  *                                      4 bits for subpriority
-  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+  *                                      3 bits for subpriority
-  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+  *                                      2 bits for subpriority
-  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+  *                                      1 bits for subpriority
-  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+  *                                      0 bits for subpriority
-  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
-  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
-  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
-{
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
- /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
-}
+/**
-/**
+  * @brief  Sets Pending bit of an external interrupt.
-  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
-  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
-{
+  /* Set interrupt pending */
-  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
-  NVIC_SetPendingIRQ(IRQn);
+}
-}
+/**
-/**
+  * @brief Gets Pending Interrupt (reads the pending register in the NVIC
-  * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+  *         and returns the pending bit for the specified interrupt).
-  *         and returns the pending bit for the specified interrupt).
+  * @param IRQn External interrupt number
-  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
-  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
-  *                 - 1  Interrupt status is pending.
+  */
-  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
-{
+  /* Return 1 if pending else 0 */
-  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
-  return NVIC_GetPendingIRQ(IRQn);
+}
-}
+/**
-/**
+  * @brief Clears the pending bit of an external interrupt.
-  * @brief Clears the pending bit of an external interrupt.
+  * @param IRQn External interrupt number
-  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
-{
+  /* Clear pending interrupt */
-  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
-  NVIC_ClearPendingIRQ(IRQn);
+}
-}
+/**
-/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
-  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
-  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
-  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
-  *                 - 1  Interrupt status is pending.
+  */
-  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
-{
+  /* Return 1 if active else 0 */
-  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
-  return NVIC_GetActive(IRQn);
+}
-}
+/**
-/**
+  * @brief  Configures the SysTick clock source.
-  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
-  * @param  CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
-{
+  /* Check the parameters */
-  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
-  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
-  }
+  else
-  else
+  {
-  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
-  }
+}
-}
+/**
-/**
+  * @brief  This function handles SYSTICK interrupt request.
-  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
-  * @retval None
+  */
-  */
+void HAL_SYSTICK_IRQHandler(void)
-void HAL_SYSTICK_IRQHandler(void)
+{
-{
+  HAL_SYSTICK_Callback();
-  HAL_SYSTICK_Callback();
+}
-}
+/**
-/**
+  * @brief  SYSTICK callback.
-  * @brief  SYSTICK callback.
+  * @retval None
-  * @retval None
+  */
-  */
+__weak void HAL_SYSTICK_Callback(void)
-__weak void HAL_SYSTICK_Callback(void)
+{
-{
+  /* NOTE : This function Should not be modified, when the callback is needed,
-  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
-            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
-   */
+}
-}
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+#endif /* HAL_CORTEX_MODULE_ENABLED */
-#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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