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1 | /** |
1 | /** |
2 | ****************************************************************************** |
2 | ****************************************************************************** |
3 | * @file stm32l1xx_hal_adc.c |
3 | * @file stm32l1xx_hal_adc.c |
4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
5 | * @brief This file provides firmware functions to manage the following |
5 | * @brief This file provides firmware functions to manage the following |
6 | * functionalities of the Analog to Digital Convertor (ADC) |
6 | * functionalities of the Analog to Digital Convertor (ADC) |
7 | * peripheral: |
7 | * peripheral: |
8 | * + Initialization and de-initialization functions |
8 | * + Initialization and de-initialization functions |
9 | * ++ Initialization and Configuration of ADC |
9 | * + Peripheral Control functions |
10 | * + Operation functions |
10 | * + Peripheral State functions |
11 | * ++ Start, stop, get result of conversions of regular |
11 | * Other functions (extended functions) are available in file |
12 | * group, using 3 possible modes: polling, interruption or DMA. |
12 | * "stm32l1xx_hal_adc_ex.c". |
13 | * + Control functions |
13 | * |
14 | * ++ Channels configuration on regular group |
14 | ****************************************************************************** |
15 | * ++ Channels configuration on injected group |
15 | * @attention |
16 | * ++ Analog Watchdog configuration |
16 | * |
17 | * + State functions |
17 | * Copyright (c) 2017 STMicroelectronics. |
18 | * ++ ADC state machine management |
18 | * All rights reserved. |
19 | * ++ Interrupts and flags management |
19 | * |
20 | * Other functions (extended functions) are available in file |
20 | * This software is licensed under terms that can be found in the LICENSE file |
21 | * "stm32l1xx_hal_adc_ex.c". |
21 | * in the root directory of this software component. |
22 | * |
22 | * If no LICENSE file comes with this software, it is provided AS-IS. |
23 | @verbatim |
23 | * |
24 | ============================================================================== |
24 | ****************************************************************************** |
25 | ##### ADC peripheral features ##### |
25 | @verbatim |
26 | ============================================================================== |
26 | ============================================================================== |
27 | [..] |
27 | ##### ADC peripheral features ##### |
28 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
28 | ============================================================================== |
29 | 29 | [..] |
|
30 | (+) Interrupt generation at the end of regular conversion, end of injected |
30 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
31 | conversion, and in case of analog watchdog or overrun events. |
31 | |
32 | |
32 | (+) Interrupt generation at the end of regular conversion, end of injected |
33 | (+) Single and continuous conversion modes. |
33 | conversion, and in case of analog watchdog or overrun events. |
34 | |
34 | |
35 | (+) Scan mode for conversion of several channels sequentially. |
35 | (+) Single and continuous conversion modes. |
36 | |
36 | |
37 | (+) Data alignment with in-built data coherency. |
37 | (+) Scan mode for conversion of several channels sequentially. |
38 | |
38 | |
39 | (+) Programmable sampling time (channel wise) |
39 | (+) Data alignment with in-built data coherency. |
40 | |
40 | |
41 | (+) ADC conversion of regular group and injected group. |
41 | (+) Programmable sampling time (channel wise) |
42 | |
42 | |
43 | (+) External trigger (timer or EXTI) with configurable polarity |
43 | (+) ADC conversion of regular group and injected group. |
44 | for both regular and injected groups. |
44 | |
45 | |
45 | (+) External trigger (timer or EXTI) with configurable polarity |
46 | (+) DMA request generation for transfer of conversions data of regular group. |
46 | for both regular and injected groups. |
47 | |
47 | |
48 | (+) ADC offset on injected channels |
48 | (+) DMA request generation for transfer of conversions data of regular group. |
49 | |
49 | |
50 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
50 | (+) ADC offset on injected channels |
51 | slower speed. |
51 | |
52 | |
52 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
53 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
53 | slower speed. |
54 | Vdda or to an external voltage reference). |
54 | |
55 | |
55 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
56 | |
56 | Vdda or to an external voltage reference). |
57 | ##### How to use this driver ##### |
57 | |
58 | ============================================================================== |
58 | |
59 | [..] |
59 | ##### How to use this driver ##### |
60 | 60 | ============================================================================== |
|
61 | *** Configuration of top level parameters related to ADC *** |
61 | [..] |
62 | ============================================================ |
62 | |
63 | [..] |
63 | *** Configuration of top level parameters related to ADC *** |
64 | 64 | ============================================================ |
|
65 | (#) Enable the ADC interface |
65 | [..] |
66 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
66 | |
67 | Caution: On STM32L1, ADC clock frequency max is 16MHz (refer |
67 | (#) Enable the ADC interface |
68 | to device datasheet). |
68 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
69 | Therefore, ADC clock prescaler must be configured in |
69 | Caution: On STM32L1, ADC clock frequency max is 16MHz (refer |
70 | function of ADC clock source frequency to remain below |
70 | to device datasheet). |
71 | this maximum frequency. |
71 | Therefore, ADC clock prescaler must be configured in |
72 | 72 | function of ADC clock source frequency to remain below |
|
73 | (++) Two clock settings are mandatory: |
73 | this maximum frequency. |
74 | (+++) ADC clock (core clock). |
74 | |
75 | (+++) ADC clock (conversions clock). |
75 | (++) Two clock settings are mandatory: |
76 | Only one possible clock source: derived from HSI RC 16MHz oscillator |
76 | (+++) ADC clock (core clock). |
77 | (HSI). |
77 | (+++) ADC clock (conversions clock). |
78 | ADC is connected directly to HSI RC 16MHz oscillator. |
78 | Only one possible clock source: derived from HSI RC 16MHz oscillator |
79 | Therefore, RCC PLL setting has no impact on ADC. |
79 | (HSI). |
80 | PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or |
80 | ADC is connected directly to HSI RC 16MHz oscillator. |
81 | enabled with HSI16 as clock source |
81 | Therefore, RCC PLL setting has no impact on ADC. |
82 | (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device |
82 | PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or |
83 | main clock source SYSCLK. |
83 | enabled with HSI16 as clock source |
84 | The only mandatory setting is ".HSIState = RCC_HSI_ON" |
84 | (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device |
85 | 85 | main clock source SYSCLK. |
|
86 | (+++) Example: |
86 | The only mandatory setting is ".HSIState = RCC_HSI_ON" |
87 | Into HAL_ADC_MspInit() (recommended code location) or with |
87 | |
88 | other device clock parameters configuration: |
88 | (+++) Example: |
89 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); |
89 | Into HAL_ADC_MspInit() (recommended code location) or with |
90 | 90 | other device clock parameters configuration: |
|
91 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
91 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); |
92 | (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); |
92 | |
93 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; |
93 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
94 | (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
94 | (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); |
95 | (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; |
95 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; |
96 | (+++) RCC_OscInitStructure.PLL.PLLSource = ... |
96 | (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
97 | (+++) RCC_OscInitStructure.PLL... |
97 | (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; |
98 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
98 | (+++) RCC_OscInitStructure.PLL.PLLSource = ... |
99 | 99 | (+++) RCC_OscInitStructure.PLL... |
|
100 | (++) ADC clock prescaler is configured at ADC level with |
100 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
101 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
101 | |
102 | 102 | (++) ADC clock prescaler is configured at ADC level with |
|
103 | (#) ADC pins configuration |
103 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
104 | (++) Enable the clock for the ADC GPIOs |
104 | |
105 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
105 | (#) ADC pins configuration |
106 | (++) Configure these ADC pins in analog mode |
106 | (++) Enable the clock for the ADC GPIOs |
107 | using function HAL_GPIO_Init() |
107 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
108 | 108 | (++) Configure these ADC pins in analog mode |
|
109 | (#) Optionally, in case of usage of ADC with interruptions: |
109 | using function HAL_GPIO_Init() |
110 | (++) Configure the NVIC for ADC |
110 | |
111 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
111 | (#) Optionally, in case of usage of ADC with interruptions: |
112 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
112 | (++) Configure the NVIC for ADC |
113 | into the function of corresponding ADC interruption vector |
113 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
114 | ADCx_IRQHandler(). |
114 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
115 | 115 | into the function of corresponding ADC interruption vector |
|
116 | (#) Optionally, in case of usage of DMA: |
116 | ADCx_IRQHandler(). |
117 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
117 | |
118 | using function HAL_DMA_Init(). |
118 | (#) Optionally, in case of usage of DMA: |
119 | (++) Configure the NVIC for DMA |
119 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
120 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
120 | using function HAL_DMA_Init(). |
121 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
121 | (++) Configure the NVIC for DMA |
122 | into the function of corresponding DMA interruption vector |
122 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
123 | DMAx_Channelx_IRQHandler(). |
123 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
124 | 124 | into the function of corresponding DMA interruption vector |
|
125 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
125 | DMAx_Channelx_IRQHandler(). |
126 | ========================================================================== |
126 | |
127 | [..] |
127 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
128 | 128 | ========================================================================== |
|
129 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
129 | [..] |
130 | and regular group parameters (conversion trigger, sequencer, ...) |
130 | |
131 | using function HAL_ADC_Init(). |
131 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
132 | 132 | and regular group parameters (conversion trigger, sequencer, ...) |
|
133 | (#) Configure the channels for regular group parameters (channel number, |
133 | using function HAL_ADC_Init(). |
134 | channel rank into sequencer, ..., into regular group) |
134 | |
135 | using function HAL_ADC_ConfigChannel(). |
135 | (#) Configure the channels for regular group parameters (channel number, |
136 | 136 | channel rank into sequencer, ..., into regular group) |
|
137 | (#) Optionally, configure the injected group parameters (conversion trigger, |
137 | using function HAL_ADC_ConfigChannel(). |
138 | sequencer, ..., of injected group) |
138 | |
139 | and the channels for injected group parameters (channel number, |
139 | (#) Optionally, configure the injected group parameters (conversion trigger, |
140 | channel rank into sequencer, ..., into injected group) |
140 | sequencer, ..., of injected group) |
141 | using function HAL_ADCEx_InjectedConfigChannel(). |
141 | and the channels for injected group parameters (channel number, |
142 | 142 | channel rank into sequencer, ..., into injected group) |
|
143 | (#) Optionally, configure the analog watchdog parameters (channels |
143 | using function HAL_ADCEx_InjectedConfigChannel(). |
144 | monitored, thresholds, ...) |
144 | |
145 | using function HAL_ADC_AnalogWDGConfig(). |
145 | (#) Optionally, configure the analog watchdog parameters (channels |
146 | 146 | monitored, thresholds, ...) |
|
147 | (#) Optionally, for devices with several ADC instances: configure the |
147 | using function HAL_ADC_AnalogWDGConfig(). |
148 | multimode parameters |
148 | |
149 | using function HAL_ADCEx_MultiModeConfigChannel(). |
149 | (#) Optionally, for devices with several ADC instances: configure the |
150 | 150 | multimode parameters |
|
151 | *** Execution of ADC conversions *** |
151 | using function HAL_ADCEx_MultiModeConfigChannel(). |
152 | ==================================== |
152 | |
153 | [..] |
153 | *** Execution of ADC conversions *** |
154 | 154 | ==================================== |
|
155 | (#) ADC driver can be used among three modes: polling, interruption, |
155 | [..] |
156 | transfer by DMA. |
156 | |
157 | 157 | (#) ADC driver can be used among three modes: polling, interruption, |
|
158 | (++) ADC conversion by polling: |
158 | transfer by DMA. |
159 | (+++) Activate the ADC peripheral and start conversions |
159 | |
160 | using function HAL_ADC_Start() |
160 | (++) ADC conversion by polling: |
161 | (+++) Wait for ADC conversion completion |
161 | (+++) Activate the ADC peripheral and start conversions |
162 | using function HAL_ADC_PollForConversion() |
162 | using function HAL_ADC_Start() |
163 | (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) |
163 | (+++) Wait for ADC conversion completion |
164 | (+++) Retrieve conversion results |
164 | using function HAL_ADC_PollForConversion() |
165 | using function HAL_ADC_GetValue() |
165 | (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) |
166 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
166 | (+++) Retrieve conversion results |
167 | (+++) Stop conversion and disable the ADC peripheral |
167 | using function HAL_ADC_GetValue() |
168 | using function HAL_ADC_Stop() |
168 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
169 | 169 | (+++) Stop conversion and disable the ADC peripheral |
|
170 | (++) ADC conversion by interruption: |
170 | using function HAL_ADC_Stop() |
171 | (+++) Activate the ADC peripheral and start conversions |
171 | |
172 | using function HAL_ADC_Start_IT() |
172 | (++) ADC conversion by interruption: |
173 | (+++) Wait for ADC conversion completion by call of function |
173 | (+++) Activate the ADC peripheral and start conversions |
174 | HAL_ADC_ConvCpltCallback() |
174 | using function HAL_ADC_Start_IT() |
175 | (this function must be implemented in user program) |
175 | (+++) Wait for ADC conversion completion by call of function |
176 | (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) |
176 | HAL_ADC_ConvCpltCallback() |
177 | (+++) Retrieve conversion results |
177 | (this function must be implemented in user program) |
178 | using function HAL_ADC_GetValue() |
178 | (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) |
179 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
179 | (+++) Retrieve conversion results |
180 | (+++) Stop conversion and disable the ADC peripheral |
180 | using function HAL_ADC_GetValue() |
181 | using function HAL_ADC_Stop_IT() |
181 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
182 | 182 | (+++) Stop conversion and disable the ADC peripheral |
|
183 | (++) ADC conversion with transfer by DMA: |
183 | using function HAL_ADC_Stop_IT() |
184 | (+++) Activate the ADC peripheral and start conversions |
184 | |
185 | using function HAL_ADC_Start_DMA() |
185 | (++) ADC conversion with transfer by DMA: |
186 | (+++) Wait for ADC conversion completion by call of function |
186 | (+++) Activate the ADC peripheral and start conversions |
187 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
187 | using function HAL_ADC_Start_DMA() |
188 | (these functions must be implemented in user program) |
188 | (+++) Wait for ADC conversion completion by call of function |
189 | (+++) Conversion results are automatically transferred by DMA into |
189 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
190 | destination variable address. |
190 | (these functions must be implemented in user program) |
191 | (+++) Stop conversion and disable the ADC peripheral |
191 | (+++) Conversion results are automatically transferred by DMA into |
192 | using function HAL_ADC_Stop_DMA() |
192 | destination variable address. |
193 | 193 | (+++) Stop conversion and disable the ADC peripheral |
|
194 | (++) For devices with several ADCs: ADC multimode conversion |
194 | using function HAL_ADC_Stop_DMA() |
195 | with transfer by DMA: |
195 | |
196 | (+++) Activate the ADC peripheral (slave) and start conversions |
196 | (++) For devices with several ADCs: ADC multimode conversion |
197 | using function HAL_ADC_Start() |
197 | with transfer by DMA: |
198 | (+++) Activate the ADC peripheral (master) and start conversions |
198 | (+++) Activate the ADC peripheral (slave) and start conversions |
199 | using function HAL_ADCEx_MultiModeStart_DMA() |
199 | using function HAL_ADC_Start() |
200 | (+++) Wait for ADC conversion completion by call of function |
200 | (+++) Activate the ADC peripheral (master) and start conversions |
201 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
201 | using function HAL_ADCEx_MultiModeStart_DMA() |
202 | (these functions must be implemented in user program) |
202 | (+++) Wait for ADC conversion completion by call of function |
203 | (+++) Conversion results are automatically transferred by DMA into |
203 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
204 | destination variable address. |
204 | (these functions must be implemented in user program) |
205 | (+++) Stop conversion and disable the ADC peripheral (master) |
205 | (+++) Conversion results are automatically transferred by DMA into |
206 | using function HAL_ADCEx_MultiModeStop_DMA() |
206 | destination variable address. |
207 | (+++) Stop conversion and disable the ADC peripheral (slave) |
207 | (+++) Stop conversion and disable the ADC peripheral (master) |
208 | using function HAL_ADC_Stop_IT() |
208 | using function HAL_ADCEx_MultiModeStop_DMA() |
209 | 209 | (+++) Stop conversion and disable the ADC peripheral (slave) |
|
210 | [..] |
210 | using function HAL_ADC_Stop_IT() |
211 | 211 | ||
212 | (@) Callback functions must be implemented in user program: |
212 | [..] |
213 | (+@) HAL_ADC_ErrorCallback() |
213 | |
214 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
214 | (@) Callback functions must be implemented in user program: |
215 | (+@) HAL_ADC_ConvCpltCallback() |
215 | (+@) HAL_ADC_ErrorCallback() |
216 | (+@) HAL_ADC_ConvHalfCpltCallback |
216 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
217 | (+@) HAL_ADCEx_InjectedConvCpltCallback() |
217 | (+@) HAL_ADC_ConvCpltCallback() |
218 | 218 | (+@) HAL_ADC_ConvHalfCpltCallback |
|
219 | *** Deinitialization of ADC *** |
219 | (+@) HAL_ADCEx_InjectedConvCpltCallback() |
220 | ============================================================ |
220 | |
221 | [..] |
221 | *** Deinitialization of ADC *** |
222 | 222 | ============================================================ |
|
223 | (#) Disable the ADC interface |
223 | [..] |
224 | (++) ADC clock can be hard reset and disabled at RCC top level. |
224 | |
225 | (++) Hard reset of ADC peripherals |
225 | (#) Disable the ADC interface |
226 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
226 | (++) ADC clock can be hard reset and disabled at RCC top level. |
227 | (++) ADC clock disable |
227 | (++) Hard reset of ADC peripherals |
228 | using the equivalent macro/functions as configuration step. |
228 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
229 | (+++) Example: |
229 | (++) ADC clock disable |
230 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
230 | using the equivalent macro/functions as configuration step. |
231 | other device clock parameters configuration: |
231 | (+++) Example: |
232 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
232 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
233 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
233 | other device clock parameters configuration: |
234 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) |
234 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
235 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
235 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
236 | 236 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) |
|
237 | (#) ADC pins configuration |
237 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
238 | (++) Disable the clock for the ADC GPIOs |
238 | |
239 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
239 | (#) ADC pins configuration |
240 | 240 | (++) Disable the clock for the ADC GPIOs |
|
241 | (#) Optionally, in case of usage of ADC with interruptions: |
241 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
242 | (++) Disable the NVIC for ADC |
242 | |
243 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
243 | (#) Optionally, in case of usage of ADC with interruptions: |
244 | 244 | (++) Disable the NVIC for ADC |
|
245 | (#) Optionally, in case of usage of DMA: |
245 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
246 | (++) Deinitialize the DMA |
246 | |
247 | using function HAL_DMA_Init(). |
247 | (#) Optionally, in case of usage of DMA: |
248 | (++) Disable the NVIC for DMA |
248 | (++) Deinitialize the DMA |
249 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
249 | using function HAL_DMA_Init(). |
250 | 250 | (++) Disable the NVIC for DMA |
|
251 | [..] |
251 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
252 | |
252 | |
253 | *** Callback registration *** |
253 | [..] |
254 | ============================================= |
254 | |
255 | [..] |
255 | *** Callback registration *** |
256 | 256 | ============================================= |
|
257 | The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, |
257 | [..] |
258 | allows the user to configure dynamically the driver callbacks. |
258 | |
259 | Use Functions @ref HAL_ADC_RegisterCallback() |
259 | The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, |
260 | to register an interrupt callback. |
260 | allows the user to configure dynamically the driver callbacks. |
261 | [..] |
261 | Use Functions HAL_ADC_RegisterCallback() |
262 | 262 | to register an interrupt callback. |
|
263 | Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: |
263 | [..] |
264 | (+) ConvCpltCallback : ADC conversion complete callback |
264 | |
265 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
265 | Function HAL_ADC_RegisterCallback() allows to register following callbacks: |
266 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
266 | (+) ConvCpltCallback : ADC conversion complete callback |
267 | (+) ErrorCallback : ADC error callback |
267 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
268 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
268 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
269 | (+) MspInitCallback : ADC Msp Init callback |
269 | (+) ErrorCallback : ADC error callback |
270 | (+) MspDeInitCallback : ADC Msp DeInit callback |
270 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
271 | This function takes as parameters the HAL peripheral handle, the Callback ID |
271 | (+) MspInitCallback : ADC Msp Init callback |
272 | and a pointer to the user callback function. |
272 | (+) MspDeInitCallback : ADC Msp DeInit callback |
273 | [..] |
273 | This function takes as parameters the HAL peripheral handle, the Callback ID |
274 | 274 | and a pointer to the user callback function. |
|
275 | Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default |
275 | [..] |
276 | weak function. |
276 | |
277 | [..] |
277 | Use function HAL_ADC_UnRegisterCallback to reset a callback to the default |
278 | 278 | weak function. |
|
279 | @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, |
279 | [..] |
280 | and the Callback ID. |
280 | |
281 | This function allows to reset following callbacks: |
281 | HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, |
282 | (+) ConvCpltCallback : ADC conversion complete callback |
282 | and the Callback ID. |
283 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
283 | This function allows to reset following callbacks: |
284 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
284 | (+) ConvCpltCallback : ADC conversion complete callback |
285 | (+) ErrorCallback : ADC error callback |
285 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
286 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
286 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
287 | (+) MspInitCallback : ADC Msp Init callback |
287 | (+) ErrorCallback : ADC error callback |
288 | (+) MspDeInitCallback : ADC Msp DeInit callback |
288 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
289 | [..] |
289 | (+) MspInitCallback : ADC Msp Init callback |
290 | 290 | (+) MspDeInitCallback : ADC Msp DeInit callback |
|
291 | By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET |
291 | [..] |
292 | all callbacks are set to the corresponding weak functions: |
292 | |
293 | examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). |
293 | By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET |
294 | Exception done for MspInit and MspDeInit functions that are |
294 | all callbacks are set to the corresponding weak functions: |
295 | reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when |
295 | examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). |
296 | these callbacks are null (not registered beforehand). |
296 | Exception done for MspInit and MspDeInit functions that are |
297 | [..] |
297 | reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when |
298 | 298 | these callbacks are null (not registered beforehand). |
|
299 | If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() |
299 | [..] |
300 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
300 | |
301 | [..] |
301 | If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() |
302 | 302 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
|
303 | Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. |
303 | [..] |
304 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
304 | |
305 | in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, |
305 | Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. |
306 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
306 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
307 | [..] |
307 | in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, |
308 | 308 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
|
309 | Then, the user first registers the MspInit/MspDeInit user callbacks |
309 | [..] |
310 | using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() |
310 | |
311 | or @ref HAL_ADC_Init() function. |
311 | Then, the user first registers the MspInit/MspDeInit user callbacks |
312 | [..] |
312 | using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() |
313 | 313 | or HAL_ADC_Init() function. |
|
314 | When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or |
314 | [..] |
315 | not defined, the callback registration feature is not available and all callbacks |
315 | |
316 | are set to the corresponding weak functions. |
316 | When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or |
317 | |
317 | not defined, the callback registration feature is not available and all callbacks |
318 | @endverbatim |
318 | are set to the corresponding weak functions. |
319 | ****************************************************************************** |
319 | |
320 | * @attention |
320 | @endverbatim |
321 | * |
321 | */ |
322 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
322 | |
323 | * All rights reserved.</center></h2> |
323 | /* Includes ------------------------------------------------------------------*/ |
324 | * |
324 | #include "stm32l1xx_hal.h" |
325 | * This software component is licensed by ST under BSD 3-Clause license, |
325 | |
326 | * the "License"; You may not use this file except in compliance with the |
326 | /** @addtogroup STM32L1xx_HAL_Driver |
327 | * License. You may obtain a copy of the License at: |
327 | * @{ |
328 | * opensource.org/licenses/BSD-3-Clause |
328 | */ |
329 | * |
329 | |
330 | ****************************************************************************** |
330 | /** @defgroup ADC ADC |
331 | */ |
331 | * @brief ADC HAL module driver |
332 | 332 | * @{ |
|
333 | /* Includes ------------------------------------------------------------------*/ |
333 | */ |
334 | #include "stm32l1xx_hal.h" |
334 | |
335 | 335 | #ifdef HAL_ADC_MODULE_ENABLED |
|
336 | /** @addtogroup STM32L1xx_HAL_Driver |
336 | |
337 | * @{ |
337 | /* Private typedef -----------------------------------------------------------*/ |
338 | */ |
338 | /* Private define ------------------------------------------------------------*/ |
339 | 339 | /** @defgroup ADC_Private_Constants ADC Private Constants |
|
340 | /** @defgroup ADC ADC |
340 | * @{ |
341 | * @brief ADC HAL module driver |
341 | */ |
342 | * @{ |
342 | |
343 | */ |
343 | /* Timeout values for ADC enable and disable settling time. */ |
344 | 344 | /* Values defined to be higher than worst cases: low clocks freq, */ |
|
345 | #ifdef HAL_ADC_MODULE_ENABLED |
345 | /* maximum prescaler. */ |
346 | 346 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
|
347 | /* Private typedef -----------------------------------------------------------*/ |
347 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
348 | /* Private define ------------------------------------------------------------*/ |
348 | /* Unit: ms */ |
349 | /** @defgroup ADC_Private_Constants ADC Private Constants |
349 | #define ADC_ENABLE_TIMEOUT (2U) |
350 | * @{ |
350 | #define ADC_DISABLE_TIMEOUT (2U) |
351 | */ |
351 | |
352 | 352 | /* Delay for ADC stabilization time. */ |
|
353 | /* Timeout values for ADC enable and disable settling time. */ |
353 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
354 | /* Values defined to be higher than worst cases: low clocks freq, */ |
354 | /* Unit: us */ |
355 | /* maximum prescaler. */ |
355 | #define ADC_STAB_DELAY_US (3U) |
356 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
356 | |
357 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
357 | /* Delay for temperature sensor stabilization time. */ |
358 | /* Unit: ms */ |
358 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
359 | #define ADC_ENABLE_TIMEOUT (2U) |
359 | /* Unit: us */ |
360 | #define ADC_DISABLE_TIMEOUT (2U) |
360 | #define ADC_TEMPSENSOR_DELAY_US (10U) |
361 | 361 | ||
362 | /* Delay for ADC stabilization time. */ |
362 | /** |
363 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
363 | * @} |
364 | /* Unit: us */ |
364 | */ |
365 | #define ADC_STAB_DELAY_US (3U) |
365 | |
366 | 366 | /* Private macro -------------------------------------------------------------*/ |
|
367 | /* Delay for temperature sensor stabilization time. */ |
367 | /* Private variables ---------------------------------------------------------*/ |
368 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
368 | /* Private function prototypes -----------------------------------------------*/ |
369 | /* Unit: us */ |
369 | /** @defgroup ADC_Private_Functions ADC Private Functions |
370 | #define ADC_TEMPSENSOR_DELAY_US (10U) |
370 | * @{ |
371 | 371 | */ |
|
372 | /** |
372 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
373 | * @} |
373 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
374 | */ |
374 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
375 | 375 | /** |
|
376 | /* Private macro -------------------------------------------------------------*/ |
376 | * @} |
377 | /* Private variables ---------------------------------------------------------*/ |
377 | */ |
378 | /* Private function prototypes -----------------------------------------------*/ |
378 | |
379 | /** @defgroup ADC_Private_Functions ADC Private Functions |
379 | /* Exported functions --------------------------------------------------------*/ |
380 | * @{ |
380 | |
381 | */ |
381 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
382 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
382 | * @{ |
383 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
383 | */ |
384 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
384 | |
385 | /** |
385 | /** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions |
386 | * @} |
386 | * @brief ADC Initialization and Configuration functions |
387 | */ |
387 | * |
388 | 388 | @verbatim |
|
389 | /* Exported functions --------------------------------------------------------*/ |
389 | =============================================================================== |
390 | 390 | ##### Initialization and de-initialization functions ##### |
|
391 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
391 | =============================================================================== |
392 | * @{ |
392 | [..] This section provides functions allowing to: |
393 | */ |
393 | (+) Initialize and configure the ADC. |
394 | 394 | (+) De-initialize the ADC. |
|
395 | /** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions |
395 | @endverbatim |
396 | * @brief ADC Initialization and Configuration functions |
396 | * @{ |
397 | * |
397 | */ |
398 | @verbatim |
398 | |
399 | =============================================================================== |
399 | /** |
400 | ##### Initialization and de-initialization functions ##### |
400 | * @brief Initializes the ADC peripheral and regular group according to |
401 | =============================================================================== |
401 | * parameters specified in structure "ADC_InitTypeDef". |
402 | [..] This section provides functions allowing to: |
402 | * @note As prerequisite, ADC clock must be configured at RCC top level |
403 | (+) Initialize and configure the ADC. |
403 | * (clock source APB2). |
404 | (+) De-initialize the ADC. |
404 | * See commented example code below that can be copied and uncommented |
405 | @endverbatim |
405 | * into HAL_ADC_MspInit(). |
406 | * @{ |
406 | * @note Possibility to update parameters on the fly: |
407 | */ |
407 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
408 | 408 | * coming from ADC state reset. Following calls to this function can |
|
409 | /** |
409 | * be used to reconfigure some parameters of ADC_InitTypeDef |
410 | * @brief Initializes the ADC peripheral and regular group according to |
410 | * structure on the fly, without modifying MSP configuration. If ADC |
411 | * parameters specified in structure "ADC_InitTypeDef". |
411 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
412 | * @note As prerequisite, ADC clock must be configured at RCC top level |
412 | * before HAL_ADC_Init(). |
413 | * (clock source APB2). |
413 | * The setting of these parameters is conditioned to ADC state. |
414 | * See commented example code below that can be copied and uncommented |
414 | * For parameters constraints, see comments of structure |
415 | * into HAL_ADC_MspInit(). |
415 | * "ADC_InitTypeDef". |
416 | * @note Possibility to update parameters on the fly: |
416 | * @note This function configures the ADC within 2 scopes: scope of entire |
417 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
417 | * ADC and scope of regular group. For parameters details, see comments |
418 | * coming from ADC state reset. Following calls to this function can |
418 | * of structure "ADC_InitTypeDef". |
419 | * be used to reconfigure some parameters of ADC_InitTypeDef |
419 | * @param hadc ADC handle |
420 | * structure on the fly, without modifying MSP configuration. If ADC |
420 | * @retval HAL status |
421 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
421 | */ |
422 | * before HAL_ADC_Init(). |
422 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
423 | * The setting of these parameters is conditioned to ADC state. |
423 | { |
424 | * For parameters constraints, see comments of structure |
424 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
425 | * "ADC_InitTypeDef". |
425 | uint32_t tmp_cr1 = 0; |
426 | * @note This function configures the ADC within 2 scopes: scope of entire |
426 | uint32_t tmp_cr2 = 0; |
427 | * ADC and scope of regular group. For parameters details, see comments |
427 | |
428 | * of structure "ADC_InitTypeDef". |
428 | /* Check ADC handle */ |
429 | * @param hadc ADC handle |
429 | if(hadc == NULL) |
430 | * @retval HAL status |
430 | { |
431 | */ |
431 | return HAL_ERROR; |
432 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
432 | } |
433 | { |
433 | |
434 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
434 | /* Check the parameters */ |
435 | uint32_t tmp_cr1 = 0; |
435 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
436 | uint32_t tmp_cr2 = 0; |
436 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
437 | 437 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
|
438 | /* Check ADC handle */ |
438 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
439 | if(hadc == NULL) |
439 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
440 | { |
440 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
441 | return HAL_ERROR; |
441 | assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait)); |
442 | } |
442 | assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff)); |
443 | 443 | assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank)); |
|
444 | /* Check the parameters */ |
444 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
445 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
445 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
446 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
446 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
447 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
447 | |
448 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
448 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
449 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
449 | { |
450 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
450 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
451 | assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait)); |
451 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
452 | assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff)); |
452 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
453 | assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank)); |
453 | { |
454 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
454 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
455 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
455 | } |
456 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
456 | } |
457 | 457 | ||
458 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
458 | if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
459 | { |
459 | { |
460 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
460 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
461 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
461 | } |
462 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
462 | |
463 | { |
463 | |
464 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
464 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
465 | } |
465 | /* at RCC top level. */ |
466 | } |
466 | /* Refer to header of this file for more details on clock enabling */ |
467 | 467 | /* procedure. */ |
|
468 | if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
468 | |
469 | { |
469 | /* Actions performed only if ADC is coming from state reset: */ |
470 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
470 | /* - Initialization of ADC MSP */ |
471 | } |
471 | if (hadc->State == HAL_ADC_STATE_RESET) |
472 | 472 | { |
|
473 | 473 | /* Initialize ADC error code */ |
|
474 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
474 | ADC_CLEAR_ERRORCODE(hadc); |
475 | /* at RCC top level. */ |
475 | |
476 | /* Refer to header of this file for more details on clock enabling */ |
476 | /* Allocate lock resource and initialize it */ |
477 | /* procedure. */ |
477 | hadc->Lock = HAL_UNLOCKED; |
478 | 478 | ||
479 | /* Actions performed only if ADC is coming from state reset: */ |
479 | /* Enable SYSCFG clock to control the routing Interface (RI) */ |
480 | /* - Initialization of ADC MSP */ |
480 | __HAL_RCC_SYSCFG_CLK_ENABLE(); |
481 | if (hadc->State == HAL_ADC_STATE_RESET) |
481 | |
482 | { |
482 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
483 | /* Initialize ADC error code */ |
483 | /* Init the ADC Callback settings */ |
484 | ADC_CLEAR_ERRORCODE(hadc); |
484 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ |
485 | 485 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ |
|
486 | /* Allocate lock resource and initialize it */ |
486 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ |
487 | hadc->Lock = HAL_UNLOCKED; |
487 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ |
488 | 488 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ |
|
489 | /* Enable SYSCFG clock to control the routing Interface (RI) */ |
489 | |
490 | __HAL_RCC_SYSCFG_CLK_ENABLE(); |
490 | if (hadc->MspInitCallback == NULL) |
491 | 491 | { |
|
492 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
492 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
493 | /* Init the ADC Callback settings */ |
493 | } |
494 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ |
494 | |
495 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ |
495 | /* Init the low level hardware */ |
496 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ |
496 | hadc->MspInitCallback(hadc); |
497 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ |
497 | #else |
498 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ |
498 | /* Init the low level hardware */ |
499 | 499 | HAL_ADC_MspInit(hadc); |
|
500 | if (hadc->MspInitCallback == NULL) |
500 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
501 | { |
501 | } |
502 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
502 | |
503 | } |
503 | /* Configuration of ADC parameters if previous preliminary actions are */ |
504 | 504 | /* correctly completed. */ |
|
505 | /* Init the low level hardware */ |
505 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
506 | hadc->MspInitCallback(hadc); |
506 | { |
507 | #else |
507 | /* Set ADC state */ |
508 | /* Init the low level hardware */ |
508 | ADC_STATE_CLR_SET(hadc->State, |
509 | HAL_ADC_MspInit(hadc); |
509 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
510 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
510 | HAL_ADC_STATE_BUSY_INTERNAL); |
511 | } |
511 | |
512 | 512 | /* Set ADC parameters */ |
|
513 | /* Configuration of ADC parameters if previous preliminary actions are */ |
513 | |
514 | /* correctly completed. */ |
514 | /* Configuration of common ADC clock: clock source HSI with selectable */ |
515 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
515 | /* prescaler */ |
516 | { |
516 | MODIFY_REG(ADC->CCR , |
517 | /* Set ADC state */ |
517 | ADC_CCR_ADCPRE , |
518 | ADC_STATE_CLR_SET(hadc->State, |
518 | hadc->Init.ClockPrescaler ); |
519 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
519 | |
520 | HAL_ADC_STATE_BUSY_INTERNAL); |
520 | /* Configuration of ADC: */ |
521 | 521 | /* - external trigger polarity */ |
|
522 | /* Set ADC parameters */ |
522 | /* - End of conversion selection */ |
523 | 523 | /* - DMA continuous request */ |
|
524 | /* Configuration of common ADC clock: clock source HSI with selectable */ |
524 | /* - Channels bank (Banks availability depends on devices categories) */ |
525 | /* prescaler */ |
525 | /* - continuous conversion mode */ |
526 | MODIFY_REG(ADC->CCR , |
526 | tmp_cr2 |= (hadc->Init.DataAlign | |
527 | ADC_CCR_ADCPRE , |
527 | hadc->Init.EOCSelection | |
528 | hadc->Init.ClockPrescaler ); |
528 | ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) | |
529 | 529 | hadc->Init.ChannelsBank | |
|
530 | /* Configuration of ADC: */ |
530 | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); |
531 | /* - external trigger polarity */ |
531 | |
532 | /* - End of conversion selection */ |
532 | /* Enable external trigger if trigger selection is different of software */ |
533 | /* - DMA continuous request */ |
533 | /* start. */ |
534 | /* - Channels bank (Banks availability depends on devices categories) */ |
534 | /* Note: This configuration keeps the hardware feature of parameter */ |
535 | /* - continuous conversion mode */ |
535 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
536 | tmp_cr2 |= (hadc->Init.DataAlign | |
536 | /* software start. */ |
537 | hadc->Init.EOCSelection | |
537 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
538 | ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) | |
538 | { |
539 | hadc->Init.ChannelsBank | |
539 | tmp_cr2 |= ( hadc->Init.ExternalTrigConv | |
540 | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); |
540 | hadc->Init.ExternalTrigConvEdge ); |
541 | 541 | } |
|
542 | /* Enable external trigger if trigger selection is different of software */ |
542 | |
543 | /* start. */ |
543 | /* Parameters update conditioned to ADC state: */ |
544 | /* Note: This configuration keeps the hardware feature of parameter */ |
544 | /* Parameters that can be updated only when ADC is disabled: */ |
545 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
545 | /* - delay selection (LowPowerAutoWait mode) */ |
546 | /* software start. */ |
546 | /* - resolution */ |
547 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
547 | /* - auto power off (LowPowerAutoPowerOff mode) */ |
548 | { |
548 | /* - scan mode */ |
549 | tmp_cr2 |= ( hadc->Init.ExternalTrigConv | |
549 | /* - discontinuous mode disable/enable */ |
550 | hadc->Init.ExternalTrigConvEdge ); |
550 | /* - discontinuous mode number of conversions */ |
551 | } |
551 | if ((ADC_IS_ENABLE(hadc) == RESET)) |
552 | 552 | { |
|
553 | /* Parameters update conditioned to ADC state: */ |
553 | tmp_cr2 |= hadc->Init.LowPowerAutoWait; |
554 | /* Parameters that can be updated only when ADC is disabled: */ |
554 | |
555 | /* - delay selection (LowPowerAutoWait mode) */ |
555 | tmp_cr1 |= (hadc->Init.Resolution | |
556 | /* - resolution */ |
556 | hadc->Init.LowPowerAutoPowerOff | |
557 | /* - auto power off (LowPowerAutoPowerOff mode) */ |
557 | ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) ); |
558 | /* - scan mode */ |
558 | |
559 | /* - discontinuous mode disable/enable */ |
559 | /* Enable discontinuous mode only if continuous mode is disabled */ |
560 | /* - discontinuous mode number of conversions */ |
560 | /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ |
561 | if ((ADC_IS_ENABLE(hadc) == RESET)) |
561 | /* discontinuous is set anyway, but has no effect on ADC HW. */ |
562 | { |
562 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
563 | tmp_cr2 |= hadc->Init.LowPowerAutoWait; |
563 | { |
564 | 564 | if (hadc->Init.ContinuousConvMode == DISABLE) |
|
565 | tmp_cr1 |= (hadc->Init.Resolution | |
565 | { |
566 | hadc->Init.LowPowerAutoPowerOff | |
566 | /* Enable the selected ADC regular discontinuous mode */ |
567 | ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) ); |
567 | /* Set the number of channels to be converted in discontinuous mode */ |
568 | 568 | SET_BIT(tmp_cr1, ADC_CR1_DISCEN | |
|
569 | /* Enable discontinuous mode only if continuous mode is disabled */ |
569 | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
570 | /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ |
570 | } |
571 | /* discontinuous is set anyway, but has no effect on ADC HW. */ |
571 | else |
572 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
572 | { |
573 | { |
573 | /* ADC regular group settings continuous and sequencer discontinuous*/ |
574 | if (hadc->Init.ContinuousConvMode == DISABLE) |
574 | /* cannot be enabled simultaneously. */ |
575 | { |
575 | |
576 | /* Enable the selected ADC regular discontinuous mode */ |
576 | /* Update ADC state machine to error */ |
577 | /* Set the number of channels to be converted in discontinuous mode */ |
577 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
578 | SET_BIT(tmp_cr1, ADC_CR1_DISCEN | |
578 | |
579 | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
579 | /* Set ADC error code to ADC IP internal error */ |
580 | } |
580 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
581 | else |
581 | } |
582 | { |
582 | } |
583 | /* ADC regular group settings continuous and sequencer discontinuous*/ |
583 | |
584 | /* cannot be enabled simultaneously. */ |
584 | /* Update ADC configuration register CR1 with previous settings */ |
585 | 585 | MODIFY_REG(hadc->Instance->CR1, |
|
586 | /* Update ADC state machine to error */ |
586 | ADC_CR1_RES | |
587 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
587 | ADC_CR1_PDI | |
588 | 588 | ADC_CR1_PDD | |
|
589 | /* Set ADC error code to ADC IP internal error */ |
589 | ADC_CR1_DISCNUM | |
590 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
590 | ADC_CR1_DISCEN | |
591 | } |
591 | ADC_CR1_SCAN , |
592 | } |
592 | tmp_cr1 ); |
593 | 593 | } |
|
594 | /* Update ADC configuration register CR1 with previous settings */ |
594 | |
595 | MODIFY_REG(hadc->Instance->CR1, |
595 | /* Update ADC configuration register CR2 with previous settings */ |
596 | ADC_CR1_RES | |
596 | MODIFY_REG(hadc->Instance->CR2 , |
597 | ADC_CR1_PDI | |
597 | ADC_CR2_MASK_ADCINIT() , |
598 | ADC_CR1_PDD | |
598 | tmp_cr2 ); |
599 | ADC_CR1_DISCNUM | |
599 | |
600 | ADC_CR1_DISCEN | |
600 | /* Configuration of regular group sequencer: */ |
601 | ADC_CR1_SCAN , |
601 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
602 | tmp_cr1 ); |
602 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
603 | } |
603 | /* Parameter "NbrOfConversion" is discarded. */ |
604 | 604 | /* Note: Scan mode is present by hardware on this device and, if */ |
|
605 | /* Update ADC configuration register CR2 with previous settings */ |
605 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
606 | MODIFY_REG(hadc->Instance->CR2 , |
606 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
607 | ADC_CR2_MASK_ADCINIT() , |
607 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
608 | tmp_cr2 ); |
608 | /* parameter "NbrOfConversion" */ |
609 | 609 | if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) |
|
610 | /* Configuration of regular group sequencer: */ |
610 | { |
611 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
611 | MODIFY_REG(hadc->Instance->SQR1 , |
612 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
612 | ADC_SQR1_L , |
613 | /* Parameter "NbrOfConversion" is discarded. */ |
613 | ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) ); |
614 | /* Note: Scan mode is present by hardware on this device and, if */ |
614 | } |
615 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
615 | else |
616 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
616 | { |
617 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
617 | MODIFY_REG(hadc->Instance->SQR1, |
618 | /* parameter "NbrOfConversion" */ |
618 | ADC_SQR1_L , |
619 | if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) |
619 | 0x00000000 ); |
620 | { |
620 | } |
621 | MODIFY_REG(hadc->Instance->SQR1 , |
621 | |
622 | ADC_SQR1_L , |
622 | /* Check back that ADC registers have effectively been configured to */ |
623 | ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) ); |
623 | /* ensure of no potential problem of ADC core IP clocking. */ |
624 | } |
624 | /* Check through register CR2 (excluding execution control bits ADON, */ |
625 | else |
625 | /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */ |
626 | { |
626 | if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON | |
627 | MODIFY_REG(hadc->Instance->SQR1, |
627 | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
628 | ADC_SQR1_L , |
628 | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL )) |
629 | 0x00000000 ); |
629 | == tmp_cr2) |
630 | } |
630 | { |
631 | 631 | /* Set ADC error code to none */ |
|
632 | /* Check back that ADC registers have effectively been configured to */ |
632 | ADC_CLEAR_ERRORCODE(hadc); |
633 | /* ensure of no potential problem of ADC core IP clocking. */ |
633 | |
634 | /* Check through register CR2 (excluding execution control bits ADON, */ |
634 | /* Set the ADC state */ |
635 | /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */ |
635 | ADC_STATE_CLR_SET(hadc->State, |
636 | if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON | |
636 | HAL_ADC_STATE_BUSY_INTERNAL, |
637 | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
637 | HAL_ADC_STATE_READY); |
638 | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL )) |
638 | } |
639 | == tmp_cr2) |
639 | else |
640 | { |
640 | { |
641 | /* Set ADC error code to none */ |
641 | /* Update ADC state machine to error */ |
642 | ADC_CLEAR_ERRORCODE(hadc); |
642 | ADC_STATE_CLR_SET(hadc->State, |
643 | 643 | HAL_ADC_STATE_BUSY_INTERNAL, |
|
644 | /* Set the ADC state */ |
644 | HAL_ADC_STATE_ERROR_INTERNAL); |
645 | ADC_STATE_CLR_SET(hadc->State, |
645 | |
646 | HAL_ADC_STATE_BUSY_INTERNAL, |
646 | /* Set ADC error code to ADC IP internal error */ |
647 | HAL_ADC_STATE_READY); |
647 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
648 | } |
648 | |
649 | else |
649 | tmp_hal_status = HAL_ERROR; |
650 | { |
650 | } |
651 | /* Update ADC state machine to error */ |
651 | |
652 | ADC_STATE_CLR_SET(hadc->State, |
652 | } |
653 | HAL_ADC_STATE_BUSY_INTERNAL, |
653 | else |
654 | HAL_ADC_STATE_ERROR_INTERNAL); |
654 | { |
655 | 655 | tmp_hal_status = HAL_ERROR; |
|
656 | /* Set ADC error code to ADC IP internal error */ |
656 | } |
657 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
657 | |
658 | 658 | /* Return function status */ |
|
659 | tmp_hal_status = HAL_ERROR; |
659 | return tmp_hal_status; |
660 | } |
660 | } |
661 | 661 | ||
662 | } |
662 | /** |
663 | else |
663 | * @brief Deinitialize the ADC peripheral registers to its default reset values. |
664 | { |
664 | * @note To not impact other ADCs, reset of common ADC registers have been |
665 | tmp_hal_status = HAL_ERROR; |
665 | * left commented below. |
666 | } |
666 | * If needed, the example code can be copied and uncommented into |
667 | 667 | * function HAL_ADC_MspDeInit(). |
|
668 | /* Return function status */ |
668 | * @param hadc ADC handle |
669 | return tmp_hal_status; |
669 | * @retval HAL status |
670 | } |
670 | */ |
671 | 671 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
|
672 | /** |
672 | { |
673 | * @brief Deinitialize the ADC peripheral registers to its default reset values. |
673 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
674 | * @note To not impact other ADCs, reset of common ADC registers have been |
674 | |
675 | * left commented below. |
675 | /* Check ADC handle */ |
676 | * If needed, the example code can be copied and uncommented into |
676 | if(hadc == NULL) |
677 | * function HAL_ADC_MspDeInit(). |
677 | { |
678 | * @param hadc ADC handle |
678 | return HAL_ERROR; |
679 | * @retval HAL status |
679 | } |
680 | */ |
680 | |
681 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
681 | /* Check the parameters */ |
682 | { |
682 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
683 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
683 | |
684 | 684 | /* Set ADC state */ |
|
685 | /* Check ADC handle */ |
685 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
686 | if(hadc == NULL) |
686 | |
687 | { |
687 | /* Stop potential conversion on going, on regular and injected groups */ |
688 | return HAL_ERROR; |
688 | /* Disable ADC peripheral */ |
689 | } |
689 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
690 | 690 | ||
691 | /* Check the parameters */ |
691 | |
692 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
692 | /* Configuration of ADC parameters if previous preliminary actions are */ |
693 | 693 | /* correctly completed. */ |
|
694 | /* Set ADC state */ |
694 | if (tmp_hal_status == HAL_OK) |
695 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
695 | { |
696 | 696 | /* ========== Reset ADC registers ========== */ |
|
697 | /* Stop potential conversion on going, on regular and injected groups */ |
697 | /* Reset register SR */ |
698 | /* Disable ADC peripheral */ |
698 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
699 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
699 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
700 | 700 | ||
701 | 701 | /* Reset register CR1 */ |
|
702 | /* Configuration of ADC parameters if previous preliminary actions are */ |
702 | CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | |
703 | /* correctly completed. */ |
703 | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD | |
704 | if (tmp_hal_status == HAL_OK) |
704 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | |
705 | { |
705 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | |
706 | /* ========== Reset ADC registers ========== */ |
706 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | |
707 | /* Reset register SR */ |
707 | ADC_CR1_AWDCH )); |
708 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
708 | |
709 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
709 | /* Reset register CR2 */ |
710 | 710 | ADC_CR2_CLEAR(hadc); |
|
711 | /* Reset register CR1 */ |
711 | |
712 | CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | |
712 | /* Reset register SMPR0 */ |
713 | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD | |
713 | ADC_SMPR0_CLEAR(hadc); |
714 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | |
714 | |
715 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | |
715 | /* Reset register SMPR1 */ |
716 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | |
716 | ADC_SMPR1_CLEAR(hadc); |
717 | ADC_CR1_AWDCH )); |
717 | |
718 | 718 | /* Reset register SMPR2 */ |
|
719 | /* Reset register CR2 */ |
719 | CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | |
720 | ADC_CR2_CLEAR(hadc); |
720 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | |
721 | 721 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | |
|
722 | /* Reset register SMPR0 */ |
722 | ADC_SMPR2_SMP10 )); |
723 | ADC_SMPR0_CLEAR(hadc); |
723 | |
724 | 724 | /* Reset register SMPR3 */ |
|
725 | /* Reset register SMPR1 */ |
725 | CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | |
726 | ADC_SMPR1_CLEAR(hadc); |
726 | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | |
727 | 727 | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 | |
|
728 | /* Reset register SMPR2 */ |
728 | ADC_SMPR3_SMP0 )); |
729 | CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | |
729 | |
730 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | |
730 | /* Reset register JOFR1 */ |
731 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | |
731 | CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); |
732 | ADC_SMPR2_SMP10 )); |
732 | /* Reset register JOFR2 */ |
733 | 733 | CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); |
|
734 | /* Reset register SMPR3 */ |
734 | /* Reset register JOFR3 */ |
735 | CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | |
735 | CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); |
736 | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | |
736 | /* Reset register JOFR4 */ |
737 | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 | |
737 | CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); |
738 | ADC_SMPR3_SMP0 )); |
738 | |
739 | 739 | /* Reset register HTR */ |
|
740 | /* Reset register JOFR1 */ |
740 | CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); |
741 | CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); |
741 | /* Reset register LTR */ |
742 | /* Reset register JOFR2 */ |
742 | CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); |
743 | CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); |
743 | |
744 | /* Reset register JOFR3 */ |
744 | /* Reset register SQR1 */ |
745 | CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); |
745 | CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX)); |
746 | /* Reset register JOFR4 */ |
746 | |
747 | CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); |
747 | /* Reset register SQR2 */ |
748 | 748 | CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | |
|
749 | /* Reset register HTR */ |
749 | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 )); |
750 | CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); |
750 | |
751 | /* Reset register LTR */ |
751 | /* Reset register SQR3 */ |
752 | CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); |
752 | CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | |
753 | 753 | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 )); |
|
754 | /* Reset register SQR1 */ |
754 | |
755 | CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX)); |
755 | /* Reset register SQR4 */ |
756 | 756 | CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | |
|
757 | /* Reset register SQR2 */ |
757 | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 )); |
758 | CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | |
758 | |
759 | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 )); |
759 | /* Reset register SQR5 */ |
760 | 760 | CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | |
|
761 | /* Reset register SQR3 */ |
761 | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); |
762 | CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | |
762 | |
763 | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 )); |
763 | |
764 | 764 | /* Reset register JSQR */ |
|
765 | /* Reset register SQR4 */ |
765 | CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | |
766 | CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | |
766 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
767 | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 )); |
767 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); |
768 | 768 | ||
769 | /* Reset register SQR5 */ |
769 | /* Reset register DR */ |
770 | CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | |
770 | /* bits in access mode read only, no direct reset applicable*/ |
771 | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); |
771 | |
772 | 772 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
|
773 | 773 | /* bits in access mode read only, no direct reset applicable*/ |
|
774 | /* Reset register JSQR */ |
774 | |
775 | CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | |
775 | /* Reset register CCR */ |
776 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
776 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
777 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); |
777 | |
778 | 778 | /* ========== Hard reset ADC peripheral ========== */ |
|
779 | /* Reset register DR */ |
779 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
780 | /* bits in access mode read only, no direct reset applicable*/ |
780 | /* forced to a similar state after device power-on. */ |
781 | 781 | /* If needed, copy-paste and uncomment the following reset code into */ |
|
782 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
782 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
783 | /* bits in access mode read only, no direct reset applicable*/ |
783 | /* */ |
784 | 784 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
|
785 | /* Reset register CCR */ |
785 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
786 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
786 | |
787 | 787 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|
788 | /* ========== Hard reset ADC peripheral ========== */ |
788 | if (hadc->MspDeInitCallback == NULL) |
789 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
789 | { |
790 | /* forced to a similar state after device power-on. */ |
790 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
791 | /* If needed, copy-paste and uncomment the following reset code into */ |
791 | } |
792 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
792 | |
793 | /* */ |
793 | /* DeInit the low level hardware */ |
794 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
794 | hadc->MspDeInitCallback(hadc); |
795 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
795 | #else |
796 | 796 | /* DeInit the low level hardware */ |
|
797 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
797 | HAL_ADC_MspDeInit(hadc); |
798 | if (hadc->MspDeInitCallback == NULL) |
798 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
799 | { |
799 | |
800 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
800 | /* Set ADC error code to none */ |
801 | } |
801 | ADC_CLEAR_ERRORCODE(hadc); |
802 | 802 | ||
803 | /* DeInit the low level hardware */ |
803 | /* Set ADC state */ |
804 | hadc->MspDeInitCallback(hadc); |
804 | hadc->State = HAL_ADC_STATE_RESET; |
805 | #else |
805 | |
806 | /* DeInit the low level hardware */ |
806 | } |
807 | HAL_ADC_MspDeInit(hadc); |
807 | |
808 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
808 | /* Process unlocked */ |
809 | 809 | __HAL_UNLOCK(hadc); |
|
810 | /* Set ADC error code to none */ |
810 | |
811 | ADC_CLEAR_ERRORCODE(hadc); |
811 | /* Return function status */ |
812 | 812 | return tmp_hal_status; |
|
813 | /* Set ADC state */ |
813 | } |
814 | hadc->State = HAL_ADC_STATE_RESET; |
814 | |
815 | 815 | /** |
|
816 | } |
816 | * @brief Initializes the ADC MSP. |
817 | 817 | * @param hadc ADC handle |
|
818 | /* Process unlocked */ |
818 | * @retval None |
819 | __HAL_UNLOCK(hadc); |
819 | */ |
820 | 820 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
|
821 | /* Return function status */ |
821 | { |
822 | return tmp_hal_status; |
822 | /* Prevent unused argument(s) compilation warning */ |
823 | } |
823 | UNUSED(hadc); |
824 | 824 | ||
825 | /** |
825 | /* NOTE : This function should not be modified. When the callback is needed, |
826 | * @brief Initializes the ADC MSP. |
826 | function HAL_ADC_MspInit must be implemented in the user file. |
827 | * @param hadc ADC handle |
827 | */ |
828 | * @retval None |
828 | } |
829 | */ |
829 | |
830 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
830 | /** |
831 | { |
831 | * @brief DeInitializes the ADC MSP. |
832 | /* Prevent unused argument(s) compilation warning */ |
832 | * @param hadc ADC handle |
833 | UNUSED(hadc); |
833 | * @retval None |
834 | 834 | */ |
|
835 | /* NOTE : This function should not be modified. When the callback is needed, |
835 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
836 | function HAL_ADC_MspInit must be implemented in the user file. |
836 | { |
837 | */ |
837 | /* Prevent unused argument(s) compilation warning */ |
838 | } |
838 | UNUSED(hadc); |
839 | 839 | ||
840 | /** |
840 | /* NOTE : This function should not be modified. When the callback is needed, |
841 | * @brief DeInitializes the ADC MSP. |
841 | function HAL_ADC_MspDeInit must be implemented in the user file. |
842 | * @param hadc ADC handle |
842 | */ |
843 | * @retval None |
843 | } |
844 | */ |
844 | |
845 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
845 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
846 | { |
846 | /** |
847 | /* Prevent unused argument(s) compilation warning */ |
847 | * @brief Register a User ADC Callback |
848 | UNUSED(hadc); |
848 | * To be used instead of the weak predefined callback |
849 | 849 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
|
850 | /* NOTE : This function should not be modified. When the callback is needed, |
850 | * the configuration information for the specified ADC. |
851 | function HAL_ADC_MspDeInit must be implemented in the user file. |
851 | * @param CallbackID ID of the callback to be registered |
852 | */ |
852 | * This parameter can be one of the following values: |
853 | } |
853 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
854 | 854 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
|
855 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
855 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
856 | /** |
856 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
857 | * @brief Register a User ADC Callback |
857 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
858 | * To be used instead of the weak predefined callback |
858 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
859 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
859 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
860 | * the configuration information for the specified ADC. |
860 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
861 | * @param CallbackID ID of the callback to be registered |
861 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
862 | * This parameter can be one of the following values: |
862 | * @param pCallback pointer to the Callback function |
863 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
863 | * @retval HAL status |
864 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
864 | */ |
865 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
865 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) |
866 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
866 | { |
867 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
867 | HAL_StatusTypeDef status = HAL_OK; |
868 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
868 | |
869 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
869 | if (pCallback == NULL) |
870 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
870 | { |
871 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
871 | /* Update the error code */ |
872 | * @param pCallback pointer to the Callback function |
872 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
873 | * @retval HAL status |
873 | |
874 | */ |
874 | return HAL_ERROR; |
875 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) |
875 | } |
876 | { |
876 | |
877 | HAL_StatusTypeDef status = HAL_OK; |
877 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
878 | 878 | { |
|
879 | if (pCallback == NULL) |
879 | switch (CallbackID) |
880 | { |
880 | { |
881 | /* Update the error code */ |
881 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
882 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
882 | hadc->ConvCpltCallback = pCallback; |
883 | 883 | break; |
|
884 | return HAL_ERROR; |
884 | |
885 | } |
885 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
886 | 886 | hadc->ConvHalfCpltCallback = pCallback; |
|
887 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
887 | break; |
888 | { |
888 | |
889 | switch (CallbackID) |
889 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
890 | { |
890 | hadc->LevelOutOfWindowCallback = pCallback; |
891 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
891 | break; |
892 | hadc->ConvCpltCallback = pCallback; |
892 | |
893 | break; |
893 | case HAL_ADC_ERROR_CB_ID : |
894 | 894 | hadc->ErrorCallback = pCallback; |
|
895 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
895 | break; |
896 | hadc->ConvHalfCpltCallback = pCallback; |
896 | |
897 | break; |
897 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
898 | 898 | hadc->InjectedConvCpltCallback = pCallback; |
|
899 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
899 | break; |
900 | hadc->LevelOutOfWindowCallback = pCallback; |
900 | |
901 | break; |
901 | case HAL_ADC_MSPINIT_CB_ID : |
902 | 902 | hadc->MspInitCallback = pCallback; |
|
903 | case HAL_ADC_ERROR_CB_ID : |
903 | break; |
904 | hadc->ErrorCallback = pCallback; |
904 | |
905 | break; |
905 | case HAL_ADC_MSPDEINIT_CB_ID : |
906 | 906 | hadc->MspDeInitCallback = pCallback; |
|
907 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
907 | break; |
908 | hadc->InjectedConvCpltCallback = pCallback; |
908 | |
909 | break; |
909 | default : |
910 | 910 | /* Update the error code */ |
|
911 | case HAL_ADC_MSPINIT_CB_ID : |
911 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
912 | hadc->MspInitCallback = pCallback; |
912 | |
913 | break; |
913 | /* Return error status */ |
914 | 914 | status = HAL_ERROR; |
|
915 | case HAL_ADC_MSPDEINIT_CB_ID : |
915 | break; |
916 | hadc->MspDeInitCallback = pCallback; |
916 | } |
917 | break; |
917 | } |
918 | 918 | else if (HAL_ADC_STATE_RESET == hadc->State) |
|
919 | default : |
919 | { |
920 | /* Update the error code */ |
920 | switch (CallbackID) |
921 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
921 | { |
922 | 922 | case HAL_ADC_MSPINIT_CB_ID : |
|
923 | /* Return error status */ |
923 | hadc->MspInitCallback = pCallback; |
924 | status = HAL_ERROR; |
924 | break; |
925 | break; |
925 | |
926 | } |
926 | case HAL_ADC_MSPDEINIT_CB_ID : |
927 | } |
927 | hadc->MspDeInitCallback = pCallback; |
928 | else if (HAL_ADC_STATE_RESET == hadc->State) |
928 | break; |
929 | { |
929 | |
930 | switch (CallbackID) |
930 | default : |
931 | { |
931 | /* Update the error code */ |
932 | case HAL_ADC_MSPINIT_CB_ID : |
932 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
933 | hadc->MspInitCallback = pCallback; |
933 | |
934 | break; |
934 | /* Return error status */ |
935 | 935 | status = HAL_ERROR; |
|
936 | case HAL_ADC_MSPDEINIT_CB_ID : |
936 | break; |
937 | hadc->MspDeInitCallback = pCallback; |
937 | } |
938 | break; |
938 | } |
939 | 939 | else |
|
940 | default : |
940 | { |
941 | /* Update the error code */ |
941 | /* Update the error code */ |
942 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
942 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
943 | 943 | ||
944 | /* Return error status */ |
944 | /* Return error status */ |
945 | status = HAL_ERROR; |
945 | status = HAL_ERROR; |
946 | break; |
946 | } |
947 | } |
947 | |
948 | } |
948 | return status; |
949 | else |
949 | } |
950 | { |
950 | |
951 | /* Update the error code */ |
951 | /** |
952 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
952 | * @brief Unregister a ADC Callback |
953 | 953 | * ADC callback is redirected to the weak predefined callback |
|
954 | /* Return error status */ |
954 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
955 | status = HAL_ERROR; |
955 | * the configuration information for the specified ADC. |
956 | } |
956 | * @param CallbackID ID of the callback to be unregistered |
957 | 957 | * This parameter can be one of the following values: |
|
958 | return status; |
958 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
959 | } |
959 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
960 | 960 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
|
961 | /** |
961 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
962 | * @brief Unregister a ADC Callback |
962 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
963 | * ADC callback is redirected to the weak predefined callback |
963 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
964 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
964 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
965 | * the configuration information for the specified ADC. |
965 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
966 | * @param CallbackID ID of the callback to be unregistered |
966 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
967 | * This parameter can be one of the following values: |
967 | * @retval HAL status |
968 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
968 | */ |
969 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
969 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) |
970 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
970 | { |
971 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
971 | HAL_StatusTypeDef status = HAL_OK; |
972 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
972 | |
973 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
973 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
974 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
974 | { |
975 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
975 | switch (CallbackID) |
976 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
976 | { |
977 | * @retval HAL status |
977 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
978 | */ |
978 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; |
979 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) |
979 | break; |
980 | { |
980 | |
981 | HAL_StatusTypeDef status = HAL_OK; |
981 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
982 | 982 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; |
|
983 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
983 | break; |
984 | { |
984 | |
985 | switch (CallbackID) |
985 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
986 | { |
986 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; |
987 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
987 | break; |
988 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; |
988 | |
989 | break; |
989 | case HAL_ADC_ERROR_CB_ID : |
990 | 990 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; |
|
991 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
991 | break; |
992 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; |
992 | |
993 | break; |
993 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
994 | 994 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; |
|
995 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
995 | break; |
996 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; |
996 | |
997 | break; |
997 | case HAL_ADC_MSPINIT_CB_ID : |
998 | 998 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
|
999 | case HAL_ADC_ERROR_CB_ID : |
999 | break; |
1000 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; |
1000 | |
1001 | break; |
1001 | case HAL_ADC_MSPDEINIT_CB_ID : |
1002 | 1002 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
|
1003 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
1003 | break; |
1004 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; |
1004 | |
1005 | break; |
1005 | default : |
1006 | 1006 | /* Update the error code */ |
|
1007 | case HAL_ADC_MSPINIT_CB_ID : |
1007 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
1008 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
1008 | |
1009 | break; |
1009 | /* Return error status */ |
1010 | 1010 | status = HAL_ERROR; |
|
1011 | case HAL_ADC_MSPDEINIT_CB_ID : |
1011 | break; |
1012 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
1012 | } |
1013 | break; |
1013 | } |
1014 | 1014 | else if (HAL_ADC_STATE_RESET == hadc->State) |
|
1015 | default : |
1015 | { |
1016 | /* Update the error code */ |
1016 | switch (CallbackID) |
1017 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
1017 | { |
1018 | 1018 | case HAL_ADC_MSPINIT_CB_ID : |
|
1019 | /* Return error status */ |
1019 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
1020 | status = HAL_ERROR; |
1020 | break; |
1021 | break; |
1021 | |
1022 | } |
1022 | case HAL_ADC_MSPDEINIT_CB_ID : |
1023 | } |
1023 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
1024 | else if (HAL_ADC_STATE_RESET == hadc->State) |
1024 | break; |
1025 | { |
1025 | |
1026 | switch (CallbackID) |
1026 | default : |
1027 | { |
1027 | /* Update the error code */ |
1028 | case HAL_ADC_MSPINIT_CB_ID : |
1028 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
1029 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
1029 | |
1030 | break; |
1030 | /* Return error status */ |
1031 | 1031 | status = HAL_ERROR; |
|
1032 | case HAL_ADC_MSPDEINIT_CB_ID : |
1032 | break; |
1033 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
1033 | } |
1034 | break; |
1034 | } |
1035 | 1035 | else |
|
1036 | default : |
1036 | { |
1037 | /* Update the error code */ |
1037 | /* Update the error code */ |
1038 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
1038 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
1039 | 1039 | ||
1040 | /* Return error status */ |
1040 | /* Return error status */ |
1041 | status = HAL_ERROR; |
1041 | status = HAL_ERROR; |
1042 | break; |
1042 | } |
1043 | } |
1043 | |
1044 | } |
1044 | return status; |
1045 | else |
1045 | } |
1046 | { |
1046 | |
1047 | /* Update the error code */ |
1047 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1048 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
1048 | |
1049 | 1049 | /** |
|
1050 | /* Return error status */ |
1050 | * @} |
1051 | status = HAL_ERROR; |
1051 | */ |
1052 | } |
1052 | |
1053 | 1053 | /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions |
|
1054 | return status; |
1054 | * @brief ADC IO operation functions |
1055 | } |
1055 | * |
1056 | 1056 | @verbatim |
|
1057 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1057 | =============================================================================== |
1058 | 1058 | ##### IO operation functions ##### |
|
1059 | /** |
1059 | =============================================================================== |
1060 | * @} |
1060 | [..] This section provides functions allowing to: |
1061 | */ |
1061 | (+) Start conversion of regular group. |
1062 | 1062 | (+) Stop conversion of regular group. |
|
1063 | /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions |
1063 | (+) Poll for conversion complete on regular group. |
1064 | * @brief ADC IO operation functions |
1064 | (+) Poll for conversion event. |
1065 | * |
1065 | (+) Get result of regular channel conversion. |
1066 | @verbatim |
1066 | (+) Start conversion of regular group and enable interruptions. |
1067 | =============================================================================== |
1067 | (+) Stop conversion of regular group and disable interruptions. |
1068 | ##### IO operation functions ##### |
1068 | (+) Handle ADC interrupt request |
1069 | =============================================================================== |
1069 | (+) Start conversion of regular group and enable DMA transfer. |
1070 | [..] This section provides functions allowing to: |
1070 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
1071 | (+) Start conversion of regular group. |
1071 | @endverbatim |
1072 | (+) Stop conversion of regular group. |
1072 | * @{ |
1073 | (+) Poll for conversion complete on regular group. |
1073 | */ |
1074 | (+) Poll for conversion event. |
1074 | |
1075 | (+) Get result of regular channel conversion. |
1075 | /** |
1076 | (+) Start conversion of regular group and enable interruptions. |
1076 | * @brief Enables ADC, starts conversion of regular group. |
1077 | (+) Stop conversion of regular group and disable interruptions. |
1077 | * Interruptions enabled in this function: None. |
1078 | (+) Handle ADC interrupt request |
1078 | * @param hadc ADC handle |
1079 | (+) Start conversion of regular group and enable DMA transfer. |
1079 | * @retval HAL status |
1080 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
1080 | */ |
1081 | @endverbatim |
1081 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
1082 | * @{ |
1082 | { |
1083 | */ |
1083 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1084 | 1084 | ||
1085 | /** |
1085 | /* Check the parameters */ |
1086 | * @brief Enables ADC, starts conversion of regular group. |
1086 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1087 | * Interruptions enabled in this function: None. |
1087 | |
1088 | * @param hadc ADC handle |
1088 | /* Process locked */ |
1089 | * @retval HAL status |
1089 | __HAL_LOCK(hadc); |
1090 | */ |
1090 | |
1091 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
1091 | /* Enable the ADC peripheral */ |
1092 | { |
1092 | tmp_hal_status = ADC_Enable(hadc); |
1093 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1093 | |
1094 | 1094 | /* Start conversion if ADC is effectively enabled */ |
|
1095 | /* Check the parameters */ |
1095 | if (tmp_hal_status == HAL_OK) |
1096 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1096 | { |
1097 | 1097 | /* Set ADC state */ |
|
1098 | /* Process locked */ |
1098 | /* - Clear state bitfield related to regular group conversion results */ |
1099 | __HAL_LOCK(hadc); |
1099 | /* - Set state bitfield related to regular group operation */ |
1100 | 1100 | ADC_STATE_CLR_SET(hadc->State, |
|
1101 | /* Enable the ADC peripheral */ |
1101 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
1102 | tmp_hal_status = ADC_Enable(hadc); |
1102 | HAL_ADC_STATE_REG_BUSY); |
1103 | 1103 | ||
1104 | /* Start conversion if ADC is effectively enabled */ |
1104 | /* If conversions on group regular are also triggering group injected, */ |
1105 | if (tmp_hal_status == HAL_OK) |
1105 | /* update ADC state. */ |
1106 | { |
1106 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
1107 | /* Set ADC state */ |
1107 | { |
1108 | /* - Clear state bitfield related to regular group conversion results */ |
1108 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
1109 | /* - Set state bitfield related to regular group operation */ |
1109 | } |
1110 | ADC_STATE_CLR_SET(hadc->State, |
1110 | |
1111 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
1111 | /* State machine update: Check if an injected conversion is ongoing */ |
1112 | HAL_ADC_STATE_REG_BUSY); |
1112 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1113 | 1113 | { |
|
1114 | /* If conversions on group regular are also triggering group injected, */ |
1114 | /* Reset ADC error code fields related to conversions on group regular */ |
1115 | /* update ADC state. */ |
1115 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
1116 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
1116 | } |
1117 | { |
1117 | else |
1118 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
1118 | { |
1119 | } |
1119 | /* Reset ADC all error code fields */ |
1120 | 1120 | ADC_CLEAR_ERRORCODE(hadc); |
|
1121 | /* State machine update: Check if an injected conversion is ongoing */ |
1121 | } |
1122 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1122 | |
1123 | { |
1123 | /* Process unlocked */ |
1124 | /* Reset ADC error code fields related to conversions on group regular */ |
1124 | /* Unlock before starting ADC conversions: in case of potential */ |
1125 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
1125 | /* interruption, to let the process to ADC IRQ Handler. */ |
1126 | } |
1126 | __HAL_UNLOCK(hadc); |
1127 | else |
1127 | |
1128 | { |
1128 | /* Clear regular group conversion flag and overrun flag */ |
1129 | /* Reset ADC all error code fields */ |
1129 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
1130 | ADC_CLEAR_ERRORCODE(hadc); |
1130 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
1131 | } |
1131 | |
1132 | 1132 | /* Enable conversion of regular group. */ |
|
1133 | /* Process unlocked */ |
1133 | /* If software start has been selected, conversion starts immediately. */ |
1134 | /* Unlock before starting ADC conversions: in case of potential */ |
1134 | /* If external trigger has been selected, conversion will start at next */ |
1135 | /* interruption, to let the process to ADC IRQ Handler. */ |
1135 | /* trigger event. */ |
1136 | __HAL_UNLOCK(hadc); |
1136 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
1137 | 1137 | { |
|
1138 | /* Clear regular group conversion flag and overrun flag */ |
1138 | /* Start ADC conversion on regular group */ |
1139 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
1139 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
1140 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
1140 | } |
1141 | 1141 | } |
|
1142 | /* Enable conversion of regular group. */ |
1142 | |
1143 | /* If software start has been selected, conversion starts immediately. */ |
1143 | /* Return function status */ |
1144 | /* If external trigger has been selected, conversion will start at next */ |
1144 | return tmp_hal_status; |
1145 | /* trigger event. */ |
1145 | } |
1146 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
1146 | |
1147 | { |
1147 | /** |
1148 | /* Start ADC conversion on regular group */ |
1148 | * @brief Stop ADC conversion of regular group (and injected channels in |
1149 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
1149 | * case of auto_injection mode), disable ADC peripheral. |
1150 | } |
1150 | * @note: ADC peripheral disable is forcing stop of potential |
1151 | } |
1151 | * conversion on injected group. If injected group is under use, it |
1152 | 1152 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
|
1153 | /* Return function status */ |
1153 | * @param hadc ADC handle |
1154 | return tmp_hal_status; |
1154 | * @retval HAL status. |
1155 | } |
1155 | */ |
1156 | 1156 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
|
1157 | /** |
1157 | { |
1158 | * @brief Stop ADC conversion of regular group (and injected channels in |
1158 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1159 | * case of auto_injection mode), disable ADC peripheral. |
1159 | |
1160 | * @note: ADC peripheral disable is forcing stop of potential |
1160 | /* Check the parameters */ |
1161 | * conversion on injected group. If injected group is under use, it |
1161 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1162 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
1162 | |
1163 | * @param hadc ADC handle |
1163 | /* Process locked */ |
1164 | * @retval HAL status. |
1164 | __HAL_LOCK(hadc); |
1165 | */ |
1165 | |
1166 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
1166 | /* Stop potential conversion on going, on regular and injected groups */ |
1167 | { |
1167 | /* Disable ADC peripheral */ |
1168 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1168 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
1169 | 1169 | ||
1170 | /* Check the parameters */ |
1170 | /* Check if ADC is effectively disabled */ |
1171 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1171 | if (tmp_hal_status == HAL_OK) |
1172 | 1172 | { |
|
1173 | /* Process locked */ |
1173 | /* Set ADC state */ |
1174 | __HAL_LOCK(hadc); |
1174 | ADC_STATE_CLR_SET(hadc->State, |
1175 | 1175 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
|
1176 | /* Stop potential conversion on going, on regular and injected groups */ |
1176 | HAL_ADC_STATE_READY); |
1177 | /* Disable ADC peripheral */ |
1177 | } |
1178 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
1178 | |
1179 | 1179 | /* Process unlocked */ |
|
1180 | /* Check if ADC is effectively disabled */ |
1180 | __HAL_UNLOCK(hadc); |
1181 | if (tmp_hal_status == HAL_OK) |
1181 | |
1182 | { |
1182 | /* Return function status */ |
1183 | /* Set ADC state */ |
1183 | return tmp_hal_status; |
1184 | ADC_STATE_CLR_SET(hadc->State, |
1184 | } |
1185 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
1185 | |
1186 | HAL_ADC_STATE_READY); |
1186 | /** |
1187 | } |
1187 | * @brief Wait for regular group conversion to be completed. |
1188 | 1188 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
|
1189 | /* Process unlocked */ |
1189 | * conversion) are cleared by this function, with an exception: |
1190 | __HAL_UNLOCK(hadc); |
1190 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
1191 | 1191 | * not cleared to not interfere with this feature until data register |
|
1192 | /* Return function status */ |
1192 | * is read using function HAL_ADC_GetValue(). |
1193 | return tmp_hal_status; |
1193 | * @note This function cannot be used in a particular setup: ADC configured |
1194 | } |
1194 | * in DMA mode and polling for end of each conversion (ADC init |
1195 | 1195 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
|
1196 | /** |
1196 | * In this case, DMA resets the flag EOC and polling cannot be |
1197 | * @brief Wait for regular group conversion to be completed. |
1197 | * performed on each conversion. Nevertheless, polling can still |
1198 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
1198 | * be performed on the complete sequence (ADC init |
1199 | * conversion) are cleared by this function, with an exception: |
1199 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
1200 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
1200 | * @param hadc ADC handle |
1201 | * not cleared to not interfere with this feature until data register |
1201 | * @param Timeout Timeout value in millisecond. |
1202 | * is read using function HAL_ADC_GetValue(). |
1202 | * @retval HAL status |
1203 | * @note This function cannot be used in a particular setup: ADC configured |
1203 | */ |
1204 | * in DMA mode and polling for end of each conversion (ADC init |
1204 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
1205 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
1205 | { |
1206 | * In this case, DMA resets the flag EOC and polling cannot be |
1206 | uint32_t tickstart = 0; |
1207 | * performed on each conversion. Nevertheless, polling can still |
1207 | |
1208 | * be performed on the complete sequence (ADC init |
1208 | /* Check the parameters */ |
1209 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
1209 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1210 | * @param hadc ADC handle |
1210 | |
1211 | * @param Timeout Timeout value in millisecond. |
1211 | /* Verification that ADC configuration is compliant with polling for */ |
1212 | * @retval HAL status |
1212 | /* each conversion: */ |
1213 | */ |
1213 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
1214 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
1214 | /* several ranks and polling for end of each conversion. */ |
1215 | { |
1215 | /* For code simplicity sake, this particular case is generalized to */ |
1216 | uint32_t tickstart = 0; |
1216 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
1217 | 1217 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && |
|
1218 | /* Check the parameters */ |
1218 | HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) |
1219 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1219 | { |
1220 | 1220 | /* Update ADC state machine to error */ |
|
1221 | /* Verification that ADC configuration is compliant with polling for */ |
1221 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
1222 | /* each conversion: */ |
1222 | |
1223 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
1223 | /* Process unlocked */ |
1224 | /* several ranks and polling for end of each conversion. */ |
1224 | __HAL_UNLOCK(hadc); |
1225 | /* For code simplicity sake, this particular case is generalized to */ |
1225 | |
1226 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
1226 | return HAL_ERROR; |
1227 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && |
1227 | } |
1228 | HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) |
1228 | |
1229 | { |
1229 | /* Get tick count */ |
1230 | /* Update ADC state machine to error */ |
1230 | tickstart = HAL_GetTick(); |
1231 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
1231 | |
1232 | 1232 | /* Wait until End of Conversion flag is raised */ |
|
1233 | /* Process unlocked */ |
1233 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
1234 | __HAL_UNLOCK(hadc); |
1234 | { |
1235 | 1235 | /* Check if timeout is disabled (set to infinite wait) */ |
|
1236 | return HAL_ERROR; |
1236 | if(Timeout != HAL_MAX_DELAY) |
1237 | } |
1237 | { |
1238 | 1238 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
|
1239 | /* Get tick count */ |
1239 | { |
1240 | tickstart = HAL_GetTick(); |
1240 | /* New check to avoid false timeout detection in case of preemption */ |
1241 | 1241 | if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
|
1242 | /* Wait until End of Conversion flag is raised */ |
1242 | { |
1243 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
1243 | /* Update ADC state machine to timeout */ |
1244 | { |
1244 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
1245 | /* Check if timeout is disabled (set to infinite wait) */ |
1245 | |
1246 | if(Timeout != HAL_MAX_DELAY) |
1246 | /* Process unlocked */ |
1247 | { |
1247 | __HAL_UNLOCK(hadc); |
1248 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
1248 | |
1249 | { |
1249 | return HAL_TIMEOUT; |
1250 | /* New check to avoid false timeout detection in case of preemption */ |
1250 | } |
1251 | if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
1251 | } |
1252 | { |
1252 | } |
1253 | /* Update ADC state machine to timeout */ |
1253 | } |
1254 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
1254 | |
1255 | 1255 | /* Clear end of conversion flag of regular group if low power feature */ |
|
1256 | /* Process unlocked */ |
1256 | /* "Auto Wait" is disabled, to not interfere with this feature until data */ |
1257 | __HAL_UNLOCK(hadc); |
1257 | /* register is read using function HAL_ADC_GetValue(). */ |
1258 | 1258 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
|
1259 | return HAL_TIMEOUT; |
1259 | { |
1260 | } |
1260 | /* Clear regular group conversion flag */ |
1261 | } |
1261 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
1262 | } |
1262 | } |
1263 | } |
1263 | |
1264 | 1264 | /* Update ADC state machine */ |
|
1265 | /* Clear end of conversion flag of regular group if low power feature */ |
1265 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
1266 | /* "Auto Wait" is disabled, to not interfere with this feature until data */ |
1266 | |
1267 | /* register is read using function HAL_ADC_GetValue(). */ |
1267 | /* Determine whether any further conversion upcoming on group regular */ |
1268 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
1268 | /* by external trigger, continuous mode or scan sequence on going. */ |
1269 | { |
1269 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
1270 | /* Clear regular group conversion flag */ |
1270 | /* The test of scan sequence on going is done either with scan */ |
1271 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
1271 | /* sequence disabled or with end of conversion flag set to */ |
1272 | } |
1272 | /* of end of sequence. */ |
1273 | 1273 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
|
1274 | /* Update ADC state machine */ |
1274 | (hadc->Init.ContinuousConvMode == DISABLE) && |
1275 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
1275 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
1276 | 1276 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
|
1277 | /* Determine whether any further conversion upcoming on group regular */ |
1277 | { |
1278 | /* by external trigger, continuous mode or scan sequence on going. */ |
1278 | /* Set ADC state */ |
1279 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
1279 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
1280 | /* The test of scan sequence on going is done either with scan */ |
1280 | |
1281 | /* sequence disabled or with end of conversion flag set to */ |
1281 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1282 | /* of end of sequence. */ |
1282 | { |
1283 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
1283 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
1284 | (hadc->Init.ContinuousConvMode == DISABLE) && |
1284 | } |
1285 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
1285 | } |
1286 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
1286 | |
1287 | { |
1287 | /* Return ADC state */ |
1288 | /* Set ADC state */ |
1288 | return HAL_OK; |
1289 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
1289 | } |
1290 | 1290 | ||
1291 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1291 | /** |
1292 | { |
1292 | * @brief Poll for conversion event. |
1293 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
1293 | * @param hadc ADC handle |
1294 | } |
1294 | * @param EventType the ADC event type. |
1295 | } |
1295 | * This parameter can be one of the following values: |
1296 | 1296 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event. |
|
1297 | /* Return ADC state */ |
1297 | * @arg ADC_OVR_EVENT: ADC Overrun event. |
1298 | return HAL_OK; |
1298 | * @param Timeout Timeout value in millisecond. |
1299 | } |
1299 | * @retval HAL status |
1300 | 1300 | */ |
|
1301 | /** |
1301 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
1302 | * @brief Poll for conversion event. |
1302 | { |
1303 | * @param hadc ADC handle |
1303 | uint32_t tickstart = 0; |
1304 | * @param EventType the ADC event type. |
1304 | |
1305 | * This parameter can be one of the following values: |
1305 | /* Check the parameters */ |
1306 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event. |
1306 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1307 | * @arg ADC_OVR_EVENT: ADC Overrun event. |
1307 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
1308 | * @param Timeout Timeout value in millisecond. |
1308 | |
1309 | * @retval HAL status |
1309 | /* Get tick count */ |
1310 | */ |
1310 | tickstart = HAL_GetTick(); |
1311 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
1311 | |
1312 | { |
1312 | /* Check selected event flag */ |
1313 | uint32_t tickstart = 0; |
1313 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
1314 | 1314 | { |
|
1315 | /* Check the parameters */ |
1315 | /* Check if timeout is disabled (set to infinite wait) */ |
1316 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1316 | if(Timeout != HAL_MAX_DELAY) |
1317 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
1317 | { |
1318 | 1318 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
|
1319 | /* Get tick count */ |
1319 | { |
1320 | tickstart = HAL_GetTick(); |
1320 | /* New check to avoid false timeout detection in case of preemption */ |
1321 | 1321 | if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
|
1322 | /* Check selected event flag */ |
1322 | { |
1323 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
1323 | /* Update ADC state machine to timeout */ |
1324 | { |
1324 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
1325 | /* Check if timeout is disabled (set to infinite wait) */ |
1325 | |
1326 | if(Timeout != HAL_MAX_DELAY) |
1326 | /* Process unlocked */ |
1327 | { |
1327 | __HAL_UNLOCK(hadc); |
1328 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
1328 | |
1329 | { |
1329 | return HAL_TIMEOUT; |
1330 | /* New check to avoid false timeout detection in case of preemption */ |
1330 | } |
1331 | if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
1331 | } |
1332 | { |
1332 | } |
1333 | /* Update ADC state machine to timeout */ |
1333 | } |
1334 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
1334 | |
1335 | 1335 | switch(EventType) |
|
1336 | /* Process unlocked */ |
1336 | { |
1337 | __HAL_UNLOCK(hadc); |
1337 | /* Analog watchdog (level out of window) event */ |
1338 | 1338 | case ADC_AWD_EVENT: |
|
1339 | return HAL_TIMEOUT; |
1339 | /* Set ADC state */ |
1340 | } |
1340 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
1341 | } |
1341 | |
1342 | } |
1342 | /* Clear ADC analog watchdog flag */ |
1343 | } |
1343 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
1344 | 1344 | break; |
|
1345 | switch(EventType) |
1345 | |
1346 | { |
1346 | /* Overrun event */ |
1347 | /* Analog watchdog (level out of window) event */ |
1347 | default: /* Case ADC_OVR_EVENT */ |
1348 | case ADC_AWD_EVENT: |
1348 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
1349 | /* Set ADC state */ |
1349 | /* refer to description of parameter "EOCSelection" for more */ |
1350 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
1350 | /* details. */ |
1351 | 1351 | ||
1352 | /* Clear ADC analog watchdog flag */ |
1352 | /* Set ADC state */ |
1353 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
1353 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
1354 | break; |
1354 | /* Set ADC error code to overrun */ |
1355 | 1355 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
|
1356 | /* Overrun event */ |
1356 | |
1357 | default: /* Case ADC_OVR_EVENT */ |
1357 | /* Clear ADC overrun flag */ |
1358 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
1358 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
1359 | /* refer to description of parameter "EOCSelection" for more */ |
1359 | break; |
1360 | /* details. */ |
1360 | } |
1361 | 1361 | ||
1362 | /* Set ADC state */ |
1362 | /* Return ADC state */ |
1363 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
1363 | return HAL_OK; |
1364 | /* Set ADC error code to overrun */ |
1364 | } |
1365 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
1365 | |
1366 | 1366 | /** |
|
1367 | /* Clear ADC overrun flag */ |
1367 | * @brief Enables ADC, starts conversion of regular group with interruption. |
1368 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
1368 | * Interruptions enabled in this function: |
1369 | break; |
1369 | * - EOC (end of conversion of regular group) |
1370 | } |
1370 | * - overrun |
1371 | 1371 | * Each of these interruptions has its dedicated callback function. |
|
1372 | /* Return ADC state */ |
1372 | * @param hadc ADC handle |
1373 | return HAL_OK; |
1373 | * @retval HAL status |
1374 | } |
1374 | */ |
1375 | 1375 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
|
1376 | /** |
1376 | { |
1377 | * @brief Enables ADC, starts conversion of regular group with interruption. |
1377 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1378 | * Interruptions enabled in this function: |
1378 | |
1379 | * - EOC (end of conversion of regular group) |
1379 | /* Check the parameters */ |
1380 | * - overrun |
1380 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1381 | * Each of these interruptions has its dedicated callback function. |
1381 | |
1382 | * @param hadc ADC handle |
1382 | /* Process locked */ |
1383 | * @retval HAL status |
1383 | __HAL_LOCK(hadc); |
1384 | */ |
1384 | |
1385 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
1385 | /* Enable the ADC peripheral */ |
1386 | { |
1386 | tmp_hal_status = ADC_Enable(hadc); |
1387 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1387 | |
1388 | 1388 | /* Start conversion if ADC is effectively enabled */ |
|
1389 | /* Check the parameters */ |
1389 | if (tmp_hal_status == HAL_OK) |
1390 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1390 | { |
1391 | 1391 | /* Set ADC state */ |
|
1392 | /* Process locked */ |
1392 | /* - Clear state bitfield related to regular group conversion results */ |
1393 | __HAL_LOCK(hadc); |
1393 | /* - Set state bitfield related to regular group operation */ |
1394 | 1394 | ADC_STATE_CLR_SET(hadc->State, |
|
1395 | /* Enable the ADC peripheral */ |
1395 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
1396 | tmp_hal_status = ADC_Enable(hadc); |
1396 | HAL_ADC_STATE_REG_BUSY); |
1397 | 1397 | ||
1398 | /* Start conversion if ADC is effectively enabled */ |
1398 | /* If conversions on group regular are also triggering group injected, */ |
1399 | if (tmp_hal_status == HAL_OK) |
1399 | /* update ADC state. */ |
1400 | { |
1400 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
1401 | /* Set ADC state */ |
1401 | { |
1402 | /* - Clear state bitfield related to regular group conversion results */ |
1402 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
1403 | /* - Set state bitfield related to regular group operation */ |
1403 | } |
1404 | ADC_STATE_CLR_SET(hadc->State, |
1404 | |
1405 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
1405 | /* State machine update: Check if an injected conversion is ongoing */ |
1406 | HAL_ADC_STATE_REG_BUSY); |
1406 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1407 | 1407 | { |
|
1408 | /* If conversions on group regular are also triggering group injected, */ |
1408 | /* Reset ADC error code fields related to conversions on group regular */ |
1409 | /* update ADC state. */ |
1409 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
1410 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
1410 | } |
1411 | { |
1411 | else |
1412 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
1412 | { |
1413 | } |
1413 | /* Reset ADC all error code fields */ |
1414 | 1414 | ADC_CLEAR_ERRORCODE(hadc); |
|
1415 | /* State machine update: Check if an injected conversion is ongoing */ |
1415 | } |
1416 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1416 | |
1417 | { |
1417 | /* Process unlocked */ |
1418 | /* Reset ADC error code fields related to conversions on group regular */ |
1418 | /* Unlock before starting ADC conversions: in case of potential */ |
1419 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
1419 | /* interruption, to let the process to ADC IRQ Handler. */ |
1420 | } |
1420 | __HAL_UNLOCK(hadc); |
1421 | else |
1421 | |
1422 | { |
1422 | /* Clear regular group conversion flag and overrun flag */ |
1423 | /* Reset ADC all error code fields */ |
1423 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
1424 | ADC_CLEAR_ERRORCODE(hadc); |
1424 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
1425 | } |
1425 | |
1426 | 1426 | /* Enable end of conversion interrupt for regular group */ |
|
1427 | /* Process unlocked */ |
1427 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); |
1428 | /* Unlock before starting ADC conversions: in case of potential */ |
1428 | |
1429 | /* interruption, to let the process to ADC IRQ Handler. */ |
1429 | /* Enable conversion of regular group. */ |
1430 | __HAL_UNLOCK(hadc); |
1430 | /* If software start has been selected, conversion starts immediately. */ |
1431 | 1431 | /* If external trigger has been selected, conversion will start at next */ |
|
1432 | /* Clear regular group conversion flag and overrun flag */ |
1432 | /* trigger event. */ |
1433 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
1433 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
1434 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
1434 | { |
1435 | 1435 | /* Start ADC conversion on regular group */ |
|
1436 | /* Enable end of conversion interrupt for regular group */ |
1436 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
1437 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); |
1437 | } |
1438 | 1438 | } |
|
1439 | /* Enable conversion of regular group. */ |
1439 | |
1440 | /* If software start has been selected, conversion starts immediately. */ |
1440 | /* Return function status */ |
1441 | /* If external trigger has been selected, conversion will start at next */ |
1441 | return tmp_hal_status; |
1442 | /* trigger event. */ |
1442 | } |
1443 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
1443 | |
1444 | { |
1444 | /** |
1445 | /* Start ADC conversion on regular group */ |
1445 | * @brief Stop ADC conversion of regular group (and injected group in |
1446 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
1446 | * case of auto_injection mode), disable interrution of |
1447 | } |
1447 | * end-of-conversion, disable ADC peripheral. |
1448 | } |
1448 | * @param hadc ADC handle |
1449 | 1449 | * @retval None |
|
1450 | /* Return function status */ |
1450 | */ |
1451 | return tmp_hal_status; |
1451 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
1452 | } |
1452 | { |
1453 | 1453 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
|
1454 | /** |
1454 | |
1455 | * @brief Stop ADC conversion of regular group (and injected group in |
1455 | /* Check the parameters */ |
1456 | * case of auto_injection mode), disable interrution of |
1456 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1457 | * end-of-conversion, disable ADC peripheral. |
1457 | |
1458 | * @param hadc ADC handle |
1458 | /* Process locked */ |
1459 | * @retval None |
1459 | __HAL_LOCK(hadc); |
1460 | */ |
1460 | |
1461 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
1461 | /* Stop potential conversion on going, on regular and injected groups */ |
1462 | { |
1462 | /* Disable ADC peripheral */ |
1463 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1463 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
1464 | 1464 | ||
1465 | /* Check the parameters */ |
1465 | /* Check if ADC is effectively disabled */ |
1466 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1466 | if (tmp_hal_status == HAL_OK) |
1467 | 1467 | { |
|
1468 | /* Process locked */ |
1468 | /* Disable ADC end of conversion interrupt for regular group */ |
1469 | __HAL_LOCK(hadc); |
1469 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
1470 | 1470 | ||
1471 | /* Stop potential conversion on going, on regular and injected groups */ |
1471 | /* Set ADC state */ |
1472 | /* Disable ADC peripheral */ |
1472 | ADC_STATE_CLR_SET(hadc->State, |
1473 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
1473 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
1474 | 1474 | HAL_ADC_STATE_READY); |
|
1475 | /* Check if ADC is effectively disabled */ |
1475 | } |
1476 | if (tmp_hal_status == HAL_OK) |
1476 | |
1477 | { |
1477 | /* Process unlocked */ |
1478 | /* Disable ADC end of conversion interrupt for regular group */ |
1478 | __HAL_UNLOCK(hadc); |
1479 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
1479 | |
1480 | 1480 | /* Return function status */ |
|
1481 | /* Set ADC state */ |
1481 | return tmp_hal_status; |
1482 | ADC_STATE_CLR_SET(hadc->State, |
1482 | } |
1483 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
1483 | |
1484 | HAL_ADC_STATE_READY); |
1484 | /** |
1485 | } |
1485 | * @brief Enables ADC, starts conversion of regular group and transfers result |
1486 | 1486 | * through DMA. |
|
1487 | /* Process unlocked */ |
1487 | * Interruptions enabled in this function: |
1488 | __HAL_UNLOCK(hadc); |
1488 | * - DMA transfer complete |
1489 | 1489 | * - DMA half transfer |
|
1490 | /* Return function status */ |
1490 | * - overrun |
1491 | return tmp_hal_status; |
1491 | * Each of these interruptions has its dedicated callback function. |
1492 | } |
1492 | * @param hadc ADC handle |
1493 | 1493 | * @param pData The destination Buffer address. |
|
1494 | /** |
1494 | * @param Length The length of data to be transferred from ADC peripheral to memory. |
1495 | * @brief Enables ADC, starts conversion of regular group and transfers result |
1495 | * @retval None |
1496 | * through DMA. |
1496 | */ |
1497 | * Interruptions enabled in this function: |
1497 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
1498 | * - DMA transfer complete |
1498 | { |
1499 | * - DMA half transfer |
1499 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1500 | * - overrun |
1500 | |
1501 | * Each of these interruptions has its dedicated callback function. |
1501 | /* Check the parameters */ |
1502 | * @param hadc ADC handle |
1502 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1503 | * @param pData The destination Buffer address. |
1503 | |
1504 | * @param Length The length of data to be transferred from ADC peripheral to memory. |
1504 | /* Process locked */ |
1505 | * @retval None |
1505 | __HAL_LOCK(hadc); |
1506 | */ |
1506 | |
1507 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
1507 | /* Enable the ADC peripheral */ |
1508 | { |
1508 | tmp_hal_status = ADC_Enable(hadc); |
1509 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1509 | |
1510 | 1510 | /* Start conversion if ADC is effectively enabled */ |
|
1511 | /* Check the parameters */ |
1511 | if (tmp_hal_status == HAL_OK) |
1512 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1512 | { |
1513 | 1513 | /* Set ADC state */ |
|
1514 | /* Process locked */ |
1514 | /* - Clear state bitfield related to regular group conversion results */ |
1515 | __HAL_LOCK(hadc); |
1515 | /* - Set state bitfield related to regular group operation */ |
1516 | 1516 | ADC_STATE_CLR_SET(hadc->State, |
|
1517 | /* Enable the ADC peripheral */ |
1517 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
1518 | tmp_hal_status = ADC_Enable(hadc); |
1518 | HAL_ADC_STATE_REG_BUSY); |
1519 | 1519 | ||
1520 | /* Start conversion if ADC is effectively enabled */ |
1520 | /* If conversions on group regular are also triggering group injected, */ |
1521 | if (tmp_hal_status == HAL_OK) |
1521 | /* update ADC state. */ |
1522 | { |
1522 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
1523 | /* Set ADC state */ |
1523 | { |
1524 | /* - Clear state bitfield related to regular group conversion results */ |
1524 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
1525 | /* - Set state bitfield related to regular group operation */ |
1525 | } |
1526 | ADC_STATE_CLR_SET(hadc->State, |
1526 | |
1527 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
1527 | /* State machine update: Check if an injected conversion is ongoing */ |
1528 | HAL_ADC_STATE_REG_BUSY); |
1528 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1529 | 1529 | { |
|
1530 | /* If conversions on group regular are also triggering group injected, */ |
1530 | /* Reset ADC error code fields related to conversions on group regular */ |
1531 | /* update ADC state. */ |
1531 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
1532 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
1532 | } |
1533 | { |
1533 | else |
1534 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
1534 | { |
1535 | } |
1535 | /* Reset ADC all error code fields */ |
1536 | 1536 | ADC_CLEAR_ERRORCODE(hadc); |
|
1537 | /* State machine update: Check if an injected conversion is ongoing */ |
1537 | } |
1538 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1538 | |
1539 | { |
1539 | /* Process unlocked */ |
1540 | /* Reset ADC error code fields related to conversions on group regular */ |
1540 | /* Unlock before starting ADC conversions: in case of potential */ |
1541 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
1541 | /* interruption, to let the process to ADC IRQ Handler. */ |
1542 | } |
1542 | __HAL_UNLOCK(hadc); |
1543 | else |
1543 | |
1544 | { |
1544 | /* Set the DMA transfer complete callback */ |
1545 | /* Reset ADC all error code fields */ |
1545 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
1546 | ADC_CLEAR_ERRORCODE(hadc); |
1546 | |
1547 | } |
1547 | /* Set the DMA half transfer complete callback */ |
1548 | 1548 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
|
1549 | /* Process unlocked */ |
1549 | |
1550 | /* Unlock before starting ADC conversions: in case of potential */ |
1550 | /* Set the DMA error callback */ |
1551 | /* interruption, to let the process to ADC IRQ Handler. */ |
1551 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
1552 | __HAL_UNLOCK(hadc); |
1552 | |
1553 | 1553 | ||
1554 | /* Set the DMA transfer complete callback */ |
1554 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
1555 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
1555 | /* start (in case of SW start): */ |
1556 | 1556 | ||
1557 | /* Set the DMA half transfer complete callback */ |
1557 | /* Clear regular group conversion flag and overrun flag */ |
1558 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
1558 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
1559 | 1559 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
|
1560 | /* Set the DMA error callback */ |
1560 | |
1561 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
1561 | /* Enable ADC overrun interrupt */ |
1562 | 1562 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
|
1563 | 1563 | ||
1564 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
1564 | /* Enable ADC DMA mode */ |
1565 | /* start (in case of SW start): */ |
1565 | hadc->Instance->CR2 |= ADC_CR2_DMA; |
1566 | 1566 | ||
1567 | /* Clear regular group conversion flag and overrun flag */ |
1567 | /* Start the DMA channel */ |
1568 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
1568 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
1569 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
1569 | |
1570 | 1570 | /* Enable conversion of regular group. */ |
|
1571 | /* Enable ADC overrun interrupt */ |
1571 | /* If software start has been selected, conversion starts immediately. */ |
1572 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
1572 | /* If external trigger has been selected, conversion will start at next */ |
1573 | 1573 | /* trigger event. */ |
|
1574 | /* Enable ADC DMA mode */ |
1574 | /* Note: Alternate trigger for single conversion could be to force an */ |
1575 | hadc->Instance->CR2 |= ADC_CR2_DMA; |
1575 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
1576 | 1576 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
|
1577 | /* Start the DMA channel */ |
1577 | { |
1578 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
1578 | /* Start ADC conversion on regular group */ |
1579 | 1579 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
|
1580 | /* Enable conversion of regular group. */ |
1580 | } |
1581 | /* If software start has been selected, conversion starts immediately. */ |
1581 | } |
1582 | /* If external trigger has been selected, conversion will start at next */ |
1582 | |
1583 | /* trigger event. */ |
1583 | /* Return function status */ |
1584 | /* Note: Alternate trigger for single conversion could be to force an */ |
1584 | return tmp_hal_status; |
1585 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
1585 | } |
1586 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
1586 | |
1587 | { |
1587 | /** |
1588 | /* Start ADC conversion on regular group */ |
1588 | * @brief Stop ADC conversion of regular group (and injected group in |
1589 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
1589 | * case of auto_injection mode), disable ADC DMA transfer, disable |
1590 | } |
1590 | * ADC peripheral. |
1591 | } |
1591 | * @note: ADC peripheral disable is forcing stop of potential |
1592 | 1592 | * conversion on injected group. If injected group is under use, it |
|
1593 | /* Return function status */ |
1593 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
1594 | return tmp_hal_status; |
1594 | * @param hadc ADC handle |
1595 | } |
1595 | * @retval HAL status. |
1596 | 1596 | */ |
|
1597 | /** |
1597 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
1598 | * @brief Stop ADC conversion of regular group (and injected group in |
1598 | { |
1599 | * case of auto_injection mode), disable ADC DMA transfer, disable |
1599 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1600 | * ADC peripheral. |
1600 | |
1601 | * @note: ADC peripheral disable is forcing stop of potential |
1601 | /* Check the parameters */ |
1602 | * conversion on injected group. If injected group is under use, it |
1602 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1603 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
1603 | |
1604 | * @param hadc ADC handle |
1604 | /* Process locked */ |
1605 | * @retval HAL status. |
1605 | __HAL_LOCK(hadc); |
1606 | */ |
1606 | |
1607 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
1607 | /* Stop potential conversion on going, on regular and injected groups */ |
1608 | { |
1608 | /* Disable ADC peripheral */ |
1609 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1609 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
1610 | 1610 | ||
1611 | /* Check the parameters */ |
1611 | /* Check if ADC is effectively disabled */ |
1612 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1612 | if (tmp_hal_status == HAL_OK) |
1613 | 1613 | { |
|
1614 | /* Process locked */ |
1614 | /* Disable ADC DMA mode */ |
1615 | __HAL_LOCK(hadc); |
1615 | hadc->Instance->CR2 &= ~ADC_CR2_DMA; |
1616 | 1616 | ||
1617 | /* Stop potential conversion on going, on regular and injected groups */ |
1617 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
1618 | /* Disable ADC peripheral */ |
1618 | /* DMA transfer is on going) */ |
1619 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
1619 | if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) |
1620 | 1620 | { |
|
1621 | /* Check if ADC is effectively disabled */ |
1621 | HAL_DMA_Abort(hadc->DMA_Handle); |
1622 | if (tmp_hal_status == HAL_OK) |
1622 | |
1623 | { |
1623 | /* Check if DMA channel effectively disabled */ |
1624 | /* Disable ADC DMA mode */ |
1624 | if (tmp_hal_status != HAL_OK) |
1625 | hadc->Instance->CR2 &= ~ADC_CR2_DMA; |
1625 | { |
1626 | 1626 | /* Update ADC state machine to error */ |
|
1627 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
1627 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
1628 | /* DMA transfer is on going) */ |
1628 | } |
1629 | if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) |
1629 | } |
1630 | { |
1630 | |
1631 | HAL_DMA_Abort(hadc->DMA_Handle); |
1631 | /* Set ADC state */ |
1632 | 1632 | ADC_STATE_CLR_SET(hadc->State, |
|
1633 | /* Check if DMA channel effectively disabled */ |
1633 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
1634 | if (tmp_hal_status != HAL_OK) |
1634 | HAL_ADC_STATE_READY); |
1635 | { |
1635 | |
1636 | /* Update ADC state machine to error */ |
1636 | /* Disable ADC overrun interrupt */ |
1637 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
1637 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
1638 | } |
1638 | } |
1639 | } |
1639 | |
1640 | 1640 | /* Process unlocked */ |
|
1641 | /* Set ADC state */ |
1641 | __HAL_UNLOCK(hadc); |
1642 | ADC_STATE_CLR_SET(hadc->State, |
1642 | |
1643 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
1643 | /* Return function status */ |
1644 | HAL_ADC_STATE_READY); |
1644 | return tmp_hal_status; |
1645 | 1645 | } |
|
1646 | /* Disable ADC overrun interrupt */ |
1646 | |
1647 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
1647 | /** |
1648 | } |
1648 | * @brief Get ADC regular group conversion result. |
1649 | 1649 | * @note Reading register DR automatically clears ADC flag EOC |
|
1650 | /* Process unlocked */ |
1650 | * (ADC group regular end of unitary conversion). |
1651 | __HAL_UNLOCK(hadc); |
1651 | * @note This function does not clear ADC flag EOS |
1652 | 1652 | * (ADC group regular end of sequence conversion). |
|
1653 | /* Return function status */ |
1653 | * Occurrence of flag EOS rising: |
1654 | return tmp_hal_status; |
1654 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
1655 | } |
1655 | * to flag EOC. |
1656 | 1656 | * - If sequencer is composed of several ranks, during the scan |
|
1657 | /** |
1657 | * sequence flag EOC only is raised, at the end of the scan sequence |
1658 | * @brief Get ADC regular group conversion result. |
1658 | * both flags EOC and EOS are raised. |
1659 | * @note Reading register DR automatically clears ADC flag EOC |
1659 | * To clear this flag, either use function: |
1660 | * (ADC group regular end of unitary conversion). |
1660 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
1661 | * @note This function does not clear ADC flag EOS |
1661 | * model polling: @ref HAL_ADC_PollForConversion() |
1662 | * (ADC group regular end of sequence conversion). |
1662 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
1663 | * Occurrence of flag EOS rising: |
1663 | * @param hadc ADC handle |
1664 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
1664 | * @retval ADC group regular conversion data |
1665 | * to flag EOC. |
1665 | */ |
1666 | * - If sequencer is composed of several ranks, during the scan |
1666 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
1667 | * sequence flag EOC only is raised, at the end of the scan sequence |
1667 | { |
1668 | * both flags EOC and EOS are raised. |
1668 | /* Check the parameters */ |
1669 | * To clear this flag, either use function: |
1669 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1670 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
1670 | |
1671 | * model polling: @ref HAL_ADC_PollForConversion() |
1671 | /* Note: EOC flag is not cleared here by software because automatically */ |
1672 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
1672 | /* cleared by hardware when reading register DR. */ |
1673 | * @param hadc ADC handle |
1673 | |
1674 | * @retval ADC group regular conversion data |
1674 | /* Return ADC converted value */ |
1675 | */ |
1675 | return hadc->Instance->DR; |
1676 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
1676 | } |
1677 | { |
1677 | |
1678 | /* Check the parameters */ |
1678 | /** |
1679 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1679 | * @brief Handles ADC interrupt request |
1680 | 1680 | * @param hadc ADC handle |
|
1681 | /* Note: EOC flag is not cleared here by software because automatically */ |
1681 | * @retval None |
1682 | /* cleared by hardware when reading register DR. */ |
1682 | */ |
1683 | 1683 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
|
1684 | /* Return ADC converted value */ |
1684 | { |
1685 | return hadc->Instance->DR; |
1685 | uint32_t tmp_sr = hadc->Instance->SR; |
1686 | } |
1686 | uint32_t tmp_cr1 = hadc->Instance->CR1; |
1687 | 1687 | ||
1688 | /** |
1688 | /* Check the parameters */ |
1689 | * @brief Handles ADC interrupt request |
1689 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1690 | * @param hadc ADC handle |
1690 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
1691 | * @retval None |
1691 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
1692 | */ |
1692 | |
1693 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
1693 | |
1694 | { |
1694 | /* ========== Check End of Conversion flag for regular group ========== */ |
1695 | /* Check the parameters */ |
1695 | if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) |
1696 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1696 | { |
1697 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
1697 | if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) |
1698 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
1698 | { |
1699 | 1699 | /* Update state machine on conversion status if not in error state */ |
|
1700 | 1700 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
|
1701 | /* ========== Check End of Conversion flag for regular group ========== */ |
1701 | { |
1702 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) |
1702 | /* Set ADC state */ |
1703 | { |
1703 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
1704 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) |
1704 | } |
1705 | { |
1705 | |
1706 | /* Update state machine on conversion status if not in error state */ |
1706 | /* Determine whether any further conversion upcoming on group regular */ |
1707 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
1707 | /* by external trigger, continuous mode or scan sequence on going. */ |
1708 | { |
1708 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
1709 | /* Set ADC state */ |
1709 | /* The test of scan sequence on going is done either with scan */ |
1710 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
1710 | /* sequence disabled or with end of conversion flag set to */ |
1711 | } |
1711 | /* of end of sequence. */ |
1712 | 1712 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
|
1713 | /* Determine whether any further conversion upcoming on group regular */ |
1713 | (hadc->Init.ContinuousConvMode == DISABLE) && |
1714 | /* by external trigger, continuous mode or scan sequence on going. */ |
1714 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
1715 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
1715 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
1716 | /* The test of scan sequence on going is done either with scan */ |
1716 | { |
1717 | /* sequence disabled or with end of conversion flag set to */ |
1717 | /* Disable ADC end of single conversion interrupt on group regular */ |
1718 | /* of end of sequence. */ |
1718 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
1719 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
1719 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
1720 | (hadc->Init.ContinuousConvMode == DISABLE) && |
1720 | /* by overrun IRQ process below. */ |
1721 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
1721 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
1722 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
1722 | |
1723 | { |
1723 | /* Set ADC state */ |
1724 | /* Disable ADC end of single conversion interrupt on group regular */ |
1724 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
1725 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
1725 | |
1726 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
1726 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1727 | /* by overrun IRQ process below. */ |
1727 | { |
1728 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
1728 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
1729 | 1729 | } |
|
1730 | /* Set ADC state */ |
1730 | } |
1731 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
1731 | |
1732 | 1732 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|
1733 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
1733 | hadc->ConvCpltCallback(hadc); |
1734 | { |
1734 | #else |
1735 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
1735 | HAL_ADC_ConvCpltCallback(hadc); |
1736 | } |
1736 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1737 | } |
1737 | |
1738 | 1738 | /* Clear regular group conversion flag */ |
|
1739 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
1739 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
1740 | hadc->ConvCpltCallback(hadc); |
1740 | } |
1741 | #else |
1741 | } |
1742 | HAL_ADC_ConvCpltCallback(hadc); |
1742 | |
1743 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1743 | /* ========== Check End of Conversion flag for injected group ========== */ |
1744 | 1744 | if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) |
|
1745 | /* Clear regular group conversion flag */ |
1745 | { |
1746 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
1746 | if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) |
1747 | } |
1747 | { |
1748 | } |
1748 | /* Update state machine on conversion status if not in error state */ |
1749 | 1749 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
|
1750 | /* ========== Check End of Conversion flag for injected group ========== */ |
1750 | { |
1751 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) |
1751 | /* Set ADC state */ |
1752 | { |
1752 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
1753 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) |
1753 | } |
1754 | { |
1754 | |
1755 | /* Update state machine on conversion status if not in error state */ |
1755 | /* Determine whether any further conversion upcoming on group injected */ |
1756 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
1756 | /* by external trigger, scan sequence on going or by automatic injected */ |
1757 | { |
1757 | /* conversion from group regular (same conditions as group regular */ |
1758 | /* Set ADC state */ |
1758 | /* interruption disabling above). */ |
1759 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
1759 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
1760 | } |
1760 | (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || |
1761 | 1761 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && |
|
1762 | /* Determine whether any further conversion upcoming on group injected */ |
1762 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
1763 | /* by external trigger, scan sequence on going or by automatic injected */ |
1763 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
1764 | /* conversion from group regular (same conditions as group regular */ |
1764 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
1765 | /* interruption disabling above). */ |
1765 | { |
1766 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
1766 | /* Disable ADC end of single conversion interrupt on group injected */ |
1767 | (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || |
1767 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
1768 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && |
1768 | |
1769 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
1769 | /* Set ADC state */ |
1770 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
1770 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
1771 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
1771 | |
1772 | { |
1772 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
1773 | /* Disable ADC end of single conversion interrupt on group injected */ |
1773 | { |
1774 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
1774 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
1775 | 1775 | } |
|
1776 | /* Set ADC state */ |
1776 | } |
1777 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
1777 | |
1778 | 1778 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|
1779 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
1779 | hadc->InjectedConvCpltCallback(hadc); |
1780 | { |
1780 | #else |
1781 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
1781 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
1782 | } |
1782 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1783 | } |
1783 | |
1784 | 1784 | /* Clear injected group conversion flag */ |
|
1785 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
1785 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
1786 | hadc->InjectedConvCpltCallback(hadc); |
1786 | } |
1787 | #else |
1787 | } |
1788 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
1788 | |
1789 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1789 | /* ========== Check Analog watchdog flags ========== */ |
1790 | 1790 | if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) |
|
1791 | /* Clear injected group conversion flag */ |
1791 | { |
1792 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
1792 | if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) |
1793 | } |
1793 | { |
1794 | } |
1794 | /* Set ADC state */ |
1795 | 1795 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
|
1796 | /* ========== Check Analog watchdog flags ========== */ |
1796 | |
1797 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
1797 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
1798 | { |
1798 | hadc->LevelOutOfWindowCallback(hadc); |
1799 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) |
1799 | #else |
1800 | { |
1800 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
1801 | /* Set ADC state */ |
1801 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1802 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
1802 | |
1803 | 1803 | /* Clear the ADC analog watchdog flag */ |
|
1804 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
1804 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
1805 | hadc->LevelOutOfWindowCallback(hadc); |
1805 | } |
1806 | #else |
1806 | } |
1807 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
1807 | |
1808 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1808 | /* ========== Check Overrun flag ========== */ |
1809 | 1809 | if((tmp_cr1 & ADC_IT_OVR) == ADC_IT_OVR) |
|
1810 | /* Clear the ADC analog watchdog flag */ |
1810 | { |
1811 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
1811 | if((tmp_sr & ADC_FLAG_OVR) == ADC_FLAG_OVR) |
1812 | } |
1812 | { |
1813 | } |
1813 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
1814 | 1814 | /* refer to description of parameter "EOCSelection" for more */ |
|
1815 | /* ========== Check Overrun flag ========== */ |
1815 | /* details. */ |
1816 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
1816 | |
1817 | { |
1817 | /* Set ADC error code to overrun */ |
1818 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR)) |
1818 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
1819 | { |
1819 | |
1820 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
1820 | /* Clear ADC overrun flag */ |
1821 | /* refer to description of parameter "EOCSelection" for more */ |
1821 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
1822 | /* details. */ |
1822 | |
1823 | 1823 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|
1824 | /* Set ADC error code to overrun */ |
1824 | hadc->ErrorCallback(hadc); |
1825 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
1825 | #else |
1826 | 1826 | HAL_ADC_ErrorCallback(hadc); |
|
1827 | /* Clear ADC overrun flag */ |
1827 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1828 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
1828 | |
1829 | 1829 | /* Clear the Overrun flag */ |
|
1830 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
1830 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
1831 | hadc->ErrorCallback(hadc); |
1831 | } |
1832 | #else |
1832 | } |
1833 | HAL_ADC_ErrorCallback(hadc); |
1833 | |
1834 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
1834 | } |
1835 | 1835 | ||
1836 | /* Clear the Overrun flag */ |
1836 | /** |
1837 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
1837 | * @brief Conversion complete callback in non blocking mode |
1838 | } |
1838 | * @param hadc ADC handle |
1839 | } |
1839 | * @retval None |
1840 | 1840 | */ |
|
1841 | } |
1841 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
1842 | 1842 | { |
|
1843 | /** |
1843 | /* Prevent unused argument(s) compilation warning */ |
1844 | * @brief Conversion complete callback in non blocking mode |
1844 | UNUSED(hadc); |
1845 | * @param hadc ADC handle |
1845 | |
1846 | * @retval None |
1846 | /* NOTE : This function should not be modified. When the callback is needed, |
1847 | */ |
1847 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
1848 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
1848 | */ |
1849 | { |
1849 | } |
1850 | /* Prevent unused argument(s) compilation warning */ |
1850 | |
1851 | UNUSED(hadc); |
1851 | /** |
1852 | 1852 | * @brief Conversion DMA half-transfer callback in non blocking mode |
|
1853 | /* NOTE : This function should not be modified. When the callback is needed, |
1853 | * @param hadc ADC handle |
1854 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
1854 | * @retval None |
1855 | */ |
1855 | */ |
1856 | } |
1856 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
1857 | 1857 | { |
|
1858 | /** |
1858 | /* Prevent unused argument(s) compilation warning */ |
1859 | * @brief Conversion DMA half-transfer callback in non blocking mode |
1859 | UNUSED(hadc); |
1860 | * @param hadc ADC handle |
1860 | |
1861 | * @retval None |
1861 | /* NOTE : This function should not be modified. When the callback is needed, |
1862 | */ |
1862 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
1863 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
1863 | */ |
1864 | { |
1864 | } |
1865 | /* Prevent unused argument(s) compilation warning */ |
1865 | |
1866 | UNUSED(hadc); |
1866 | /** |
1867 | 1867 | * @brief Analog watchdog callback in non blocking mode. |
|
1868 | /* NOTE : This function should not be modified. When the callback is needed, |
1868 | * @param hadc ADC handle |
1869 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
1869 | * @retval None |
1870 | */ |
1870 | */ |
1871 | } |
1871 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
1872 | 1872 | { |
|
1873 | /** |
1873 | /* Prevent unused argument(s) compilation warning */ |
1874 | * @brief Analog watchdog callback in non blocking mode. |
1874 | UNUSED(hadc); |
1875 | * @param hadc ADC handle |
1875 | |
1876 | * @retval None |
1876 | /* NOTE : This function should not be modified. When the callback is needed, |
1877 | */ |
1877 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
1878 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
1878 | */ |
1879 | { |
1879 | } |
1880 | /* Prevent unused argument(s) compilation warning */ |
1880 | |
1881 | UNUSED(hadc); |
1881 | /** |
1882 | 1882 | * @brief ADC error callback in non blocking mode |
|
1883 | /* NOTE : This function should not be modified. When the callback is needed, |
1883 | * (ADC conversion with interruption or transfer by DMA) |
1884 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
1884 | * @note In case of error due to overrun when using ADC with DMA transfer |
1885 | */ |
1885 | * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): |
1886 | } |
1886 | * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". |
1887 | 1887 | * - If needed, restart a new ADC conversion using function |
|
1888 | /** |
1888 | * "HAL_ADC_Start_DMA()" |
1889 | * @brief ADC error callback in non blocking mode |
1889 | * (this function is also clearing overrun flag) |
1890 | * (ADC conversion with interruption or transfer by DMA) |
1890 | * @param hadc ADC handle |
1891 | * @note In case of error due to overrun when using ADC with DMA transfer |
1891 | * @retval None |
1892 | * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): |
1892 | */ |
1893 | * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". |
1893 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
1894 | * - If needed, restart a new ADC conversion using function |
1894 | { |
1895 | * "HAL_ADC_Start_DMA()" |
1895 | /* Prevent unused argument(s) compilation warning */ |
1896 | * (this function is also clearing overrun flag) |
1896 | UNUSED(hadc); |
1897 | * @param hadc ADC handle |
1897 | |
1898 | * @retval None |
1898 | /* NOTE : This function should not be modified. When the callback is needed, |
1899 | */ |
1899 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
1900 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
1900 | */ |
1901 | { |
1901 | } |
1902 | /* Prevent unused argument(s) compilation warning */ |
1902 | |
1903 | UNUSED(hadc); |
1903 | |
1904 | 1904 | /** |
|
1905 | /* NOTE : This function should not be modified. When the callback is needed, |
1905 | * @} |
1906 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
1906 | */ |
1907 | */ |
1907 | |
1908 | } |
1908 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
1909 | 1909 | * @brief Peripheral Control functions |
|
1910 | 1910 | * |
|
1911 | /** |
1911 | @verbatim |
1912 | * @} |
1912 | =============================================================================== |
1913 | */ |
1913 | ##### Peripheral Control functions ##### |
1914 | 1914 | =============================================================================== |
|
1915 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
1915 | [..] This section provides functions allowing to: |
1916 | * @brief Peripheral Control functions |
1916 | (+) Configure channels on regular group |
1917 | * |
1917 | (+) Configure the analog watchdog |
1918 | @verbatim |
1918 | |
1919 | =============================================================================== |
1919 | @endverbatim |
1920 | ##### Peripheral Control functions ##### |
1920 | * @{ |
1921 | =============================================================================== |
1921 | */ |
1922 | [..] This section provides functions allowing to: |
1922 | |
1923 | (+) Configure channels on regular group |
1923 | /** |
1924 | (+) Configure the analog watchdog |
1924 | * @brief Configures the the selected channel to be linked to the regular |
1925 | |
1925 | * group. |
1926 | @endverbatim |
1926 | * @note In case of usage of internal measurement channels: |
1927 | * @{ |
1927 | * Vbat/VrefInt/TempSensor. |
1928 | */ |
1928 | * These internal paths can be be disabled using function |
1929 | 1929 | * HAL_ADC_DeInit(). |
|
1930 | /** |
1930 | * @note Possibility to update parameters on the fly: |
1931 | * @brief Configures the the selected channel to be linked to the regular |
1931 | * This function initializes channel into regular group, following |
1932 | * group. |
1932 | * calls to this function can be used to reconfigure some parameters |
1933 | * @note In case of usage of internal measurement channels: |
1933 | * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting |
1934 | * Vbat/VrefInt/TempSensor. |
1934 | * the ADC. |
1935 | * These internal paths can be be disabled using function |
1935 | * The setting of these parameters is conditioned to ADC state. |
1936 | * HAL_ADC_DeInit(). |
1936 | * For parameters constraints, see comments of structure |
1937 | * @note Possibility to update parameters on the fly: |
1937 | * "ADC_ChannelConfTypeDef". |
1938 | * This function initializes channel into regular group, following |
1938 | * @param hadc ADC handle |
1939 | * calls to this function can be used to reconfigure some parameters |
1939 | * @param sConfig Structure of ADC channel for regular group. |
1940 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
1940 | * @retval HAL status |
1941 | * the ADC. |
1941 | */ |
1942 | * The setting of these parameters is conditioned to ADC state. |
1942 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
1943 | * For parameters constraints, see comments of structure |
1943 | { |
1944 | * "ADC_ChannelConfTypeDef". |
1944 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1945 | * @param hadc ADC handle |
1945 | __IO uint32_t wait_loop_index = 0; |
1946 | * @param sConfig Structure of ADC channel for regular group. |
1946 | |
1947 | * @retval HAL status |
1947 | /* Check the parameters */ |
1948 | */ |
1948 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1949 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
1949 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
1950 | { |
1950 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
1951 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
1951 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
1952 | __IO uint32_t wait_loop_index = 0; |
1952 | |
1953 | 1953 | /* Process locked */ |
|
1954 | /* Check the parameters */ |
1954 | __HAL_LOCK(hadc); |
1955 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
1955 | |
1956 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
1956 | |
1957 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
1957 | /* Regular sequence configuration */ |
1958 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
1958 | /* For Rank 1 to 6 */ |
1959 | 1959 | if (sConfig->Rank < 7) |
|
1960 | /* Process locked */ |
1960 | { |
1961 | __HAL_LOCK(hadc); |
1961 | MODIFY_REG(hadc->Instance->SQR5, |
1962 | 1962 | ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), |
|
1963 | 1963 | ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); |
|
1964 | /* Regular sequence configuration */ |
1964 | } |
1965 | /* For Rank 1 to 6 */ |
1965 | /* For Rank 7 to 12 */ |
1966 | if (sConfig->Rank < 7) |
1966 | else if (sConfig->Rank < 13) |
1967 | { |
1967 | { |
1968 | MODIFY_REG(hadc->Instance->SQR5, |
1968 | MODIFY_REG(hadc->Instance->SQR4, |
1969 | ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), |
1969 | ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), |
1970 | ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); |
1970 | ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); |
1971 | } |
1971 | } |
1972 | /* For Rank 7 to 12 */ |
1972 | /* For Rank 13 to 18 */ |
1973 | else if (sConfig->Rank < 13) |
1973 | else if (sConfig->Rank < 19) |
1974 | { |
1974 | { |
1975 | MODIFY_REG(hadc->Instance->SQR4, |
1975 | MODIFY_REG(hadc->Instance->SQR3, |
1976 | ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), |
1976 | ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), |
1977 | ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); |
1977 | ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); |
1978 | } |
1978 | } |
1979 | /* For Rank 13 to 18 */ |
1979 | /* For Rank 19 to 24 */ |
1980 | else if (sConfig->Rank < 19) |
1980 | else if (sConfig->Rank < 25) |
1981 | { |
1981 | { |
1982 | MODIFY_REG(hadc->Instance->SQR3, |
1982 | MODIFY_REG(hadc->Instance->SQR2, |
1983 | ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), |
1983 | ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), |
1984 | ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); |
1984 | ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); |
1985 | } |
1985 | } |
1986 | /* For Rank 19 to 24 */ |
1986 | /* For Rank 25 to 28 */ |
1987 | else if (sConfig->Rank < 25) |
1987 | else |
1988 | { |
1988 | { |
1989 | MODIFY_REG(hadc->Instance->SQR2, |
1989 | MODIFY_REG(hadc->Instance->SQR1, |
1990 | ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), |
1990 | ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), |
1991 | ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); |
1991 | ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); |
1992 | } |
1992 | } |
1993 | /* For Rank 25 to 28 */ |
1993 | |
1994 | else |
1994 | |
1995 | { |
1995 | /* Channel sampling time configuration */ |
1996 | MODIFY_REG(hadc->Instance->SQR1, |
1996 | /* For channels 0 to 9 */ |
1997 | ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), |
1997 | if (sConfig->Channel < ADC_CHANNEL_10) |
1998 | ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); |
1998 | { |
1999 | } |
1999 | MODIFY_REG(hadc->Instance->SMPR3, |
2000 | 2000 | ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), |
|
2001 | 2001 | ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); |
|
2002 | /* Channel sampling time configuration */ |
2002 | } |
2003 | /* For channels 0 to 9 */ |
2003 | /* For channels 10 to 19 */ |
2004 | if (sConfig->Channel < ADC_CHANNEL_10) |
2004 | else if (sConfig->Channel < ADC_CHANNEL_20) |
2005 | { |
2005 | { |
2006 | MODIFY_REG(hadc->Instance->SMPR3, |
2006 | MODIFY_REG(hadc->Instance->SMPR2, |
2007 | ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), |
2007 | ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), |
2008 | ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); |
2008 | ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); |
2009 | } |
2009 | } |
2010 | /* For channels 10 to 19 */ |
2010 | /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ |
2011 | else if (sConfig->Channel < ADC_CHANNEL_20) |
2011 | /* For channels 20 to 29 for devices Cat4, Cat.5 */ |
2012 | { |
2012 | else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) |
2013 | MODIFY_REG(hadc->Instance->SMPR2, |
2013 | { |
2014 | ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), |
2014 | MODIFY_REG(hadc->Instance->SMPR1, |
2015 | ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); |
2015 | ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), |
2016 | } |
2016 | ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); |
2017 | /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ |
2017 | } |
2018 | /* For channels 20 to 29 for devices Cat4, Cat.5 */ |
2018 | /* For channels 30 to 31 for devices Cat4, Cat.5 */ |
2019 | else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) |
2019 | else |
2020 | { |
2020 | { |
2021 | MODIFY_REG(hadc->Instance->SMPR1, |
2021 | ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); |
2022 | ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), |
2022 | } |
2023 | ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); |
2023 | |
2024 | } |
2024 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
2025 | /* For channels 30 to 31 for devices Cat4, Cat.5 */ |
2025 | /* and VREFINT measurement path. */ |
2026 | else |
2026 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || |
2027 | { |
2027 | (sConfig->Channel == ADC_CHANNEL_VREFINT) ) |
2028 | ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); |
2028 | { |
2029 | } |
2029 | if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET) |
2030 | 2030 | { |
|
2031 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
2031 | SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
2032 | /* and VREFINT measurement path. */ |
2032 | |
2033 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || |
2033 | if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) |
2034 | (sConfig->Channel == ADC_CHANNEL_VREFINT) ) |
2034 | { |
2035 | { |
2035 | /* Delay for temperature sensor stabilization time */ |
2036 | if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET) |
2036 | /* Compute number of CPU cycles to wait for */ |
2037 | { |
2037 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); |
2038 | SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
2038 | while(wait_loop_index != 0) |
2039 | 2039 | { |
|
2040 | if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) |
2040 | wait_loop_index--; |
2041 | { |
2041 | } |
2042 | /* Delay for temperature sensor stabilization time */ |
2042 | } |
2043 | /* Compute number of CPU cycles to wait for */ |
2043 | } |
2044 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); |
2044 | } |
2045 | while(wait_loop_index != 0) |
2045 | |
2046 | { |
2046 | /* Process unlocked */ |
2047 | wait_loop_index--; |
2047 | __HAL_UNLOCK(hadc); |
2048 | } |
2048 | |
2049 | } |
2049 | /* Return function status */ |
2050 | } |
2050 | return tmp_hal_status; |
2051 | } |
2051 | } |
2052 | 2052 | ||
2053 | /* Process unlocked */ |
2053 | /** |
2054 | __HAL_UNLOCK(hadc); |
2054 | * @brief Configures the analog watchdog. |
2055 | 2055 | * @note Analog watchdog thresholds can be modified while ADC conversion |
|
2056 | /* Return function status */ |
2056 | * is on going. |
2057 | return tmp_hal_status; |
2057 | * In this case, some constraints must be taken into account: |
2058 | } |
2058 | * the programmed threshold values are effective from the next |
2059 | 2059 | * ADC EOC (end of unitary conversion). |
|
2060 | /** |
2060 | * Considering that registers write delay may happen due to |
2061 | * @brief Configures the analog watchdog. |
2061 | * bus activity, this might cause an uncertainty on the |
2062 | * @note Analog watchdog thresholds can be modified while ADC conversion |
2062 | * effective timing of the new programmed threshold values. |
2063 | * is on going. |
2063 | * @param hadc ADC handle |
2064 | * In this case, some constraints must be taken into account: |
2064 | * @param AnalogWDGConfig Structure of ADC analog watchdog configuration |
2065 | * the programmed threshold values are effective from the next |
2065 | * @retval HAL status |
2066 | * ADC EOC (end of unitary conversion). |
2066 | */ |
2067 | * Considering that registers write delay may happen due to |
2067 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
2068 | * bus activity, this might cause an uncertainty on the |
2068 | { |
2069 | * effective timing of the new programmed threshold values. |
2069 | /* Check the parameters */ |
2070 | * @param hadc ADC handle |
2070 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
2071 | * @param AnalogWDGConfig Structure of ADC analog watchdog configuration |
2071 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
2072 | * @retval HAL status |
2072 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
2073 | */ |
2073 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); |
2074 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
2074 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); |
2075 | { |
2075 | |
2076 | /* Check the parameters */ |
2076 | if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || |
2077 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
2077 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || |
2078 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
2078 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) |
2079 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
2079 | { |
2080 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); |
2080 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
2081 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); |
2081 | } |
2082 | 2082 | ||
2083 | if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || |
2083 | /* Process locked */ |
2084 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || |
2084 | __HAL_LOCK(hadc); |
2085 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) |
2085 | |
2086 | { |
2086 | /* Analog watchdog configuration */ |
2087 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
2087 | |
2088 | } |
2088 | /* Configure ADC Analog watchdog interrupt */ |
2089 | 2089 | if(AnalogWDGConfig->ITMode == ENABLE) |
|
2090 | /* Process locked */ |
2090 | { |
2091 | __HAL_LOCK(hadc); |
2091 | /* Enable the ADC Analog watchdog interrupt */ |
2092 | 2092 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
|
2093 | /* Analog watchdog configuration */ |
2093 | } |
2094 | 2094 | else |
|
2095 | /* Configure ADC Analog watchdog interrupt */ |
2095 | { |
2096 | if(AnalogWDGConfig->ITMode == ENABLE) |
2096 | /* Disable the ADC Analog watchdog interrupt */ |
2097 | { |
2097 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
2098 | /* Enable the ADC Analog watchdog interrupt */ |
2098 | } |
2099 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
2099 | |
2100 | } |
2100 | /* Configuration of analog watchdog: */ |
2101 | else |
2101 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
2102 | { |
2102 | /* one or all channels. */ |
2103 | /* Disable the ADC Analog watchdog interrupt */ |
2103 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
2104 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
2104 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
2105 | } |
2105 | hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | |
2106 | 2106 | ADC_CR1_JAWDEN | |
|
2107 | /* Configuration of analog watchdog: */ |
2107 | ADC_CR1_AWDEN | |
2108 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
2108 | ADC_CR1_AWDCH ); |
2109 | /* one or all channels. */ |
2109 | |
2110 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
2110 | hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | |
2111 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
2111 | AnalogWDGConfig->Channel ); |
2112 | hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | |
2112 | |
2113 | ADC_CR1_JAWDEN | |
2113 | /* Set the high threshold */ |
2114 | ADC_CR1_AWDEN | |
2114 | hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; |
2115 | ADC_CR1_AWDCH ); |
2115 | |
2116 | 2116 | /* Set the low threshold */ |
|
2117 | hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | |
2117 | hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; |
2118 | AnalogWDGConfig->Channel ); |
2118 | |
2119 | 2119 | /* Process unlocked */ |
|
2120 | /* Set the high threshold */ |
2120 | __HAL_UNLOCK(hadc); |
2121 | hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; |
2121 | |
2122 | 2122 | /* Return function status */ |
|
2123 | /* Set the low threshold */ |
2123 | return HAL_OK; |
2124 | hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; |
2124 | } |
2125 | 2125 | ||
2126 | /* Process unlocked */ |
2126 | |
2127 | __HAL_UNLOCK(hadc); |
2127 | /** |
2128 | 2128 | * @} |
|
2129 | /* Return function status */ |
2129 | */ |
2130 | return HAL_OK; |
2130 | |
2131 | } |
2131 | |
2132 | 2132 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
|
2133 | 2133 | * @brief Peripheral State functions |
|
2134 | /** |
2134 | * |
2135 | * @} |
2135 | @verbatim |
2136 | */ |
2136 | =============================================================================== |
2137 | 2137 | ##### Peripheral State and Errors functions ##### |
|
2138 | 2138 | =============================================================================== |
|
2139 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
2139 | [..] |
2140 | * @brief Peripheral State functions |
2140 | This subsection provides functions to get in run-time the status of the |
2141 | * |
2141 | peripheral. |
2142 | @verbatim |
2142 | (+) Check the ADC state |
2143 | =============================================================================== |
2143 | (+) Check the ADC error code |
2144 | ##### Peripheral State and Errors functions ##### |
2144 | |
2145 | =============================================================================== |
2145 | @endverbatim |
2146 | [..] |
2146 | * @{ |
2147 | This subsection provides functions to get in run-time the status of the |
2147 | */ |
2148 | peripheral. |
2148 | |
2149 | (+) Check the ADC state |
2149 | /** |
2150 | (+) Check the ADC error code |
2150 | * @brief return the ADC state |
2151 | 2151 | * @param hadc ADC handle |
|
2152 | @endverbatim |
2152 | * @retval HAL state |
2153 | * @{ |
2153 | */ |
2154 | */ |
2154 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
2155 | 2155 | { |
|
2156 | /** |
2156 | /* Return ADC state */ |
2157 | * @brief return the ADC state |
2157 | return hadc->State; |
2158 | * @param hadc ADC handle |
2158 | } |
2159 | * @retval HAL state |
2159 | |
2160 | */ |
2160 | /** |
2161 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
2161 | * @brief Return the ADC error code |
2162 | { |
2162 | * @param hadc ADC handle |
2163 | /* Return ADC state */ |
2163 | * @retval ADC Error Code |
2164 | return hadc->State; |
2164 | */ |
2165 | } |
2165 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
2166 | 2166 | { |
|
2167 | /** |
2167 | return hadc->ErrorCode; |
2168 | * @brief Return the ADC error code |
2168 | } |
2169 | * @param hadc ADC handle |
2169 | |
2170 | * @retval ADC Error Code |
2170 | /** |
2171 | */ |
2171 | * @} |
2172 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
2172 | */ |
2173 | { |
2173 | |
2174 | return hadc->ErrorCode; |
2174 | /** |
2175 | } |
2175 | * @} |
2176 | 2176 | */ |
|
2177 | /** |
2177 | |
2178 | * @} |
2178 | /** @defgroup ADC_Private_Functions ADC Private Functions |
2179 | */ |
2179 | * @{ |
2180 | 2180 | */ |
|
2181 | /** |
2181 | |
2182 | * @} |
2182 | /** |
2183 | */ |
2183 | * @brief Enable the selected ADC. |
2184 | 2184 | * @note Prerequisite condition to use this function: ADC must be disabled |
|
2185 | /** @defgroup ADC_Private_Functions ADC Private Functions |
2185 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
2186 | * @{ |
2186 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
2187 | */ |
2187 | * performed automatically by hardware. |
2188 | 2188 | * In this mode, this function is useless and must not be called because |
|
2189 | /** |
2189 | * flag ADC_FLAG_RDY is not usable. |
2190 | * @brief Enable the selected ADC. |
2190 | * Therefore, this function must be called under condition of |
2191 | * @note Prerequisite condition to use this function: ADC must be disabled |
2191 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
2192 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
2192 | * @param hadc ADC handle |
2193 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
2193 | * @retval HAL status. |
2194 | * performed automatically by hardware. |
2194 | */ |
2195 | * In this mode, this function is useless and must not be called because |
2195 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
2196 | * flag ADC_FLAG_RDY is not usable. |
2196 | { |
2197 | * Therefore, this function must be called under condition of |
2197 | uint32_t tickstart = 0; |
2198 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
2198 | __IO uint32_t wait_loop_index = 0; |
2199 | * @param hadc ADC handle |
2199 | |
2200 | * @retval HAL status. |
2200 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
2201 | */ |
2201 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
2202 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
2202 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
2203 | { |
2203 | /* causes: ADC clock not running, ...). */ |
2204 | uint32_t tickstart = 0; |
2204 | if (ADC_IS_ENABLE(hadc) == RESET) |
2205 | __IO uint32_t wait_loop_index = 0; |
2205 | { |
2206 | 2206 | /* Enable the Peripheral */ |
|
2207 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
2207 | __HAL_ADC_ENABLE(hadc); |
2208 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
2208 | |
2209 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
2209 | /* Delay for ADC stabilization time */ |
2210 | /* causes: ADC clock not running, ...). */ |
2210 | /* Compute number of CPU cycles to wait for */ |
2211 | if (ADC_IS_ENABLE(hadc) == RESET) |
2211 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); |
2212 | { |
2212 | while(wait_loop_index != 0) |
2213 | /* Enable the Peripheral */ |
2213 | { |
2214 | __HAL_ADC_ENABLE(hadc); |
2214 | wait_loop_index--; |
2215 | 2215 | } |
|
2216 | /* Delay for ADC stabilization time */ |
2216 | |
2217 | /* Compute number of CPU cycles to wait for */ |
2217 | /* Get tick count */ |
2218 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); |
2218 | tickstart = HAL_GetTick(); |
2219 | while(wait_loop_index != 0) |
2219 | |
2220 | { |
2220 | /* Wait for ADC effectively enabled */ |
2221 | wait_loop_index--; |
2221 | while(ADC_IS_ENABLE(hadc) == RESET) |
2222 | } |
2222 | { |
2223 | 2223 | if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) |
|
2224 | /* Get tick count */ |
2224 | { |
2225 | tickstart = HAL_GetTick(); |
2225 | /* New check to avoid false timeout detection in case of preemption */ |
2226 | 2226 | if(ADC_IS_ENABLE(hadc) == RESET) |
|
2227 | /* Wait for ADC effectively enabled */ |
2227 | { |
2228 | while(ADC_IS_ENABLE(hadc) == RESET) |
2228 | /* Update ADC state machine to error */ |
2229 | { |
2229 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
2230 | if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) |
2230 | |
2231 | { |
2231 | /* Set ADC error code to ADC IP internal error */ |
2232 | /* New check to avoid false timeout detection in case of preemption */ |
2232 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
2233 | if(ADC_IS_ENABLE(hadc) == RESET) |
2233 | |
2234 | { |
2234 | /* Process unlocked */ |
2235 | /* Update ADC state machine to error */ |
2235 | __HAL_UNLOCK(hadc); |
2236 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
2236 | |
2237 | 2237 | return HAL_ERROR; |
|
2238 | /* Set ADC error code to ADC IP internal error */ |
2238 | } |
2239 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
2239 | } |
2240 | 2240 | } |
|
2241 | /* Process unlocked */ |
2241 | } |
2242 | __HAL_UNLOCK(hadc); |
2242 | |
2243 | 2243 | /* Return HAL status */ |
|
2244 | return HAL_ERROR; |
2244 | return HAL_OK; |
2245 | } |
2245 | } |
2246 | } |
2246 | |
2247 | } |
2247 | /** |
2248 | } |
2248 | * @brief Stop ADC conversion and disable the selected ADC |
2249 | 2249 | * @note Prerequisite condition to use this function: ADC conversions must be |
|
2250 | /* Return HAL status */ |
2250 | * stopped to disable the ADC. |
2251 | return HAL_OK; |
2251 | * @param hadc ADC handle |
2252 | } |
2252 | * @retval HAL status. |
2253 | 2253 | */ |
|
2254 | /** |
2254 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
2255 | * @brief Stop ADC conversion and disable the selected ADC |
2255 | { |
2256 | * @note Prerequisite condition to use this function: ADC conversions must be |
2256 | uint32_t tickstart = 0; |
2257 | * stopped to disable the ADC. |
2257 | |
2258 | * @param hadc ADC handle |
2258 | /* Verification if ADC is not already disabled */ |
2259 | * @retval HAL status. |
2259 | if (ADC_IS_ENABLE(hadc) != RESET) |
2260 | */ |
2260 | { |
2261 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
2261 | /* Disable the ADC peripheral */ |
2262 | { |
2262 | __HAL_ADC_DISABLE(hadc); |
2263 | uint32_t tickstart = 0; |
2263 | |
2264 | 2264 | /* Get tick count */ |
|
2265 | /* Verification if ADC is not already disabled */ |
2265 | tickstart = HAL_GetTick(); |
2266 | if (ADC_IS_ENABLE(hadc) != RESET) |
2266 | |
2267 | { |
2267 | /* Wait for ADC effectively disabled */ |
2268 | /* Disable the ADC peripheral */ |
2268 | while(ADC_IS_ENABLE(hadc) != RESET) |
2269 | __HAL_ADC_DISABLE(hadc); |
2269 | { |
2270 | 2270 | if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) |
|
2271 | /* Get tick count */ |
2271 | { |
2272 | tickstart = HAL_GetTick(); |
2272 | /* New check to avoid false timeout detection in case of preemption */ |
2273 | 2273 | if(ADC_IS_ENABLE(hadc) != RESET) |
|
2274 | /* Wait for ADC effectively disabled */ |
2274 | { |
2275 | while(ADC_IS_ENABLE(hadc) != RESET) |
2275 | /* Update ADC state machine to error */ |
2276 | { |
2276 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
2277 | if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) |
2277 | |
2278 | { |
2278 | /* Set ADC error code to ADC IP internal error */ |
2279 | /* New check to avoid false timeout detection in case of preemption */ |
2279 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
2280 | if(ADC_IS_ENABLE(hadc) != RESET) |
2280 | |
2281 | { |
2281 | return HAL_ERROR; |
2282 | /* Update ADC state machine to error */ |
2282 | } |
2283 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
2283 | } |
2284 | 2284 | } |
|
2285 | /* Set ADC error code to ADC IP internal error */ |
2285 | } |
2286 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
2286 | |
2287 | 2287 | /* Return HAL status */ |
|
2288 | return HAL_ERROR; |
2288 | return HAL_OK; |
2289 | } |
2289 | } |
2290 | } |
2290 | |
2291 | } |
2291 | /** |
2292 | } |
2292 | * @brief DMA transfer complete callback. |
2293 | 2293 | * @param hdma pointer to DMA handle. |
|
2294 | /* Return HAL status */ |
2294 | * @retval None |
2295 | return HAL_OK; |
2295 | */ |
2296 | } |
2296 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
2297 | 2297 | { |
|
2298 | /** |
2298 | /* Retrieve ADC handle corresponding to current DMA handle */ |
2299 | * @brief DMA transfer complete callback. |
2299 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2300 | * @param hdma pointer to DMA handle. |
2300 | |
2301 | * @retval None |
2301 | /* Update state machine on conversion status if not in error state */ |
2302 | */ |
2302 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
2303 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
2303 | { |
2304 | { |
2304 | /* Update ADC state machine */ |
2305 | /* Retrieve ADC handle corresponding to current DMA handle */ |
2305 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
2306 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2306 | |
2307 | 2307 | /* Determine whether any further conversion upcoming on group regular */ |
|
2308 | /* Update state machine on conversion status if not in error state */ |
2308 | /* by external trigger, continuous mode or scan sequence on going. */ |
2309 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
2309 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
2310 | { |
2310 | /* The test of scan sequence on going is done either with scan */ |
2311 | /* Update ADC state machine */ |
2311 | /* sequence disabled or with end of conversion flag set to */ |
2312 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
2312 | /* of end of sequence. */ |
2313 | 2313 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
|
2314 | /* Determine whether any further conversion upcoming on group regular */ |
2314 | (hadc->Init.ContinuousConvMode == DISABLE) && |
2315 | /* by external trigger, continuous mode or scan sequence on going. */ |
2315 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
2316 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
2316 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
2317 | /* The test of scan sequence on going is done either with scan */ |
2317 | { |
2318 | /* sequence disabled or with end of conversion flag set to */ |
2318 | /* Disable ADC end of single conversion interrupt on group regular */ |
2319 | /* of end of sequence. */ |
2319 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
2320 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
2320 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
2321 | (hadc->Init.ContinuousConvMode == DISABLE) && |
2321 | /* by overrun IRQ process below. */ |
2322 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
2322 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
2323 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
2323 | |
2324 | { |
2324 | /* Set ADC state */ |
2325 | /* Disable ADC end of single conversion interrupt on group regular */ |
2325 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
2326 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
2326 | |
2327 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
2327 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
2328 | /* by overrun IRQ process below. */ |
2328 | { |
2329 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
2329 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
2330 | 2330 | } |
|
2331 | /* Set ADC state */ |
2331 | } |
2332 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
2332 | |
2333 | 2333 | /* Conversion complete callback */ |
|
2334 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
2334 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
2335 | { |
2335 | hadc->ConvCpltCallback(hadc); |
2336 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
2336 | #else |
2337 | } |
2337 | HAL_ADC_ConvCpltCallback(hadc); |
2338 | } |
2338 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
2339 | 2339 | } |
|
2340 | /* Conversion complete callback */ |
2340 | else |
2341 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
2341 | { |
2342 | hadc->ConvCpltCallback(hadc); |
2342 | /* Call DMA error callback */ |
2343 | #else |
2343 | hadc->DMA_Handle->XferErrorCallback(hdma); |
2344 | HAL_ADC_ConvCpltCallback(hadc); |
2344 | } |
2345 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
2345 | } |
2346 | } |
2346 | |
2347 | else |
2347 | /** |
2348 | { |
2348 | * @brief DMA half transfer complete callback. |
2349 | /* Call DMA error callback */ |
2349 | * @param hdma pointer to DMA handle. |
2350 | hadc->DMA_Handle->XferErrorCallback(hdma); |
2350 | * @retval None |
2351 | } |
2351 | */ |
2352 | } |
2352 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
2353 | 2353 | { |
|
2354 | /** |
2354 | /* Retrieve ADC handle corresponding to current DMA handle */ |
2355 | * @brief DMA half transfer complete callback. |
2355 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2356 | * @param hdma pointer to DMA handle. |
2356 | |
2357 | * @retval None |
2357 | /* Half conversion callback */ |
2358 | */ |
2358 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
2359 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
2359 | hadc->ConvHalfCpltCallback(hadc); |
2360 | { |
2360 | #else |
2361 | /* Retrieve ADC handle corresponding to current DMA handle */ |
2361 | HAL_ADC_ConvHalfCpltCallback(hadc); |
2362 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2362 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
2363 | 2363 | } |
|
2364 | /* Half conversion callback */ |
2364 | |
2365 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
2365 | /** |
2366 | hadc->ConvHalfCpltCallback(hadc); |
2366 | * @brief DMA error callback |
2367 | #else |
2367 | * @param hdma pointer to DMA handle. |
2368 | HAL_ADC_ConvHalfCpltCallback(hadc); |
2368 | * @retval None |
2369 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
2369 | */ |
2370 | } |
2370 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
2371 | 2371 | { |
|
2372 | /** |
2372 | /* Retrieve ADC handle corresponding to current DMA handle */ |
2373 | * @brief DMA error callback |
2373 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2374 | * @param hdma pointer to DMA handle. |
2374 | |
2375 | * @retval None |
2375 | /* Set ADC state */ |
2376 | */ |
2376 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
2377 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
2377 | |
2378 | { |
2378 | /* Set ADC error code to DMA error */ |
2379 | /* Retrieve ADC handle corresponding to current DMA handle */ |
2379 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
2380 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2380 | |
2381 | 2381 | /* Error callback */ |
|
2382 | /* Set ADC state */ |
2382 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
2383 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
2383 | hadc->ErrorCallback(hadc); |
2384 | 2384 | #else |
|
2385 | /* Set ADC error code to DMA error */ |
2385 | HAL_ADC_ErrorCallback(hadc); |
2386 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
2386 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
2387 | 2387 | } |
|
2388 | /* Error callback */ |
2388 | |
2389 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
2389 | /** |
2390 | hadc->ErrorCallback(hadc); |
2390 | * @} |
2391 | #else |
2391 | */ |
2392 | HAL_ADC_ErrorCallback(hadc); |
2392 | |
2393 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
2393 | #endif /* HAL_ADC_MODULE_ENABLED */ |
2394 | } |
2394 | /** |
2395 | 2395 | * @} |
|
2396 | /** |
2396 | */ |
2397 | * @} |
2397 | |
2398 | */ |
2398 | /** |
2399 | 2399 | * @} |
|
2400 | #endif /* HAL_ADC_MODULE_ENABLED */ |
2400 | */ |
2401 | /** |
- | |
2402 | * @} |
- | |
2403 | */ |
- | |
2404 | - | ||
2405 | /** |
- | |
2406 | * @} |
- | |
2407 | */ |
- | |
2408 | - | ||
2409 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- |