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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_tim.h |
3 | * @file stm32l1xx_ll_tim.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of TIM LL module. |
5 | * @brief Header file of TIM LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef __STM32L1xx_LL_TIM_H |
| 21 | #ifndef __STM32L1xx_LL_TIM_H |
21 | #define __STM32L1xx_LL_TIM_H |
| 22 | #define __STM32L1xx_LL_TIM_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32l1xx.h" |
| 29 | #include "stm32l1xx.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7) |
|
| 35 | #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7) |
35 | |
| 36 | 36 | /** @defgroup TIM_LL TIM |
|
| 37 | /** @defgroup TIM_LL TIM |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
| 43 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
43 | * @{ |
| 44 | * @{ |
44 | */ |
| 45 | */ |
45 | static const uint8_t OFFSET_TAB_CCMRx[] = |
| 46 | static const uint8_t OFFSET_TAB_CCMRx[] = |
46 | { |
| 47 | { |
47 | 0x00U, /* 0: TIMx_CH1 */ |
| 48 | 0x00U, /* 0: TIMx_CH1 */ |
48 | 0x00U, /* 1: NA */ |
| 49 | 0x00U, /* 1: NA */ |
49 | 0x00U, /* 2: TIMx_CH2 */ |
| 50 | 0x00U, /* 2: TIMx_CH2 */ |
50 | 0x00U, /* 3: NA */ |
| 51 | 0x00U, /* 3: NA */ |
51 | 0x04U, /* 4: TIMx_CH3 */ |
| 52 | 0x04U, /* 4: TIMx_CH3 */ |
52 | 0x00U, /* 5: NA */ |
| 53 | 0x00U, /* 5: NA */ |
53 | 0x04U /* 6: TIMx_CH4 */ |
| 54 | 0x04U /* 6: TIMx_CH4 */ |
54 | }; |
| 55 | }; |
55 | |
| 56 | 56 | static const uint8_t SHIFT_TAB_OCxx[] = |
|
| 57 | static const uint8_t SHIFT_TAB_OCxx[] = |
57 | { |
| 58 | { |
58 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
| 59 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
59 | 0U, /* 1: - NA */ |
| 60 | 0U, /* 1: - NA */ |
60 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
| 61 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
61 | 0U, /* 3: - NA */ |
| 62 | 0U, /* 3: - NA */ |
62 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
| 63 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
63 | 0U, /* 5: - NA */ |
| 64 | 0U, /* 5: - NA */ |
64 | 8U /* 6: OC4M, OC4FE, OC4PE */ |
| 65 | 8U /* 6: OC4M, OC4FE, OC4PE */ |
65 | }; |
| 66 | }; |
66 | |
| 67 | 67 | static const uint8_t SHIFT_TAB_ICxx[] = |
|
| 68 | static const uint8_t SHIFT_TAB_ICxx[] = |
68 | { |
| 69 | { |
69 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
| 70 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
70 | 0U, /* 1: - NA */ |
| 71 | 0U, /* 1: - NA */ |
71 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
| 72 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
72 | 0U, /* 3: - NA */ |
| 73 | 0U, /* 3: - NA */ |
73 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
| 74 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
74 | 0U, /* 5: - NA */ |
| 75 | 0U, /* 5: - NA */ |
75 | 8U /* 6: CC4S, IC4PSC, IC4F */ |
| 76 | 8U /* 6: CC4S, IC4PSC, IC4F */ |
76 | }; |
| 77 | }; |
77 | |
| 78 | 78 | static const uint8_t SHIFT_TAB_CCxP[] = |
|
| 79 | static const uint8_t SHIFT_TAB_CCxP[] = |
79 | { |
| 80 | { |
80 | 0U, /* 0: CC1P */ |
| 81 | 0U, /* 0: CC1P */ |
81 | 0U, /* 1: NA */ |
| 82 | 0U, /* 1: NA */ |
82 | 4U, /* 2: CC2P */ |
| 83 | 4U, /* 2: CC2P */ |
83 | 0U, /* 3: NA */ |
| 84 | 0U, /* 3: NA */ |
84 | 8U, /* 4: CC3P */ |
| 85 | 8U, /* 4: CC3P */ |
85 | 0U, /* 5: NA */ |
| 86 | 0U, /* 5: NA */ |
86 | 12U /* 6: CC4P */ |
| 87 | 12U /* 6: CC4P */ |
87 | }; |
| 88 | }; |
88 | |
| 89 | 89 | /** |
|
| 90 | /** |
90 | * @} |
| 91 | * @} |
91 | */ |
| 92 | */ |
92 | |
| 93 | 93 | /* Private constants ---------------------------------------------------------*/ |
|
| 94 | /* Private constants ---------------------------------------------------------*/ |
94 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
| 95 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
95 | * @{ |
| 96 | * @{ |
96 | */ |
| 97 | */ |
97 | |
| 98 | 98 | ||
| 99 | 99 | #define TIMx_OR_RMP_SHIFT 16U |
|
| 100 | #define TIMx_OR_RMP_SHIFT 16U |
100 | #define TIMx_OR_RMP_MASK 0x0000FFFFU |
| 101 | #define TIMx_OR_RMP_MASK 0x0000FFFFU |
101 | #define TIM_OR_RMP_MASK ((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT) |
| 102 | #define TIM_OR_RMP_MASK ((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT) |
102 | #define TIM9_OR_RMP_MASK ((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT) |
| 103 | #define TIM9_OR_RMP_MASK ((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT) |
103 | #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) |
| 104 | #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) |
104 | #define TIM3_OR_RMP_MASK (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT) |
| 105 | #define TIM3_OR_RMP_MASK (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT) |
105 | |
| 106 | 106 | ||
| 107 | 107 | ||
| 108 | 108 | /** |
|
| 109 | /** |
109 | * @} |
| 110 | * @} |
110 | */ |
| 111 | */ |
111 | |
| 112 | 112 | /* Private macros ------------------------------------------------------------*/ |
|
| 113 | /* Private macros ------------------------------------------------------------*/ |
113 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
| 114 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
114 | * @{ |
| 115 | * @{ |
115 | */ |
| 116 | */ |
116 | /** @brief Convert channel id into channel index. |
| 117 | /** @brief Convert channel id into channel index. |
117 | * @param __CHANNEL__ This parameter can be one of the following values: |
| 118 | * @param __CHANNEL__ This parameter can be one of the following values: |
118 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 119 | * @arg @ref LL_TIM_CHANNEL_CH1 |
119 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 120 | * @arg @ref LL_TIM_CHANNEL_CH2 |
120 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 121 | * @arg @ref LL_TIM_CHANNEL_CH3 |
121 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 122 | * @arg @ref LL_TIM_CHANNEL_CH4 |
122 | * @retval none |
| 123 | * @retval none |
123 | */ |
| 124 | */ |
124 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
| 125 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
125 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
| 126 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
126 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
| 127 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
127 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U) |
| 128 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U) |
128 | |
| 129 | 129 | /** |
|
| 130 | /** |
130 | * @} |
| 131 | * @} |
131 | */ |
| 132 | */ |
132 | |
| 133 | 133 | ||
| 134 | 134 | /* Exported types ------------------------------------------------------------*/ |
|
| 135 | /* Exported types ------------------------------------------------------------*/ |
135 | #if defined(USE_FULL_LL_DRIVER) |
| 136 | #if defined(USE_FULL_LL_DRIVER) |
136 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
| 137 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
137 | * @{ |
| 138 | * @{ |
138 | */ |
| 139 | */ |
139 | |
| 140 | 140 | /** |
|
| 141 | /** |
141 | * @brief TIM Time Base configuration structure definition. |
| 142 | * @brief TIM Time Base configuration structure definition. |
142 | */ |
| 143 | */ |
143 | typedef struct |
| 144 | typedef struct |
144 | { |
| 145 | { |
145 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
| 146 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
146 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| 147 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
147 | |
| 148 | 148 | This feature can be modified afterwards using unitary function |
|
| 149 | This feature can be modified afterwards using unitary function |
149 | @ref LL_TIM_SetPrescaler().*/ |
| 150 | @ref LL_TIM_SetPrescaler().*/ |
150 | |
| 151 | 151 | uint32_t CounterMode; /*!< Specifies the counter mode. |
|
| 152 | uint32_t CounterMode; /*!< Specifies the counter mode. |
152 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
| 153 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
153 | |
| 154 | 154 | This feature can be modified afterwards using unitary function |
|
| 155 | This feature can be modified afterwards using unitary function |
155 | @ref LL_TIM_SetCounterMode().*/ |
| 156 | @ref LL_TIM_SetCounterMode().*/ |
156 | |
| 157 | 157 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
|
| 158 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
158 | Auto-Reload Register at the next update event. |
| 159 | Auto-Reload Register at the next update event. |
159 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| 160 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
160 | Some timer instances may support 32 bits counters. In that case this parameter must |
| 161 | Some timer instances may support 32 bits counters. In that case this parameter must |
161 | be a number between 0x0000 and 0xFFFFFFFF. |
| 162 | be a number between 0x0000 and 0xFFFFFFFF. |
162 | |
| 163 | 163 | This feature can be modified afterwards using unitary function |
|
| 164 | This feature can be modified afterwards using unitary function |
164 | @ref LL_TIM_SetAutoReload().*/ |
| 165 | @ref LL_TIM_SetAutoReload().*/ |
165 | |
| 166 | 166 | uint32_t ClockDivision; /*!< Specifies the clock division. |
|
| 167 | uint32_t ClockDivision; /*!< Specifies the clock division. |
167 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
| 168 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
168 | |
| 169 | 169 | This feature can be modified afterwards using unitary function |
|
| 170 | This feature can be modified afterwards using unitary function |
170 | @ref LL_TIM_SetClockDivision().*/ |
| 171 | @ref LL_TIM_SetClockDivision().*/ |
171 | } LL_TIM_InitTypeDef; |
| 172 | } LL_TIM_InitTypeDef; |
172 | |
| 173 | 173 | /** |
|
| 174 | /** |
174 | * @brief TIM Output Compare configuration structure definition. |
| 175 | * @brief TIM Output Compare configuration structure definition. |
175 | */ |
| 176 | */ |
176 | typedef struct |
| 177 | typedef struct |
177 | { |
| 178 | { |
178 | uint32_t OCMode; /*!< Specifies the output mode. |
| 179 | uint32_t OCMode; /*!< Specifies the output mode. |
179 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
| 180 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
180 | |
| 181 | 181 | This feature can be modified afterwards using unitary function |
|
| 182 | This feature can be modified afterwards using unitary function |
182 | @ref LL_TIM_OC_SetMode().*/ |
| 183 | @ref LL_TIM_OC_SetMode().*/ |
183 | |
| 184 | 184 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
|
| 185 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
185 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
| 186 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
186 | |
| 187 | 187 | This feature can be modified afterwards using unitary functions |
|
| 188 | This feature can be modified afterwards using unitary functions |
188 | @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
| 189 | @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
189 | |
| 190 | 190 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
|
| 191 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
191 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| 192 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
192 | |
| 193 | 193 | This feature can be modified afterwards using unitary function |
|
| 194 | This feature can be modified afterwards using unitary function |
194 | LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
| 195 | LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
195 | |
| 196 | 196 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
|
| 197 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
197 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
| 198 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
198 | |
| 199 | 199 | This feature can be modified afterwards using unitary function |
|
| 200 | This feature can be modified afterwards using unitary function |
200 | @ref LL_TIM_OC_SetPolarity().*/ |
| 201 | @ref LL_TIM_OC_SetPolarity().*/ |
201 | |
| 202 | 202 | ||
| 203 | 203 | } LL_TIM_OC_InitTypeDef; |
|
| 204 | } LL_TIM_OC_InitTypeDef; |
204 | |
| 205 | 205 | /** |
|
| 206 | /** |
206 | * @brief TIM Input Capture configuration structure definition. |
| 207 | * @brief TIM Input Capture configuration structure definition. |
207 | */ |
| 208 | */ |
208 | |
| 209 | 209 | typedef struct |
|
| 210 | typedef struct |
210 | { |
| 211 | { |
211 | |
| 212 | 212 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
|
| 213 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
213 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 214 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
214 | |
| 215 | 215 | This feature can be modified afterwards using unitary function |
|
| 216 | This feature can be modified afterwards using unitary function |
216 | @ref LL_TIM_IC_SetPolarity().*/ |
| 217 | @ref LL_TIM_IC_SetPolarity().*/ |
217 | |
| 218 | 218 | uint32_t ICActiveInput; /*!< Specifies the input. |
|
| 219 | uint32_t ICActiveInput; /*!< Specifies the input. |
219 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| 220 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
220 | |
| 221 | 221 | This feature can be modified afterwards using unitary function |
|
| 222 | This feature can be modified afterwards using unitary function |
222 | @ref LL_TIM_IC_SetActiveInput().*/ |
| 223 | @ref LL_TIM_IC_SetActiveInput().*/ |
223 | |
| 224 | 224 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
|
| 225 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
225 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 226 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
226 | |
| 227 | 227 | This feature can be modified afterwards using unitary function |
|
| 228 | This feature can be modified afterwards using unitary function |
228 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 229 | @ref LL_TIM_IC_SetPrescaler().*/ |
229 | |
| 230 | 230 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
|
| 231 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
231 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| 232 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
232 | |
| 233 | 233 | This feature can be modified afterwards using unitary function |
|
| 234 | This feature can be modified afterwards using unitary function |
234 | @ref LL_TIM_IC_SetFilter().*/ |
| 235 | @ref LL_TIM_IC_SetFilter().*/ |
235 | } LL_TIM_IC_InitTypeDef; |
| 236 | } LL_TIM_IC_InitTypeDef; |
236 | |
| 237 | 237 | ||
| 238 | 238 | /** |
|
| 239 | /** |
239 | * @brief TIM Encoder interface configuration structure definition. |
| 240 | * @brief TIM Encoder interface configuration structure definition. |
240 | */ |
| 241 | */ |
241 | typedef struct |
| 242 | typedef struct |
242 | { |
| 243 | { |
243 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
| 244 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
244 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
| 245 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
245 | |
| 246 | 246 | This feature can be modified afterwards using unitary function |
|
| 247 | This feature can be modified afterwards using unitary function |
247 | @ref LL_TIM_SetEncoderMode().*/ |
| 248 | @ref LL_TIM_SetEncoderMode().*/ |
248 | |
| 249 | 249 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
|
| 250 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
250 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 251 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
251 | |
| 252 | 252 | This feature can be modified afterwards using unitary function |
|
| 253 | This feature can be modified afterwards using unitary function |
253 | @ref LL_TIM_IC_SetPolarity().*/ |
| 254 | @ref LL_TIM_IC_SetPolarity().*/ |
254 | |
| 255 | 255 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
|
| 256 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
256 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| 257 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
257 | |
| 258 | 258 | This feature can be modified afterwards using unitary function |
|
| 259 | This feature can be modified afterwards using unitary function |
259 | @ref LL_TIM_IC_SetActiveInput().*/ |
| 260 | @ref LL_TIM_IC_SetActiveInput().*/ |
260 | |
| 261 | 261 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
|
| 262 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
262 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 263 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
263 | |
| 264 | 264 | This feature can be modified afterwards using unitary function |
|
| 265 | This feature can be modified afterwards using unitary function |
265 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 266 | @ref LL_TIM_IC_SetPrescaler().*/ |
266 | |
| 267 | 267 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
|
| 268 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
268 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| 269 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
269 | |
| 270 | 270 | This feature can be modified afterwards using unitary function |
|
| 271 | This feature can be modified afterwards using unitary function |
271 | @ref LL_TIM_IC_SetFilter().*/ |
| 272 | @ref LL_TIM_IC_SetFilter().*/ |
272 | |
| 273 | 273 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
|
| 274 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
274 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 275 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
275 | |
| 276 | 276 | This feature can be modified afterwards using unitary function |
|
| 277 | This feature can be modified afterwards using unitary function |
277 | @ref LL_TIM_IC_SetPolarity().*/ |
| 278 | @ref LL_TIM_IC_SetPolarity().*/ |
278 | |
| 279 | 279 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
|
| 280 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
280 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| 281 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
281 | |
| 282 | 282 | This feature can be modified afterwards using unitary function |
|
| 283 | This feature can be modified afterwards using unitary function |
283 | @ref LL_TIM_IC_SetActiveInput().*/ |
| 284 | @ref LL_TIM_IC_SetActiveInput().*/ |
284 | |
| 285 | 285 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
|
| 286 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
286 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 287 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
287 | |
| 288 | 288 | This feature can be modified afterwards using unitary function |
|
| 289 | This feature can be modified afterwards using unitary function |
289 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 290 | @ref LL_TIM_IC_SetPrescaler().*/ |
290 | |
| 291 | 291 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
|
| 292 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
292 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| 293 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
293 | |
| 294 | 294 | This feature can be modified afterwards using unitary function |
|
| 295 | This feature can be modified afterwards using unitary function |
295 | @ref LL_TIM_IC_SetFilter().*/ |
| 296 | @ref LL_TIM_IC_SetFilter().*/ |
296 | |
| 297 | 297 | } LL_TIM_ENCODER_InitTypeDef; |
|
| 298 | } LL_TIM_ENCODER_InitTypeDef; |
298 | |
| 299 | 299 | ||
| 300 | 300 | /** |
|
| 301 | /** |
301 | * @} |
| 302 | * @} |
302 | */ |
| 303 | */ |
303 | #endif /* USE_FULL_LL_DRIVER */ |
| 304 | #endif /* USE_FULL_LL_DRIVER */ |
304 | |
| 305 | 305 | /* Exported constants --------------------------------------------------------*/ |
|
| 306 | /* Exported constants --------------------------------------------------------*/ |
306 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
| 307 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
307 | * @{ |
| 308 | * @{ |
308 | */ |
| 309 | */ |
309 | |
| 310 | 310 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
|
| 311 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
311 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
| 312 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
312 | * @{ |
| 313 | * @{ |
313 | */ |
| 314 | */ |
314 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
| 315 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
315 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
| 316 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
316 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
| 317 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
317 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
| 318 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
318 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
| 319 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
319 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
| 320 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
320 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
| 321 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
321 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
| 322 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
322 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
| 323 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
323 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
| 324 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
324 | /** |
| 325 | /** |
325 | * @} |
| 326 | * @} |
326 | */ |
| 327 | */ |
327 | |
| 328 | 328 | /** @defgroup TIM_LL_EC_IT IT Defines |
|
| 329 | /** @defgroup TIM_LL_EC_IT IT Defines |
329 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
| 330 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
330 | * @{ |
| 331 | * @{ |
331 | */ |
| 332 | */ |
332 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
| 333 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
333 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
| 334 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
334 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
| 335 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
335 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
| 336 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
336 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
| 337 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
337 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
| 338 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
338 | /** |
| 339 | /** |
339 | * @} |
| 340 | * @} |
340 | */ |
| 341 | */ |
341 | |
| 342 | 342 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
|
| 343 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
343 | * @{ |
| 344 | * @{ |
344 | */ |
| 345 | */ |
345 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
| 346 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
346 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
| 347 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
347 | /** |
| 348 | /** |
348 | * @} |
| 349 | * @} |
349 | */ |
| 350 | */ |
350 | |
| 351 | 351 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
|
| 352 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
352 | * @{ |
| 353 | * @{ |
353 | */ |
| 354 | */ |
354 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
| 355 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
355 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
| 356 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
356 | /** |
| 357 | /** |
357 | * @} |
| 358 | * @} |
358 | */ |
| 359 | */ |
359 | |
| 360 | 360 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
|
| 361 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
361 | * @{ |
| 362 | * @{ |
362 | */ |
| 363 | */ |
363 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
| 364 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
364 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
| 365 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
365 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
| 366 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
366 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
| 367 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
367 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
| 368 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
368 | /** |
| 369 | /** |
369 | * @} |
| 370 | * @} |
370 | */ |
| 371 | */ |
371 | |
| 372 | 372 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
|
| 373 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
373 | * @{ |
| 374 | * @{ |
374 | */ |
| 375 | */ |
375 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
| 376 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
376 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
| 377 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
377 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
| 378 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
378 | /** |
| 379 | /** |
379 | * @} |
| 380 | * @} |
380 | */ |
| 381 | */ |
381 | |
| 382 | 382 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
|
| 383 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
383 | * @{ |
| 384 | * @{ |
384 | */ |
| 385 | */ |
385 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
| 386 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
386 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
| 387 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
387 | /** |
| 388 | /** |
388 | * @} |
| 389 | * @} |
389 | */ |
| 390 | */ |
390 | |
| 391 | 391 | ||
| 392 | 392 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
|
| 393 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
393 | * @{ |
| 394 | * @{ |
394 | */ |
| 395 | */ |
395 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
| 396 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
396 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
| 397 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
397 | /** |
| 398 | /** |
398 | * @} |
| 399 | * @} |
399 | */ |
| 400 | */ |
400 | |
| 401 | 401 | ||
| 402 | 402 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
|
| 403 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
403 | * @{ |
| 404 | * @{ |
404 | */ |
| 405 | */ |
405 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
| 406 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
406 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
| 407 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
407 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
| 408 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
408 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
| 409 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
409 | /** |
| 410 | /** |
410 | * @} |
| 411 | * @} |
411 | */ |
| 412 | */ |
412 | |
| 413 | 413 | #if defined(USE_FULL_LL_DRIVER) |
|
| 414 | #if defined(USE_FULL_LL_DRIVER) |
414 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
| 415 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
415 | * @{ |
| 416 | * @{ |
416 | */ |
| 417 | */ |
417 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
| 418 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
418 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
| 419 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
419 | /** |
| 420 | /** |
420 | * @} |
| 421 | * @} |
421 | */ |
| 422 | */ |
422 | #endif /* USE_FULL_LL_DRIVER */ |
| 423 | #endif /* USE_FULL_LL_DRIVER */ |
423 | |
| 424 | 424 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
|
| 425 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
425 | * @{ |
| 426 | * @{ |
426 | */ |
| 427 | */ |
427 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
| 428 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
428 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
| 429 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
429 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
| 430 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
430 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
| 431 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
431 | #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ |
| 432 | #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ |
432 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
| 433 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
433 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
| 434 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
434 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
| 435 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
435 | /** |
| 436 | /** |
436 | * @} |
| 437 | * @} |
437 | */ |
| 438 | */ |
438 | |
| 439 | 439 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
|
| 440 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
440 | * @{ |
| 441 | * @{ |
441 | */ |
| 442 | */ |
442 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
| 443 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
443 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
| 444 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
444 | /** |
| 445 | /** |
445 | * @} |
| 446 | * @} |
446 | */ |
| 447 | */ |
447 | |
| 448 | 448 | ||
| 449 | 449 | ||
| 450 | 450 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
|
| 451 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
451 | * @{ |
| 452 | * @{ |
452 | */ |
| 453 | */ |
453 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
| 454 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
454 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
| 455 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
455 | #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
| 456 | #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
456 | /** |
| 457 | /** |
457 | * @} |
| 458 | * @} |
458 | */ |
| 459 | */ |
459 | |
| 460 | 460 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
|
| 461 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
461 | * @{ |
| 462 | * @{ |
462 | */ |
| 463 | */ |
463 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
| 464 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
464 | #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
| 465 | #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
465 | #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
| 466 | #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
466 | #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
| 467 | #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
467 | /** |
| 468 | /** |
468 | * @} |
| 469 | * @} |
469 | */ |
| 470 | */ |
470 | |
| 471 | 471 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
|
| 472 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
472 | * @{ |
| 473 | * @{ |
473 | */ |
| 474 | */ |
474 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
| 475 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
475 | #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
| 476 | #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
476 | #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
| 477 | #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
477 | #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
| 478 | #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
478 | #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
| 479 | #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
479 | #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
| 480 | #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
480 | #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
| 481 | #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
481 | #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
| 482 | #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
482 | #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
| 483 | #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
483 | #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
| 484 | #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
484 | #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
| 485 | #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
485 | #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
| 486 | #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
486 | #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
| 487 | #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
487 | #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
| 488 | #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
488 | #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
| 489 | #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
489 | #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
| 490 | #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
490 | /** |
| 491 | /** |
491 | * @} |
| 492 | * @} |
492 | */ |
| 493 | */ |
493 | |
| 494 | 494 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
|
| 495 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
495 | * @{ |
| 496 | * @{ |
496 | */ |
| 497 | */ |
497 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
| 498 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
498 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
| 499 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
499 | #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ |
| 500 | #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ |
500 | /** |
| 501 | /** |
501 | * @} |
| 502 | * @} |
502 | */ |
| 503 | */ |
503 | |
| 504 | 504 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
|
| 505 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
505 | * @{ |
| 506 | * @{ |
506 | */ |
| 507 | */ |
507 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
| 508 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
508 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ |
| 509 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ |
509 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
| 510 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
510 | /** |
| 511 | /** |
511 | * @} |
| 512 | * @} |
512 | */ |
| 513 | */ |
513 | |
| 514 | 514 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
|
| 515 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
515 | * @{ |
| 516 | * @{ |
516 | */ |
| 517 | */ |
517 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
| 518 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
518 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
| 519 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
519 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ |
| 520 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ |
520 | /** |
| 521 | /** |
521 | * @} |
| 522 | * @} |
522 | */ |
| 523 | */ |
523 | |
| 524 | 524 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
|
| 525 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
525 | * @{ |
| 526 | * @{ |
526 | */ |
| 527 | */ |
527 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
| 528 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
528 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
| 529 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
529 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
| 530 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
530 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
| 531 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
531 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
| 532 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
532 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
| 533 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
533 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
| 534 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
534 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
| 535 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
535 | /** |
| 536 | /** |
536 | * @} |
| 537 | * @} |
537 | */ |
| 538 | */ |
538 | |
| 539 | 539 | ||
| 540 | 540 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
|
| 541 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
541 | * @{ |
| 542 | * @{ |
542 | */ |
| 543 | */ |
543 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
| 544 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
544 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
| 545 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
545 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
| 546 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
546 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
| 547 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
547 | /** |
| 548 | /** |
548 | * @} |
| 549 | * @} |
549 | */ |
| 550 | */ |
550 | |
| 551 | 551 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
|
| 552 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
552 | * @{ |
| 553 | * @{ |
553 | */ |
| 554 | */ |
554 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
| 555 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
555 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
| 556 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
556 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
| 557 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
557 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
| 558 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
558 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
| 559 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
559 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
| 560 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
560 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
| 561 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
561 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
| 562 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
562 | /** |
| 563 | /** |
563 | * @} |
| 564 | * @} |
564 | */ |
| 565 | */ |
565 | |
| 566 | 566 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
|
| 567 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
567 | * @{ |
| 568 | * @{ |
568 | */ |
| 569 | */ |
569 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
| 570 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
570 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
| 571 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
571 | /** |
| 572 | /** |
572 | * @} |
| 573 | * @} |
573 | */ |
| 574 | */ |
574 | |
| 575 | 575 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
|
| 576 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
576 | * @{ |
| 577 | * @{ |
577 | */ |
| 578 | */ |
578 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
| 579 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
579 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
| 580 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
580 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
| 581 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
581 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
| 582 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
582 | /** |
| 583 | /** |
583 | * @} |
| 584 | * @} |
584 | */ |
| 585 | */ |
585 | |
| 586 | 586 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
|
| 587 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
587 | * @{ |
| 588 | * @{ |
588 | */ |
| 589 | */ |
589 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
| 590 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
590 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
| 591 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
591 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
| 592 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
592 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
| 593 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
593 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
| 594 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
594 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
| 595 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
595 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ |
| 596 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ |
596 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
| 597 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
597 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
| 598 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
598 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
| 599 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
599 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ |
| 600 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ |
600 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
| 601 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
601 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ |
| 602 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ |
602 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
| 603 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
603 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
| 604 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
604 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
| 605 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
605 | /** |
| 606 | /** |
606 | * @} |
| 607 | * @} |
607 | */ |
| 608 | */ |
608 | |
| 609 | 609 | ||
| 610 | 610 | ||
| 611 | 611 | ||
| 612 | 612 | ||
| 613 | 613 | ||
| 614 | 614 | ||
| 615 | 615 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
|
| 616 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
616 | * @{ |
| 617 | * @{ |
617 | */ |
| 618 | */ |
618 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
| 619 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
619 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
| 620 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
620 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
| 621 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
621 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
| 622 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
622 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
| 623 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
623 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
| 624 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
624 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
| 625 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
625 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
| 626 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
626 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
| 627 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
627 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
| 628 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
628 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
| 629 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
629 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
| 630 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
630 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
| 631 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
631 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
| 632 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
632 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
| 633 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
633 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
| 634 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
634 | #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */ |
| 635 | #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */ |
635 | /** |
| 636 | /** |
636 | * @} |
| 637 | * @} |
637 | */ |
| 638 | */ |
638 | |
| 639 | 639 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
|
| 640 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
640 | * @{ |
| 641 | * @{ |
641 | */ |
| 642 | */ |
642 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
| 643 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
643 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
| 644 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
644 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
| 645 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
645 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
| 646 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
646 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
| 647 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
647 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
| 648 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
648 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
| 649 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
649 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
| 650 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
650 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
| 651 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
651 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
| 652 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
652 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
| 653 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
653 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
| 654 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
654 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
| 655 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
655 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
| 656 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
656 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
| 657 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
657 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
| 658 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
658 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
| 659 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
659 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
| 660 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
660 | /** |
| 661 | /** |
661 | * @} |
| 662 | * @} |
662 | */ |
| 663 | */ |
663 | |
| 664 | 664 | /** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability |
|
| 665 | /** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability |
665 | * @{ |
| 666 | * @{ |
666 | */ |
| 667 | */ |
667 | #define LL_TIM_TIM10_TI1_RMP_GPIO TIM_OR_RMP_MASK /*!< TIM10 channel1 is connected to GPIO */ |
| 668 | #define LL_TIM_TIM10_TI1_RMP_GPIO TIM_OR_RMP_MASK /*!< TIM10 channel1 is connected to GPIO */ |
668 | #define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSI internal clock */ |
| 669 | #define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSI internal clock */ |
669 | #define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSE internal clock */ |
| 670 | #define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSE internal clock */ |
670 | #define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */ |
| 671 | #define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */ |
671 | /** |
| 672 | /** |
672 | * @} |
| 673 | * @} |
673 | */ |
| 674 | */ |
674 | |
| 675 | 675 | /** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap |
|
| 676 | /** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap |
676 | * @{ |
| 677 | * @{ |
677 | */ |
| 678 | */ |
678 | #define LL_TIM_TIM10_ETR_RMP_LSE TIM_OR_RMP_MASK /*!< TIM10 ETR input is connected to LSE */ |
| 679 | #define LL_TIM_TIM10_ETR_RMP_LSE TIM_OR_RMP_MASK /*!< TIM10 ETR input is connected to LSE */ |
679 | #define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM10 ETR input is connected to TIM9 TGO */ |
| 680 | #define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM10 ETR input is connected to TIM9 TGO */ |
680 | /** |
| 681 | /** |
681 | * @} |
| 682 | * @} |
682 | */ |
| 683 | */ |
683 | |
| 684 | 684 | /** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI) |
|
| 685 | /** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI) |
685 | * @{ |
| 686 | * @{ |
686 | */ |
| 687 | */ |
687 | #define LL_TIM_TIM10_TI1_RMP TIM_OR_RMP_MASK /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */ |
| 688 | #define LL_TIM_TIM10_TI1_RMP TIM_OR_RMP_MASK /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */ |
688 | #define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RI */ |
| 689 | #define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RI */ |
689 | /** |
| 690 | /** |
690 | * @} |
| 691 | * @} |
691 | */ |
| 692 | */ |
692 | |
| 693 | 693 | /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability |
|
| 694 | /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability |
694 | * @{ |
| 695 | * @{ |
695 | */ |
| 696 | */ |
696 | #define LL_TIM_TIM11_TI1_RMP_GPIO TIM_OR_RMP_MASK /*!< TIM11 channel1 is connected to GPIO */ |
| 697 | #define LL_TIM_TIM11_TI1_RMP_GPIO TIM_OR_RMP_MASK /*!< TIM11 channel1 is connected to GPIO */ |
697 | #define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to MSI internal clock */ |
| 698 | #define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to MSI internal clock */ |
698 | #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to HSE RTC clock */ |
| 699 | #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to HSE RTC clock */ |
699 | #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */ |
| 700 | #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */ |
700 | /** |
| 701 | /** |
701 | * @} |
| 702 | * @} |
702 | */ |
| 703 | */ |
703 | |
| 704 | 704 | /** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap |
|
| 705 | /** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap |
705 | * @{ |
| 706 | * @{ |
706 | */ |
| 707 | */ |
707 | #define LL_TIM_TIM11_ETR_RMP_LSE TIM_OR_RMP_MASK /*!< TIM11 ETR input is connected to LSE */ |
| 708 | #define LL_TIM_TIM11_ETR_RMP_LSE TIM_OR_RMP_MASK /*!< TIM11 ETR input is connected to LSE */ |
708 | #define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM11 ETR input is connected to TIM9 TGO clock */ |
| 709 | #define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM11 ETR input is connected to TIM9 TGO clock */ |
709 | /** |
| 710 | /** |
710 | * @} |
| 711 | * @} |
711 | */ |
| 712 | */ |
712 | |
| 713 | 713 | /** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI) |
|
| 714 | /** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI) |
714 | * @{ |
| 715 | * @{ |
715 | */ |
| 716 | */ |
716 | #define LL_TIM_TIM11_TI1_RMP TIM_OR_RMP_MASK /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */ |
| 717 | #define LL_TIM_TIM11_TI1_RMP TIM_OR_RMP_MASK /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */ |
717 | #define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to RI */ |
| 718 | #define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to RI */ |
718 | /** |
| 719 | /** |
719 | * @} |
| 720 | * @} |
720 | */ |
| 721 | */ |
721 | |
| 722 | 722 | /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap |
|
| 723 | /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap |
723 | * @{ |
| 724 | * @{ |
724 | */ |
| 725 | */ |
725 | #define LL_TIM_TIM9_TI1_RMP_GPIO TIM9_OR_RMP_MASK /*!< TIM9 channel1 is connected to GPIO */ |
| 726 | #define LL_TIM_TIM9_TI1_RMP_GPIO TIM9_OR_RMP_MASK /*!< TIM9 channel1 is connected to GPIO */ |
726 | #define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to LSE internal clock */ |
| 727 | #define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to LSE internal clock */ |
727 | #define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */ |
| 728 | #define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */ |
728 | #define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */ |
| 729 | #define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */ |
729 | /** |
| 730 | /** |
730 | * @} |
| 731 | * @} |
731 | */ |
| 732 | */ |
732 | |
| 733 | 733 | /** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap |
|
| 734 | /** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap |
734 | * @{ |
| 735 | * @{ |
735 | */ |
| 736 | */ |
736 | #define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO TIM9_OR_RMP_MASK /*!< TIM9 channel1 is connected to TIM3 TGO signal */ |
| 737 | #define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO TIM9_OR_RMP_MASK /*!< TIM9 channel1 is connected to TIM3 TGO signal */ |
737 | #define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to touch sensing I/O */ |
| 738 | #define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to touch sensing I/O */ |
738 | /** |
| 739 | /** |
739 | * @} |
| 740 | * @} |
740 | */ |
| 741 | */ |
741 | |
| 742 | 742 | /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap |
|
| 743 | /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap |
743 | * @{ |
| 744 | * @{ |
744 | */ |
| 745 | */ |
745 | #define LL_TIM_TIM2_TIR1_RMP_TIM10_OC TIM9_OR_RMP_MASK /*!< TIM2 ITR1 input is connected to TIM10 OC*/ |
| 746 | #define LL_TIM_TIM2_TIR1_RMP_TIM10_OC TIM9_OR_RMP_MASK /*!< TIM2 ITR1 input is connected to TIM10 OC*/ |
746 | #define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM2 ITR1 input is connected to TIM5 TGO */ |
| 747 | #define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM2 ITR1 input is connected to TIM5 TGO */ |
747 | /** |
| 748 | /** |
748 | * @} |
| 749 | * @} |
749 | */ |
| 750 | */ |
750 | |
| 751 | 751 | /** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap |
|
| 752 | /** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap |
752 | * @{ |
| 753 | * @{ |
753 | */ |
| 754 | */ |
754 | #define LL_TIM_TIM3_TIR2_RMP_TIM11_OC TIM9_OR_RMP_MASK /*!< TIM3 ITR2 input is connected to TIM11 OC */ |
| 755 | #define LL_TIM_TIM3_TIR2_RMP_TIM11_OC TIM9_OR_RMP_MASK /*!< TIM3 ITR2 input is connected to TIM11 OC */ |
755 | #define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK) /*!< TIM3 ITR2 input is connected to TIM5 TGO */ |
| 756 | #define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK) /*!< TIM3 ITR2 input is connected to TIM5 TGO */ |
756 | /** |
| 757 | /** |
757 | * @} |
| 758 | * @} |
758 | */ |
| 759 | */ |
759 | |
| 760 | 760 | ||
| 761 | 761 | /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection |
|
| 762 | /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection |
762 | * @{ |
| 763 | * @{ |
763 | */ |
| 764 | */ |
764 | #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */ |
| 765 | #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */ |
765 | #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ |
| 766 | #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ |
766 | /** |
| 767 | /** |
767 | * @} |
| 768 | * @} |
768 | */ |
| 769 | */ |
769 | |
| 770 | 770 | ||
| 771 | /** |
771 | /** |
| 772 | * @} |
772 | * @} |
| 773 | */ |
773 | */ |
| 774 | 774 | ||
| 775 | /* Exported macro ------------------------------------------------------------*/ |
775 | /* Exported macro ------------------------------------------------------------*/ |
| 776 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
776 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
| 777 | * @{ |
777 | * @{ |
| 778 | */ |
778 | */ |
| 779 | 779 | ||
| 780 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
780 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
| 781 | * @{ |
781 | * @{ |
| 782 | */ |
782 | */ |
| 783 | /** |
783 | /** |
| 784 | * @brief Write a value in TIM register. |
784 | * @brief Write a value in TIM register. |
| 785 | * @param __INSTANCE__ TIM Instance |
785 | * @param __INSTANCE__ TIM Instance |
| 786 | * @param __REG__ Register to be written |
786 | * @param __REG__ Register to be written |
| 787 | * @param __VALUE__ Value to be written in the register |
787 | * @param __VALUE__ Value to be written in the register |
| 788 | * @retval None |
788 | * @retval None |
| 789 | */ |
789 | */ |
| 790 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) |
790 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) |
| 791 | 791 | ||
| 792 | /** |
792 | /** |
| 793 | * @brief Read a value in TIM register. |
793 | * @brief Read a value in TIM register. |
| 794 | * @param __INSTANCE__ TIM Instance |
794 | * @param __INSTANCE__ TIM Instance |
| 795 | * @param __REG__ Register to be read |
795 | * @param __REG__ Register to be read |
| 796 | * @retval Register value |
796 | * @retval Register value |
| 797 | */ |
797 | */ |
| 798 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) |
798 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) |
| 799 | /** |
799 | /** |
| 800 | * @} |
800 | * @} |
| 801 | */ |
801 | */ |
| 802 | 802 | ||
| 803 | /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros |
803 | /** |
| 804 | * @{ |
804 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
| 805 | */ |
805 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
| 806 | 806 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
|
| 807 | /** |
807 | * @param __CNTCLK__ counter clock frequency (in Hz) |
| 808 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
808 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
| 809 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
809 | */ |
| 810 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
810 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
| 811 | * @param __CNTCLK__ counter clock frequency (in Hz) |
811 | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) |
| 812 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
812 | |
| 813 | */ |
813 | /** |
| 814 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
814 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
| 815 | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) |
815 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
| 816 | 816 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
|
| 817 | /** |
817 | * @param __PSC__ prescaler |
| 818 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
818 | * @param __FREQ__ output signal frequency (in Hz) |
| 819 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
819 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
| 820 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
820 | */ |
| 821 | * @param __PSC__ prescaler |
821 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
| 822 | * @param __FREQ__ output signal frequency (in Hz) |
822 | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) |
| 823 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
823 | |
| 824 | */ |
824 | /** |
| 825 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
825 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare |
| 826 | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) |
826 | * active/inactive delay. |
| 827 | 827 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
|
| 828 | /** |
828 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| 829 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare |
829 | * @param __PSC__ prescaler |
| 830 | * active/inactive delay. |
830 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
| 831 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
831 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
| 832 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
832 | */ |
| 833 | * @param __PSC__ prescaler |
833 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
| 834 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
834 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
| 835 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
835 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
| 836 | */ |
836 | |
| 837 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
837 | /** |
| 838 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
838 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration |
| 839 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
839 | * (when the timer operates in one pulse mode). |
| 840 | 840 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
|
| 841 | /** |
841 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| 842 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration |
842 | * @param __PSC__ prescaler |
| 843 | * (when the timer operates in one pulse mode). |
843 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
| 844 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
844 | * @param __PULSE__ pulse duration (in us) |
| 845 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
845 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
| 846 | * @param __PSC__ prescaler |
846 | */ |
| 847 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
847 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
| 848 | * @param __PULSE__ pulse duration (in us) |
848 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
| 849 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
849 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
| 850 | */ |
850 | |
| 851 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
851 | /** |
| 852 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
852 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
| 853 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
853 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
| 854 | 854 | * @param __ICPSC__ This parameter can be one of the following values: |
|
| 855 | /** |
855 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| 856 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
856 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| 857 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
857 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| 858 | * @param __ICPSC__ This parameter can be one of the following values: |
858 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| 859 | * @arg @ref LL_TIM_ICPSC_DIV1 |
859 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
| 860 | * @arg @ref LL_TIM_ICPSC_DIV2 |
860 | */ |
| 861 | * @arg @ref LL_TIM_ICPSC_DIV4 |
861 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
| 862 | * @arg @ref LL_TIM_ICPSC_DIV8 |
862 | ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
| 863 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
863 | |
| 864 | */ |
864 | |
| 865 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
865 | /** |
| 866 | ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
866 | * @} |
| 867 | 867 | */ |
|
| 868 | 868 | ||
| 869 | /** |
869 | /* Exported functions --------------------------------------------------------*/ |
| 870 | * @} |
870 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
| 871 | */ |
871 | * @{ |
| 872 | 872 | */ |
|
| 873 | 873 | ||
| 874 | /** |
874 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
| 875 | * @} |
875 | * @{ |
| 876 | */ |
876 | */ |
| 877 | 877 | /** |
|
| 878 | /* Exported functions --------------------------------------------------------*/ |
878 | * @brief Enable timer counter. |
| 879 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
879 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
| 880 | * @{ |
880 | * @param TIMx Timer instance |
| 881 | */ |
881 | * @retval None |
| 882 | 882 | */ |
|
| 883 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
883 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
| 884 | * @{ |
884 | { |
| 885 | */ |
885 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
| 886 | /** |
886 | } |
| 887 | * @brief Enable timer counter. |
887 | |
| 888 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
888 | /** |
| 889 | * @param TIMx Timer instance |
889 | * @brief Disable timer counter. |
| 890 | * @retval None |
890 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
| 891 | */ |
891 | * @param TIMx Timer instance |
| 892 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
892 | * @retval None |
| 893 | { |
893 | */ |
| 894 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
894 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
| 895 | } |
895 | { |
| 896 | 896 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
|
| 897 | /** |
897 | } |
| 898 | * @brief Disable timer counter. |
898 | |
| 899 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
899 | /** |
| 900 | * @param TIMx Timer instance |
900 | * @brief Indicates whether the timer counter is enabled. |
| 901 | * @retval None |
901 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
| 902 | */ |
902 | * @param TIMx Timer instance |
| 903 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
903 | * @retval State of bit (1 or 0). |
| 904 | { |
904 | */ |
| 905 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
905 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) |
| 906 | } |
906 | { |
| 907 | 907 | return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); |
|
| 908 | /** |
908 | } |
| 909 | * @brief Indicates whether the timer counter is enabled. |
909 | |
| 910 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
910 | /** |
| 911 | * @param TIMx Timer instance |
911 | * @brief Enable update event generation. |
| 912 | * @retval State of bit (1 or 0). |
912 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
| 913 | */ |
913 | * @param TIMx Timer instance |
| 914 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) |
914 | * @retval None |
| 915 | { |
915 | */ |
| 916 | return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); |
916 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
| 917 | } |
917 | { |
| 918 | 918 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
|
| 919 | /** |
919 | } |
| 920 | * @brief Enable update event generation. |
920 | |
| 921 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
921 | /** |
| 922 | * @param TIMx Timer instance |
922 | * @brief Disable update event generation. |
| 923 | * @retval None |
923 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
| 924 | */ |
924 | * @param TIMx Timer instance |
| 925 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
925 | * @retval None |
| 926 | { |
926 | */ |
| 927 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
927 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
| 928 | } |
928 | { |
| 929 | 929 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
|
| 930 | /** |
930 | } |
| 931 | * @brief Disable update event generation. |
931 | |
| 932 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
932 | /** |
| 933 | * @param TIMx Timer instance |
933 | * @brief Indicates whether update event generation is enabled. |
| 934 | * @retval None |
934 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
| 935 | */ |
935 | * @param TIMx Timer instance |
| 936 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
936 | * @retval Inverted state of bit (0 or 1). |
| 937 | { |
937 | */ |
| 938 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
938 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) |
| 939 | } |
939 | { |
| 940 | 940 | return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); |
|
| 941 | /** |
941 | } |
| 942 | * @brief Indicates whether update event generation is enabled. |
942 | |
| 943 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
943 | /** |
| 944 | * @param TIMx Timer instance |
944 | * @brief Set update event source |
| 945 | * @retval Inverted state of bit (0 or 1). |
945 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
| 946 | */ |
946 | * generate an update interrupt or DMA request if enabled: |
| 947 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) |
947 | * - Counter overflow/underflow |
| 948 | { |
948 | * - Setting the UG bit |
| 949 | return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); |
949 | * - Update generation through the slave mode controller |
| 950 | } |
950 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
| 951 | 951 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
|
| 952 | /** |
952 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
| 953 | * @brief Set update event source |
953 | * @param TIMx Timer instance |
| 954 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
954 | * @param UpdateSource This parameter can be one of the following values: |
| 955 | * generate an update interrupt or DMA request if enabled: |
955 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
| 956 | * - Counter overflow/underflow |
956 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
| 957 | * - Setting the UG bit |
957 | * @retval None |
| 958 | * - Update generation through the slave mode controller |
958 | */ |
| 959 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
959 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
| 960 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
960 | { |
| 961 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
961 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
| 962 | * @param TIMx Timer instance |
962 | } |
| 963 | * @param UpdateSource This parameter can be one of the following values: |
963 | |
| 964 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
964 | /** |
| 965 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
965 | * @brief Get actual event update source |
| 966 | * @retval None |
966 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
| 967 | */ |
967 | * @param TIMx Timer instance |
| 968 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
968 | * @retval Returned value can be one of the following values: |
| 969 | { |
969 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
| 970 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
970 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
| 971 | } |
971 | */ |
| 972 | 972 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) |
|
| 973 | /** |
973 | { |
| 974 | * @brief Get actual event update source |
974 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
| 975 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
975 | } |
| 976 | * @param TIMx Timer instance |
976 | |
| 977 | * @retval Returned value can be one of the following values: |
977 | /** |
| 978 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
978 | * @brief Set one pulse mode (one shot v.s. repetitive). |
| 979 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
979 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
| 980 | */ |
980 | * @param TIMx Timer instance |
| 981 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) |
981 | * @param OnePulseMode This parameter can be one of the following values: |
| 982 | { |
982 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
| 983 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
983 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
| 984 | } |
984 | * @retval None |
| 985 | 985 | */ |
|
| 986 | /** |
986 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
| 987 | * @brief Set one pulse mode (one shot v.s. repetitive). |
987 | { |
| 988 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
988 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
| 989 | * @param TIMx Timer instance |
989 | } |
| 990 | * @param OnePulseMode This parameter can be one of the following values: |
990 | |
| 991 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
991 | /** |
| 992 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
992 | * @brief Get actual one pulse mode. |
| 993 | * @retval None |
993 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
| 994 | */ |
994 | * @param TIMx Timer instance |
| 995 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
995 | * @retval Returned value can be one of the following values: |
| 996 | { |
996 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
| 997 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
997 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
| 998 | } |
998 | */ |
| 999 | 999 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) |
|
| 1000 | /** |
1000 | { |
| 1001 | * @brief Get actual one pulse mode. |
1001 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
| 1002 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
1002 | } |
| 1003 | * @param TIMx Timer instance |
1003 | |
| 1004 | * @retval Returned value can be one of the following values: |
1004 | /** |
| 1005 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
1005 | * @brief Set the timer counter counting mode. |
| 1006 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
1006 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
| 1007 | */ |
1007 | * check whether or not the counter mode selection feature is supported |
| 1008 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) |
1008 | * by a timer instance. |
| 1009 | { |
1009 | * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| 1010 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
1010 | * requires a timer reset to avoid unexpected direction |
| 1011 | } |
1011 | * due to DIR bit readonly in center aligned mode. |
| 1012 | 1012 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
|
| 1013 | /** |
1013 | * CR1 CMS LL_TIM_SetCounterMode |
| 1014 | * @brief Set the timer counter counting mode. |
1014 | * @param TIMx Timer instance |
| 1015 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
1015 | * @param CounterMode This parameter can be one of the following values: |
| 1016 | * check whether or not the counter mode selection feature is supported |
1016 | * @arg @ref LL_TIM_COUNTERMODE_UP |
| 1017 | * by a timer instance. |
1017 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
| 1018 | * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
1018 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
| 1019 | * requires a timer reset to avoid unexpected direction |
1019 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
| 1020 | * due to DIR bit readonly in center aligned mode. |
1020 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
| 1021 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
1021 | * @retval None |
| 1022 | * CR1 CMS LL_TIM_SetCounterMode |
1022 | */ |
| 1023 | * @param TIMx Timer instance |
1023 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
| 1024 | * @param CounterMode This parameter can be one of the following values: |
1024 | { |
| 1025 | * @arg @ref LL_TIM_COUNTERMODE_UP |
1025 | MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); |
| 1026 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
1026 | } |
| 1027 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
1027 | |
| 1028 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
1028 | /** |
| 1029 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
1029 | * @brief Get actual counter mode. |
| 1030 | * @retval None |
1030 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
| 1031 | */ |
1031 | * check whether or not the counter mode selection feature is supported |
| 1032 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
1032 | * by a timer instance. |
| 1033 | { |
1033 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
| 1034 | MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); |
1034 | * CR1 CMS LL_TIM_GetCounterMode |
| 1035 | } |
1035 | * @param TIMx Timer instance |
| 1036 | 1036 | * @retval Returned value can be one of the following values: |
|
| 1037 | /** |
1037 | * @arg @ref LL_TIM_COUNTERMODE_UP |
| 1038 | * @brief Get actual counter mode. |
1038 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
| 1039 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
1039 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
| 1040 | * check whether or not the counter mode selection feature is supported |
1040 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
| 1041 | * by a timer instance. |
1041 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
| 1042 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
1042 | */ |
| 1043 | * CR1 CMS LL_TIM_GetCounterMode |
1043 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) |
| 1044 | * @param TIMx Timer instance |
1044 | { |
| 1045 | * @retval Returned value can be one of the following values: |
1045 | uint32_t counter_mode; |
| 1046 | * @arg @ref LL_TIM_COUNTERMODE_UP |
1046 | |
| 1047 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
1047 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); |
| 1048 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
1048 | |
| 1049 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
1049 | if (counter_mode == 0U) |
| 1050 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
1050 | { |
| 1051 | */ |
1051 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
| 1052 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) |
1052 | } |
| 1053 | { |
1053 | |
| 1054 | uint32_t counter_mode; |
1054 | return counter_mode; |
| 1055 | 1055 | } |
|
| 1056 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); |
1056 | |
| 1057 | 1057 | /** |
|
| 1058 | if (counter_mode == 0U) |
1058 | * @brief Enable auto-reload (ARR) preload. |
| 1059 | { |
1059 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
| 1060 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
1060 | * @param TIMx Timer instance |
| 1061 | } |
1061 | * @retval None |
| 1062 | 1062 | */ |
|
| 1063 | return counter_mode; |
1063 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
| 1064 | } |
1064 | { |
| 1065 | 1065 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
|
| 1066 | /** |
1066 | } |
| 1067 | * @brief Enable auto-reload (ARR) preload. |
1067 | |
| 1068 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
1068 | /** |
| 1069 | * @param TIMx Timer instance |
1069 | * @brief Disable auto-reload (ARR) preload. |
| 1070 | * @retval None |
1070 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
| 1071 | */ |
1071 | * @param TIMx Timer instance |
| 1072 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
1072 | * @retval None |
| 1073 | { |
1073 | */ |
| 1074 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
1074 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
| 1075 | } |
1075 | { |
| 1076 | 1076 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
|
| 1077 | /** |
1077 | } |
| 1078 | * @brief Disable auto-reload (ARR) preload. |
1078 | |
| 1079 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
1079 | /** |
| 1080 | * @param TIMx Timer instance |
1080 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
| 1081 | * @retval None |
1081 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
| 1082 | */ |
1082 | * @param TIMx Timer instance |
| 1083 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
1083 | * @retval State of bit (1 or 0). |
| 1084 | { |
1084 | */ |
| 1085 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
1085 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) |
| 1086 | } |
1086 | { |
| 1087 | 1087 | return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); |
|
| 1088 | /** |
1088 | } |
| 1089 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
1089 | |
| 1090 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
1090 | /** |
| 1091 | * @param TIMx Timer instance |
1091 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators |
| 1092 | * @retval State of bit (1 or 0). |
1092 | * (when supported) and the digital filters. |
| 1093 | */ |
1093 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
| 1094 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) |
1094 | * whether or not the clock division feature is supported by the timer |
| 1095 | { |
1095 | * instance. |
| 1096 | return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); |
1096 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
| 1097 | } |
1097 | * @param TIMx Timer instance |
| 1098 | 1098 | * @param ClockDivision This parameter can be one of the following values: |
|
| 1099 | /** |
1099 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| 1100 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators |
1100 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| 1101 | * (when supported) and the digital filters. |
1101 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| 1102 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
1102 | * @retval None |
| 1103 | * whether or not the clock division feature is supported by the timer |
1103 | */ |
| 1104 | * instance. |
1104 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
| 1105 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
1105 | { |
| 1106 | * @param TIMx Timer instance |
1106 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
| 1107 | * @param ClockDivision This parameter can be one of the following values: |
1107 | } |
| 1108 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
1108 | |
| 1109 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
1109 | /** |
| 1110 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
1110 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time |
| 1111 | * @retval None |
1111 | * generators (when supported) and the digital filters. |
| 1112 | */ |
1112 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
| 1113 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
1113 | * whether or not the clock division feature is supported by the timer |
| 1114 | { |
1114 | * instance. |
| 1115 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
1115 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
| 1116 | } |
1116 | * @param TIMx Timer instance |
| 1117 | 1117 | * @retval Returned value can be one of the following values: |
|
| 1118 | /** |
1118 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| 1119 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time |
1119 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| 1120 | * generators (when supported) and the digital filters. |
1120 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| 1121 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
1121 | */ |
| 1122 | * whether or not the clock division feature is supported by the timer |
1122 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) |
| 1123 | * instance. |
1123 | { |
| 1124 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
1124 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
| 1125 | * @param TIMx Timer instance |
1125 | } |
| 1126 | * @retval Returned value can be one of the following values: |
1126 | |
| 1127 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
1127 | /** |
| 1128 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
1128 | * @brief Set the counter value. |
| 1129 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
1129 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1130 | */ |
1130 | * whether or not a timer instance supports a 32 bits counter. |
| 1131 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) |
1131 | * @rmtoll CNT CNT LL_TIM_SetCounter |
| 1132 | { |
1132 | * @param TIMx Timer instance |
| 1133 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
1133 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
| 1134 | } |
1134 | * @retval None |
| 1135 | 1135 | */ |
|
| 1136 | /** |
1136 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
| 1137 | * @brief Set the counter value. |
1137 | { |
| 1138 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1138 | WRITE_REG(TIMx->CNT, Counter); |
| 1139 | * whether or not a timer instance supports a 32 bits counter. |
1139 | } |
| 1140 | * @rmtoll CNT CNT LL_TIM_SetCounter |
1140 | |
| 1141 | * @param TIMx Timer instance |
1141 | /** |
| 1142 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
1142 | * @brief Get the counter value. |
| 1143 | * @retval None |
1143 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1144 | */ |
1144 | * whether or not a timer instance supports a 32 bits counter. |
| 1145 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
1145 | * @rmtoll CNT CNT LL_TIM_GetCounter |
| 1146 | { |
1146 | * @param TIMx Timer instance |
| 1147 | WRITE_REG(TIMx->CNT, Counter); |
1147 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
| 1148 | } |
1148 | */ |
| 1149 | 1149 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) |
|
| 1150 | /** |
1150 | { |
| 1151 | * @brief Get the counter value. |
1151 | return (uint32_t)(READ_REG(TIMx->CNT)); |
| 1152 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1152 | } |
| 1153 | * whether or not a timer instance supports a 32 bits counter. |
1153 | |
| 1154 | * @rmtoll CNT CNT LL_TIM_GetCounter |
1154 | /** |
| 1155 | * @param TIMx Timer instance |
1155 | * @brief Get the current direction of the counter |
| 1156 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
1156 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
| 1157 | */ |
1157 | * @param TIMx Timer instance |
| 1158 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) |
1158 | * @retval Returned value can be one of the following values: |
| 1159 | { |
1159 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
| 1160 | return (uint32_t)(READ_REG(TIMx->CNT)); |
1160 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
| 1161 | } |
1161 | */ |
| 1162 | 1162 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) |
|
| 1163 | /** |
1163 | { |
| 1164 | * @brief Get the current direction of the counter |
1164 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
| 1165 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
1165 | } |
| 1166 | * @param TIMx Timer instance |
1166 | |
| 1167 | * @retval Returned value can be one of the following values: |
1167 | /** |
| 1168 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
1168 | * @brief Set the prescaler value. |
| 1169 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
1169 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
| 1170 | */ |
1170 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
| 1171 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) |
1171 | * prescaler ratio is taken into account at the next update event. |
| 1172 | { |
1172 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
| 1173 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
1173 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
| 1174 | } |
1174 | * @param TIMx Timer instance |
| 1175 | 1175 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
|
| 1176 | /** |
1176 | * @retval None |
| 1177 | * @brief Set the prescaler value. |
1177 | */ |
| 1178 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
1178 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
| 1179 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
1179 | { |
| 1180 | * prescaler ratio is taken into account at the next update event. |
1180 | WRITE_REG(TIMx->PSC, Prescaler); |
| 1181 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
1181 | } |
| 1182 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
1182 | |
| 1183 | * @param TIMx Timer instance |
1183 | /** |
| 1184 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
1184 | * @brief Get the prescaler value. |
| 1185 | * @retval None |
1185 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
| 1186 | */ |
1186 | * @param TIMx Timer instance |
| 1187 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
1187 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
| 1188 | { |
1188 | */ |
| 1189 | WRITE_REG(TIMx->PSC, Prescaler); |
1189 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) |
| 1190 | } |
1190 | { |
| 1191 | 1191 | return (uint32_t)(READ_REG(TIMx->PSC)); |
|
| 1192 | /** |
1192 | } |
| 1193 | * @brief Get the prescaler value. |
1193 | |
| 1194 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
1194 | /** |
| 1195 | * @param TIMx Timer instance |
1195 | * @brief Set the auto-reload value. |
| 1196 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
1196 | * @note The counter is blocked while the auto-reload value is null. |
| 1197 | */ |
1197 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1198 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) |
1198 | * whether or not a timer instance supports a 32 bits counter. |
| 1199 | { |
1199 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
| 1200 | return (uint32_t)(READ_REG(TIMx->PSC)); |
1200 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
| 1201 | } |
1201 | * @param TIMx Timer instance |
| 1202 | 1202 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
|
| 1203 | /** |
1203 | * @retval None |
| 1204 | * @brief Set the auto-reload value. |
1204 | */ |
| 1205 | * @note The counter is blocked while the auto-reload value is null. |
1205 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
| 1206 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1206 | { |
| 1207 | * whether or not a timer instance supports a 32 bits counter. |
1207 | WRITE_REG(TIMx->ARR, AutoReload); |
| 1208 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
1208 | } |
| 1209 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
1209 | |
| 1210 | * @param TIMx Timer instance |
1210 | /** |
| 1211 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
1211 | * @brief Get the auto-reload value. |
| 1212 | * @retval None |
1212 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
| 1213 | */ |
1213 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1214 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
1214 | * whether or not a timer instance supports a 32 bits counter. |
| 1215 | { |
1215 | * @param TIMx Timer instance |
| 1216 | WRITE_REG(TIMx->ARR, AutoReload); |
1216 | * @retval Auto-reload value |
| 1217 | } |
1217 | */ |
| 1218 | 1218 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) |
|
| 1219 | /** |
1219 | { |
| 1220 | * @brief Get the auto-reload value. |
1220 | return (uint32_t)(READ_REG(TIMx->ARR)); |
| 1221 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
1221 | } |
| 1222 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1222 | |
| 1223 | * whether or not a timer instance supports a 32 bits counter. |
1223 | /** |
| 1224 | * @param TIMx Timer instance |
1224 | * @} |
| 1225 | * @retval Auto-reload value |
1225 | */ |
| 1226 | */ |
1226 | |
| 1227 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) |
1227 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
| 1228 | { |
1228 | * @{ |
| 1229 | return (uint32_t)(READ_REG(TIMx->ARR)); |
1229 | */ |
| 1230 | } |
1230 | /** |
| 1231 | 1231 | * @brief Set the trigger of the capture/compare DMA request. |
|
| 1232 | /** |
1232 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
| 1233 | * @} |
1233 | * @param TIMx Timer instance |
| 1234 | */ |
1234 | * @param DMAReqTrigger This parameter can be one of the following values: |
| 1235 | 1235 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
|
| 1236 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
1236 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
| 1237 | * @{ |
1237 | * @retval None |
| 1238 | */ |
1238 | */ |
| 1239 | /** |
1239 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
| 1240 | * @brief Set the trigger of the capture/compare DMA request. |
1240 | { |
| 1241 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
1241 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
| 1242 | * @param TIMx Timer instance |
1242 | } |
| 1243 | * @param DMAReqTrigger This parameter can be one of the following values: |
1243 | |
| 1244 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
1244 | /** |
| 1245 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
1245 | * @brief Get actual trigger of the capture/compare DMA request. |
| 1246 | * @retval None |
1246 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
| 1247 | */ |
1247 | * @param TIMx Timer instance |
| 1248 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
1248 | * @retval Returned value can be one of the following values: |
| 1249 | { |
1249 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
| 1250 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
1250 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
| 1251 | } |
1251 | */ |
| 1252 | 1252 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) |
|
| 1253 | /** |
1253 | { |
| 1254 | * @brief Get actual trigger of the capture/compare DMA request. |
1254 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
| 1255 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
1255 | } |
| 1256 | * @param TIMx Timer instance |
1256 | |
| 1257 | * @retval Returned value can be one of the following values: |
1257 | /** |
| 1258 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
1258 | * @brief Enable capture/compare channels. |
| 1259 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
1259 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
| 1260 | */ |
1260 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
| 1261 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) |
1261 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
| 1262 | { |
1262 | * CCER CC4E LL_TIM_CC_EnableChannel |
| 1263 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
1263 | * @param TIMx Timer instance |
| 1264 | } |
1264 | * @param Channels This parameter can be a combination of the following values: |
| 1265 | 1265 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1266 | /** |
1266 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1267 | * @brief Enable capture/compare channels. |
1267 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1268 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
1268 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1269 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
1269 | * @retval None |
| 1270 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
1270 | */ |
| 1271 | * CCER CC4E LL_TIM_CC_EnableChannel |
1271 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| 1272 | * @param TIMx Timer instance |
1272 | { |
| 1273 | * @param Channels This parameter can be a combination of the following values: |
1273 | SET_BIT(TIMx->CCER, Channels); |
| 1274 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1274 | } |
| 1275 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1275 | |
| 1276 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1276 | /** |
| 1277 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1277 | * @brief Disable capture/compare channels. |
| 1278 | * @retval None |
1278 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
| 1279 | */ |
1279 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
| 1280 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
1280 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
| 1281 | { |
1281 | * CCER CC4E LL_TIM_CC_DisableChannel |
| 1282 | SET_BIT(TIMx->CCER, Channels); |
1282 | * @param TIMx Timer instance |
| 1283 | } |
1283 | * @param Channels This parameter can be a combination of the following values: |
| 1284 | 1284 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1285 | /** |
1285 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1286 | * @brief Disable capture/compare channels. |
1286 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1287 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
1287 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1288 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
1288 | * @retval None |
| 1289 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
1289 | */ |
| 1290 | * CCER CC4E LL_TIM_CC_DisableChannel |
1290 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| 1291 | * @param TIMx Timer instance |
1291 | { |
| 1292 | * @param Channels This parameter can be a combination of the following values: |
1292 | CLEAR_BIT(TIMx->CCER, Channels); |
| 1293 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1293 | } |
| 1294 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1294 | |
| 1295 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1295 | /** |
| 1296 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1296 | * @brief Indicate whether channel(s) is(are) enabled. |
| 1297 | * @retval None |
1297 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
| 1298 | */ |
1298 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
| 1299 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
1299 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
| 1300 | { |
1300 | * CCER CC4E LL_TIM_CC_IsEnabledChannel |
| 1301 | CLEAR_BIT(TIMx->CCER, Channels); |
1301 | * @param TIMx Timer instance |
| 1302 | } |
1302 | * @param Channels This parameter can be a combination of the following values: |
| 1303 | 1303 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1304 | /** |
1304 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1305 | * @brief Indicate whether channel(s) is(are) enabled. |
1305 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1306 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
1306 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1307 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
1307 | * @retval State of bit (1 or 0). |
| 1308 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
1308 | */ |
| 1309 | * CCER CC4E LL_TIM_CC_IsEnabledChannel |
1309 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) |
| 1310 | * @param TIMx Timer instance |
1310 | { |
| 1311 | * @param Channels This parameter can be a combination of the following values: |
1311 | return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); |
| 1312 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1312 | } |
| 1313 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1313 | |
| 1314 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1314 | /** |
| 1315 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1315 | * @} |
| 1316 | * @retval State of bit (1 or 0). |
1316 | */ |
| 1317 | */ |
1317 | |
| 1318 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
1318 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
| 1319 | { |
1319 | * @{ |
| 1320 | return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); |
1320 | */ |
| 1321 | } |
1321 | /** |
| 1322 | 1322 | * @brief Configure an output channel. |
|
| 1323 | /** |
1323 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
| 1324 | * @} |
1324 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
| 1325 | */ |
1325 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
| 1326 | 1326 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
|
| 1327 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
1327 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
| 1328 | * @{ |
1328 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
| 1329 | */ |
1329 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
| 1330 | /** |
1330 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
| 1331 | * @brief Configure an output channel. |
1331 | * @param TIMx Timer instance |
| 1332 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
1332 | * @param Channel This parameter can be one of the following values: |
| 1333 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
1333 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1334 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
1334 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1335 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
1335 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1336 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
1336 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1337 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
1337 | * @param Configuration This parameter must be a combination of all the following values: |
| 1338 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
1338 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
| 1339 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
1339 | * @retval None |
| 1340 | * @param TIMx Timer instance |
1340 | */ |
| 1341 | * @param Channel This parameter can be one of the following values: |
1341 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| 1342 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1342 | { |
| 1343 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1343 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1344 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1344 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1345 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1345 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
| 1346 | * @param Configuration This parameter must be a combination of all the following values: |
1346 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
| 1347 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
1347 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
| 1348 | * @retval None |
1348 | } |
| 1349 | */ |
1349 | |
| 1350 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
1350 | /** |
| 1351 | { |
1351 | * @brief Define the behavior of the output reference signal OCxREF from which |
| 1352 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1352 | * OCx and OCxN (when relevant) are derived. |
| 1353 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1353 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
| 1354 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
1354 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
| 1355 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
1355 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
| 1356 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
1356 | * CCMR2 OC4M LL_TIM_OC_SetMode |
| 1357 | } |
1357 | * @param TIMx Timer instance |
| 1358 | 1358 | * @param Channel This parameter can be one of the following values: |
|
| 1359 | /** |
1359 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1360 | * @brief Define the behavior of the output reference signal OCxREF from which |
1360 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1361 | * OCx and OCxN (when relevant) are derived. |
1361 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1362 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
1362 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1363 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
1363 | * @param Mode This parameter can be one of the following values: |
| 1364 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
1364 | * @arg @ref LL_TIM_OCMODE_FROZEN |
| 1365 | * CCMR2 OC4M LL_TIM_OC_SetMode |
1365 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
| 1366 | * @param TIMx Timer instance |
1366 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
| 1367 | * @param Channel This parameter can be one of the following values: |
1367 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
| 1368 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1368 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
| 1369 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1369 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
| 1370 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1370 | * @arg @ref LL_TIM_OCMODE_PWM1 |
| 1371 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1371 | * @arg @ref LL_TIM_OCMODE_PWM2 |
| 1372 | * @param Mode This parameter can be one of the following values: |
1372 | * @retval None |
| 1373 | * @arg @ref LL_TIM_OCMODE_FROZEN |
1373 | */ |
| 1374 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
1374 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
| 1375 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
1375 | { |
| 1376 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
1376 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1377 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
1377 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1378 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
1378 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
| 1379 | * @arg @ref LL_TIM_OCMODE_PWM1 |
1379 | } |
| 1380 | * @arg @ref LL_TIM_OCMODE_PWM2 |
1380 | |
| 1381 | * @retval None |
1381 | /** |
| 1382 | */ |
1382 | * @brief Get the output compare mode of an output channel. |
| 1383 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
1383 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
| 1384 | { |
1384 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
| 1385 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1385 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
| 1386 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1386 | * CCMR2 OC4M LL_TIM_OC_GetMode |
| 1387 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
1387 | * @param TIMx Timer instance |
| 1388 | } |
1388 | * @param Channel This parameter can be one of the following values: |
| 1389 | 1389 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1390 | /** |
1390 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1391 | * @brief Get the output compare mode of an output channel. |
1391 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1392 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
1392 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1393 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
1393 | * @retval Returned value can be one of the following values: |
| 1394 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
1394 | * @arg @ref LL_TIM_OCMODE_FROZEN |
| 1395 | * CCMR2 OC4M LL_TIM_OC_GetMode |
1395 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
| 1396 | * @param TIMx Timer instance |
1396 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
| 1397 | * @param Channel This parameter can be one of the following values: |
1397 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
| 1398 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1398 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
| 1399 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1399 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
| 1400 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1400 | * @arg @ref LL_TIM_OCMODE_PWM1 |
| 1401 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1401 | * @arg @ref LL_TIM_OCMODE_PWM2 |
| 1402 | * @retval Returned value can be one of the following values: |
1402 | */ |
| 1403 | * @arg @ref LL_TIM_OCMODE_FROZEN |
1403 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1404 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
1404 | { |
| 1405 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
1405 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1406 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
1406 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1407 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
1407 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
| 1408 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
1408 | } |
| 1409 | * @arg @ref LL_TIM_OCMODE_PWM1 |
1409 | |
| 1410 | * @arg @ref LL_TIM_OCMODE_PWM2 |
1410 | /** |
| 1411 | */ |
1411 | * @brief Set the polarity of an output channel. |
| 1412 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) |
1412 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
| 1413 | { |
1413 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
| 1414 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1414 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
| 1415 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1415 | * CCER CC4P LL_TIM_OC_SetPolarity |
| 1416 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
1416 | * @param TIMx Timer instance |
| 1417 | } |
1417 | * @param Channel This parameter can be one of the following values: |
| 1418 | 1418 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1419 | /** |
1419 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1420 | * @brief Set the polarity of an output channel. |
1420 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1421 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
1421 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1422 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
1422 | * @param Polarity This parameter can be one of the following values: |
| 1423 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
1423 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
| 1424 | * CCER CC4P LL_TIM_OC_SetPolarity |
1424 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
| 1425 | * @param TIMx Timer instance |
1425 | * @retval None |
| 1426 | * @param Channel This parameter can be one of the following values: |
1426 | */ |
| 1427 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1427 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
| 1428 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1428 | { |
| 1429 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1429 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1430 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1430 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
| 1431 | * @param Polarity This parameter can be one of the following values: |
1431 | } |
| 1432 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
1432 | |
| 1433 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
1433 | /** |
| 1434 | * @retval None |
1434 | * @brief Get the polarity of an output channel. |
| 1435 | */ |
1435 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
| 1436 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
1436 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
| 1437 | { |
1437 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
| 1438 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1438 | * CCER CC4P LL_TIM_OC_GetPolarity |
| 1439 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
1439 | * @param TIMx Timer instance |
| 1440 | } |
1440 | * @param Channel This parameter can be one of the following values: |
| 1441 | 1441 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1442 | /** |
1442 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1443 | * @brief Get the polarity of an output channel. |
1443 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1444 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
1444 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1445 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
1445 | * @retval Returned value can be one of the following values: |
| 1446 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
1446 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
| 1447 | * CCER CC4P LL_TIM_OC_GetPolarity |
1447 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
| 1448 | * @param TIMx Timer instance |
1448 | */ |
| 1449 | * @param Channel This parameter can be one of the following values: |
1449 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1450 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1450 | { |
| 1451 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1451 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1452 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1452 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
| 1453 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1453 | } |
| 1454 | * @retval Returned value can be one of the following values: |
1454 | |
| 1455 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
1455 | /** |
| 1456 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
1456 | * @brief Enable fast mode for the output channel. |
| 1457 | */ |
1457 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
| 1458 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
1458 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
| 1459 | { |
1459 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
| 1460 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1460 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
| 1461 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
1461 | * CCMR2 OC4FE LL_TIM_OC_EnableFast |
| 1462 | } |
1462 | * @param TIMx Timer instance |
| 1463 | 1463 | * @param Channel This parameter can be one of the following values: |
|
| 1464 | /** |
1464 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1465 | * @brief Enable fast mode for the output channel. |
1465 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1466 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
1466 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1467 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
1467 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1468 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
1468 | * @retval None |
| 1469 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
1469 | */ |
| 1470 | * CCMR2 OC4FE LL_TIM_OC_EnableFast |
1470 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1471 | * @param TIMx Timer instance |
1471 | { |
| 1472 | * @param Channel This parameter can be one of the following values: |
1472 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1473 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1473 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1474 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1474 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
| 1475 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1475 | |
| 1476 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1476 | } |
| 1477 | * @retval None |
1477 | |
| 1478 | */ |
1478 | /** |
| 1479 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
1479 | * @brief Disable fast mode for the output channel. |
| 1480 | { |
1480 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
| 1481 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1481 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
| 1482 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1482 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
| 1483 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
1483 | * CCMR2 OC4FE LL_TIM_OC_DisableFast |
| 1484 | 1484 | * @param TIMx Timer instance |
|
| 1485 | } |
1485 | * @param Channel This parameter can be one of the following values: |
| 1486 | 1486 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1487 | /** |
1487 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1488 | * @brief Disable fast mode for the output channel. |
1488 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1489 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
1489 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1490 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
1490 | * @retval None |
| 1491 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
1491 | */ |
| 1492 | * CCMR2 OC4FE LL_TIM_OC_DisableFast |
1492 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1493 | * @param TIMx Timer instance |
1493 | { |
| 1494 | * @param Channel This parameter can be one of the following values: |
1494 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1495 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1495 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1496 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1496 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
| 1497 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1497 | |
| 1498 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1498 | } |
| 1499 | * @retval None |
1499 | |
| 1500 | */ |
1500 | /** |
| 1501 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
1501 | * @brief Indicates whether fast mode is enabled for the output channel. |
| 1502 | { |
1502 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
| 1503 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1503 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
| 1504 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1504 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
| 1505 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
1505 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
| 1506 | 1506 | * @param TIMx Timer instance |
|
| 1507 | } |
1507 | * @param Channel This parameter can be one of the following values: |
| 1508 | 1508 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1509 | /** |
1509 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1510 | * @brief Indicates whether fast mode is enabled for the output channel. |
1510 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1511 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
1511 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1512 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
1512 | * @retval State of bit (1 or 0). |
| 1513 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
1513 | */ |
| 1514 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
1514 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1515 | * @param TIMx Timer instance |
1515 | { |
| 1516 | * @param Channel This parameter can be one of the following values: |
1516 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1517 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1517 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1518 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1518 | uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
| 1519 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1519 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
| 1520 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1520 | } |
| 1521 | * @retval State of bit (1 or 0). |
1521 | |
| 1522 | */ |
1522 | /** |
| 1523 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) |
1523 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
| 1524 | { |
1524 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
| 1525 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1525 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
| 1526 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1526 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
| 1527 | uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
1527 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload |
| 1528 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
1528 | * @param TIMx Timer instance |
| 1529 | } |
1529 | * @param Channel This parameter can be one of the following values: |
| 1530 | 1530 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1531 | /** |
1531 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1532 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
1532 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1533 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
1533 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1534 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
1534 | * @retval None |
| 1535 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
1535 | */ |
| 1536 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload |
1536 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1537 | * @param TIMx Timer instance |
1537 | { |
| 1538 | * @param Channel This parameter can be one of the following values: |
1538 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1539 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1539 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1540 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1540 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
| 1541 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1541 | } |
| 1542 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1542 | |
| 1543 | * @retval None |
1543 | /** |
| 1544 | */ |
1544 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
| 1545 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
1545 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
| 1546 | { |
1546 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
| 1547 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1547 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
| 1548 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1548 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload |
| 1549 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
1549 | * @param TIMx Timer instance |
| 1550 | } |
1550 | * @param Channel This parameter can be one of the following values: |
| 1551 | 1551 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1552 | /** |
1552 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1553 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
1553 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1554 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
1554 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1555 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
1555 | * @retval None |
| 1556 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
1556 | */ |
| 1557 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload |
1557 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1558 | * @param TIMx Timer instance |
1558 | { |
| 1559 | * @param Channel This parameter can be one of the following values: |
1559 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1560 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1560 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1561 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1561 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
| 1562 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1562 | } |
| 1563 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1563 | |
| 1564 | * @retval None |
1564 | /** |
| 1565 | */ |
1565 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
| 1566 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
1566 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
| 1567 | { |
1567 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
| 1568 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1568 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
| 1569 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1569 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
| 1570 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
1570 | * @param TIMx Timer instance |
| 1571 | } |
1571 | * @param Channel This parameter can be one of the following values: |
| 1572 | 1572 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1573 | /** |
1573 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1574 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
1574 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1575 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
1575 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1576 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
1576 | * @retval State of bit (1 or 0). |
| 1577 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
1577 | */ |
| 1578 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
1578 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1579 | * @param TIMx Timer instance |
1579 | { |
| 1580 | * @param Channel This parameter can be one of the following values: |
1580 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1581 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1581 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1582 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1582 | uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
| 1583 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1583 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
| 1584 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1584 | } |
| 1585 | * @retval State of bit (1 or 0). |
1585 | |
| 1586 | */ |
1586 | /** |
| 1587 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) |
1587 | * @brief Enable clearing the output channel on an external event. |
| 1588 | { |
1588 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
| 1589 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1589 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| 1590 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1590 | * or not a timer instance can clear the OCxREF signal on an external event. |
| 1591 | uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
1591 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
| 1592 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
1592 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
| 1593 | } |
1593 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
| 1594 | 1594 | * CCMR2 OC4CE LL_TIM_OC_EnableClear |
|
| 1595 | /** |
1595 | * @param TIMx Timer instance |
| 1596 | * @brief Enable clearing the output channel on an external event. |
1596 | * @param Channel This parameter can be one of the following values: |
| 1597 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
1597 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1598 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
1598 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1599 | * or not a timer instance can clear the OCxREF signal on an external event. |
1599 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1600 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
1600 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1601 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
1601 | * @retval None |
| 1602 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
1602 | */ |
| 1603 | * CCMR2 OC4CE LL_TIM_OC_EnableClear |
1603 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1604 | * @param TIMx Timer instance |
1604 | { |
| 1605 | * @param Channel This parameter can be one of the following values: |
1605 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1606 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1606 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1607 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1607 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
| 1608 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1608 | } |
| 1609 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1609 | |
| 1610 | * @retval None |
1610 | /** |
| 1611 | */ |
1611 | * @brief Disable clearing the output channel on an external event. |
| 1612 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
1612 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| 1613 | { |
1613 | * or not a timer instance can clear the OCxREF signal on an external event. |
| 1614 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1614 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
| 1615 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1615 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
| 1616 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
1616 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
| 1617 | } |
1617 | * CCMR2 OC4CE LL_TIM_OC_DisableClear |
| 1618 | 1618 | * @param TIMx Timer instance |
|
| 1619 | /** |
1619 | * @param Channel This parameter can be one of the following values: |
| 1620 | * @brief Disable clearing the output channel on an external event. |
1620 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1621 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
1621 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1622 | * or not a timer instance can clear the OCxREF signal on an external event. |
1622 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1623 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
1623 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1624 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
1624 | * @retval None |
| 1625 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
1625 | */ |
| 1626 | * CCMR2 OC4CE LL_TIM_OC_DisableClear |
1626 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1627 | * @param TIMx Timer instance |
1627 | { |
| 1628 | * @param Channel This parameter can be one of the following values: |
1628 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1629 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1629 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1630 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1630 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
| 1631 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1631 | } |
| 1632 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1632 | |
| 1633 | * @retval None |
1633 | /** |
| 1634 | */ |
1634 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
| 1635 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
1635 | * @note This function enables clearing the output channel on an external event. |
| 1636 | { |
1636 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
| 1637 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1637 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| 1638 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1638 | * or not a timer instance can clear the OCxREF signal on an external event. |
| 1639 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
1639 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
| 1640 | } |
1640 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
| 1641 | 1641 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
|
| 1642 | /** |
1642 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
| 1643 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
1643 | * @param TIMx Timer instance |
| 1644 | * @note This function enables clearing the output channel on an external event. |
1644 | * @param Channel This parameter can be one of the following values: |
| 1645 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
1645 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1646 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
1646 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1647 | * or not a timer instance can clear the OCxREF signal on an external event. |
1647 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1648 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
1648 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1649 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
1649 | * @retval State of bit (1 or 0). |
| 1650 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
1650 | */ |
| 1651 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
1651 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1652 | * @param TIMx Timer instance |
1652 | { |
| 1653 | * @param Channel This parameter can be one of the following values: |
1653 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1654 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1654 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1655 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1655 | uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
| 1656 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1656 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
| 1657 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1657 | } |
| 1658 | * @retval State of bit (1 or 0). |
1658 | |
| 1659 | */ |
1659 | /** |
| 1660 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) |
1660 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
| 1661 | { |
1661 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1662 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1662 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1663 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1663 | * whether or not a timer instance supports a 32 bits counter. |
| 1664 | uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
1664 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| 1665 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
1665 | * output channel 1 is supported by a timer instance. |
| 1666 | } |
1666 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
| 1667 | 1667 | * @param TIMx Timer instance |
|
| 1668 | /** |
1668 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 1669 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
1669 | * @retval None |
| 1670 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
1670 | */ |
| 1671 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1671 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 1672 | * whether or not a timer instance supports a 32 bits counter. |
1672 | { |
| 1673 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
1673 | WRITE_REG(TIMx->CCR1, CompareValue); |
| 1674 | * output channel 1 is supported by a timer instance. |
1674 | } |
| 1675 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
1675 | |
| 1676 | * @param TIMx Timer instance |
1676 | /** |
| 1677 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
1677 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
| 1678 | * @retval None |
1678 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1679 | */ |
1679 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1680 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
1680 | * whether or not a timer instance supports a 32 bits counter. |
| 1681 | { |
1681 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| 1682 | WRITE_REG(TIMx->CCR1, CompareValue); |
1682 | * output channel 2 is supported by a timer instance. |
| 1683 | } |
1683 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
| 1684 | 1684 | * @param TIMx Timer instance |
|
| 1685 | /** |
1685 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 1686 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
1686 | * @retval None |
| 1687 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
1687 | */ |
| 1688 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1688 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 1689 | * whether or not a timer instance supports a 32 bits counter. |
1689 | { |
| 1690 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
1690 | WRITE_REG(TIMx->CCR2, CompareValue); |
| 1691 | * output channel 2 is supported by a timer instance. |
1691 | } |
| 1692 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
1692 | |
| 1693 | * @param TIMx Timer instance |
1693 | /** |
| 1694 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
1694 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
| 1695 | * @retval None |
1695 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1696 | */ |
1696 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1697 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
1697 | * whether or not a timer instance supports a 32 bits counter. |
| 1698 | { |
1698 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| 1699 | WRITE_REG(TIMx->CCR2, CompareValue); |
1699 | * output channel is supported by a timer instance. |
| 1700 | } |
1700 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
| 1701 | 1701 | * @param TIMx Timer instance |
|
| 1702 | /** |
1702 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 1703 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
1703 | * @retval None |
| 1704 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
1704 | */ |
| 1705 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1705 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 1706 | * whether or not a timer instance supports a 32 bits counter. |
1706 | { |
| 1707 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
1707 | WRITE_REG(TIMx->CCR3, CompareValue); |
| 1708 | * output channel is supported by a timer instance. |
1708 | } |
| 1709 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
1709 | |
| 1710 | * @param TIMx Timer instance |
1710 | /** |
| 1711 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
1711 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
| 1712 | * @retval None |
1712 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1713 | */ |
1713 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1714 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
1714 | * whether or not a timer instance supports a 32 bits counter. |
| 1715 | { |
1715 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| 1716 | WRITE_REG(TIMx->CCR3, CompareValue); |
1716 | * output channel 4 is supported by a timer instance. |
| 1717 | } |
1717 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
| 1718 | 1718 | * @param TIMx Timer instance |
|
| 1719 | /** |
1719 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 1720 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
1720 | * @retval None |
| 1721 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
1721 | */ |
| 1722 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1722 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 1723 | * whether or not a timer instance supports a 32 bits counter. |
1723 | { |
| 1724 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
1724 | WRITE_REG(TIMx->CCR4, CompareValue); |
| 1725 | * output channel 4 is supported by a timer instance. |
1725 | } |
| 1726 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
1726 | |
| 1727 | * @param TIMx Timer instance |
1727 | /** |
| 1728 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
1728 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
| 1729 | * @retval None |
1729 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1730 | */ |
1730 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1731 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
1731 | * whether or not a timer instance supports a 32 bits counter. |
| 1732 | { |
1732 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| 1733 | WRITE_REG(TIMx->CCR4, CompareValue); |
1733 | * output channel 1 is supported by a timer instance. |
| 1734 | } |
1734 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
| 1735 | 1735 | * @param TIMx Timer instance |
|
| 1736 | /** |
1736 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 1737 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
1737 | */ |
| 1738 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
1738 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) |
| 1739 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1739 | { |
| 1740 | * whether or not a timer instance supports a 32 bits counter. |
1740 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
| 1741 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
1741 | } |
| 1742 | * output channel 1 is supported by a timer instance. |
1742 | |
| 1743 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
1743 | /** |
| 1744 | * @param TIMx Timer instance |
1744 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
| 1745 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
1745 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1746 | */ |
1746 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1747 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) |
1747 | * whether or not a timer instance supports a 32 bits counter. |
| 1748 | { |
1748 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| 1749 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
1749 | * output channel 2 is supported by a timer instance. |
| 1750 | } |
1750 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
| 1751 | 1751 | * @param TIMx Timer instance |
|
| 1752 | /** |
1752 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 1753 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
1753 | */ |
| 1754 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
1754 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) |
| 1755 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1755 | { |
| 1756 | * whether or not a timer instance supports a 32 bits counter. |
1756 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
| 1757 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
1757 | } |
| 1758 | * output channel 2 is supported by a timer instance. |
1758 | |
| 1759 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
1759 | /** |
| 1760 | * @param TIMx Timer instance |
1760 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
| 1761 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
1761 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1762 | */ |
1762 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1763 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) |
1763 | * whether or not a timer instance supports a 32 bits counter. |
| 1764 | { |
1764 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| 1765 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
1765 | * output channel 3 is supported by a timer instance. |
| 1766 | } |
1766 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
| 1767 | 1767 | * @param TIMx Timer instance |
|
| 1768 | /** |
1768 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 1769 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
1769 | */ |
| 1770 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
1770 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) |
| 1771 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1771 | { |
| 1772 | * whether or not a timer instance supports a 32 bits counter. |
1772 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
| 1773 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
1773 | } |
| 1774 | * output channel 3 is supported by a timer instance. |
1774 | |
| 1775 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
1775 | /** |
| 1776 | * @param TIMx Timer instance |
1776 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
| 1777 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
1777 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| 1778 | */ |
1778 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 1779 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) |
1779 | * whether or not a timer instance supports a 32 bits counter. |
| 1780 | { |
1780 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| 1781 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
1781 | * output channel 4 is supported by a timer instance. |
| 1782 | } |
1782 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
| 1783 | 1783 | * @param TIMx Timer instance |
|
| 1784 | /** |
1784 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 1785 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
1785 | */ |
| 1786 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
1786 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) |
| 1787 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
1787 | { |
| 1788 | * whether or not a timer instance supports a 32 bits counter. |
1788 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
| 1789 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
1789 | } |
| 1790 | * output channel 4 is supported by a timer instance. |
1790 | |
| 1791 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
1791 | /** |
| 1792 | * @param TIMx Timer instance |
1792 | * @} |
| 1793 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
1793 | */ |
| 1794 | */ |
1794 | |
| 1795 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) |
1795 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
| 1796 | { |
1796 | * @{ |
| 1797 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
1797 | */ |
| 1798 | } |
1798 | /** |
| 1799 | 1799 | * @brief Configure input channel. |
|
| 1800 | /** |
1800 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
| 1801 | * @} |
1801 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
| 1802 | */ |
1802 | * CCMR1 IC1F LL_TIM_IC_Config\n |
| 1803 | 1803 | * CCMR1 CC2S LL_TIM_IC_Config\n |
|
| 1804 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
1804 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
| 1805 | * @{ |
1805 | * CCMR1 IC2F LL_TIM_IC_Config\n |
| 1806 | */ |
1806 | * CCMR2 CC3S LL_TIM_IC_Config\n |
| 1807 | /** |
1807 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
| 1808 | * @brief Configure input channel. |
1808 | * CCMR2 IC3F LL_TIM_IC_Config\n |
| 1809 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
1809 | * CCMR2 CC4S LL_TIM_IC_Config\n |
| 1810 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
1810 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
| 1811 | * CCMR1 IC1F LL_TIM_IC_Config\n |
1811 | * CCMR2 IC4F LL_TIM_IC_Config\n |
| 1812 | * CCMR1 CC2S LL_TIM_IC_Config\n |
1812 | * CCER CC1P LL_TIM_IC_Config\n |
| 1813 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
1813 | * CCER CC1NP LL_TIM_IC_Config\n |
| 1814 | * CCMR1 IC2F LL_TIM_IC_Config\n |
1814 | * CCER CC2P LL_TIM_IC_Config\n |
| 1815 | * CCMR2 CC3S LL_TIM_IC_Config\n |
1815 | * CCER CC2NP LL_TIM_IC_Config\n |
| 1816 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
1816 | * CCER CC3P LL_TIM_IC_Config\n |
| 1817 | * CCMR2 IC3F LL_TIM_IC_Config\n |
1817 | * CCER CC3NP LL_TIM_IC_Config\n |
| 1818 | * CCMR2 CC4S LL_TIM_IC_Config\n |
1818 | * CCER CC4P LL_TIM_IC_Config\n |
| 1819 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
1819 | * CCER CC4NP LL_TIM_IC_Config |
| 1820 | * CCMR2 IC4F LL_TIM_IC_Config\n |
1820 | * @param TIMx Timer instance |
| 1821 | * CCER CC1P LL_TIM_IC_Config\n |
1821 | * @param Channel This parameter can be one of the following values: |
| 1822 | * CCER CC1NP LL_TIM_IC_Config\n |
1822 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1823 | * CCER CC2P LL_TIM_IC_Config\n |
1823 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1824 | * CCER CC2NP LL_TIM_IC_Config\n |
1824 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1825 | * CCER CC3P LL_TIM_IC_Config\n |
1825 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1826 | * CCER CC3NP LL_TIM_IC_Config\n |
1826 | * @param Configuration This parameter must be a combination of all the following values: |
| 1827 | * CCER CC4P LL_TIM_IC_Config\n |
1827 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
| 1828 | * CCER CC4NP LL_TIM_IC_Config |
1828 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
| 1829 | * @param TIMx Timer instance |
1829 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| 1830 | * @param Channel This parameter can be one of the following values: |
1830 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE |
| 1831 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1831 | * @retval None |
| 1832 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1832 | */ |
| 1833 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1833 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| 1834 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1834 | { |
| 1835 | * @param Configuration This parameter must be a combination of all the following values: |
1835 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1836 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
1836 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1837 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
1837 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
| 1838 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
1838 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ |
| 1839 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE |
1839 | << SHIFT_TAB_ICxx[iChannel]); |
| 1840 | * @retval None |
1840 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
| 1841 | */ |
1841 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
| 1842 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
1842 | } |
| 1843 | { |
1843 | |
| 1844 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1844 | /** |
| 1845 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1845 | * @brief Set the active input. |
| 1846 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
1846 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
| 1847 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ |
1847 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
| 1848 | << SHIFT_TAB_ICxx[iChannel]); |
1848 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
| 1849 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
1849 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
| 1850 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
1850 | * @param TIMx Timer instance |
| 1851 | } |
1851 | * @param Channel This parameter can be one of the following values: |
| 1852 | 1852 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1853 | /** |
1853 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1854 | * @brief Set the active input. |
1854 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1855 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
1855 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1856 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
1856 | * @param ICActiveInput This parameter can be one of the following values: |
| 1857 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
1857 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
| 1858 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
1858 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
| 1859 | * @param TIMx Timer instance |
1859 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
| 1860 | * @param Channel This parameter can be one of the following values: |
1860 | * @retval None |
| 1861 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1861 | */ |
| 1862 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1862 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
| 1863 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1863 | { |
| 1864 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1864 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1865 | * @param ICActiveInput This parameter can be one of the following values: |
1865 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1866 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
1866 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| 1867 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
1867 | } |
| 1868 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
1868 | |
| 1869 | * @retval None |
1869 | /** |
| 1870 | */ |
1870 | * @brief Get the current active input. |
| 1871 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
1871 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
| 1872 | { |
1872 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
| 1873 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1873 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
| 1874 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1874 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
| 1875 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
1875 | * @param TIMx Timer instance |
| 1876 | } |
1876 | * @param Channel This parameter can be one of the following values: |
| 1877 | 1877 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1878 | /** |
1878 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1879 | * @brief Get the current active input. |
1879 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1880 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
1880 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1881 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
1881 | * @retval Returned value can be one of the following values: |
| 1882 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
1882 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
| 1883 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
1883 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
| 1884 | * @param TIMx Timer instance |
1884 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
| 1885 | * @param Channel This parameter can be one of the following values: |
1885 | */ |
| 1886 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1886 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1887 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1887 | { |
| 1888 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1888 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1889 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1889 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1890 | * @retval Returned value can be one of the following values: |
1890 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| 1891 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
1891 | } |
| 1892 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
1892 | |
| 1893 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
1893 | /** |
| 1894 | */ |
1894 | * @brief Set the prescaler of input channel. |
| 1895 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) |
1895 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
| 1896 | { |
1896 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
| 1897 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1897 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
| 1898 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1898 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
| 1899 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
1899 | * @param TIMx Timer instance |
| 1900 | } |
1900 | * @param Channel This parameter can be one of the following values: |
| 1901 | 1901 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1902 | /** |
1902 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1903 | * @brief Set the prescaler of input channel. |
1903 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1904 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
1904 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1905 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
1905 | * @param ICPrescaler This parameter can be one of the following values: |
| 1906 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
1906 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| 1907 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
1907 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| 1908 | * @param TIMx Timer instance |
1908 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| 1909 | * @param Channel This parameter can be one of the following values: |
1909 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| 1910 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1910 | * @retval None |
| 1911 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1911 | */ |
| 1912 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1912 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
| 1913 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1913 | { |
| 1914 | * @param ICPrescaler This parameter can be one of the following values: |
1914 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1915 | * @arg @ref LL_TIM_ICPSC_DIV1 |
1915 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1916 | * @arg @ref LL_TIM_ICPSC_DIV2 |
1916 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| 1917 | * @arg @ref LL_TIM_ICPSC_DIV4 |
1917 | } |
| 1918 | * @arg @ref LL_TIM_ICPSC_DIV8 |
1918 | |
| 1919 | * @retval None |
1919 | /** |
| 1920 | */ |
1920 | * @brief Get the current prescaler value acting on an input channel. |
| 1921 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
1921 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
| 1922 | { |
1922 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
| 1923 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1923 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
| 1924 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1924 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
| 1925 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
1925 | * @param TIMx Timer instance |
| 1926 | } |
1926 | * @param Channel This parameter can be one of the following values: |
| 1927 | 1927 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1928 | /** |
1928 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1929 | * @brief Get the current prescaler value acting on an input channel. |
1929 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1930 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
1930 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1931 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
1931 | * @retval Returned value can be one of the following values: |
| 1932 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
1932 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| 1933 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
1933 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| 1934 | * @param TIMx Timer instance |
1934 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| 1935 | * @param Channel This parameter can be one of the following values: |
1935 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| 1936 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1936 | */ |
| 1937 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1937 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1938 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1938 | { |
| 1939 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1939 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1940 | * @retval Returned value can be one of the following values: |
1940 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1941 | * @arg @ref LL_TIM_ICPSC_DIV1 |
1941 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| 1942 | * @arg @ref LL_TIM_ICPSC_DIV2 |
1942 | } |
| 1943 | * @arg @ref LL_TIM_ICPSC_DIV4 |
1943 | |
| 1944 | * @arg @ref LL_TIM_ICPSC_DIV8 |
1944 | /** |
| 1945 | */ |
1945 | * @brief Set the input filter duration. |
| 1946 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) |
1946 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
| 1947 | { |
1947 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
| 1948 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1948 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
| 1949 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1949 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
| 1950 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
1950 | * @param TIMx Timer instance |
| 1951 | } |
1951 | * @param Channel This parameter can be one of the following values: |
| 1952 | 1952 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1953 | /** |
1953 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1954 | * @brief Set the input filter duration. |
1954 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1955 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
1955 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1956 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
1956 | * @param ICFilter This parameter can be one of the following values: |
| 1957 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
1957 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
| 1958 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
1958 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
| 1959 | * @param TIMx Timer instance |
1959 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
| 1960 | * @param Channel This parameter can be one of the following values: |
1960 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
| 1961 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1961 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
| 1962 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1962 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
| 1963 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1963 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
| 1964 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1964 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
| 1965 | * @param ICFilter This parameter can be one of the following values: |
1965 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
| 1966 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
1966 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
| 1967 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
1967 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
| 1968 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
1968 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
| 1969 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
1969 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
| 1970 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
1970 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
| 1971 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
1971 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
| 1972 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
1972 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| 1973 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
1973 | * @retval None |
| 1974 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
1974 | */ |
| 1975 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
1975 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
| 1976 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
1976 | { |
| 1977 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
1977 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1978 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
1978 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1979 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
1979 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| 1980 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
1980 | } |
| 1981 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
1981 | |
| 1982 | * @retval None |
1982 | /** |
| 1983 | */ |
1983 | * @brief Get the input filter duration. |
| 1984 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
1984 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
| 1985 | { |
1985 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
| 1986 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1986 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
| 1987 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1987 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
| 1988 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
1988 | * @param TIMx Timer instance |
| 1989 | } |
1989 | * @param Channel This parameter can be one of the following values: |
| 1990 | 1990 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1991 | /** |
1991 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1992 | * @brief Get the input filter duration. |
1992 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1993 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
1993 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1994 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
1994 | * @retval Returned value can be one of the following values: |
| 1995 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
1995 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
| 1996 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
1996 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
| 1997 | * @param TIMx Timer instance |
1997 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
| 1998 | * @param Channel This parameter can be one of the following values: |
1998 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
| 1999 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1999 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
| 2000 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2000 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
| 2001 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2001 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
| 2002 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2002 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
| 2003 | * @retval Returned value can be one of the following values: |
2003 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
| 2004 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
2004 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
| 2005 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
2005 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
| 2006 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
2006 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
| 2007 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
2007 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
| 2008 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
2008 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
| 2009 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
2009 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
| 2010 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
2010 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| 2011 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
2011 | */ |
| 2012 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
2012 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2013 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
2013 | { |
| 2014 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
2014 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2015 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
2015 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2016 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
2016 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| 2017 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
2017 | } |
| 2018 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
2018 | |
| 2019 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
2019 | /** |
| 2020 | */ |
2020 | * @brief Set the input channel polarity. |
| 2021 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) |
2021 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
| 2022 | { |
2022 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
| 2023 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2023 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
| 2024 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2024 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
| 2025 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
2025 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
| 2026 | } |
2026 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
| 2027 | 2027 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
|
| 2028 | /** |
2028 | * CCER CC4NP LL_TIM_IC_SetPolarity |
| 2029 | * @brief Set the input channel polarity. |
2029 | * @param TIMx Timer instance |
| 2030 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
2030 | * @param Channel This parameter can be one of the following values: |
| 2031 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
2031 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 2032 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
2032 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2033 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
2033 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2034 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
2034 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2035 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
2035 | * @param ICPolarity This parameter can be one of the following values: |
| 2036 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
2036 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
| 2037 | * CCER CC4NP LL_TIM_IC_SetPolarity |
2037 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
| 2038 | * @param TIMx Timer instance |
2038 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
| 2039 | * @param Channel This parameter can be one of the following values: |
2039 | * @retval None |
| 2040 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2040 | */ |
| 2041 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2041 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
| 2042 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2042 | { |
| 2043 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2043 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2044 | * @param ICPolarity This parameter can be one of the following values: |
2044 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
| 2045 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
2045 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
| 2046 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
2046 | } |
| 2047 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
2047 | |
| 2048 | * @retval None |
2048 | /** |
| 2049 | */ |
2049 | * @brief Get the current input channel polarity. |
| 2050 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
2050 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
| 2051 | { |
2051 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
| 2052 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2052 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
| 2053 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
2053 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
| 2054 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
2054 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
| 2055 | } |
2055 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
| 2056 | 2056 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
|
| 2057 | /** |
2057 | * CCER CC4NP LL_TIM_IC_GetPolarity |
| 2058 | * @brief Get the current input channel polarity. |
2058 | * @param TIMx Timer instance |
| 2059 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
2059 | * @param Channel This parameter can be one of the following values: |
| 2060 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
2060 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 2061 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
2061 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2062 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
2062 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2063 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
2063 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2064 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
2064 | * @retval Returned value can be one of the following values: |
| 2065 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
2065 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
| 2066 | * CCER CC4NP LL_TIM_IC_GetPolarity |
2066 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
| 2067 | * @param TIMx Timer instance |
2067 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
| 2068 | * @param Channel This parameter can be one of the following values: |
2068 | */ |
| 2069 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2069 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2070 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2070 | { |
| 2071 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2071 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2072 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2072 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
| 2073 | * @retval Returned value can be one of the following values: |
2073 | SHIFT_TAB_CCxP[iChannel]); |
| 2074 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
2074 | } |
| 2075 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
2075 | |
| 2076 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
2076 | /** |
| 2077 | */ |
2077 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
| 2078 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
2078 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| 2079 | { |
2079 | * a timer instance provides an XOR input. |
| 2080 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2080 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
| 2081 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
2081 | * @param TIMx Timer instance |
| 2082 | SHIFT_TAB_CCxP[iChannel]); |
2082 | * @retval None |
| 2083 | } |
2083 | */ |
| 2084 | 2084 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
|
| 2085 | /** |
2085 | { |
| 2086 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
2086 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
| 2087 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
2087 | } |
| 2088 | * a timer instance provides an XOR input. |
2088 | |
| 2089 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
2089 | /** |
| 2090 | * @param TIMx Timer instance |
2090 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
| 2091 | * @retval None |
2091 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| 2092 | */ |
2092 | * a timer instance provides an XOR input. |
| 2093 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
2093 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
| 2094 | { |
2094 | * @param TIMx Timer instance |
| 2095 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
2095 | * @retval None |
| 2096 | } |
2096 | */ |
| 2097 | 2097 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
|
| 2098 | /** |
2098 | { |
| 2099 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
2099 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
| 2100 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
2100 | } |
| 2101 | * a timer instance provides an XOR input. |
2101 | |
| 2102 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
2102 | /** |
| 2103 | * @param TIMx Timer instance |
2103 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
| 2104 | * @retval None |
2104 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| 2105 | */ |
2105 | * a timer instance provides an XOR input. |
| 2106 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
2106 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
| 2107 | { |
2107 | * @param TIMx Timer instance |
| 2108 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
2108 | * @retval State of bit (1 or 0). |
| 2109 | } |
2109 | */ |
| 2110 | 2110 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) |
|
| 2111 | /** |
2111 | { |
| 2112 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
2112 | return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); |
| 2113 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
2113 | } |
| 2114 | * a timer instance provides an XOR input. |
2114 | |
| 2115 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
2115 | /** |
| 2116 | * @param TIMx Timer instance |
2116 | * @brief Get captured value for input channel 1. |
| 2117 | * @retval State of bit (1 or 0). |
2117 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| 2118 | */ |
2118 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 2119 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) |
2119 | * whether or not a timer instance supports a 32 bits counter. |
| 2120 | { |
2120 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| 2121 | return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); |
2121 | * input channel 1 is supported by a timer instance. |
| 2122 | } |
2122 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
| 2123 | 2123 | * @param TIMx Timer instance |
|
| 2124 | /** |
2124 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2125 | * @brief Get captured value for input channel 1. |
2125 | */ |
| 2126 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
2126 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) |
| 2127 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
2127 | { |
| 2128 | * whether or not a timer instance supports a 32 bits counter. |
2128 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
| 2129 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
2129 | } |
| 2130 | * input channel 1 is supported by a timer instance. |
2130 | |
| 2131 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
2131 | /** |
| 2132 | * @param TIMx Timer instance |
2132 | * @brief Get captured value for input channel 2. |
| 2133 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2133 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| 2134 | */ |
2134 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 2135 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) |
2135 | * whether or not a timer instance supports a 32 bits counter. |
| 2136 | { |
2136 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| 2137 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
2137 | * input channel 2 is supported by a timer instance. |
| 2138 | } |
2138 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
| 2139 | 2139 | * @param TIMx Timer instance |
|
| 2140 | /** |
2140 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2141 | * @brief Get captured value for input channel 2. |
2141 | */ |
| 2142 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
2142 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) |
| 2143 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
2143 | { |
| 2144 | * whether or not a timer instance supports a 32 bits counter. |
2144 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
| 2145 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
2145 | } |
| 2146 | * input channel 2 is supported by a timer instance. |
2146 | |
| 2147 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
2147 | /** |
| 2148 | * @param TIMx Timer instance |
2148 | * @brief Get captured value for input channel 3. |
| 2149 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2149 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| 2150 | */ |
2150 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 2151 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) |
2151 | * whether or not a timer instance supports a 32 bits counter. |
| 2152 | { |
2152 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| 2153 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
2153 | * input channel 3 is supported by a timer instance. |
| 2154 | } |
2154 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
| 2155 | 2155 | * @param TIMx Timer instance |
|
| 2156 | /** |
2156 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2157 | * @brief Get captured value for input channel 3. |
2157 | */ |
| 2158 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
2158 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) |
| 2159 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
2159 | { |
| 2160 | * whether or not a timer instance supports a 32 bits counter. |
2160 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
| 2161 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
2161 | } |
| 2162 | * input channel 3 is supported by a timer instance. |
2162 | |
| 2163 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
2163 | /** |
| 2164 | * @param TIMx Timer instance |
2164 | * @brief Get captured value for input channel 4. |
| 2165 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2165 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| 2166 | */ |
2166 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| 2167 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) |
2167 | * whether or not a timer instance supports a 32 bits counter. |
| 2168 | { |
2168 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| 2169 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
2169 | * input channel 4 is supported by a timer instance. |
| 2170 | } |
2170 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
| 2171 | 2171 | * @param TIMx Timer instance |
|
| 2172 | /** |
2172 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2173 | * @brief Get captured value for input channel 4. |
2173 | */ |
| 2174 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
2174 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) |
| 2175 | * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
2175 | { |
| 2176 | * whether or not a timer instance supports a 32 bits counter. |
2176 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
| 2177 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
2177 | } |
| 2178 | * input channel 4 is supported by a timer instance. |
2178 | |
| 2179 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
2179 | /** |
| 2180 | * @param TIMx Timer instance |
2180 | * @} |
| 2181 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2181 | */ |
| 2182 | */ |
2182 | |
| 2183 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) |
2183 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
| 2184 | { |
2184 | * @{ |
| 2185 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
2185 | */ |
| 2186 | } |
2186 | /** |
| 2187 | 2187 | * @brief Enable external clock mode 2. |
|
| 2188 | /** |
2188 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
| 2189 | * @} |
2189 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| 2190 | */ |
2190 | * whether or not a timer instance supports external clock mode2. |
| 2191 | 2191 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
|
| 2192 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
2192 | * @param TIMx Timer instance |
| 2193 | * @{ |
2193 | * @retval None |
| 2194 | */ |
2194 | */ |
| 2195 | /** |
2195 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
| 2196 | * @brief Enable external clock mode 2. |
2196 | { |
| 2197 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
2197 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
| 2198 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2198 | } |
| 2199 | * whether or not a timer instance supports external clock mode2. |
2199 | |
| 2200 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
2200 | /** |
| 2201 | * @param TIMx Timer instance |
2201 | * @brief Disable external clock mode 2. |
| 2202 | * @retval None |
2202 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| 2203 | */ |
2203 | * whether or not a timer instance supports external clock mode2. |
| 2204 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
2204 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
| 2205 | { |
2205 | * @param TIMx Timer instance |
| 2206 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
2206 | * @retval None |
| 2207 | } |
2207 | */ |
| 2208 | 2208 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
|
| 2209 | /** |
2209 | { |
| 2210 | * @brief Disable external clock mode 2. |
2210 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
| 2211 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2211 | } |
| 2212 | * whether or not a timer instance supports external clock mode2. |
2212 | |
| 2213 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
2213 | /** |
| 2214 | * @param TIMx Timer instance |
2214 | * @brief Indicate whether external clock mode 2 is enabled. |
| 2215 | * @retval None |
2215 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| 2216 | */ |
2216 | * whether or not a timer instance supports external clock mode2. |
| 2217 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
2217 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
| 2218 | { |
2218 | * @param TIMx Timer instance |
| 2219 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
2219 | * @retval State of bit (1 or 0). |
| 2220 | } |
2220 | */ |
| 2221 | 2221 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) |
|
| 2222 | /** |
2222 | { |
| 2223 | * @brief Indicate whether external clock mode 2 is enabled. |
2223 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); |
| 2224 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2224 | } |
| 2225 | * whether or not a timer instance supports external clock mode2. |
2225 | |
| 2226 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
2226 | /** |
| 2227 | * @param TIMx Timer instance |
2227 | * @brief Set the clock source of the counter clock. |
| 2228 | * @retval State of bit (1 or 0). |
2228 | * @note when selected clock source is external clock mode 1, the timer input |
| 2229 | */ |
2229 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
| 2230 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) |
2230 | * function. This timer input must be configured by calling |
| 2231 | { |
2231 | * the @ref LL_TIM_IC_Config() function. |
| 2232 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); |
2232 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
| 2233 | } |
2233 | * whether or not a timer instance supports external clock mode1. |
| 2234 | 2234 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
|
| 2235 | /** |
2235 | * whether or not a timer instance supports external clock mode2. |
| 2236 | * @brief Set the clock source of the counter clock. |
2236 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
| 2237 | * @note when selected clock source is external clock mode 1, the timer input |
2237 | * SMCR ECE LL_TIM_SetClockSource |
| 2238 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
2238 | * @param TIMx Timer instance |
| 2239 | * function. This timer input must be configured by calling |
2239 | * @param ClockSource This parameter can be one of the following values: |
| 2240 | * the @ref LL_TIM_IC_Config() function. |
2240 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
| 2241 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
2241 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
| 2242 | * whether or not a timer instance supports external clock mode1. |
2242 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
| 2243 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2243 | * @retval None |
| 2244 | * whether or not a timer instance supports external clock mode2. |
2244 | */ |
| 2245 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
2245 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
| 2246 | * SMCR ECE LL_TIM_SetClockSource |
2246 | { |
| 2247 | * @param TIMx Timer instance |
2247 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
| 2248 | * @param ClockSource This parameter can be one of the following values: |
2248 | } |
| 2249 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
2249 | |
| 2250 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
2250 | /** |
| 2251 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
2251 | * @brief Set the encoder interface mode. |
| 2252 | * @retval None |
2252 | * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
| 2253 | */ |
2253 | * whether or not a timer instance supports the encoder mode. |
| 2254 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
2254 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
| 2255 | { |
2255 | * @param TIMx Timer instance |
| 2256 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
2256 | * @param EncoderMode This parameter can be one of the following values: |
| 2257 | } |
2257 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
| 2258 | 2258 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
|
| 2259 | /** |
2259 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
| 2260 | * @brief Set the encoder interface mode. |
2260 | * @retval None |
| 2261 | * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
2261 | */ |
| 2262 | * whether or not a timer instance supports the encoder mode. |
2262 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
| 2263 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
2263 | { |
| 2264 | * @param TIMx Timer instance |
2264 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
| 2265 | * @param EncoderMode This parameter can be one of the following values: |
2265 | } |
| 2266 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
2266 | |
| 2267 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
2267 | /** |
| 2268 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
2268 | * @} |
| 2269 | * @retval None |
2269 | */ |
| 2270 | */ |
2270 | |
| 2271 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
2271 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
| 2272 | { |
2272 | * @{ |
| 2273 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
2273 | */ |
| 2274 | } |
2274 | /** |
| 2275 | 2275 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
|
| 2276 | /** |
2276 | * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
| 2277 | * @} |
2277 | * whether or not a timer instance can operate as a master timer. |
| 2278 | */ |
2278 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
| 2279 | 2279 | * @param TIMx Timer instance |
|
| 2280 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
2280 | * @param TimerSynchronization This parameter can be one of the following values: |
| 2281 | * @{ |
2281 | * @arg @ref LL_TIM_TRGO_RESET |
| 2282 | */ |
2282 | * @arg @ref LL_TIM_TRGO_ENABLE |
| 2283 | /** |
2283 | * @arg @ref LL_TIM_TRGO_UPDATE |
| 2284 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
2284 | * @arg @ref LL_TIM_TRGO_CC1IF |
| 2285 | * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
2285 | * @arg @ref LL_TIM_TRGO_OC1REF |
| 2286 | * whether or not a timer instance can operate as a master timer. |
2286 | * @arg @ref LL_TIM_TRGO_OC2REF |
| 2287 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
2287 | * @arg @ref LL_TIM_TRGO_OC3REF |
| 2288 | * @param TIMx Timer instance |
2288 | * @arg @ref LL_TIM_TRGO_OC4REF |
| 2289 | * @param TimerSynchronization This parameter can be one of the following values: |
2289 | * @retval None |
| 2290 | * @arg @ref LL_TIM_TRGO_RESET |
2290 | */ |
| 2291 | * @arg @ref LL_TIM_TRGO_ENABLE |
2291 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
| 2292 | * @arg @ref LL_TIM_TRGO_UPDATE |
2292 | { |
| 2293 | * @arg @ref LL_TIM_TRGO_CC1IF |
2293 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
| 2294 | * @arg @ref LL_TIM_TRGO_OC1REF |
2294 | } |
| 2295 | * @arg @ref LL_TIM_TRGO_OC2REF |
2295 | |
| 2296 | * @arg @ref LL_TIM_TRGO_OC3REF |
2296 | /** |
| 2297 | * @arg @ref LL_TIM_TRGO_OC4REF |
2297 | * @brief Set the synchronization mode of a slave timer. |
| 2298 | * @retval None |
2298 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2299 | */ |
2299 | * a timer instance can operate as a slave timer. |
| 2300 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
2300 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
| 2301 | { |
2301 | * @param TIMx Timer instance |
| 2302 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
2302 | * @param SlaveMode This parameter can be one of the following values: |
| 2303 | } |
2303 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
| 2304 | 2304 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
|
| 2305 | /** |
2305 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
| 2306 | * @brief Set the synchronization mode of a slave timer. |
2306 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
| 2307 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2307 | * @retval None |
| 2308 | * a timer instance can operate as a slave timer. |
2308 | */ |
| 2309 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
2309 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
| 2310 | * @param TIMx Timer instance |
2310 | { |
| 2311 | * @param SlaveMode This parameter can be one of the following values: |
2311 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
| 2312 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
2312 | } |
| 2313 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
2313 | |
| 2314 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
2314 | /** |
| 2315 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
2315 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
| 2316 | * @retval None |
2316 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2317 | */ |
2317 | * a timer instance can operate as a slave timer. |
| 2318 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
2318 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
| 2319 | { |
2319 | * @param TIMx Timer instance |
| 2320 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
2320 | * @param TriggerInput This parameter can be one of the following values: |
| 2321 | } |
2321 | * @arg @ref LL_TIM_TS_ITR0 |
| 2322 | 2322 | * @arg @ref LL_TIM_TS_ITR1 |
|
| 2323 | /** |
2323 | * @arg @ref LL_TIM_TS_ITR2 |
| 2324 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
2324 | * @arg @ref LL_TIM_TS_ITR3 |
| 2325 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2325 | * @arg @ref LL_TIM_TS_TI1F_ED |
| 2326 | * a timer instance can operate as a slave timer. |
2326 | * @arg @ref LL_TIM_TS_TI1FP1 |
| 2327 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
2327 | * @arg @ref LL_TIM_TS_TI2FP2 |
| 2328 | * @param TIMx Timer instance |
2328 | * @arg @ref LL_TIM_TS_ETRF |
| 2329 | * @param TriggerInput This parameter can be one of the following values: |
2329 | * @retval None |
| 2330 | * @arg @ref LL_TIM_TS_ITR0 |
2330 | */ |
| 2331 | * @arg @ref LL_TIM_TS_ITR1 |
2331 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
| 2332 | * @arg @ref LL_TIM_TS_ITR2 |
2332 | { |
| 2333 | * @arg @ref LL_TIM_TS_ITR3 |
2333 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
| 2334 | * @arg @ref LL_TIM_TS_TI1F_ED |
2334 | } |
| 2335 | * @arg @ref LL_TIM_TS_TI1FP1 |
2335 | |
| 2336 | * @arg @ref LL_TIM_TS_TI2FP2 |
2336 | /** |
| 2337 | * @arg @ref LL_TIM_TS_ETRF |
2337 | * @brief Enable the Master/Slave mode. |
| 2338 | * @retval None |
2338 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2339 | */ |
2339 | * a timer instance can operate as a slave timer. |
| 2340 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
2340 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
| 2341 | { |
2341 | * @param TIMx Timer instance |
| 2342 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
2342 | * @retval None |
| 2343 | } |
2343 | */ |
| 2344 | 2344 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
|
| 2345 | /** |
2345 | { |
| 2346 | * @brief Enable the Master/Slave mode. |
2346 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
| 2347 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2347 | } |
| 2348 | * a timer instance can operate as a slave timer. |
2348 | |
| 2349 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
2349 | /** |
| 2350 | * @param TIMx Timer instance |
2350 | * @brief Disable the Master/Slave mode. |
| 2351 | * @retval None |
2351 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2352 | */ |
2352 | * a timer instance can operate as a slave timer. |
| 2353 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
2353 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
| 2354 | { |
2354 | * @param TIMx Timer instance |
| 2355 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
2355 | * @retval None |
| 2356 | } |
2356 | */ |
| 2357 | 2357 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
|
| 2358 | /** |
2358 | { |
| 2359 | * @brief Disable the Master/Slave mode. |
2359 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
| 2360 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2360 | } |
| 2361 | * a timer instance can operate as a slave timer. |
2361 | |
| 2362 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
2362 | /** |
| 2363 | * @param TIMx Timer instance |
2363 | * @brief Indicates whether the Master/Slave mode is enabled. |
| 2364 | * @retval None |
2364 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2365 | */ |
2365 | * a timer instance can operate as a slave timer. |
| 2366 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
2366 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
| 2367 | { |
2367 | * @param TIMx Timer instance |
| 2368 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
2368 | * @retval State of bit (1 or 0). |
| 2369 | } |
2369 | */ |
| 2370 | 2370 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) |
|
| 2371 | /** |
2371 | { |
| 2372 | * @brief Indicates whether the Master/Slave mode is enabled. |
2372 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); |
| 2373 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2373 | } |
| 2374 | * a timer instance can operate as a slave timer. |
2374 | |
| 2375 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
2375 | /** |
| 2376 | * @param TIMx Timer instance |
2376 | * @brief Configure the external trigger (ETR) input. |
| 2377 | * @retval State of bit (1 or 0). |
2377 | * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
| 2378 | */ |
2378 | * a timer instance provides an external trigger input. |
| 2379 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) |
2379 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
| 2380 | { |
2380 | * SMCR ETPS LL_TIM_ConfigETR\n |
| 2381 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); |
2381 | * SMCR ETF LL_TIM_ConfigETR |
| 2382 | } |
2382 | * @param TIMx Timer instance |
| 2383 | 2383 | * @param ETRPolarity This parameter can be one of the following values: |
|
| 2384 | /** |
2384 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
| 2385 | * @brief Configure the external trigger (ETR) input. |
2385 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
| 2386 | * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
2386 | * @param ETRPrescaler This parameter can be one of the following values: |
| 2387 | * a timer instance provides an external trigger input. |
2387 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
| 2388 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
2388 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
| 2389 | * SMCR ETPS LL_TIM_ConfigETR\n |
2389 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
| 2390 | * SMCR ETF LL_TIM_ConfigETR |
2390 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
| 2391 | * @param TIMx Timer instance |
2391 | * @param ETRFilter This parameter can be one of the following values: |
| 2392 | * @param ETRPolarity This parameter can be one of the following values: |
2392 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
| 2393 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
2393 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
| 2394 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
2394 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
| 2395 | * @param ETRPrescaler This parameter can be one of the following values: |
2395 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
| 2396 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
2396 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
| 2397 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
2397 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
| 2398 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
2398 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
| 2399 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
2399 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
| 2400 | * @param ETRFilter This parameter can be one of the following values: |
2400 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
| 2401 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
2401 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
| 2402 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
2402 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
| 2403 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
2403 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
| 2404 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
2404 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
| 2405 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
2405 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
| 2406 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
2406 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
| 2407 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
2407 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
| 2408 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
2408 | * @retval None |
| 2409 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
2409 | */ |
| 2410 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
2410 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
| 2411 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
2411 | uint32_t ETRFilter) |
| 2412 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
2412 | { |
| 2413 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
2413 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
| 2414 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
2414 | } |
| 2415 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
2415 | |
| 2416 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
2416 | /** |
| 2417 | * @retval None |
2417 | * @} |
| 2418 | */ |
2418 | */ |
| 2419 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
2419 | |
| 2420 | uint32_t ETRFilter) |
2420 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
| 2421 | { |
2421 | * @{ |
| 2422 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
2422 | */ |
| 2423 | } |
2423 | /** |
| 2424 | 2424 | * @brief Configures the timer DMA burst feature. |
|
| 2425 | /** |
2425 | * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
| 2426 | * @} |
2426 | * not a timer instance supports the DMA burst mode. |
| 2427 | */ |
2427 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
| 2428 | 2428 | * DCR DBA LL_TIM_ConfigDMABurst |
|
| 2429 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
2429 | * @param TIMx Timer instance |
| 2430 | * @{ |
2430 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
| 2431 | */ |
2431 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
| 2432 | /** |
2432 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
| 2433 | * @brief Configures the timer DMA burst feature. |
2433 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
| 2434 | * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
2434 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
| 2435 | * not a timer instance supports the DMA burst mode. |
2435 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
| 2436 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
2436 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
| 2437 | * DCR DBA LL_TIM_ConfigDMABurst |
2437 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
| 2438 | * @param TIMx Timer instance |
2438 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
| 2439 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
2439 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
| 2440 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
2440 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
| 2441 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
2441 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
| 2442 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
2442 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
| 2443 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
2443 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
| 2444 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
2444 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
| 2445 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
2445 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
| 2446 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
2446 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
| 2447 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
2447 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR |
| 2448 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
2448 | * @param DMABurstLength This parameter can be one of the following values: |
| 2449 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
2449 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
| 2450 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
2450 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
| 2451 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
2451 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
| 2452 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
2452 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
| 2453 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
2453 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
| 2454 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
2454 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
| 2455 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
2455 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
| 2456 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR |
2456 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
| 2457 | * @param DMABurstLength This parameter can be one of the following values: |
2457 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
| 2458 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
2458 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
| 2459 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
2459 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
| 2460 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
2460 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
| 2461 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
2461 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
| 2462 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
2462 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
| 2463 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
2463 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
| 2464 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
2464 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
| 2465 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
2465 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
| 2466 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
2466 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
| 2467 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
2467 | * @retval None |
| 2468 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
2468 | */ |
| 2469 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
2469 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
| 2470 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
2470 | { |
| 2471 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
2471 | MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); |
| 2472 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
2472 | } |
| 2473 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
2473 | |
| 2474 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
2474 | /** |
| 2475 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
2475 | * @} |
| 2476 | * @retval None |
2476 | */ |
| 2477 | */ |
2477 | |
| 2478 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
2478 | /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping |
| 2479 | { |
2479 | * @{ |
| 2480 | MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); |
2480 | */ |
| 2481 | } |
2481 | /** |
| 2482 | 2482 | * @brief Remap TIM inputs (input channel, internal/external triggers). |
|
| 2483 | /** |
2483 | * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not |
| 2484 | * @} |
2484 | * a some timer inputs can be remapped. |
| 2485 | */ |
2485 | * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n |
| 2486 | 2486 | * TIM3_OR ITR2_RMP LL_TIM_SetRemap\n |
|
| 2487 | /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping |
2487 | * TIM9_OR TI1_RMP LL_TIM_SetRemap\n |
| 2488 | * @{ |
2488 | * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n |
| 2489 | */ |
2489 | * TIM10_OR TI1_RMP LL_TIM_SetRemap\n |
| 2490 | /** |
2490 | * TIM10_OR ETR_RMP LL_TIM_SetRemap\n |
| 2491 | * @brief Remap TIM inputs (input channel, internal/external triggers). |
2491 | * TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n |
| 2492 | * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not |
2492 | * TIM11_OR TI1_RMP LL_TIM_SetRemap\n |
| 2493 | * a some timer inputs can be remapped. |
2493 | * TIM11_OR ETR_RMP LL_TIM_SetRemap\n |
| 2494 | * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n |
2494 | * TIM11_OR TI1_RMP_RI LL_TIM_SetRemap |
| 2495 | * TIM3_OR ITR2_RMP LL_TIM_SetRemap\n |
2495 | * @param TIMx Timer instance |
| 2496 | * TIM9_OR TI1_RMP LL_TIM_SetRemap\n |
2496 | * @param Remap Remap params depends on the TIMx. Description available only |
| 2497 | * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n |
2497 | * in CHM version of the User Manual (not in .pdf). |
| 2498 | * TIM10_OR TI1_RMP LL_TIM_SetRemap\n |
2498 | * Otherwise see Reference Manual description of OR registers. |
| 2499 | * TIM10_OR ETR_RMP LL_TIM_SetRemap\n |
2499 | * |
| 2500 | * TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n |
2500 | * Below description summarizes "Timer Instance" and "Remap" param combinations: |
| 2501 | * TIM11_OR TI1_RMP LL_TIM_SetRemap\n |
2501 | * |
| 2502 | * TIM11_OR ETR_RMP LL_TIM_SetRemap\n |
2502 | * TIM2: any combination of ITR1_RMP where |
| 2503 | * TIM11_OR TI1_RMP_RI LL_TIM_SetRemap |
2503 | * |
| 2504 | * @param TIMx Timer instance |
2504 | * . . ITR1_RMP can be one of the following values |
| 2505 | * @param Remap Remap params depends on the TIMx. Description available only |
2505 | * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**) |
| 2506 | * in CHM version of the User Manual (not in .pdf). |
2506 | * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**) |
| 2507 | * Otherwise see Reference Manual description of OR registers. |
2507 | * |
| 2508 | * |
2508 | * TIM3: any combination of ITR2_RMP where |
| 2509 | * Below description summarizes "Timer Instance" and "Remap" param combinations: |
2509 | * |
| 2510 | * |
2510 | * . . ITR2_RMP can be one of the following values |
| 2511 | * TIM2: any combination of ITR1_RMP where |
2511 | * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**) |
| 2512 | * |
2512 | * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**) |
| 2513 | * . . ITR1_RMP can be one of the following values |
2513 | * |
| 2514 | * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**) |
2514 | * TIM9: any combination of TI1_RMP, ITR1_RMP where |
| 2515 | * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**) |
2515 | * |
| 2516 | * |
2516 | * . . TI1_RMP can be one of the following values |
| 2517 | * TIM3: any combination of ITR2_RMP where |
2517 | * @arg @ref LL_TIM_TIM9_TI1_RMP_LSE |
| 2518 | * |
2518 | * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO |
| 2519 | * . . ITR2_RMP can be one of the following values |
2519 | * |
| 2520 | * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**) |
2520 | * . . ITR1_RMP can be one of the following values |
| 2521 | * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**) |
2521 | * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*) |
| 2522 | * |
2522 | * @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*) |
| 2523 | * TIM9: any combination of TI1_RMP, ITR1_RMP where |
2523 | * |
| 2524 | * |
2524 | * |
| 2525 | * . . TI1_RMP can be one of the following values |
2525 | * TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where |
| 2526 | * @arg @ref LL_TIM_TIM9_TI1_RMP_LSE |
2526 | * |
| 2527 | * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO |
2527 | * . . TI1_RMP can be one of the following values |
| 2528 | * |
2528 | * @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO |
| 2529 | * . . ITR1_RMP can be one of the following values |
2529 | * @arg @ref LL_TIM_TIM10_TI1_RMP_LSI |
| 2530 | * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*) |
2530 | * @arg @ref LL_TIM_TIM10_TI1_RMP_LSE |
| 2531 | * @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*) |
2531 | * @arg @ref LL_TIM_TIM10_TI1_RMP_RTC |
| 2532 | * |
2532 | * |
| 2533 | * |
2533 | * . . ETR_RMP can be one of the following values |
| 2534 | * TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where |
2534 | * @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*) |
| 2535 | * |
2535 | * |
| 2536 | * . . TI1_RMP can be one of the following values |
2536 | * . . TI1_RMP_RI can be one of the following values |
| 2537 | * @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO |
2537 | * @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*) |
| 2538 | * @arg @ref LL_TIM_TIM10_TI1_RMP_LSI |
2538 | * |
| 2539 | * @arg @ref LL_TIM_TIM10_TI1_RMP_LSE |
2539 | * |
| 2540 | * @arg @ref LL_TIM_TIM10_TI1_RMP_RTC |
2540 | * TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where |
| 2541 | * |
2541 | * |
| 2542 | * . . ETR_RMP can be one of the following values |
2542 | * . . TI1_RMP can be one of the following values |
| 2543 | * @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*) |
2543 | * @arg @ref LL_TIM_TIM11_TI1_RMP_MSI |
| 2544 | * |
2544 | * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC |
| 2545 | * . . TI1_RMP_RI can be one of the following values |
2545 | * @arg @ref LL_TIM_TIM11_TI1_RMP |
| 2546 | * @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*) |
2546 | * |
| 2547 | * |
2547 | * . . ETR_RMP can be one of the following values |
| 2548 | * |
2548 | * @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*) |
| 2549 | * TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where |
2549 | * |
| 2550 | * |
2550 | * . . TI1_RMP_RI can be one of the following values |
| 2551 | * . . TI1_RMP can be one of the following values |
2551 | * @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*) |
| 2552 | * @arg @ref LL_TIM_TIM11_TI1_RMP_MSI |
2552 | * |
| 2553 | * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC |
2553 | * (*) value not available in all devices categories |
| 2554 | * @arg @ref LL_TIM_TIM11_TI1_RMP |
2554 | * (**) register not available in all devices categories |
| 2555 | * |
2555 | * |
| 2556 | * . . ETR_RMP can be one of the following values |
2556 | * @note Option registers are available only for cat.3, cat.4 and cat.5 devices |
| 2557 | * @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*) |
2557 | * @retval None |
| 2558 | * |
2558 | */ |
| 2559 | * . . TI1_RMP_RI can be one of the following values |
2559 | __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) |
| 2560 | * @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*) |
2560 | { |
| 2561 | * |
2561 | MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); |
| 2562 | * (*) value not available in all devices categories |
2562 | } |
| 2563 | * (**) register not available in all devices categories |
2563 | |
| 2564 | * |
2564 | /** |
| 2565 | * @note Option registers are available only for cat.3, cat.4 and cat.5 devices |
2565 | * @} |
| 2566 | * @retval None |
2566 | */ |
| 2567 | */ |
2567 | |
| 2568 | __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) |
2568 | /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management |
| 2569 | { |
2569 | * @{ |
| 2570 | MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); |
2570 | */ |
| 2571 | } |
2571 | /** |
| 2572 | 2572 | * @brief Set the OCREF clear input source |
|
| 2573 | /** |
2573 | * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT |
| 2574 | * @} |
2574 | * @note This function can only be used in Output compare and PWM modes. |
| 2575 | */ |
2575 | * @note the ETR signal can be connected to the output of a comparator to be used for current handling |
| 2576 | 2576 | * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource |
|
| 2577 | /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management |
2577 | * @param TIMx Timer instance |
| 2578 | * @{ |
2578 | * @param OCRefClearInputSource This parameter can be one of the following values: |
| 2579 | */ |
2579 | * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR |
| 2580 | /** |
2580 | * @arg @ref LL_TIM_OCREF_CLR_INT_ETR |
| 2581 | * @brief Set the OCREF clear input source |
2581 | * @retval None |
| 2582 | * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT |
2582 | */ |
| 2583 | * @note This function can only be used in Output compare and PWM modes. |
2583 | __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) |
| 2584 | * @note the ETR signal can be connected to the output of a comparator to be used for current handling |
2584 | { |
| 2585 | * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource |
2585 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); |
| 2586 | * @param TIMx Timer instance |
2586 | } |
| 2587 | * @param OCRefClearInputSource This parameter can be one of the following values: |
2587 | /** |
| 2588 | * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR |
2588 | * @} |
| 2589 | * @arg @ref LL_TIM_OCREF_CLR_INT_ETR |
2589 | */ |
| 2590 | * @retval None |
2590 | |
| 2591 | */ |
2591 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
| 2592 | __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) |
2592 | * @{ |
| 2593 | { |
2593 | */ |
| 2594 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); |
2594 | /** |
| 2595 | } |
2595 | * @brief Clear the update interrupt flag (UIF). |
| 2596 | /** |
2596 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
| 2597 | * @} |
2597 | * @param TIMx Timer instance |
| 2598 | */ |
2598 | * @retval None |
| 2599 | 2599 | */ |
|
| 2600 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
2600 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
| 2601 | * @{ |
2601 | { |
| 2602 | */ |
2602 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
| 2603 | /** |
2603 | } |
| 2604 | * @brief Clear the update interrupt flag (UIF). |
2604 | |
| 2605 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
2605 | /** |
| 2606 | * @param TIMx Timer instance |
2606 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
| 2607 | * @retval None |
2607 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
| 2608 | */ |
2608 | * @param TIMx Timer instance |
| 2609 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
2609 | * @retval State of bit (1 or 0). |
| 2610 | { |
2610 | */ |
| 2611 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
2611 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) |
| 2612 | } |
2612 | { |
| 2613 | 2613 | return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); |
|
| 2614 | /** |
2614 | } |
| 2615 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
2615 | |
| 2616 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
2616 | /** |
| 2617 | * @param TIMx Timer instance |
2617 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
| 2618 | * @retval State of bit (1 or 0). |
2618 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
| 2619 | */ |
2619 | * @param TIMx Timer instance |
| 2620 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) |
2620 | * @retval None |
| 2621 | { |
2621 | */ |
| 2622 | return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); |
2622 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
| 2623 | } |
2623 | { |
| 2624 | 2624 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
|
| 2625 | /** |
2625 | } |
| 2626 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
2626 | |
| 2627 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
2627 | /** |
| 2628 | * @param TIMx Timer instance |
2628 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
| 2629 | * @retval None |
2629 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
| 2630 | */ |
2630 | * @param TIMx Timer instance |
| 2631 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
2631 | * @retval State of bit (1 or 0). |
| 2632 | { |
2632 | */ |
| 2633 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
2633 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) |
| 2634 | } |
2634 | { |
| 2635 | 2635 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); |
|
| 2636 | /** |
2636 | } |
| 2637 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
2637 | |
| 2638 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
2638 | /** |
| 2639 | * @param TIMx Timer instance |
2639 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
| 2640 | * @retval State of bit (1 or 0). |
2640 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
| 2641 | */ |
2641 | * @param TIMx Timer instance |
| 2642 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) |
2642 | * @retval None |
| 2643 | { |
2643 | */ |
| 2644 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); |
2644 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
| 2645 | } |
2645 | { |
| 2646 | 2646 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
|
| 2647 | /** |
2647 | } |
| 2648 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
2648 | |
| 2649 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
2649 | /** |
| 2650 | * @param TIMx Timer instance |
2650 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
| 2651 | * @retval None |
2651 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
| 2652 | */ |
2652 | * @param TIMx Timer instance |
| 2653 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
2653 | * @retval State of bit (1 or 0). |
| 2654 | { |
2654 | */ |
| 2655 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
2655 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) |
| 2656 | } |
2656 | { |
| 2657 | 2657 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); |
|
| 2658 | /** |
2658 | } |
| 2659 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
2659 | |
| 2660 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
2660 | /** |
| 2661 | * @param TIMx Timer instance |
2661 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
| 2662 | * @retval State of bit (1 or 0). |
2662 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
| 2663 | */ |
2663 | * @param TIMx Timer instance |
| 2664 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) |
2664 | * @retval None |
| 2665 | { |
2665 | */ |
| 2666 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); |
2666 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
| 2667 | } |
2667 | { |
| 2668 | 2668 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
|
| 2669 | /** |
2669 | } |
| 2670 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
2670 | |
| 2671 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
2671 | /** |
| 2672 | * @param TIMx Timer instance |
2672 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
| 2673 | * @retval None |
2673 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
| 2674 | */ |
2674 | * @param TIMx Timer instance |
| 2675 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
2675 | * @retval State of bit (1 or 0). |
| 2676 | { |
2676 | */ |
| 2677 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
2677 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) |
| 2678 | } |
2678 | { |
| 2679 | 2679 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); |
|
| 2680 | /** |
2680 | } |
| 2681 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
2681 | |
| 2682 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
2682 | /** |
| 2683 | * @param TIMx Timer instance |
2683 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
| 2684 | * @retval State of bit (1 or 0). |
2684 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
| 2685 | */ |
2685 | * @param TIMx Timer instance |
| 2686 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) |
2686 | * @retval None |
| 2687 | { |
2687 | */ |
| 2688 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); |
2688 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
| 2689 | } |
2689 | { |
| 2690 | 2690 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
|
| 2691 | /** |
2691 | } |
| 2692 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
2692 | |
| 2693 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
2693 | /** |
| 2694 | * @param TIMx Timer instance |
2694 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
| 2695 | * @retval None |
2695 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
| 2696 | */ |
2696 | * @param TIMx Timer instance |
| 2697 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
2697 | * @retval State of bit (1 or 0). |
| 2698 | { |
2698 | */ |
| 2699 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
2699 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) |
| 2700 | } |
2700 | { |
| 2701 | 2701 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); |
|
| 2702 | /** |
2702 | } |
| 2703 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
2703 | |
| 2704 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
2704 | /** |
| 2705 | * @param TIMx Timer instance |
2705 | * @brief Clear the trigger interrupt flag (TIF). |
| 2706 | * @retval State of bit (1 or 0). |
2706 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
| 2707 | */ |
2707 | * @param TIMx Timer instance |
| 2708 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) |
2708 | * @retval None |
| 2709 | { |
2709 | */ |
| 2710 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); |
2710 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
| 2711 | } |
2711 | { |
| 2712 | 2712 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
|
| 2713 | /** |
2713 | } |
| 2714 | * @brief Clear the trigger interrupt flag (TIF). |
2714 | |
| 2715 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
2715 | /** |
| 2716 | * @param TIMx Timer instance |
2716 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
| 2717 | * @retval None |
2717 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
| 2718 | */ |
2718 | * @param TIMx Timer instance |
| 2719 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
2719 | * @retval State of bit (1 or 0). |
| 2720 | { |
2720 | */ |
| 2721 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
2721 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) |
| 2722 | } |
2722 | { |
| 2723 | 2723 | return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); |
|
| 2724 | /** |
2724 | } |
| 2725 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
2725 | |
| 2726 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
2726 | /** |
| 2727 | * @param TIMx Timer instance |
2727 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
| 2728 | * @retval State of bit (1 or 0). |
2728 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
| 2729 | */ |
2729 | * @param TIMx Timer instance |
| 2730 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) |
2730 | * @retval None |
| 2731 | { |
2731 | */ |
| 2732 | return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); |
2732 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
| 2733 | } |
2733 | { |
| 2734 | 2734 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
|
| 2735 | /** |
2735 | } |
| 2736 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
2736 | |
| 2737 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
2737 | /** |
| 2738 | * @param TIMx Timer instance |
2738 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set |
| 2739 | * @retval None |
2739 | * (Capture/Compare 1 interrupt is pending). |
| 2740 | */ |
2740 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
| 2741 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
2741 | * @param TIMx Timer instance |
| 2742 | { |
2742 | * @retval State of bit (1 or 0). |
| 2743 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
2743 | */ |
| 2744 | } |
2744 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) |
| 2745 | 2745 | { |
|
| 2746 | /** |
2746 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); |
| 2747 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set |
2747 | } |
| 2748 | * (Capture/Compare 1 interrupt is pending). |
2748 | |
| 2749 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
2749 | /** |
| 2750 | * @param TIMx Timer instance |
2750 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
| 2751 | * @retval State of bit (1 or 0). |
2751 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
| 2752 | */ |
2752 | * @param TIMx Timer instance |
| 2753 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) |
2753 | * @retval None |
| 2754 | { |
2754 | */ |
| 2755 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); |
2755 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
| 2756 | } |
2756 | { |
| 2757 | 2757 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
|
| 2758 | /** |
2758 | } |
| 2759 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
2759 | |
| 2760 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
2760 | /** |
| 2761 | * @param TIMx Timer instance |
2761 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set |
| 2762 | * @retval None |
2762 | * (Capture/Compare 2 over-capture interrupt is pending). |
| 2763 | */ |
2763 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
| 2764 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
2764 | * @param TIMx Timer instance |
| 2765 | { |
2765 | * @retval State of bit (1 or 0). |
| 2766 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
2766 | */ |
| 2767 | } |
2767 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) |
| 2768 | 2768 | { |
|
| 2769 | /** |
2769 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); |
| 2770 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set |
2770 | } |
| 2771 | * (Capture/Compare 2 over-capture interrupt is pending). |
2771 | |
| 2772 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
2772 | /** |
| 2773 | * @param TIMx Timer instance |
2773 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
| 2774 | * @retval State of bit (1 or 0). |
2774 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
| 2775 | */ |
2775 | * @param TIMx Timer instance |
| 2776 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) |
2776 | * @retval None |
| 2777 | { |
2777 | */ |
| 2778 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); |
2778 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
| 2779 | } |
2779 | { |
| 2780 | 2780 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
|
| 2781 | /** |
2781 | } |
| 2782 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
2782 | |
| 2783 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
2783 | /** |
| 2784 | * @param TIMx Timer instance |
2784 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set |
| 2785 | * @retval None |
2785 | * (Capture/Compare 3 over-capture interrupt is pending). |
| 2786 | */ |
2786 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
| 2787 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
2787 | * @param TIMx Timer instance |
| 2788 | { |
2788 | * @retval State of bit (1 or 0). |
| 2789 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
2789 | */ |
| 2790 | } |
2790 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) |
| 2791 | 2791 | { |
|
| 2792 | /** |
2792 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); |
| 2793 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set |
2793 | } |
| 2794 | * (Capture/Compare 3 over-capture interrupt is pending). |
2794 | |
| 2795 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
2795 | /** |
| 2796 | * @param TIMx Timer instance |
2796 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
| 2797 | * @retval State of bit (1 or 0). |
2797 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
| 2798 | */ |
2798 | * @param TIMx Timer instance |
| 2799 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) |
2799 | * @retval None |
| 2800 | { |
2800 | */ |
| 2801 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); |
2801 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
| 2802 | } |
2802 | { |
| 2803 | 2803 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
|
| 2804 | /** |
2804 | } |
| 2805 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
2805 | |
| 2806 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
2806 | /** |
| 2807 | * @param TIMx Timer instance |
2807 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set |
| 2808 | * @retval None |
2808 | * (Capture/Compare 4 over-capture interrupt is pending). |
| 2809 | */ |
2809 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
| 2810 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
2810 | * @param TIMx Timer instance |
| 2811 | { |
2811 | * @retval State of bit (1 or 0). |
| 2812 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
2812 | */ |
| 2813 | } |
2813 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) |
| 2814 | 2814 | { |
|
| 2815 | /** |
2815 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); |
| 2816 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set |
2816 | } |
| 2817 | * (Capture/Compare 4 over-capture interrupt is pending). |
2817 | |
| 2818 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
2818 | /** |
| 2819 | * @param TIMx Timer instance |
2819 | * @} |
| 2820 | * @retval State of bit (1 or 0). |
2820 | */ |
| 2821 | */ |
2821 | |
| 2822 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) |
2822 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
| 2823 | { |
2823 | * @{ |
| 2824 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); |
2824 | */ |
| 2825 | } |
2825 | /** |
| 2826 | 2826 | * @brief Enable update interrupt (UIE). |
|
| 2827 | /** |
2827 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
| 2828 | * @} |
2828 | * @param TIMx Timer instance |
| 2829 | */ |
2829 | * @retval None |
| 2830 | 2830 | */ |
|
| 2831 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
2831 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
| 2832 | * @{ |
2832 | { |
| 2833 | */ |
2833 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
| 2834 | /** |
2834 | } |
| 2835 | * @brief Enable update interrupt (UIE). |
2835 | |
| 2836 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
2836 | /** |
| 2837 | * @param TIMx Timer instance |
2837 | * @brief Disable update interrupt (UIE). |
| 2838 | * @retval None |
2838 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
| 2839 | */ |
2839 | * @param TIMx Timer instance |
| 2840 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
2840 | * @retval None |
| 2841 | { |
2841 | */ |
| 2842 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
2842 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
| 2843 | } |
2843 | { |
| 2844 | 2844 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
|
| 2845 | /** |
2845 | } |
| 2846 | * @brief Disable update interrupt (UIE). |
2846 | |
| 2847 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
2847 | /** |
| 2848 | * @param TIMx Timer instance |
2848 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
| 2849 | * @retval None |
2849 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
| 2850 | */ |
2850 | * @param TIMx Timer instance |
| 2851 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
2851 | * @retval State of bit (1 or 0). |
| 2852 | { |
2852 | */ |
| 2853 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
2853 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) |
| 2854 | } |
2854 | { |
| 2855 | 2855 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); |
|
| 2856 | /** |
2856 | } |
| 2857 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
2857 | |
| 2858 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
2858 | /** |
| 2859 | * @param TIMx Timer instance |
2859 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
| 2860 | * @retval State of bit (1 or 0). |
2860 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
| 2861 | */ |
2861 | * @param TIMx Timer instance |
| 2862 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) |
2862 | * @retval None |
| 2863 | { |
2863 | */ |
| 2864 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); |
2864 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
| 2865 | } |
2865 | { |
| 2866 | 2866 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
|
| 2867 | /** |
2867 | } |
| 2868 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
2868 | |
| 2869 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
2869 | /** |
| 2870 | * @param TIMx Timer instance |
2870 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
| 2871 | * @retval None |
2871 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
| 2872 | */ |
2872 | * @param TIMx Timer instance |
| 2873 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
2873 | * @retval None |
| 2874 | { |
2874 | */ |
| 2875 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
2875 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
| 2876 | } |
2876 | { |
| 2877 | 2877 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
|
| 2878 | /** |
2878 | } |
| 2879 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
2879 | |
| 2880 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
2880 | /** |
| 2881 | * @param TIMx Timer instance |
2881 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
| 2882 | * @retval None |
2882 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
| 2883 | */ |
2883 | * @param TIMx Timer instance |
| 2884 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
2884 | * @retval State of bit (1 or 0). |
| 2885 | { |
2885 | */ |
| 2886 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
2886 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) |
| 2887 | } |
2887 | { |
| 2888 | 2888 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); |
|
| 2889 | /** |
2889 | } |
| 2890 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
2890 | |
| 2891 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
2891 | /** |
| 2892 | * @param TIMx Timer instance |
2892 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
| 2893 | * @retval State of bit (1 or 0). |
2893 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
| 2894 | */ |
2894 | * @param TIMx Timer instance |
| 2895 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) |
2895 | * @retval None |
| 2896 | { |
2896 | */ |
| 2897 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); |
2897 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
| 2898 | } |
2898 | { |
| 2899 | 2899 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
|
| 2900 | /** |
2900 | } |
| 2901 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
2901 | |
| 2902 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
2902 | /** |
| 2903 | * @param TIMx Timer instance |
2903 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
| 2904 | * @retval None |
2904 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
| 2905 | */ |
2905 | * @param TIMx Timer instance |
| 2906 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
2906 | * @retval None |
| 2907 | { |
2907 | */ |
| 2908 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
2908 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
| 2909 | } |
2909 | { |
| 2910 | 2910 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
|
| 2911 | /** |
2911 | } |
| 2912 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
2912 | |
| 2913 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
2913 | /** |
| 2914 | * @param TIMx Timer instance |
2914 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
| 2915 | * @retval None |
2915 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
| 2916 | */ |
2916 | * @param TIMx Timer instance |
| 2917 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
2917 | * @retval State of bit (1 or 0). |
| 2918 | { |
2918 | */ |
| 2919 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
2919 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) |
| 2920 | } |
2920 | { |
| 2921 | 2921 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); |
|
| 2922 | /** |
2922 | } |
| 2923 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
2923 | |
| 2924 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
2924 | /** |
| 2925 | * @param TIMx Timer instance |
2925 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
| 2926 | * @retval State of bit (1 or 0). |
2926 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
| 2927 | */ |
2927 | * @param TIMx Timer instance |
| 2928 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) |
2928 | * @retval None |
| 2929 | { |
2929 | */ |
| 2930 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); |
2930 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
| 2931 | } |
2931 | { |
| 2932 | 2932 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
|
| 2933 | /** |
2933 | } |
| 2934 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
2934 | |
| 2935 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
2935 | /** |
| 2936 | * @param TIMx Timer instance |
2936 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
| 2937 | * @retval None |
2937 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
| 2938 | */ |
2938 | * @param TIMx Timer instance |
| 2939 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
2939 | * @retval None |
| 2940 | { |
2940 | */ |
| 2941 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
2941 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
| 2942 | } |
2942 | { |
| 2943 | 2943 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
|
| 2944 | /** |
2944 | } |
| 2945 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
2945 | |
| 2946 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
2946 | /** |
| 2947 | * @param TIMx Timer instance |
2947 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
| 2948 | * @retval None |
2948 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
| 2949 | */ |
2949 | * @param TIMx Timer instance |
| 2950 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
2950 | * @retval State of bit (1 or 0). |
| 2951 | { |
2951 | */ |
| 2952 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
2952 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) |
| 2953 | } |
2953 | { |
| 2954 | 2954 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); |
|
| 2955 | /** |
2955 | } |
| 2956 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
2956 | |
| 2957 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
2957 | /** |
| 2958 | * @param TIMx Timer instance |
2958 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
| 2959 | * @retval State of bit (1 or 0). |
2959 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
| 2960 | */ |
2960 | * @param TIMx Timer instance |
| 2961 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) |
2961 | * @retval None |
| 2962 | { |
2962 | */ |
| 2963 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); |
2963 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
| 2964 | } |
2964 | { |
| 2965 | 2965 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
|
| 2966 | /** |
2966 | } |
| 2967 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
2967 | |
| 2968 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
2968 | /** |
| 2969 | * @param TIMx Timer instance |
2969 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
| 2970 | * @retval None |
2970 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
| 2971 | */ |
2971 | * @param TIMx Timer instance |
| 2972 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
2972 | * @retval None |
| 2973 | { |
2973 | */ |
| 2974 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
2974 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
| 2975 | } |
2975 | { |
| 2976 | 2976 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
|
| 2977 | /** |
2977 | } |
| 2978 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
2978 | |
| 2979 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
2979 | /** |
| 2980 | * @param TIMx Timer instance |
2980 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
| 2981 | * @retval None |
2981 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
| 2982 | */ |
2982 | * @param TIMx Timer instance |
| 2983 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
2983 | * @retval State of bit (1 or 0). |
| 2984 | { |
2984 | */ |
| 2985 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
2985 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) |
| 2986 | } |
2986 | { |
| 2987 | 2987 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); |
|
| 2988 | /** |
2988 | } |
| 2989 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
2989 | |
| 2990 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
2990 | /** |
| 2991 | * @param TIMx Timer instance |
2991 | * @brief Enable trigger interrupt (TIE). |
| 2992 | * @retval State of bit (1 or 0). |
2992 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
| 2993 | */ |
2993 | * @param TIMx Timer instance |
| 2994 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) |
2994 | * @retval None |
| 2995 | { |
2995 | */ |
| 2996 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); |
2996 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
| 2997 | } |
2997 | { |
| 2998 | 2998 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
|
| 2999 | /** |
2999 | } |
| 3000 | * @brief Enable trigger interrupt (TIE). |
3000 | |
| 3001 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
3001 | /** |
| 3002 | * @param TIMx Timer instance |
3002 | * @brief Disable trigger interrupt (TIE). |
| 3003 | * @retval None |
3003 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
| 3004 | */ |
3004 | * @param TIMx Timer instance |
| 3005 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
3005 | * @retval None |
| 3006 | { |
3006 | */ |
| 3007 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
3007 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
| 3008 | } |
3008 | { |
| 3009 | 3009 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
|
| 3010 | /** |
3010 | } |
| 3011 | * @brief Disable trigger interrupt (TIE). |
3011 | |
| 3012 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
3012 | /** |
| 3013 | * @param TIMx Timer instance |
3013 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
| 3014 | * @retval None |
3014 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
| 3015 | */ |
3015 | * @param TIMx Timer instance |
| 3016 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
3016 | * @retval State of bit (1 or 0). |
| 3017 | { |
3017 | */ |
| 3018 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
3018 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) |
| 3019 | } |
3019 | { |
| 3020 | 3020 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); |
|
| 3021 | /** |
3021 | } |
| 3022 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
3022 | |
| 3023 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
3023 | /** |
| 3024 | * @param TIMx Timer instance |
3024 | * @} |
| 3025 | * @retval State of bit (1 or 0). |
3025 | */ |
| 3026 | */ |
3026 | |
| 3027 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) |
3027 | /** @defgroup TIM_LL_EF_DMA_Management DMA Management |
| 3028 | { |
3028 | * @{ |
| 3029 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); |
3029 | */ |
| 3030 | } |
3030 | /** |
| 3031 | 3031 | * @brief Enable update DMA request (UDE). |
|
| 3032 | /** |
3032 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
| 3033 | * @} |
3033 | * @param TIMx Timer instance |
| 3034 | */ |
3034 | * @retval None |
| 3035 | 3035 | */ |
|
| 3036 | /** @defgroup TIM_LL_EF_DMA_Management DMA-Management |
3036 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| 3037 | * @{ |
3037 | { |
| 3038 | */ |
3038 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
| 3039 | /** |
3039 | } |
| 3040 | * @brief Enable update DMA request (UDE). |
3040 | |
| 3041 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
3041 | /** |
| 3042 | * @param TIMx Timer instance |
3042 | * @brief Disable update DMA request (UDE). |
| 3043 | * @retval None |
3043 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
| 3044 | */ |
3044 | * @param TIMx Timer instance |
| 3045 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
3045 | * @retval None |
| 3046 | { |
3046 | */ |
| 3047 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
3047 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| 3048 | } |
3048 | { |
| 3049 | 3049 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
|
| 3050 | /** |
3050 | } |
| 3051 | * @brief Disable update DMA request (UDE). |
3051 | |
| 3052 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
3052 | /** |
| 3053 | * @param TIMx Timer instance |
3053 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
| 3054 | * @retval None |
3054 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
| 3055 | */ |
3055 | * @param TIMx Timer instance |
| 3056 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
3056 | * @retval State of bit (1 or 0). |
| 3057 | { |
3057 | */ |
| 3058 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
3058 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) |
| 3059 | } |
3059 | { |
| 3060 | 3060 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); |
|
| 3061 | /** |
3061 | } |
| 3062 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
3062 | |
| 3063 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
3063 | /** |
| 3064 | * @param TIMx Timer instance |
3064 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
| 3065 | * @retval State of bit (1 or 0). |
3065 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
| 3066 | */ |
3066 | * @param TIMx Timer instance |
| 3067 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) |
3067 | * @retval None |
| 3068 | { |
3068 | */ |
| 3069 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); |
3069 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
| 3070 | } |
3070 | { |
| 3071 | 3071 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
|
| 3072 | /** |
3072 | } |
| 3073 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
3073 | |
| 3074 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
3074 | /** |
| 3075 | * @param TIMx Timer instance |
3075 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
| 3076 | * @retval None |
3076 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
| 3077 | */ |
3077 | * @param TIMx Timer instance |
| 3078 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
3078 | * @retval None |
| 3079 | { |
3079 | */ |
| 3080 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
3080 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
| 3081 | } |
3081 | { |
| 3082 | 3082 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
|
| 3083 | /** |
3083 | } |
| 3084 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
3084 | |
| 3085 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
3085 | /** |
| 3086 | * @param TIMx Timer instance |
3086 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
| 3087 | * @retval None |
3087 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
| 3088 | */ |
3088 | * @param TIMx Timer instance |
| 3089 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
3089 | * @retval State of bit (1 or 0). |
| 3090 | { |
3090 | */ |
| 3091 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
3091 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) |
| 3092 | } |
3092 | { |
| 3093 | 3093 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); |
|
| 3094 | /** |
3094 | } |
| 3095 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
3095 | |
| 3096 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
3096 | /** |
| 3097 | * @param TIMx Timer instance |
3097 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
| 3098 | * @retval State of bit (1 or 0). |
3098 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
| 3099 | */ |
3099 | * @param TIMx Timer instance |
| 3100 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) |
3100 | * @retval None |
| 3101 | { |
3101 | */ |
| 3102 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); |
3102 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
| 3103 | } |
3103 | { |
| 3104 | 3104 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
|
| 3105 | /** |
3105 | } |
| 3106 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
3106 | |
| 3107 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
3107 | /** |
| 3108 | * @param TIMx Timer instance |
3108 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
| 3109 | * @retval None |
3109 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
| 3110 | */ |
3110 | * @param TIMx Timer instance |
| 3111 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
3111 | * @retval None |
| 3112 | { |
3112 | */ |
| 3113 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
3113 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
| 3114 | } |
3114 | { |
| 3115 | 3115 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
|
| 3116 | /** |
3116 | } |
| 3117 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
3117 | |
| 3118 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
3118 | /** |
| 3119 | * @param TIMx Timer instance |
3119 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
| 3120 | * @retval None |
3120 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
| 3121 | */ |
3121 | * @param TIMx Timer instance |
| 3122 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
3122 | * @retval State of bit (1 or 0). |
| 3123 | { |
3123 | */ |
| 3124 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
3124 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) |
| 3125 | } |
3125 | { |
| 3126 | 3126 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); |
|
| 3127 | /** |
3127 | } |
| 3128 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
3128 | |
| 3129 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
3129 | /** |
| 3130 | * @param TIMx Timer instance |
3130 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
| 3131 | * @retval State of bit (1 or 0). |
3131 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
| 3132 | */ |
3132 | * @param TIMx Timer instance |
| 3133 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) |
3133 | * @retval None |
| 3134 | { |
3134 | */ |
| 3135 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); |
3135 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
| 3136 | } |
3136 | { |
| 3137 | 3137 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
|
| 3138 | /** |
3138 | } |
| 3139 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
3139 | |
| 3140 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
3140 | /** |
| 3141 | * @param TIMx Timer instance |
3141 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
| 3142 | * @retval None |
3142 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
| 3143 | */ |
3143 | * @param TIMx Timer instance |
| 3144 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
3144 | * @retval None |
| 3145 | { |
3145 | */ |
| 3146 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
3146 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
| 3147 | } |
3147 | { |
| 3148 | 3148 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
|
| 3149 | /** |
3149 | } |
| 3150 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
3150 | |
| 3151 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
3151 | /** |
| 3152 | * @param TIMx Timer instance |
3152 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
| 3153 | * @retval None |
3153 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
| 3154 | */ |
3154 | * @param TIMx Timer instance |
| 3155 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
3155 | * @retval State of bit (1 or 0). |
| 3156 | { |
3156 | */ |
| 3157 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
3157 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) |
| 3158 | } |
3158 | { |
| 3159 | 3159 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); |
|
| 3160 | /** |
3160 | } |
| 3161 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
3161 | |
| 3162 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
3162 | /** |
| 3163 | * @param TIMx Timer instance |
3163 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
| 3164 | * @retval State of bit (1 or 0). |
3164 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
| 3165 | */ |
3165 | * @param TIMx Timer instance |
| 3166 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) |
3166 | * @retval None |
| 3167 | { |
3167 | */ |
| 3168 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); |
3168 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
| 3169 | } |
3169 | { |
| 3170 | 3170 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
|
| 3171 | /** |
3171 | } |
| 3172 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
3172 | |
| 3173 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
3173 | /** |
| 3174 | * @param TIMx Timer instance |
3174 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
| 3175 | * @retval None |
3175 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
| 3176 | */ |
3176 | * @param TIMx Timer instance |
| 3177 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
3177 | * @retval None |
| 3178 | { |
3178 | */ |
| 3179 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
3179 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
| 3180 | } |
3180 | { |
| 3181 | 3181 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
|
| 3182 | /** |
3182 | } |
| 3183 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
3183 | |
| 3184 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
3184 | /** |
| 3185 | * @param TIMx Timer instance |
3185 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
| 3186 | * @retval None |
3186 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
| 3187 | */ |
3187 | * @param TIMx Timer instance |
| 3188 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
3188 | * @retval State of bit (1 or 0). |
| 3189 | { |
3189 | */ |
| 3190 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
3190 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) |
| 3191 | } |
3191 | { |
| 3192 | 3192 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); |
|
| 3193 | /** |
3193 | } |
| 3194 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
3194 | |
| 3195 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
3195 | /** |
| 3196 | * @param TIMx Timer instance |
3196 | * @brief Enable trigger interrupt (TDE). |
| 3197 | * @retval State of bit (1 or 0). |
3197 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
| 3198 | */ |
3198 | * @param TIMx Timer instance |
| 3199 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) |
3199 | * @retval None |
| 3200 | { |
3200 | */ |
| 3201 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); |
3201 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
| 3202 | } |
3202 | { |
| 3203 | 3203 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
|
| 3204 | /** |
3204 | } |
| 3205 | * @brief Enable trigger interrupt (TDE). |
3205 | |
| 3206 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
3206 | /** |
| 3207 | * @param TIMx Timer instance |
3207 | * @brief Disable trigger interrupt (TDE). |
| 3208 | * @retval None |
3208 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
| 3209 | */ |
3209 | * @param TIMx Timer instance |
| 3210 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
3210 | * @retval None |
| 3211 | { |
3211 | */ |
| 3212 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
3212 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
| 3213 | } |
3213 | { |
| 3214 | 3214 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
|
| 3215 | /** |
3215 | } |
| 3216 | * @brief Disable trigger interrupt (TDE). |
3216 | |
| 3217 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
3217 | /** |
| 3218 | * @param TIMx Timer instance |
3218 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
| 3219 | * @retval None |
3219 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
| 3220 | */ |
3220 | * @param TIMx Timer instance |
| 3221 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
3221 | * @retval State of bit (1 or 0). |
| 3222 | { |
3222 | */ |
| 3223 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
3223 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) |
| 3224 | } |
3224 | { |
| 3225 | 3225 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); |
|
| 3226 | /** |
3226 | } |
| 3227 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
3227 | |
| 3228 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
3228 | /** |
| 3229 | * @param TIMx Timer instance |
3229 | * @} |
| 3230 | * @retval State of bit (1 or 0). |
3230 | */ |
| 3231 | */ |
3231 | |
| 3232 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) |
3232 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
| 3233 | { |
3233 | * @{ |
| 3234 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); |
3234 | */ |
| 3235 | } |
3235 | /** |
| 3236 | 3236 | * @brief Generate an update event. |
|
| 3237 | /** |
3237 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
| 3238 | * @} |
3238 | * @param TIMx Timer instance |
| 3239 | */ |
3239 | * @retval None |
| 3240 | 3240 | */ |
|
| 3241 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
3241 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
| 3242 | * @{ |
3242 | { |
| 3243 | */ |
3243 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
| 3244 | /** |
3244 | } |
| 3245 | * @brief Generate an update event. |
3245 | |
| 3246 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
3246 | /** |
| 3247 | * @param TIMx Timer instance |
3247 | * @brief Generate Capture/Compare 1 event. |
| 3248 | * @retval None |
3248 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
| 3249 | */ |
3249 | * @param TIMx Timer instance |
| 3250 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
3250 | * @retval None |
| 3251 | { |
3251 | */ |
| 3252 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
3252 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
| 3253 | } |
3253 | { |
| 3254 | 3254 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
|
| 3255 | /** |
3255 | } |
| 3256 | * @brief Generate Capture/Compare 1 event. |
3256 | |
| 3257 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
3257 | /** |
| 3258 | * @param TIMx Timer instance |
3258 | * @brief Generate Capture/Compare 2 event. |
| 3259 | * @retval None |
3259 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
| 3260 | */ |
3260 | * @param TIMx Timer instance |
| 3261 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
3261 | * @retval None |
| 3262 | { |
3262 | */ |
| 3263 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
3263 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
| 3264 | } |
3264 | { |
| 3265 | 3265 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
|
| 3266 | /** |
3266 | } |
| 3267 | * @brief Generate Capture/Compare 2 event. |
3267 | |
| 3268 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
3268 | /** |
| 3269 | * @param TIMx Timer instance |
3269 | * @brief Generate Capture/Compare 3 event. |
| 3270 | * @retval None |
3270 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
| 3271 | */ |
3271 | * @param TIMx Timer instance |
| 3272 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
3272 | * @retval None |
| 3273 | { |
3273 | */ |
| 3274 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
3274 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
| 3275 | } |
3275 | { |
| 3276 | 3276 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
|
| 3277 | /** |
3277 | } |
| 3278 | * @brief Generate Capture/Compare 3 event. |
3278 | |
| 3279 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
3279 | /** |
| 3280 | * @param TIMx Timer instance |
3280 | * @brief Generate Capture/Compare 4 event. |
| 3281 | * @retval None |
3281 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
| 3282 | */ |
3282 | * @param TIMx Timer instance |
| 3283 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
3283 | * @retval None |
| 3284 | { |
3284 | */ |
| 3285 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
3285 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
| 3286 | } |
3286 | { |
| 3287 | 3287 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
|
| 3288 | /** |
3288 | } |
| 3289 | * @brief Generate Capture/Compare 4 event. |
3289 | |
| 3290 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
3290 | /** |
| 3291 | * @param TIMx Timer instance |
3291 | * @brief Generate trigger event. |
| 3292 | * @retval None |
3292 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
| 3293 | */ |
3293 | * @param TIMx Timer instance |
| 3294 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
3294 | * @retval None |
| 3295 | { |
3295 | */ |
| 3296 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
3296 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
| 3297 | } |
3297 | { |
| 3298 | 3298 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
|
| 3299 | /** |
3299 | } |
| 3300 | * @brief Generate trigger event. |
3300 | |
| 3301 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
3301 | /** |
| 3302 | * @param TIMx Timer instance |
3302 | * @} |
| 3303 | * @retval None |
3303 | */ |
| 3304 | */ |
3304 | |
| 3305 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
3305 | #if defined(USE_FULL_LL_DRIVER) |
| 3306 | { |
3306 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
| 3307 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
3307 | * @{ |
| 3308 | } |
3308 | */ |
| 3309 | 3309 | ||
| 3310 | /** |
3310 | ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); |
| 3311 | * @} |
3311 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
| 3312 | */ |
3312 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); |
| 3313 | 3313 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
|
| 3314 | #if defined(USE_FULL_LL_DRIVER) |
3314 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
| 3315 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
3315 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| 3316 | * @{ |
3316 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
| 3317 | */ |
3317 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
| 3318 | 3318 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
|
| 3319 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); |
3319 | /** |
| 3320 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
3320 | * @} |
| 3321 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); |
3321 | */ |
| 3322 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
3322 | #endif /* USE_FULL_LL_DRIVER */ |
| 3323 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
3323 | |
| 3324 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
3324 | /** |
| 3325 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
3325 | * @} |
| 3326 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
3326 | */ |
| 3327 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
3327 | |
| 3328 | /** |
3328 | /** |
| 3329 | * @} |
3329 | * @} |
| 3330 | */ |
3330 | */ |
| 3331 | #endif /* USE_FULL_LL_DRIVER */ |
3331 | |
| 3332 | 3332 | #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */ |
|
| 3333 | /** |
3333 | |
| 3334 | * @} |
3334 | /** |
| 3335 | */ |
3335 | * @} |
| 3336 | 3336 | */ |
|
| 3337 | /** |
3337 | |
| 3338 | * @} |
3338 | #ifdef __cplusplus |
| 3339 | */ |
3339 | } |
| 3340 | 3340 | #endif |
|
| 3341 | #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */ |
3341 | |
| 3342 | 3342 | #endif /* __STM32L1xx_LL_TIM_H */ |
|
| 3343 | /** |
- | |
| 3344 | * @} |
- | |
| 3345 | */ |
- | |
| 3346 | - | ||
| 3347 | #ifdef __cplusplus |
- | |
| 3348 | } |
- | |
| 3349 | #endif |
- | |
| 3350 | - | ||
| 3351 | #endif /* __STM32L1xx_LL_TIM_H */ |
- | |
| 3352 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |