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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_system.h |
3 | * @file stm32l1xx_ll_system.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of SYSTEM LL module. |
5 | * @brief Header file of SYSTEM LL module. |
| 6 | @verbatim |
6 | * |
| 7 | ============================================================================== |
7 | ****************************************************************************** |
| 8 | ##### How to use this driver ##### |
8 | * @attention |
| 9 | ============================================================================== |
9 | * |
| 10 | [..] |
10 | * Copyright (c) 2017 STMicroelectronics. |
| 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
11 | * All rights reserved. |
| 12 | used by user: |
12 | * |
| 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
13 | * This software is licensed under terms that can be found in the LICENSE file |
| 14 | (+) Access to DBGCMU registers |
14 | * in the root directory of this software component. |
| 15 | (+) Access to SYSCFG registers |
15 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 16 | (+) Access to Routing Interfaces registers |
16 | * |
| 17 | 17 | ****************************************************************************** |
|
| 18 | @endverbatim |
18 | @verbatim |
| 19 | ****************************************************************************** |
19 | ============================================================================== |
| 20 | * @attention |
20 | ##### How to use this driver ##### |
| 21 | * |
21 | ============================================================================== |
| 22 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
22 | [..] |
| 23 | * All rights reserved.</center></h2> |
23 | The LL SYSTEM driver contains a set of generic APIs that can be |
| 24 | * |
24 | used by user: |
| 25 | * This software component is licensed by ST under BSD 3-Clause license, |
25 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
| 26 | * the "License"; You may not use this file except in compliance with the |
26 | (+) Access to DBGCMU registers |
| 27 | * License. You may obtain a copy of the License at: |
27 | (+) Access to SYSCFG registers |
| 28 | * opensource.org/licenses/BSD-3-Clause |
28 | (+) Access to Routing Interfaces registers |
| 29 | * |
29 | |
| 30 | ****************************************************************************** |
30 | @endverbatim |
| 31 | */ |
31 | ****************************************************************************** |
| 32 | 32 | */ |
|
| 33 | /* Define to prevent recursive inclusion -------------------------------------*/ |
33 | |
| 34 | #ifndef __STM32L1xx_LL_SYSTEM_H |
34 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 35 | #define __STM32L1xx_LL_SYSTEM_H |
35 | #ifndef __STM32L1xx_LL_SYSTEM_H |
| 36 | 36 | #define __STM32L1xx_LL_SYSTEM_H |
|
| 37 | #ifdef __cplusplus |
37 | |
| 38 | extern "C" { |
38 | #ifdef __cplusplus |
| 39 | #endif |
39 | extern "C" { |
| 40 | 40 | #endif |
|
| 41 | /* Includes ------------------------------------------------------------------*/ |
41 | |
| 42 | #include "stm32l1xx.h" |
42 | /* Includes ------------------------------------------------------------------*/ |
| 43 | 43 | #include "stm32l1xx.h" |
|
| 44 | /** @addtogroup STM32L1xx_LL_Driver |
44 | |
| 45 | * @{ |
45 | /** @addtogroup STM32L1xx_LL_Driver |
| 46 | */ |
46 | * @{ |
| 47 | 47 | */ |
|
| 48 | #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) |
48 | |
| 49 | 49 | #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) |
|
| 50 | /** @defgroup SYSTEM_LL SYSTEM |
50 | |
| 51 | * @{ |
51 | /** @defgroup SYSTEM_LL SYSTEM |
| 52 | */ |
52 | * @{ |
| 53 | 53 | */ |
|
| 54 | /* Private types -------------------------------------------------------------*/ |
54 | |
| 55 | /* Private variables ---------------------------------------------------------*/ |
55 | /* Private types -------------------------------------------------------------*/ |
| 56 | 56 | /* Private variables ---------------------------------------------------------*/ |
|
| 57 | /* Private constants ---------------------------------------------------------*/ |
57 | |
| 58 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
58 | /* Private constants ---------------------------------------------------------*/ |
| 59 | * @{ |
59 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
| 60 | */ |
60 | * @{ |
| 61 | 61 | */ |
|
| 62 | /** |
62 | |
| 63 | * @brief Power-down in Run mode Flash key |
63 | /** |
| 64 | */ |
64 | * @brief Power-down in Run mode Flash key |
| 65 | #define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */ |
65 | */ |
| 66 | #define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 |
66 | #define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */ |
| 67 | to unlock the RUN_PD bit in FLASH_ACR */ |
67 | #define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 |
| 68 | 68 | to unlock the RUN_PD bit in FLASH_ACR */ |
|
| 69 | /** |
69 | |
| 70 | * @} |
70 | /** |
| 71 | */ |
71 | * @} |
| 72 | 72 | */ |
|
| 73 | /* Private macros ------------------------------------------------------------*/ |
73 | |
| 74 | 74 | /* Private macros ------------------------------------------------------------*/ |
|
| 75 | /* Exported types ------------------------------------------------------------*/ |
75 | |
| 76 | /* Exported constants --------------------------------------------------------*/ |
76 | /* Exported types ------------------------------------------------------------*/ |
| 77 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
77 | /* Exported constants --------------------------------------------------------*/ |
| 78 | * @{ |
78 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
| 79 | */ |
79 | * @{ |
| 80 | 80 | */ |
|
| 81 | /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP |
81 | |
| 82 | * @{ |
82 | /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP |
| 83 | */ |
83 | * @{ |
| 84 | #define LL_SYSCFG_REMAP_FLASH (0x00000000U) /*<! Main Flash memory mapped at 0x00000000 */ |
84 | */ |
| 85 | #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*<! System Flash memory mapped at 0x00000000 */ |
85 | #define LL_SYSCFG_REMAP_FLASH (0x00000000U) /*<! Main Flash memory mapped at 0x00000000 */ |
| 86 | #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*<! Embedded SRAM mapped at 0x00000000 */ |
86 | #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*<! System Flash memory mapped at 0x00000000 */ |
| 87 | #if defined(FSMC_R_BASE) |
87 | #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*<! Embedded SRAM mapped at 0x00000000 */ |
| 88 | #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*<! FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ |
88 | #if defined(FSMC_R_BASE) |
| 89 | #endif /* FSMC_R_BASE */ |
89 | #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*<! FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ |
| 90 | /** |
90 | #endif /* FSMC_R_BASE */ |
| 91 | * @} |
91 | /** |
| 92 | */ |
92 | * @} |
| 93 | 93 | */ |
|
| 94 | /** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE |
94 | |
| 95 | * @{ |
95 | /** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE |
| 96 | */ |
96 | * @{ |
| 97 | #define LL_SYSCFG_BOOTMODE_FLASH (0x00000000U) /*<! Main Flash memory boot mode */ |
97 | */ |
| 98 | #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_MEMRMP_BOOT_MODE_0 /*<! System Flash memory boot mode */ |
98 | #define LL_SYSCFG_BOOTMODE_FLASH (0x00000000U) /*<! Main Flash memory boot mode */ |
| 99 | #if defined(FSMC_BANK1) |
99 | #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_MEMRMP_BOOT_MODE_0 /*<! System Flash memory boot mode */ |
| 100 | #define LL_SYSCFG_BOOTMODE_FSMC SYSCFG_MEMRMP_BOOT_MODE_1 /*<! FSMC boot mode */ |
100 | #if defined(FSMC_BANK1) |
| 101 | #endif /* FSMC_BANK1 */ |
101 | #define LL_SYSCFG_BOOTMODE_FSMC SYSCFG_MEMRMP_BOOT_MODE_1 /*<! FSMC boot mode */ |
| 102 | #define LL_SYSCFG_BOOTMODE_SRAM SYSCFG_MEMRMP_BOOT_MODE /*<! Embedded SRAM boot mode */ |
102 | #endif /* FSMC_BANK1 */ |
| 103 | /** |
103 | #define LL_SYSCFG_BOOTMODE_SRAM SYSCFG_MEMRMP_BOOT_MODE /*<! Embedded SRAM boot mode */ |
| 104 | * @} |
104 | /** |
| 105 | */ |
105 | * @} |
| 106 | 106 | */ |
|
| 107 | #if defined(LCD) |
107 | |
| 108 | /** @defgroup SYSTEM_LL_EC_LCDCAPA SYSCFG LCD capacitance connection |
108 | #if defined(LCD) |
| 109 | * @{ |
109 | /** @defgroup SYSTEM_LL_EC_LCDCAPA SYSCFG LCD capacitance connection |
| 110 | */ |
110 | * @{ |
| 111 | #define LL_SYSCFG_LCDCAPA_PB2 SYSCFG_PMC_LCD_CAPA_0 /*<! controls the connection of VLCDrail2 on PB2/LCD_VCAP2 */ |
111 | */ |
| 112 | #define LL_SYSCFG_LCDCAPA_PB12 SYSCFG_PMC_LCD_CAPA_1 /*<! controls the connection of VLCDrail1 on PB12/LCD_VCAP1 */ |
112 | #define LL_SYSCFG_LCDCAPA_PB2 SYSCFG_PMC_LCD_CAPA_0 /*<! controls the connection of VLCDrail2 on PB2/LCD_VCAP2 */ |
| 113 | #define LL_SYSCFG_LCDCAPA_PB0 SYSCFG_PMC_LCD_CAPA_2 /*<! controls the connection of VLCDrail3 on PB0/LCD_VCAP3 */ |
113 | #define LL_SYSCFG_LCDCAPA_PB12 SYSCFG_PMC_LCD_CAPA_1 /*<! controls the connection of VLCDrail1 on PB12/LCD_VCAP1 */ |
| 114 | #define LL_SYSCFG_LCDCAPA_PE11 SYSCFG_PMC_LCD_CAPA_3 /*<! controls the connection of VLCDrail1 on PE11/LCD_VCAP1 */ |
114 | #define LL_SYSCFG_LCDCAPA_PB0 SYSCFG_PMC_LCD_CAPA_2 /*<! controls the connection of VLCDrail3 on PB0/LCD_VCAP3 */ |
| 115 | #define LL_SYSCFG_LCDCAPA_PE12 SYSCFG_PMC_LCD_CAPA_4 /*<! controls the connection of VLCDrail3 on PE12/LCD_VCAP3 */ |
115 | #define LL_SYSCFG_LCDCAPA_PE11 SYSCFG_PMC_LCD_CAPA_3 /*<! controls the connection of VLCDrail1 on PE11/LCD_VCAP1 */ |
| 116 | /** |
116 | #define LL_SYSCFG_LCDCAPA_PE12 SYSCFG_PMC_LCD_CAPA_4 /*<! controls the connection of VLCDrail3 on PE12/LCD_VCAP3 */ |
| 117 | * @} |
117 | /** |
| 118 | */ |
118 | * @} |
| 119 | 119 | */ |
|
| 120 | #endif /* LCD */ |
120 | |
| 121 | 121 | #endif /* LCD */ |
|
| 122 | /** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT |
122 | |
| 123 | * @{ |
123 | /** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT |
| 124 | */ |
124 | * @{ |
| 125 | #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ |
125 | */ |
| 126 | #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ |
126 | #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ |
| 127 | #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ |
127 | #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ |
| 128 | #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ |
128 | #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ |
| 129 | #if defined(GPIOE) |
129 | #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ |
| 130 | #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ |
130 | #if defined(GPIOE) |
| 131 | #endif /* GPIOE */ |
131 | #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ |
| 132 | #if defined(GPIOF) |
132 | #endif /* GPIOE */ |
| 133 | #define LL_SYSCFG_EXTI_PORTF 6U /*!< EXTI PORT F */ |
133 | #if defined(GPIOF) |
| 134 | #endif /* GPIOF */ |
134 | #define LL_SYSCFG_EXTI_PORTF 6U /*!< EXTI PORT F */ |
| 135 | #if defined(GPIOG) |
135 | #endif /* GPIOF */ |
| 136 | #define LL_SYSCFG_EXTI_PORTG 7U /*!< EXTI PORT G */ |
136 | #if defined(GPIOG) |
| 137 | #endif /* GPIOG */ |
137 | #define LL_SYSCFG_EXTI_PORTG 7U /*!< EXTI PORT G */ |
| 138 | #define LL_SYSCFG_EXTI_PORTH 5U /*!< EXTI PORT H */ |
138 | #endif /* GPIOG */ |
| 139 | /** |
139 | #define LL_SYSCFG_EXTI_PORTH 5U /*!< EXTI PORT H */ |
| 140 | * @} |
140 | /** |
| 141 | */ |
141 | * @} |
| 142 | 142 | */ |
|
| 143 | /** @addtogroup SYSTEM_LL_EC_SYSCFG EXTI LINE |
143 | |
| 144 | * @{ |
144 | /** @addtogroup SYSTEM_LL_EC_SYSCFG EXTI LINE |
| 145 | */ |
145 | * @{ |
| 146 | #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */ |
146 | */ |
| 147 | #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */ |
147 | #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */ |
| 148 | #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */ |
148 | #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */ |
| 149 | #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */ |
149 | #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */ |
| 150 | #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */ |
150 | #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */ |
| 151 | #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */ |
151 | #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */ |
| 152 | #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */ |
152 | #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */ |
| 153 | #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */ |
153 | #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */ |
| 154 | #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */ |
154 | #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */ |
| 155 | #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */ |
155 | #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */ |
| 156 | #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */ |
156 | #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */ |
| 157 | #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */ |
157 | #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */ |
| 158 | #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */ |
158 | #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */ |
| 159 | #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */ |
159 | #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */ |
| 160 | #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */ |
160 | #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */ |
| 161 | #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */ |
161 | #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */ |
| 162 | /** |
162 | #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */ |
| 163 | * @} |
163 | /** |
| 164 | */ |
164 | * @} |
| 165 | 165 | */ |
|
| 166 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
166 | |
| 167 | * @{ |
167 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
| 168 | */ |
168 | * @{ |
| 169 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
169 | */ |
| 170 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
170 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
| 171 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
171 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
| 172 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
172 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
| 173 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
173 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
| 174 | /** |
174 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
| 175 | * @} |
175 | /** |
| 176 | */ |
176 | * @} |
| 177 | 177 | */ |
|
| 178 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
178 | |
| 179 | * @{ |
179 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
| 180 | */ |
180 | * @{ |
| 181 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
181 | */ |
| 182 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
182 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
| 183 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
183 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
| 184 | #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
184 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
| 185 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
185 | #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| 186 | #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ |
186 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
| 187 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
187 | #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ |
| 188 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
188 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
| 189 | #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
189 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
| 190 | #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Counter stopped when Core is halted */ |
190 | #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| 191 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
191 | #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Counter stopped when Core is halted */ |
| 192 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
192 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
| 193 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
193 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
| 194 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
194 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
| 195 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
195 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| 196 | /** |
196 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
| 197 | * @} |
197 | /** |
| 198 | */ |
198 | * @} |
| 199 | 199 | */ |
|
| 200 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
200 | |
| 201 | * @{ |
201 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
| 202 | */ |
202 | * @{ |
| 203 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
203 | */ |
| 204 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
204 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
| 205 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
205 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
| 206 | /** |
206 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
| 207 | * @} |
207 | /** |
| 208 | */ |
208 | * @} |
| 209 | 209 | */ |
|
| 210 | /** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection |
210 | |
| 211 | * @{ |
211 | /** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection |
| 212 | */ |
212 | * @{ |
| 213 | #define LL_RI_TIM_SELECT_NONE (0x00000000U) /*!< No timer selected */ |
213 | */ |
| 214 | #define LL_RI_TIM_SELECT_TIM2 RI_ICR_TIM_0 /*!< Timer 2 selected */ |
214 | #define LL_RI_TIM_SELECT_NONE (0x00000000U) /*!< No timer selected */ |
| 215 | #define LL_RI_TIM_SELECT_TIM3 RI_ICR_TIM_1 /*!< Timer 3 selected */ |
215 | #define LL_RI_TIM_SELECT_TIM2 RI_ICR_TIM_0 /*!< Timer 2 selected */ |
| 216 | #define LL_RI_TIM_SELECT_TIM4 RI_ICR_TIM /*!< Timer 4 selected */ |
216 | #define LL_RI_TIM_SELECT_TIM3 RI_ICR_TIM_1 /*!< Timer 3 selected */ |
| 217 | /** |
217 | #define LL_RI_TIM_SELECT_TIM4 RI_ICR_TIM /*!< Timer 4 selected */ |
| 218 | * @} |
218 | /** |
| 219 | */ |
219 | * @} |
| 220 | 220 | */ |
|
| 221 | /** @defgroup SYSTEM_LL_EC_INPUTCAPTURE RI Input Capture number |
221 | |
| 222 | * @{ |
222 | /** @defgroup SYSTEM_LL_EC_INPUTCAPTURE RI Input Capture number |
| 223 | */ |
223 | * @{ |
| 224 | #define LL_RI_INPUTCAPTURE_1 (RI_ICR_IC1 | RI_ICR_IC1OS) /*!< Input Capture 1 select output */ |
224 | */ |
| 225 | #define LL_RI_INPUTCAPTURE_2 (RI_ICR_IC2 | RI_ICR_IC2OS) /*!< Input Capture 2 select output */ |
225 | #define LL_RI_INPUTCAPTURE_1 (RI_ICR_IC1 | RI_ICR_IC1OS) /*!< Input Capture 1 select output */ |
| 226 | #define LL_RI_INPUTCAPTURE_3 (RI_ICR_IC3 | RI_ICR_IC3OS) /*!< Input Capture 3 select output */ |
226 | #define LL_RI_INPUTCAPTURE_2 (RI_ICR_IC2 | RI_ICR_IC2OS) /*!< Input Capture 2 select output */ |
| 227 | #define LL_RI_INPUTCAPTURE_4 (RI_ICR_IC4 | RI_ICR_IC4OS) /*!< Input Capture 4 select output */ |
227 | #define LL_RI_INPUTCAPTURE_3 (RI_ICR_IC3 | RI_ICR_IC3OS) /*!< Input Capture 3 select output */ |
| 228 | /** |
228 | #define LL_RI_INPUTCAPTURE_4 (RI_ICR_IC4 | RI_ICR_IC4OS) /*!< Input Capture 4 select output */ |
| 229 | * @} |
229 | /** |
| 230 | */ |
230 | * @} |
| 231 | 231 | */ |
|
| 232 | /** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing |
232 | |
| 233 | * @{ |
233 | /** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing |
| 234 | */ |
234 | * @{ |
| 235 | /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ |
235 | */ |
| 236 | #define LL_RI_INPUTCAPTUREROUTING_0 (0x00000000U) /*!< PA0 PA1 PA2 PA3 */ |
236 | /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ |
| 237 | #define LL_RI_INPUTCAPTUREROUTING_1 (0x00000001U) /*!< PA4 PA5 PA6 PA7 */ |
237 | #define LL_RI_INPUTCAPTUREROUTING_0 (0x00000000U) /*!< PA0 PA1 PA2 PA3 */ |
| 238 | #define LL_RI_INPUTCAPTUREROUTING_2 (0x00000002U) /*!< PA8 PA9 PA10 PA11 */ |
238 | #define LL_RI_INPUTCAPTUREROUTING_1 (0x00000001U) /*!< PA4 PA5 PA6 PA7 */ |
| 239 | #define LL_RI_INPUTCAPTUREROUTING_3 (0x00000003U) /*!< PA12 PA13 PA14 PA15 */ |
239 | #define LL_RI_INPUTCAPTUREROUTING_2 (0x00000002U) /*!< PA8 PA9 PA10 PA11 */ |
| 240 | #define LL_RI_INPUTCAPTUREROUTING_4 (0x00000004U) /*!< PC0 PC1 PC2 PC3 */ |
240 | #define LL_RI_INPUTCAPTUREROUTING_3 (0x00000003U) /*!< PA12 PA13 PA14 PA15 */ |
| 241 | #define LL_RI_INPUTCAPTUREROUTING_5 (0x00000005U) /*!< PC4 PC5 PC6 PC7 */ |
241 | #define LL_RI_INPUTCAPTUREROUTING_4 (0x00000004U) /*!< PC0 PC1 PC2 PC3 */ |
| 242 | #define LL_RI_INPUTCAPTUREROUTING_6 (0x00000006U) /*!< PC8 PC9 PC10 PC11 */ |
242 | #define LL_RI_INPUTCAPTUREROUTING_5 (0x00000005U) /*!< PC4 PC5 PC6 PC7 */ |
| 243 | #define LL_RI_INPUTCAPTUREROUTING_7 (0x00000007U) /*!< PC12 PC13 PC14 PC15 */ |
243 | #define LL_RI_INPUTCAPTUREROUTING_6 (0x00000006U) /*!< PC8 PC9 PC10 PC11 */ |
| 244 | #define LL_RI_INPUTCAPTUREROUTING_8 (0x00000008U) /*!< PD0 PD1 PD2 PD3 */ |
244 | #define LL_RI_INPUTCAPTUREROUTING_7 (0x00000007U) /*!< PC12 PC13 PC14 PC15 */ |
| 245 | #define LL_RI_INPUTCAPTUREROUTING_9 (0x00000009U) /*!< PD4 PD5 PD6 PD7 */ |
245 | #define LL_RI_INPUTCAPTUREROUTING_8 (0x00000008U) /*!< PD0 PD1 PD2 PD3 */ |
| 246 | #define LL_RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /*!< PD8 PD9 PD10 PD11 */ |
246 | #define LL_RI_INPUTCAPTUREROUTING_9 (0x00000009U) /*!< PD4 PD5 PD6 PD7 */ |
| 247 | #define LL_RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /*!< PD12 PD13 PD14 PD15 */ |
247 | #define LL_RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /*!< PD8 PD9 PD10 PD11 */ |
| 248 | #if defined(GPIOE) |
248 | #define LL_RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /*!< PD12 PD13 PD14 PD15 */ |
| 249 | #define LL_RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /*!< PE0 PE1 PE2 PE3 */ |
249 | #if defined(GPIOE) |
| 250 | #define LL_RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /*!< PE4 PE5 PE6 PE7 */ |
250 | #define LL_RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /*!< PE0 PE1 PE2 PE3 */ |
| 251 | #define LL_RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /*!< PE8 PE9 PE10 PE11 */ |
251 | #define LL_RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /*!< PE4 PE5 PE6 PE7 */ |
| 252 | #define LL_RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /*!< PE12 PE13 PE14 PE15 */ |
252 | #define LL_RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /*!< PE8 PE9 PE10 PE11 */ |
| 253 | #endif /* GPIOE */ |
253 | #define LL_RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /*!< PE12 PE13 PE14 PE15 */ |
| 254 | /** |
254 | #endif /* GPIOE */ |
| 255 | * @} |
255 | /** |
| 256 | */ |
256 | * @} |
| 257 | 257 | */ |
|
| 258 | /** @defgroup SYSTEM_LL_EC_IOSWITCH_LINKED_ADC RI IO Switch linked to ADC |
258 | |
| 259 | * @{ |
259 | /** @defgroup SYSTEM_LL_EC_IOSWITCH_LINKED_ADC RI IO Switch linked to ADC |
| 260 | */ |
260 | * @{ |
| 261 | #define LL_RI_IOSWITCH_CH0 RI_ASCR1_CH_0 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
261 | */ |
| 262 | #define LL_RI_IOSWITCH_CH1 RI_ASCR1_CH_1 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
262 | #define LL_RI_IOSWITCH_CH0 RI_ASCR1_CH_0 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| 263 | #define LL_RI_IOSWITCH_CH2 RI_ASCR1_CH_2 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
263 | #define LL_RI_IOSWITCH_CH1 RI_ASCR1_CH_1 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| 264 | #define LL_RI_IOSWITCH_CH3 RI_ASCR1_CH_3 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
264 | #define LL_RI_IOSWITCH_CH2 RI_ASCR1_CH_2 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| 265 | #define LL_RI_IOSWITCH_CH4 RI_ASCR1_CH_4 /*!< CH4: Analog switch control */ |
265 | #define LL_RI_IOSWITCH_CH3 RI_ASCR1_CH_3 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| 266 | #define LL_RI_IOSWITCH_CH5 RI_ASCR1_CH_5 /*!< CH5: Comparator 1 analog switch*/ |
266 | #define LL_RI_IOSWITCH_CH4 RI_ASCR1_CH_4 /*!< CH4: Analog switch control */ |
| 267 | #define LL_RI_IOSWITCH_CH6 RI_ASCR1_CH_6 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */ |
267 | #define LL_RI_IOSWITCH_CH5 RI_ASCR1_CH_5 /*!< CH5: Comparator 1 analog switch*/ |
| 268 | #define LL_RI_IOSWITCH_CH7 RI_ASCR1_CH_7 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */ |
268 | #define LL_RI_IOSWITCH_CH6 RI_ASCR1_CH_6 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */ |
| 269 | #define LL_RI_IOSWITCH_CH8 RI_ASCR1_CH_8 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */ |
269 | #define LL_RI_IOSWITCH_CH7 RI_ASCR1_CH_7 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */ |
| 270 | #define LL_RI_IOSWITCH_CH9 RI_ASCR1_CH_9 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */ |
270 | #define LL_RI_IOSWITCH_CH8 RI_ASCR1_CH_8 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */ |
| 271 | #define LL_RI_IOSWITCH_CH10 RI_ASCR1_CH_10 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
271 | #define LL_RI_IOSWITCH_CH9 RI_ASCR1_CH_9 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */ |
| 272 | #define LL_RI_IOSWITCH_CH11 RI_ASCR1_CH_11 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
272 | #define LL_RI_IOSWITCH_CH10 RI_ASCR1_CH_10 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| 273 | #define LL_RI_IOSWITCH_CH12 RI_ASCR1_CH_12 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
273 | #define LL_RI_IOSWITCH_CH11 RI_ASCR1_CH_11 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| 274 | #define LL_RI_IOSWITCH_CH13 RI_ASCR1_CH_13 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
274 | #define LL_RI_IOSWITCH_CH12 RI_ASCR1_CH_12 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| 275 | #define LL_RI_IOSWITCH_CH14 RI_ASCR1_CH_14 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */ |
275 | #define LL_RI_IOSWITCH_CH13 RI_ASCR1_CH_13 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| 276 | #define LL_RI_IOSWITCH_CH15 RI_ASCR1_CH_15 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */ |
276 | #define LL_RI_IOSWITCH_CH14 RI_ASCR1_CH_14 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */ |
| 277 | #define LL_RI_IOSWITCH_CH18 RI_ASCR1_CH_18 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
277 | #define LL_RI_IOSWITCH_CH15 RI_ASCR1_CH_15 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */ |
| 278 | #define LL_RI_IOSWITCH_CH19 RI_ASCR1_CH_19 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
278 | #define LL_RI_IOSWITCH_CH18 RI_ASCR1_CH_18 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| 279 | #define LL_RI_IOSWITCH_CH20 RI_ASCR1_CH_20 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
279 | #define LL_RI_IOSWITCH_CH19 RI_ASCR1_CH_19 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| 280 | #define LL_RI_IOSWITCH_CH21 RI_ASCR1_CH_21 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
280 | #define LL_RI_IOSWITCH_CH20 RI_ASCR1_CH_20 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| 281 | #define LL_RI_IOSWITCH_CH22 RI_ASCR1_CH_22 /*!< Analog I/O switch control of channels CH22 */ |
281 | #define LL_RI_IOSWITCH_CH21 RI_ASCR1_CH_21 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| 282 | #define LL_RI_IOSWITCH_CH23 RI_ASCR1_CH_23 /*!< Analog I/O switch control of channels CH23 */ |
282 | #define LL_RI_IOSWITCH_CH22 RI_ASCR1_CH_22 /*!< Analog I/O switch control of channels CH22 */ |
| 283 | #define LL_RI_IOSWITCH_CH24 RI_ASCR1_CH_24 /*!< Analog I/O switch control of channels CH24 */ |
283 | #define LL_RI_IOSWITCH_CH23 RI_ASCR1_CH_23 /*!< Analog I/O switch control of channels CH23 */ |
| 284 | #define LL_RI_IOSWITCH_CH25 RI_ASCR1_CH_25 /*!< Analog I/O switch control of channels CH25 */ |
284 | #define LL_RI_IOSWITCH_CH24 RI_ASCR1_CH_24 /*!< Analog I/O switch control of channels CH24 */ |
| 285 | #define LL_RI_IOSWITCH_VCOMP RI_ASCR1_VCOMP /*!< VCOMP (ADC channel 26) is an internal switch |
285 | #define LL_RI_IOSWITCH_CH25 RI_ASCR1_CH_25 /*!< Analog I/O switch control of channels CH25 */ |
| 286 | used to connect selected channel to COMP1 non inverting input */ |
286 | #define LL_RI_IOSWITCH_VCOMP RI_ASCR1_VCOMP /*!< VCOMP (ADC channel 26) is an internal switch |
| 287 | #if defined(RI_ASCR1_CH_27) |
287 | used to connect selected channel to COMP1 non inverting input */ |
| 288 | #define LL_RI_IOSWITCH_CH27 RI_ASCR1_CH_27 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
288 | #if defined(RI_ASCR1_CH_27) |
| 289 | #define LL_RI_IOSWITCH_CH28 RI_ASCR1_CH_28 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
289 | #define LL_RI_IOSWITCH_CH27 RI_ASCR1_CH_27 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| 290 | #define LL_RI_IOSWITCH_CH29 RI_ASCR1_CH_29 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
290 | #define LL_RI_IOSWITCH_CH28 RI_ASCR1_CH_28 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| 291 | #define LL_RI_IOSWITCH_CH30 RI_ASCR1_CH_30 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
291 | #define LL_RI_IOSWITCH_CH29 RI_ASCR1_CH_29 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| 292 | #define LL_RI_IOSWITCH_CH31 RI_ASCR1_CH_31 /*!< CH31/GR11-5 I/O Analog switch control */ |
292 | #define LL_RI_IOSWITCH_CH30 RI_ASCR1_CH_30 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| 293 | #endif /* RI_ASCR1_CH_27 */ |
293 | #define LL_RI_IOSWITCH_CH31 RI_ASCR1_CH_31 /*!< CH31/GR11-5 I/O Analog switch control */ |
| 294 | /** |
294 | #endif /* RI_ASCR1_CH_27 */ |
| 295 | * @} |
295 | /** |
| 296 | */ |
296 | * @} |
| 297 | 297 | */ |
|
| 298 | /** @defgroup SYSTEM_LL_EC_IOSWITCH_NOT_LINKED_ADC RI IO Switch not linked to ADC |
298 | |
| 299 | * @{ |
299 | /** @defgroup SYSTEM_LL_EC_IOSWITCH_NOT_LINKED_ADC RI IO Switch not linked to ADC |
| 300 | */ |
300 | * @{ |
| 301 | #define LL_RI_IOSWITCH_GR10_1 RI_ASCR2_GR10_1 /*!< GR10-1 I/O analog switch control */ |
301 | */ |
| 302 | #define LL_RI_IOSWITCH_GR10_2 RI_ASCR2_GR10_2 /*!< GR10-2 I/O analog switch control */ |
302 | #define LL_RI_IOSWITCH_GR10_1 RI_ASCR2_GR10_1 /*!< GR10-1 I/O analog switch control */ |
| 303 | #define LL_RI_IOSWITCH_GR10_3 RI_ASCR2_GR10_3 /*!< GR10-3 I/O analog switch control */ |
303 | #define LL_RI_IOSWITCH_GR10_2 RI_ASCR2_GR10_2 /*!< GR10-2 I/O analog switch control */ |
| 304 | #define LL_RI_IOSWITCH_GR10_4 RI_ASCR2_GR10_4 /*!< GR10-4 I/O analog switch control */ |
304 | #define LL_RI_IOSWITCH_GR10_3 RI_ASCR2_GR10_3 /*!< GR10-3 I/O analog switch control */ |
| 305 | #define LL_RI_IOSWITCH_GR6_1 RI_ASCR2_GR6_1 /*!< GR6-1 I/O analog switch control */ |
305 | #define LL_RI_IOSWITCH_GR10_4 RI_ASCR2_GR10_4 /*!< GR10-4 I/O analog switch control */ |
| 306 | #define LL_RI_IOSWITCH_GR6_2 RI_ASCR2_GR6_2 /*!< GR6-2 I/O analog switch control */ |
306 | #define LL_RI_IOSWITCH_GR6_1 RI_ASCR2_GR6_1 /*!< GR6-1 I/O analog switch control */ |
| 307 | #define LL_RI_IOSWITCH_GR5_1 RI_ASCR2_GR5_1 /*!< GR5-1 I/O analog switch control */ |
307 | #define LL_RI_IOSWITCH_GR6_2 RI_ASCR2_GR6_2 /*!< GR6-2 I/O analog switch control */ |
| 308 | #define LL_RI_IOSWITCH_GR5_2 RI_ASCR2_GR5_2 /*!< GR5-2 I/O analog switch control */ |
308 | #define LL_RI_IOSWITCH_GR5_1 RI_ASCR2_GR5_1 /*!< GR5-1 I/O analog switch control */ |
| 309 | #define LL_RI_IOSWITCH_GR5_3 RI_ASCR2_GR5_3 /*!< GR5-3 I/O analog switch control */ |
309 | #define LL_RI_IOSWITCH_GR5_2 RI_ASCR2_GR5_2 /*!< GR5-2 I/O analog switch control */ |
| 310 | #define LL_RI_IOSWITCH_GR4_1 RI_ASCR2_GR4_1 /*!< GR4-1 I/O analog switch control */ |
310 | #define LL_RI_IOSWITCH_GR5_3 RI_ASCR2_GR5_3 /*!< GR5-3 I/O analog switch control */ |
| 311 | #define LL_RI_IOSWITCH_GR4_2 RI_ASCR2_GR4_2 /*!< GR4-2 I/O analog switch control */ |
311 | #define LL_RI_IOSWITCH_GR4_1 RI_ASCR2_GR4_1 /*!< GR4-1 I/O analog switch control */ |
| 312 | #define LL_RI_IOSWITCH_GR4_3 RI_ASCR2_GR4_3 /*!< GR4-3 I/O analog switch control */ |
312 | #define LL_RI_IOSWITCH_GR4_2 RI_ASCR2_GR4_2 /*!< GR4-2 I/O analog switch control */ |
| 313 | #if defined(RI_ASCR2_CH0b) |
313 | #define LL_RI_IOSWITCH_GR4_3 RI_ASCR2_GR4_3 /*!< GR4-3 I/O analog switch control */ |
| 314 | #define LL_RI_IOSWITCH_CH0b RI_ASCR2_CH0b /*!< CH0b-GR03-3 I/O analog switch control */ |
314 | #if defined(RI_ASCR2_CH0b) |
| 315 | #if defined(RI_ASCR2_CH1b) |
315 | #define LL_RI_IOSWITCH_CH0b RI_ASCR2_CH0b /*!< CH0b-GR03-3 I/O analog switch control */ |
| 316 | #define LL_RI_IOSWITCH_CH1b RI_ASCR2_CH1b /*!< CH1b-GR03-4 I/O analog switch control */ |
316 | #if defined(RI_ASCR2_CH1b) |
| 317 | #define LL_RI_IOSWITCH_CH2b RI_ASCR2_CH2b /*!< CH2b-GR03-5 I/O analog switch control */ |
317 | #define LL_RI_IOSWITCH_CH1b RI_ASCR2_CH1b /*!< CH1b-GR03-4 I/O analog switch control */ |
| 318 | #define LL_RI_IOSWITCH_CH3b RI_ASCR2_CH3b /*!< CH3b-GR09-3 I/O analog switch control */ |
318 | #define LL_RI_IOSWITCH_CH2b RI_ASCR2_CH2b /*!< CH2b-GR03-5 I/O analog switch control */ |
| 319 | #define LL_RI_IOSWITCH_CH6b RI_ASCR2_CH6b /*!< CH6b-GR09-4 I/O analog switch control */ |
319 | #define LL_RI_IOSWITCH_CH3b RI_ASCR2_CH3b /*!< CH3b-GR09-3 I/O analog switch control */ |
| 320 | #define LL_RI_IOSWITCH_CH7b RI_ASCR2_CH7b /*!< CH7b-GR02-3 I/O analog switch control */ |
320 | #define LL_RI_IOSWITCH_CH6b RI_ASCR2_CH6b /*!< CH6b-GR09-4 I/O analog switch control */ |
| 321 | #define LL_RI_IOSWITCH_CH8b RI_ASCR2_CH8b /*!< CH8b-GR02-4 I/O analog switch control */ |
321 | #define LL_RI_IOSWITCH_CH7b RI_ASCR2_CH7b /*!< CH7b-GR02-3 I/O analog switch control */ |
| 322 | #define LL_RI_IOSWITCH_CH9b RI_ASCR2_CH9b /*!< CH9b-GR02-5 I/O analog switch control */ |
322 | #define LL_RI_IOSWITCH_CH8b RI_ASCR2_CH8b /*!< CH8b-GR02-4 I/O analog switch control */ |
| 323 | #define LL_RI_IOSWITCH_CH10b RI_ASCR2_CH10b /*!< CH10b-GR07-5 I/O analog switch control */ |
323 | #define LL_RI_IOSWITCH_CH9b RI_ASCR2_CH9b /*!< CH9b-GR02-5 I/O analog switch control */ |
| 324 | #define LL_RI_IOSWITCH_CH11b RI_ASCR2_CH11b /*!< CH11b-GR07-6 I/O analog switch control */ |
324 | #define LL_RI_IOSWITCH_CH10b RI_ASCR2_CH10b /*!< CH10b-GR07-5 I/O analog switch control */ |
| 325 | #define LL_RI_IOSWITCH_CH12b RI_ASCR2_CH12b /*!< CH12b-GR07-7 I/O analog switch control */ |
325 | #define LL_RI_IOSWITCH_CH11b RI_ASCR2_CH11b /*!< CH11b-GR07-6 I/O analog switch control */ |
| 326 | #endif /* RI_ASCR2_CH1b */ |
326 | #define LL_RI_IOSWITCH_CH12b RI_ASCR2_CH12b /*!< CH12b-GR07-7 I/O analog switch control */ |
| 327 | #define LL_RI_IOSWITCH_GR6_3 RI_ASCR2_GR6_3 /*!< GR6-3 I/O analog switch control */ |
327 | #endif /* RI_ASCR2_CH1b */ |
| 328 | #define LL_RI_IOSWITCH_GR6_4 RI_ASCR2_GR6_4 /*!< GR6-4 I/O analog switch control */ |
328 | #define LL_RI_IOSWITCH_GR6_3 RI_ASCR2_GR6_3 /*!< GR6-3 I/O analog switch control */ |
| 329 | #endif /* RI_ASCR2_CH0b */ |
329 | #define LL_RI_IOSWITCH_GR6_4 RI_ASCR2_GR6_4 /*!< GR6-4 I/O analog switch control */ |
| 330 | /** |
330 | #endif /* RI_ASCR2_CH0b */ |
| 331 | * @} |
331 | /** |
| 332 | */ |
332 | * @} |
| 333 | 333 | */ |
|
| 334 | /** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT |
334 | |
| 335 | * @{ |
335 | /** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT |
| 336 | */ |
336 | * @{ |
| 337 | #define LL_RI_HSYTERESIS_PORT_A 0U /*!< HYSTERESIS PORT A */ |
337 | */ |
| 338 | #define LL_RI_HSYTERESIS_PORT_B 1U /*!< HYSTERESIS PORT B */ |
338 | #define LL_RI_HSYTERESIS_PORT_A 0U /*!< HYSTERESIS PORT A */ |
| 339 | #define LL_RI_HSYTERESIS_PORT_C 2U /*!< HYSTERESIS PORT C */ |
339 | #define LL_RI_HSYTERESIS_PORT_B 1U /*!< HYSTERESIS PORT B */ |
| 340 | #define LL_RI_HSYTERESIS_PORT_D 3U /*!< HYSTERESIS PORT D */ |
340 | #define LL_RI_HSYTERESIS_PORT_C 2U /*!< HYSTERESIS PORT C */ |
| 341 | #if defined(GPIOE) |
341 | #define LL_RI_HSYTERESIS_PORT_D 3U /*!< HYSTERESIS PORT D */ |
| 342 | #define LL_RI_HSYTERESIS_PORT_E 4U /*!< HYSTERESIS PORT E */ |
342 | #if defined(GPIOE) |
| 343 | #endif /* GPIOE */ |
343 | #define LL_RI_HSYTERESIS_PORT_E 4U /*!< HYSTERESIS PORT E */ |
| 344 | #if defined(GPIOF) |
344 | #endif /* GPIOE */ |
| 345 | #define LL_RI_HSYTERESIS_PORT_F 5U /*!< HYSTERESIS PORT F */ |
345 | #if defined(GPIOF) |
| 346 | #endif /* GPIOF */ |
346 | #define LL_RI_HSYTERESIS_PORT_F 5U /*!< HYSTERESIS PORT F */ |
| 347 | #if defined(GPIOG) |
347 | #endif /* GPIOF */ |
| 348 | #define LL_RI_HSYTERESIS_PORT_G 6U /*!< HYSTERESIS PORT G */ |
348 | #if defined(GPIOG) |
| 349 | #endif /* GPIOG */ |
349 | #define LL_RI_HSYTERESIS_PORT_G 6U /*!< HYSTERESIS PORT G */ |
| 350 | /** |
350 | #endif /* GPIOG */ |
| 351 | * @} |
351 | /** |
| 352 | */ |
352 | * @} |
| 353 | 353 | */ |
|
| 354 | /** @defgroup SYSTEM_LL_EC_PIN RI PIN |
354 | |
| 355 | * @{ |
355 | /** @defgroup SYSTEM_LL_EC_PIN RI PIN |
| 356 | */ |
356 | * @{ |
| 357 | #define LL_RI_PIN_0 ((uint16_t)0x0001U) /*!< Pin 0 selected */ |
357 | */ |
| 358 | #define LL_RI_PIN_1 ((uint16_t)0x0002U) /*!< Pin 1 selected */ |
358 | #define LL_RI_PIN_0 ((uint16_t)0x0001U) /*!< Pin 0 selected */ |
| 359 | #define LL_RI_PIN_2 ((uint16_t)0x0004U) /*!< Pin 2 selected */ |
359 | #define LL_RI_PIN_1 ((uint16_t)0x0002U) /*!< Pin 1 selected */ |
| 360 | #define LL_RI_PIN_3 ((uint16_t)0x0008U) /*!< Pin 3 selected */ |
360 | #define LL_RI_PIN_2 ((uint16_t)0x0004U) /*!< Pin 2 selected */ |
| 361 | #define LL_RI_PIN_4 ((uint16_t)0x0010U) /*!< Pin 4 selected */ |
361 | #define LL_RI_PIN_3 ((uint16_t)0x0008U) /*!< Pin 3 selected */ |
| 362 | #define LL_RI_PIN_5 ((uint16_t)0x0020U) /*!< Pin 5 selected */ |
362 | #define LL_RI_PIN_4 ((uint16_t)0x0010U) /*!< Pin 4 selected */ |
| 363 | #define LL_RI_PIN_6 ((uint16_t)0x0040U) /*!< Pin 6 selected */ |
363 | #define LL_RI_PIN_5 ((uint16_t)0x0020U) /*!< Pin 5 selected */ |
| 364 | #define LL_RI_PIN_7 ((uint16_t)0x0080U) /*!< Pin 7 selected */ |
364 | #define LL_RI_PIN_6 ((uint16_t)0x0040U) /*!< Pin 6 selected */ |
| 365 | #define LL_RI_PIN_8 ((uint16_t)0x0100U) /*!< Pin 8 selected */ |
365 | #define LL_RI_PIN_7 ((uint16_t)0x0080U) /*!< Pin 7 selected */ |
| 366 | #define LL_RI_PIN_9 ((uint16_t)0x0200U) /*!< Pin 9 selected */ |
366 | #define LL_RI_PIN_8 ((uint16_t)0x0100U) /*!< Pin 8 selected */ |
| 367 | #define LL_RI_PIN_10 ((uint16_t)0x0400U) /*!< Pin 10 selected */ |
367 | #define LL_RI_PIN_9 ((uint16_t)0x0200U) /*!< Pin 9 selected */ |
| 368 | #define LL_RI_PIN_11 ((uint16_t)0x0800U) /*!< Pin 11 selected */ |
368 | #define LL_RI_PIN_10 ((uint16_t)0x0400U) /*!< Pin 10 selected */ |
| 369 | #define LL_RI_PIN_12 ((uint16_t)0x1000U) /*!< Pin 12 selected */ |
369 | #define LL_RI_PIN_11 ((uint16_t)0x0800U) /*!< Pin 11 selected */ |
| 370 | #define LL_RI_PIN_13 ((uint16_t)0x2000U) /*!< Pin 13 selected */ |
370 | #define LL_RI_PIN_12 ((uint16_t)0x1000U) /*!< Pin 12 selected */ |
| 371 | #define LL_RI_PIN_14 ((uint16_t)0x4000U) /*!< Pin 14 selected */ |
371 | #define LL_RI_PIN_13 ((uint16_t)0x2000U) /*!< Pin 13 selected */ |
| 372 | #define LL_RI_PIN_15 ((uint16_t)0x8000U) /*!< Pin 15 selected */ |
372 | #define LL_RI_PIN_14 ((uint16_t)0x4000U) /*!< Pin 14 selected */ |
| 373 | #define LL_RI_PIN_ALL ((uint16_t)0xFFFFU) /*!< All pins selected */ |
373 | #define LL_RI_PIN_15 ((uint16_t)0x8000U) /*!< Pin 15 selected */ |
| 374 | /** |
374 | #define LL_RI_PIN_ALL ((uint16_t)0xFFFFU) /*!< All pins selected */ |
| 375 | * @} |
375 | /** |
| 376 | */ |
376 | * @} |
| 377 | 377 | */ |
|
| 378 | #if defined(RI_ASMR1_PA) |
378 | |
| 379 | /** @defgroup SYSTEM_LL_EC_PORT RI PORT |
379 | #if defined(RI_ASMR1_PA) |
| 380 | * @{ |
380 | /** @defgroup SYSTEM_LL_EC_PORT RI PORT |
| 381 | */ |
381 | * @{ |
| 382 | #define LL_RI_PORT_A 0U /*!< PORT A */ |
382 | */ |
| 383 | #define LL_RI_PORT_B 1U /*!< PORT B */ |
383 | #define LL_RI_PORT_A 0U /*!< PORT A */ |
| 384 | #define LL_RI_PORT_C 2U /*!< PORT C */ |
384 | #define LL_RI_PORT_B 1U /*!< PORT B */ |
| 385 | #if defined(GPIOF) |
385 | #define LL_RI_PORT_C 2U /*!< PORT C */ |
| 386 | #define LL_RI_PORT_F 3U /*!< PORT F */ |
386 | #if defined(GPIOF) |
| 387 | #endif /* GPIOF */ |
387 | #define LL_RI_PORT_F 3U /*!< PORT F */ |
| 388 | #if defined(GPIOG) |
388 | #endif /* GPIOF */ |
| 389 | #define LL_RI_PORT_G 4U /*!< PORT G */ |
389 | #if defined(GPIOG) |
| 390 | #endif /* GPIOG */ |
390 | #define LL_RI_PORT_G 4U /*!< PORT G */ |
| 391 | /** |
391 | #endif /* GPIOG */ |
| 392 | * @} |
392 | /** |
| 393 | */ |
393 | * @} |
| 394 | 394 | */ |
|
| 395 | #endif /* RI_ASMR1_PA */ |
395 | |
| 396 | 396 | #endif /* RI_ASMR1_PA */ |
|
| 397 | 397 | ||
| 398 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
398 | |
| 399 | * @{ |
399 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
| 400 | */ |
400 | * @{ |
| 401 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
401 | */ |
| 402 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ |
402 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
| 403 | /** |
403 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ |
| 404 | * @} |
404 | /** |
| 405 | */ |
405 | * @} |
| 406 | 406 | */ |
|
| 407 | /** |
407 | |
| 408 | * @} |
408 | /** |
| 409 | */ |
409 | * @} |
| 410 | 410 | */ |
|
| 411 | /* Exported macro ------------------------------------------------------------*/ |
411 | |
| 412 | 412 | /* Exported macro ------------------------------------------------------------*/ |
|
| 413 | /* Exported functions --------------------------------------------------------*/ |
413 | |
| 414 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
414 | /* Exported functions --------------------------------------------------------*/ |
| 415 | * @{ |
415 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
| 416 | */ |
416 | * @{ |
| 417 | 417 | */ |
|
| 418 | /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG |
418 | |
| 419 | * @{ |
419 | /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG |
| 420 | */ |
420 | * @{ |
| 421 | 421 | */ |
|
| 422 | /** |
422 | |
| 423 | * @brief Set memory mapping at address 0x00000000 |
423 | /** |
| 424 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory |
424 | * @brief Set memory mapping at address 0x00000000 |
| 425 | * @param Memory This parameter can be one of the following values: |
425 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory |
| 426 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
426 | * @param Memory This parameter can be one of the following values: |
| 427 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
427 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
| 428 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
428 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
| 429 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
429 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
| 430 | * |
430 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
| 431 | * (*) value not defined in all devices |
431 | * |
| 432 | * @retval None |
432 | * (*) value not defined in all devices |
| 433 | */ |
433 | * @retval None |
| 434 | __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) |
434 | */ |
| 435 | { |
435 | __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) |
| 436 | MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); |
436 | { |
| 437 | } |
437 | MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); |
| 438 | 438 | } |
|
| 439 | /** |
439 | |
| 440 | * @brief Get memory mapping at address 0x00000000 |
440 | /** |
| 441 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory |
441 | * @brief Get memory mapping at address 0x00000000 |
| 442 | * @retval Returned value can be one of the following values: |
442 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory |
| 443 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
443 | * @retval Returned value can be one of the following values: |
| 444 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
444 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
| 445 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
445 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
| 446 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
446 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
| 447 | * |
447 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
| 448 | * (*) value not defined in all devices. |
448 | * |
| 449 | */ |
449 | * (*) value not defined in all devices. |
| 450 | __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) |
450 | */ |
| 451 | { |
451 | __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) |
| 452 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); |
452 | { |
| 453 | } |
453 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); |
| 454 | 454 | } |
|
| 455 | /** |
455 | |
| 456 | * @brief Return the boot mode as configured by user. |
456 | /** |
| 457 | * @rmtoll SYSCFG_MEMRMP BOOT_MODE LL_SYSCFG_GetBootMode |
457 | * @brief Return the boot mode as configured by user. |
| 458 | * @retval Returned value can be one of the following values: |
458 | * @rmtoll SYSCFG_MEMRMP BOOT_MODE LL_SYSCFG_GetBootMode |
| 459 | * @arg @ref LL_SYSCFG_BOOTMODE_FLASH |
459 | * @retval Returned value can be one of the following values: |
| 460 | * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH |
460 | * @arg @ref LL_SYSCFG_BOOTMODE_FLASH |
| 461 | * @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*) |
461 | * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH |
| 462 | * @arg @ref LL_SYSCFG_BOOTMODE_SRAM |
462 | * @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*) |
| 463 | * |
463 | * @arg @ref LL_SYSCFG_BOOTMODE_SRAM |
| 464 | * (*) value not defined in all devices. |
464 | * |
| 465 | */ |
465 | * (*) value not defined in all devices. |
| 466 | __STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void) |
466 | */ |
| 467 | { |
467 | __STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void) |
| 468 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)); |
468 | { |
| 469 | } |
469 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)); |
| 470 | 470 | } |
|
| 471 | /** |
471 | |
| 472 | * @brief Enable internal pull-up on USB DP line. |
472 | /** |
| 473 | * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_EnableUSBPullUp |
473 | * @brief Enable internal pull-up on USB DP line. |
| 474 | * @retval None |
474 | * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_EnableUSBPullUp |
| 475 | */ |
475 | * @retval None |
| 476 | __STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void) |
476 | */ |
| 477 | { |
477 | __STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void) |
| 478 | SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); |
478 | { |
| 479 | } |
479 | SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); |
| 480 | 480 | } |
|
| 481 | /** |
481 | |
| 482 | * @brief Disable internal pull-up on USB DP line. |
482 | /** |
| 483 | * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_DisableUSBPullUp |
483 | * @brief Disable internal pull-up on USB DP line. |
| 484 | * @retval None |
484 | * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_DisableUSBPullUp |
| 485 | */ |
485 | * @retval None |
| 486 | __STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void) |
486 | */ |
| 487 | { |
487 | __STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void) |
| 488 | CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); |
488 | { |
| 489 | } |
489 | CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); |
| 490 | 490 | } |
|
| 491 | #if defined(LCD) |
491 | |
| 492 | /** |
492 | #if defined(LCD) |
| 493 | * @brief Enable decoupling capacitance connection. |
493 | /** |
| 494 | * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_EnableLCDCapacitanceConnection |
494 | * @brief Enable decoupling capacitance connection. |
| 495 | * @param Pin This parameter can be a combination of the following values: |
495 | * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_EnableLCDCapacitanceConnection |
| 496 | * @arg @ref LL_SYSCFG_LCDCAPA_PB2 |
496 | * @param Pin This parameter can be a combination of the following values: |
| 497 | * @arg @ref LL_SYSCFG_LCDCAPA_PB12 |
497 | * @arg @ref LL_SYSCFG_LCDCAPA_PB2 |
| 498 | * @arg @ref LL_SYSCFG_LCDCAPA_PB0 |
498 | * @arg @ref LL_SYSCFG_LCDCAPA_PB12 |
| 499 | * @arg @ref LL_SYSCFG_LCDCAPA_PE11 |
499 | * @arg @ref LL_SYSCFG_LCDCAPA_PB0 |
| 500 | * @arg @ref LL_SYSCFG_LCDCAPA_PE12 |
500 | * @arg @ref LL_SYSCFG_LCDCAPA_PE11 |
| 501 | * @retval None |
501 | * @arg @ref LL_SYSCFG_LCDCAPA_PE12 |
| 502 | */ |
502 | * @retval None |
| 503 | __STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin) |
503 | */ |
| 504 | { |
504 | __STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin) |
| 505 | SET_BIT(SYSCFG->PMC, Pin); |
505 | { |
| 506 | } |
506 | SET_BIT(SYSCFG->PMC, Pin); |
| 507 | 507 | } |
|
| 508 | /** |
508 | |
| 509 | * @brief DIsable decoupling capacitance connection. |
509 | /** |
| 510 | * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_DisableLCDCapacitanceConnection |
510 | * @brief DIsable decoupling capacitance connection. |
| 511 | * @param Pin This parameter can be a combination of the following values: |
511 | * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_DisableLCDCapacitanceConnection |
| 512 | * @arg @ref LL_SYSCFG_LCDCAPA_PB2 |
512 | * @param Pin This parameter can be a combination of the following values: |
| 513 | * @arg @ref LL_SYSCFG_LCDCAPA_PB12 |
513 | * @arg @ref LL_SYSCFG_LCDCAPA_PB2 |
| 514 | * @arg @ref LL_SYSCFG_LCDCAPA_PB0 |
514 | * @arg @ref LL_SYSCFG_LCDCAPA_PB12 |
| 515 | * @arg @ref LL_SYSCFG_LCDCAPA_PE11 |
515 | * @arg @ref LL_SYSCFG_LCDCAPA_PB0 |
| 516 | * @arg @ref LL_SYSCFG_LCDCAPA_PE12 |
516 | * @arg @ref LL_SYSCFG_LCDCAPA_PE11 |
| 517 | * @retval None |
517 | * @arg @ref LL_SYSCFG_LCDCAPA_PE12 |
| 518 | */ |
518 | * @retval None |
| 519 | __STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin) |
519 | */ |
| 520 | { |
520 | __STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin) |
| 521 | CLEAR_BIT(SYSCFG->PMC, Pin); |
521 | { |
| 522 | } |
522 | CLEAR_BIT(SYSCFG->PMC, Pin); |
| 523 | #endif /* LCD */ |
523 | } |
| 524 | 524 | #endif /* LCD */ |
|
| 525 | /** |
525 | |
| 526 | * @brief Configure source input for the EXTI external interrupt. |
526 | /** |
| 527 | * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n |
527 | * @brief Configure source input for the EXTI external interrupt. |
| 528 | * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n |
528 | * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n |
| 529 | * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n |
529 | * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n |
| 530 | * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n |
530 | * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n |
| 531 | * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n |
531 | * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n |
| 532 | * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n |
532 | * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n |
| 533 | * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n |
533 | * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n |
| 534 | * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n |
534 | * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n |
| 535 | * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n |
535 | * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n |
| 536 | * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n |
536 | * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n |
| 537 | * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n |
537 | * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n |
| 538 | * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n |
538 | * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n |
| 539 | * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n |
539 | * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n |
| 540 | * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n |
540 | * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n |
| 541 | * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n |
541 | * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n |
| 542 | * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n |
542 | * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n |
| 543 | * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n |
543 | * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n |
| 544 | * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n |
544 | * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n |
| 545 | * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n |
545 | * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n |
| 546 | * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n |
546 | * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n |
| 547 | * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n |
547 | * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n |
| 548 | * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n |
548 | * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n |
| 549 | * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n |
549 | * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n |
| 550 | * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n |
550 | * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n |
| 551 | * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n |
551 | * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n |
| 552 | * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n |
552 | * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n |
| 553 | * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n |
553 | * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n |
| 554 | * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n |
554 | * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n |
| 555 | * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n |
555 | * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n |
| 556 | * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n |
556 | * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n |
| 557 | * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n |
557 | * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n |
| 558 | * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n |
558 | * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n |
| 559 | * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n |
559 | * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n |
| 560 | * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n |
560 | * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n |
| 561 | * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n |
561 | * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n |
| 562 | * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n |
562 | * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n |
| 563 | * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n |
563 | * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n |
| 564 | * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n |
564 | * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n |
| 565 | * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n |
565 | * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n |
| 566 | * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n |
566 | * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n |
| 567 | * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n |
567 | * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n |
| 568 | * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n |
568 | * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n |
| 569 | * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n |
569 | * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n |
| 570 | * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n |
570 | * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n |
| 571 | * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n |
571 | * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n |
| 572 | * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n |
572 | * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n |
| 573 | * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n |
573 | * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n |
| 574 | * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n |
574 | * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n |
| 575 | * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n |
575 | * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n |
| 576 | * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n |
576 | * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n |
| 577 | * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n |
577 | * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n |
| 578 | * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n |
578 | * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n |
| 579 | * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n |
579 | * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n |
| 580 | * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n |
580 | * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n |
| 581 | * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n |
581 | * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n |
| 582 | * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n |
582 | * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n |
| 583 | * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n |
583 | * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n |
| 584 | * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n |
584 | * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n |
| 585 | * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n |
585 | * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n |
| 586 | * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n |
586 | * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n |
| 587 | * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n |
587 | * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n |
| 588 | * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n |
588 | * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n |
| 589 | * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n |
589 | * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n |
| 590 | * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource |
590 | * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n |
| 591 | * @param Port This parameter can be one of the following values: |
591 | * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource |
| 592 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
592 | * @param Port This parameter can be one of the following values: |
| 593 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
593 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
| 594 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
594 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
| 595 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
595 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
| 596 | * @arg @ref LL_SYSCFG_EXTI_PORTE (*) |
596 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
| 597 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
597 | * @arg @ref LL_SYSCFG_EXTI_PORTE (*) |
| 598 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
598 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
| 599 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
599 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
| 600 | * |
600 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
| 601 | * (*) value not defined in all devices. |
601 | * |
| 602 | * @param Line This parameter can be one of the following values: |
602 | * (*) value not defined in all devices. |
| 603 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
603 | * @param Line This parameter can be one of the following values: |
| 604 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
604 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
| 605 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
605 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
| 606 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
606 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
| 607 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
607 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
| 608 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
608 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
| 609 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
609 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
| 610 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
610 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
| 611 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
611 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
| 612 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
612 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
| 613 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
613 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
| 614 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
614 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
| 615 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
615 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
| 616 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
616 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
| 617 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
617 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
| 618 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
618 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
| 619 | * @retval None |
619 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
| 620 | */ |
620 | * @retval None |
| 621 | __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) |
621 | */ |
| 622 | { |
622 | __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) |
| 623 | MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16), Port << POSITION_VAL((Line >> 16))); |
623 | { |
| 624 | } |
624 | MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16), Port << POSITION_VAL((Line >> 16))); |
| 625 | 625 | } |
|
| 626 | /** |
626 | |
| 627 | * @brief Get the configured defined for specific EXTI Line |
627 | /** |
| 628 | * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n |
628 | * @brief Get the configured defined for specific EXTI Line |
| 629 | * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n |
629 | * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n |
| 630 | * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n |
630 | * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n |
| 631 | * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n |
631 | * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n |
| 632 | * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n |
632 | * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n |
| 633 | * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n |
633 | * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n |
| 634 | * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n |
634 | * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n |
| 635 | * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n |
635 | * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n |
| 636 | * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n |
636 | * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n |
| 637 | * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n |
637 | * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n |
| 638 | * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n |
638 | * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n |
| 639 | * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n |
639 | * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n |
| 640 | * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n |
640 | * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n |
| 641 | * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n |
641 | * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n |
| 642 | * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n |
642 | * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n |
| 643 | * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n |
643 | * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n |
| 644 | * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n |
644 | * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n |
| 645 | * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n |
645 | * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n |
| 646 | * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n |
646 | * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n |
| 647 | * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n |
647 | * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n |
| 648 | * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n |
648 | * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n |
| 649 | * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n |
649 | * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n |
| 650 | * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n |
650 | * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n |
| 651 | * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n |
651 | * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n |
| 652 | * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n |
652 | * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n |
| 653 | * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n |
653 | * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n |
| 654 | * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n |
654 | * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n |
| 655 | * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n |
655 | * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n |
| 656 | * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n |
656 | * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n |
| 657 | * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n |
657 | * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n |
| 658 | * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n |
658 | * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n |
| 659 | * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n |
659 | * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n |
| 660 | * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n |
660 | * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n |
| 661 | * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n |
661 | * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n |
| 662 | * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n |
662 | * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n |
| 663 | * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n |
663 | * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n |
| 664 | * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n |
664 | * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n |
| 665 | * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n |
665 | * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n |
| 666 | * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n |
666 | * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n |
| 667 | * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n |
667 | * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n |
| 668 | * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n |
668 | * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n |
| 669 | * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n |
669 | * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n |
| 670 | * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n |
670 | * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n |
| 671 | * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n |
671 | * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n |
| 672 | * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n |
672 | * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n |
| 673 | * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n |
673 | * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n |
| 674 | * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n |
674 | * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n |
| 675 | * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n |
675 | * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n |
| 676 | * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n |
676 | * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n |
| 677 | * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n |
677 | * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n |
| 678 | * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n |
678 | * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n |
| 679 | * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n |
679 | * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n |
| 680 | * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n |
680 | * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n |
| 681 | * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n |
681 | * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n |
| 682 | * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n |
682 | * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n |
| 683 | * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n |
683 | * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n |
| 684 | * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n |
684 | * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n |
| 685 | * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n |
685 | * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n |
| 686 | * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n |
686 | * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n |
| 687 | * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n |
687 | * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n |
| 688 | * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n |
688 | * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n |
| 689 | * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n |
689 | * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n |
| 690 | * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n |
690 | * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n |
| 691 | * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource |
691 | * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n |
| 692 | * @param Line This parameter can be one of the following values: |
692 | * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource |
| 693 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
693 | * @param Line This parameter can be one of the following values: |
| 694 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
694 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
| 695 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
695 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
| 696 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
696 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
| 697 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
697 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
| 698 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
698 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
| 699 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
699 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
| 700 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
700 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
| 701 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
701 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
| 702 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
702 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
| 703 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
703 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
| 704 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
704 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
| 705 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
705 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
| 706 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
706 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
| 707 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
707 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
| 708 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
708 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
| 709 | * @retval Returned value can be one of the following values: |
709 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
| 710 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
710 | * @retval Returned value can be one of the following values: |
| 711 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
711 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
| 712 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
712 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
| 713 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
713 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
| 714 | * @arg @ref LL_SYSCFG_EXTI_PORTE (*) |
714 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
| 715 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
715 | * @arg @ref LL_SYSCFG_EXTI_PORTE (*) |
| 716 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
716 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
| 717 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
717 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
| 718 | * |
718 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
| 719 | * (*) value not defined in all devices. |
719 | * |
| 720 | */ |
720 | * (*) value not defined in all devices. |
| 721 | __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) |
721 | */ |
| 722 | { |
722 | __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) |
| 723 | return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16)) >> POSITION_VAL(Line >> 16)); |
723 | { |
| 724 | } |
724 | return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16)) >> POSITION_VAL(Line >> 16)); |
| 725 | 725 | } |
|
| 726 | /** |
726 | |
| 727 | * @} |
727 | /** |
| 728 | */ |
728 | * @} |
| 729 | 729 | */ |
|
| 730 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
730 | |
| 731 | * @{ |
731 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
| 732 | */ |
732 | * @{ |
| 733 | 733 | */ |
|
| 734 | /** |
734 | |
| 735 | * @brief Return the device identifier |
735 | /** |
| 736 | * @note 0x416: Cat.1 device\n |
736 | * @brief Return the device identifier |
| 737 | * 0x429: Cat.2 device\n |
737 | * @note 0x416: Cat.1 device\n |
| 738 | * 0x427: Cat.3 device\n |
738 | * 0x429: Cat.2 device\n |
| 739 | * 0x436: Cat.4 device or Cat.3 device(1)\n |
739 | * 0x427: Cat.3 device\n |
| 740 | * 0x437: Cat.5 device\n |
740 | * 0x436: Cat.4 device or Cat.3 device(1)\n |
| 741 | * |
741 | * 0x437: Cat.5 device\n |
| 742 | * (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with |
742 | * |
| 743 | * RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin. |
743 | * (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with |
| 744 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
744 | * RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin. |
| 745 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
745 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
| 746 | */ |
746 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
| 747 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
747 | */ |
| 748 | { |
748 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
| 749 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
749 | { |
| 750 | } |
750 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
| 751 | 751 | } |
|
| 752 | /** |
752 | |
| 753 | * @brief Return the device revision identifier |
753 | /** |
| 754 | * @note This field indicates the revision of the device. |
754 | * @brief Return the device revision identifier |
| 755 | For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018... |
755 | * @note This field indicates the revision of the device. |
| 756 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
756 | For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018... |
| 757 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
757 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
| 758 | */ |
758 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
| 759 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
759 | */ |
| 760 | { |
760 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
| 761 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
761 | { |
| 762 | } |
762 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
| 763 | 763 | } |
|
| 764 | /** |
764 | |
| 765 | * @brief Enable the Debug Module during SLEEP mode |
765 | /** |
| 766 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
766 | * @brief Enable the Debug Module during SLEEP mode |
| 767 | * @retval None |
767 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
| 768 | */ |
768 | * @retval None |
| 769 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
769 | */ |
| 770 | { |
770 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
| 771 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
771 | { |
| 772 | } |
772 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| 773 | 773 | } |
|
| 774 | /** |
774 | |
| 775 | * @brief Disable the Debug Module during SLEEP mode |
775 | /** |
| 776 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
776 | * @brief Disable the Debug Module during SLEEP mode |
| 777 | * @retval None |
777 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
| 778 | */ |
778 | * @retval None |
| 779 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
779 | */ |
| 780 | { |
780 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
| 781 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
781 | { |
| 782 | } |
782 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| 783 | 783 | } |
|
| 784 | /** |
784 | |
| 785 | * @brief Enable the Debug Module during STOP mode |
785 | /** |
| 786 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
786 | * @brief Enable the Debug Module during STOP mode |
| 787 | * @retval None |
787 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
| 788 | */ |
788 | * @retval None |
| 789 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
789 | */ |
| 790 | { |
790 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
| 791 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
791 | { |
| 792 | } |
792 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| 793 | 793 | } |
|
| 794 | /** |
794 | |
| 795 | * @brief Disable the Debug Module during STOP mode |
795 | /** |
| 796 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
796 | * @brief Disable the Debug Module during STOP mode |
| 797 | * @retval None |
797 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
| 798 | */ |
798 | * @retval None |
| 799 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
799 | */ |
| 800 | { |
800 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
| 801 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
801 | { |
| 802 | } |
802 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| 803 | 803 | } |
|
| 804 | /** |
804 | |
| 805 | * @brief Enable the Debug Module during STANDBY mode |
805 | /** |
| 806 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
806 | * @brief Enable the Debug Module during STANDBY mode |
| 807 | * @retval None |
807 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
| 808 | */ |
808 | * @retval None |
| 809 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
809 | */ |
| 810 | { |
810 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
| 811 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
811 | { |
| 812 | } |
812 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| 813 | 813 | } |
|
| 814 | /** |
814 | |
| 815 | * @brief Disable the Debug Module during STANDBY mode |
815 | /** |
| 816 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
816 | * @brief Disable the Debug Module during STANDBY mode |
| 817 | * @retval None |
817 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
| 818 | */ |
818 | * @retval None |
| 819 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
819 | */ |
| 820 | { |
820 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
| 821 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
821 | { |
| 822 | } |
822 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| 823 | 823 | } |
|
| 824 | /** |
824 | |
| 825 | * @brief Set Trace pin assignment control |
825 | /** |
| 826 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
826 | * @brief Set Trace pin assignment control |
| 827 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
827 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
| 828 | * @param PinAssignment This parameter can be one of the following values: |
828 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
| 829 | * @arg @ref LL_DBGMCU_TRACE_NONE |
829 | * @param PinAssignment This parameter can be one of the following values: |
| 830 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
830 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| 831 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
831 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| 832 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
832 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| 833 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
833 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| 834 | * @retval None |
834 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| 835 | */ |
835 | * @retval None |
| 836 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
836 | */ |
| 837 | { |
837 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
| 838 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
838 | { |
| 839 | } |
839 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
| 840 | 840 | } |
|
| 841 | /** |
841 | |
| 842 | * @brief Get Trace pin assignment control |
842 | /** |
| 843 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
843 | * @brief Get Trace pin assignment control |
| 844 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
844 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
| 845 | * @retval Returned value can be one of the following values: |
845 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
| 846 | * @arg @ref LL_DBGMCU_TRACE_NONE |
846 | * @retval Returned value can be one of the following values: |
| 847 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
847 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| 848 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
848 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| 849 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
849 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| 850 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
850 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| 851 | */ |
851 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| 852 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
852 | */ |
| 853 | { |
853 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
| 854 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
854 | { |
| 855 | } |
855 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
| 856 | 856 | } |
|
| 857 | /** |
857 | |
| 858 | * @brief Freeze APB1 peripherals (group1 peripherals) |
858 | /** |
| 859 | * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
859 | * @brief Freeze APB1 peripherals (group1 peripherals) |
| 860 | * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
860 | * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 861 | * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
861 | * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 862 | * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
862 | * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 863 | * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
863 | * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 864 | * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
864 | * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 865 | * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
865 | * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 866 | * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
866 | * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 867 | * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
867 | * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 868 | * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
868 | * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 869 | * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph |
869 | * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 870 | * @param Periphs This parameter can be a combination of the following values: |
870 | * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph |
| 871 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
871 | * @param Periphs This parameter can be a combination of the following values: |
| 872 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
872 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| 873 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
873 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| 874 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
874 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| 875 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
875 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
| 876 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
876 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| 877 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) |
877 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| 878 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
878 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) |
| 879 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
879 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| 880 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
880 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| 881 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
881 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| 882 | * (*) value not defined in all devices. |
882 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
| 883 | * @retval None |
883 | * (*) value not defined in all devices. |
| 884 | */ |
884 | * @retval None |
| 885 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
885 | */ |
| 886 | { |
886 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
| 887 | SET_BIT(DBGMCU->APB1FZ, Periphs); |
887 | { |
| 888 | } |
888 | SET_BIT(DBGMCU->APB1FZ, Periphs); |
| 889 | 889 | } |
|
| 890 | /** |
890 | |
| 891 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
891 | /** |
| 892 | * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
892 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
| 893 | * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
893 | * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 894 | * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
894 | * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 895 | * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
895 | * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 896 | * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
896 | * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 897 | * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
897 | * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 898 | * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
898 | * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 899 | * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
899 | * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 900 | * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
900 | * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 901 | * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
901 | * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 902 | * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
902 | * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 903 | * @param Periphs This parameter can be a combination of the following values: |
903 | * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
| 904 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
904 | * @param Periphs This parameter can be a combination of the following values: |
| 905 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
905 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| 906 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
906 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| 907 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
907 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| 908 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
908 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
| 909 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
909 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| 910 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) |
910 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| 911 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
911 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) |
| 912 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
912 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| 913 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
913 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| 914 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
914 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| 915 | * (*) value not defined in all devices. |
915 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
| 916 | * @retval None |
916 | * (*) value not defined in all devices. |
| 917 | */ |
917 | * @retval None |
| 918 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
918 | */ |
| 919 | { |
919 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
| 920 | CLEAR_BIT(DBGMCU->APB1FZ, Periphs); |
920 | { |
| 921 | } |
921 | CLEAR_BIT(DBGMCU->APB1FZ, Periphs); |
| 922 | 922 | } |
|
| 923 | /** |
923 | |
| 924 | * @brief Freeze APB2 peripherals |
924 | /** |
| 925 | * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
925 | * @brief Freeze APB2 peripherals |
| 926 | * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
926 | * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 927 | * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
927 | * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 928 | * @param Periphs This parameter can be a combination of the following values: |
928 | * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| 929 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
929 | * @param Periphs This parameter can be a combination of the following values: |
| 930 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
930 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
| 931 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
931 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
| 932 | * @retval None |
932 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
| 933 | */ |
933 | * @retval None |
| 934 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
934 | */ |
| 935 | { |
935 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
| 936 | SET_BIT(DBGMCU->APB2FZ, Periphs); |
936 | { |
| 937 | } |
937 | SET_BIT(DBGMCU->APB2FZ, Periphs); |
| 938 | 938 | } |
|
| 939 | /** |
939 | |
| 940 | * @brief Unfreeze APB2 peripherals |
940 | /** |
| 941 | * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
941 | * @brief Unfreeze APB2 peripherals |
| 942 | * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
942 | * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| 943 | * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph |
943 | * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| 944 | * @param Periphs This parameter can be a combination of the following values: |
944 | * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph |
| 945 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
945 | * @param Periphs This parameter can be a combination of the following values: |
| 946 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
946 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
| 947 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
947 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
| 948 | * @retval None |
948 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
| 949 | */ |
949 | * @retval None |
| 950 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
950 | */ |
| 951 | { |
951 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
| 952 | CLEAR_BIT(DBGMCU->APB2FZ, Periphs); |
952 | { |
| 953 | } |
953 | CLEAR_BIT(DBGMCU->APB2FZ, Periphs); |
| 954 | 954 | } |
|
| 955 | /** |
955 | |
| 956 | * @} |
956 | /** |
| 957 | */ |
957 | * @} |
| 958 | 958 | */ |
|
| 959 | #if defined(COMP_CSR_VREFOUTEN) |
959 | |
| 960 | /** @defgroup SYSTEM_LL_EF_VREFOUT VREFOUT |
960 | #if defined(COMP_CSR_VREFOUTEN) |
| 961 | * @{ |
961 | /** @defgroup SYSTEM_LL_EF_VREFOUT VREFOUT |
| 962 | */ |
962 | * @{ |
| 963 | 963 | */ |
|
| 964 | /** |
964 | |
| 965 | * @brief Enable the output of internal reference voltage (VrefInt) on I/O pin. |
965 | /** |
| 966 | * @note The VrefInt output can be routed to any I/O in group 3: |
966 | * @brief Enable the output of internal reference voltage (VrefInt) on I/O pin. |
| 967 | * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). |
967 | * @note The VrefInt output can be routed to any I/O in group 3: |
| 968 | * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). |
968 | * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). |
| 969 | * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), |
969 | * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). |
| 970 | * CH1b (PF11) or CH2b (PF12). |
970 | * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), |
| 971 | * Note: Comparator peripheral clock must be preliminarily enabled. |
971 | * CH1b (PF11) or CH2b (PF12). |
| 972 | * Refer to function "LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_COMP)". |
972 | * Note: Comparator peripheral clock must be preliminarily enabled. |
| 973 | * Note: In addition with this macro, VrefInt output buffer must be |
973 | * Refer to function "LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_COMP)". |
| 974 | * connected to the selected I/O pin. Refer to functions |
974 | * Note: In addition with this macro, VrefInt output buffer must be |
| 975 | * "LL_RI_EnableSwitchControlMode()" and "LL_RI_CloseIOSwitchLinkedToADC()". |
975 | * connected to the selected I/O pin. Refer to functions |
| 976 | * @note VrefInt output enable: Internal reference voltage connected to I/O group 3 |
976 | * "LL_RI_EnableSwitchControlMode()" and "LL_RI_CloseIOSwitchLinkedToADC()". |
| 977 | * VrefInt output disable: Internal reference voltage disconnected from I/O group 3 |
977 | * @note VrefInt output enable: Internal reference voltage connected to I/O group 3 |
| 978 | * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Enable |
978 | * VrefInt output disable: Internal reference voltage disconnected from I/O group 3 |
| 979 | * @retval None |
979 | * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Enable |
| 980 | */ |
980 | * @retval None |
| 981 | __STATIC_INLINE void LL_VREFOUT_Enable(void) |
981 | */ |
| 982 | { |
982 | __STATIC_INLINE void LL_VREFOUT_Enable(void) |
| 983 | SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN); |
983 | { |
| 984 | } |
984 | SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN); |
| 985 | 985 | } |
|
| 986 | /** |
986 | |
| 987 | * @brief Disable the output of internal reference voltage (VrefInt) on I/O pin. |
987 | /** |
| 988 | * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Disable |
988 | * @brief Disable the output of internal reference voltage (VrefInt) on I/O pin. |
| 989 | * @retval None |
989 | * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Disable |
| 990 | */ |
990 | * @retval None |
| 991 | __STATIC_INLINE void LL_VREFOUT_Disable(void) |
991 | */ |
| 992 | { |
992 | __STATIC_INLINE void LL_VREFOUT_Disable(void) |
| 993 | CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN); |
993 | { |
| 994 | } |
994 | CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN); |
| 995 | 995 | } |
|
| 996 | /** |
996 | |
| 997 | * @brief Check if output of internal reference voltage (VrefInt) is connected to I/O pin. |
997 | /** |
| 998 | * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_IsEnabled |
998 | * @brief Check if output of internal reference voltage (VrefInt) is connected to I/O pin. |
| 999 | * @retval State of bit (1 or 0). |
999 | * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_IsEnabled |
| 1000 | */ |
1000 | * @retval State of bit (1 or 0). |
| 1001 | __STATIC_INLINE uint32_t LL_VREFOUT_IsEnabled(void) |
1001 | */ |
| 1002 | { |
1002 | __STATIC_INLINE uint32_t LL_VREFOUT_IsEnabled(void) |
| 1003 | return ((READ_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) == COMP_CSR_VREFOUTEN) ? 1UL : 0UL); |
1003 | { |
| 1004 | } |
1004 | return ((READ_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) == COMP_CSR_VREFOUTEN) ? 1UL : 0UL); |
| 1005 | 1005 | } |
|
| 1006 | /** |
1006 | |
| 1007 | * @} |
1007 | /** |
| 1008 | */ |
1008 | * @} |
| 1009 | #endif /* COMP_CSR_VREFOUTEN */ |
1009 | */ |
| 1010 | 1010 | #endif /* COMP_CSR_VREFOUTEN */ |
|
| 1011 | /** @defgroup SYSTEM_LL_EF_RI RI |
1011 | |
| 1012 | * @{ |
1012 | /** @defgroup SYSTEM_LL_EF_RI RI |
| 1013 | */ |
1013 | * @{ |
| 1014 | 1014 | */ |
|
| 1015 | /** |
1015 | |
| 1016 | * @brief Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin. |
1016 | /** |
| 1017 | * @rmtoll RI_ICR IC1OS LL_RI_SetRemapInputCapture_TIM\n |
1017 | * @brief Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin. |
| 1018 | * RI_ICR IC2OS LL_RI_SetRemapInputCapture_TIM\n |
1018 | * @rmtoll RI_ICR IC1OS LL_RI_SetRemapInputCapture_TIM\n |
| 1019 | * RI_ICR IC3OS LL_RI_SetRemapInputCapture_TIM\n |
1019 | * RI_ICR IC2OS LL_RI_SetRemapInputCapture_TIM\n |
| 1020 | * RI_ICR IC4OS LL_RI_SetRemapInputCapture_TIM\n |
1020 | * RI_ICR IC3OS LL_RI_SetRemapInputCapture_TIM\n |
| 1021 | * RI_ICR TIM LL_RI_SetRemapInputCapture_TIM\n |
1021 | * RI_ICR IC4OS LL_RI_SetRemapInputCapture_TIM\n |
| 1022 | * RI_ICR IC1 LL_RI_SetRemapInputCapture_TIM\n |
1022 | * RI_ICR TIM LL_RI_SetRemapInputCapture_TIM\n |
| 1023 | * RI_ICR IC2 LL_RI_SetRemapInputCapture_TIM\n |
1023 | * RI_ICR IC1 LL_RI_SetRemapInputCapture_TIM\n |
| 1024 | * RI_ICR IC3 LL_RI_SetRemapInputCapture_TIM\n |
1024 | * RI_ICR IC2 LL_RI_SetRemapInputCapture_TIM\n |
| 1025 | * RI_ICR IC4 LL_RI_SetRemapInputCapture_TIM |
1025 | * RI_ICR IC3 LL_RI_SetRemapInputCapture_TIM\n |
| 1026 | * @param TIM_Select This parameter can be one of the following values: |
1026 | * RI_ICR IC4 LL_RI_SetRemapInputCapture_TIM |
| 1027 | * @arg @ref LL_RI_TIM_SELECT_NONE |
1027 | * @param TIM_Select This parameter can be one of the following values: |
| 1028 | * @arg @ref LL_RI_TIM_SELECT_TIM2 |
1028 | * @arg @ref LL_RI_TIM_SELECT_NONE |
| 1029 | * @arg @ref LL_RI_TIM_SELECT_TIM3 |
1029 | * @arg @ref LL_RI_TIM_SELECT_TIM2 |
| 1030 | * @arg @ref LL_RI_TIM_SELECT_TIM4 |
1030 | * @arg @ref LL_RI_TIM_SELECT_TIM3 |
| 1031 | * @param InputCaptureChannel This parameter can be one of the following values: |
1031 | * @arg @ref LL_RI_TIM_SELECT_TIM4 |
| 1032 | * @arg @ref LL_RI_INPUTCAPTURE_1 |
1032 | * @param InputCaptureChannel This parameter can be one of the following values: |
| 1033 | * @arg @ref LL_RI_INPUTCAPTURE_2 |
1033 | * @arg @ref LL_RI_INPUTCAPTURE_1 |
| 1034 | * @arg @ref LL_RI_INPUTCAPTURE_3 |
1034 | * @arg @ref LL_RI_INPUTCAPTURE_2 |
| 1035 | * @arg @ref LL_RI_INPUTCAPTURE_4 |
1035 | * @arg @ref LL_RI_INPUTCAPTURE_3 |
| 1036 | * @param Input This parameter can be one of the following values: |
1036 | * @arg @ref LL_RI_INPUTCAPTURE_4 |
| 1037 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_0 |
1037 | * @param Input This parameter can be one of the following values: |
| 1038 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_1 |
1038 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_0 |
| 1039 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_2 |
1039 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_1 |
| 1040 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_3 |
1040 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_2 |
| 1041 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_4 |
1041 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_3 |
| 1042 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_5 |
1042 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_4 |
| 1043 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_6 |
1043 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_5 |
| 1044 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_7 |
1044 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_6 |
| 1045 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_8 |
1045 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_7 |
| 1046 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_9 |
1046 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_8 |
| 1047 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_10 |
1047 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_9 |
| 1048 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_11 |
1048 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_10 |
| 1049 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*) |
1049 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_11 |
| 1050 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*) |
1050 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*) |
| 1051 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*) |
1051 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*) |
| 1052 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*) |
1052 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*) |
| 1053 | * |
1053 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*) |
| 1054 | * (*) value not defined in all devices. |
1054 | * |
| 1055 | * @retval None |
1055 | * (*) value not defined in all devices. |
| 1056 | */ |
1056 | * @retval None |
| 1057 | __STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input) |
1057 | */ |
| 1058 | { |
1058 | __STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input) |
| 1059 | MODIFY_REG(RI->ICR, |
1059 | { |
| 1060 | RI_ICR_TIM | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (InputCaptureChannel & (RI_ICR_IC4OS | RI_ICR_IC3OS | RI_ICR_IC2OS | RI_ICR_IC1OS)), |
1060 | MODIFY_REG(RI->ICR, |
| 1061 | TIM_Select | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (Input << POSITION_VAL(InputCaptureChannel))); |
1061 | RI_ICR_TIM | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (InputCaptureChannel & (RI_ICR_IC4OS | RI_ICR_IC3OS | RI_ICR_IC2OS | RI_ICR_IC1OS)), |
| 1062 | } |
1062 | TIM_Select | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (Input << POSITION_VAL(InputCaptureChannel))); |
| 1063 | 1063 | } |
|
| 1064 | /** |
1064 | |
| 1065 | * @brief Disable the TIM Input capture remap (select the standard AF) |
1065 | /** |
| 1066 | * @rmtoll RI_ICR IC1 LL_RI_DisableRemapInputCapture_TIM\n |
1066 | * @brief Disable the TIM Input capture remap (select the standard AF) |
| 1067 | * RI_ICR IC2 LL_RI_DisableRemapInputCapture_TIM\n |
1067 | * @rmtoll RI_ICR IC1 LL_RI_DisableRemapInputCapture_TIM\n |
| 1068 | * RI_ICR IC3 LL_RI_DisableRemapInputCapture_TIM\n |
1068 | * RI_ICR IC2 LL_RI_DisableRemapInputCapture_TIM\n |
| 1069 | * RI_ICR IC4 LL_RI_DisableRemapInputCapture_TIM |
1069 | * RI_ICR IC3 LL_RI_DisableRemapInputCapture_TIM\n |
| 1070 | * @param InputCaptureChannel This parameter can be a combination of the following values: |
1070 | * RI_ICR IC4 LL_RI_DisableRemapInputCapture_TIM |
| 1071 | * @arg @ref LL_RI_INPUTCAPTURE_1 |
1071 | * @param InputCaptureChannel This parameter can be a combination of the following values: |
| 1072 | * @arg @ref LL_RI_INPUTCAPTURE_2 |
1072 | * @arg @ref LL_RI_INPUTCAPTURE_1 |
| 1073 | * @arg @ref LL_RI_INPUTCAPTURE_3 |
1073 | * @arg @ref LL_RI_INPUTCAPTURE_2 |
| 1074 | * @arg @ref LL_RI_INPUTCAPTURE_4 |
1074 | * @arg @ref LL_RI_INPUTCAPTURE_3 |
| 1075 | * @retval None |
1075 | * @arg @ref LL_RI_INPUTCAPTURE_4 |
| 1076 | */ |
1076 | * @retval None |
| 1077 | __STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel) |
1077 | */ |
| 1078 | { |
1078 | __STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel) |
| 1079 | CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1))); |
1079 | { |
| 1080 | } |
1080 | CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1))); |
| 1081 | 1081 | } |
|
| 1082 | /** |
1082 | |
| 1083 | * @brief Close the routing interface Input Output switches linked to ADC. |
1083 | /** |
| 1084 | * @rmtoll RI_ASCR1 CH LL_RI_CloseIOSwitchLinkedToADC\n |
1084 | * @brief Close the routing interface Input Output switches linked to ADC. |
| 1085 | * RI_ASCR1 VCOMP LL_RI_CloseIOSwitchLinkedToADC |
1085 | * @rmtoll RI_ASCR1 CH LL_RI_CloseIOSwitchLinkedToADC\n |
| 1086 | * @param IOSwitch This parameter can be a combination of the following values: |
1086 | * RI_ASCR1 VCOMP LL_RI_CloseIOSwitchLinkedToADC |
| 1087 | * @arg @ref LL_RI_IOSWITCH_CH0 |
1087 | * @param IOSwitch This parameter can be a combination of the following values: |
| 1088 | * @arg @ref LL_RI_IOSWITCH_CH1 |
1088 | * @arg @ref LL_RI_IOSWITCH_CH0 |
| 1089 | * @arg @ref LL_RI_IOSWITCH_CH2 |
1089 | * @arg @ref LL_RI_IOSWITCH_CH1 |
| 1090 | * @arg @ref LL_RI_IOSWITCH_CH3 |
1090 | * @arg @ref LL_RI_IOSWITCH_CH2 |
| 1091 | * @arg @ref LL_RI_IOSWITCH_CH4 |
1091 | * @arg @ref LL_RI_IOSWITCH_CH3 |
| 1092 | * @arg @ref LL_RI_IOSWITCH_CH5 |
1092 | * @arg @ref LL_RI_IOSWITCH_CH4 |
| 1093 | * @arg @ref LL_RI_IOSWITCH_CH6 |
1093 | * @arg @ref LL_RI_IOSWITCH_CH5 |
| 1094 | * @arg @ref LL_RI_IOSWITCH_CH7 |
1094 | * @arg @ref LL_RI_IOSWITCH_CH6 |
| 1095 | * @arg @ref LL_RI_IOSWITCH_CH8 |
1095 | * @arg @ref LL_RI_IOSWITCH_CH7 |
| 1096 | * @arg @ref LL_RI_IOSWITCH_CH9 |
1096 | * @arg @ref LL_RI_IOSWITCH_CH8 |
| 1097 | * @arg @ref LL_RI_IOSWITCH_CH10 |
1097 | * @arg @ref LL_RI_IOSWITCH_CH9 |
| 1098 | * @arg @ref LL_RI_IOSWITCH_CH11 |
1098 | * @arg @ref LL_RI_IOSWITCH_CH10 |
| 1099 | * @arg @ref LL_RI_IOSWITCH_CH12 |
1099 | * @arg @ref LL_RI_IOSWITCH_CH11 |
| 1100 | * @arg @ref LL_RI_IOSWITCH_CH13 |
1100 | * @arg @ref LL_RI_IOSWITCH_CH12 |
| 1101 | * @arg @ref LL_RI_IOSWITCH_CH14 |
1101 | * @arg @ref LL_RI_IOSWITCH_CH13 |
| 1102 | * @arg @ref LL_RI_IOSWITCH_CH15 |
1102 | * @arg @ref LL_RI_IOSWITCH_CH14 |
| 1103 | * @arg @ref LL_RI_IOSWITCH_CH18 |
1103 | * @arg @ref LL_RI_IOSWITCH_CH15 |
| 1104 | * @arg @ref LL_RI_IOSWITCH_CH19 |
1104 | * @arg @ref LL_RI_IOSWITCH_CH18 |
| 1105 | * @arg @ref LL_RI_IOSWITCH_CH20 |
1105 | * @arg @ref LL_RI_IOSWITCH_CH19 |
| 1106 | * @arg @ref LL_RI_IOSWITCH_CH21 |
1106 | * @arg @ref LL_RI_IOSWITCH_CH20 |
| 1107 | * @arg @ref LL_RI_IOSWITCH_CH22 |
1107 | * @arg @ref LL_RI_IOSWITCH_CH21 |
| 1108 | * @arg @ref LL_RI_IOSWITCH_CH23 |
1108 | * @arg @ref LL_RI_IOSWITCH_CH22 |
| 1109 | * @arg @ref LL_RI_IOSWITCH_CH24 |
1109 | * @arg @ref LL_RI_IOSWITCH_CH23 |
| 1110 | * @arg @ref LL_RI_IOSWITCH_CH25 |
1110 | * @arg @ref LL_RI_IOSWITCH_CH24 |
| 1111 | * @arg @ref LL_RI_IOSWITCH_VCOMP |
1111 | * @arg @ref LL_RI_IOSWITCH_CH25 |
| 1112 | * @arg @ref LL_RI_IOSWITCH_CH27 (*) |
1112 | * @arg @ref LL_RI_IOSWITCH_VCOMP |
| 1113 | * @arg @ref LL_RI_IOSWITCH_CH28 (*) |
1113 | * @arg @ref LL_RI_IOSWITCH_CH27 (*) |
| 1114 | * @arg @ref LL_RI_IOSWITCH_CH29 (*) |
1114 | * @arg @ref LL_RI_IOSWITCH_CH28 (*) |
| 1115 | * @arg @ref LL_RI_IOSWITCH_CH30 (*) |
1115 | * @arg @ref LL_RI_IOSWITCH_CH29 (*) |
| 1116 | * @arg @ref LL_RI_IOSWITCH_CH31 (*) |
1116 | * @arg @ref LL_RI_IOSWITCH_CH30 (*) |
| 1117 | * |
1117 | * @arg @ref LL_RI_IOSWITCH_CH31 (*) |
| 1118 | * (*) value not defined in all devices. |
1118 | * |
| 1119 | * @retval None |
1119 | * (*) value not defined in all devices. |
| 1120 | */ |
1120 | * @retval None |
| 1121 | __STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch) |
1121 | */ |
| 1122 | { |
1122 | __STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch) |
| 1123 | SET_BIT(RI->ASCR1, IOSwitch); |
1123 | { |
| 1124 | } |
1124 | SET_BIT(RI->ASCR1, IOSwitch); |
| 1125 | 1125 | } |
|
| 1126 | /** |
1126 | |
| 1127 | * @brief Open the routing interface Input Output switches linked to ADC. |
1127 | /** |
| 1128 | * @rmtoll RI_ASCR1 CH LL_RI_OpenIOSwitchLinkedToADC\n |
1128 | * @brief Open the routing interface Input Output switches linked to ADC. |
| 1129 | * RI_ASCR1 VCOMP LL_RI_OpenIOSwitchLinkedToADC |
1129 | * @rmtoll RI_ASCR1 CH LL_RI_OpenIOSwitchLinkedToADC\n |
| 1130 | * @param IOSwitch This parameter can be a combination of the following values: |
1130 | * RI_ASCR1 VCOMP LL_RI_OpenIOSwitchLinkedToADC |
| 1131 | * @arg @ref LL_RI_IOSWITCH_CH0 |
1131 | * @param IOSwitch This parameter can be a combination of the following values: |
| 1132 | * @arg @ref LL_RI_IOSWITCH_CH1 |
1132 | * @arg @ref LL_RI_IOSWITCH_CH0 |
| 1133 | * @arg @ref LL_RI_IOSWITCH_CH2 |
1133 | * @arg @ref LL_RI_IOSWITCH_CH1 |
| 1134 | * @arg @ref LL_RI_IOSWITCH_CH3 |
1134 | * @arg @ref LL_RI_IOSWITCH_CH2 |
| 1135 | * @arg @ref LL_RI_IOSWITCH_CH4 |
1135 | * @arg @ref LL_RI_IOSWITCH_CH3 |
| 1136 | * @arg @ref LL_RI_IOSWITCH_CH5 |
1136 | * @arg @ref LL_RI_IOSWITCH_CH4 |
| 1137 | * @arg @ref LL_RI_IOSWITCH_CH6 |
1137 | * @arg @ref LL_RI_IOSWITCH_CH5 |
| 1138 | * @arg @ref LL_RI_IOSWITCH_CH7 |
1138 | * @arg @ref LL_RI_IOSWITCH_CH6 |
| 1139 | * @arg @ref LL_RI_IOSWITCH_CH8 |
1139 | * @arg @ref LL_RI_IOSWITCH_CH7 |
| 1140 | * @arg @ref LL_RI_IOSWITCH_CH9 |
1140 | * @arg @ref LL_RI_IOSWITCH_CH8 |
| 1141 | * @arg @ref LL_RI_IOSWITCH_CH10 |
1141 | * @arg @ref LL_RI_IOSWITCH_CH9 |
| 1142 | * @arg @ref LL_RI_IOSWITCH_CH11 |
1142 | * @arg @ref LL_RI_IOSWITCH_CH10 |
| 1143 | * @arg @ref LL_RI_IOSWITCH_CH12 |
1143 | * @arg @ref LL_RI_IOSWITCH_CH11 |
| 1144 | * @arg @ref LL_RI_IOSWITCH_CH13 |
1144 | * @arg @ref LL_RI_IOSWITCH_CH12 |
| 1145 | * @arg @ref LL_RI_IOSWITCH_CH14 |
1145 | * @arg @ref LL_RI_IOSWITCH_CH13 |
| 1146 | * @arg @ref LL_RI_IOSWITCH_CH15 |
1146 | * @arg @ref LL_RI_IOSWITCH_CH14 |
| 1147 | * @arg @ref LL_RI_IOSWITCH_CH18 |
1147 | * @arg @ref LL_RI_IOSWITCH_CH15 |
| 1148 | * @arg @ref LL_RI_IOSWITCH_CH19 |
1148 | * @arg @ref LL_RI_IOSWITCH_CH18 |
| 1149 | * @arg @ref LL_RI_IOSWITCH_CH20 |
1149 | * @arg @ref LL_RI_IOSWITCH_CH19 |
| 1150 | * @arg @ref LL_RI_IOSWITCH_CH21 |
1150 | * @arg @ref LL_RI_IOSWITCH_CH20 |
| 1151 | * @arg @ref LL_RI_IOSWITCH_CH22 |
1151 | * @arg @ref LL_RI_IOSWITCH_CH21 |
| 1152 | * @arg @ref LL_RI_IOSWITCH_CH23 |
1152 | * @arg @ref LL_RI_IOSWITCH_CH22 |
| 1153 | * @arg @ref LL_RI_IOSWITCH_CH24 |
1153 | * @arg @ref LL_RI_IOSWITCH_CH23 |
| 1154 | * @arg @ref LL_RI_IOSWITCH_CH25 |
1154 | * @arg @ref LL_RI_IOSWITCH_CH24 |
| 1155 | * @arg @ref LL_RI_IOSWITCH_VCOMP |
1155 | * @arg @ref LL_RI_IOSWITCH_CH25 |
| 1156 | * @arg @ref LL_RI_IOSWITCH_CH27 (*) |
1156 | * @arg @ref LL_RI_IOSWITCH_VCOMP |
| 1157 | * @arg @ref LL_RI_IOSWITCH_CH28 (*) |
1157 | * @arg @ref LL_RI_IOSWITCH_CH27 (*) |
| 1158 | * @arg @ref LL_RI_IOSWITCH_CH29 (*) |
1158 | * @arg @ref LL_RI_IOSWITCH_CH28 (*) |
| 1159 | * @arg @ref LL_RI_IOSWITCH_CH30 (*) |
1159 | * @arg @ref LL_RI_IOSWITCH_CH29 (*) |
| 1160 | * @arg @ref LL_RI_IOSWITCH_CH31 (*) |
1160 | * @arg @ref LL_RI_IOSWITCH_CH30 (*) |
| 1161 | * |
1161 | * @arg @ref LL_RI_IOSWITCH_CH31 (*) |
| 1162 | * (*) value not defined in all devices. |
1162 | * |
| 1163 | * @retval None |
1163 | * (*) value not defined in all devices. |
| 1164 | */ |
1164 | * @retval None |
| 1165 | __STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch) |
1165 | */ |
| 1166 | { |
1166 | __STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch) |
| 1167 | CLEAR_BIT(RI->ASCR1, IOSwitch); |
1167 | { |
| 1168 | } |
1168 | CLEAR_BIT(RI->ASCR1, IOSwitch); |
| 1169 | 1169 | } |
|
| 1170 | /** |
1170 | |
| 1171 | * @brief Enable the switch control mode. |
1171 | /** |
| 1172 | * @rmtoll RI_ASCR1 SCM LL_RI_EnableSwitchControlMode |
1172 | * @brief Enable the switch control mode. |
| 1173 | * @retval None |
1173 | * @rmtoll RI_ASCR1 SCM LL_RI_EnableSwitchControlMode |
| 1174 | */ |
1174 | * @retval None |
| 1175 | __STATIC_INLINE void LL_RI_EnableSwitchControlMode(void) |
1175 | */ |
| 1176 | { |
1176 | __STATIC_INLINE void LL_RI_EnableSwitchControlMode(void) |
| 1177 | SET_BIT(RI->ASCR1, RI_ASCR1_SCM); |
1177 | { |
| 1178 | } |
1178 | SET_BIT(RI->ASCR1, RI_ASCR1_SCM); |
| 1179 | 1179 | } |
|
| 1180 | /** |
1180 | |
| 1181 | * @brief Disable the switch control mode. |
1181 | /** |
| 1182 | * @rmtoll RI_ASCR1 SCM LL_RI_DisableSwitchControlMode |
1182 | * @brief Disable the switch control mode. |
| 1183 | * @retval None |
1183 | * @rmtoll RI_ASCR1 SCM LL_RI_DisableSwitchControlMode |
| 1184 | */ |
1184 | * @retval None |
| 1185 | __STATIC_INLINE void LL_RI_DisableSwitchControlMode(void) |
1185 | */ |
| 1186 | { |
1186 | __STATIC_INLINE void LL_RI_DisableSwitchControlMode(void) |
| 1187 | CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM); |
1187 | { |
| 1188 | } |
1188 | CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM); |
| 1189 | 1189 | } |
|
| 1190 | /** |
1190 | |
| 1191 | * @brief Close the routing interface Input Output switches not linked to ADC. |
1191 | /** |
| 1192 | * @rmtoll RI_ASCR2 GR10_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1192 | * @brief Close the routing interface Input Output switches not linked to ADC. |
| 1193 | * RI_ASCR2 GR10_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1193 | * @rmtoll RI_ASCR2 GR10_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1194 | * RI_ASCR2 GR10_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1194 | * RI_ASCR2 GR10_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1195 | * RI_ASCR2 GR10_4 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1195 | * RI_ASCR2 GR10_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1196 | * RI_ASCR2 GR6_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1196 | * RI_ASCR2 GR10_4 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1197 | * RI_ASCR2 GR6_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1197 | * RI_ASCR2 GR6_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1198 | * RI_ASCR2 GR5_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1198 | * RI_ASCR2 GR6_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1199 | * RI_ASCR2 GR5_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1199 | * RI_ASCR2 GR5_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1200 | * RI_ASCR2 GR5_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1200 | * RI_ASCR2 GR5_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1201 | * RI_ASCR2 GR4_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1201 | * RI_ASCR2 GR5_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1202 | * RI_ASCR2 GR4_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1202 | * RI_ASCR2 GR4_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1203 | * RI_ASCR2 GR4_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1203 | * RI_ASCR2 GR4_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1204 | * RI_ASCR2 GR4_4 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1204 | * RI_ASCR2 GR4_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1205 | * RI_ASCR2 CH0b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1205 | * RI_ASCR2 GR4_4 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1206 | * RI_ASCR2 CH1b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1206 | * RI_ASCR2 CH0b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1207 | * RI_ASCR2 CH2b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1207 | * RI_ASCR2 CH1b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1208 | * RI_ASCR2 CH3b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1208 | * RI_ASCR2 CH2b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1209 | * RI_ASCR2 CH6b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1209 | * RI_ASCR2 CH3b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1210 | * RI_ASCR2 CH7b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1210 | * RI_ASCR2 CH6b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1211 | * RI_ASCR2 CH8b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1211 | * RI_ASCR2 CH7b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1212 | * RI_ASCR2 CH9b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1212 | * RI_ASCR2 CH8b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1213 | * RI_ASCR2 CH10b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1213 | * RI_ASCR2 CH9b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1214 | * RI_ASCR2 CH11b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1214 | * RI_ASCR2 CH10b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1215 | * RI_ASCR2 CH12b LL_RI_CloseIOSwitchNotLinkedToADC\n |
1215 | * RI_ASCR2 CH11b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1216 | * RI_ASCR2 GR6_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
1216 | * RI_ASCR2 CH12b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1217 | * RI_ASCR2 GR6_4 LL_RI_CloseIOSwitchNotLinkedToADC |
1217 | * RI_ASCR2 GR6_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| 1218 | * @param IOSwitch This parameter can be a combination of the following values: |
1218 | * RI_ASCR2 GR6_4 LL_RI_CloseIOSwitchNotLinkedToADC |
| 1219 | * @arg @ref LL_RI_IOSWITCH_GR10_1 |
1219 | * @param IOSwitch This parameter can be a combination of the following values: |
| 1220 | * @arg @ref LL_RI_IOSWITCH_GR10_2 |
1220 | * @arg @ref LL_RI_IOSWITCH_GR10_1 |
| 1221 | * @arg @ref LL_RI_IOSWITCH_GR10_3 |
1221 | * @arg @ref LL_RI_IOSWITCH_GR10_2 |
| 1222 | * @arg @ref LL_RI_IOSWITCH_GR10_4 |
1222 | * @arg @ref LL_RI_IOSWITCH_GR10_3 |
| 1223 | * @arg @ref LL_RI_IOSWITCH_GR6_1 |
1223 | * @arg @ref LL_RI_IOSWITCH_GR10_4 |
| 1224 | * @arg @ref LL_RI_IOSWITCH_GR6_2 |
1224 | * @arg @ref LL_RI_IOSWITCH_GR6_1 |
| 1225 | * @arg @ref LL_RI_IOSWITCH_GR5_1 |
1225 | * @arg @ref LL_RI_IOSWITCH_GR6_2 |
| 1226 | * @arg @ref LL_RI_IOSWITCH_GR5_2 |
1226 | * @arg @ref LL_RI_IOSWITCH_GR5_1 |
| 1227 | * @arg @ref LL_RI_IOSWITCH_GR5_3 |
1227 | * @arg @ref LL_RI_IOSWITCH_GR5_2 |
| 1228 | * @arg @ref LL_RI_IOSWITCH_GR4_1 |
1228 | * @arg @ref LL_RI_IOSWITCH_GR5_3 |
| 1229 | * @arg @ref LL_RI_IOSWITCH_GR4_2 |
1229 | * @arg @ref LL_RI_IOSWITCH_GR4_1 |
| 1230 | * @arg @ref LL_RI_IOSWITCH_GR4_3 |
1230 | * @arg @ref LL_RI_IOSWITCH_GR4_2 |
| 1231 | * @arg @ref LL_RI_IOSWITCH_CH0b (*) |
1231 | * @arg @ref LL_RI_IOSWITCH_GR4_3 |
| 1232 | * @arg @ref LL_RI_IOSWITCH_CH1b (*) |
1232 | * @arg @ref LL_RI_IOSWITCH_CH0b (*) |
| 1233 | * @arg @ref LL_RI_IOSWITCH_CH2b (*) |
1233 | * @arg @ref LL_RI_IOSWITCH_CH1b (*) |
| 1234 | * @arg @ref LL_RI_IOSWITCH_CH3b (*) |
1234 | * @arg @ref LL_RI_IOSWITCH_CH2b (*) |
| 1235 | * @arg @ref LL_RI_IOSWITCH_CH6b (*) |
1235 | * @arg @ref LL_RI_IOSWITCH_CH3b (*) |
| 1236 | * @arg @ref LL_RI_IOSWITCH_CH7b (*) |
1236 | * @arg @ref LL_RI_IOSWITCH_CH6b (*) |
| 1237 | * @arg @ref LL_RI_IOSWITCH_CH8b (*) |
1237 | * @arg @ref LL_RI_IOSWITCH_CH7b (*) |
| 1238 | * @arg @ref LL_RI_IOSWITCH_CH9b (*) |
1238 | * @arg @ref LL_RI_IOSWITCH_CH8b (*) |
| 1239 | * @arg @ref LL_RI_IOSWITCH_CH10b (*) |
1239 | * @arg @ref LL_RI_IOSWITCH_CH9b (*) |
| 1240 | * @arg @ref LL_RI_IOSWITCH_CH11b (*) |
1240 | * @arg @ref LL_RI_IOSWITCH_CH10b (*) |
| 1241 | * @arg @ref LL_RI_IOSWITCH_CH12b (*) |
1241 | * @arg @ref LL_RI_IOSWITCH_CH11b (*) |
| 1242 | * @arg @ref LL_RI_IOSWITCH_GR6_3 |
1242 | * @arg @ref LL_RI_IOSWITCH_CH12b (*) |
| 1243 | * @arg @ref LL_RI_IOSWITCH_GR6_4 |
1243 | * @arg @ref LL_RI_IOSWITCH_GR6_3 |
| 1244 | * |
1244 | * @arg @ref LL_RI_IOSWITCH_GR6_4 |
| 1245 | * (*) value not defined in all devices. |
1245 | * |
| 1246 | * @retval None |
1246 | * (*) value not defined in all devices. |
| 1247 | */ |
1247 | * @retval None |
| 1248 | __STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch) |
1248 | */ |
| 1249 | { |
1249 | __STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch) |
| 1250 | SET_BIT(RI->ASCR2, IOSwitch); |
1250 | { |
| 1251 | } |
1251 | SET_BIT(RI->ASCR2, IOSwitch); |
| 1252 | 1252 | } |
|
| 1253 | /** |
1253 | |
| 1254 | * @brief Open the routing interface Input Output switches not linked to ADC. |
1254 | /** |
| 1255 | * @rmtoll RI_ASCR2 GR10_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1255 | * @brief Open the routing interface Input Output switches not linked to ADC. |
| 1256 | * RI_ASCR2 GR10_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1256 | * @rmtoll RI_ASCR2 GR10_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1257 | * RI_ASCR2 GR10_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1257 | * RI_ASCR2 GR10_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1258 | * RI_ASCR2 GR10_4 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1258 | * RI_ASCR2 GR10_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1259 | * RI_ASCR2 GR6_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1259 | * RI_ASCR2 GR10_4 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1260 | * RI_ASCR2 GR6_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1260 | * RI_ASCR2 GR6_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1261 | * RI_ASCR2 GR5_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1261 | * RI_ASCR2 GR6_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1262 | * RI_ASCR2 GR5_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1262 | * RI_ASCR2 GR5_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1263 | * RI_ASCR2 GR5_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1263 | * RI_ASCR2 GR5_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1264 | * RI_ASCR2 GR4_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1264 | * RI_ASCR2 GR5_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1265 | * RI_ASCR2 GR4_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1265 | * RI_ASCR2 GR4_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1266 | * RI_ASCR2 GR4_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1266 | * RI_ASCR2 GR4_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1267 | * RI_ASCR2 GR4_4 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1267 | * RI_ASCR2 GR4_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1268 | * RI_ASCR2 CH0b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1268 | * RI_ASCR2 GR4_4 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1269 | * RI_ASCR2 CH1b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1269 | * RI_ASCR2 CH0b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1270 | * RI_ASCR2 CH2b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1270 | * RI_ASCR2 CH1b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1271 | * RI_ASCR2 CH3b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1271 | * RI_ASCR2 CH2b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1272 | * RI_ASCR2 CH6b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1272 | * RI_ASCR2 CH3b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1273 | * RI_ASCR2 CH7b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1273 | * RI_ASCR2 CH6b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1274 | * RI_ASCR2 CH8b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1274 | * RI_ASCR2 CH7b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1275 | * RI_ASCR2 CH9b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1275 | * RI_ASCR2 CH8b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1276 | * RI_ASCR2 CH10b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1276 | * RI_ASCR2 CH9b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1277 | * RI_ASCR2 CH11b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1277 | * RI_ASCR2 CH10b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1278 | * RI_ASCR2 CH12b LL_RI_OpenIOSwitchNotLinkedToADC\n |
1278 | * RI_ASCR2 CH11b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1279 | * RI_ASCR2 GR6_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
1279 | * RI_ASCR2 CH12b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1280 | * RI_ASCR2 GR6_4 LL_RI_OpenIOSwitchNotLinkedToADC |
1280 | * RI_ASCR2 GR6_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| 1281 | * @param IOSwitch This parameter can be a combination of the following values: |
1281 | * RI_ASCR2 GR6_4 LL_RI_OpenIOSwitchNotLinkedToADC |
| 1282 | * @arg @ref LL_RI_IOSWITCH_GR10_1 |
1282 | * @param IOSwitch This parameter can be a combination of the following values: |
| 1283 | * @arg @ref LL_RI_IOSWITCH_GR10_2 |
1283 | * @arg @ref LL_RI_IOSWITCH_GR10_1 |
| 1284 | * @arg @ref LL_RI_IOSWITCH_GR10_3 |
1284 | * @arg @ref LL_RI_IOSWITCH_GR10_2 |
| 1285 | * @arg @ref LL_RI_IOSWITCH_GR10_4 |
1285 | * @arg @ref LL_RI_IOSWITCH_GR10_3 |
| 1286 | * @arg @ref LL_RI_IOSWITCH_GR6_1 |
1286 | * @arg @ref LL_RI_IOSWITCH_GR10_4 |
| 1287 | * @arg @ref LL_RI_IOSWITCH_GR6_2 |
1287 | * @arg @ref LL_RI_IOSWITCH_GR6_1 |
| 1288 | * @arg @ref LL_RI_IOSWITCH_GR5_1 |
1288 | * @arg @ref LL_RI_IOSWITCH_GR6_2 |
| 1289 | * @arg @ref LL_RI_IOSWITCH_GR5_2 |
1289 | * @arg @ref LL_RI_IOSWITCH_GR5_1 |
| 1290 | * @arg @ref LL_RI_IOSWITCH_GR5_3 |
1290 | * @arg @ref LL_RI_IOSWITCH_GR5_2 |
| 1291 | * @arg @ref LL_RI_IOSWITCH_GR4_1 |
1291 | * @arg @ref LL_RI_IOSWITCH_GR5_3 |
| 1292 | * @arg @ref LL_RI_IOSWITCH_GR4_2 |
1292 | * @arg @ref LL_RI_IOSWITCH_GR4_1 |
| 1293 | * @arg @ref LL_RI_IOSWITCH_GR4_3 |
1293 | * @arg @ref LL_RI_IOSWITCH_GR4_2 |
| 1294 | * @arg @ref LL_RI_IOSWITCH_CH0b (*) |
1294 | * @arg @ref LL_RI_IOSWITCH_GR4_3 |
| 1295 | * @arg @ref LL_RI_IOSWITCH_CH1b (*) |
1295 | * @arg @ref LL_RI_IOSWITCH_CH0b (*) |
| 1296 | * @arg @ref LL_RI_IOSWITCH_CH2b (*) |
1296 | * @arg @ref LL_RI_IOSWITCH_CH1b (*) |
| 1297 | * @arg @ref LL_RI_IOSWITCH_CH3b (*) |
1297 | * @arg @ref LL_RI_IOSWITCH_CH2b (*) |
| 1298 | * @arg @ref LL_RI_IOSWITCH_CH6b (*) |
1298 | * @arg @ref LL_RI_IOSWITCH_CH3b (*) |
| 1299 | * @arg @ref LL_RI_IOSWITCH_CH7b (*) |
1299 | * @arg @ref LL_RI_IOSWITCH_CH6b (*) |
| 1300 | * @arg @ref LL_RI_IOSWITCH_CH8b (*) |
1300 | * @arg @ref LL_RI_IOSWITCH_CH7b (*) |
| 1301 | * @arg @ref LL_RI_IOSWITCH_CH9b (*) |
1301 | * @arg @ref LL_RI_IOSWITCH_CH8b (*) |
| 1302 | * @arg @ref LL_RI_IOSWITCH_CH10b (*) |
1302 | * @arg @ref LL_RI_IOSWITCH_CH9b (*) |
| 1303 | * @arg @ref LL_RI_IOSWITCH_CH11b (*) |
1303 | * @arg @ref LL_RI_IOSWITCH_CH10b (*) |
| 1304 | * @arg @ref LL_RI_IOSWITCH_CH12b (*) |
1304 | * @arg @ref LL_RI_IOSWITCH_CH11b (*) |
| 1305 | * @arg @ref LL_RI_IOSWITCH_GR6_3 |
1305 | * @arg @ref LL_RI_IOSWITCH_CH12b (*) |
| 1306 | * @arg @ref LL_RI_IOSWITCH_GR6_4 |
1306 | * @arg @ref LL_RI_IOSWITCH_GR6_3 |
| 1307 | * |
1307 | * @arg @ref LL_RI_IOSWITCH_GR6_4 |
| 1308 | * (*) value not defined in all devices. |
1308 | * |
| 1309 | * @retval None |
1309 | * (*) value not defined in all devices. |
| 1310 | */ |
1310 | * @retval None |
| 1311 | __STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch) |
1311 | */ |
| 1312 | { |
1312 | __STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch) |
| 1313 | CLEAR_BIT(RI->ASCR2, IOSwitch); |
1313 | { |
| 1314 | } |
1314 | CLEAR_BIT(RI->ASCR2, IOSwitch); |
| 1315 | 1315 | } |
|
| 1316 | /** |
1316 | |
| 1317 | * @brief Enable Hysteresis of the input schmitt triger of the port X |
1317 | /** |
| 1318 | * @rmtoll RI_HYSCR1 PA LL_RI_EnableHysteresis\n |
1318 | * @brief Enable Hysteresis of the input schmitt trigger of the port X |
| 1319 | * RI_HYSCR1 PB LL_RI_EnableHysteresis\n |
1319 | * @rmtoll RI_HYSCR1 PA LL_RI_EnableHysteresis\n |
| 1320 | * RI_HYSCR1 PC LL_RI_EnableHysteresis\n |
1320 | * RI_HYSCR1 PB LL_RI_EnableHysteresis\n |
| 1321 | * RI_HYSCR1 PD LL_RI_EnableHysteresis\n |
1321 | * RI_HYSCR1 PC LL_RI_EnableHysteresis\n |
| 1322 | * RI_HYSCR1 PE LL_RI_EnableHysteresis\n |
1322 | * RI_HYSCR1 PD LL_RI_EnableHysteresis\n |
| 1323 | * RI_HYSCR1 PF LL_RI_EnableHysteresis\n |
1323 | * RI_HYSCR1 PE LL_RI_EnableHysteresis\n |
| 1324 | * RI_HYSCR1 PG LL_RI_EnableHysteresis\n |
1324 | * RI_HYSCR1 PF LL_RI_EnableHysteresis\n |
| 1325 | * RI_HYSCR2 PA LL_RI_EnableHysteresis\n |
1325 | * RI_HYSCR1 PG LL_RI_EnableHysteresis\n |
| 1326 | * RI_HYSCR2 PB LL_RI_EnableHysteresis\n |
1326 | * RI_HYSCR2 PA LL_RI_EnableHysteresis\n |
| 1327 | * RI_HYSCR2 PC LL_RI_EnableHysteresis\n |
1327 | * RI_HYSCR2 PB LL_RI_EnableHysteresis\n |
| 1328 | * RI_HYSCR2 PD LL_RI_EnableHysteresis\n |
1328 | * RI_HYSCR2 PC LL_RI_EnableHysteresis\n |
| 1329 | * RI_HYSCR2 PE LL_RI_EnableHysteresis\n |
1329 | * RI_HYSCR2 PD LL_RI_EnableHysteresis\n |
| 1330 | * RI_HYSCR2 PF LL_RI_EnableHysteresis\n |
1330 | * RI_HYSCR2 PE LL_RI_EnableHysteresis\n |
| 1331 | * RI_HYSCR2 PG LL_RI_EnableHysteresis\n |
1331 | * RI_HYSCR2 PF LL_RI_EnableHysteresis\n |
| 1332 | * RI_HYSCR3 PA LL_RI_EnableHysteresis\n |
1332 | * RI_HYSCR2 PG LL_RI_EnableHysteresis\n |
| 1333 | * RI_HYSCR3 PB LL_RI_EnableHysteresis\n |
1333 | * RI_HYSCR3 PA LL_RI_EnableHysteresis\n |
| 1334 | * RI_HYSCR3 PC LL_RI_EnableHysteresis\n |
1334 | * RI_HYSCR3 PB LL_RI_EnableHysteresis\n |
| 1335 | * RI_HYSCR3 PD LL_RI_EnableHysteresis\n |
1335 | * RI_HYSCR3 PC LL_RI_EnableHysteresis\n |
| 1336 | * RI_HYSCR3 PE LL_RI_EnableHysteresis\n |
1336 | * RI_HYSCR3 PD LL_RI_EnableHysteresis\n |
| 1337 | * RI_HYSCR3 PF LL_RI_EnableHysteresis\n |
1337 | * RI_HYSCR3 PE LL_RI_EnableHysteresis\n |
| 1338 | * RI_HYSCR3 PG LL_RI_EnableHysteresis\n |
1338 | * RI_HYSCR3 PF LL_RI_EnableHysteresis\n |
| 1339 | * RI_HYSCR4 PA LL_RI_EnableHysteresis\n |
1339 | * RI_HYSCR3 PG LL_RI_EnableHysteresis\n |
| 1340 | * RI_HYSCR4 PB LL_RI_EnableHysteresis\n |
1340 | * RI_HYSCR4 PA LL_RI_EnableHysteresis\n |
| 1341 | * RI_HYSCR4 PC LL_RI_EnableHysteresis\n |
1341 | * RI_HYSCR4 PB LL_RI_EnableHysteresis\n |
| 1342 | * RI_HYSCR4 PD LL_RI_EnableHysteresis\n |
1342 | * RI_HYSCR4 PC LL_RI_EnableHysteresis\n |
| 1343 | * RI_HYSCR4 PE LL_RI_EnableHysteresis\n |
1343 | * RI_HYSCR4 PD LL_RI_EnableHysteresis\n |
| 1344 | * RI_HYSCR4 PF LL_RI_EnableHysteresis\n |
1344 | * RI_HYSCR4 PE LL_RI_EnableHysteresis\n |
| 1345 | * RI_HYSCR4 PG LL_RI_EnableHysteresis |
1345 | * RI_HYSCR4 PF LL_RI_EnableHysteresis\n |
| 1346 | * @param Port This parameter can be one of the following values: |
1346 | * RI_HYSCR4 PG LL_RI_EnableHysteresis |
| 1347 | * @arg @ref LL_RI_HSYTERESIS_PORT_A |
1347 | * @param Port This parameter can be one of the following values: |
| 1348 | * @arg @ref LL_RI_HSYTERESIS_PORT_B |
1348 | * @arg @ref LL_RI_HSYTERESIS_PORT_A |
| 1349 | * @arg @ref LL_RI_HSYTERESIS_PORT_C |
1349 | * @arg @ref LL_RI_HSYTERESIS_PORT_B |
| 1350 | * @arg @ref LL_RI_HSYTERESIS_PORT_D |
1350 | * @arg @ref LL_RI_HSYTERESIS_PORT_C |
| 1351 | * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) |
1351 | * @arg @ref LL_RI_HSYTERESIS_PORT_D |
| 1352 | * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) |
1352 | * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) |
| 1353 | * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) |
1353 | * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) |
| 1354 | * |
1354 | * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) |
| 1355 | * (*) value not defined in all devices. |
1355 | * |
| 1356 | * @param Pin This parameter can be a combination of the following values: |
1356 | * (*) value not defined in all devices. |
| 1357 | * @arg @ref LL_RI_PIN_0 |
1357 | * @param Pin This parameter can be a combination of the following values: |
| 1358 | * @arg @ref LL_RI_PIN_1 |
1358 | * @arg @ref LL_RI_PIN_0 |
| 1359 | * @arg @ref LL_RI_PIN_2 |
1359 | * @arg @ref LL_RI_PIN_1 |
| 1360 | * @arg @ref LL_RI_PIN_3 |
1360 | * @arg @ref LL_RI_PIN_2 |
| 1361 | * @arg @ref LL_RI_PIN_4 |
1361 | * @arg @ref LL_RI_PIN_3 |
| 1362 | * @arg @ref LL_RI_PIN_5 |
1362 | * @arg @ref LL_RI_PIN_4 |
| 1363 | * @arg @ref LL_RI_PIN_6 |
1363 | * @arg @ref LL_RI_PIN_5 |
| 1364 | * @arg @ref LL_RI_PIN_7 |
1364 | * @arg @ref LL_RI_PIN_6 |
| 1365 | * @arg @ref LL_RI_PIN_8 |
1365 | * @arg @ref LL_RI_PIN_7 |
| 1366 | * @arg @ref LL_RI_PIN_9 |
1366 | * @arg @ref LL_RI_PIN_8 |
| 1367 | * @arg @ref LL_RI_PIN_10 |
1367 | * @arg @ref LL_RI_PIN_9 |
| 1368 | * @arg @ref LL_RI_PIN_11 |
1368 | * @arg @ref LL_RI_PIN_10 |
| 1369 | * @arg @ref LL_RI_PIN_12 |
1369 | * @arg @ref LL_RI_PIN_11 |
| 1370 | * @arg @ref LL_RI_PIN_13 |
1370 | * @arg @ref LL_RI_PIN_12 |
| 1371 | * @arg @ref LL_RI_PIN_14 |
1371 | * @arg @ref LL_RI_PIN_13 |
| 1372 | * @arg @ref LL_RI_PIN_15 |
1372 | * @arg @ref LL_RI_PIN_14 |
| 1373 | * @arg @ref LL_RI_PIN_ALL |
1373 | * @arg @ref LL_RI_PIN_15 |
| 1374 | * @retval None |
1374 | * @arg @ref LL_RI_PIN_ALL |
| 1375 | */ |
1375 | * @retval None |
| 1376 | __STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin) |
1376 | */ |
| 1377 | { |
1377 | __STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin) |
| 1378 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1U)); |
1378 | { |
| 1379 | CLEAR_BIT(*reg, Pin << (16U * (Port & 1U))); |
1379 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1U)); |
| 1380 | } |
1380 | CLEAR_BIT(*reg, Pin << (16U * (Port & 1U))); |
| 1381 | 1381 | } |
|
| 1382 | /** |
1382 | |
| 1383 | * @brief Disable Hysteresis of the input schmitt triger of the port X |
1383 | /** |
| 1384 | * @rmtoll RI_HYSCR1 PA LL_RI_DisableHysteresis\n |
1384 | * @brief Disable Hysteresis of the input schmitt trigger of the port X |
| 1385 | * RI_HYSCR1 PB LL_RI_DisableHysteresis\n |
1385 | * @rmtoll RI_HYSCR1 PA LL_RI_DisableHysteresis\n |
| 1386 | * RI_HYSCR1 PC LL_RI_DisableHysteresis\n |
1386 | * RI_HYSCR1 PB LL_RI_DisableHysteresis\n |
| 1387 | * RI_HYSCR1 PD LL_RI_DisableHysteresis\n |
1387 | * RI_HYSCR1 PC LL_RI_DisableHysteresis\n |
| 1388 | * RI_HYSCR1 PE LL_RI_DisableHysteresis\n |
1388 | * RI_HYSCR1 PD LL_RI_DisableHysteresis\n |
| 1389 | * RI_HYSCR1 PF LL_RI_DisableHysteresis\n |
1389 | * RI_HYSCR1 PE LL_RI_DisableHysteresis\n |
| 1390 | * RI_HYSCR1 PG LL_RI_DisableHysteresis\n |
1390 | * RI_HYSCR1 PF LL_RI_DisableHysteresis\n |
| 1391 | * RI_HYSCR2 PA LL_RI_DisableHysteresis\n |
1391 | * RI_HYSCR1 PG LL_RI_DisableHysteresis\n |
| 1392 | * RI_HYSCR2 PB LL_RI_DisableHysteresis\n |
1392 | * RI_HYSCR2 PA LL_RI_DisableHysteresis\n |
| 1393 | * RI_HYSCR2 PC LL_RI_DisableHysteresis\n |
1393 | * RI_HYSCR2 PB LL_RI_DisableHysteresis\n |
| 1394 | * RI_HYSCR2 PD LL_RI_DisableHysteresis\n |
1394 | * RI_HYSCR2 PC LL_RI_DisableHysteresis\n |
| 1395 | * RI_HYSCR2 PE LL_RI_DisableHysteresis\n |
1395 | * RI_HYSCR2 PD LL_RI_DisableHysteresis\n |
| 1396 | * RI_HYSCR2 PF LL_RI_DisableHysteresis\n |
1396 | * RI_HYSCR2 PE LL_RI_DisableHysteresis\n |
| 1397 | * RI_HYSCR2 PG LL_RI_DisableHysteresis\n |
1397 | * RI_HYSCR2 PF LL_RI_DisableHysteresis\n |
| 1398 | * RI_HYSCR3 PA LL_RI_DisableHysteresis\n |
1398 | * RI_HYSCR2 PG LL_RI_DisableHysteresis\n |
| 1399 | * RI_HYSCR3 PB LL_RI_DisableHysteresis\n |
1399 | * RI_HYSCR3 PA LL_RI_DisableHysteresis\n |
| 1400 | * RI_HYSCR3 PC LL_RI_DisableHysteresis\n |
1400 | * RI_HYSCR3 PB LL_RI_DisableHysteresis\n |
| 1401 | * RI_HYSCR3 PD LL_RI_DisableHysteresis\n |
1401 | * RI_HYSCR3 PC LL_RI_DisableHysteresis\n |
| 1402 | * RI_HYSCR3 PE LL_RI_DisableHysteresis\n |
1402 | * RI_HYSCR3 PD LL_RI_DisableHysteresis\n |
| 1403 | * RI_HYSCR3 PF LL_RI_DisableHysteresis\n |
1403 | * RI_HYSCR3 PE LL_RI_DisableHysteresis\n |
| 1404 | * RI_HYSCR3 PG LL_RI_DisableHysteresis\n |
1404 | * RI_HYSCR3 PF LL_RI_DisableHysteresis\n |
| 1405 | * RI_HYSCR4 PA LL_RI_DisableHysteresis\n |
1405 | * RI_HYSCR3 PG LL_RI_DisableHysteresis\n |
| 1406 | * RI_HYSCR4 PB LL_RI_DisableHysteresis\n |
1406 | * RI_HYSCR4 PA LL_RI_DisableHysteresis\n |
| 1407 | * RI_HYSCR4 PC LL_RI_DisableHysteresis\n |
1407 | * RI_HYSCR4 PB LL_RI_DisableHysteresis\n |
| 1408 | * RI_HYSCR4 PD LL_RI_DisableHysteresis\n |
1408 | * RI_HYSCR4 PC LL_RI_DisableHysteresis\n |
| 1409 | * RI_HYSCR4 PE LL_RI_DisableHysteresis\n |
1409 | * RI_HYSCR4 PD LL_RI_DisableHysteresis\n |
| 1410 | * RI_HYSCR4 PF LL_RI_DisableHysteresis\n |
1410 | * RI_HYSCR4 PE LL_RI_DisableHysteresis\n |
| 1411 | * RI_HYSCR4 PG LL_RI_DisableHysteresis |
1411 | * RI_HYSCR4 PF LL_RI_DisableHysteresis\n |
| 1412 | * @param Port This parameter can be one of the following values: |
1412 | * RI_HYSCR4 PG LL_RI_DisableHysteresis |
| 1413 | * @arg @ref LL_RI_HSYTERESIS_PORT_A |
1413 | * @param Port This parameter can be one of the following values: |
| 1414 | * @arg @ref LL_RI_HSYTERESIS_PORT_B |
1414 | * @arg @ref LL_RI_HSYTERESIS_PORT_A |
| 1415 | * @arg @ref LL_RI_HSYTERESIS_PORT_C |
1415 | * @arg @ref LL_RI_HSYTERESIS_PORT_B |
| 1416 | * @arg @ref LL_RI_HSYTERESIS_PORT_D |
1416 | * @arg @ref LL_RI_HSYTERESIS_PORT_C |
| 1417 | * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) |
1417 | * @arg @ref LL_RI_HSYTERESIS_PORT_D |
| 1418 | * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) |
1418 | * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) |
| 1419 | * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) |
1419 | * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) |
| 1420 | * |
1420 | * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) |
| 1421 | * (*) value not defined in all devices. |
1421 | * |
| 1422 | * @param Pin This parameter can be a combination of the following values: |
1422 | * (*) value not defined in all devices. |
| 1423 | * @arg @ref LL_RI_PIN_0 |
1423 | * @param Pin This parameter can be a combination of the following values: |
| 1424 | * @arg @ref LL_RI_PIN_1 |
1424 | * @arg @ref LL_RI_PIN_0 |
| 1425 | * @arg @ref LL_RI_PIN_2 |
1425 | * @arg @ref LL_RI_PIN_1 |
| 1426 | * @arg @ref LL_RI_PIN_3 |
1426 | * @arg @ref LL_RI_PIN_2 |
| 1427 | * @arg @ref LL_RI_PIN_4 |
1427 | * @arg @ref LL_RI_PIN_3 |
| 1428 | * @arg @ref LL_RI_PIN_5 |
1428 | * @arg @ref LL_RI_PIN_4 |
| 1429 | * @arg @ref LL_RI_PIN_6 |
1429 | * @arg @ref LL_RI_PIN_5 |
| 1430 | * @arg @ref LL_RI_PIN_7 |
1430 | * @arg @ref LL_RI_PIN_6 |
| 1431 | * @arg @ref LL_RI_PIN_8 |
1431 | * @arg @ref LL_RI_PIN_7 |
| 1432 | * @arg @ref LL_RI_PIN_9 |
1432 | * @arg @ref LL_RI_PIN_8 |
| 1433 | * @arg @ref LL_RI_PIN_10 |
1433 | * @arg @ref LL_RI_PIN_9 |
| 1434 | * @arg @ref LL_RI_PIN_11 |
1434 | * @arg @ref LL_RI_PIN_10 |
| 1435 | * @arg @ref LL_RI_PIN_12 |
1435 | * @arg @ref LL_RI_PIN_11 |
| 1436 | * @arg @ref LL_RI_PIN_13 |
1436 | * @arg @ref LL_RI_PIN_12 |
| 1437 | * @arg @ref LL_RI_PIN_14 |
1437 | * @arg @ref LL_RI_PIN_13 |
| 1438 | * @arg @ref LL_RI_PIN_15 |
1438 | * @arg @ref LL_RI_PIN_14 |
| 1439 | * @arg @ref LL_RI_PIN_ALL |
1439 | * @arg @ref LL_RI_PIN_15 |
| 1440 | * @retval None |
1440 | * @arg @ref LL_RI_PIN_ALL |
| 1441 | */ |
1441 | * @retval None |
| 1442 | __STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin) |
1442 | */ |
| 1443 | { |
1443 | __STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin) |
| 1444 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1U) << 2U)); |
1444 | { |
| 1445 | SET_BIT(*reg, Pin << (16U * (Port & 1U))); |
1445 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1U) << 2U)); |
| 1446 | } |
1446 | SET_BIT(*reg, Pin << (16U * (Port & 1U))); |
| 1447 | 1447 | } |
|
| 1448 | #if defined(RI_ASMR1_PA) |
1448 | |
| 1449 | /** |
1449 | #if defined(RI_ASMR1_PA) |
| 1450 | * @brief Control analog switches of port X through the ADC interface or RI_ASCRx registers. |
1450 | /** |
| 1451 | * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByADC\n |
1451 | * @brief Control analog switches of port X through the ADC interface or RI_ASCRx registers. |
| 1452 | * RI_ASMR1 PB LL_RI_ControlSwitchByADC\n |
1452 | * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByADC\n |
| 1453 | * RI_ASMR1 PC LL_RI_ControlSwitchByADC\n |
1453 | * RI_ASMR1 PB LL_RI_ControlSwitchByADC\n |
| 1454 | * RI_ASMR1 PF LL_RI_ControlSwitchByADC\n |
1454 | * RI_ASMR1 PC LL_RI_ControlSwitchByADC\n |
| 1455 | * RI_ASMR1 PG LL_RI_ControlSwitchByADC\n |
1455 | * RI_ASMR1 PF LL_RI_ControlSwitchByADC\n |
| 1456 | * RI_ASMR2 PA LL_RI_ControlSwitchByADC\n |
1456 | * RI_ASMR1 PG LL_RI_ControlSwitchByADC\n |
| 1457 | * RI_ASMR2 PB LL_RI_ControlSwitchByADC\n |
1457 | * RI_ASMR2 PA LL_RI_ControlSwitchByADC\n |
| 1458 | * RI_ASMR2 PC LL_RI_ControlSwitchByADC\n |
1458 | * RI_ASMR2 PB LL_RI_ControlSwitchByADC\n |
| 1459 | * RI_ASMR2 PF LL_RI_ControlSwitchByADC\n |
1459 | * RI_ASMR2 PC LL_RI_ControlSwitchByADC\n |
| 1460 | * RI_ASMR2 PG LL_RI_ControlSwitchByADC\n |
1460 | * RI_ASMR2 PF LL_RI_ControlSwitchByADC\n |
| 1461 | * RI_ASMR3 PA LL_RI_ControlSwitchByADC\n |
1461 | * RI_ASMR2 PG LL_RI_ControlSwitchByADC\n |
| 1462 | * RI_ASMR3 PB LL_RI_ControlSwitchByADC\n |
1462 | * RI_ASMR3 PA LL_RI_ControlSwitchByADC\n |
| 1463 | * RI_ASMR3 PC LL_RI_ControlSwitchByADC\n |
1463 | * RI_ASMR3 PB LL_RI_ControlSwitchByADC\n |
| 1464 | * RI_ASMR3 PF LL_RI_ControlSwitchByADC\n |
1464 | * RI_ASMR3 PC LL_RI_ControlSwitchByADC\n |
| 1465 | * RI_ASMR3 PG LL_RI_ControlSwitchByADC\n |
1465 | * RI_ASMR3 PF LL_RI_ControlSwitchByADC\n |
| 1466 | * RI_ASMR4 PA LL_RI_ControlSwitchByADC\n |
1466 | * RI_ASMR3 PG LL_RI_ControlSwitchByADC\n |
| 1467 | * RI_ASMR4 PB LL_RI_ControlSwitchByADC\n |
1467 | * RI_ASMR4 PA LL_RI_ControlSwitchByADC\n |
| 1468 | * RI_ASMR4 PC LL_RI_ControlSwitchByADC\n |
1468 | * RI_ASMR4 PB LL_RI_ControlSwitchByADC\n |
| 1469 | * RI_ASMR4 PF LL_RI_ControlSwitchByADC\n |
1469 | * RI_ASMR4 PC LL_RI_ControlSwitchByADC\n |
| 1470 | * RI_ASMR4 PG LL_RI_ControlSwitchByADC\n |
1470 | * RI_ASMR4 PF LL_RI_ControlSwitchByADC\n |
| 1471 | * RI_ASMR5 PA LL_RI_ControlSwitchByADC\n |
1471 | * RI_ASMR4 PG LL_RI_ControlSwitchByADC\n |
| 1472 | * RI_ASMR5 PB LL_RI_ControlSwitchByADC\n |
1472 | * RI_ASMR5 PA LL_RI_ControlSwitchByADC\n |
| 1473 | * RI_ASMR5 PC LL_RI_ControlSwitchByADC\n |
1473 | * RI_ASMR5 PB LL_RI_ControlSwitchByADC\n |
| 1474 | * RI_ASMR5 PF LL_RI_ControlSwitchByADC\n |
1474 | * RI_ASMR5 PC LL_RI_ControlSwitchByADC\n |
| 1475 | * RI_ASMR5 PG LL_RI_ControlSwitchByADC |
1475 | * RI_ASMR5 PF LL_RI_ControlSwitchByADC\n |
| 1476 | * @param Port This parameter can be one of the following values: |
1476 | * RI_ASMR5 PG LL_RI_ControlSwitchByADC |
| 1477 | * @arg @ref LL_RI_PORT_A |
1477 | * @param Port This parameter can be one of the following values: |
| 1478 | * @arg @ref LL_RI_PORT_B |
1478 | * @arg @ref LL_RI_PORT_A |
| 1479 | * @arg @ref LL_RI_PORT_C |
1479 | * @arg @ref LL_RI_PORT_B |
| 1480 | * @arg @ref LL_RI_PORT_F (*) |
1480 | * @arg @ref LL_RI_PORT_C |
| 1481 | * @arg @ref LL_RI_PORT_G (*) |
1481 | * @arg @ref LL_RI_PORT_F (*) |
| 1482 | * |
1482 | * @arg @ref LL_RI_PORT_G (*) |
| 1483 | * (*) value not defined in all devices. |
1483 | * |
| 1484 | * @param Pin This parameter can be a combination of the following values: |
1484 | * (*) value not defined in all devices. |
| 1485 | * @arg @ref LL_RI_PIN_0 |
1485 | * @param Pin This parameter can be a combination of the following values: |
| 1486 | * @arg @ref LL_RI_PIN_1 |
1486 | * @arg @ref LL_RI_PIN_0 |
| 1487 | * @arg @ref LL_RI_PIN_2 |
1487 | * @arg @ref LL_RI_PIN_1 |
| 1488 | * @arg @ref LL_RI_PIN_3 |
1488 | * @arg @ref LL_RI_PIN_2 |
| 1489 | * @arg @ref LL_RI_PIN_4 |
1489 | * @arg @ref LL_RI_PIN_3 |
| 1490 | * @arg @ref LL_RI_PIN_5 |
1490 | * @arg @ref LL_RI_PIN_4 |
| 1491 | * @arg @ref LL_RI_PIN_6 |
1491 | * @arg @ref LL_RI_PIN_5 |
| 1492 | * @arg @ref LL_RI_PIN_7 |
1492 | * @arg @ref LL_RI_PIN_6 |
| 1493 | * @arg @ref LL_RI_PIN_8 |
1493 | * @arg @ref LL_RI_PIN_7 |
| 1494 | * @arg @ref LL_RI_PIN_9 |
1494 | * @arg @ref LL_RI_PIN_8 |
| 1495 | * @arg @ref LL_RI_PIN_10 |
1495 | * @arg @ref LL_RI_PIN_9 |
| 1496 | * @arg @ref LL_RI_PIN_11 |
1496 | * @arg @ref LL_RI_PIN_10 |
| 1497 | * @arg @ref LL_RI_PIN_12 |
1497 | * @arg @ref LL_RI_PIN_11 |
| 1498 | * @arg @ref LL_RI_PIN_13 |
1498 | * @arg @ref LL_RI_PIN_12 |
| 1499 | * @arg @ref LL_RI_PIN_14 |
1499 | * @arg @ref LL_RI_PIN_13 |
| 1500 | * @arg @ref LL_RI_PIN_15 |
1500 | * @arg @ref LL_RI_PIN_14 |
| 1501 | * @arg @ref LL_RI_PIN_ALL |
1501 | * @arg @ref LL_RI_PIN_15 |
| 1502 | * @retval None |
1502 | * @arg @ref LL_RI_PIN_ALL |
| 1503 | */ |
1503 | * @retval None |
| 1504 | __STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin) |
1504 | */ |
| 1505 | { |
1505 | __STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin) |
| 1506 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); |
1506 | { |
| 1507 | CLEAR_BIT(*reg, Pin); |
1507 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); |
| 1508 | } |
1508 | CLEAR_BIT(*reg, Pin); |
| 1509 | #endif /* RI_ASMR1_PA */ |
1509 | } |
| 1510 | 1510 | #endif /* RI_ASMR1_PA */ |
|
| 1511 | #if defined(RI_ASMR1_PA) |
1511 | |
| 1512 | /** |
1512 | #if defined(RI_ASMR1_PA) |
| 1513 | * @brief Control analog switches of port X by the timer OC. |
1513 | /** |
| 1514 | * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByTIM\n |
1514 | * @brief Control analog switches of port X by the timer OC. |
| 1515 | * RI_ASMR1 PB LL_RI_ControlSwitchByTIM\n |
1515 | * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByTIM\n |
| 1516 | * RI_ASMR1 PC LL_RI_ControlSwitchByTIM\n |
1516 | * RI_ASMR1 PB LL_RI_ControlSwitchByTIM\n |
| 1517 | * RI_ASMR1 PF LL_RI_ControlSwitchByTIM\n |
1517 | * RI_ASMR1 PC LL_RI_ControlSwitchByTIM\n |
| 1518 | * RI_ASMR1 PG LL_RI_ControlSwitchByTIM\n |
1518 | * RI_ASMR1 PF LL_RI_ControlSwitchByTIM\n |
| 1519 | * RI_ASMR2 PA LL_RI_ControlSwitchByTIM\n |
1519 | * RI_ASMR1 PG LL_RI_ControlSwitchByTIM\n |
| 1520 | * RI_ASMR2 PB LL_RI_ControlSwitchByTIM\n |
1520 | * RI_ASMR2 PA LL_RI_ControlSwitchByTIM\n |
| 1521 | * RI_ASMR2 PC LL_RI_ControlSwitchByTIM\n |
1521 | * RI_ASMR2 PB LL_RI_ControlSwitchByTIM\n |
| 1522 | * RI_ASMR2 PF LL_RI_ControlSwitchByTIM\n |
1522 | * RI_ASMR2 PC LL_RI_ControlSwitchByTIM\n |
| 1523 | * RI_ASMR2 PG LL_RI_ControlSwitchByTIM\n |
1523 | * RI_ASMR2 PF LL_RI_ControlSwitchByTIM\n |
| 1524 | * RI_ASMR3 PA LL_RI_ControlSwitchByTIM\n |
1524 | * RI_ASMR2 PG LL_RI_ControlSwitchByTIM\n |
| 1525 | * RI_ASMR3 PB LL_RI_ControlSwitchByTIM\n |
1525 | * RI_ASMR3 PA LL_RI_ControlSwitchByTIM\n |
| 1526 | * RI_ASMR3 PC LL_RI_ControlSwitchByTIM\n |
1526 | * RI_ASMR3 PB LL_RI_ControlSwitchByTIM\n |
| 1527 | * RI_ASMR3 PF LL_RI_ControlSwitchByTIM\n |
1527 | * RI_ASMR3 PC LL_RI_ControlSwitchByTIM\n |
| 1528 | * RI_ASMR3 PG LL_RI_ControlSwitchByTIM\n |
1528 | * RI_ASMR3 PF LL_RI_ControlSwitchByTIM\n |
| 1529 | * RI_ASMR4 PA LL_RI_ControlSwitchByTIM\n |
1529 | * RI_ASMR3 PG LL_RI_ControlSwitchByTIM\n |
| 1530 | * RI_ASMR4 PB LL_RI_ControlSwitchByTIM\n |
1530 | * RI_ASMR4 PA LL_RI_ControlSwitchByTIM\n |
| 1531 | * RI_ASMR4 PC LL_RI_ControlSwitchByTIM\n |
1531 | * RI_ASMR4 PB LL_RI_ControlSwitchByTIM\n |
| 1532 | * RI_ASMR4 PF LL_RI_ControlSwitchByTIM\n |
1532 | * RI_ASMR4 PC LL_RI_ControlSwitchByTIM\n |
| 1533 | * RI_ASMR4 PG LL_RI_ControlSwitchByTIM\n |
1533 | * RI_ASMR4 PF LL_RI_ControlSwitchByTIM\n |
| 1534 | * RI_ASMR5 PA LL_RI_ControlSwitchByTIM\n |
1534 | * RI_ASMR4 PG LL_RI_ControlSwitchByTIM\n |
| 1535 | * RI_ASMR5 PB LL_RI_ControlSwitchByTIM\n |
1535 | * RI_ASMR5 PA LL_RI_ControlSwitchByTIM\n |
| 1536 | * RI_ASMR5 PC LL_RI_ControlSwitchByTIM\n |
1536 | * RI_ASMR5 PB LL_RI_ControlSwitchByTIM\n |
| 1537 | * RI_ASMR5 PF LL_RI_ControlSwitchByTIM\n |
1537 | * RI_ASMR5 PC LL_RI_ControlSwitchByTIM\n |
| 1538 | * RI_ASMR5 PG LL_RI_ControlSwitchByTIM |
1538 | * RI_ASMR5 PF LL_RI_ControlSwitchByTIM\n |
| 1539 | * @param Port This parameter can be one of the following values: |
1539 | * RI_ASMR5 PG LL_RI_ControlSwitchByTIM |
| 1540 | * @arg @ref LL_RI_PORT_A |
1540 | * @param Port This parameter can be one of the following values: |
| 1541 | * @arg @ref LL_RI_PORT_B |
1541 | * @arg @ref LL_RI_PORT_A |
| 1542 | * @arg @ref LL_RI_PORT_C |
1542 | * @arg @ref LL_RI_PORT_B |
| 1543 | * @arg @ref LL_RI_PORT_F (*) |
1543 | * @arg @ref LL_RI_PORT_C |
| 1544 | * @arg @ref LL_RI_PORT_G (*) |
1544 | * @arg @ref LL_RI_PORT_F (*) |
| 1545 | * |
1545 | * @arg @ref LL_RI_PORT_G (*) |
| 1546 | * (*) value not defined in all devices. |
1546 | * |
| 1547 | * @param Pin This parameter can be a combination of the following values: |
1547 | * (*) value not defined in all devices. |
| 1548 | * @arg @ref LL_RI_PIN_0 |
1548 | * @param Pin This parameter can be a combination of the following values: |
| 1549 | * @arg @ref LL_RI_PIN_1 |
1549 | * @arg @ref LL_RI_PIN_0 |
| 1550 | * @arg @ref LL_RI_PIN_2 |
1550 | * @arg @ref LL_RI_PIN_1 |
| 1551 | * @arg @ref LL_RI_PIN_3 |
1551 | * @arg @ref LL_RI_PIN_2 |
| 1552 | * @arg @ref LL_RI_PIN_4 |
1552 | * @arg @ref LL_RI_PIN_3 |
| 1553 | * @arg @ref LL_RI_PIN_5 |
1553 | * @arg @ref LL_RI_PIN_4 |
| 1554 | * @arg @ref LL_RI_PIN_6 |
1554 | * @arg @ref LL_RI_PIN_5 |
| 1555 | * @arg @ref LL_RI_PIN_7 |
1555 | * @arg @ref LL_RI_PIN_6 |
| 1556 | * @arg @ref LL_RI_PIN_8 |
1556 | * @arg @ref LL_RI_PIN_7 |
| 1557 | * @arg @ref LL_RI_PIN_9 |
1557 | * @arg @ref LL_RI_PIN_8 |
| 1558 | * @arg @ref LL_RI_PIN_10 |
1558 | * @arg @ref LL_RI_PIN_9 |
| 1559 | * @arg @ref LL_RI_PIN_11 |
1559 | * @arg @ref LL_RI_PIN_10 |
| 1560 | * @arg @ref LL_RI_PIN_12 |
1560 | * @arg @ref LL_RI_PIN_11 |
| 1561 | * @arg @ref LL_RI_PIN_13 |
1561 | * @arg @ref LL_RI_PIN_12 |
| 1562 | * @arg @ref LL_RI_PIN_14 |
1562 | * @arg @ref LL_RI_PIN_13 |
| 1563 | * @arg @ref LL_RI_PIN_15 |
1563 | * @arg @ref LL_RI_PIN_14 |
| 1564 | * @arg @ref LL_RI_PIN_ALL |
1564 | * @arg @ref LL_RI_PIN_15 |
| 1565 | * @retval None |
1565 | * @arg @ref LL_RI_PIN_ALL |
| 1566 | */ |
1566 | * @retval None |
| 1567 | __STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin) |
1567 | */ |
| 1568 | { |
1568 | __STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin) |
| 1569 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); |
1569 | { |
| 1570 | SET_BIT(*reg, Pin); |
1570 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); |
| 1571 | } |
1571 | SET_BIT(*reg, Pin); |
| 1572 | #endif /* RI_ASMR1_PA */ |
1572 | } |
| 1573 | 1573 | #endif /* RI_ASMR1_PA */ |
|
| 1574 | #if defined(RI_CMR1_PA) |
1574 | |
| 1575 | /** |
1575 | #if defined(RI_CMR1_PA) |
| 1576 | * @brief Mask the input of port X during the capacitive sensing acquisition. |
1576 | /** |
| 1577 | * @rmtoll RI_CMR1 PA LL_RI_MaskChannelDuringAcquisition\n |
1577 | * @brief Mask the input of port X during the capacitive sensing acquisition. |
| 1578 | * RI_CMR1 PB LL_RI_MaskChannelDuringAcquisition\n |
1578 | * @rmtoll RI_CMR1 PA LL_RI_MaskChannelDuringAcquisition\n |
| 1579 | * RI_CMR1 PC LL_RI_MaskChannelDuringAcquisition\n |
1579 | * RI_CMR1 PB LL_RI_MaskChannelDuringAcquisition\n |
| 1580 | * RI_CMR1 PF LL_RI_MaskChannelDuringAcquisition\n |
1580 | * RI_CMR1 PC LL_RI_MaskChannelDuringAcquisition\n |
| 1581 | * RI_CMR1 PG LL_RI_MaskChannelDuringAcquisition\n |
1581 | * RI_CMR1 PF LL_RI_MaskChannelDuringAcquisition\n |
| 1582 | * RI_CMR2 PA LL_RI_MaskChannelDuringAcquisition\n |
1582 | * RI_CMR1 PG LL_RI_MaskChannelDuringAcquisition\n |
| 1583 | * RI_CMR2 PB LL_RI_MaskChannelDuringAcquisition\n |
1583 | * RI_CMR2 PA LL_RI_MaskChannelDuringAcquisition\n |
| 1584 | * RI_CMR2 PC LL_RI_MaskChannelDuringAcquisition\n |
1584 | * RI_CMR2 PB LL_RI_MaskChannelDuringAcquisition\n |
| 1585 | * RI_CMR2 PF LL_RI_MaskChannelDuringAcquisition\n |
1585 | * RI_CMR2 PC LL_RI_MaskChannelDuringAcquisition\n |
| 1586 | * RI_CMR2 PG LL_RI_MaskChannelDuringAcquisition\n |
1586 | * RI_CMR2 PF LL_RI_MaskChannelDuringAcquisition\n |
| 1587 | * RI_CMR3 PA LL_RI_MaskChannelDuringAcquisition\n |
1587 | * RI_CMR2 PG LL_RI_MaskChannelDuringAcquisition\n |
| 1588 | * RI_CMR3 PB LL_RI_MaskChannelDuringAcquisition\n |
1588 | * RI_CMR3 PA LL_RI_MaskChannelDuringAcquisition\n |
| 1589 | * RI_CMR3 PC LL_RI_MaskChannelDuringAcquisition\n |
1589 | * RI_CMR3 PB LL_RI_MaskChannelDuringAcquisition\n |
| 1590 | * RI_CMR3 PF LL_RI_MaskChannelDuringAcquisition\n |
1590 | * RI_CMR3 PC LL_RI_MaskChannelDuringAcquisition\n |
| 1591 | * RI_CMR3 PG LL_RI_MaskChannelDuringAcquisition\n |
1591 | * RI_CMR3 PF LL_RI_MaskChannelDuringAcquisition\n |
| 1592 | * RI_CMR4 PA LL_RI_MaskChannelDuringAcquisition\n |
1592 | * RI_CMR3 PG LL_RI_MaskChannelDuringAcquisition\n |
| 1593 | * RI_CMR4 PB LL_RI_MaskChannelDuringAcquisition\n |
1593 | * RI_CMR4 PA LL_RI_MaskChannelDuringAcquisition\n |
| 1594 | * RI_CMR4 PC LL_RI_MaskChannelDuringAcquisition\n |
1594 | * RI_CMR4 PB LL_RI_MaskChannelDuringAcquisition\n |
| 1595 | * RI_CMR4 PF LL_RI_MaskChannelDuringAcquisition\n |
1595 | * RI_CMR4 PC LL_RI_MaskChannelDuringAcquisition\n |
| 1596 | * RI_CMR4 PG LL_RI_MaskChannelDuringAcquisition\n |
1596 | * RI_CMR4 PF LL_RI_MaskChannelDuringAcquisition\n |
| 1597 | * RI_CMR5 PA LL_RI_MaskChannelDuringAcquisition\n |
1597 | * RI_CMR4 PG LL_RI_MaskChannelDuringAcquisition\n |
| 1598 | * RI_CMR5 PB LL_RI_MaskChannelDuringAcquisition\n |
1598 | * RI_CMR5 PA LL_RI_MaskChannelDuringAcquisition\n |
| 1599 | * RI_CMR5 PC LL_RI_MaskChannelDuringAcquisition\n |
1599 | * RI_CMR5 PB LL_RI_MaskChannelDuringAcquisition\n |
| 1600 | * RI_CMR5 PF LL_RI_MaskChannelDuringAcquisition\n |
1600 | * RI_CMR5 PC LL_RI_MaskChannelDuringAcquisition\n |
| 1601 | * RI_CMR5 PG LL_RI_MaskChannelDuringAcquisition |
1601 | * RI_CMR5 PF LL_RI_MaskChannelDuringAcquisition\n |
| 1602 | * @param Port This parameter can be one of the following values: |
1602 | * RI_CMR5 PG LL_RI_MaskChannelDuringAcquisition |
| 1603 | * @arg @ref LL_RI_PORT_A |
1603 | * @param Port This parameter can be one of the following values: |
| 1604 | * @arg @ref LL_RI_PORT_B |
1604 | * @arg @ref LL_RI_PORT_A |
| 1605 | * @arg @ref LL_RI_PORT_C |
1605 | * @arg @ref LL_RI_PORT_B |
| 1606 | * @arg @ref LL_RI_PORT_F (*) |
1606 | * @arg @ref LL_RI_PORT_C |
| 1607 | * @arg @ref LL_RI_PORT_G (*) |
1607 | * @arg @ref LL_RI_PORT_F (*) |
| 1608 | * |
1608 | * @arg @ref LL_RI_PORT_G (*) |
| 1609 | * (*) value not defined in all devices. |
1609 | * |
| 1610 | * @param Pin This parameter can be a combination of the following values: |
1610 | * (*) value not defined in all devices. |
| 1611 | * @arg @ref LL_RI_PIN_0 |
1611 | * @param Pin This parameter can be a combination of the following values: |
| 1612 | * @arg @ref LL_RI_PIN_1 |
1612 | * @arg @ref LL_RI_PIN_0 |
| 1613 | * @arg @ref LL_RI_PIN_2 |
1613 | * @arg @ref LL_RI_PIN_1 |
| 1614 | * @arg @ref LL_RI_PIN_3 |
1614 | * @arg @ref LL_RI_PIN_2 |
| 1615 | * @arg @ref LL_RI_PIN_4 |
1615 | * @arg @ref LL_RI_PIN_3 |
| 1616 | * @arg @ref LL_RI_PIN_5 |
1616 | * @arg @ref LL_RI_PIN_4 |
| 1617 | * @arg @ref LL_RI_PIN_6 |
1617 | * @arg @ref LL_RI_PIN_5 |
| 1618 | * @arg @ref LL_RI_PIN_7 |
1618 | * @arg @ref LL_RI_PIN_6 |
| 1619 | * @arg @ref LL_RI_PIN_8 |
1619 | * @arg @ref LL_RI_PIN_7 |
| 1620 | * @arg @ref LL_RI_PIN_9 |
1620 | * @arg @ref LL_RI_PIN_8 |
| 1621 | * @arg @ref LL_RI_PIN_10 |
1621 | * @arg @ref LL_RI_PIN_9 |
| 1622 | * @arg @ref LL_RI_PIN_11 |
1622 | * @arg @ref LL_RI_PIN_10 |
| 1623 | * @arg @ref LL_RI_PIN_12 |
1623 | * @arg @ref LL_RI_PIN_11 |
| 1624 | * @arg @ref LL_RI_PIN_13 |
1624 | * @arg @ref LL_RI_PIN_12 |
| 1625 | * @arg @ref LL_RI_PIN_14 |
1625 | * @arg @ref LL_RI_PIN_13 |
| 1626 | * @arg @ref LL_RI_PIN_15 |
1626 | * @arg @ref LL_RI_PIN_14 |
| 1627 | * @arg @ref LL_RI_PIN_ALL |
1627 | * @arg @ref LL_RI_PIN_15 |
| 1628 | * @retval None |
1628 | * @arg @ref LL_RI_PIN_ALL |
| 1629 | */ |
1629 | * @retval None |
| 1630 | __STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) |
1630 | */ |
| 1631 | { |
1631 | __STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) |
| 1632 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); |
1632 | { |
| 1633 | CLEAR_BIT(*reg, Pin); |
1633 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); |
| 1634 | } |
1634 | CLEAR_BIT(*reg, Pin); |
| 1635 | #endif /* RI_CMR1_PA */ |
1635 | } |
| 1636 | 1636 | #endif /* RI_CMR1_PA */ |
|
| 1637 | #if defined(RI_CMR1_PA) |
1637 | |
| 1638 | /** |
1638 | #if defined(RI_CMR1_PA) |
| 1639 | * @brief Unmask the input of port X during the capacitive sensing acquisition. |
1639 | /** |
| 1640 | * @rmtoll RI_CMR1 PA LL_RI_UnmaskChannelDuringAcquisition\n |
1640 | * @brief Unmask the input of port X during the capacitive sensing acquisition. |
| 1641 | * RI_CMR1 PB LL_RI_UnmaskChannelDuringAcquisition\n |
1641 | * @rmtoll RI_CMR1 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| 1642 | * RI_CMR1 PC LL_RI_UnmaskChannelDuringAcquisition\n |
1642 | * RI_CMR1 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| 1643 | * RI_CMR1 PF LL_RI_UnmaskChannelDuringAcquisition\n |
1643 | * RI_CMR1 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| 1644 | * RI_CMR1 PG LL_RI_UnmaskChannelDuringAcquisition\n |
1644 | * RI_CMR1 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| 1645 | * RI_CMR2 PA LL_RI_UnmaskChannelDuringAcquisition\n |
1645 | * RI_CMR1 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| 1646 | * RI_CMR2 PB LL_RI_UnmaskChannelDuringAcquisition\n |
1646 | * RI_CMR2 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| 1647 | * RI_CMR2 PC LL_RI_UnmaskChannelDuringAcquisition\n |
1647 | * RI_CMR2 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| 1648 | * RI_CMR2 PF LL_RI_UnmaskChannelDuringAcquisition\n |
1648 | * RI_CMR2 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| 1649 | * RI_CMR2 PG LL_RI_UnmaskChannelDuringAcquisition\n |
1649 | * RI_CMR2 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| 1650 | * RI_CMR3 PA LL_RI_UnmaskChannelDuringAcquisition\n |
1650 | * RI_CMR2 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| 1651 | * RI_CMR3 PB LL_RI_UnmaskChannelDuringAcquisition\n |
1651 | * RI_CMR3 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| 1652 | * RI_CMR3 PC LL_RI_UnmaskChannelDuringAcquisition\n |
1652 | * RI_CMR3 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| 1653 | * RI_CMR3 PF LL_RI_UnmaskChannelDuringAcquisition\n |
1653 | * RI_CMR3 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| 1654 | * RI_CMR3 PG LL_RI_UnmaskChannelDuringAcquisition\n |
1654 | * RI_CMR3 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| 1655 | * RI_CMR4 PA LL_RI_UnmaskChannelDuringAcquisition\n |
1655 | * RI_CMR3 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| 1656 | * RI_CMR4 PB LL_RI_UnmaskChannelDuringAcquisition\n |
1656 | * RI_CMR4 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| 1657 | * RI_CMR4 PC LL_RI_UnmaskChannelDuringAcquisition\n |
1657 | * RI_CMR4 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| 1658 | * RI_CMR4 PF LL_RI_UnmaskChannelDuringAcquisition\n |
1658 | * RI_CMR4 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| 1659 | * RI_CMR4 PG LL_RI_UnmaskChannelDuringAcquisition\n |
1659 | * RI_CMR4 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| 1660 | * RI_CMR5 PA LL_RI_UnmaskChannelDuringAcquisition\n |
1660 | * RI_CMR4 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| 1661 | * RI_CMR5 PB LL_RI_UnmaskChannelDuringAcquisition\n |
1661 | * RI_CMR5 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| 1662 | * RI_CMR5 PC LL_RI_UnmaskChannelDuringAcquisition\n |
1662 | * RI_CMR5 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| 1663 | * RI_CMR5 PF LL_RI_UnmaskChannelDuringAcquisition\n |
1663 | * RI_CMR5 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| 1664 | * RI_CMR5 PG LL_RI_UnmaskChannelDuringAcquisition |
1664 | * RI_CMR5 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| 1665 | * @param Port This parameter can be one of the following values: |
1665 | * RI_CMR5 PG LL_RI_UnmaskChannelDuringAcquisition |
| 1666 | * @arg @ref LL_RI_PORT_A |
1666 | * @param Port This parameter can be one of the following values: |
| 1667 | * @arg @ref LL_RI_PORT_B |
1667 | * @arg @ref LL_RI_PORT_A |
| 1668 | * @arg @ref LL_RI_PORT_C |
1668 | * @arg @ref LL_RI_PORT_B |
| 1669 | * @arg @ref LL_RI_PORT_F (*) |
1669 | * @arg @ref LL_RI_PORT_C |
| 1670 | * @arg @ref LL_RI_PORT_G (*) |
1670 | * @arg @ref LL_RI_PORT_F (*) |
| 1671 | * |
1671 | * @arg @ref LL_RI_PORT_G (*) |
| 1672 | * (*) value not defined in all devices. |
1672 | * |
| 1673 | * @param Pin This parameter can be a combination of the following values: |
1673 | * (*) value not defined in all devices. |
| 1674 | * @arg @ref LL_RI_PIN_0 |
1674 | * @param Pin This parameter can be a combination of the following values: |
| 1675 | * @arg @ref LL_RI_PIN_1 |
1675 | * @arg @ref LL_RI_PIN_0 |
| 1676 | * @arg @ref LL_RI_PIN_2 |
1676 | * @arg @ref LL_RI_PIN_1 |
| 1677 | * @arg @ref LL_RI_PIN_3 |
1677 | * @arg @ref LL_RI_PIN_2 |
| 1678 | * @arg @ref LL_RI_PIN_4 |
1678 | * @arg @ref LL_RI_PIN_3 |
| 1679 | * @arg @ref LL_RI_PIN_5 |
1679 | * @arg @ref LL_RI_PIN_4 |
| 1680 | * @arg @ref LL_RI_PIN_6 |
1680 | * @arg @ref LL_RI_PIN_5 |
| 1681 | * @arg @ref LL_RI_PIN_7 |
1681 | * @arg @ref LL_RI_PIN_6 |
| 1682 | * @arg @ref LL_RI_PIN_8 |
1682 | * @arg @ref LL_RI_PIN_7 |
| 1683 | * @arg @ref LL_RI_PIN_9 |
1683 | * @arg @ref LL_RI_PIN_8 |
| 1684 | * @arg @ref LL_RI_PIN_10 |
1684 | * @arg @ref LL_RI_PIN_9 |
| 1685 | * @arg @ref LL_RI_PIN_11 |
1685 | * @arg @ref LL_RI_PIN_10 |
| 1686 | * @arg @ref LL_RI_PIN_12 |
1686 | * @arg @ref LL_RI_PIN_11 |
| 1687 | * @arg @ref LL_RI_PIN_13 |
1687 | * @arg @ref LL_RI_PIN_12 |
| 1688 | * @arg @ref LL_RI_PIN_14 |
1688 | * @arg @ref LL_RI_PIN_13 |
| 1689 | * @arg @ref LL_RI_PIN_15 |
1689 | * @arg @ref LL_RI_PIN_14 |
| 1690 | * @arg @ref LL_RI_PIN_ALL |
1690 | * @arg @ref LL_RI_PIN_15 |
| 1691 | * @retval None |
1691 | * @arg @ref LL_RI_PIN_ALL |
| 1692 | */ |
1692 | * @retval None |
| 1693 | __STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) |
1693 | */ |
| 1694 | { |
1694 | __STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) |
| 1695 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); |
1695 | { |
| 1696 | SET_BIT(*reg, Pin); |
1696 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); |
| 1697 | } |
1697 | SET_BIT(*reg, Pin); |
| 1698 | #endif /* RI_CMR1_PA */ |
1698 | } |
| 1699 | 1699 | #endif /* RI_CMR1_PA */ |
|
| 1700 | #if defined(RI_CICR1_PA) |
1700 | |
| 1701 | /** |
1701 | #if defined(RI_CICR1_PA) |
| 1702 | * @brief Identify channel for timer input capture |
1702 | /** |
| 1703 | * @rmtoll RI_CICR1 PA LL_RI_IdentifyChannelIO\n |
1703 | * @brief Identify channel for timer input capture |
| 1704 | * RI_CICR1 PB LL_RI_IdentifyChannelIO\n |
1704 | * @rmtoll RI_CICR1 PA LL_RI_IdentifyChannelIO\n |
| 1705 | * RI_CICR1 PC LL_RI_IdentifyChannelIO\n |
1705 | * RI_CICR1 PB LL_RI_IdentifyChannelIO\n |
| 1706 | * RI_CICR1 PF LL_RI_IdentifyChannelIO\n |
1706 | * RI_CICR1 PC LL_RI_IdentifyChannelIO\n |
| 1707 | * RI_CICR1 PG LL_RI_IdentifyChannelIO\n |
1707 | * RI_CICR1 PF LL_RI_IdentifyChannelIO\n |
| 1708 | * RI_CICR2 PA LL_RI_IdentifyChannelIO\n |
1708 | * RI_CICR1 PG LL_RI_IdentifyChannelIO\n |
| 1709 | * RI_CICR2 PB LL_RI_IdentifyChannelIO\n |
1709 | * RI_CICR2 PA LL_RI_IdentifyChannelIO\n |
| 1710 | * RI_CICR2 PC LL_RI_IdentifyChannelIO\n |
1710 | * RI_CICR2 PB LL_RI_IdentifyChannelIO\n |
| 1711 | * RI_CICR2 PF LL_RI_IdentifyChannelIO\n |
1711 | * RI_CICR2 PC LL_RI_IdentifyChannelIO\n |
| 1712 | * RI_CICR2 PG LL_RI_IdentifyChannelIO\n |
1712 | * RI_CICR2 PF LL_RI_IdentifyChannelIO\n |
| 1713 | * RI_CICR3 PA LL_RI_IdentifyChannelIO\n |
1713 | * RI_CICR2 PG LL_RI_IdentifyChannelIO\n |
| 1714 | * RI_CICR3 PB LL_RI_IdentifyChannelIO\n |
1714 | * RI_CICR3 PA LL_RI_IdentifyChannelIO\n |
| 1715 | * RI_CICR3 PC LL_RI_IdentifyChannelIO\n |
1715 | * RI_CICR3 PB LL_RI_IdentifyChannelIO\n |
| 1716 | * RI_CICR3 PF LL_RI_IdentifyChannelIO\n |
1716 | * RI_CICR3 PC LL_RI_IdentifyChannelIO\n |
| 1717 | * RI_CICR3 PG LL_RI_IdentifyChannelIO\n |
1717 | * RI_CICR3 PF LL_RI_IdentifyChannelIO\n |
| 1718 | * RI_CICR4 PA LL_RI_IdentifyChannelIO\n |
1718 | * RI_CICR3 PG LL_RI_IdentifyChannelIO\n |
| 1719 | * RI_CICR4 PB LL_RI_IdentifyChannelIO\n |
1719 | * RI_CICR4 PA LL_RI_IdentifyChannelIO\n |
| 1720 | * RI_CICR4 PC LL_RI_IdentifyChannelIO\n |
1720 | * RI_CICR4 PB LL_RI_IdentifyChannelIO\n |
| 1721 | * RI_CICR4 PF LL_RI_IdentifyChannelIO\n |
1721 | * RI_CICR4 PC LL_RI_IdentifyChannelIO\n |
| 1722 | * RI_CICR4 PG LL_RI_IdentifyChannelIO\n |
1722 | * RI_CICR4 PF LL_RI_IdentifyChannelIO\n |
| 1723 | * RI_CICR5 PA LL_RI_IdentifyChannelIO\n |
1723 | * RI_CICR4 PG LL_RI_IdentifyChannelIO\n |
| 1724 | * RI_CICR5 PB LL_RI_IdentifyChannelIO\n |
1724 | * RI_CICR5 PA LL_RI_IdentifyChannelIO\n |
| 1725 | * RI_CICR5 PC LL_RI_IdentifyChannelIO\n |
1725 | * RI_CICR5 PB LL_RI_IdentifyChannelIO\n |
| 1726 | * RI_CICR5 PF LL_RI_IdentifyChannelIO\n |
1726 | * RI_CICR5 PC LL_RI_IdentifyChannelIO\n |
| 1727 | * RI_CICR5 PG LL_RI_IdentifyChannelIO |
1727 | * RI_CICR5 PF LL_RI_IdentifyChannelIO\n |
| 1728 | * @param Port This parameter can be one of the following values: |
1728 | * RI_CICR5 PG LL_RI_IdentifyChannelIO |
| 1729 | * @arg @ref LL_RI_PORT_A |
1729 | * @param Port This parameter can be one of the following values: |
| 1730 | * @arg @ref LL_RI_PORT_B |
1730 | * @arg @ref LL_RI_PORT_A |
| 1731 | * @arg @ref LL_RI_PORT_C |
1731 | * @arg @ref LL_RI_PORT_B |
| 1732 | * @arg @ref LL_RI_PORT_F (*) |
1732 | * @arg @ref LL_RI_PORT_C |
| 1733 | * @arg @ref LL_RI_PORT_G (*) |
1733 | * @arg @ref LL_RI_PORT_F (*) |
| 1734 | * |
1734 | * @arg @ref LL_RI_PORT_G (*) |
| 1735 | * (*) value not defined in all devices. |
1735 | * |
| 1736 | * @param Pin This parameter can be a combination of the following values: |
1736 | * (*) value not defined in all devices. |
| 1737 | * @arg @ref LL_RI_PIN_0 |
1737 | * @param Pin This parameter can be a combination of the following values: |
| 1738 | * @arg @ref LL_RI_PIN_1 |
1738 | * @arg @ref LL_RI_PIN_0 |
| 1739 | * @arg @ref LL_RI_PIN_2 |
1739 | * @arg @ref LL_RI_PIN_1 |
| 1740 | * @arg @ref LL_RI_PIN_3 |
1740 | * @arg @ref LL_RI_PIN_2 |
| 1741 | * @arg @ref LL_RI_PIN_4 |
1741 | * @arg @ref LL_RI_PIN_3 |
| 1742 | * @arg @ref LL_RI_PIN_5 |
1742 | * @arg @ref LL_RI_PIN_4 |
| 1743 | * @arg @ref LL_RI_PIN_6 |
1743 | * @arg @ref LL_RI_PIN_5 |
| 1744 | * @arg @ref LL_RI_PIN_7 |
1744 | * @arg @ref LL_RI_PIN_6 |
| 1745 | * @arg @ref LL_RI_PIN_8 |
1745 | * @arg @ref LL_RI_PIN_7 |
| 1746 | * @arg @ref LL_RI_PIN_9 |
1746 | * @arg @ref LL_RI_PIN_8 |
| 1747 | * @arg @ref LL_RI_PIN_10 |
1747 | * @arg @ref LL_RI_PIN_9 |
| 1748 | * @arg @ref LL_RI_PIN_11 |
1748 | * @arg @ref LL_RI_PIN_10 |
| 1749 | * @arg @ref LL_RI_PIN_12 |
1749 | * @arg @ref LL_RI_PIN_11 |
| 1750 | * @arg @ref LL_RI_PIN_13 |
1750 | * @arg @ref LL_RI_PIN_12 |
| 1751 | * @arg @ref LL_RI_PIN_14 |
1751 | * @arg @ref LL_RI_PIN_13 |
| 1752 | * @arg @ref LL_RI_PIN_15 |
1752 | * @arg @ref LL_RI_PIN_14 |
| 1753 | * @arg @ref LL_RI_PIN_ALL |
1753 | * @arg @ref LL_RI_PIN_15 |
| 1754 | * @retval None |
1754 | * @arg @ref LL_RI_PIN_ALL |
| 1755 | */ |
1755 | * @retval None |
| 1756 | __STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin) |
1756 | */ |
| 1757 | { |
1757 | __STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin) |
| 1758 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); |
1758 | { |
| 1759 | CLEAR_BIT(*reg, Pin); |
1759 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); |
| 1760 | } |
1760 | CLEAR_BIT(*reg, Pin); |
| 1761 | #endif /* RI_CICR1_PA */ |
1761 | } |
| 1762 | 1762 | #endif /* RI_CICR1_PA */ |
|
| 1763 | #if defined(RI_CICR1_PA) |
1763 | |
| 1764 | /** |
1764 | #if defined(RI_CICR1_PA) |
| 1765 | * @brief Identify sampling capacitor for timer input capture |
1765 | /** |
| 1766 | * @rmtoll RI_CICR1 PA LL_RI_IdentifySamplingCapacitorIO\n |
1766 | * @brief Identify sampling capacitor for timer input capture |
| 1767 | * RI_CICR1 PB LL_RI_IdentifySamplingCapacitorIO\n |
1767 | * @rmtoll RI_CICR1 PA LL_RI_IdentifySamplingCapacitorIO\n |
| 1768 | * RI_CICR1 PC LL_RI_IdentifySamplingCapacitorIO\n |
1768 | * RI_CICR1 PB LL_RI_IdentifySamplingCapacitorIO\n |
| 1769 | * RI_CICR1 PF LL_RI_IdentifySamplingCapacitorIO\n |
1769 | * RI_CICR1 PC LL_RI_IdentifySamplingCapacitorIO\n |
| 1770 | * RI_CICR1 PG LL_RI_IdentifySamplingCapacitorIO\n |
1770 | * RI_CICR1 PF LL_RI_IdentifySamplingCapacitorIO\n |
| 1771 | * RI_CICR2 PA LL_RI_IdentifySamplingCapacitorIO\n |
1771 | * RI_CICR1 PG LL_RI_IdentifySamplingCapacitorIO\n |
| 1772 | * RI_CICR2 PB LL_RI_IdentifySamplingCapacitorIO\n |
1772 | * RI_CICR2 PA LL_RI_IdentifySamplingCapacitorIO\n |
| 1773 | * RI_CICR2 PC LL_RI_IdentifySamplingCapacitorIO\n |
1773 | * RI_CICR2 PB LL_RI_IdentifySamplingCapacitorIO\n |
| 1774 | * RI_CICR2 PF LL_RI_IdentifySamplingCapacitorIO\n |
1774 | * RI_CICR2 PC LL_RI_IdentifySamplingCapacitorIO\n |
| 1775 | * RI_CICR2 PG LL_RI_IdentifySamplingCapacitorIO\n |
1775 | * RI_CICR2 PF LL_RI_IdentifySamplingCapacitorIO\n |
| 1776 | * RI_CICR3 PA LL_RI_IdentifySamplingCapacitorIO\n |
1776 | * RI_CICR2 PG LL_RI_IdentifySamplingCapacitorIO\n |
| 1777 | * RI_CICR3 PB LL_RI_IdentifySamplingCapacitorIO\n |
1777 | * RI_CICR3 PA LL_RI_IdentifySamplingCapacitorIO\n |
| 1778 | * RI_CICR3 PC LL_RI_IdentifySamplingCapacitorIO\n |
1778 | * RI_CICR3 PB LL_RI_IdentifySamplingCapacitorIO\n |
| 1779 | * RI_CICR3 PF LL_RI_IdentifySamplingCapacitorIO\n |
1779 | * RI_CICR3 PC LL_RI_IdentifySamplingCapacitorIO\n |
| 1780 | * RI_CICR3 PG LL_RI_IdentifySamplingCapacitorIO\n |
1780 | * RI_CICR3 PF LL_RI_IdentifySamplingCapacitorIO\n |
| 1781 | * RI_CICR4 PA LL_RI_IdentifySamplingCapacitorIO\n |
1781 | * RI_CICR3 PG LL_RI_IdentifySamplingCapacitorIO\n |
| 1782 | * RI_CICR4 PB LL_RI_IdentifySamplingCapacitorIO\n |
1782 | * RI_CICR4 PA LL_RI_IdentifySamplingCapacitorIO\n |
| 1783 | * RI_CICR4 PC LL_RI_IdentifySamplingCapacitorIO\n |
1783 | * RI_CICR4 PB LL_RI_IdentifySamplingCapacitorIO\n |
| 1784 | * RI_CICR4 PF LL_RI_IdentifySamplingCapacitorIO\n |
1784 | * RI_CICR4 PC LL_RI_IdentifySamplingCapacitorIO\n |
| 1785 | * RI_CICR4 PG LL_RI_IdentifySamplingCapacitorIO\n |
1785 | * RI_CICR4 PF LL_RI_IdentifySamplingCapacitorIO\n |
| 1786 | * RI_CICR5 PA LL_RI_IdentifySamplingCapacitorIO\n |
1786 | * RI_CICR4 PG LL_RI_IdentifySamplingCapacitorIO\n |
| 1787 | * RI_CICR5 PB LL_RI_IdentifySamplingCapacitorIO\n |
1787 | * RI_CICR5 PA LL_RI_IdentifySamplingCapacitorIO\n |
| 1788 | * RI_CICR5 PC LL_RI_IdentifySamplingCapacitorIO\n |
1788 | * RI_CICR5 PB LL_RI_IdentifySamplingCapacitorIO\n |
| 1789 | * RI_CICR5 PF LL_RI_IdentifySamplingCapacitorIO\n |
1789 | * RI_CICR5 PC LL_RI_IdentifySamplingCapacitorIO\n |
| 1790 | * RI_CICR5 PG LL_RI_IdentifySamplingCapacitorIO |
1790 | * RI_CICR5 PF LL_RI_IdentifySamplingCapacitorIO\n |
| 1791 | * @param Port This parameter can be one of the following values: |
1791 | * RI_CICR5 PG LL_RI_IdentifySamplingCapacitorIO |
| 1792 | * @arg @ref LL_RI_PORT_A |
1792 | * @param Port This parameter can be one of the following values: |
| 1793 | * @arg @ref LL_RI_PORT_B |
1793 | * @arg @ref LL_RI_PORT_A |
| 1794 | * @arg @ref LL_RI_PORT_C |
1794 | * @arg @ref LL_RI_PORT_B |
| 1795 | * @arg @ref LL_RI_PORT_F (*) |
1795 | * @arg @ref LL_RI_PORT_C |
| 1796 | * @arg @ref LL_RI_PORT_G (*) |
1796 | * @arg @ref LL_RI_PORT_F (*) |
| 1797 | * |
1797 | * @arg @ref LL_RI_PORT_G (*) |
| 1798 | * (*) value not defined in all devices. |
1798 | * |
| 1799 | * @param Pin This parameter can be a combination of the following values: |
1799 | * (*) value not defined in all devices. |
| 1800 | * @arg @ref LL_RI_PIN_0 |
1800 | * @param Pin This parameter can be a combination of the following values: |
| 1801 | * @arg @ref LL_RI_PIN_1 |
1801 | * @arg @ref LL_RI_PIN_0 |
| 1802 | * @arg @ref LL_RI_PIN_2 |
1802 | * @arg @ref LL_RI_PIN_1 |
| 1803 | * @arg @ref LL_RI_PIN_3 |
1803 | * @arg @ref LL_RI_PIN_2 |
| 1804 | * @arg @ref LL_RI_PIN_4 |
1804 | * @arg @ref LL_RI_PIN_3 |
| 1805 | * @arg @ref LL_RI_PIN_5 |
1805 | * @arg @ref LL_RI_PIN_4 |
| 1806 | * @arg @ref LL_RI_PIN_6 |
1806 | * @arg @ref LL_RI_PIN_5 |
| 1807 | * @arg @ref LL_RI_PIN_7 |
1807 | * @arg @ref LL_RI_PIN_6 |
| 1808 | * @arg @ref LL_RI_PIN_8 |
1808 | * @arg @ref LL_RI_PIN_7 |
| 1809 | * @arg @ref LL_RI_PIN_9 |
1809 | * @arg @ref LL_RI_PIN_8 |
| 1810 | * @arg @ref LL_RI_PIN_10 |
1810 | * @arg @ref LL_RI_PIN_9 |
| 1811 | * @arg @ref LL_RI_PIN_11 |
1811 | * @arg @ref LL_RI_PIN_10 |
| 1812 | * @arg @ref LL_RI_PIN_12 |
1812 | * @arg @ref LL_RI_PIN_11 |
| 1813 | * @arg @ref LL_RI_PIN_13 |
1813 | * @arg @ref LL_RI_PIN_12 |
| 1814 | * @arg @ref LL_RI_PIN_14 |
1814 | * @arg @ref LL_RI_PIN_13 |
| 1815 | * @arg @ref LL_RI_PIN_15 |
1815 | * @arg @ref LL_RI_PIN_14 |
| 1816 | * @arg @ref LL_RI_PIN_ALL |
1816 | * @arg @ref LL_RI_PIN_15 |
| 1817 | * @retval None |
1817 | * @arg @ref LL_RI_PIN_ALL |
| 1818 | */ |
1818 | * @retval None |
| 1819 | __STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin) |
1819 | */ |
| 1820 | { |
1820 | __STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin) |
| 1821 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); |
1821 | { |
| 1822 | SET_BIT(*reg, Pin); |
1822 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); |
| 1823 | } |
1823 | SET_BIT(*reg, Pin); |
| 1824 | #endif /* RI_CICR1_PA */ |
1824 | } |
| 1825 | 1825 | #endif /* RI_CICR1_PA */ |
|
| 1826 | /** |
1826 | |
| 1827 | * @} |
1827 | /** |
| 1828 | */ |
1828 | * @} |
| 1829 | 1829 | */ |
|
| 1830 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
1830 | |
| 1831 | * @{ |
1831 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
| 1832 | */ |
1832 | * @{ |
| 1833 | 1833 | */ |
|
| 1834 | /** |
1834 | |
| 1835 | * @brief Set FLASH Latency |
1835 | /** |
| 1836 | * @note Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
1836 | * @brief Set FLASH Latency |
| 1837 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
1837 | * @note Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
| 1838 | * @param Latency This parameter can be one of the following values: |
1838 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
| 1839 | * @arg @ref LL_FLASH_LATENCY_0 |
1839 | * @param Latency This parameter can be one of the following values: |
| 1840 | * @arg @ref LL_FLASH_LATENCY_1 |
1840 | * @arg @ref LL_FLASH_LATENCY_0 |
| 1841 | * @retval None |
1841 | * @arg @ref LL_FLASH_LATENCY_1 |
| 1842 | */ |
1842 | * @retval None |
| 1843 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
1843 | */ |
| 1844 | { |
1844 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
| 1845 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
1845 | { |
| 1846 | } |
1846 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
| 1847 | 1847 | } |
|
| 1848 | /** |
1848 | |
| 1849 | * @brief Get FLASH Latency |
1849 | /** |
| 1850 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
1850 | * @brief Get FLASH Latency |
| 1851 | * @retval Returned value can be one of the following values: |
1851 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
| 1852 | * @arg @ref LL_FLASH_LATENCY_0 |
1852 | * @retval Returned value can be one of the following values: |
| 1853 | * @arg @ref LL_FLASH_LATENCY_1 |
1853 | * @arg @ref LL_FLASH_LATENCY_0 |
| 1854 | */ |
1854 | * @arg @ref LL_FLASH_LATENCY_1 |
| 1855 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
1855 | */ |
| 1856 | { |
1856 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
| 1857 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
1857 | { |
| 1858 | } |
1858 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
| 1859 | 1859 | } |
|
| 1860 | /** |
1860 | |
| 1861 | * @brief Enable Prefetch |
1861 | /** |
| 1862 | * @note Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
1862 | * @brief Enable Prefetch |
| 1863 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch |
1863 | * @note Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
| 1864 | * @retval None |
1864 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch |
| 1865 | */ |
1865 | * @retval None |
| 1866 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
1866 | */ |
| 1867 | { |
1867 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
| 1868 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
1868 | { |
| 1869 | } |
1869 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
| 1870 | 1870 | } |
|
| 1871 | /** |
1871 | |
| 1872 | * @brief Disable Prefetch |
1872 | /** |
| 1873 | * @note Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
1873 | * @brief Disable Prefetch |
| 1874 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch |
1874 | * @note Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
| 1875 | * @retval None |
1875 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch |
| 1876 | */ |
1876 | * @retval None |
| 1877 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
1877 | */ |
| 1878 | { |
1878 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
| 1879 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
1879 | { |
| 1880 | } |
1880 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
| 1881 | 1881 | } |
|
| 1882 | /** |
1882 | |
| 1883 | * @brief Check if Prefetch buffer is enabled |
1883 | /** |
| 1884 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled |
1884 | * @brief Check if Prefetch buffer is enabled |
| 1885 | * @retval State of bit (1 or 0). |
1885 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled |
| 1886 | */ |
1886 | * @retval State of bit (1 or 0). |
| 1887 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
1887 | */ |
| 1888 | { |
1888 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
| 1889 | return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == FLASH_ACR_PRFTEN) ? 1UL : 0UL); |
1889 | { |
| 1890 | } |
1890 | return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == FLASH_ACR_PRFTEN) ? 1UL : 0UL); |
| 1891 | 1891 | } |
|
| 1892 | /** |
1892 | |
| 1893 | * @brief Enable 64-bit access |
1893 | /** |
| 1894 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Enable64bitAccess |
1894 | * @brief Enable 64-bit access |
| 1895 | * @retval None |
1895 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Enable64bitAccess |
| 1896 | */ |
1896 | * @retval None |
| 1897 | __STATIC_INLINE void LL_FLASH_Enable64bitAccess(void) |
1897 | */ |
| 1898 | { |
1898 | __STATIC_INLINE void LL_FLASH_Enable64bitAccess(void) |
| 1899 | SET_BIT(FLASH->ACR, FLASH_ACR_ACC64); |
1899 | { |
| 1900 | } |
1900 | SET_BIT(FLASH->ACR, FLASH_ACR_ACC64); |
| 1901 | 1901 | } |
|
| 1902 | /** |
1902 | |
| 1903 | * @brief Disable 64-bit access |
1903 | /** |
| 1904 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Disable64bitAccess |
1904 | * @brief Disable 64-bit access |
| 1905 | * @retval None |
1905 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Disable64bitAccess |
| 1906 | */ |
1906 | * @retval None |
| 1907 | __STATIC_INLINE void LL_FLASH_Disable64bitAccess(void) |
1907 | */ |
| 1908 | { |
1908 | __STATIC_INLINE void LL_FLASH_Disable64bitAccess(void) |
| 1909 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64); |
1909 | { |
| 1910 | } |
1910 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64); |
| 1911 | 1911 | } |
|
| 1912 | /** |
1912 | |
| 1913 | * @brief Check if 64-bit access is enabled |
1913 | /** |
| 1914 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Is64bitAccessEnabled |
1914 | * @brief Check if 64-bit access is enabled |
| 1915 | * @retval State of bit (1 or 0). |
1915 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Is64bitAccessEnabled |
| 1916 | */ |
1916 | * @retval State of bit (1 or 0). |
| 1917 | __STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void) |
1917 | */ |
| 1918 | { |
1918 | __STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void) |
| 1919 | return ((READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == FLASH_ACR_ACC64) ? 1UL : 0UL); |
1919 | { |
| 1920 | } |
1920 | return ((READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == FLASH_ACR_ACC64) ? 1UL : 0UL); |
| 1921 | 1921 | } |
|
| 1922 | 1922 | ||
| 1923 | /** |
1923 | |
| 1924 | * @brief Enable Flash Power-down mode during run mode or Low-power run mode |
1924 | /** |
| 1925 | * @note Flash memory can be put in power-down mode only when the code is executed |
1925 | * @brief Enable Flash Power-down mode during run mode or Low-power run mode |
| 1926 | * from RAM |
1926 | * @note Flash memory can be put in power-down mode only when the code is executed |
| 1927 | * @note Flash must not be accessed when power down is enabled |
1927 | * from RAM |
| 1928 | * @note Flash must not be put in power-down while a program or an erase operation |
1928 | * @note Flash must not be accessed when power down is enabled |
| 1929 | * is on-going |
1929 | * @note Flash must not be put in power-down while a program or an erase operation |
| 1930 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n |
1930 | * is on-going |
| 1931 | * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n |
1931 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n |
| 1932 | * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown |
1932 | * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n |
| 1933 | * @retval None |
1933 | * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown |
| 1934 | */ |
1934 | * @retval None |
| 1935 | __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) |
1935 | */ |
| 1936 | { |
1936 | __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) |
| 1937 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
1937 | { |
| 1938 | FLASH_ACR */ |
1938 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
| 1939 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
1939 | FLASH_ACR */ |
| 1940 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
1940 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
| 1941 | SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
1941 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
| 1942 | } |
1942 | SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
| 1943 | 1943 | } |
|
| 1944 | /** |
1944 | |
| 1945 | * @brief Disable Flash Power-down mode during run mode or Low-power run mode |
1945 | /** |
| 1946 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n |
1946 | * @brief Disable Flash Power-down mode during run mode or Low-power run mode |
| 1947 | * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n |
1947 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n |
| 1948 | * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown |
1948 | * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n |
| 1949 | * @retval None |
1949 | * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown |
| 1950 | */ |
1950 | * @retval None |
| 1951 | __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) |
1951 | */ |
| 1952 | { |
1952 | __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) |
| 1953 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
1953 | { |
| 1954 | FLASH_ACR */ |
1954 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
| 1955 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
1955 | FLASH_ACR */ |
| 1956 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
1956 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
| 1957 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
1957 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
| 1958 | } |
1958 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
| 1959 | 1959 | } |
|
| 1960 | /** |
1960 | |
| 1961 | * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode |
1961 | /** |
| 1962 | * @note Flash must not be put in power-down while a program or an erase operation |
1962 | * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode |
| 1963 | * is on-going |
1963 | * @note Flash must not be put in power-down while a program or an erase operation |
| 1964 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown |
1964 | * is on-going |
| 1965 | * @retval None |
1965 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown |
| 1966 | */ |
1966 | * @retval None |
| 1967 | __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) |
1967 | */ |
| 1968 | { |
1968 | __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) |
| 1969 | SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
1969 | { |
| 1970 | } |
1970 | SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
| 1971 | 1971 | } |
|
| 1972 | /** |
1972 | |
| 1973 | * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode |
1973 | /** |
| 1974 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown |
1974 | * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode |
| 1975 | * @retval None |
1975 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown |
| 1976 | */ |
1976 | * @retval None |
| 1977 | __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) |
1977 | */ |
| 1978 | { |
1978 | __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) |
| 1979 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
1979 | { |
| 1980 | } |
1980 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
| 1981 | 1981 | } |
|
| 1982 | /** |
1982 | |
| 1983 | * @} |
1983 | /** |
| 1984 | */ |
1984 | * @} |
| 1985 | 1985 | */ |
|
| 1986 | /** |
1986 | |
| 1987 | * @} |
1987 | /** |
| 1988 | */ |
1988 | * @} |
| 1989 | 1989 | */ |
|
| 1990 | /** |
1990 | |
| 1991 | * @} |
1991 | /** |
| 1992 | */ |
1992 | * @} |
| 1993 | 1993 | */ |
|
| 1994 | #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) */ |
1994 | |
| 1995 | 1995 | #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) */ |
|
| 1996 | /** |
1996 | |
| 1997 | * @} |
1997 | /** |
| 1998 | */ |
1998 | * @} |
| 1999 | 1999 | */ |
|
| 2000 | #ifdef __cplusplus |
2000 | |
| 2001 | } |
2001 | #ifdef __cplusplus |
| 2002 | #endif |
2002 | } |
| 2003 | 2003 | #endif |
|
| 2004 | #endif /* __STM32L1xx_LL_SYSTEM_H */ |
2004 | |
| 2005 | 2005 | #endif /* __STM32L1xx_LL_SYSTEM_H */ |
|
| 2006 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
2006 | |
| - | 2007 | ||