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| 128 | /* Exported constants --------------------------------------------------------*/ |
128 | /* Exported constants --------------------------------------------------------*/ |
| 129 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
129 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
| 130 | * @{ |
130 | * @{ |
| 131 | */ |
131 | */ |
| 132 | #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
132 | #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ |
| 133 | #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ |
133 | #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ |
| 134 | #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ |
134 | #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ |
| 135 | #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ |
135 | #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ |
| 136 | #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ |
136 | #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ |
| 137 | #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ |
137 | #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ |
| 138 | #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ |
138 | #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ |
| 139 | #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ |
139 | #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ |
| 140 | #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the |
140 | #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the |
| 141 | number of transferred bytes does not match the block length */ |
141 | number of transferred bytes does not match the block length */ |
| 142 | #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ |
142 | #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ |
| 143 | #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ |
143 | #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ |
| 144 | #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ |
144 | #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ |
| 145 | #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock |
145 | #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock |
| 146 | command or if there was an attempt to access a locked card */ |
146 | command or if there was an attempt to access a locked card */ |
| 147 | #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ |
147 | #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ |
| 148 | #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ |
148 | #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ |
| 149 | #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ |
149 | #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ |
| 150 | #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ |
150 | #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ |
| 151 | #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ |
151 | #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ |
| 152 | #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ |
152 | #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ |
| 153 | #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ |
153 | #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ |
| 154 | #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ |
154 | #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ |
| 155 | #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ |
155 | #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ |
| 156 | #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ |
156 | #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ |
| 157 | #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out |
157 | #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out |
| 158 | of erase sequence command was received */ |
158 | of erase sequence command was received */ |
| 159 | #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ |
159 | #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ |
| 160 | #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ |
160 | #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ |
| 161 | #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ |
161 | #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ |
| 162 | #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ |
162 | #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ |
| 163 | #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ |
163 | #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ |
| 164 | #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ |
164 | #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ |
| 165 | #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ |
165 | #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ |
| 166 | #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ |
166 | #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ |
| 167 | #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ |
167 | #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ |
| 168 | 168 | ||
| 169 | /** |
169 | /** |
| 170 | * @brief SDMMC Commands Index |
170 | * @brief SDMMC Commands Index |
| 171 | */ |
171 | */ |
| 172 | #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ |
172 | #define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ |
| 173 | #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ |
173 | #define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ |
| 174 | #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ |
174 | #define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ |
| 175 | #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ |
175 | #define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ |
| 176 | #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ |
176 | #define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ |
| 177 | #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its |
177 | #define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its |
| 178 | operating condition register (OCR) content in the response on the CMD line. */ |
178 | operating condition register (OCR) content in the response on the CMD line. */ |
| 179 | #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ |
179 | #define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ |
| 180 | #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ |
180 | #define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ |
| 181 | #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information |
181 | #define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information |
| 182 | and asks the card whether card supports voltage. */ |
182 | and asks the card whether card supports voltage. */ |
| 183 | #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ |
183 | #define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ |
| 184 | #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ |
184 | #define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ |
| 185 | #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ |
185 | #define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ |
| 186 | #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ |
186 | #define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ |
| 187 | #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ |
187 | #define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ |
| 188 | #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ |
188 | #define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ |
| 189 | #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ |
189 | #define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ |
| 190 | #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands |
190 | #define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands |
| 191 | (read, write, lock). Default block length is fixed to 512 Bytes. Not effective |
191 | (read, write, lock). Default block length is fixed to 512 Bytes. Not effective |
| 192 | for SDHS and SDXC. */ |
192 | for SDHS and SDXC. */ |
| 193 | #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
193 | #define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
| 194 | fixed 512 bytes in case of SDHC and SDXC. */ |
194 | fixed 512 bytes in case of SDHC and SDXC. */ |
| 195 | #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by |
195 | #define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by |
| 196 | STOP_TRANSMISSION command. */ |
196 | STOP_TRANSMISSION command. */ |
| 197 | #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ |
197 | #define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ |
| 198 | #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ |
198 | #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ |
| 199 | #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ |
199 | #define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ |
| 200 | #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
200 | #define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
| 201 | fixed 512 bytes in case of SDHC and SDXC. */ |
201 | fixed 512 bytes in case of SDHC and SDXC. */ |
| 202 | #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ |
202 | #define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ |
| 203 | #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ |
203 | #define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ |
| 204 | #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ |
204 | #define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ |
| 205 | #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ |
205 | #define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ |
| 206 | #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ |
206 | #define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ |
| 207 | #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ |
207 | #define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ |
| 208 | #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ |
208 | #define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ |
| 209 | #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ |
209 | #define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ |
| 210 | #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command |
210 | #define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command |
| 211 | system set by switch function command (CMD6). */ |
211 | system set by switch function command (CMD6). */ |
| 212 | #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. |
212 | #define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. |
| 213 | Reserved for each command system set by switch function command (CMD6). */ |
213 | Reserved for each command system set by switch function command (CMD6). */ |
| 214 | #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ |
214 | #define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ |
| 215 | #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ |
215 | #define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ |
| 216 | #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ |
216 | #define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ |
| 217 | #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by |
217 | #define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by |
| 218 | the SET_BLOCK_LEN command. */ |
218 | the SET_BLOCK_LEN command. */ |
| 219 | #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather |
219 | #define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather |
| 220 | than a standard command. */ |
220 | than a standard command. */ |
| 221 | #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card |
221 | #define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card |
| 222 | for general purpose/application specific commands. */ |
222 | for general purpose/application specific commands. */ |
| 223 | #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ |
223 | #define SDMMC_CMD_NO_CMD 64U /*!< No command */ |
| 224 | 224 | ||
| 225 | /** |
225 | /** |
| 226 | * @brief Following commands are SD Card Specific commands. |
226 | * @brief Following commands are SD Card Specific commands. |
| 227 | * SDMMC_APP_CMD should be sent before sending these commands. |
227 | * SDMMC_APP_CMD should be sent before sending these commands. |
| 228 | */ |
228 | */ |
| 229 | #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus |
229 | #define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus |
| 230 | widths are given in SCR register. */ |
230 | widths are given in SCR register. */ |
| 231 | #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ |
231 | #define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ |
| 232 | #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with |
232 | #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with |
| 233 | 32bit+CRC data block. */ |
233 | 32bit+CRC data block. */ |
| 234 | #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to |
234 | #define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to |
| 235 | send its operating condition register (OCR) content in the response on the CMD line. */ |
235 | send its operating condition register (OCR) content in the response on the CMD line. */ |
| 236 | #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ |
236 | #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ |
| 237 | #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ |
237 | #define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ |
| 238 | #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ |
238 | #define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ |
| 239 | #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ |
239 | #define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ |
| 240 | 240 | ||
| 241 | /** |
241 | /** |
| 242 | * @brief Following commands are SD Card Specific security commands. |
242 | * @brief Following commands are SD Card Specific security commands. |
| 243 | * SDMMC_CMD_APP_CMD should be sent before sending these commands. |
243 | * SDMMC_CMD_APP_CMD should be sent before sending these commands. |
| 244 | */ |
244 | */ |
| 245 | #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) |
245 | #define SDMMC_CMD_SD_APP_GET_MKB 43U |
| 246 | #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) |
246 | #define SDMMC_CMD_SD_APP_GET_MID 44U |
| 247 | #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) |
247 | #define SDMMC_CMD_SD_APP_SET_CER_RN1 45U |
| 248 | #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) |
248 | #define SDMMC_CMD_SD_APP_GET_CER_RN2 46U |
| 249 | #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) |
249 | #define SDMMC_CMD_SD_APP_SET_CER_RES2 47U |
| 250 | #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) |
250 | #define SDMMC_CMD_SD_APP_GET_CER_RES1 48U |
| 251 | #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) |
251 | #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U |
| 252 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) |
252 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U |
| 253 | #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) |
253 | #define SDMMC_CMD_SD_APP_SECURE_ERASE 38U |
| 254 | #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) |
254 | #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U |
| 255 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) |
255 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U |
| 256 | 256 | ||
| 257 | /** |
257 | /** |
| 258 | * @brief Masks for errors Card Status R1 (OCR Register) |
258 | * @brief Masks for errors Card Status R1 (OCR Register) |
| 259 | */ |
259 | */ |
| 260 | #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) |
260 | #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U |
| 261 | #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) |
261 | #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U |
| 262 | #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) |
262 | #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U |
| 263 | #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) |
263 | #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U |
| 264 | #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) |
264 | #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U |
| 265 | #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) |
265 | #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U |
| 266 | #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) |
266 | #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U |
| 267 | #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) |
267 | #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U |
| 268 | #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) |
268 | #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U |
| 269 | #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) |
269 | #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U |
| 270 | #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) |
270 | #define SDMMC_OCR_CC_ERROR 0x00100000U |
| 271 | #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) |
271 | #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U |
| 272 | #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) |
272 | #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U |
| 273 | #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) |
273 | #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U |
| 274 | #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) |
274 | #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U |
| 275 | #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) |
275 | #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U |
| 276 | #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) |
276 | #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U |
| 277 | #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) |
277 | #define SDMMC_OCR_ERASE_RESET 0x00002000U |
| 278 | #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) |
278 | #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U |
| 279 | #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) |
279 | #define SDMMC_OCR_ERRORBITS 0xFDFFE008U |
| 280 | 280 | ||
| 281 | /** |
281 | /** |
| 282 | * @brief Masks for R6 Response |
282 | * @brief Masks for R6 Response |
| 283 | */ |
283 | */ |
| 284 | #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) |
284 | #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U |
| 285 | #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) |
285 | #define SDMMC_R6_ILLEGAL_CMD 0x00004000U |
| 286 | #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) |
286 | #define SDMMC_R6_COM_CRC_FAILED 0x00008000U |
| - | 287 | ||
| - | 288 | #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U |
|
| - | 289 | #define SDMMC_HIGH_CAPACITY 0x40000000U |
|
| - | 290 | #define SDMMC_STD_CAPACITY 0x00000000U |
|
| - | 291 | #define SDMMC_CHECK_PATTERN 0x000001AAU |
|
| - | 292 | #define SD_SWITCH_1_8V_CAPACITY 0x01000000U |
|
| - | 293 | ||
| - | 294 | #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU |
|
| - | 295 | ||
| - | 296 | #define SDMMC_MAX_TRIAL 0x0000FFFFU |
|
| - | 297 | ||
| - | 298 | #define SDMMC_ALLZERO 0x00000000U |
|
| - | 299 | ||
| - | 300 | #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U |
|
| - | 301 | #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U |
|
| - | 302 | #define SDMMC_CARD_LOCKED 0x02000000U |
|
| - | 303 | ||
| - | 304 | #ifndef SDMMC_DATATIMEOUT |
|
| - | 305 | #define SDMMC_DATATIMEOUT 0xFFFFFFFFU |
|
| - | 306 | #endif /* SDMMC_DATATIMEOUT */ |
|
| - | 307 | ||
| - | 308 | #define SDMMC_0TO7BITS 0x000000FFU |
|
| - | 309 | #define SDMMC_8TO15BITS 0x0000FF00U |
|
| - | 310 | #define SDMMC_16TO23BITS 0x00FF0000U |
|
| - | 311 | #define SDMMC_24TO31BITS 0xFF000000U |
|
| - | 312 | #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU |
|
| 287 | 313 | ||
| 288 | #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) |
- | |
| 289 | #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) |
- | |
| 290 | #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) |
- | |
| 291 | #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) |
- | |
| 292 | #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) |
- | |
| 293 | - | ||
| 294 | #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) |
- | |
| 295 | - | ||
| 296 | #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) |
- | |
| 297 | - | ||
| 298 | #define SDMMC_ALLZERO ((uint32_t)0x00000000U) |
- | |
| 299 | - | ||
| 300 | #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) |
- | |
| 301 | #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) |
- | |
| 302 | #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) |
- | |
| 303 | - | ||
| 304 | #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) |
- | |
| 305 | - | ||
| 306 | #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) |
- | |
| 307 | #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) |
- | |
| 308 | #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) |
- | |
| 309 | #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) |
- | |
| 310 | #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) |
- | |
| 311 | - | ||
| 312 | #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) |
314 | #define SDMMC_HALFFIFO 0x00000008U |
| 313 | #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) |
315 | #define SDMMC_HALFFIFOBYTES 0x00000020U |
| 314 | 316 | ||
| 315 | /** |
317 | /** |
| 316 | * @brief Command Class supported |
318 | * @brief Command Class supported |
| 317 | */ |
319 | */ |
| 318 | #define SDIO_CCCC_ERASE ((uint32_t)0x00000020U) |
320 | #define SDIO_CCCC_ERASE 0x00000020U |
| 319 | 321 | ||
| 320 | #define SDIO_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ |
322 | #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ |
| 321 | #define SDIO_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ |
323 | #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ |
| 322 | #define SDIO_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ |
324 | #define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ |
| 323 | 325 | ||
| 324 | /** @defgroup SDIO_LL_Clock_Edge Clock Edge |
326 | /** @defgroup SDIO_LL_Clock_Edge Clock Edge |
| 325 | * @{ |
327 | * @{ |
| 326 | */ |
328 | */ |
| 327 | #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) |
329 | #define SDIO_CLOCK_EDGE_RISING 0x00000000U |
| 328 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
330 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
| 329 | 331 | ||
| 330 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
332 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
| 331 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
333 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
| 332 | /** |
334 | /** |
| Line 334... | Line 336... | ||
| 334 | */ |
336 | */ |
| 335 | 337 | ||
| 336 | /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass |
338 | /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass |
| 337 | * @{ |
339 | * @{ |
| 338 | */ |
340 | */ |
| 339 | #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) |
341 | #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U |
| 340 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
342 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
| 341 | 343 | ||
| 342 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
344 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
| 343 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
345 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
| 344 | /** |
346 | /** |
| Line 346... | Line 348... | ||
| 346 | */ |
348 | */ |
| 347 | 349 | ||
| 348 | /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving |
350 | /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving |
| 349 | * @{ |
351 | * @{ |
| 350 | */ |
352 | */ |
| 351 | #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) |
353 | #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U |
| 352 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
354 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
| 353 | 355 | ||
| 354 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
356 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
| 355 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
357 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
| 356 | /** |
358 | /** |
| Line 358... | Line 360... | ||
| 358 | */ |
360 | */ |
| 359 | 361 | ||
| 360 | /** @defgroup SDIO_LL_Bus_Wide Bus Width |
362 | /** @defgroup SDIO_LL_Bus_Wide Bus Width |
| 361 | * @{ |
363 | * @{ |
| 362 | */ |
364 | */ |
| 363 | #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000U) |
365 | #define SDIO_BUS_WIDE_1B 0x00000000U |
| 364 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
366 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
| 365 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
367 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
| 366 | 368 | ||
| 367 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
369 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
| 368 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
370 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
| Line 372... | Line 374... | ||
| 372 | */ |
374 | */ |
| 373 | 375 | ||
| 374 | /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control |
376 | /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control |
| 375 | * @{ |
377 | * @{ |
| 376 | */ |
378 | */ |
| 377 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) |
379 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U |
| 378 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
380 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
| 379 | 381 | ||
| 380 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
382 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
| 381 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
383 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
| 382 | /** |
384 | /** |
| Line 400... | Line 402... | ||
| 400 | */ |
402 | */ |
| 401 | 403 | ||
| 402 | /** @defgroup SDIO_LL_Response_Type Response Type |
404 | /** @defgroup SDIO_LL_Response_Type Response Type |
| 403 | * @{ |
405 | * @{ |
| 404 | */ |
406 | */ |
| 405 | #define SDIO_RESPONSE_NO ((uint32_t)0x00000000U) |
407 | #define SDIO_RESPONSE_NO 0x00000000U |
| 406 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
408 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
| 407 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
409 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
| 408 | 410 | ||
| 409 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
411 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
| 410 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
412 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
| Line 414... | Line 416... | ||
| 414 | */ |
416 | */ |
| 415 | 417 | ||
| 416 | /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt |
418 | /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt |
| 417 | * @{ |
419 | * @{ |
| 418 | */ |
420 | */ |
| 419 | #define SDIO_WAIT_NO ((uint32_t)0x00000000U) |
421 | #define SDIO_WAIT_NO 0x00000000U |
| 420 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
422 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
| 421 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
423 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
| 422 | 424 | ||
| 423 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
425 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
| 424 | ((WAIT) == SDIO_WAIT_IT) || \ |
426 | ((WAIT) == SDIO_WAIT_IT) || \ |
| Line 428... | Line 430... | ||
| 428 | */ |
430 | */ |
| 429 | 431 | ||
| 430 | /** @defgroup SDIO_LL_CPSM_State CPSM State |
432 | /** @defgroup SDIO_LL_CPSM_State CPSM State |
| 431 | * @{ |
433 | * @{ |
| 432 | */ |
434 | */ |
| 433 | #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000U) |
435 | #define SDIO_CPSM_DISABLE 0x00000000U |
| 434 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
436 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
| 435 | 437 | ||
| 436 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
438 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
| 437 | ((CPSM) == SDIO_CPSM_ENABLE)) |
439 | ((CPSM) == SDIO_CPSM_ENABLE)) |
| 438 | /** |
440 | /** |
| Line 440... | Line 442... | ||
| 440 | */ |
442 | */ |
| 441 | 443 | ||
| 442 | /** @defgroup SDIO_LL_Response_Registers Response Register |
444 | /** @defgroup SDIO_LL_Response_Registers Response Register |
| 443 | * @{ |
445 | * @{ |
| 444 | */ |
446 | */ |
| 445 | #define SDIO_RESP1 ((uint32_t)0x00000000U) |
447 | #define SDIO_RESP1 0x00000000U |
| 446 | #define SDIO_RESP2 ((uint32_t)0x00000004U) |
448 | #define SDIO_RESP2 0x00000004U |
| 447 | #define SDIO_RESP3 ((uint32_t)0x00000008U) |
449 | #define SDIO_RESP3 0x00000008U |
| 448 | #define SDIO_RESP4 ((uint32_t)0x0000000CU) |
450 | #define SDIO_RESP4 0x0000000CU |
| 449 | 451 | ||
| 450 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
452 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
| 451 | ((RESP) == SDIO_RESP2) || \ |
453 | ((RESP) == SDIO_RESP2) || \ |
| 452 | ((RESP) == SDIO_RESP3) || \ |
454 | ((RESP) == SDIO_RESP3) || \ |
| 453 | ((RESP) == SDIO_RESP4)) |
455 | ((RESP) == SDIO_RESP4)) |
| 454 | /** |
456 | /** |
| 455 | * @} |
457 | * @} |
| 456 | */ |
458 | */ |
| 457 | 459 | ||
| 458 | /** @defgroup SDIO_LL_Data_Length Data Lenght |
460 | /** @defgroup SDIO_LL_Data_Length Data Length |
| 459 | * @{ |
461 | * @{ |
| 460 | */ |
462 | */ |
| 461 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) |
463 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) |
| 462 | /** |
464 | /** |
| 463 | * @} |
465 | * @} |
| 464 | */ |
466 | */ |
| 465 | 467 | ||
| 466 | /** @defgroup SDIO_LL_Data_Block_Size Data Block Size |
468 | /** @defgroup SDIO_LL_Data_Block_Size Data Block Size |
| 467 | * @{ |
469 | * @{ |
| 468 | */ |
470 | */ |
| 469 | #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) |
471 | #define SDIO_DATABLOCK_SIZE_1B 0x00000000U |
| 470 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
472 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
| 471 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
473 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
| 472 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
474 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
| 473 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
475 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
| 474 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
476 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
| Line 502... | Line 504... | ||
| 502 | */ |
504 | */ |
| 503 | 505 | ||
| 504 | /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction |
506 | /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction |
| 505 | * @{ |
507 | * @{ |
| 506 | */ |
508 | */ |
| 507 | #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) |
509 | #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U |
| 508 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
510 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
| 509 | 511 | ||
| 510 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
512 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
| 511 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
513 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
| 512 | /** |
514 | /** |
| Line 514... | Line 516... | ||
| 514 | */ |
516 | */ |
| 515 | 517 | ||
| 516 | /** @defgroup SDIO_LL_Transfer_Type Transfer Type |
518 | /** @defgroup SDIO_LL_Transfer_Type Transfer Type |
| 517 | * @{ |
519 | * @{ |
| 518 | */ |
520 | */ |
| 519 | #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) |
521 | #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U |
| 520 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
522 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
| 521 | 523 | ||
| 522 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
524 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
| 523 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
525 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
| 524 | /** |
526 | /** |
| Line 526... | Line 528... | ||
| 526 | */ |
528 | */ |
| 527 | 529 | ||
| 528 | /** @defgroup SDIO_LL_DPSM_State DPSM State |
530 | /** @defgroup SDIO_LL_DPSM_State DPSM State |
| 529 | * @{ |
531 | * @{ |
| 530 | */ |
532 | */ |
| 531 | #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000U) |
533 | #define SDIO_DPSM_DISABLE 0x00000000U |
| 532 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
534 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
| 533 | 535 | ||
| 534 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
536 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
| 535 | ((DPSM) == SDIO_DPSM_ENABLE)) |
537 | ((DPSM) == SDIO_DPSM_ENABLE)) |
| 536 | /** |
538 | /** |
| Line 538... | Line 540... | ||
| 538 | */ |
540 | */ |
| 539 | 541 | ||
| 540 | /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode |
542 | /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode |
| 541 | * @{ |
543 | * @{ |
| 542 | */ |
544 | */ |
| 543 | #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) |
545 | #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U |
| 544 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
546 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
| 545 | 547 | ||
| 546 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
548 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
| 547 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
549 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
| 548 | /** |
550 | /** |
| Line 1077... | Line 1079... | ||
| 1077 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1079 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1078 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); |
1080 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); |
| 1079 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); |
1081 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); |
| 1080 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); |
1082 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); |
| 1081 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1083 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| - | 1084 | uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
|
| 1082 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); |
1085 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); |
| 1083 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1086 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1084 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); |
1087 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); |
| 1085 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1088 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1086 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1089 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); |