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1 
/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32l1xx_ll_rcc.h
 3 
  * @file    stm32l1xx_ll_rcc.h
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Header file of RCC LL module.
 5 
  * @brief   Header file of RCC LL module.
6 
  ******************************************************************************
 6 
  ******************************************************************************
7 
  * @attention
 7 
  * @attention
8 
  *
 8 
  *
9 
  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
 9 
  * Copyright (c) 2017 STMicroelectronics.
10 
  * All rights reserved.</center></h2>
 10 
  * All rights reserved.
11 
  *
 11 
  *
12 
  * This software component is licensed by ST under BSD 3-Clause license,
 12 
  * This software is licensed under terms that can be found in the LICENSE file in
13 
  * the "License"; You may not use this file except in compliance with the
 13 
  * the root directory of this software component.
14 
  * License. You may obtain a copy of the License at:
 14 
  * If no LICENSE file comes with this software, it is provided AS-IS.
15 
  *                        opensource.org/licenses/BSD-3-Clause
 15 
  ******************************************************************************
16 
  *
 16 
  */
17 
  ******************************************************************************
 17 
 
18 
  */
 18 
/* Define to prevent recursive inclusion -------------------------------------*/
19 
 
 19 
#ifndef __STM32L1xx_LL_RCC_H
20 
/* Define to prevent recursive inclusion -------------------------------------*/
 20 
#define __STM32L1xx_LL_RCC_H
21 
#ifndef __STM32L1xx_LL_RCC_H
 21 
 
22 
#define __STM32L1xx_LL_RCC_H
 22 
#ifdef __cplusplus
23 
 
 23 
extern "C" {
24 
#ifdef __cplusplus
 24 
#endif
25 
extern "C" {
 25 
 
26 
#endif
 26 
/* Includes ------------------------------------------------------------------*/
27 
 
 27 
#include "stm32l1xx.h"
28 
/* Includes ------------------------------------------------------------------*/
 28 
 
29 
#include "stm32l1xx.h"
 29 
/** @addtogroup STM32L1xx_LL_Driver
30 
 
 30 
  * @{
31 
/** @addtogroup STM32L1xx_LL_Driver
 31 
  */
32 
  * @{
 32 
 
33 
  */
 33 
#if defined(RCC)
34 
 
 34 
 
35 
#if defined(RCC)
 35 
/** @defgroup RCC_LL RCC
36 
 
 36 
  * @{
37 
/** @defgroup RCC_LL RCC
 37 
  */
38 
  * @{
 38 
 
39 
  */
 39 
/* Private types -------------------------------------------------------------*/
40 
 
 40 
/* Private variables ---------------------------------------------------------*/
41 
/* Private types -------------------------------------------------------------*/
 41 
/* Private constants ---------------------------------------------------------*/
42 
/* Private variables ---------------------------------------------------------*/
 42 
/* Private macros ------------------------------------------------------------*/
43 
/* Private constants ---------------------------------------------------------*/
 43 
/* Exported types ------------------------------------------------------------*/
44 
/* Private macros ------------------------------------------------------------*/
 44 
#if defined(USE_FULL_LL_DRIVER)
45 
/* Exported types ------------------------------------------------------------*/
 45 
/** @defgroup RCC_LL_Exported_Types RCC Exported Types
46 
#if defined(USE_FULL_LL_DRIVER)
 46 
  * @{
47 
/** @defgroup RCC_LL_Exported_Types RCC Exported Types
 47 
  */
48 
  * @{
 48 
 
49 
  */
 49 
/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
50 
 
 50 
  * @{
51 
/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
 51 
  */
52 
  * @{
 52 
 
53 
  */
 53 
/**
54 
 
 54 
  * @brief  RCC Clocks Frequency Structure
55 
/**
 55 
  */
56 
  * @brief  RCC Clocks Frequency Structure
 56 
typedef struct
57 
  */
 57 
{
58 
typedef struct
 58 
  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
59 
{
 59 
  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
60 
  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
 60 
  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
61 
  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
 61 
  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
62 
  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
 62 
} LL_RCC_ClocksTypeDef;
63 
  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
 63 
 
64 
} LL_RCC_ClocksTypeDef;
 64 
/**
65 
 
 65 
  * @}
66 
/**
 66 
  */
67 
  * @}
 67 
 
68 
  */
 68 
/**
69 
 
 69 
  * @}
70 
/**
 70 
  */
71 
  * @}
 71 
#endif /* USE_FULL_LL_DRIVER */
72 
  */
 72 
 
73 
#endif /* USE_FULL_LL_DRIVER */
 73 
/* Exported constants --------------------------------------------------------*/
74 
 
 74 
/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
75 
/* Exported constants --------------------------------------------------------*/
 75 
  * @{
76 
/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
 76 
  */
77 
  * @{
 77 
 
78 
  */
 78 
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
79 
 
 79 
  * @brief    Defines used to adapt values of different oscillators
80 
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
 80 
  * @note     These values could be modified in the user environment according to
81 
  * @brief    Defines used to adapt values of different oscillators
 81 
  *           HW set-up.
82 
  * @note     These values could be modified in the user environment according to
 82 
  * @{
83 
  *           HW set-up.
 83 
  */
84 
  * @{
 84 
#if !defined  (HSE_VALUE)
85 
  */
 85 
#define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
86 
#if !defined  (HSE_VALUE)
 86 
#endif /* HSE_VALUE */
87 
#define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
 87 
 
88 
#endif /* HSE_VALUE */
 88 
#if !defined  (HSI_VALUE)
89 
 
 89 
#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
90 
#if !defined  (HSI_VALUE)
 90 
#endif /* HSI_VALUE */
91 
#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
 91 
 
92 
#endif /* HSI_VALUE */
 92 
#if !defined  (LSE_VALUE)
93 
 
 93 
#define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
94 
#if !defined  (LSE_VALUE)
 94 
#endif /* LSE_VALUE */
95 
#define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
 95 
 
96 
#endif /* LSE_VALUE */
 96 
#if !defined  (LSI_VALUE)
97 
 
 97 
#define LSI_VALUE    37000U    /*!< Value of the LSI oscillator in Hz */
98 
#if !defined  (LSI_VALUE)
 98 
#endif /* LSI_VALUE */
99 
#define LSI_VALUE    37000U    /*!< Value of the LSI oscillator in Hz */
 99 
/**
100 
#endif /* LSI_VALUE */
 100 
  * @}
101 
/**
 101 
  */
102 
  * @}
 102 
 
103 
  */
 103 
/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
104 
 
 104 
  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
105 
/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
 105 
  * @{
106 
  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
 106 
  */
107 
  * @{
 107 
#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
108 
  */
 108 
#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
109 
#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
 109 
#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
110 
#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
 110 
#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
111 
#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
 111 
#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
112 
#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
 112 
#define LL_RCC_CIR_MSIRDYC                RCC_CIR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
113 
#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
 113 
#if defined(RCC_LSECSS_SUPPORT)
114 
#define LL_RCC_CIR_MSIRDYC                RCC_CIR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
 114 
#define LL_RCC_CIR_LSECSSC                RCC_CIR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
115 
#if defined(RCC_LSECSS_SUPPORT)
 115 
#endif /* RCC_LSECSS_SUPPORT */
116 
#define LL_RCC_CIR_LSECSSC                RCC_CIR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
 116 
#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
117 
#endif /* RCC_LSECSS_SUPPORT */
 117 
/**
118 
#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
 118 
  * @}
119 
/**
 119 
  */
120 
  * @}
 120 
 
121 
  */
 121 
/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
122 
 
 122 
  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
123 
/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
 123 
  * @{
124 
  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
 124 
  */
125 
  * @{
 125 
#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
126 
  */
 126 
#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
127 
#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
 127 
#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
128 
#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
 128 
#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
129 
#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
 129 
#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
130 
#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
 130 
#define LL_RCC_CIR_MSIRDYF                RCC_CIR_MSIRDYF     /*!< MSI Ready Interrupt flag */
131 
#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
 131 
#if defined(RCC_LSECSS_SUPPORT)
132 
#define LL_RCC_CIR_MSIRDYF                RCC_CIR_MSIRDYF     /*!< MSI Ready Interrupt flag */
 132 
#define LL_RCC_CIR_LSECSSF                RCC_CIR_LSECSSF    /*!< LSE Clock Security System Interrupt flag */
133 
#if defined(RCC_LSECSS_SUPPORT)
 133 
#endif /* RCC_LSECSS_SUPPORT */
134 
#define LL_RCC_CIR_LSECSSF                RCC_CIR_LSECSSF    /*!< LSE Clock Security System Interrupt flag */
 134 
#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF       /*!< Clock Security System Interrupt flag */
135 
#endif /* RCC_LSECSS_SUPPORT */
 135 
#define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         /*!< OBL reset flag */
136 
#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF       /*!< Clock Security System Interrupt flag */
 136 
#define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         /*!< PIN reset flag */
137 
#define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         /*!< OBL reset flag */
 137 
#define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         /*!< POR/PDR reset flag */
138 
#define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         /*!< PIN reset flag */
 138 
#define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         /*!< Software Reset flag */
139 
#define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         /*!< POR/PDR reset flag */
 139 
#define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        /*!< Independent Watchdog reset flag */
140 
#define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         /*!< Software Reset flag */
 140 
#define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        /*!< Window watchdog reset flag */
141 
#define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        /*!< Independent Watchdog reset flag */
 141 
#define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        /*!< Low-Power reset flag */
142 
#define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        /*!< Window watchdog reset flag */
 142 
/**
143 
#define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        /*!< Low-Power reset flag */
 143 
  * @}
144 
/**
 144 
  */
145 
  * @}
 145 
 
146 
  */
 146 
/** @defgroup RCC_LL_EC_IT IT Defines
147 
 
 147 
  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
148 
/** @defgroup RCC_LL_EC_IT IT Defines
 148 
  * @{
149 
  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
 149 
  */
150 
  * @{
 150 
#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
151 
  */
 151 
#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
152 
#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
 152 
#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
153 
#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
 153 
#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
154 
#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
 154 
#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
155 
#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
 155 
#define LL_RCC_CIR_MSIRDYIE               RCC_CIR_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
156 
#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
 156 
#if defined(RCC_LSECSS_SUPPORT)
157 
#define LL_RCC_CIR_MSIRDYIE               RCC_CIR_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
 157 
#define LL_RCC_CIR_LSECSSIE               RCC_CIR_LSECSSIE      /*!< LSE CSS Interrupt Enable */
158 
#if defined(RCC_LSECSS_SUPPORT)
 158 
#endif /* RCC_LSECSS_SUPPORT */
159 
#define LL_RCC_CIR_LSECSSIE               RCC_CIR_LSECSSIE      /*!< LSE CSS Interrupt Enable */
 159 
/**
160 
#endif /* RCC_LSECSS_SUPPORT */
 160 
  * @}
161 
/**
 161 
  */
162 
  * @}
 162 
 
163 
  */
 163 
/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
164 
 
 164 
  * @{
165 
/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
 165 
  */
166 
  * @{
 166 
#define LL_RCC_RTC_HSE_DIV_2               0x00000000U          /*!< HSE is divided by 2 for RTC clock  */
167 
  */
 167 
#define LL_RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0      /*!< HSE is divided by 4 for RTC clock  */
168 
#define LL_RCC_RTC_HSE_DIV_2               0x00000000U          /*!< HSE is divided by 2 for RTC clock  */
 168 
#define LL_RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1      /*!< HSE is divided by 8 for RTC clock  */
169 
#define LL_RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0      /*!< HSE is divided by 4 for RTC clock  */
 169 
#define LL_RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE        /*!< HSE is divided by 16 for RTC clock */
170 
#define LL_RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1      /*!< HSE is divided by 8 for RTC clock  */
 170 
/**
171 
#define LL_RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE        /*!< HSE is divided by 16 for RTC clock */
 171 
  * @}
172 
/**
 172 
  */
173 
  * @}
 173 
 
174 
  */
 174 
/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
175 
 
 175 
  * @{
176 
/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
 176 
  */
177 
  * @{
 177 
#define LL_RCC_MSIRANGE_0                  RCC_ICSCR_MSIRANGE_0  /*!< MSI = 65.536 KHz */
178 
  */
 178 
#define LL_RCC_MSIRANGE_1                  RCC_ICSCR_MSIRANGE_1  /*!< MSI = 131.072 KHz*/
179 
#define LL_RCC_MSIRANGE_0                  RCC_ICSCR_MSIRANGE_0  /*!< MSI = 65.536 KHz */
 179 
#define LL_RCC_MSIRANGE_2                  RCC_ICSCR_MSIRANGE_2  /*!< MSI = 262.144 KHz */
180 
#define LL_RCC_MSIRANGE_1                  RCC_ICSCR_MSIRANGE_1  /*!< MSI = 131.072 KHz*/
 180 
#define LL_RCC_MSIRANGE_3                  RCC_ICSCR_MSIRANGE_3  /*!< MSI = 524.288 KHz */
181 
#define LL_RCC_MSIRANGE_2                  RCC_ICSCR_MSIRANGE_2  /*!< MSI = 262.144 KHz */
 181 
#define LL_RCC_MSIRANGE_4                  RCC_ICSCR_MSIRANGE_4  /*!< MSI = 1.048 MHz */
182 
#define LL_RCC_MSIRANGE_3                  RCC_ICSCR_MSIRANGE_3  /*!< MSI = 524.288 KHz */
 182 
#define LL_RCC_MSIRANGE_5                  RCC_ICSCR_MSIRANGE_5  /*!< MSI = 2.097 MHz */
183 
#define LL_RCC_MSIRANGE_4                  RCC_ICSCR_MSIRANGE_4  /*!< MSI = 1.048 MHz */
 183 
#define LL_RCC_MSIRANGE_6                  RCC_ICSCR_MSIRANGE_6  /*!< MSI = 4.194 MHz */
184 
#define LL_RCC_MSIRANGE_5                  RCC_ICSCR_MSIRANGE_5  /*!< MSI = 2.097 MHz */
 184 
/**
185 
#define LL_RCC_MSIRANGE_6                  RCC_ICSCR_MSIRANGE_6  /*!< MSI = 4.194 MHz */
 185 
  * @}
186 
/**
 186 
  */
187 
  * @}
 187 
 
188 
  */
 188 
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
189 
 
 189 
  * @{
190 
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
 190 
  */
191 
  * @{
 191 
#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
192 
  */
 192 
#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
193 
#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
 193 
#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
194 
#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
 194 
#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
195 
#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
 195 
/**
196 
#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
 196 
  * @}
197 
/**
 197 
  */
198 
  * @}
 198 
 
199 
  */
 199 
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
200 
 
 200 
  * @{
201 
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
 201 
  */
202 
  * @{
 202 
#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
203 
  */
 203 
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
204 
#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
 204 
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
205 
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
 205 
#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
206 
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
 206 
/**
207 
#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
 207 
  * @}
208 
/**
 208 
  */
209 
  * @}
 209 
 
210 
  */
 210 
/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
211 
 
 211 
  * @{
212 
/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
 212 
  */
213 
  * @{
 213 
#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
214 
  */
 214 
#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
215 
#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
 215 
#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
216 
#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
 216 
#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
217 
#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
 217 
#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
218 
#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
 218 
#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
219 
#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
 219 
#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
220 
#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
 220 
#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
221 
#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
 221 
#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
222 
#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
 222 
/**
223 
#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
 223 
  * @}
224 
/**
 224 
  */
225 
  * @}
 225 
 
226 
  */
 226 
/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
227 
 
 227 
  * @{
228 
/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
 228 
  */
229 
  * @{
 229 
#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
230 
  */
 230 
#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
231 
#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
 231 
#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
232 
#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
 232 
#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
233 
#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
 233 
#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
234 
#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
 234 
/**
235 
#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
 235 
  * @}
236 
/**
 236 
  */
237 
  * @}
 237 
 
238 
  */
 238 
/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
239 
 
 239 
  * @{
240 
/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
 240 
  */
241 
  * @{
 241 
#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
242 
  */
 242 
#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
243 
#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
 243 
#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
244 
#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
 244 
#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
245 
#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
 245 
#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
246 
#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
 246 
/**
247 
#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
 247 
  * @}
248 
/**
 248 
  */
249 
  * @}
 249 
 
250 
  */
 250 
/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
251 
 
 251 
  * @{
252 
/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
 252 
  */
253 
  * @{
 253 
#define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
254 
  */
 254 
#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
255 
#define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
 255 
#define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
256 
#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
 256 
#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_MSI          /*!< MSI selection as MCO source */
257 
#define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
 257 
#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
258 
#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_MSI          /*!< MSI selection as MCO source */
 258 
#define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          /*!< LSI selection as MCO source */
259 
#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
 259 
#define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          /*!< LSE selection as MCO source */
260 
#define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          /*!< LSI selection as MCO source */
 260 
#define LL_RCC_MCO1SOURCE_PLLCLK           RCC_CFGR_MCOSEL_PLL          /*!< PLLCLK selection as MCO source */
261 
#define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          /*!< LSE selection as MCO source */
 261 
/**
262 
#define LL_RCC_MCO1SOURCE_PLLCLK           RCC_CFGR_MCOSEL_PLL          /*!< PLLCLK selection as MCO source */
 262 
  * @}
263 
/**
 263 
  */
264 
  * @}
 264 
 
265 
  */
 265 
/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
266 
 
 266 
  * @{
267 
/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
 267 
  */
268 
  * @{
 268 
#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1  /*!< MCO Clock divided by 1  */
269 
  */
 269 
#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2  /*!< MCO Clock divided by 2  */
270 
#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1  /*!< MCO Clock divided by 1  */
 270 
#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4  /*!< MCO Clock divided by 4  */
271 
#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2  /*!< MCO Clock divided by 2  */
 271 
#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8  /*!< MCO Clock divided by 8  */
272 
#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4  /*!< MCO Clock divided by 4  */
 272 
#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
273 
#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8  /*!< MCO Clock divided by 8  */
 273 
/**
274 
#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
 274 
  * @}
275 
/**
 275 
  */
276 
  * @}
 276 
#if defined(USE_FULL_LL_DRIVER)
277 
  */
 277 
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
278 
#if defined(USE_FULL_LL_DRIVER)
 278 
  * @{
279 
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
 279 
  */
280 
  * @{
 280 
#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
281 
  */
 281 
#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
282 
#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
 282 
/**
283 
#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
 283 
  * @}
284 
/**
 284 
  */
285 
  * @}
 285 
#endif /* USE_FULL_LL_DRIVER */
286 
  */
 286 
 
287 
#endif /* USE_FULL_LL_DRIVER */
 287 
 
288 
 
 288 
 
289 
 
 289 
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
290 
 
 290 
  * @{
291 
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
 291 
  */
292 
  * @{
 292 
#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
293 
  */
 293 
#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CSR_RTCSEL_LSE            /*!< LSE oscillator clock used as RTC clock */
294 
#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
 294 
#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CSR_RTCSEL_LSI            /*!< LSI oscillator clock used as RTC clock */
295 
#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CSR_RTCSEL_LSE            /*!< LSE oscillator clock used as RTC clock */
 295 
#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_CSR_RTCSEL_HSE            /*!< HSE oscillator clock divided by a programmable prescaler
296 
#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CSR_RTCSEL_LSI            /*!< LSI oscillator clock used as RTC clock */
 296 
                                                                             (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
297 
#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_CSR_RTCSEL_HSE            /*!< HSE oscillator clock divided by a programmable prescaler
 297 
/**
298 
                                                                             (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
 298 
  * @}
299 
/**
 299 
  */
300 
  * @}
 300 
 
301 
  */
 301 
/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
302 
 
 302 
  * @{
303 
/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
 303 
  */
304 
  * @{
 304 
#define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  /*!< PLL input clock * 3  */
305 
  */
 305 
#define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  /*!< PLL input clock * 4  */
306 
#define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  /*!< PLL input clock * 3  */
 306 
#define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  /*!< PLL input clock * 6  */
307 
#define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  /*!< PLL input clock * 4  */
 307 
#define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  /*!< PLL input clock * 8  */
308 
#define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  /*!< PLL input clock * 6  */
 308 
#define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
309 
#define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  /*!< PLL input clock * 8  */
 309 
#define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
310 
#define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
 310 
#define LL_RCC_PLL_MUL_24                  RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
311 
#define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
 311 
#define LL_RCC_PLL_MUL_32                  RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
312 
#define LL_RCC_PLL_MUL_24                  RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
 312 
#define LL_RCC_PLL_MUL_48                  RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
313 
#define LL_RCC_PLL_MUL_32                  RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
 313 
/**
314 
#define LL_RCC_PLL_MUL_48                  RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
 314 
  * @}
315 
/**
 315 
  */
316 
  * @}
 316 
 
317 
  */
 317 
/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
318 
 
 318 
  * @{
319 
/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
 319 
  */
320 
  * @{
 320 
#define LL_RCC_PLL_DIV_2                   RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
321 
  */
 321 
#define LL_RCC_PLL_DIV_3                   RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
322 
#define LL_RCC_PLL_DIV_2                   RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
 322 
#define LL_RCC_PLL_DIV_4                   RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
323 
#define LL_RCC_PLL_DIV_3                   RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
 323 
/**
324 
#define LL_RCC_PLL_DIV_4                   RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
 324 
  * @}
325 
/**
 325 
  */
326 
  * @}
 326 
 
327 
  */
 327 
/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
328 
 
 328 
  * @{
329 
/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
 329 
  */
330 
  * @{
 330 
#define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI                           /*!< HSI clock selected as PLL entry clock source */
331 
  */
 331 
#define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE                           /*!< HSE clock selected as PLL entry clock source */
332 
#define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI                           /*!< HSI clock selected as PLL entry clock source */
 332 
/**
333 
#define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE                           /*!< HSE clock selected as PLL entry clock source */
 333 
  * @}
334 
/**
 334 
  */
335 
  * @}
 335 
 
336 
  */
 336 
/**
337 
 
 337 
  * @}
338 
/**
 338 
  */
339 
  * @}
 339 
 
340 
  */
 340 
/* Exported macro ------------------------------------------------------------*/
341 
 
 341 
/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
342 
/* Exported macro ------------------------------------------------------------*/
 342 
  * @{
343 
/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
 343 
  */
344 
  * @{
 344 
 
345 
  */
 345 
/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
346 
 
 346 
  * @{
347 
/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
 347 
  */
348 
  * @{
 348 
 
349 
  */
 349 
/**
350 
 
 350 
  * @brief  Write a value in RCC register
351 
/**
 351 
  * @param  __REG__ Register to be written
352 
  * @brief  Write a value in RCC register
 352 
  * @param  __VALUE__ Value to be written in the register
353 
  * @param  __REG__ Register to be written
 353 
  * @retval None
354 
  * @param  __VALUE__ Value to be written in the register
 354 
  */
355 
  * @retval None
 355 
#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
356 
  */
 356 
 
357 
#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
 357 
/**
358 
 
 358 
  * @brief  Read a value in RCC register
359 
/**
 359 
  * @param  __REG__ Register to be read
360 
  * @brief  Read a value in RCC register
 360 
  * @retval Register value
361 
  * @param  __REG__ Register to be read
 361 
  */
362 
  * @retval Register value
 362 
#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
363 
  */
 363 
/**
364 
#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
 364 
  * @}
365 
/**
 365 
  */
366 
  * @}
 366 
 
367 
  */
 367 
/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
368 
 
 368 
  * @{
369 
/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
 369 
  */
370 
  * @{
 370 
 
371 
  */
 371 
/**
372 
 
 372 
  * @brief  Helper macro to calculate the PLLCLK frequency
373 
/**
 373 
  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
374 
  * @brief  Helper macro to calculate the PLLCLK frequency
 374 
  *                                      @ref LL_RCC_PLL_GetMultiplicator (),
375 
  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
 375 
  *                                      @ref LL_RCC_PLL_GetDivider ());
376 
  *                                      @ref LL_RCC_PLL_GetMultiplicator (),
 376 
  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
377 
  *                                      @ref LL_RCC_PLL_GetDivider ());
 377 
  * @param  __PLLMUL__ This parameter can be one of the following values:
378 
  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
 378 
  *         @arg @ref LL_RCC_PLL_MUL_3
379 
  * @param  __PLLMUL__ This parameter can be one of the following values:
 379 
  *         @arg @ref LL_RCC_PLL_MUL_4
380 
  *         @arg @ref LL_RCC_PLL_MUL_3
 380 
  *         @arg @ref LL_RCC_PLL_MUL_6
381 
  *         @arg @ref LL_RCC_PLL_MUL_4
 381 
  *         @arg @ref LL_RCC_PLL_MUL_8
382 
  *         @arg @ref LL_RCC_PLL_MUL_6
 382 
  *         @arg @ref LL_RCC_PLL_MUL_12
383 
  *         @arg @ref LL_RCC_PLL_MUL_8
 383 
  *         @arg @ref LL_RCC_PLL_MUL_16
384 
  *         @arg @ref LL_RCC_PLL_MUL_12
 384 
  *         @arg @ref LL_RCC_PLL_MUL_24
385 
  *         @arg @ref LL_RCC_PLL_MUL_16
 385 
  *         @arg @ref LL_RCC_PLL_MUL_32
386 
  *         @arg @ref LL_RCC_PLL_MUL_24
 386 
  *         @arg @ref LL_RCC_PLL_MUL_48
387 
  *         @arg @ref LL_RCC_PLL_MUL_32
 387 
  * @param  __PLLDIV__ This parameter can be one of the following values:
388 
  *         @arg @ref LL_RCC_PLL_MUL_48
 388 
  *         @arg @ref LL_RCC_PLL_DIV_2
389 
  * @param  __PLLDIV__ This parameter can be one of the following values:
 389 
  *         @arg @ref LL_RCC_PLL_DIV_3
390 
  *         @arg @ref LL_RCC_PLL_DIV_2
 390 
  *         @arg @ref LL_RCC_PLL_DIV_4
391 
  *         @arg @ref LL_RCC_PLL_DIV_3
 391 
  * @retval PLL clock frequency (in Hz)
392 
  *         @arg @ref LL_RCC_PLL_DIV_4
 392 
  */
393 
  * @retval PLL clock frequency (in Hz)
 393 
#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__,  __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1U))
394 
  */
 394 
 
395 
#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__,  __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1U))
 395 
/**
396 
 
 396 
  * @brief  Helper macro to calculate the HCLK frequency
397 
/**
 397 
  * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
398 
  * @brief  Helper macro to calculate the HCLK frequency
 398 
  *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
399 
  * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
 399 
  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
400 
  *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
 400 
  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
401 
  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
 401 
  *         @arg @ref LL_RCC_SYSCLK_DIV_1
402 
  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
 402 
  *         @arg @ref LL_RCC_SYSCLK_DIV_2
403 
  *         @arg @ref LL_RCC_SYSCLK_DIV_1
 403 
  *         @arg @ref LL_RCC_SYSCLK_DIV_4
404 
  *         @arg @ref LL_RCC_SYSCLK_DIV_2
 404 
  *         @arg @ref LL_RCC_SYSCLK_DIV_8
405 
  *         @arg @ref LL_RCC_SYSCLK_DIV_4
 405 
  *         @arg @ref LL_RCC_SYSCLK_DIV_16
406 
  *         @arg @ref LL_RCC_SYSCLK_DIV_8
 406 
  *         @arg @ref LL_RCC_SYSCLK_DIV_64
407 
  *         @arg @ref LL_RCC_SYSCLK_DIV_16
 407 
  *         @arg @ref LL_RCC_SYSCLK_DIV_128
408 
  *         @arg @ref LL_RCC_SYSCLK_DIV_64
 408 
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
409 
  *         @arg @ref LL_RCC_SYSCLK_DIV_128
 409 
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
410 
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
 410 
  * @retval HCLK clock frequency (in Hz)
411 
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
 411 
  */
412 
  * @retval HCLK clock frequency (in Hz)
 412 
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
413 
  */
 413 
 
414 
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
 414 
/**
415 
 
 415 
  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
416 
/**
 416 
  * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
417 
  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
 417 
  *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
418 
  * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
 418 
  * @param  __HCLKFREQ__ HCLK frequency
419 
  *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
 419 
  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
420 
  * @param  __HCLKFREQ__ HCLK frequency
 420 
  *         @arg @ref LL_RCC_APB1_DIV_1
421 
  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
 421 
  *         @arg @ref LL_RCC_APB1_DIV_2
422 
  *         @arg @ref LL_RCC_APB1_DIV_1
 422 
  *         @arg @ref LL_RCC_APB1_DIV_4
423 
  *         @arg @ref LL_RCC_APB1_DIV_2
 423 
  *         @arg @ref LL_RCC_APB1_DIV_8
424 
  *         @arg @ref LL_RCC_APB1_DIV_4
 424 
  *         @arg @ref LL_RCC_APB1_DIV_16
425 
  *         @arg @ref LL_RCC_APB1_DIV_8
 425 
  * @retval PCLK1 clock frequency (in Hz)
426 
  *         @arg @ref LL_RCC_APB1_DIV_16
 426 
  */
427 
  * @retval PCLK1 clock frequency (in Hz)
 427 
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
428 
  */
 428 
 
429 
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
 429 
/**
430 
 
 430 
  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
431 
/**
 431 
  * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
432 
  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
 432 
  *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
433 
  * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
 433 
  * @param  __HCLKFREQ__ HCLK frequency
434 
  *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
 434 
  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
435 
  * @param  __HCLKFREQ__ HCLK frequency
 435 
  *         @arg @ref LL_RCC_APB2_DIV_1
436 
  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
 436 
  *         @arg @ref LL_RCC_APB2_DIV_2
437 
  *         @arg @ref LL_RCC_APB2_DIV_1
 437 
  *         @arg @ref LL_RCC_APB2_DIV_4
438 
  *         @arg @ref LL_RCC_APB2_DIV_2
 438 
  *         @arg @ref LL_RCC_APB2_DIV_8
439 
  *         @arg @ref LL_RCC_APB2_DIV_4
 439 
  *         @arg @ref LL_RCC_APB2_DIV_16
440 
  *         @arg @ref LL_RCC_APB2_DIV_8
 440 
  * @retval PCLK2 clock frequency (in Hz)
441 
  *         @arg @ref LL_RCC_APB2_DIV_16
 441 
  */
442 
  * @retval PCLK2 clock frequency (in Hz)
 442 
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
443 
  */
 443 
 
444 
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
 444 
/**
445 
 
 445 
  * @brief  Helper macro to calculate the MSI frequency (in Hz)
446 
/**
 446 
  * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
447 
  * @brief  Helper macro to calculate the MSI frequency (in Hz)
 447 
  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
448 
  * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
 448 
  * @param  __MSIRANGE__ This parameter can be one of the following values:
449 
  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
 449 
  *         @arg @ref LL_RCC_MSIRANGE_0
450 
  * @param  __MSIRANGE__ This parameter can be one of the following values:
 450 
  *         @arg @ref LL_RCC_MSIRANGE_1
451 
  *         @arg @ref LL_RCC_MSIRANGE_0
 451 
  *         @arg @ref LL_RCC_MSIRANGE_2
452 
  *         @arg @ref LL_RCC_MSIRANGE_1
 452 
  *         @arg @ref LL_RCC_MSIRANGE_3
453 
  *         @arg @ref LL_RCC_MSIRANGE_2
 453 
  *         @arg @ref LL_RCC_MSIRANGE_4
454 
  *         @arg @ref LL_RCC_MSIRANGE_3
 454 
  *         @arg @ref LL_RCC_MSIRANGE_5
455 
  *         @arg @ref LL_RCC_MSIRANGE_4
 455 
  *         @arg @ref LL_RCC_MSIRANGE_6
456 
  *         @arg @ref LL_RCC_MSIRANGE_5
 456 
  * @retval MSI clock frequency (in Hz)
457 
  *         @arg @ref LL_RCC_MSIRANGE_6
 457 
  */
458 
  * @retval MSI clock frequency (in Hz)
 458 
#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1U))))
459 
  */
 459 
 
460 
#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1U))))
 460 
/**
461 
 
 461 
  * @}
462 
/**
 462 
  */
463 
  * @}
 463 
 
464 
  */
 464 
/**
465 
 
 465 
  * @}
466 
/**
 466 
  */
467 
  * @}
 467 
 
468 
  */
 468 
/* Exported functions --------------------------------------------------------*/
469 
 
 469 
/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
470 
/* Exported functions --------------------------------------------------------*/
 470 
  * @{
471 
/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
 471 
  */
472 
  * @{
 472 
 
473 
  */
 473 
/** @defgroup RCC_LL_EF_HSE HSE
474 
 
 474 
  * @{
475 
/** @defgroup RCC_LL_EF_HSE HSE
 475 
  */
476 
  * @{
 476 
 
477 
  */
 477 
/**
478 
 
 478 
  * @brief  Enable the Clock Security System.
479 
/**
 479 
  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
480 
  * @brief  Enable the Clock Security System.
 480 
  * @retval None
481 
  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
 481 
  */
482 
  * @retval None
 482 
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
483 
  */
 483 
{
484 
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
 484 
  SET_BIT(RCC->CR, RCC_CR_CSSON);
485 
{
 485 
}
486 
  SET_BIT(RCC->CR, RCC_CR_CSSON);
 486 
 
487 
}
 487 
/**
488 
 
 488 
  * @brief  Disable the Clock Security System.
489 
/**
 489 
  * @note Cannot be disabled in HSE is ready (only by hardware)
490 
  * @brief  Disable the Clock Security System.
 490 
  * @rmtoll CR           CSSON         LL_RCC_HSE_DisableCSS
491 
  * @note Cannot be disabled in HSE is ready (only by hardware)
 491 
  * @retval None
492 
  * @rmtoll CR           CSSON         LL_RCC_HSE_DisableCSS
 492 
  */
493 
  * @retval None
 493 
__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
494 
  */
 494 
{
495 
__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
 495 
  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
496 
{
 496 
}
497 
  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
 497 
 
498 
}
 498 
/**
499 
 
 499 
  * @brief  Enable HSE external oscillator (HSE Bypass)
500 
/**
 500 
  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
501 
  * @brief  Enable HSE external oscillator (HSE Bypass)
 501 
  * @retval None
502 
  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
 502 
  */
503 
  * @retval None
 503 
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
504 
  */
 504 
{
505 
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
 505 
  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
506 
{
 506 
}
507 
  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
 507 
 
508 
}
 508 
/**
509 
 
 509 
  * @brief  Disable HSE external oscillator (HSE Bypass)
510 
/**
 510 
  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
511 
  * @brief  Disable HSE external oscillator (HSE Bypass)
 511 
  * @retval None
512 
  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
 512 
  */
513 
  * @retval None
 513 
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
514 
  */
 514 
{
515 
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
 515 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
516 
{
 516 
}
517 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
 517 
 
518 
}
 518 
/**
519 
 
 519 
  * @brief  Enable HSE crystal oscillator (HSE ON)
520 
/**
 520 
  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
521 
  * @brief  Enable HSE crystal oscillator (HSE ON)
 521 
  * @retval None
522 
  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
 522 
  */
523 
  * @retval None
 523 
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
524 
  */
 524 
{
525 
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
 525 
  SET_BIT(RCC->CR, RCC_CR_HSEON);
526 
{
 526 
}
527 
  SET_BIT(RCC->CR, RCC_CR_HSEON);
 527 
 
528 
}
 528 
/**
529 
 
 529 
  * @brief  Disable HSE crystal oscillator (HSE ON)
530 
/**
 530 
  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
531 
  * @brief  Disable HSE crystal oscillator (HSE ON)
 531 
  * @retval None
532 
  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
 532 
  */
533 
  * @retval None
 533 
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
534 
  */
 534 
{
535 
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
 535 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
536 
{
 536 
}
537 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
 537 
 
538 
}
 538 
/**
539 
 
 539 
  * @brief  Check if HSE oscillator Ready
540 
/**
 540 
  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
541 
  * @brief  Check if HSE oscillator Ready
 541 
  * @retval State of bit (1 or 0).
542 
  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
 542 
  */
543 
  * @retval State of bit (1 or 0).
 543 
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
544 
  */
 544 
{
545 
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
 545 
  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
546 
{
 546 
}
547 
  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
 547 
 
548 
}
 548 
/**
549 
 
 549 
  * @brief  Configure the RTC prescaler (divider)
550 
/**
 550 
  * @rmtoll CR           RTCPRE        LL_RCC_SetRTC_HSEPrescaler
551 
  * @brief  Configure the RTC prescaler (divider)
 551 
  * @param  Div This parameter can be one of the following values:
552 
  * @rmtoll CR           RTCPRE        LL_RCC_SetRTC_HSEPrescaler
 552 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
553 
  * @param  Div This parameter can be one of the following values:
 553 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
554 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
 554 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
555 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
 555 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
556 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
 556 
  * @retval None
557 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
 557 
  */
558 
  * @retval None
 558 
__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
559 
  */
 559 
{
560 
__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
 560 
  MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
561 
{
 561 
}
562 
  MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
 562 
 
563 
}
 563 
/**
564 
 
 564 
  * @brief  Get the RTC divider (prescaler)
565 
/**
 565 
  * @rmtoll CR           RTCPRE        LL_RCC_GetRTC_HSEPrescaler
566 
  * @brief  Get the RTC divider (prescaler)
 566 
  * @retval Returned value can be one of the following values:
567 
  * @rmtoll CR           RTCPRE        LL_RCC_GetRTC_HSEPrescaler
 567 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
568 
  * @retval Returned value can be one of the following values:
 568 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
569 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
 569 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
570 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
 570 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
571 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
 571 
  */
572 
  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
 572 
__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
573 
  */
 573 
{
574 
__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
 574 
  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
575 
{
 575 
}
576 
  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
 576 
 
577 
}
 577 
/**
578 
 
 578 
  * @}
579 
/**
 579 
  */
580 
  * @}
 580 
 
581 
  */
 581 
/** @defgroup RCC_LL_EF_HSI HSI
582 
 
 582 
  * @{
583 
/** @defgroup RCC_LL_EF_HSI HSI
 583 
  */
584 
  * @{
 584 
 
585 
  */
 585 
/**
586 
 
 586 
  * @brief  Enable HSI oscillator
587 
/**
 587 
  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
588 
  * @brief  Enable HSI oscillator
 588 
  * @retval None
589 
  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
 589 
  */
590 
  * @retval None
 590 
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
591 
  */
 591 
{
592 
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
 592 
  SET_BIT(RCC->CR, RCC_CR_HSION);
593 
{
 593 
}
594 
  SET_BIT(RCC->CR, RCC_CR_HSION);
 594 
 
595 
}
 595 
/**
596 
 
 596 
  * @brief  Disable HSI oscillator
597 
/**
 597 
  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
598 
  * @brief  Disable HSI oscillator
 598 
  * @retval None
599 
  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
 599 
  */
600 
  * @retval None
 600 
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
601 
  */
 601 
{
602 
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
 602 
  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
603 
{
 603 
}
604 
  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
 604 
 
605 
}
 605 
/**
606 
 
 606 
  * @brief  Check if HSI clock is ready
607 
/**
 607 
  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
608 
  * @brief  Check if HSI clock is ready
 608 
  * @retval State of bit (1 or 0).
609 
  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
 609 
  */
610 
  * @retval State of bit (1 or 0).
 610 
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
611 
  */
 611 
{
612 
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
 612 
  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
613 
{
 613 
}
614 
  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
 614 
 
615 
}
 615 
/**
616 
 
 616 
  * @brief  Get HSI Calibration value
617 
/**
 617 
  * @note When HSITRIM is written, HSICAL is updated with the sum of
618 
  * @brief  Get HSI Calibration value
 618 
  *       HSITRIM and the factory trim value
619 
  * @note When HSITRIM is written, HSICAL is updated with the sum of
 619 
  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
620 
  *       HSITRIM and the factory trim value
 620 
  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
621 
  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
 621 
  */
622 
  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
 622 
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
623 
  */
 623 
{
624 
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
 624 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
625 
{
 625 
}
626 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
 626 
 
627 
}
 627 
/**
628 
 
 628 
  * @brief  Set HSI Calibration trimming
629 
/**
 629 
  * @note user-programmable trimming value that is added to the HSICAL
630 
  * @brief  Set HSI Calibration trimming
 630 
  * @note Default value is 16, which, when added to the HSICAL value,
631 
  * @note user-programmable trimming value that is added to the HSICAL
 631 
  *       should trim the HSI to 16 MHz +/- 1 %
632 
  * @note Default value is 16, which, when added to the HSICAL value,
 632 
  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
633 
  *       should trim the HSI to 16 MHz +/- 1 %
 633 
  * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
634 
  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
 634 
  * @retval None
635 
  * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
 635 
  */
636 
  * @retval None
 636 
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
637 
  */
 637 
{
638 
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
 638 
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
639 
{
 639 
}
640 
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
 640 
 
641 
}
 641 
/**
642 
 
 642 
  * @brief  Get HSI Calibration trimming
643 
/**
 643 
  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
644 
  * @brief  Get HSI Calibration trimming
 644 
  * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
645 
  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
 645 
  */
646 
  * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
 646 
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
647 
  */
 647 
{
648 
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
 648 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
649 
{
 649 
}
650 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
 650 
 
651 
}
 651 
/**
652 
 
 652 
  * @}
653 
/**
 653 
  */
654 
  * @}
 654 
 
655 
  */
 655 
/** @defgroup RCC_LL_EF_LSE LSE
656 
 
 656 
  * @{
657 
/** @defgroup RCC_LL_EF_LSE LSE
 657 
  */
658 
  * @{
 658 
 
659 
  */
 659 
/**
660 
 
 660 
  * @brief  Enable  Low Speed External (LSE) crystal.
661 
/**
 661 
  * @rmtoll CSR         LSEON         LL_RCC_LSE_Enable
662 
  * @brief  Enable  Low Speed External (LSE) crystal.
 662 
  * @retval None
663 
  * @rmtoll CSR         LSEON         LL_RCC_LSE_Enable
 663 
  */
664 
  * @retval None
 664 
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
665 
  */
 665 
{
666 
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
 666 
  SET_BIT(RCC->CSR, RCC_CSR_LSEON);
667 
{
 667 
}
668 
  SET_BIT(RCC->CSR, RCC_CSR_LSEON);
 668 
 
669 
}
 669 
/**
670 
 
 670 
  * @brief  Disable  Low Speed External (LSE) crystal.
671 
/**
 671 
  * @rmtoll CSR         LSEON         LL_RCC_LSE_Disable
672 
  * @brief  Disable  Low Speed External (LSE) crystal.
 672 
  * @retval None
673 
  * @rmtoll CSR         LSEON         LL_RCC_LSE_Disable
 673 
  */
674 
  * @retval None
 674 
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
675 
  */
 675 
{
676 
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
 676 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
677 
{
 677 
}
678 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
 678 
 
679 
}
 679 
/**
680 
 
 680 
  * @brief  Enable external clock source (LSE bypass).
681 
/**
 681 
  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_EnableBypass
682 
  * @brief  Enable external clock source (LSE bypass).
 682 
  * @retval None
683 
  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_EnableBypass
 683 
  */
684 
  * @retval None
 684 
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
685 
  */
 685 
{
686 
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
 686 
  SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
687 
{
 687 
}
688 
  SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
 688 
 
689 
}
 689 
/**
690 
 
 690 
  * @brief  Disable external clock source (LSE bypass).
691 
/**
 691 
  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_DisableBypass
692 
  * @brief  Disable external clock source (LSE bypass).
 692 
  * @retval None
693 
  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_DisableBypass
 693 
  */
694 
  * @retval None
 694 
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
695 
  */
 695 
{
696 
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
 696 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
697 
{
 697 
}
698 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
 698 
 
699 
}
 699 
#if defined(RCC_LSECSS_SUPPORT)
700 
 
 700 
/**
701 
#if defined(RCC_LSECSS_SUPPORT)
 701 
  * @brief  Enable Clock security system on LSE.
702 
/**
 702 
  * @rmtoll CSR         LSECSSON      LL_RCC_LSE_EnableCSS
703 
  * @brief  Enable Clock security system on LSE.
 703 
  * @retval None
704 
  * @rmtoll CSR         LSECSSON      LL_RCC_LSE_EnableCSS
 704 
  */
705 
  * @retval None
 705 
__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
706 
  */
 706 
{
707 
__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
 707 
  SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
708 
{
 708 
}
709 
  SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
 709 
 
710 
}
 710 
/**
711 
 
 711 
  * @brief  Disable Clock security system on LSE.
712 
/**
 712 
  * @note   Clock security system can be disabled only after a LSE
713 
  * @brief  Disable Clock security system on LSE.
 713 
  *         failure detection. In that case it MUST be disabled by software.
714 
  * @note   Clock security system can be disabled only after a LSE
 714 
  * @rmtoll CSR          LSECSSON      LL_RCC_LSE_DisableCSS
715 
  *         failure detection. In that case it MUST be disabled by software.
 715 
  * @retval None
716 
  * @rmtoll CSR          LSECSSON      LL_RCC_LSE_DisableCSS
 716 
  */
717 
  * @retval None
 717 
__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
718 
  */
 718 
{
719 
__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
 719 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
720 
{
 720 
}
721 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
 721 
 
722 
}
 722 
#endif /* RCC_LSECSS_SUPPORT */
723 
 
 723 
/**
724 
#endif /* RCC_LSECSS_SUPPORT */
 724 
  * @brief  Check if LSE oscillator Ready
725 
/**
 725 
  * @rmtoll CSR         LSERDY        LL_RCC_LSE_IsReady
726 
  * @brief  Check if LSE oscillator Ready
 726 
  * @retval State of bit (1 or 0).
727 
  * @rmtoll CSR         LSERDY        LL_RCC_LSE_IsReady
 727 
  */
728 
  * @retval State of bit (1 or 0).
 728 
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
729 
  */
 729 
{
730 
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
 730 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
731 
{
 731 
}
732 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
 732 
 
733 
}
 733 
#if defined(RCC_LSECSS_SUPPORT)
734 
 
 734 
/**
735 
#if defined(RCC_LSECSS_SUPPORT)
 735 
  * @brief  Check if CSS on LSE failure Detection
736 
/**
 736 
  * @rmtoll CSR         LSECSSD       LL_RCC_LSE_IsCSSDetected
737 
  * @brief  Check if CSS on LSE failure Detection
 737 
  * @retval State of bit (1 or 0).
738 
  * @rmtoll CSR         LSECSSD       LL_RCC_LSE_IsCSSDetected
 738 
  */
739 
  * @retval State of bit (1 or 0).
 739 
__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
740 
  */
 740 
{
741 
__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
 741 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL);
742 
{
 742 
}
743 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL);
 743 
 
744 
}
 744 
#endif /* RCC_LSECSS_SUPPORT */
745 
 
 745 
/**
746 
#endif /* RCC_LSECSS_SUPPORT */
 746 
  * @}
747 
/**
 747 
  */
748 
  * @}
 748 
 
749 
  */
 749 
/** @defgroup RCC_LL_EF_LSI LSI
750 
 
 750 
  * @{
751 
/** @defgroup RCC_LL_EF_LSI LSI
 751 
  */
752 
  * @{
 752 
 
753 
  */
 753 
/**
754 
 
 754 
  * @brief  Enable LSI Oscillator
755 
/**
 755 
  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
756 
  * @brief  Enable LSI Oscillator
 756 
  * @retval None
757 
  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
 757 
  */
758 
  * @retval None
 758 
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
759 
  */
 759 
{
760 
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
 760 
  SET_BIT(RCC->CSR, RCC_CSR_LSION);
761 
{
 761 
}
762 
  SET_BIT(RCC->CSR, RCC_CSR_LSION);
 762 
 
763 
}
 763 
/**
764 
 
 764 
  * @brief  Disable LSI Oscillator
765 
/**
 765 
  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
766 
  * @brief  Disable LSI Oscillator
 766 
  * @retval None
767 
  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
 767 
  */
768 
  * @retval None
 768 
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
769 
  */
 769 
{
770 
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
 770 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
771 
{
 771 
}
772 
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
 772 
 
773 
}
 773 
/**
774 
 
 774 
  * @brief  Check if LSI is Ready
775 
/**
 775 
  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
776 
  * @brief  Check if LSI is Ready
 776 
  * @retval State of bit (1 or 0).
777 
  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
 777 
  */
778 
  * @retval State of bit (1 or 0).
 778 
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
779 
  */
 779 
{
780 
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
 780 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
781 
{
 781 
}
782 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
 782 
 
783 
}
 783 
/**
784 
 
 784 
  * @}
785 
/**
 785 
  */
786 
  * @}
 786 
 
787 
  */
 787 
/** @defgroup RCC_LL_EF_MSI MSI
788 
 
 788 
  * @{
789 
/** @defgroup RCC_LL_EF_MSI MSI
 789 
  */
790 
  * @{
 790 
 
791 
  */
 791 
/**
792 
 
 792 
  * @brief  Enable MSI oscillator
793 
/**
 793 
  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
794 
  * @brief  Enable MSI oscillator
 794 
  * @retval None
795 
  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
 795 
  */
796 
  * @retval None
 796 
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
797 
  */
 797 
{
798 
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
 798 
  SET_BIT(RCC->CR, RCC_CR_MSION);
799 
{
 799 
}
800 
  SET_BIT(RCC->CR, RCC_CR_MSION);
 800 
 
801 
}
 801 
/**
802 
 
 802 
  * @brief  Disable MSI oscillator
803 
/**
 803 
  * @rmtoll CR           MSION         LL_RCC_MSI_Disable
804 
  * @brief  Disable MSI oscillator
 804 
  * @retval None
805 
  * @rmtoll CR           MSION         LL_RCC_MSI_Disable
 805 
  */
806 
  * @retval None
 806 
__STATIC_INLINE void LL_RCC_MSI_Disable(void)
807 
  */
 807 
{
808 
__STATIC_INLINE void LL_RCC_MSI_Disable(void)
 808 
  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
809 
{
 809 
}
810 
  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
 810 
 
811 
}
 811 
/**
812 
 
 812 
  * @brief  Check if MSI oscillator Ready
813 
/**
 813 
  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
814 
  * @brief  Check if MSI oscillator Ready
 814 
  * @retval State of bit (1 or 0).
815 
  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
 815 
  */
816 
  * @retval State of bit (1 or 0).
 816 
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
817 
  */
 817 
{
818 
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
 818 
  return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
819 
{
 819 
}
820 
  return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
 820 
 
821 
}
 821 
/**
822 
 
 822 
  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
823 
/**
 823 
  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_SetRange
824 
  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
 824 
  * @param  Range This parameter can be one of the following values:
825 
  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_SetRange
 825 
  *         @arg @ref LL_RCC_MSIRANGE_0
826 
  * @param  Range This parameter can be one of the following values:
 826 
  *         @arg @ref LL_RCC_MSIRANGE_1
827 
  *         @arg @ref LL_RCC_MSIRANGE_0
 827 
  *         @arg @ref LL_RCC_MSIRANGE_2
828 
  *         @arg @ref LL_RCC_MSIRANGE_1
 828 
  *         @arg @ref LL_RCC_MSIRANGE_3
829 
  *         @arg @ref LL_RCC_MSIRANGE_2
 829 
  *         @arg @ref LL_RCC_MSIRANGE_4
830 
  *         @arg @ref LL_RCC_MSIRANGE_3
 830 
  *         @arg @ref LL_RCC_MSIRANGE_5
831 
  *         @arg @ref LL_RCC_MSIRANGE_4
 831 
  *         @arg @ref LL_RCC_MSIRANGE_6
832 
  *         @arg @ref LL_RCC_MSIRANGE_5
 832 
  * @retval None
833 
  *         @arg @ref LL_RCC_MSIRANGE_6
 833 
  */
834 
  * @retval None
 834 
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
835 
  */
 835 
{
836 
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
 836 
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
837 
{
 837 
}
838 
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
 838 
 
839 
}
 839 
/**
840 
 
 840 
  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
841 
/**
 841 
  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_GetRange
842 
  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
 842 
  * @retval Returned value can be one of the following values:
843 
  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_GetRange
 843 
  *         @arg @ref LL_RCC_MSIRANGE_0
844 
  * @retval Returned value can be one of the following values:
 844 
  *         @arg @ref LL_RCC_MSIRANGE_1
845 
  *         @arg @ref LL_RCC_MSIRANGE_0
 845 
  *         @arg @ref LL_RCC_MSIRANGE_2
846 
  *         @arg @ref LL_RCC_MSIRANGE_1
 846 
  *         @arg @ref LL_RCC_MSIRANGE_3
847 
  *         @arg @ref LL_RCC_MSIRANGE_2
 847 
  *         @arg @ref LL_RCC_MSIRANGE_4
848 
  *         @arg @ref LL_RCC_MSIRANGE_3
 848 
  *         @arg @ref LL_RCC_MSIRANGE_5
849 
  *         @arg @ref LL_RCC_MSIRANGE_4
 849 
  *         @arg @ref LL_RCC_MSIRANGE_6
850 
  *         @arg @ref LL_RCC_MSIRANGE_5
 850 
  */
851 
  *         @arg @ref LL_RCC_MSIRANGE_6
 851 
__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
852 
  */
 852 
{
853 
__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
 853 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
854 
{
 854 
}
855 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
 855 
 
856 
}
 856 
/**
857 
 
 857 
  * @brief  Get MSI Calibration value
858 
/**
 858 
  * @note When MSITRIM is written, MSICAL is updated with the sum of
859 
  * @brief  Get MSI Calibration value
 859 
  *       MSITRIM and the factory trim value
860 
  * @note When MSITRIM is written, MSICAL is updated with the sum of
 860 
  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
861 
  *       MSITRIM and the factory trim value
 861 
  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
862 
  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
 862 
  */
863 
  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
 863 
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
864 
  */
 864 
{
865 
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
 865 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
866 
{
 866 
}
867 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
 867 
 
868 
}
 868 
/**
869 
 
 869 
  * @brief  Set MSI Calibration trimming
870 
/**
 870 
  * @note user-programmable trimming value that is added to the MSICAL
871 
  * @brief  Set MSI Calibration trimming
 871 
  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
872 
  * @note user-programmable trimming value that is added to the MSICAL
 872 
  * @param  Value between Min_Data = 0x00 and Max_Data = 0xFF
873 
  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
 873 
  * @retval None
874 
  * @param  Value between Min_Data = 0x00 and Max_Data = 0xFF
 874 
  */
875 
  * @retval None
 875 
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
876 
  */
 876 
{
877 
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
 877 
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
878 
{
 878 
}
879 
  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
 879 
 
880 
}
 880 
/**
881 
 
 881 
  * @brief  Get MSI Calibration trimming
882 
/**
 882 
  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
883 
  * @brief  Get MSI Calibration trimming
 883 
  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
884 
  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
 884 
  */
885 
  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
 885 
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
886 
  */
 886 
{
887 
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
 887 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
888 
{
 888 
}
889 
  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
 889 
 
890 
}
 890 
/**
891 
 
 891 
  * @}
892 
/**
 892 
  */
893 
  * @}
 893 
 
894 
  */
 894 
/** @defgroup RCC_LL_EF_System System
895 
 
 895 
  * @{
896 
/** @defgroup RCC_LL_EF_System System
 896 
  */
897 
  * @{
 897 
 
898 
  */
 898 
/**
899 
 
 899 
  * @brief  Configure the system clock source
900 
/**
 900 
  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
901 
  * @brief  Configure the system clock source
 901 
  * @param  Source This parameter can be one of the following values:
902 
  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
 902 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
903 
  * @param  Source This parameter can be one of the following values:
 903 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
904 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
 904 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
905 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
 905 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
906 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
 906 
  * @retval None
907 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
 907 
  */
908 
  * @retval None
 908 
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
909 
  */
 909 
{
910 
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
 910 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
911 
{
 911 
}
912 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
 912 
 
913 
}
 913 
/**
914 
 
 914 
  * @brief  Get the system clock source
915 
/**
 915 
  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
916 
  * @brief  Get the system clock source
 916 
  * @retval Returned value can be one of the following values:
917 
  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
 917 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
918 
  * @retval Returned value can be one of the following values:
 918 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
919 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
 919 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
920 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
 920 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
921 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
 921 
  */
922 
  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
 922 
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
923 
  */
 923 
{
924 
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
 924 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
925 
{
 925 
}
926 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
 926 
 
927 
}
 927 
/**
928 
 
 928 
  * @brief  Set AHB prescaler
929 
/**
 929 
  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
930 
  * @brief  Set AHB prescaler
 930 
  * @param  Prescaler This parameter can be one of the following values:
931 
  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
 931 
  *         @arg @ref LL_RCC_SYSCLK_DIV_1
932 
  * @param  Prescaler This parameter can be one of the following values:
 932 
  *         @arg @ref LL_RCC_SYSCLK_DIV_2
933 
  *         @arg @ref LL_RCC_SYSCLK_DIV_1
 933 
  *         @arg @ref LL_RCC_SYSCLK_DIV_4
934 
  *         @arg @ref LL_RCC_SYSCLK_DIV_2
 934 
  *         @arg @ref LL_RCC_SYSCLK_DIV_8
935 
  *         @arg @ref LL_RCC_SYSCLK_DIV_4
 935 
  *         @arg @ref LL_RCC_SYSCLK_DIV_16
936 
  *         @arg @ref LL_RCC_SYSCLK_DIV_8
 936 
  *         @arg @ref LL_RCC_SYSCLK_DIV_64
937 
  *         @arg @ref LL_RCC_SYSCLK_DIV_16
 937 
  *         @arg @ref LL_RCC_SYSCLK_DIV_128
938 
  *         @arg @ref LL_RCC_SYSCLK_DIV_64
 938 
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
939 
  *         @arg @ref LL_RCC_SYSCLK_DIV_128
 939 
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
940 
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
 940 
  * @retval None
941 
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
 941 
  */
942 
  * @retval None
 942 
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
943 
  */
 943 
{
944 
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
 944 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
945 
{
 945 
}
946 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
 946 
 
947 
}
 947 
/**
948 
 
 948 
  * @brief  Set APB1 prescaler
949 
/**
 949 
  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
950 
  * @brief  Set APB1 prescaler
 950 
  * @param  Prescaler This parameter can be one of the following values:
951 
  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
 951 
  *         @arg @ref LL_RCC_APB1_DIV_1
952 
  * @param  Prescaler This parameter can be one of the following values:
 952 
  *         @arg @ref LL_RCC_APB1_DIV_2
953 
  *         @arg @ref LL_RCC_APB1_DIV_1
 953 
  *         @arg @ref LL_RCC_APB1_DIV_4
954 
  *         @arg @ref LL_RCC_APB1_DIV_2
 954 
  *         @arg @ref LL_RCC_APB1_DIV_8
955 
  *         @arg @ref LL_RCC_APB1_DIV_4
 955 
  *         @arg @ref LL_RCC_APB1_DIV_16
956 
  *         @arg @ref LL_RCC_APB1_DIV_8
 956 
  * @retval None
957 
  *         @arg @ref LL_RCC_APB1_DIV_16
 957 
  */
958 
  * @retval None
 958 
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
959 
  */
 959 
{
960 
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
 960 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
961 
{
 961 
}
962 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
 962 
 
963 
}
 963 
/**
964 
 
 964 
  * @brief  Set APB2 prescaler
965 
/**
 965 
  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
966 
  * @brief  Set APB2 prescaler
 966 
  * @param  Prescaler This parameter can be one of the following values:
967 
  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
 967 
  *         @arg @ref LL_RCC_APB2_DIV_1
968 
  * @param  Prescaler This parameter can be one of the following values:
 968 
  *         @arg @ref LL_RCC_APB2_DIV_2
969 
  *         @arg @ref LL_RCC_APB2_DIV_1
 969 
  *         @arg @ref LL_RCC_APB2_DIV_4
970 
  *         @arg @ref LL_RCC_APB2_DIV_2
 970 
  *         @arg @ref LL_RCC_APB2_DIV_8
971 
  *         @arg @ref LL_RCC_APB2_DIV_4
 971 
  *         @arg @ref LL_RCC_APB2_DIV_16
972 
  *         @arg @ref LL_RCC_APB2_DIV_8
 972 
  * @retval None
973 
  *         @arg @ref LL_RCC_APB2_DIV_16
 973 
  */
974 
  * @retval None
 974 
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
975 
  */
 975 
{
976 
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
 976 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
977 
{
 977 
}
978 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
 978 
 
979 
}
 979 
/**
980 
 
 980 
  * @brief  Get AHB prescaler
981 
/**
 981 
  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
982 
  * @brief  Get AHB prescaler
 982 
  * @retval Returned value can be one of the following values:
983 
  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
 983 
  *         @arg @ref LL_RCC_SYSCLK_DIV_1
984 
  * @retval Returned value can be one of the following values:
 984 
  *         @arg @ref LL_RCC_SYSCLK_DIV_2
985 
  *         @arg @ref LL_RCC_SYSCLK_DIV_1
 985 
  *         @arg @ref LL_RCC_SYSCLK_DIV_4
986 
  *         @arg @ref LL_RCC_SYSCLK_DIV_2
 986 
  *         @arg @ref LL_RCC_SYSCLK_DIV_8
987 
  *         @arg @ref LL_RCC_SYSCLK_DIV_4
 987 
  *         @arg @ref LL_RCC_SYSCLK_DIV_16
988 
  *         @arg @ref LL_RCC_SYSCLK_DIV_8
 988 
  *         @arg @ref LL_RCC_SYSCLK_DIV_64
989 
  *         @arg @ref LL_RCC_SYSCLK_DIV_16
 989 
  *         @arg @ref LL_RCC_SYSCLK_DIV_128
990 
  *         @arg @ref LL_RCC_SYSCLK_DIV_64
 990 
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
991 
  *         @arg @ref LL_RCC_SYSCLK_DIV_128
 991 
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
992 
  *         @arg @ref LL_RCC_SYSCLK_DIV_256
 992 
  */
993 
  *         @arg @ref LL_RCC_SYSCLK_DIV_512
 993 
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
994 
  */
 994 
{
995 
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
 995 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
996 
{
 996 
}
997 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
 997 
 
998 
}
 998 
/**
999 
 
 999 
  * @brief  Get APB1 prescaler
1000 
/**
 1000 
  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
1001 
  * @brief  Get APB1 prescaler
 1001 
  * @retval Returned value can be one of the following values:
1002 
  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
 1002 
  *         @arg @ref LL_RCC_APB1_DIV_1
1003 
  * @retval Returned value can be one of the following values:
 1003 
  *         @arg @ref LL_RCC_APB1_DIV_2
1004 
  *         @arg @ref LL_RCC_APB1_DIV_1
 1004 
  *         @arg @ref LL_RCC_APB1_DIV_4
1005 
  *         @arg @ref LL_RCC_APB1_DIV_2
 1005 
  *         @arg @ref LL_RCC_APB1_DIV_8
1006 
  *         @arg @ref LL_RCC_APB1_DIV_4
 1006 
  *         @arg @ref LL_RCC_APB1_DIV_16
1007 
  *         @arg @ref LL_RCC_APB1_DIV_8
 1007 
  */
1008 
  *         @arg @ref LL_RCC_APB1_DIV_16
 1008 
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1009 
  */
 1009 
{
1010 
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
 1010 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1011 
{
 1011 
}
1012 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
 1012 
 
1013 
}
 1013 
/**
1014 
 
 1014 
  * @brief  Get APB2 prescaler
1015 
/**
 1015 
  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
1016 
  * @brief  Get APB2 prescaler
 1016 
  * @retval Returned value can be one of the following values:
1017 
  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
 1017 
  *         @arg @ref LL_RCC_APB2_DIV_1
1018 
  * @retval Returned value can be one of the following values:
 1018 
  *         @arg @ref LL_RCC_APB2_DIV_2
1019 
  *         @arg @ref LL_RCC_APB2_DIV_1
 1019 
  *         @arg @ref LL_RCC_APB2_DIV_4
1020 
  *         @arg @ref LL_RCC_APB2_DIV_2
 1020 
  *         @arg @ref LL_RCC_APB2_DIV_8
1021 
  *         @arg @ref LL_RCC_APB2_DIV_4
 1021 
  *         @arg @ref LL_RCC_APB2_DIV_16
1022 
  *         @arg @ref LL_RCC_APB2_DIV_8
 1022 
  */
1023 
  *         @arg @ref LL_RCC_APB2_DIV_16
 1023 
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1024 
  */
 1024 
{
1025 
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
 1025 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1026 
{
 1026 
}
1027 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
 1027 
 
1028 
}
 1028 
/**
1029 
 
 1029 
  * @}
1030 
/**
 1030 
  */
1031 
  * @}
 1031 
 
1032 
  */
 1032 
/** @defgroup RCC_LL_EF_MCO MCO
1033 
 
 1033 
  * @{
1034 
/** @defgroup RCC_LL_EF_MCO MCO
 1034 
  */
1035 
  * @{
 1035 
 
1036 
  */
 1036 
/**
1037 
 
 1037 
  * @brief  Configure MCOx
1038 
/**
 1038 
  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
1039 
  * @brief  Configure MCOx
 1039 
  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
1040 
  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
 1040 
  * @param  MCOxSource This parameter can be one of the following values:
1041 
  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
 1041 
  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1042 
  * @param  MCOxSource This parameter can be one of the following values:
 1042 
  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1043 
  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
 1043 
  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
1044 
  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
 1044 
  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
1045 
  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
 1045 
  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
1046 
  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
 1046 
  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1047 
  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
 1047 
  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
1048 
  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
 1048 
  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
1049 
  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
 1049 
  * @param  MCOxPrescaler This parameter can be one of the following values:
1050 
  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
 1050 
  *         @arg @ref LL_RCC_MCO1_DIV_1
1051 
  * @param  MCOxPrescaler This parameter can be one of the following values:
 1051 
  *         @arg @ref LL_RCC_MCO1_DIV_2
1052 
  *         @arg @ref LL_RCC_MCO1_DIV_1
 1052 
  *         @arg @ref LL_RCC_MCO1_DIV_4
1053 
  *         @arg @ref LL_RCC_MCO1_DIV_2
 1053 
  *         @arg @ref LL_RCC_MCO1_DIV_8
1054 
  *         @arg @ref LL_RCC_MCO1_DIV_4
 1054 
  *         @arg @ref LL_RCC_MCO1_DIV_16
1055 
  *         @arg @ref LL_RCC_MCO1_DIV_8
 1055 
  * @retval None
1056 
  *         @arg @ref LL_RCC_MCO1_DIV_16
 1056 
  */
1057 
  * @retval None
 1057 
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1058 
  */
 1058 
{
1059 
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
 1059 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1060 
{
 1060 
}
1061 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
 1061 
 
1062 
}
 1062 
/**
1063 
 
 1063 
  * @}
1064 
/**
 1064 
  */
1065 
  * @}
 1065 
 
1066 
  */
 1066 
 
1067 
 
 1067 
 
1068 
 
 1068 
/** @defgroup RCC_LL_EF_RTC RTC
1069 
 
 1069 
  * @{
1070 
/** @defgroup RCC_LL_EF_RTC RTC
 1070 
  */
1071 
  * @{
 1071 
 
1072 
  */
 1072 
/**
1073 
 
 1073 
  * @brief  Set RTC Clock Source
1074 
/**
 1074 
  * @note Once the RTC clock source has been selected, it cannot be changed any more unless
1075 
  * @brief  Set RTC Clock Source
 1075 
  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1076 
  * @note Once the RTC clock source has been selected, it cannot be changed any more unless
 1076 
  *       set). The RTCRST bit can be used to reset them.
1077 
  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
 1077 
  * @rmtoll CSR         RTCSEL        LL_RCC_SetRTCClockSource
1078 
  *       set). The RTCRST bit can be used to reset them.
 1078 
  * @param  Source This parameter can be one of the following values:
1079 
  * @rmtoll CSR         RTCSEL        LL_RCC_SetRTCClockSource
 1079 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1080 
  * @param  Source This parameter can be one of the following values:
 1080 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1081 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
 1081 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1082 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
 1082 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1083 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
 1083 
  * @retval None
1084 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
 1084 
  */
1085 
  * @retval None
 1085 
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1086 
  */
 1086 
{
1087 
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
 1087 
  MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
1088 
{
 1088 
}
1089 
  MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
 1089 
 
1090 
}
 1090 
/**
1091 
 
 1091 
  * @brief  Get RTC Clock Source
1092 
/**
 1092 
  * @rmtoll CSR         RTCSEL        LL_RCC_GetRTCClockSource
1093 
  * @brief  Get RTC Clock Source
 1093 
  * @retval Returned value can be one of the following values:
1094 
  * @rmtoll CSR         RTCSEL        LL_RCC_GetRTCClockSource
 1094 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1095 
  * @retval Returned value can be one of the following values:
 1095 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1096 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
 1096 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1097 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
 1097 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1098 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
 1098 
  */
1099 
  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
 1099 
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1100 
  */
 1100 
{
1101 
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
 1101 
  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
1102 
{
 1102 
}
1103 
  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
 1103 
 
1104 
}
 1104 
/**
1105 
 
 1105 
  * @brief  Enable RTC
1106 
/**
 1106 
  * @rmtoll CSR         RTCEN         LL_RCC_EnableRTC
1107 
  * @brief  Enable RTC
 1107 
  * @retval None
1108 
  * @rmtoll CSR         RTCEN         LL_RCC_EnableRTC
 1108 
  */
1109 
  * @retval None
 1109 
__STATIC_INLINE void LL_RCC_EnableRTC(void)
1110 
  */
 1110 
{
1111 
__STATIC_INLINE void LL_RCC_EnableRTC(void)
 1111 
  SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
1112 
{
 1112 
}
1113 
  SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
 1113 
 
1114 
}
 1114 
/**
1115 
 
 1115 
  * @brief  Disable RTC
1116 
/**
 1116 
  * @rmtoll CSR         RTCEN         LL_RCC_DisableRTC
1117 
  * @brief  Disable RTC
 1117 
  * @retval None
1118 
  * @rmtoll CSR         RTCEN         LL_RCC_DisableRTC
 1118 
  */
1119 
  * @retval None
 1119 
__STATIC_INLINE void LL_RCC_DisableRTC(void)
1120 
  */
 1120 
{
1121 
__STATIC_INLINE void LL_RCC_DisableRTC(void)
 1121 
  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
1122 
{
 1122 
}
1123 
  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
 1123 
 
1124 
}
 1124 
/**
1125 
 
 1125 
  * @brief  Check if RTC has been enabled or not
1126 
/**
 1126 
  * @rmtoll CSR         RTCEN         LL_RCC_IsEnabledRTC
1127 
  * @brief  Check if RTC has been enabled or not
 1127 
  * @retval State of bit (1 or 0).
1128 
  * @rmtoll CSR         RTCEN         LL_RCC_IsEnabledRTC
 1128 
  */
1129 
  * @retval State of bit (1 or 0).
 1129 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1130 
  */
 1130 
{
1131 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
 1131 
  return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL);
1132 
{
 1132 
}
1133 
  return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL);
 1133 
 
1134 
}
 1134 
/**
1135 
 
 1135 
  * @brief  Force the Backup domain reset
1136 
/**
 1136 
  * @rmtoll CSR         RTCRST         LL_RCC_ForceBackupDomainReset
1137 
  * @brief  Force the Backup domain reset
 1137 
  * @retval None
1138 
  * @rmtoll CSR         RTCRST         LL_RCC_ForceBackupDomainReset
 1138 
  */
1139 
  * @retval None
 1139 
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1140 
  */
 1140 
{
1141 
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
 1141 
  SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
1142 
{
 1142 
}
1143 
  SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
 1143 
 
1144 
}
 1144 
/**
1145 
 
 1145 
  * @brief  Release the Backup domain reset
1146 
/**
 1146 
  * @rmtoll CSR         RTCRST         LL_RCC_ReleaseBackupDomainReset
1147 
  * @brief  Release the Backup domain reset
 1147 
  * @retval None
1148 
  * @rmtoll CSR         RTCRST         LL_RCC_ReleaseBackupDomainReset
 1148 
  */
1149 
  * @retval None
 1149 
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1150 
  */
 1150 
{
1151 
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
 1151 
  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
1152 
{
 1152 
}
1153 
  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
 1153 
 
1154 
}
 1154 
/**
1155 
 
 1155 
  * @}
1156 
/**
 1156 
  */
1157 
  * @}
 1157 
 
1158 
  */
 1158 
/** @defgroup RCC_LL_EF_PLL PLL
1159 
 
 1159 
  * @{
1160 
/** @defgroup RCC_LL_EF_PLL PLL
 1160 
  */
1161 
  * @{
 1161 
 
1162 
  */
 1162 
/**
1163 
 
 1163 
  * @brief  Enable PLL
1164 
/**
 1164 
  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
1165 
  * @brief  Enable PLL
 1165 
  * @retval None
1166 
  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
 1166 
  */
1167 
  * @retval None
 1167 
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
1168 
  */
 1168 
{
1169 
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
 1169 
  SET_BIT(RCC->CR, RCC_CR_PLLON);
1170 
{
 1170 
}
1171 
  SET_BIT(RCC->CR, RCC_CR_PLLON);
 1171 
 
1172 
}
 1172 
/**
1173 
 
 1173 
  * @brief  Disable PLL
1174 
/**
 1174 
  * @note Cannot be disabled if the PLL clock is used as the system clock
1175 
  * @brief  Disable PLL
 1175 
  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
1176 
  * @note Cannot be disabled if the PLL clock is used as the system clock
 1176 
  * @retval None
1177 
  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
 1177 
  */
1178 
  * @retval None
 1178 
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
1179 
  */
 1179 
{
1180 
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
 1180 
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
1181 
{
 1181 
}
1182 
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
 1182 
 
1183 
}
 1183 
/**
1184 
 
 1184 
  * @brief  Check if PLL Ready
1185 
/**
 1185 
  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
1186 
  * @brief  Check if PLL Ready
 1186 
  * @retval State of bit (1 or 0).
1187 
  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
 1187 
  */
1188 
  * @retval State of bit (1 or 0).
 1188 
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
1189 
  */
 1189 
{
1190 
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
 1190 
  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
1191 
{
 1191 
}
1192 
  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
 1192 
 
1193 
}
 1193 
/**
1194 
 
 1194 
  * @brief  Configure PLL used for SYSCLK Domain
1195 
/**
 1195 
  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
1196 
  * @brief  Configure PLL used for SYSCLK Domain
 1196 
  *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
1197 
  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
 1197 
  *         CFGR         PLLDIV        LL_RCC_PLL_ConfigDomain_SYS
1198 
  *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
 1198 
  * @param  Source This parameter can be one of the following values:
1199 
  *         CFGR         PLLDIV        LL_RCC_PLL_ConfigDomain_SYS
 1199 
  *         @arg @ref LL_RCC_PLLSOURCE_HSI
1200 
  * @param  Source This parameter can be one of the following values:
 1200 
  *         @arg @ref LL_RCC_PLLSOURCE_HSE
1201 
  *         @arg @ref LL_RCC_PLLSOURCE_HSI
 1201 
  * @param  PLLMul This parameter can be one of the following values:
1202 
  *         @arg @ref LL_RCC_PLLSOURCE_HSE
 1202 
  *         @arg @ref LL_RCC_PLL_MUL_3
1203 
  * @param  PLLMul This parameter can be one of the following values:
 1203 
  *         @arg @ref LL_RCC_PLL_MUL_4
1204 
  *         @arg @ref LL_RCC_PLL_MUL_3
 1204 
  *         @arg @ref LL_RCC_PLL_MUL_6
1205 
  *         @arg @ref LL_RCC_PLL_MUL_4
 1205 
  *         @arg @ref LL_RCC_PLL_MUL_8
1206 
  *         @arg @ref LL_RCC_PLL_MUL_6
 1206 
  *         @arg @ref LL_RCC_PLL_MUL_12
1207 
  *         @arg @ref LL_RCC_PLL_MUL_8
 1207 
  *         @arg @ref LL_RCC_PLL_MUL_16
1208 
  *         @arg @ref LL_RCC_PLL_MUL_12
 1208 
  *         @arg @ref LL_RCC_PLL_MUL_24
1209 
  *         @arg @ref LL_RCC_PLL_MUL_16
 1209 
  *         @arg @ref LL_RCC_PLL_MUL_32
1210 
  *         @arg @ref LL_RCC_PLL_MUL_24
 1210 
  *         @arg @ref LL_RCC_PLL_MUL_48
1211 
  *         @arg @ref LL_RCC_PLL_MUL_32
 1211 
  * @param  PLLDiv This parameter can be one of the following values:
1212 
  *         @arg @ref LL_RCC_PLL_MUL_48
 1212 
  *         @arg @ref LL_RCC_PLL_DIV_2
1213 
  * @param  PLLDiv This parameter can be one of the following values:
 1213 
  *         @arg @ref LL_RCC_PLL_DIV_3
1214 
  *         @arg @ref LL_RCC_PLL_DIV_2
 1214 
  *         @arg @ref LL_RCC_PLL_DIV_4
1215 
  *         @arg @ref LL_RCC_PLL_DIV_3
 1215 
  * @retval None
1216 
  *         @arg @ref LL_RCC_PLL_DIV_4
 1216 
  */
1217 
  * @retval None
 1217 
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
1218 
  */
 1218 
{
1219 
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
 1219 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
1220 
{
 1220 
}
1221 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
 1221 
 
1222 
}
 1222 
/**
1223 
 
 1223 
  * @brief  Configure PLL clock source
1224 
/**
 1224 
  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_SetMainSource
1225 
  * @brief  Configure PLL clock source
 1225 
  * @param  PLLSource This parameter can be one of the following values:
1226 
  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_SetMainSource
 1226 
  *         @arg @ref LL_RCC_PLLSOURCE_HSI
1227 
  * @param  PLLSource This parameter can be one of the following values:
 1227 
  *         @arg @ref LL_RCC_PLLSOURCE_HSE
1228 
  *         @arg @ref LL_RCC_PLLSOURCE_HSI
 1228 
  * @retval None
1229 
  *         @arg @ref LL_RCC_PLLSOURCE_HSE
 1229 
  */
1230 
  * @retval None
 1230 
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
1231 
  */
 1231 
{
1232 
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
 1232 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
1233 
{
 1233 
}
1234 
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
 1234 
 
1235 
}
 1235 
/**
1236 
 
 1236 
  * @brief  Get the oscillator used as PLL clock source.
1237 
/**
 1237 
  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource
1238 
  * @brief  Get the oscillator used as PLL clock source.
 1238 
  * @retval Returned value can be one of the following values:
1239 
  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource
 1239 
  *         @arg @ref LL_RCC_PLLSOURCE_HSI
1240 
  * @retval Returned value can be one of the following values:
 1240 
  *         @arg @ref LL_RCC_PLLSOURCE_HSE
1241 
  *         @arg @ref LL_RCC_PLLSOURCE_HSI
 1241 
  */
1242 
  *         @arg @ref LL_RCC_PLLSOURCE_HSE
 1242 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
1243 
  */
 1243 
{
1244 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
 1244 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
1245 
{
 1245 
}
1246 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
 1246 
 
1247 
}
 1247 
/**
1248 
 
 1248 
  * @brief  Get PLL multiplication Factor
1249 
/**
 1249 
  * @rmtoll CFGR         PLLMUL        LL_RCC_PLL_GetMultiplicator
1250 
  * @brief  Get PLL multiplication Factor
 1250 
  * @retval Returned value can be one of the following values:
1251 
  * @rmtoll CFGR         PLLMUL        LL_RCC_PLL_GetMultiplicator
 1251 
  *         @arg @ref LL_RCC_PLL_MUL_3
1252 
  * @retval Returned value can be one of the following values:
 1252 
  *         @arg @ref LL_RCC_PLL_MUL_4
1253 
  *         @arg @ref LL_RCC_PLL_MUL_3
 1253 
  *         @arg @ref LL_RCC_PLL_MUL_6
1254 
  *         @arg @ref LL_RCC_PLL_MUL_4
 1254 
  *         @arg @ref LL_RCC_PLL_MUL_8
1255 
  *         @arg @ref LL_RCC_PLL_MUL_6
 1255 
  *         @arg @ref LL_RCC_PLL_MUL_12
1256 
  *         @arg @ref LL_RCC_PLL_MUL_8
 1256 
  *         @arg @ref LL_RCC_PLL_MUL_16
1257 
  *         @arg @ref LL_RCC_PLL_MUL_12
 1257 
  *         @arg @ref LL_RCC_PLL_MUL_24
1258 
  *         @arg @ref LL_RCC_PLL_MUL_16
 1258 
  *         @arg @ref LL_RCC_PLL_MUL_32
1259 
  *         @arg @ref LL_RCC_PLL_MUL_24
 1259 
  *         @arg @ref LL_RCC_PLL_MUL_48
1260 
  *         @arg @ref LL_RCC_PLL_MUL_32
 1260 
  */
1261 
  *         @arg @ref LL_RCC_PLL_MUL_48
 1261 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
1262 
  */
 1262 
{
1263 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
 1263 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
1264 
{
 1264 
}
1265 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
 1265 
 
1266 
}
 1266 
/**
1267 
 
 1267 
  * @brief  Get Division factor for the main PLL and other PLL
1268 
/**
 1268 
  * @rmtoll CFGR         PLLDIV        LL_RCC_PLL_GetDivider
1269 
  * @brief  Get Division factor for the main PLL and other PLL
 1269 
  * @retval Returned value can be one of the following values:
1270 
  * @rmtoll CFGR         PLLDIV        LL_RCC_PLL_GetDivider
 1270 
  *         @arg @ref LL_RCC_PLL_DIV_2
1271 
  * @retval Returned value can be one of the following values:
 1271 
  *         @arg @ref LL_RCC_PLL_DIV_3
1272 
  *         @arg @ref LL_RCC_PLL_DIV_2
 1272 
  *         @arg @ref LL_RCC_PLL_DIV_4
1273 
  *         @arg @ref LL_RCC_PLL_DIV_3
 1273 
  */
1274 
  *         @arg @ref LL_RCC_PLL_DIV_4
 1274 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
1275 
  */
 1275 
{
1276 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
 1276 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
1277 
{
 1277 
}
1278 
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
 1278 
 
1279 
}
 1279 
/**
1280 
 
 1280 
  * @}
1281 
/**
 1281 
  */
1282 
  * @}
 1282 
 
1283 
  */
 1283 
/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1284 
 
 1284 
  * @{
1285 
/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
 1285 
  */
1286 
  * @{
 1286 
 
1287 
  */
 1287 
/**
1288 
 
 1288 
  * @brief  Clear LSI ready interrupt flag
1289 
/**
 1289 
  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
1290 
  * @brief  Clear LSI ready interrupt flag
 1290 
  * @retval None
1291 
  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
 1291 
  */
1292 
  * @retval None
 1292 
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1293 
  */
 1293 
{
1294 
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
 1294 
  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
1295 
{
 1295 
}
1296 
  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
 1296 
 
1297 
}
 1297 
/**
1298 
 
 1298 
  * @brief  Clear LSE ready interrupt flag
1299 
/**
 1299 
  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
1300 
  * @brief  Clear LSE ready interrupt flag
 1300 
  * @retval None
1301 
  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
 1301 
  */
1302 
  * @retval None
 1302 
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1303 
  */
 1303 
{
1304 
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
 1304 
  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
1305 
{
 1305 
}
1306 
  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
 1306 
 
1307 
}
 1307 
/**
1308 
 
 1308 
  * @brief  Clear MSI ready interrupt flag
1309 
/**
 1309 
  * @rmtoll CIR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
1310 
  * @brief  Clear MSI ready interrupt flag
 1310 
  * @retval None
1311 
  * @rmtoll CIR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
 1311 
  */
1312 
  * @retval None
 1312 
__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
1313 
  */
 1313 
{
1314 
__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
 1314 
  SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC);
1315 
{
 1315 
}
1316 
  SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC);
 1316 
 
1317 
}
 1317 
/**
1318 
 
 1318 
  * @brief  Clear HSI ready interrupt flag
1319 
/**
 1319 
  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
1320 
  * @brief  Clear HSI ready interrupt flag
 1320 
  * @retval None
1321 
  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
 1321 
  */
1322 
  * @retval None
 1322 
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1323 
  */
 1323 
{
1324 
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
 1324 
  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
1325 
{
 1325 
}
1326 
  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
 1326 
 
1327 
}
 1327 
/**
1328 
 
 1328 
  * @brief  Clear HSE ready interrupt flag
1329 
/**
 1329 
  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
1330 
  * @brief  Clear HSE ready interrupt flag
 1330 
  * @retval None
1331 
  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
 1331 
  */
1332 
  * @retval None
 1332 
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1333 
  */
 1333 
{
1334 
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
 1334 
  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
1335 
{
 1335 
}
1336 
  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
 1336 
 
1337 
}
 1337 
/**
1338 
 
 1338 
  * @brief  Clear PLL ready interrupt flag
1339 
/**
 1339 
  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
1340 
  * @brief  Clear PLL ready interrupt flag
 1340 
  * @retval None
1341 
  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
 1341 
  */
1342 
  * @retval None
 1342 
__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
1343 
  */
 1343 
{
1344 
__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
 1344 
  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
1345 
{
 1345 
}
1346 
  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
 1346 
 
1347 
}
 1347 
/**
1348 
 
 1348 
  * @brief  Clear Clock security system interrupt flag
1349 
/**
 1349 
  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
1350 
  * @brief  Clear Clock security system interrupt flag
 1350 
  * @retval None
1351 
  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
 1351 
  */
1352 
  * @retval None
 1352 
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
1353 
  */
 1353 
{
1354 
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
 1354 
  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
1355 
{
 1355 
}
1356 
  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
 1356 
 
1357 
}
 1357 
#if defined(RCC_LSECSS_SUPPORT)
1358 
 
 1358 
/**
1359 
#if defined(RCC_LSECSS_SUPPORT)
 1359 
  * @brief  Clear LSE Clock security system interrupt flag
1360 
/**
 1360 
  * @rmtoll CIR         LSECSSC       LL_RCC_ClearFlag_LSECSS
1361 
  * @brief  Clear LSE Clock security system interrupt flag
 1361 
  * @retval None
1362 
  * @rmtoll CIR         LSECSSC       LL_RCC_ClearFlag_LSECSS
 1362 
  */
1363 
  * @retval None
 1363 
__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
1364 
  */
 1364 
{
1365 
__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
 1365 
  SET_BIT(RCC->CIR, RCC_CIR_LSECSSC);
1366 
{
 1366 
}
1367 
  SET_BIT(RCC->CIR, RCC_CIR_LSECSSC);
 1367 
 
1368 
}
 1368 
#endif /* RCC_LSECSS_SUPPORT */
1369 
 
 1369 
/**
1370 
#endif /* RCC_LSECSS_SUPPORT */
 1370 
  * @brief  Check if LSI ready interrupt occurred or not
1371 
/**
 1371 
  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
1372 
  * @brief  Check if LSI ready interrupt occurred or not
 1372 
  * @retval State of bit (1 or 0).
1373 
  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
 1373 
  */
1374 
  * @retval State of bit (1 or 0).
 1374 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
1375 
  */
 1375 
{
1376 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
 1376 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == RCC_CIR_LSIRDYF) ? 1UL : 0UL);
1377 
{
 1377 
}
1378 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == RCC_CIR_LSIRDYF) ? 1UL : 0UL);
 1378 
 
1379 
}
 1379 
/**
1380 
 
 1380 
  * @brief  Check if LSE ready interrupt occurred or not
1381 
/**
 1381 
  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
1382 
  * @brief  Check if LSE ready interrupt occurred or not
 1382 
  * @retval State of bit (1 or 0).
1383 
  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
 1383 
  */
1384 
  * @retval State of bit (1 or 0).
 1384 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
1385 
  */
 1385 
{
1386 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
 1386 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == RCC_CIR_LSERDYF) ? 1UL : 0UL);
1387 
{
 1387 
}
1388 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == RCC_CIR_LSERDYF) ? 1UL : 0UL);
 1388 
 
1389 
}
 1389 
/**
1390 
 
 1390 
  * @brief  Check if MSI ready interrupt occurred or not
1391 
/**
 1391 
  * @rmtoll CIR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
1392 
  * @brief  Check if MSI ready interrupt occurred or not
 1392 
  * @retval State of bit (1 or 0).
1393 
  * @rmtoll CIR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
 1393 
  */
1394 
  * @retval State of bit (1 or 0).
 1394 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
1395 
  */
 1395 
{
1396 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
 1396 
  return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == RCC_CIR_MSIRDYF) ? 1UL : 0UL);
1397 
{
 1397 
}
1398 
  return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == RCC_CIR_MSIRDYF) ? 1UL : 0UL);
 1398 
 
1399 
}
 1399 
/**
1400 
 
 1400 
  * @brief  Check if HSI ready interrupt occurred or not
1401 
/**
 1401 
  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
1402 
  * @brief  Check if HSI ready interrupt occurred or not
 1402 
  * @retval State of bit (1 or 0).
1403 
  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
 1403 
  */
1404 
  * @retval State of bit (1 or 0).
 1404 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
1405 
  */
 1405 
{
1406 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
 1406 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == RCC_CIR_HSIRDYF) ? 1UL : 0UL);
1407 
{
 1407 
}
1408 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == RCC_CIR_HSIRDYF) ? 1UL : 0UL);
 1408 
 
1409 
}
 1409 
/**
1410 
 
 1410 
  * @brief  Check if HSE ready interrupt occurred or not
1411 
/**
 1411 
  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
1412 
  * @brief  Check if HSE ready interrupt occurred or not
 1412 
  * @retval State of bit (1 or 0).
1413 
  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
 1413 
  */
1414 
  * @retval State of bit (1 or 0).
 1414 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
1415 
  */
 1415 
{
1416 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
 1416 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == RCC_CIR_HSERDYF) ? 1UL : 0UL);
1417 
{
 1417 
}
1418 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == RCC_CIR_HSERDYF) ? 1UL : 0UL);
 1418 
 
1419 
}
 1419 
/**
1420 
 
 1420 
  * @brief  Check if PLL ready interrupt occurred or not
1421 
/**
 1421 
  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
1422 
  * @brief  Check if PLL ready interrupt occurred or not
 1422 
  * @retval State of bit (1 or 0).
1423 
  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
 1423 
  */
1424 
  * @retval State of bit (1 or 0).
 1424 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
1425 
  */
 1425 
{
1426 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
 1426 
  return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == RCC_CIR_PLLRDYF) ? 1UL : 0UL);
1427 
{
 1427 
}
1428 
  return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == RCC_CIR_PLLRDYF) ? 1UL : 0UL);
 1428 
 
1429 
}
 1429 
/**
1430 
 
 1430 
  * @brief  Check if Clock security system interrupt occurred or not
1431 
/**
 1431 
  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
1432 
  * @brief  Check if Clock security system interrupt occurred or not
 1432 
  * @retval State of bit (1 or 0).
1433 
  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
 1433 
  */
1434 
  * @retval State of bit (1 or 0).
 1434 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
1435 
  */
 1435 
{
1436 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
 1436 
  return ((READ_BIT(RCC->CIR, RCC_CIR_CSSF) == RCC_CIR_CSSF) ? 1UL : 0UL);
1437 
{
 1437 
}
1438 
  return ((READ_BIT(RCC->CIR, RCC_CIR_CSSF) == RCC_CIR_CSSF) ? 1UL : 0UL);
 1438 
 
1439 
}
 1439 
#if defined(RCC_LSECSS_SUPPORT)
1440 
 
 1440 
/**
1441 
#if defined(RCC_LSECSS_SUPPORT)
 1441 
  * @brief  Check if LSE Clock security system interrupt occurred or not
1442 
/**
 1442 
  * @rmtoll CIR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
1443 
  * @brief  Check if LSE Clock security system interrupt occurred or not
 1443 
  * @retval State of bit (1 or 0).
1444 
  * @rmtoll CIR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
 1444 
  */
1445 
  * @retval State of bit (1 or 0).
 1445 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
1446 
  */
 1446 
{
1447 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
 1447 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == RCC_CIR_LSECSSF) ? 1UL : 0UL);
1448 
{
 1448 
}
1449 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == RCC_CIR_LSECSSF) ? 1UL : 0UL);
 1449 
#endif /* RCC_LSECSS_SUPPORT */
1450 
}
 1450 
 
1451 
#endif /* RCC_LSECSS_SUPPORT */
 1451 
/**
1452 
 
 1452 
  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
1453 
/**
 1453 
  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
1454 
  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
 1454 
  * @retval State of bit (1 or 0).
1455 
  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
 1455 
  */
1456 
  * @retval State of bit (1 or 0).
 1456 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
1457 
  */
 1457 
{
1458 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
 1458 
  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
1459 
{
 1459 
}
1460 
  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
 1460 
 
1461 
}
 1461 
/**
1462 
 
 1462 
  * @brief  Check if RCC flag Low Power reset is set or not.
1463 
/**
 1463 
  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
1464 
  * @brief  Check if RCC flag Low Power reset is set or not.
 1464 
  * @retval State of bit (1 or 0).
1465 
  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
 1465 
  */
1466 
  * @retval State of bit (1 or 0).
 1466 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
1467 
  */
 1467 
{
1468 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
 1468 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
1469 
{
 1469 
}
1470 
  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
 1470 
 
1471 
}
 1471 
/**
1472 
 
 1472 
  * @brief  Check if RCC flag is set or not.
1473 
/**
 1473 
  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
1474 
  * @brief  Check if RCC flag is set or not.
 1474 
  * @retval State of bit (1 or 0).
1475 
  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
 1475 
  */
1476 
  * @retval State of bit (1 or 0).
 1476 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
1477 
  */
 1477 
{
1478 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
 1478 
  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
1479 
{
 1479 
}
1480 
  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
 1480 
 
1481 
}
 1481 
/**
1482 
 
 1482 
  * @brief  Check if RCC flag Pin reset is set or not.
1483 
/**
 1483 
  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
1484 
  * @brief  Check if RCC flag Pin reset is set or not.
 1484 
  * @retval State of bit (1 or 0).
1485 
  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
 1485 
  */
1486 
  * @retval State of bit (1 or 0).
 1486 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
1487 
  */
 1487 
{
1488 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
 1488 
  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
1489 
{
 1489 
}
1490 
  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
 1490 
 
1491 
}
 1491 
/**
1492 
 
 1492 
  * @brief  Check if RCC flag POR/PDR reset is set or not.
1493 
/**
 1493 
  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
1494 
  * @brief  Check if RCC flag POR/PDR reset is set or not.
 1494 
  * @retval State of bit (1 or 0).
1495 
  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
 1495 
  */
1496 
  * @retval State of bit (1 or 0).
 1496 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
1497 
  */
 1497 
{
1498 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
 1498 
  return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL);
1499 
{
 1499 
}
1500 
  return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL);
 1500 
 
1501 
}
 1501 
/**
1502 
 
 1502 
  * @brief  Check if RCC flag Software reset is set or not.
1503 
/**
 1503 
  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
1504 
  * @brief  Check if RCC flag Software reset is set or not.
 1504 
  * @retval State of bit (1 or 0).
1505 
  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
 1505 
  */
1506 
  * @retval State of bit (1 or 0).
 1506 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
1507 
  */
 1507 
{
1508 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
 1508 
  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
1509 
{
 1509 
}
1510 
  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
 1510 
 
1511 
}
 1511 
/**
1512 
 
 1512 
  * @brief  Check if RCC flag Window Watchdog reset is set or not.
1513 
/**
 1513 
  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
1514 
  * @brief  Check if RCC flag Window Watchdog reset is set or not.
 1514 
  * @retval State of bit (1 or 0).
1515 
  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
 1515 
  */
1516 
  * @retval State of bit (1 or 0).
 1516 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
1517 
  */
 1517 
{
1518 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
 1518 
  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
1519 
{
 1519 
}
1520 
  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
 1520 
 
1521 
}
 1521 
/**
1522 
 
 1522 
  * @brief  Set RMVF bit to clear the reset flags.
1523 
/**
 1523 
  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
1524 
  * @brief  Set RMVF bit to clear the reset flags.
 1524 
  * @retval None
1525 
  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
 1525 
  */
1526 
  * @retval None
 1526 
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
1527 
  */
 1527 
{
1528 
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
 1528 
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
1529 
{
 1529 
}
1530 
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
 1530 
 
1531 
}
 1531 
/**
1532 
 
 1532 
  * @}
1533 
/**
 1533 
  */
1534 
  * @}
 1534 
 
1535 
  */
 1535 
/** @defgroup RCC_LL_EF_IT_Management IT Management
1536 
 
 1536 
  * @{
1537 
/** @defgroup RCC_LL_EF_IT_Management IT Management
 1537 
  */
1538 
  * @{
 1538 
 
1539 
  */
 1539 
/**
1540 
 
 1540 
  * @brief  Enable LSI ready interrupt
1541 
/**
 1541 
  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
1542 
  * @brief  Enable LSI ready interrupt
 1542 
  * @retval None
1543 
  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
 1543 
  */
1544 
  * @retval None
 1544 
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
1545 
  */
 1545 
{
1546 
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
 1546 
  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
1547 
{
 1547 
}
1548 
  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
 1548 
 
1549 
}
 1549 
/**
1550 
 
 1550 
  * @brief  Enable LSE ready interrupt
1551 
/**
 1551 
  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
1552 
  * @brief  Enable LSE ready interrupt
 1552 
  * @retval None
1553 
  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
 1553 
  */
1554 
  * @retval None
 1554 
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
1555 
  */
 1555 
{
1556 
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
 1556 
  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
1557 
{
 1557 
}
1558 
  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
 1558 
 
1559 
}
 1559 
/**
1560 
 
 1560 
  * @brief  Enable MSI ready interrupt
1561 
/**
 1561 
  * @rmtoll CIR         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
1562 
  * @brief  Enable MSI ready interrupt
 1562 
  * @retval None
1563 
  * @rmtoll CIR         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
 1563 
  */
1564 
  * @retval None
 1564 
__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
1565 
  */
 1565 
{
1566 
__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
 1566 
  SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
1567 
{
 1567 
}
1568 
  SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
 1568 
 
1569 
}
 1569 
/**
1570 
 
 1570 
  * @brief  Enable HSI ready interrupt
1571 
/**
 1571 
  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
1572 
  * @brief  Enable HSI ready interrupt
 1572 
  * @retval None
1573 
  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
 1573 
  */
1574 
  * @retval None
 1574 
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
1575 
  */
 1575 
{
1576 
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
 1576 
  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
1577 
{
 1577 
}
1578 
  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
 1578 
 
1579 
}
 1579 
/**
1580 
 
 1580 
  * @brief  Enable HSE ready interrupt
1581 
/**
 1581 
  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
1582 
  * @brief  Enable HSE ready interrupt
 1582 
  * @retval None
1583 
  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
 1583 
  */
1584 
  * @retval None
 1584 
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
1585 
  */
 1585 
{
1586 
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
 1586 
  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
1587 
{
 1587 
}
1588 
  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
 1588 
 
1589 
}
 1589 
/**
1590 
 
 1590 
  * @brief  Enable PLL ready interrupt
1591 
/**
 1591 
  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
1592 
  * @brief  Enable PLL ready interrupt
 1592 
  * @retval None
1593 
  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
 1593 
  */
1594 
  * @retval None
 1594 
__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
1595 
  */
 1595 
{
1596 
__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
 1596 
  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
1597 
{
 1597 
}
1598 
  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
 1598 
 
1599 
}
 1599 
#if defined(RCC_LSECSS_SUPPORT)
1600 
 
 1600 
/**
1601 
#if defined(RCC_LSECSS_SUPPORT)
 1601 
  * @brief  Enable LSE clock security system interrupt
1602 
/**
 1602 
  * @rmtoll CIR         LSECSSIE      LL_RCC_EnableIT_LSECSS
1603 
  * @brief  Enable LSE clock security system interrupt
 1603 
  * @retval None
1604 
  * @rmtoll CIR         LSECSSIE      LL_RCC_EnableIT_LSECSS
 1604 
  */
1605 
  * @retval None
 1605 
__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
1606 
  */
 1606 
{
1607 
__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
 1607 
  SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
1608 
{
 1608 
}
1609 
  SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
 1609 
#endif /* RCC_LSECSS_SUPPORT */
1610 
}
 1610 
 
1611 
#endif /* RCC_LSECSS_SUPPORT */
 1611 
/**
1612 
 
 1612 
  * @brief  Disable LSI ready interrupt
1613 
/**
 1613 
  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
1614 
  * @brief  Disable LSI ready interrupt
 1614 
  * @retval None
1615 
  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
 1615 
  */
1616 
  * @retval None
 1616 
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
1617 
  */
 1617 
{
1618 
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
 1618 
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
1619 
{
 1619 
}
1620 
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
 1620 
 
1621 
}
 1621 
/**
1622 
 
 1622 
  * @brief  Disable LSE ready interrupt
1623 
/**
 1623 
  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
1624 
  * @brief  Disable LSE ready interrupt
 1624 
  * @retval None
1625 
  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
 1625 
  */
1626 
  * @retval None
 1626 
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
1627 
  */
 1627 
{
1628 
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
 1628 
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
1629 
{
 1629 
}
1630 
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
 1630 
 
1631 
}
 1631 
/**
1632 
 
 1632 
  * @brief  Disable MSI ready interrupt
1633 
/**
 1633 
  * @rmtoll CIR         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
1634 
  * @brief  Disable MSI ready interrupt
 1634 
  * @retval None
1635 
  * @rmtoll CIR         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
 1635 
  */
1636 
  * @retval None
 1636 
__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
1637 
  */
 1637 
{
1638 
__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
 1638 
  CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
1639 
{
 1639 
}
1640 
  CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
 1640 
 
1641 
}
 1641 
/**
1642 
 
 1642 
  * @brief  Disable HSI ready interrupt
1643 
/**
 1643 
  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
1644 
  * @brief  Disable HSI ready interrupt
 1644 
  * @retval None
1645 
  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
 1645 
  */
1646 
  * @retval None
 1646 
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
1647 
  */
 1647 
{
1648 
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
 1648 
  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
1649 
{
 1649 
}
1650 
  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
 1650 
 
1651 
}
 1651 
/**
1652 
 
 1652 
  * @brief  Disable HSE ready interrupt
1653 
/**
 1653 
  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
1654 
  * @brief  Disable HSE ready interrupt
 1654 
  * @retval None
1655 
  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
 1655 
  */
1656 
  * @retval None
 1656 
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
1657 
  */
 1657 
{
1658 
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
 1658 
  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
1659 
{
 1659 
}
1660 
  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
 1660 
 
1661 
}
 1661 
/**
1662 
 
 1662 
  * @brief  Disable PLL ready interrupt
1663 
/**
 1663 
  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
1664 
  * @brief  Disable PLL ready interrupt
 1664 
  * @retval None
1665 
  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
 1665 
  */
1666 
  * @retval None
 1666 
__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
1667 
  */
 1667 
{
1668 
__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
 1668 
  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
1669 
{
 1669 
}
1670 
  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
 1670 
 
1671 
}
 1671 
#if defined(RCC_LSECSS_SUPPORT)
1672 
 
 1672 
/**
1673 
#if defined(RCC_LSECSS_SUPPORT)
 1673 
  * @brief  Disable LSE clock security system interrupt
1674 
/**
 1674 
  * @rmtoll CIR         LSECSSIE      LL_RCC_DisableIT_LSECSS
1675 
  * @brief  Disable LSE clock security system interrupt
 1675 
  * @retval None
1676 
  * @rmtoll CIR         LSECSSIE      LL_RCC_DisableIT_LSECSS
 1676 
  */
1677 
  * @retval None
 1677 
__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
1678 
  */
 1678 
{
1679 
__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
 1679 
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
1680 
{
 1680 
}
1681 
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
 1681 
#endif /* RCC_LSECSS_SUPPORT */
1682 
}
 1682 
 
1683 
#endif /* RCC_LSECSS_SUPPORT */
 1683 
/**
1684 
 
 1684 
  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
1685 
/**
 1685 
  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
1686 
  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
 1686 
  * @retval State of bit (1 or 0).
1687 
  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
 1687 
  */
1688 
  * @retval State of bit (1 or 0).
 1688 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
1689 
  */
 1689 
{
1690 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
 1690 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == RCC_CIR_LSIRDYIE) ? 1UL : 0UL);
1691 
{
 1691 
}
1692 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == RCC_CIR_LSIRDYIE) ? 1UL : 0UL);
 1692 
 
1693 
}
 1693 
/**
1694 
 
 1694 
  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
1695 
/**
 1695 
  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
1696 
  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
 1696 
  * @retval State of bit (1 or 0).
1697 
  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
 1697 
  */
1698 
  * @retval State of bit (1 or 0).
 1698 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
1699 
  */
 1699 
{
1700 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
 1700 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == RCC_CIR_LSERDYIE) ? 1UL : 0UL);
1701 
{
 1701 
}
1702 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == RCC_CIR_LSERDYIE) ? 1UL : 0UL);
 1702 
 
1703 
}
 1703 
/**
1704 
 
 1704 
  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
1705 
/**
 1705 
  * @rmtoll CIR         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
1706 
  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
 1706 
  * @retval State of bit (1 or 0).
1707 
  * @rmtoll CIR         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
 1707 
  */
1708 
  * @retval State of bit (1 or 0).
 1708 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
1709 
  */
 1709 
{
1710 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
 1710 
  return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == RCC_CIR_MSIRDYIE) ? 1UL : 0UL);
1711 
{
 1711 
}
1712 
  return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == RCC_CIR_MSIRDYIE) ? 1UL : 0UL);
 1712 
 
1713 
}
 1713 
/**
1714 
 
 1714 
  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
1715 
/**
 1715 
  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
1716 
  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
 1716 
  * @retval State of bit (1 or 0).
1717 
  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
 1717 
  */
1718 
  * @retval State of bit (1 or 0).
 1718 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
1719 
  */
 1719 
{
1720 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
 1720 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == RCC_CIR_HSIRDYIE) ? 1UL : 0UL);
1721 
{
 1721 
}
1722 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == RCC_CIR_HSIRDYIE) ? 1UL : 0UL);
 1722 
 
1723 
}
 1723 
/**
1724 
 
 1724 
  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
1725 
/**
 1725 
  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
1726 
  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
 1726 
  * @retval State of bit (1 or 0).
1727 
  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
 1727 
  */
1728 
  * @retval State of bit (1 or 0).
 1728 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
1729 
  */
 1729 
{
1730 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
 1730 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == RCC_CIR_HSERDYIE) ? 1UL : 0UL);
1731 
{
 1731 
}
1732 
  return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == RCC_CIR_HSERDYIE) ? 1UL : 0UL);
 1732 
 
1733 
}
 1733 
/**
1734 
 
 1734 
  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
1735 
/**
 1735 
  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
1736 
  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
 1736 
  * @retval State of bit (1 or 0).
1737 
  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
 1737 
  */
1738 
  * @retval State of bit (1 or 0).
 1738 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
1739 
  */
 1739 
{
1740 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
 1740 
  return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == RCC_CIR_PLLRDYIE) ? 1UL : 0UL);
1741 
{
 1741 
}
1742 
  return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == RCC_CIR_PLLRDYIE) ? 1UL : 0UL);
 1742 
 
1743 
}
 1743 
#if defined(RCC_LSECSS_SUPPORT)
1744 
 
 1744 
/**
1745 
#if defined(RCC_LSECSS_SUPPORT)
 1745 
  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
1746 
/**
 1746 
  * @rmtoll CIR         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
1747 
  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
 1747 
  * @retval State of bit (1 or 0).
1748 
  * @rmtoll CIR         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
 1748 
  */
1749 
  * @retval State of bit (1 or 0).
 1749 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
1750 
  */
 1750 
{
1751 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
 1751 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == RCC_CIR_LSECSSIE) ? 1UL : 0UL);
1752 
{
 1752 
}
1753 
  return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == RCC_CIR_LSECSSIE) ? 1UL : 0UL);
 1753 
#endif /* RCC_LSECSS_SUPPORT */
1754 
}
 1754 
 
1755 
#endif /* RCC_LSECSS_SUPPORT */
 1755 
/**
1756 
 
 1756 
  * @}
1757 
/**
 1757 
  */
1758 
  * @}
 1758 
 
1759 
  */
 1759 
#if defined(USE_FULL_LL_DRIVER)
1760 
 
 1760 
/** @defgroup RCC_LL_EF_Init De-initialization function
1761 
#if defined(USE_FULL_LL_DRIVER)
 1761 
  * @{
1762 
/** @defgroup RCC_LL_EF_Init De-initialization function
 1762 
  */
1763 
  * @{
 1763 
ErrorStatus LL_RCC_DeInit(void);
1764 
  */
 1764 
/**
1765 
ErrorStatus LL_RCC_DeInit(void);
 1765 
  * @}
1766 
/**
 1766 
  */
1767 
  * @}
 1767 
 
1768 
  */
 1768 
/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
1769 
 
 1769 
  * @{
1770 
/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
 1770 
  */
1771 
  * @{
 1771 
void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
1772 
  */
 1772 
/**
1773 
void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
 1773 
  * @}
1774 
/**
 1774 
  */
1775 
  * @}
 1775 
#endif /* USE_FULL_LL_DRIVER */
1776 
  */
 1776 
 
1777 
#endif /* USE_FULL_LL_DRIVER */
 1777 
/**
1778 
 
 1778 
  * @}
1779 
/**
 1779 
  */
1780 
  * @}
 1780 
 
1781 
  */
 1781 
/**
1782 
 
 1782 
  * @}
1783 
/**
 1783 
  */
1784 
  * @}
 1784 
 
1785 
  */
 1785 
#endif /* RCC */
1786 
 
 1786 
 
1787 
#endif /* RCC */
 1787 
/**
1788 
 
 1788 
  * @}
1789 
/**
 1789 
  */
1790 
  * @}
 1790 
 
1791 
  */
 1791 
#ifdef __cplusplus
1792 
 
 1792 
}
1793 
#ifdef __cplusplus
 1793 
#endif
1794 
}
 1794 
 
1795 
#endif
 1795 
#endif /* __STM32L1xx_LL_RCC_H */
1796 
 
 1796 
 
1797 
#endif /* __STM32L1xx_LL_RCC_H */
 - 
 
1798 
 
 - 
 
1799 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 -