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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_iwdg.h |
3 | * @file stm32l1xx_ll_iwdg.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of IWDG LL module. |
5 | * @brief Header file of IWDG LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32L1xx_LL_IWDG_H |
| 21 | #ifndef STM32L1xx_LL_IWDG_H |
21 | #define STM32L1xx_LL_IWDG_H |
| 22 | #define STM32L1xx_LL_IWDG_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32l1xx.h" |
| 29 | #include "stm32l1xx.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined(IWDG) |
|
| 35 | #if defined(IWDG) |
35 | |
| 36 | 36 | /** @defgroup IWDG_LL IWDG |
|
| 37 | /** @defgroup IWDG_LL IWDG |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | |
| 43 | 43 | /* Private constants ---------------------------------------------------------*/ |
|
| 44 | /* Private constants ---------------------------------------------------------*/ |
44 | /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants |
| 45 | /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants |
45 | * @{ |
| 46 | * @{ |
46 | */ |
| 47 | */ |
47 | #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ |
| 48 | #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ |
48 | #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ |
| 49 | #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ |
49 | #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ |
| 50 | #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ |
50 | #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ |
| 51 | #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ |
51 | /** |
| 52 | /** |
52 | * @} |
| 53 | * @} |
53 | */ |
| 54 | */ |
54 | |
| 55 | 55 | /* Private macros ------------------------------------------------------------*/ |
|
| 56 | /* Private macros ------------------------------------------------------------*/ |
56 | |
| 57 | 57 | /* Exported types ------------------------------------------------------------*/ |
|
| 58 | /* Exported types ------------------------------------------------------------*/ |
58 | /* Exported constants --------------------------------------------------------*/ |
| 59 | /* Exported constants --------------------------------------------------------*/ |
59 | /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants |
| 60 | /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants |
60 | * @{ |
| 61 | * @{ |
61 | */ |
| 62 | */ |
62 | |
| 63 | 63 | /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines |
|
| 64 | /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines |
64 | * @brief Flags defines which can be used with LL_IWDG_ReadReg function |
| 65 | * @brief Flags defines which can be used with LL_IWDG_ReadReg function |
65 | * @{ |
| 66 | * @{ |
66 | */ |
| 67 | */ |
67 | #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ |
| 68 | #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ |
68 | #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ |
| 69 | #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ |
69 | /** |
| 70 | /** |
70 | * @} |
| 71 | * @} |
71 | */ |
| 72 | */ |
72 | |
| 73 | 73 | /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider |
|
| 74 | /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider |
74 | * @{ |
| 75 | * @{ |
75 | */ |
| 76 | */ |
76 | #define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ |
| 77 | #define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ |
77 | #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ |
| 78 | #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ |
78 | #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ |
| 79 | #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ |
79 | #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ |
| 80 | #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ |
80 | #define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ |
| 81 | #define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ |
81 | #define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ |
| 82 | #define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ |
82 | #define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ |
| 83 | #define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ |
83 | /** |
| 84 | /** |
84 | * @} |
| 85 | * @} |
85 | */ |
| 86 | */ |
86 | |
| 87 | 87 | /** |
|
| 88 | /** |
88 | * @} |
| 89 | * @} |
89 | */ |
| 90 | */ |
90 | |
| 91 | 91 | /* Exported macro ------------------------------------------------------------*/ |
|
| 92 | /* Exported macro ------------------------------------------------------------*/ |
92 | /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros |
| 93 | /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros |
93 | * @{ |
| 94 | * @{ |
94 | */ |
| 95 | */ |
95 | |
| 96 | 96 | /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros |
|
| 97 | /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros |
97 | * @{ |
| 98 | * @{ |
98 | */ |
| 99 | */ |
99 | |
| 100 | 100 | /** |
|
| 101 | /** |
101 | * @brief Write a value in IWDG register |
| 102 | * @brief Write a value in IWDG register |
102 | * @param __INSTANCE__ IWDG Instance |
| 103 | * @param __INSTANCE__ IWDG Instance |
103 | * @param __REG__ Register to be written |
| 104 | * @param __REG__ Register to be written |
104 | * @param __VALUE__ Value to be written in the register |
| 105 | * @param __VALUE__ Value to be written in the register |
105 | * @retval None |
| 106 | * @retval None |
106 | */ |
| 107 | */ |
107 | #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| 108 | #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
108 | |
| 109 | 109 | /** |
|
| 110 | /** |
110 | * @brief Read a value in IWDG register |
| 111 | * @brief Read a value in IWDG register |
111 | * @param __INSTANCE__ IWDG Instance |
| 112 | * @param __INSTANCE__ IWDG Instance |
112 | * @param __REG__ Register to be read |
| 113 | * @param __REG__ Register to be read |
113 | * @retval Register value |
| 114 | * @retval Register value |
114 | */ |
| 115 | */ |
115 | #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| 116 | #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
116 | /** |
| 117 | /** |
117 | * @} |
| 118 | * @} |
118 | */ |
| 119 | */ |
119 | |
| 120 | 120 | /** |
|
| 121 | /** |
121 | * @} |
| 122 | * @} |
122 | */ |
| 123 | */ |
123 | |
| 124 | 124 | ||
| 125 | 125 | /* Exported functions --------------------------------------------------------*/ |
|
| 126 | /* Exported functions --------------------------------------------------------*/ |
126 | /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions |
| 127 | /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions |
127 | * @{ |
| 128 | * @{ |
128 | */ |
| 129 | */ |
129 | /** @defgroup IWDG_LL_EF_Configuration Configuration |
| 130 | /** @defgroup IWDG_LL_EF_Configuration Configuration |
130 | * @{ |
| 131 | * @{ |
131 | */ |
| 132 | */ |
132 | |
| 133 | 133 | /** |
|
| 134 | /** |
134 | * @brief Start the Independent Watchdog |
| 135 | * @brief Start the Independent Watchdog |
135 | * @note Except if the hardware watchdog option is selected |
| 136 | * @note Except if the hardware watchdog option is selected |
136 | * @rmtoll KR KEY LL_IWDG_Enable |
| 137 | * @rmtoll KR KEY LL_IWDG_Enable |
137 | * @param IWDGx IWDG Instance |
| 138 | * @param IWDGx IWDG Instance |
138 | * @retval None |
| 139 | * @retval None |
139 | */ |
| 140 | */ |
140 | __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) |
| 141 | __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) |
141 | { |
| 142 | { |
142 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); |
| 143 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); |
143 | } |
| 144 | } |
144 | |
| 145 | 145 | /** |
|
| 146 | /** |
146 | * @brief Reloads IWDG counter with value defined in the reload register |
| 147 | * @brief Reloads IWDG counter with value defined in the reload register |
147 | * @rmtoll KR KEY LL_IWDG_ReloadCounter |
| 148 | * @rmtoll KR KEY LL_IWDG_ReloadCounter |
148 | * @param IWDGx IWDG Instance |
| 149 | * @param IWDGx IWDG Instance |
149 | * @retval None |
| 150 | * @retval None |
150 | */ |
| 151 | */ |
151 | __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) |
| 152 | __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) |
152 | { |
| 153 | { |
153 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); |
| 154 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); |
154 | } |
| 155 | } |
155 | |
| 156 | 156 | /** |
|
| 157 | /** |
157 | * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
| 158 | * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
158 | * @rmtoll KR KEY LL_IWDG_EnableWriteAccess |
| 159 | * @rmtoll KR KEY LL_IWDG_EnableWriteAccess |
159 | * @param IWDGx IWDG Instance |
| 160 | * @param IWDGx IWDG Instance |
160 | * @retval None |
| 161 | * @retval None |
161 | */ |
| 162 | */ |
162 | __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) |
| 163 | __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) |
163 | { |
| 164 | { |
164 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); |
| 165 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); |
165 | } |
| 166 | } |
166 | |
| 167 | 167 | /** |
|
| 168 | /** |
168 | * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
| 169 | * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
169 | * @rmtoll KR KEY LL_IWDG_DisableWriteAccess |
| 170 | * @rmtoll KR KEY LL_IWDG_DisableWriteAccess |
170 | * @param IWDGx IWDG Instance |
| 171 | * @param IWDGx IWDG Instance |
171 | * @retval None |
| 172 | * @retval None |
172 | */ |
| 173 | */ |
173 | __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) |
| 174 | __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) |
174 | { |
| 175 | { |
175 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); |
| 176 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); |
176 | } |
| 177 | } |
177 | |
| 178 | 178 | /** |
|
| 179 | /** |
179 | * @brief Select the prescaler of the IWDG |
| 180 | * @brief Select the prescaler of the IWDG |
180 | * @rmtoll PR PR LL_IWDG_SetPrescaler |
| 181 | * @rmtoll PR PR LL_IWDG_SetPrescaler |
181 | * @param IWDGx IWDG Instance |
| 182 | * @param IWDGx IWDG Instance |
182 | * @param Prescaler This parameter can be one of the following values: |
| 183 | * @param Prescaler This parameter can be one of the following values: |
183 | * @arg @ref LL_IWDG_PRESCALER_4 |
| 184 | * @arg @ref LL_IWDG_PRESCALER_4 |
184 | * @arg @ref LL_IWDG_PRESCALER_8 |
| 185 | * @arg @ref LL_IWDG_PRESCALER_8 |
185 | * @arg @ref LL_IWDG_PRESCALER_16 |
| 186 | * @arg @ref LL_IWDG_PRESCALER_16 |
186 | * @arg @ref LL_IWDG_PRESCALER_32 |
| 187 | * @arg @ref LL_IWDG_PRESCALER_32 |
187 | * @arg @ref LL_IWDG_PRESCALER_64 |
| 188 | * @arg @ref LL_IWDG_PRESCALER_64 |
188 | * @arg @ref LL_IWDG_PRESCALER_128 |
| 189 | * @arg @ref LL_IWDG_PRESCALER_128 |
189 | * @arg @ref LL_IWDG_PRESCALER_256 |
| 190 | * @arg @ref LL_IWDG_PRESCALER_256 |
190 | * @retval None |
| 191 | * @retval None |
191 | */ |
| 192 | */ |
192 | __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) |
| 193 | __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) |
193 | { |
| 194 | { |
194 | WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); |
| 195 | WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); |
195 | } |
| 196 | } |
196 | |
| 197 | 197 | /** |
|
| 198 | /** |
198 | * @brief Get the selected prescaler of the IWDG |
| 199 | * @brief Get the selected prescaler of the IWDG |
199 | * @rmtoll PR PR LL_IWDG_GetPrescaler |
| 200 | * @rmtoll PR PR LL_IWDG_GetPrescaler |
200 | * @param IWDGx IWDG Instance |
| 201 | * @param IWDGx IWDG Instance |
201 | * @retval Returned value can be one of the following values: |
| 202 | * @retval Returned value can be one of the following values: |
202 | * @arg @ref LL_IWDG_PRESCALER_4 |
| 203 | * @arg @ref LL_IWDG_PRESCALER_4 |
203 | * @arg @ref LL_IWDG_PRESCALER_8 |
| 204 | * @arg @ref LL_IWDG_PRESCALER_8 |
204 | * @arg @ref LL_IWDG_PRESCALER_16 |
| 205 | * @arg @ref LL_IWDG_PRESCALER_16 |
205 | * @arg @ref LL_IWDG_PRESCALER_32 |
| 206 | * @arg @ref LL_IWDG_PRESCALER_32 |
206 | * @arg @ref LL_IWDG_PRESCALER_64 |
| 207 | * @arg @ref LL_IWDG_PRESCALER_64 |
207 | * @arg @ref LL_IWDG_PRESCALER_128 |
| 208 | * @arg @ref LL_IWDG_PRESCALER_128 |
208 | * @arg @ref LL_IWDG_PRESCALER_256 |
| 209 | * @arg @ref LL_IWDG_PRESCALER_256 |
209 | */ |
| 210 | */ |
210 | __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) |
| 211 | __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) |
211 | { |
| 212 | { |
212 | return (READ_REG(IWDGx->PR)); |
| 213 | return (READ_REG(IWDGx->PR)); |
213 | } |
| 214 | } |
214 | |
| 215 | 215 | /** |
|
| 216 | /** |
216 | * @brief Specify the IWDG down-counter reload value |
| 217 | * @brief Specify the IWDG down-counter reload value |
217 | * @rmtoll RLR RL LL_IWDG_SetReloadCounter |
| 218 | * @rmtoll RLR RL LL_IWDG_SetReloadCounter |
218 | * @param IWDGx IWDG Instance |
| 219 | * @param IWDGx IWDG Instance |
219 | * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF |
| 220 | * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF |
220 | * @retval None |
| 221 | * @retval None |
221 | */ |
| 222 | */ |
222 | __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) |
| 223 | __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) |
223 | { |
| 224 | { |
224 | WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); |
| 225 | WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); |
225 | } |
| 226 | } |
226 | |
| 227 | 227 | /** |
|
| 228 | /** |
228 | * @brief Get the specified IWDG down-counter reload value |
| 229 | * @brief Get the specified IWDG down-counter reload value |
229 | * @rmtoll RLR RL LL_IWDG_GetReloadCounter |
| 230 | * @rmtoll RLR RL LL_IWDG_GetReloadCounter |
230 | * @param IWDGx IWDG Instance |
| 231 | * @param IWDGx IWDG Instance |
231 | * @retval Value between Min_Data=0 and Max_Data=0x0FFF |
| 232 | * @retval Value between Min_Data=0 and Max_Data=0x0FFF |
232 | */ |
| 233 | */ |
233 | __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) |
| 234 | __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) |
234 | { |
| 235 | { |
235 | return (READ_REG(IWDGx->RLR)); |
| 236 | return (READ_REG(IWDGx->RLR)); |
236 | } |
| 237 | } |
237 | |
| 238 | 238 | /** |
|
| 239 | /** |
239 | * @} |
| 240 | * @} |
240 | */ |
| 241 | */ |
241 | |
| 242 | 242 | /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management |
|
| 243 | /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management |
243 | * @{ |
| 244 | * @{ |
244 | */ |
| 245 | */ |
245 | |
| 246 | 246 | /** |
|
| 247 | /** |
247 | * @brief Check if flag Prescaler Value Update is set or not |
| 248 | * @brief Check if flag Prescaler Value Update is set or not |
248 | * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU |
| 249 | * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU |
249 | * @param IWDGx IWDG Instance |
| 250 | * @param IWDGx IWDG Instance |
250 | * @retval State of bit (1 or 0). |
| 251 | * @retval State of bit (1 or 0). |
251 | */ |
| 252 | */ |
252 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) |
| 253 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) |
253 | { |
| 254 | { |
254 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); |
| 255 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); |
255 | } |
| 256 | } |
256 | |
| 257 | 257 | /** |
|
| 258 | /** |
258 | * @brief Check if flag Reload Value Update is set or not |
| 259 | * @brief Check if flag Reload Value Update is set or not |
259 | * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU |
| 260 | * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU |
260 | * @param IWDGx IWDG Instance |
| 261 | * @param IWDGx IWDG Instance |
261 | * @retval State of bit (1 or 0). |
| 262 | * @retval State of bit (1 or 0). |
262 | */ |
| 263 | */ |
263 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) |
| 264 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) |
264 | { |
| 265 | { |
265 | return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); |
| 266 | return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); |
266 | } |
| 267 | } |
267 | |
| 268 | 268 | /** |
|
| 269 | /** |
269 | * @brief Check if flags Prescaler & Reload Value Update are reset or not |
| 270 | * @brief Check if flags Prescaler & Reload Value Update are reset or not |
270 | * @rmtoll SR PVU LL_IWDG_IsReady\n |
| 271 | * @rmtoll SR PVU LL_IWDG_IsReady\n |
271 | * SR RVU LL_IWDG_IsReady |
| 272 | * SR RVU LL_IWDG_IsReady |
272 | * @param IWDGx IWDG Instance |
| 273 | * @param IWDGx IWDG Instance |
273 | * @retval State of bits (1 or 0). |
| 274 | * @retval State of bits (1 or 0). |
274 | */ |
| 275 | */ |
275 | __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) |
| 276 | __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) |
276 | { |
| 277 | { |
277 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); |
| 278 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); |
278 | } |
| 279 | } |
279 | |
| 280 | 280 | /** |
|
| 281 | /** |
281 | * @} |
| 282 | * @} |
282 | */ |
| 283 | */ |
283 | |
| 284 | 284 | /** |
|
| 285 | /** |
285 | * @} |
| 286 | * @} |
286 | */ |
| 287 | */ |
287 | |
| 288 | 288 | /** |
|
| 289 | /** |
289 | * @} |
| 290 | * @} |
290 | */ |
| 291 | */ |
291 | |
| 292 | 292 | #endif /* IWDG */ |
|
| 293 | #endif /* IWDG */ |
293 | |
| 294 | 294 | /** |
|
| 295 | /** |
295 | * @} |
| 296 | * @} |
296 | */ |
| 297 | */ |
297 | |
| 298 | 298 | #ifdef __cplusplus |
|
| 299 | #ifdef __cplusplus |
299 | } |
| 300 | } |
300 | #endif |
| 301 | #endif |
301 | |
| 302 | 302 | #endif /* STM32L1xx_LL_IWDG_H */ |
|
| 303 | #endif /* STM32L1xx_LL_IWDG_H */ |
- | |
| 304 | - | ||
| 305 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |