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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_fsmc.h |
3 | * @file stm32l1xx_ll_fsmc.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of FSMC HAL module. |
5 | * @brief Header file of FSMC HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32L1xx_LL_FSMC_H |
| 21 | #ifndef STM32L1xx_LL_FSMC_H |
21 | #define STM32L1xx_LL_FSMC_H |
| 22 | #define STM32L1xx_LL_FSMC_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32l1xx_hal_def.h" |
| 29 | #include "stm32l1xx_hal_def.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_HAL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | /** @addtogroup FSMC_LL |
|
| 35 | /** @addtogroup FSMC_LL |
35 | * @{ |
| 36 | * @{ |
36 | */ |
| 37 | */ |
37 | |
| 38 | 38 | /** @addtogroup FSMC_LL_Private_Macros |
|
| 39 | /** @addtogroup FSMC_LL_Private_Macros |
39 | * @{ |
| 40 | * @{ |
40 | */ |
| 41 | */ |
41 | #if defined(FSMC_BANK1) |
| 42 | #if defined(FSMC_BANK1) |
42 | |
| 43 | 43 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
|
| 44 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
44 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| 45 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
45 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| 46 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
46 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| 47 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
47 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| 48 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
48 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| 49 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
49 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| 50 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
50 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| 51 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
51 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| 52 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
52 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| 53 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
53 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| 54 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
54 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| 55 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
55 | #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ |
| 56 | #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ |
56 | ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ |
| 57 | ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ |
57 | ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ |
| 58 | ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ |
58 | ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ |
| 59 | ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ |
59 | ((__SIZE__) == FSMC_PAGE_SIZE_1024)) |
| 60 | ((__SIZE__) == FSMC_PAGE_SIZE_1024)) |
60 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| 61 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
61 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| 62 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
62 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| 63 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
63 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| 64 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
64 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| 65 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
65 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| 66 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
66 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| 67 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
67 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| 68 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
68 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| 69 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
69 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| 70 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
70 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| 71 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
71 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| 72 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
72 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| 73 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
73 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| 74 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
74 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| 75 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
75 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| 76 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
76 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| 77 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
77 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| 78 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
78 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| 79 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
79 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| 80 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
80 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) |
| 81 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) |
81 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| 82 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
82 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| 83 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
83 | #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| 84 | #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
84 | ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| 85 | ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
85 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) |
| 86 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) |
86 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) |
| 87 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) |
87 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) |
| 88 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) |
88 | #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) |
| 89 | #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) |
89 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) |
| 90 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) |
90 | #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) |
| 91 | #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) |
91 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| 92 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
92 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| 93 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
93 | |
| 94 | 94 | #endif /* FSMC_BANK1 */ |
|
| 95 | #endif /* FSMC_BANK1 */ |
95 | |
| 96 | 96 | /** |
|
| 97 | /** |
97 | * @} |
| 98 | * @} |
98 | */ |
| 99 | */ |
99 | |
| 100 | 100 | /* Exported typedef ----------------------------------------------------------*/ |
|
| 101 | /* Exported typedef ----------------------------------------------------------*/ |
101 | |
| 102 | 102 | /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types |
|
| 103 | /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types |
103 | * @{ |
| 104 | * @{ |
104 | */ |
| 105 | */ |
105 | |
| 106 | 106 | #if defined(FSMC_BANK1) |
|
| 107 | #if defined(FSMC_BANK1) |
107 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| 108 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
108 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| 109 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
109 | #endif /* FSMC_BANK1 */ |
| 110 | #endif /* FSMC_BANK1 */ |
110 | |
| 111 | 111 | #if defined(FSMC_BANK1) |
|
| 112 | #if defined(FSMC_BANK1) |
112 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| 113 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
113 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| 114 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
114 | #endif /* FSMC_BANK1 */ |
| 115 | #endif /* FSMC_BANK1 */ |
115 | |
| 116 | 116 | #if defined(FSMC_BANK1) |
|
| 117 | #if defined(FSMC_BANK1) |
117 | /** |
| 118 | /** |
118 | * @brief FSMC NORSRAM Configuration Structure definition |
| 119 | * @brief FSMC NORSRAM Configuration Structure definition |
119 | */ |
| 120 | */ |
120 | typedef struct |
| 121 | typedef struct |
121 | { |
| 122 | { |
122 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| 123 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
123 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| 124 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
124 | |
| 125 | 125 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
|
| 126 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
126 | multiplexed on the data bus or not. |
| 127 | multiplexed on the data bus or not. |
127 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| 128 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
128 | |
| 129 | 129 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
|
| 130 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
130 | the corresponding memory device. |
| 131 | the corresponding memory device. |
131 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| 132 | This parameter can be a value of @ref FSMC_Memory_Type */ |
132 | |
| 133 | 133 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
|
| 134 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
134 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| 135 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
135 | |
| 136 | 136 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
|
| 137 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
137 | valid only with synchronous burst Flash memories. |
| 138 | valid only with synchronous burst Flash memories. |
138 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| 139 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
139 | |
| 140 | 140 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
|
| 141 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
141 | the Flash memory in burst mode. |
| 142 | the Flash memory in burst mode. |
142 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| 143 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
143 | |
| 144 | 144 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
|
| 145 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
145 | memory, valid only when accessing Flash memories in burst mode. |
| 146 | memory, valid only when accessing Flash memories in burst mode. |
146 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| 147 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
147 | |
| 148 | 148 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
|
| 149 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
149 | clock cycle before the wait state or during the wait state, |
| 150 | clock cycle before the wait state or during the wait state, |
150 | valid only when accessing memories in burst mode. |
| 151 | valid only when accessing memories in burst mode. |
151 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| 152 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
152 | |
| 153 | 153 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
|
| 154 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
154 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| 155 | This parameter can be a value of @ref FSMC_Write_Operation */ |
155 | |
| 156 | 156 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
|
| 157 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
157 | signal, valid for Flash memory access in burst mode. |
| 158 | signal, valid for Flash memory access in burst mode. |
158 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| 159 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
159 | |
| 160 | 160 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
|
| 161 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
161 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| 162 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
162 | |
| 163 | 163 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
|
| 164 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
164 | valid only with asynchronous Flash memories. |
| 165 | valid only with asynchronous Flash memories. |
165 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| 166 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
166 | |
| 167 | 167 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
|
| 168 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
168 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| 169 | This parameter can be a value of @ref FSMC_Write_Burst */ |
169 | |
| 170 | 170 | ||
| 171 | 171 | uint32_t PageSize; /*!< Specifies the memory page size. |
|
| 172 | uint32_t PageSize; /*!< Specifies the memory page size. |
172 | This parameter can be a value of @ref FSMC_Page_Size */ |
| 173 | This parameter can be a value of @ref FSMC_Page_Size */ |
173 | } FSMC_NORSRAM_InitTypeDef; |
| 174 | } FSMC_NORSRAM_InitTypeDef; |
174 | |
| 175 | 175 | /** |
|
| 176 | /** |
176 | * @brief FSMC NORSRAM Timing parameters structure definition |
| 177 | * @brief FSMC NORSRAM Timing parameters structure definition |
177 | */ |
| 178 | */ |
178 | typedef struct |
| 179 | typedef struct |
179 | { |
| 180 | { |
180 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| 181 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
181 | the duration of the address setup time. |
| 182 | the duration of the address setup time. |
182 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| 183 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
183 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| 184 | @note This parameter is not used with synchronous NOR Flash memories. */ |
184 | |
| 185 | 185 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
|
| 186 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
186 | the duration of the address hold time. |
| 187 | the duration of the address hold time. |
187 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| 188 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
188 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| 189 | @note This parameter is not used with synchronous NOR Flash memories. */ |
189 | |
| 190 | 190 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
|
| 191 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
191 | the duration of the data setup time. |
| 192 | the duration of the data setup time. |
192 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| 193 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
193 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| 194 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
194 | NOR Flash memories. */ |
| 195 | NOR Flash memories. */ |
195 | |
| 196 | 196 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
|
| 197 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
197 | the duration of the bus turnaround. |
| 198 | the duration of the bus turnaround. |
198 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| 199 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
199 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| 200 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
200 | |
| 201 | 201 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
|
| 202 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
202 | HCLK cycles. This parameter can be a value between Min_Data = 2 and |
| 203 | HCLK cycles. This parameter can be a value between Min_Data = 2 and |
203 | Max_Data = 16. |
| 204 | Max_Data = 16. |
204 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| 205 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
205 | accesses. */ |
| 206 | accesses. */ |
206 | |
| 207 | 207 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
|
| 208 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
208 | to the memory before getting the first data. |
| 209 | to the memory before getting the first data. |
209 | The parameter value depends on the memory type as shown below: |
| 210 | The parameter value depends on the memory type as shown below: |
210 | - It must be set to 0 in case of a CRAM |
| 211 | - It must be set to 0 in case of a CRAM |
211 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| 212 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
212 | - It may assume a value between Min_Data = 2 and Max_Data = 17 |
| 213 | - It may assume a value between Min_Data = 2 and Max_Data = 17 |
213 | in NOR Flash memories with synchronous burst mode enable */ |
| 214 | in NOR Flash memories with synchronous burst mode enable */ |
214 | |
| 215 | 215 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
|
| 216 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
216 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| 217 | This parameter can be a value of @ref FSMC_Access_Mode */ |
217 | } FSMC_NORSRAM_TimingTypeDef; |
| 218 | } FSMC_NORSRAM_TimingTypeDef; |
218 | #endif /* FSMC_BANK1 */ |
| 219 | #endif /* FSMC_BANK1 */ |
219 | |
| 220 | 220 | ||
| 221 | 221 | ||
| 222 | 222 | ||
| 223 | 223 | /** |
|
| 224 | /** |
224 | * @} |
| 225 | * @} |
225 | */ |
| 226 | */ |
226 | |
| 227 | 227 | /* Exported constants --------------------------------------------------------*/ |
|
| 228 | /* Exported constants --------------------------------------------------------*/ |
228 | /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants |
| 229 | /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants |
229 | * @{ |
| 230 | * @{ |
230 | */ |
| 231 | */ |
231 | #if defined(FSMC_BANK1) |
| 232 | #if defined(FSMC_BANK1) |
232 | |
| 233 | 233 | /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
|
| 234 | /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
234 | * @{ |
| 235 | * @{ |
235 | */ |
| 236 | */ |
236 | |
| 237 | 237 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
|
| 238 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
238 | * @{ |
| 239 | * @{ |
239 | */ |
| 240 | */ |
240 | #define FSMC_NORSRAM_BANK1 (0x00000000U) |
| 241 | #define FSMC_NORSRAM_BANK1 (0x00000000U) |
241 | #define FSMC_NORSRAM_BANK2 (0x00000002U) |
| 242 | #define FSMC_NORSRAM_BANK2 (0x00000002U) |
242 | #define FSMC_NORSRAM_BANK3 (0x00000004U) |
| 243 | #define FSMC_NORSRAM_BANK3 (0x00000004U) |
243 | #define FSMC_NORSRAM_BANK4 (0x00000006U) |
| 244 | #define FSMC_NORSRAM_BANK4 (0x00000006U) |
244 | /** |
| 245 | /** |
245 | * @} |
| 246 | * @} |
246 | */ |
| 247 | */ |
247 | |
| 248 | 248 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
|
| 249 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
249 | * @{ |
| 250 | * @{ |
250 | */ |
| 251 | */ |
251 | #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) |
| 252 | #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) |
252 | #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) |
| 253 | #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) |
253 | /** |
| 254 | /** |
254 | * @} |
| 255 | * @} |
255 | */ |
| 256 | */ |
256 | |
| 257 | 257 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
|
| 258 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
258 | * @{ |
| 259 | * @{ |
259 | */ |
| 260 | */ |
260 | #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) |
| 261 | #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) |
261 | #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) |
| 262 | #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) |
262 | #define FSMC_MEMORY_TYPE_NOR (0x00000008U) |
| 263 | #define FSMC_MEMORY_TYPE_NOR (0x00000008U) |
263 | /** |
| 264 | /** |
264 | * @} |
| 265 | * @} |
265 | */ |
| 266 | */ |
266 | |
| 267 | 267 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width |
|
| 268 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width |
268 | * @{ |
| 269 | * @{ |
269 | */ |
| 270 | */ |
270 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) |
| 271 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) |
271 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) |
| 272 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) |
272 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) |
| 273 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) |
273 | /** |
| 274 | /** |
274 | * @} |
| 275 | * @} |
275 | */ |
| 276 | */ |
276 | |
| 277 | 277 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
|
| 278 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
278 | * @{ |
| 279 | * @{ |
279 | */ |
| 280 | */ |
280 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) |
| 281 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) |
281 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) |
| 282 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) |
282 | /** |
| 283 | /** |
283 | * @} |
| 284 | * @} |
284 | */ |
| 285 | */ |
285 | |
| 286 | 286 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
|
| 287 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
287 | * @{ |
| 288 | * @{ |
288 | */ |
| 289 | */ |
289 | #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) |
| 290 | #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) |
290 | #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) |
| 291 | #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) |
291 | /** |
| 292 | /** |
292 | * @} |
| 293 | * @} |
293 | */ |
| 294 | */ |
294 | |
| 295 | 295 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
|
| 296 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
296 | * @{ |
| 297 | * @{ |
297 | */ |
| 298 | */ |
298 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) |
| 299 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) |
299 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) |
| 300 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) |
300 | /** |
| 301 | /** |
301 | * @} |
| 302 | * @} |
302 | */ |
| 303 | */ |
303 | |
| 304 | 304 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
|
| 305 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
305 | * @{ |
| 306 | * @{ |
306 | */ |
| 307 | */ |
307 | #define FSMC_WRAP_MODE_DISABLE (0x00000000U) |
| 308 | #define FSMC_WRAP_MODE_DISABLE (0x00000000U) |
308 | #define FSMC_WRAP_MODE_ENABLE (0x00000400U) |
| 309 | #define FSMC_WRAP_MODE_ENABLE (0x00000400U) |
309 | /** |
| 310 | /** |
310 | * @} |
| 311 | * @} |
311 | */ |
| 312 | */ |
312 | |
| 313 | 313 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
|
| 314 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
314 | * @{ |
| 315 | * @{ |
315 | */ |
| 316 | */ |
316 | #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) |
| 317 | #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) |
317 | #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) |
| 318 | #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) |
318 | /** |
| 319 | /** |
319 | * @} |
| 320 | * @} |
320 | */ |
| 321 | */ |
321 | |
| 322 | 322 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
|
| 323 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
323 | * @{ |
| 324 | * @{ |
324 | */ |
| 325 | */ |
325 | #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) |
| 326 | #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) |
326 | #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) |
| 327 | #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) |
327 | /** |
| 328 | /** |
328 | * @} |
| 329 | * @} |
329 | */ |
| 330 | */ |
330 | |
| 331 | 331 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
|
| 332 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
332 | * @{ |
| 333 | * @{ |
333 | */ |
| 334 | */ |
334 | #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) |
| 335 | #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) |
335 | #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) |
| 336 | #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) |
336 | /** |
| 337 | /** |
337 | * @} |
| 338 | * @} |
338 | */ |
| 339 | */ |
339 | |
| 340 | 340 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
|
| 341 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
341 | * @{ |
| 342 | * @{ |
342 | */ |
| 343 | */ |
343 | #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) |
| 344 | #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) |
344 | #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) |
| 345 | #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) |
345 | /** |
| 346 | /** |
346 | * @} |
| 347 | * @} |
347 | */ |
| 348 | */ |
348 | |
| 349 | 349 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
|
| 350 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
350 | * @{ |
| 351 | * @{ |
351 | */ |
| 352 | */ |
352 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) |
| 353 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) |
353 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) |
| 354 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) |
354 | /** |
| 355 | /** |
355 | * @} |
| 356 | * @} |
356 | */ |
| 357 | */ |
357 | |
| 358 | 358 | /** @defgroup FSMC_Page_Size FSMC Page Size |
|
| 359 | /** @defgroup FSMC_Page_Size FSMC Page Size |
359 | * @{ |
| 360 | * @{ |
360 | */ |
| 361 | */ |
361 | #define FSMC_PAGE_SIZE_NONE (0x00000000U) |
| 362 | #define FSMC_PAGE_SIZE_NONE (0x00000000U) |
362 | #define FSMC_PAGE_SIZE_128 FSMC_BCRx_CPSIZE_0 |
| 363 | #define FSMC_PAGE_SIZE_128 FSMC_BCRx_CPSIZE_0 |
363 | #define FSMC_PAGE_SIZE_256 FSMC_BCRx_CPSIZE_1 |
| 364 | #define FSMC_PAGE_SIZE_256 FSMC_BCRx_CPSIZE_1 |
364 | #define FSMC_PAGE_SIZE_512 (FSMC_BCRx_CPSIZE_0\ |
| 365 | #define FSMC_PAGE_SIZE_512 (FSMC_BCRx_CPSIZE_0\ |
365 | | FSMC_BCRx_CPSIZE_1) |
| 366 | | FSMC_BCRx_CPSIZE_1) |
366 | #define FSMC_PAGE_SIZE_1024 FSMC_BCRx_CPSIZE_2 |
| 367 | #define FSMC_PAGE_SIZE_1024 FSMC_BCRx_CPSIZE_2 |
367 | /** |
| 368 | /** |
368 | * @} |
| 369 | * @} |
369 | */ |
| 370 | */ |
370 | |
| 371 | 371 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
|
| 372 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
372 | * @{ |
| 373 | * @{ |
373 | */ |
| 374 | */ |
374 | #define FSMC_WRITE_BURST_DISABLE (0x00000000U) |
| 375 | #define FSMC_WRITE_BURST_DISABLE (0x00000000U) |
375 | #define FSMC_WRITE_BURST_ENABLE (0x00080000U) |
| 376 | #define FSMC_WRITE_BURST_ENABLE (0x00080000U) |
376 | /** |
| 377 | /** |
377 | * @} |
| 378 | * @} |
378 | */ |
| 379 | */ |
379 | |
| 380 | 380 | /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock |
|
| 381 | /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock |
381 | * @{ |
| 382 | * @{ |
382 | */ |
| 383 | */ |
383 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) |
| 384 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) |
384 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) |
| 385 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) |
385 | /** |
| 386 | /** |
386 | * @} |
| 387 | * @} |
387 | */ |
| 388 | */ |
388 | |
| 389 | 389 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
|
| 390 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
390 | * @{ |
| 391 | * @{ |
391 | */ |
| 392 | */ |
392 | #define FSMC_ACCESS_MODE_A (0x00000000U) |
| 393 | #define FSMC_ACCESS_MODE_A (0x00000000U) |
393 | #define FSMC_ACCESS_MODE_B (0x10000000U) |
| 394 | #define FSMC_ACCESS_MODE_B (0x10000000U) |
394 | #define FSMC_ACCESS_MODE_C (0x20000000U) |
| 395 | #define FSMC_ACCESS_MODE_C (0x20000000U) |
395 | #define FSMC_ACCESS_MODE_D (0x30000000U) |
| 396 | #define FSMC_ACCESS_MODE_D (0x30000000U) |
396 | /** |
| 397 | /** |
397 | * @} |
| 398 | * @} |
398 | */ |
| 399 | */ |
399 | |
| 400 | 400 | /** |
|
| 401 | /** |
401 | * @} |
| 402 | * @} |
402 | */ |
| 403 | */ |
403 | #endif /* FSMC_BANK1 */ |
| 404 | #endif /* FSMC_BANK1 */ |
404 | |
| 405 | 405 | ||
| 406 | 406 | ||
| 407 | 407 | /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition |
|
| 408 | /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition |
408 | * @{ |
| 409 | * @{ |
409 | */ |
| 410 | */ |
410 | /** |
| 411 | /** |
411 | * @} |
| 412 | * @} |
412 | */ |
| 413 | */ |
413 | |
| 414 | 414 | /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition |
|
| 415 | /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition |
415 | * @{ |
| 416 | * @{ |
416 | */ |
| 417 | */ |
417 | /** |
| 418 | /** |
418 | * @} |
| 419 | * @} |
419 | */ |
| 420 | */ |
420 | |
| 421 | 421 | /** |
|
| 422 | /** |
422 | * @} |
| 423 | * @} |
423 | */ |
| 424 | */ |
424 | |
| 425 | 425 | /** |
|
| 426 | /** |
426 | * @} |
| 427 | * @} |
427 | */ |
| 428 | */ |
428 | |
| 429 | 429 | /* Private macro -------------------------------------------------------------*/ |
|
| 430 | /* Private macro -------------------------------------------------------------*/ |
430 | /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros |
| 431 | /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros |
431 | * @{ |
| 432 | * @{ |
432 | */ |
| 433 | */ |
433 | #if defined(FSMC_BANK1) |
| 434 | #if defined(FSMC_BANK1) |
434 | /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros |
| 435 | /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros |
435 | * @brief macros to handle NOR device enable/disable and read/write operations |
| 436 | * @brief macros to handle NOR device enable/disable and read/write operations |
436 | * @{ |
| 437 | * @{ |
437 | */ |
| 438 | */ |
438 | |
| 439 | 439 | /** |
|
| 440 | /** |
440 | * @brief Enable the NORSRAM device access. |
| 441 | * @brief Enable the NORSRAM device access. |
441 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
| 442 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
442 | * @param __BANK__ FSMC_NORSRAM Bank |
| 443 | * @param __BANK__ FSMC_NORSRAM Bank |
443 | * @retval None |
| 444 | * @retval None |
444 | */ |
| 445 | */ |
445 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
| 446 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
446 | |= FSMC_BCRx_MBKEN) |
| 447 | |= FSMC_BCRx_MBKEN) |
447 | |
| 448 | 448 | /** |
|
| 449 | /** |
449 | * @brief Disable the NORSRAM device access. |
| 450 | * @brief Disable the NORSRAM device access. |
450 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
| 451 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
451 | * @param __BANK__ FSMC_NORSRAM Bank |
| 452 | * @param __BANK__ FSMC_NORSRAM Bank |
452 | * @retval None |
| 453 | * @retval None |
453 | */ |
| 454 | */ |
454 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
| 455 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
455 | &= ~FSMC_BCRx_MBKEN) |
| 456 | &= ~FSMC_BCRx_MBKEN) |
456 | |
| 457 | 457 | /** |
|
| 458 | /** |
458 | * @} |
| 459 | * @} |
459 | */ |
| 460 | */ |
460 | #endif /* FSMC_BANK1 */ |
| 461 | #endif /* FSMC_BANK1 */ |
461 | |
| 462 | 462 | ||
| 463 | 463 | ||
| 464 | 464 | ||
| 465 | 465 | /** |
|
| 466 | /** |
466 | * @} |
| 467 | * @} |
467 | */ |
| 468 | */ |
468 | |
| 469 | 469 | /** |
|
| 470 | /** |
470 | * @} |
| 471 | * @} |
471 | */ |
| 472 | */ |
472 | |
| 473 | 473 | /* Private functions ---------------------------------------------------------*/ |
|
| 474 | /* Private functions ---------------------------------------------------------*/ |
474 | /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
| 475 | /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
475 | * @{ |
| 476 | * @{ |
476 | */ |
| 477 | */ |
477 | |
| 478 | 478 | #if defined(FSMC_BANK1) |
|
| 479 | #if defined(FSMC_BANK1) |
479 | /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
| 480 | /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
480 | * @{ |
| 481 | * @{ |
481 | */ |
| 482 | */ |
482 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
| 483 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
483 | * @{ |
| 484 | * @{ |
484 | */ |
| 485 | */ |
485 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, |
| 486 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, |
486 | FSMC_NORSRAM_InitTypeDef *Init); |
| 487 | FSMC_NORSRAM_InitTypeDef *Init); |
487 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, |
| 488 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, |
488 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| 489 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
489 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, |
| 490 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, |
490 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, |
| 491 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, |
491 | uint32_t ExtendedMode); |
| 492 | uint32_t ExtendedMode); |
492 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, |
| 493 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, |
493 | FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| 494 | FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
494 | /** |
| 495 | /** |
495 | * @} |
| 496 | * @} |
496 | */ |
| 497 | */ |
497 | |
| 498 | 498 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
|
| 499 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
499 | * @{ |
| 500 | * @{ |
500 | */ |
| 501 | */ |
501 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| 502 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
502 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| 503 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
503 | /** |
| 504 | /** |
504 | * @} |
| 505 | * @} |
505 | */ |
| 506 | */ |
506 | /** |
| 507 | /** |
507 | * @} |
| 508 | * @} |
508 | */ |
| 509 | */ |
509 | #endif /* FSMC_BANK1 */ |
| 510 | #endif /* FSMC_BANK1 */ |
510 | |
| 511 | 511 | ||
| 512 | 512 | ||
| 513 | 513 | ||
| 514 | 514 | /** |
|
| 515 | /** |
515 | * @} |
| 516 | * @} |
516 | */ |
| 517 | */ |
517 | |
| 518 | 518 | /** |
|
| 519 | /** |
519 | * @} |
| 520 | * @} |
520 | */ |
| 521 | */ |
521 | |
| 522 | 522 | /** |
|
| 523 | /** |
523 | * @} |
| 524 | * @} |
524 | */ |
| 525 | */ |
525 | |
| 526 | 526 | #ifdef __cplusplus |
|
| 527 | #ifdef __cplusplus |
527 | } |
| 528 | } |
528 | #endif |
| 529 | #endif |
529 | |
| 530 | 530 | #endif /* STM32L1xx_LL_FSMC_H */ |
|
| 531 | #endif /* STM32L1xx_LL_FSMC_H */ |
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| 532 | - | ||
| 533 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |