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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_dac.h |
3 | * @file stm32l1xx_ll_dac.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of DAC LL module. |
5 | * @brief Header file of DAC LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32L1xx_LL_DAC_H |
| 21 | #ifndef STM32L1xx_LL_DAC_H |
21 | #define STM32L1xx_LL_DAC_H |
| 22 | #define STM32L1xx_LL_DAC_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32l1xx.h" |
| 29 | #include "stm32l1xx.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined(DAC1) |
|
| 35 | #if defined(DAC1) |
35 | |
| 36 | 36 | /** @defgroup DAC_LL DAC |
|
| 37 | /** @defgroup DAC_LL DAC |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | |
| 43 | 43 | /* Private constants ---------------------------------------------------------*/ |
|
| 44 | /* Private constants ---------------------------------------------------------*/ |
44 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
| 45 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
45 | * @{ |
| 46 | * @{ |
46 | */ |
| 47 | */ |
47 | |
| 48 | 48 | /* Internal masks for DAC channels definition */ |
|
| 49 | /* Internal masks for DAC channels definition */ |
49 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
| 50 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
50 | /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ |
| 51 | /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ |
51 | /* - channel bits position into register SWTRIG */ |
| 52 | /* - channel bits position into register SWTRIG */ |
52 | /* - channel register offset of data holding register DHRx */ |
| 53 | /* - channel register offset of data holding register DHRx */ |
53 | /* - channel register offset of data output register DORx */ |
| 54 | /* - channel register offset of data output register DORx */ |
54 | #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers |
| 55 | #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers |
55 | CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
| 56 | CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
56 | #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers |
| 57 | #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers |
57 | CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
| 58 | CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
58 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
| 59 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
59 | |
| 60 | 60 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ |
|
| 61 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ |
61 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ |
| 62 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ |
62 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
| 63 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
63 | |
| 64 | 64 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ |
|
| 65 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ |
65 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus |
| 66 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus |
66 | DHR12Rx channel 1 (shifted left of 20 bits) */ |
| 67 | DHR12Rx channel 1 (shifted left of 20 bits) */ |
67 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus |
| 68 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus |
68 | DHR12Rx channel 1 (shifted left of 24 bits) */ |
| 69 | DHR12Rx channel 1 (shifted left of 24 bits) */ |
69 | |
| 70 | 70 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus |
|
| 71 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus |
71 | DHR12Rx channel 1 (shifted left of 16 bits) */ |
| 72 | DHR12Rx channel 1 (shifted left of 16 bits) */ |
72 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus |
| 73 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus |
73 | DHR12Rx channel 1 (shifted left of 20 bits) */ |
| 74 | DHR12Rx channel 1 (shifted left of 20 bits) */ |
74 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus |
| 75 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus |
75 | DHR12Rx channel 1 (shifted left of 24 bits) */ |
| 76 | DHR12Rx channel 1 (shifted left of 24 bits) */ |
76 | |
| 77 | 77 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL |
|
| 78 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL |
78 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL |
| 79 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL |
79 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL |
| 80 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL |
80 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ |
| 81 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ |
81 | | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
| 82 | | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
82 | |
| 83 | 83 | #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ |
|
| 84 | #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ |
84 | |
| 85 | 85 | #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus |
|
| 86 | #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus |
86 | DORx channel 2 (shifted left of 28 bits) */ |
| 87 | DORx channel 2 (shifted left of 28 bits) */ |
87 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
| 88 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
88 | |
| 89 | 89 | ||
| 90 | 90 | ||
| 91 | 91 | #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, |
|
| 92 | #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, |
92 | DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ |
| 93 | DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ |
93 | #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted |
| 94 | #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted |
94 | to position 0 */ |
| 95 | to position 0 */ |
95 | #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted |
| 96 | #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted |
96 | to position 0 */ |
| 97 | to position 0 */ |
97 | |
| 98 | 98 | #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx |
|
| 99 | #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx |
99 | channel 1 or 2 versus DHR12Rx channel 1 |
| 100 | channel 1 or 2 versus DHR12Rx channel 1 |
100 | (shifted left of 16 bits) */ |
| 101 | (shifted left of 16 bits) */ |
101 | #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx |
| 102 | #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx |
102 | channel 1 or 2 versus DHR12Rx channel 1 |
| 103 | channel 1 or 2 versus DHR12Rx channel 1 |
103 | (shifted left of 20 bits) */ |
| 104 | (shifted left of 20 bits) */ |
104 | #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx |
| 105 | #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx |
105 | channel 1 or 2 versus DHR12Rx channel 1 |
| 106 | channel 1 or 2 versus DHR12Rx channel 1 |
106 | (shifted left of 24 bits) */ |
| 107 | (shifted left of 24 bits) */ |
107 | #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx |
| 108 | #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx |
108 | channel 1 or 2 versus DORx channel 1 |
| 109 | channel 1 or 2 versus DORx channel 1 |
109 | (shifted left of 28 bits) */ |
| 110 | (shifted left of 28 bits) */ |
110 | |
| 111 | 111 | /* DAC registers bits positions */ |
|
| 112 | /* DAC registers bits positions */ |
112 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos |
| 113 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos |
113 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos |
| 114 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos |
114 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos |
| 115 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos |
115 | |
| 116 | 116 | /* Miscellaneous data */ |
|
| 117 | /* Miscellaneous data */ |
117 | #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 |
| 118 | #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 |
118 | bits (voltage range determined by analog voltage |
| 119 | bits (voltage range determined by analog voltage |
119 | references Vref+ and Vref-, refer to reference manual) */ |
| 120 | references Vref+ and Vref-, refer to reference manual) */ |
120 | |
| 121 | 121 | /** |
|
| 122 | /** |
122 | * @} |
| 123 | * @} |
123 | */ |
| 124 | */ |
124 | |
| 125 | 125 | ||
| 126 | 126 | /* Private macros ------------------------------------------------------------*/ |
|
| 127 | /* Private macros ------------------------------------------------------------*/ |
127 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
| 128 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
128 | * @{ |
| 129 | * @{ |
129 | */ |
| 130 | */ |
130 | |
| 131 | 131 | /** |
|
| 132 | /** |
132 | * @brief Driver macro reserved for internal use: set a pointer to |
| 133 | * @brief Driver macro reserved for internal use: set a pointer to |
133 | * a register from a register basis from which an offset |
| 134 | * a register from a register basis from which an offset |
134 | * is applied. |
| 135 | * is applied. |
135 | * @param __REG__ Register basis from which the offset is applied. |
| 136 | * @param __REG__ Register basis from which the offset is applied. |
136 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
| 137 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
137 | * @retval Pointer to register address |
| 138 | * @retval Pointer to register address |
138 | */ |
| 139 | */ |
139 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
| 140 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
140 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) |
| 141 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) |
141 | |
| 142 | 142 | /** |
|
| 143 | /** |
143 | * @} |
| 144 | * @} |
144 | */ |
| 145 | */ |
145 | |
| 146 | 146 | ||
| 147 | 147 | /* Exported types ------------------------------------------------------------*/ |
|
| 148 | /* Exported types ------------------------------------------------------------*/ |
148 | #if defined(USE_FULL_LL_DRIVER) |
| 149 | #if defined(USE_FULL_LL_DRIVER) |
149 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
| 150 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
150 | * @{ |
| 151 | * @{ |
151 | */ |
| 152 | */ |
152 | |
| 153 | 153 | /** |
|
| 154 | /** |
154 | * @brief Structure definition of some features of DAC instance. |
| 155 | * @brief Structure definition of some features of DAC instance. |
155 | */ |
| 156 | */ |
156 | typedef struct |
| 157 | typedef struct |
157 | { |
| 158 | { |
158 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: |
| 159 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: |
159 | internal (SW start) or from external peripheral |
| 160 | internal (SW start) or from external peripheral |
160 | (timer event, external interrupt line). |
| 161 | (timer event, external interrupt line). |
161 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
| 162 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
162 | |
| 163 | 163 | This feature can be modified afterwards using unitary |
|
| 164 | This feature can be modified afterwards using unitary |
164 | function @ref LL_DAC_SetTriggerSource(). */ |
| 165 | function @ref LL_DAC_SetTriggerSource(). */ |
165 | |
| 166 | 166 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
|
| 167 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
167 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
| 168 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
168 | |
| 169 | 169 | This feature can be modified afterwards using unitary |
|
| 170 | This feature can be modified afterwards using unitary |
170 | function @ref LL_DAC_SetWaveAutoGeneration(). */ |
| 171 | function @ref LL_DAC_SetWaveAutoGeneration(). */ |
171 | |
| 172 | 172 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
|
| 173 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
173 | If waveform automatic generation mode is set to noise, this parameter |
| 174 | If waveform automatic generation mode is set to noise, this parameter |
174 | can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
| 175 | can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
175 | If waveform automatic generation mode is set to triangle, |
| 176 | If waveform automatic generation mode is set to triangle, |
176 | this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
| 177 | this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
177 | @note If waveform automatic generation mode is disabled, |
| 178 | @note If waveform automatic generation mode is disabled, |
178 | this parameter is discarded. |
| 179 | this parameter is discarded. |
179 | |
| 180 | 180 | This feature can be modified afterwards using unitary |
|
| 181 | This feature can be modified afterwards using unitary |
181 | function @ref LL_DAC_SetWaveNoiseLFSR(), |
| 182 | function @ref LL_DAC_SetWaveNoiseLFSR(), |
182 | @ref LL_DAC_SetWaveTriangleAmplitude() |
| 183 | @ref LL_DAC_SetWaveTriangleAmplitude() |
183 | depending on the wave automatic generation selected. */ |
| 184 | depending on the wave automatic generation selected. */ |
184 | |
| 185 | 185 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
|
| 186 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
186 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
| 187 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
187 | |
| 188 | 188 | This feature can be modified afterwards using unitary |
|
| 189 | This feature can be modified afterwards using unitary |
189 | function @ref LL_DAC_SetOutputBuffer(). */ |
| 190 | function @ref LL_DAC_SetOutputBuffer(). */ |
190 | } LL_DAC_InitTypeDef; |
| 191 | } LL_DAC_InitTypeDef; |
191 | |
| 192 | 192 | /** |
|
| 193 | /** |
193 | * @} |
| 194 | * @} |
194 | */ |
| 195 | */ |
195 | #endif /* USE_FULL_LL_DRIVER */ |
| 196 | #endif /* USE_FULL_LL_DRIVER */ |
196 | |
| 197 | 197 | /* Exported constants --------------------------------------------------------*/ |
|
| 198 | /* Exported constants --------------------------------------------------------*/ |
198 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
| 199 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
199 | * @{ |
| 200 | * @{ |
200 | */ |
| 201 | */ |
201 | |
| 202 | 202 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
|
| 203 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
203 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
| 204 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
204 | * @{ |
| 205 | * @{ |
205 | */ |
| 206 | */ |
206 | /* DAC channel 1 flags */ |
| 207 | /* DAC channel 1 flags */ |
207 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
| 208 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
208 | |
| 209 | 209 | /* DAC channel 2 flags */ |
|
| 210 | /* DAC channel 2 flags */ |
210 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
| 211 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
211 | |
| 212 | 212 | /** |
|
| 213 | /** |
213 | * @} |
| 214 | * @} |
214 | */ |
| 215 | */ |
215 | |
| 216 | 216 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
|
| 217 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
217 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
| 218 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
218 | * @{ |
| 219 | * @{ |
219 | */ |
| 220 | */ |
220 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
| 221 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
221 | |
| 222 | 222 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
|
| 223 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
223 | |
| 224 | 224 | /** |
|
| 225 | /** |
225 | * @} |
| 226 | * @} |
226 | */ |
| 227 | */ |
227 | |
| 228 | 228 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
|
| 229 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
229 | * @{ |
| 230 | * @{ |
230 | */ |
| 231 | */ |
231 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
| 232 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
232 | |
| 233 | 233 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
|
| 234 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
234 | |
| 235 | 235 | /** |
|
| 236 | /** |
236 | * @} |
| 237 | * @} |
237 | */ |
| 238 | */ |
238 | |
| 239 | 239 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
|
| 240 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
240 | * @{ |
| 241 | * @{ |
241 | */ |
| 242 | */ |
242 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
| 243 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
243 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ |
| 244 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ |
244 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ |
| 245 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ |
245 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ |
| 246 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ |
246 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ |
| 247 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ |
247 | #define LL_DAC_TRIG_EXT_TIM9_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ |
| 248 | #define LL_DAC_TRIG_EXT_TIM9_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ |
248 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ |
| 249 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ |
249 | /** |
| 250 | /** |
250 | * @} |
| 251 | * @} |
251 | */ |
| 252 | */ |
252 | |
| 253 | 253 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
|
| 254 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
254 | * @{ |
| 255 | * @{ |
255 | */ |
| 256 | */ |
256 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ |
| 257 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ |
257 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
| 258 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
258 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
| 259 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
259 | /** |
| 260 | /** |
260 | * @} |
| 261 | * @} |
261 | */ |
| 262 | */ |
262 | |
| 263 | 263 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
|
| 264 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
264 | * @{ |
| 265 | * @{ |
265 | */ |
| 266 | */ |
266 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
| 267 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
267 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
| 268 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
268 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
| 269 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
269 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
| 270 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
270 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
| 271 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
271 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
| 272 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
272 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
| 273 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
273 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
| 274 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
274 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
| 275 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
275 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
| 276 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
276 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
| 277 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
277 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
| 278 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
278 | /** |
| 279 | /** |
279 | * @} |
| 280 | * @} |
280 | */ |
| 281 | */ |
281 | |
| 282 | 282 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
|
| 283 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
283 | * @{ |
| 284 | * @{ |
284 | */ |
| 285 | */ |
285 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
| 286 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
286 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
| 287 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
287 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
| 288 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
288 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
| 289 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
289 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
| 290 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
290 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
| 291 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
291 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
| 292 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
292 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
| 293 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
293 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
| 294 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
294 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
| 295 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
295 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
| 296 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
296 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
| 297 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
297 | /** |
| 298 | /** |
298 | * @} |
| 299 | * @} |
299 | */ |
| 300 | */ |
300 | |
| 301 | 301 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
|
| 302 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
302 | * @{ |
| 303 | * @{ |
303 | */ |
| 304 | */ |
304 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
| 305 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
305 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
| 306 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
306 | /** |
| 307 | /** |
307 | * @} |
| 308 | * @} |
308 | */ |
| 309 | */ |
309 | |
| 310 | 310 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
|
| 311 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
311 | * @{ |
| 312 | * @{ |
312 | */ |
| 313 | */ |
313 | #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ |
| 314 | #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ |
314 | #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ |
| 315 | #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ |
315 | /** |
| 316 | /** |
316 | * @} |
| 317 | * @} |
317 | */ |
| 318 | */ |
318 | |
| 319 | 319 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
|
| 320 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
320 | * @{ |
| 321 | * @{ |
321 | */ |
| 322 | */ |
322 | /* List of DAC registers intended to be used (most commonly) with */ |
| 323 | /* List of DAC registers intended to be used (most commonly) with */ |
323 | /* DMA transfer. */ |
| 324 | /* DMA transfer. */ |
324 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
| 325 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
325 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ |
| 326 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ |
326 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ |
| 327 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ |
327 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ |
| 328 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ |
328 | /** |
| 329 | /** |
329 | * @} |
| 330 | * @} |
330 | */ |
| 331 | */ |
331 | |
| 332 | 332 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
|
| 333 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
333 | * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, |
| 334 | * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, |
334 | * not timeout values. |
| 335 | * not timeout values. |
335 | * For details on delays values, refer to descriptions in source code |
| 336 | * For details on delays values, refer to descriptions in source code |
336 | * above each literal definition. |
| 337 | * above each literal definition. |
337 | * @{ |
| 338 | * @{ |
338 | */ |
| 339 | */ |
339 | |
| 340 | 340 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
|
| 341 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
341 | /* (transition from disable to enable). */ |
| 342 | /* (transition from disable to enable). */ |
342 | /* Note: DAC channel startup time depends on board application environment: */ |
| 343 | /* Note: DAC channel startup time depends on board application environment: */ |
343 | /* impedance connected to DAC channel output. */ |
| 344 | /* impedance connected to DAC channel output. */ |
344 | /* The delay below is specified under conditions: */ |
| 345 | /* The delay below is specified under conditions: */ |
345 | /* - voltage maximum transition (lowest to highest value) */ |
| 346 | /* - voltage maximum transition (lowest to highest value) */ |
346 | /* - until voltage reaches final value +-1LSB */ |
| 347 | /* - until voltage reaches final value +-1LSB */ |
347 | /* - DAC channel output buffer enabled */ |
| 348 | /* - DAC channel output buffer enabled */ |
348 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
| 349 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
349 | /* Literal set to maximum value (refer to device datasheet, */ |
| 350 | /* Literal set to maximum value (refer to device datasheet, */ |
350 | /* parameter "tWAKEUP"). */ |
| 351 | /* parameter "tWAKEUP"). */ |
351 | /* Unit: us */ |
| 352 | /* Unit: us */ |
352 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
| 353 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
353 | |
| 354 | 354 | /* Delay for DAC channel voltage settling time. */ |
|
| 355 | /* Delay for DAC channel voltage settling time. */ |
355 | /* Note: DAC channel startup time depends on board application environment: */ |
| 356 | /* Note: DAC channel startup time depends on board application environment: */ |
356 | /* impedance connected to DAC channel output. */ |
| 357 | /* impedance connected to DAC channel output. */ |
357 | /* The delay below is specified under conditions: */ |
| 358 | /* The delay below is specified under conditions: */ |
358 | /* - voltage maximum transition (lowest to highest value) */ |
| 359 | /* - voltage maximum transition (lowest to highest value) */ |
359 | /* - until voltage reaches final value +-1LSB */ |
| 360 | /* - until voltage reaches final value +-1LSB */ |
360 | /* - DAC channel output buffer enabled */ |
| 361 | /* - DAC channel output buffer enabled */ |
361 | /* - load impedance of 5kOhm min, 50pF max */ |
| 362 | /* - load impedance of 5kOhm min, 50pF max */ |
362 | /* Literal set to maximum value (refer to device datasheet, */ |
| 363 | /* Literal set to maximum value (refer to device datasheet, */ |
363 | /* parameter "tSETTLING"). */ |
| 364 | /* parameter "tSETTLING"). */ |
364 | /* Unit: us */ |
| 365 | /* Unit: us */ |
365 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ |
| 366 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ |
366 | |
| 367 | 367 | /** |
|
| 368 | /** |
368 | * @} |
| 369 | * @} |
369 | */ |
| 370 | */ |
370 | |
| 371 | 371 | /** |
|
| 372 | /** |
372 | * @} |
| 373 | * @} |
373 | */ |
| 374 | */ |
374 | |
| 375 | 375 | /* Exported macro ------------------------------------------------------------*/ |
|
| 376 | /* Exported macro ------------------------------------------------------------*/ |
376 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
| 377 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
377 | * @{ |
| 378 | * @{ |
378 | */ |
| 379 | */ |
379 | |
| 380 | 380 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
|
| 381 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
381 | * @{ |
| 382 | * @{ |
382 | */ |
| 383 | */ |
383 | |
| 384 | 384 | /** |
|
| 385 | /** |
385 | * @brief Write a value in DAC register |
| 386 | * @brief Write a value in DAC register |
386 | * @param __INSTANCE__ DAC Instance |
| 387 | * @param __INSTANCE__ DAC Instance |
387 | * @param __REG__ Register to be written |
| 388 | * @param __REG__ Register to be written |
388 | * @param __VALUE__ Value to be written in the register |
| 389 | * @param __VALUE__ Value to be written in the register |
389 | * @retval None |
| 390 | * @retval None |
390 | */ |
| 391 | */ |
391 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| 392 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
392 | |
| 393 | 393 | /** |
|
| 394 | /** |
394 | * @brief Read a value in DAC register |
| 395 | * @brief Read a value in DAC register |
395 | * @param __INSTANCE__ DAC Instance |
| 396 | * @param __INSTANCE__ DAC Instance |
396 | * @param __REG__ Register to be read |
| 397 | * @param __REG__ Register to be read |
397 | * @retval Register value |
| 398 | * @retval Register value |
398 | */ |
| 399 | */ |
399 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| 400 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
400 | |
| 401 | 401 | /** |
|
| 402 | /** |
402 | * @} |
| 403 | * @} |
403 | */ |
| 404 | */ |
404 | |
| 405 | 405 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
|
| 406 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
406 | * @{ |
| 407 | * @{ |
407 | */ |
| 408 | */ |
408 | |
| 409 | 409 | /** |
|
| 410 | /** |
410 | * @brief Helper macro to get DAC channel number in decimal format |
| 411 | * @brief Helper macro to get DAC channel number in decimal format |
411 | * from literals LL_DAC_CHANNEL_x. |
| 412 | * from literals LL_DAC_CHANNEL_x. |
412 | * Example: |
| 413 | * Example: |
413 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
| 414 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
414 | * will return decimal number "1". |
| 415 | * will return decimal number "1". |
415 | * @note The input can be a value from functions where a channel |
| 416 | * @note The input can be a value from functions where a channel |
416 | * number is returned. |
| 417 | * number is returned. |
417 | * @param __CHANNEL__ This parameter can be one of the following values: |
| 418 | * @param __CHANNEL__ This parameter can be one of the following values: |
418 | * @arg @ref LL_DAC_CHANNEL_1 |
| 419 | * @arg @ref LL_DAC_CHANNEL_1 |
419 | * @arg @ref LL_DAC_CHANNEL_2 |
| 420 | * @arg @ref LL_DAC_CHANNEL_2 |
420 | * @retval 1...2 |
| 421 | * @retval 1...2 |
421 | */ |
| 422 | */ |
422 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
| 423 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
423 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
| 424 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
424 | |
| 425 | 425 | /** |
|
| 426 | /** |
426 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
| 427 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
427 | * from number in decimal format. |
| 428 | * from number in decimal format. |
428 | * Example: |
| 429 | * Example: |
429 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
| 430 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
430 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
| 431 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
431 | * @note If the input parameter does not correspond to a DAC channel, |
| 432 | * @note If the input parameter does not correspond to a DAC channel, |
432 | * this macro returns value '0'. |
| 433 | * this macro returns value '0'. |
433 | * @param __DECIMAL_NB__ 1...2 |
| 434 | * @param __DECIMAL_NB__ 1...2 |
434 | * @retval Returned value can be one of the following values: |
| 435 | * @retval Returned value can be one of the following values: |
435 | * @arg @ref LL_DAC_CHANNEL_1 |
| 436 | * @arg @ref LL_DAC_CHANNEL_1 |
436 | * @arg @ref LL_DAC_CHANNEL_2 |
| 437 | * @arg @ref LL_DAC_CHANNEL_2 |
437 | */ |
| 438 | */ |
438 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ |
| 439 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ |
439 | (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) |
| 440 | (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) |
440 | |
| 441 | 441 | /** |
|
| 442 | /** |
442 | * @brief Helper macro to define the DAC conversion data full-scale digital |
| 443 | * @brief Helper macro to define the DAC conversion data full-scale digital |
443 | * value corresponding to the selected DAC resolution. |
| 444 | * value corresponding to the selected DAC resolution. |
444 | * @note DAC conversion data full-scale corresponds to voltage range |
| 445 | * @note DAC conversion data full-scale corresponds to voltage range |
445 | * determined by analog voltage references Vref+ and Vref- |
| 446 | * determined by analog voltage references Vref+ and Vref- |
446 | * (refer to reference manual). |
| 447 | * (refer to reference manual). |
447 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
| 448 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
448 | * @arg @ref LL_DAC_RESOLUTION_12B |
| 449 | * @arg @ref LL_DAC_RESOLUTION_12B |
449 | * @arg @ref LL_DAC_RESOLUTION_8B |
| 450 | * @arg @ref LL_DAC_RESOLUTION_8B |
450 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
| 451 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
451 | */ |
| 452 | */ |
452 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
| 453 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
453 | ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) |
| 454 | ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) |
454 | |
| 455 | 455 | /** |
|
| 456 | /** |
456 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
| 457 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
457 | * value) corresponding to a voltage (unit: mVolt). |
| 458 | * value) corresponding to a voltage (unit: mVolt). |
458 | * @note This helper macro is intended to provide input data in voltage |
| 459 | * @note This helper macro is intended to provide input data in voltage |
459 | * rather than digital value, |
| 460 | * rather than digital value, |
460 | * to be used with LL DAC functions such as |
| 461 | * to be used with LL DAC functions such as |
461 | * @ref LL_DAC_ConvertData12RightAligned(). |
| 462 | * @ref LL_DAC_ConvertData12RightAligned(). |
462 | * @note Analog reference voltage (Vref+) must be either known from |
| 463 | * @note Analog reference voltage (Vref+) must be either known from |
463 | * user board environment or can be calculated using ADC measurement |
| 464 | * user board environment or can be calculated using ADC measurement |
464 | * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
| 465 | * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
465 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
| 466 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
466 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
| 467 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
467 | * (unit: mVolt). |
| 468 | * (unit: mVolt). |
468 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
| 469 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
469 | * @arg @ref LL_DAC_RESOLUTION_12B |
| 470 | * @arg @ref LL_DAC_RESOLUTION_12B |
470 | * @arg @ref LL_DAC_RESOLUTION_8B |
| 471 | * @arg @ref LL_DAC_RESOLUTION_8B |
471 | * @retval DAC conversion data (unit: digital value) |
| 472 | * @retval DAC conversion data (unit: digital value) |
472 | */ |
| 473 | */ |
473 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ |
| 474 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ |
474 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
| 475 | __DAC_VOLTAGE__,\ |
475 | / (__VREFANALOG_VOLTAGE__) \ |
| 476 | __DAC_RESOLUTION__) \ |
476 | ) |
| 477 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
477 | |
| 478 | / (__VREFANALOG_VOLTAGE__) \ |
478 | /** |
| 479 | ) |
479 | * @} |
| 480 | 480 | */ |
|
| 481 | /** |
481 | |
| 482 | * @} |
482 | /** |
| 483 | */ |
483 | * @} |
| 484 | 484 | */ |
|
| 485 | /** |
485 | |
| 486 | * @} |
486 | |
| 487 | */ |
487 | /* Exported functions --------------------------------------------------------*/ |
| 488 | 488 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
|
| 489 | 489 | * @{ |
|
| 490 | /* Exported functions --------------------------------------------------------*/ |
490 | */ |
| 491 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
491 | |
| 492 | * @{ |
492 | /** |
| 493 | */ |
493 | * @brief Set the conversion trigger source for the selected DAC channel. |
| 494 | /** |
494 | * @note For conversion trigger source to be effective, DAC trigger |
| 495 | * @brief Set the conversion trigger source for the selected DAC channel. |
495 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
| 496 | * @note For conversion trigger source to be effective, DAC trigger |
496 | * @note To set conversion trigger source, DAC channel must be disabled. |
| 497 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
497 | * Otherwise, the setting is discarded. |
| 498 | * @note To set conversion trigger source, DAC channel must be disabled. |
498 | * @note Availability of parameters of trigger sources from timer |
| 499 | * Otherwise, the setting is discarded. |
499 | * depends on timers availability on the selected device. |
| 500 | * @note Availability of parameters of trigger sources from timer |
500 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
| 501 | * depends on timers availability on the selected device. |
501 | * CR TSEL2 LL_DAC_SetTriggerSource |
| 502 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
502 | * @param DACx DAC instance |
| 503 | * CR TSEL2 LL_DAC_SetTriggerSource |
503 | * @param DAC_Channel This parameter can be one of the following values: |
| 504 | * @param DACx DAC instance |
504 | * @arg @ref LL_DAC_CHANNEL_1 |
| 505 | * @param DAC_Channel This parameter can be one of the following values: |
505 | * @arg @ref LL_DAC_CHANNEL_2 |
| 506 | * @arg @ref LL_DAC_CHANNEL_1 |
506 | * @param TriggerSource This parameter can be one of the following values: |
| 507 | * @arg @ref LL_DAC_CHANNEL_2 |
507 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
| 508 | * @param TriggerSource This parameter can be one of the following values: |
508 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
| 509 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
509 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
| 510 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
510 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
| 511 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
511 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
| 512 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
512 | * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO |
| 513 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
513 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
| 514 | * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO |
514 | * @retval None |
| 515 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
515 | */ |
| 516 | * @retval None |
516 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
| 517 | */ |
517 | { |
| 518 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
518 | MODIFY_REG(DACx->CR, |
| 519 | { |
519 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
| 520 | MODIFY_REG(DACx->CR, |
520 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 521 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
521 | } |
| 522 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
522 | |
| 523 | } |
523 | /** |
| 524 | 524 | * @brief Get the conversion trigger source for the selected DAC channel. |
|
| 525 | /** |
525 | * @note For conversion trigger source to be effective, DAC trigger |
| 526 | * @brief Get the conversion trigger source for the selected DAC channel. |
526 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
| 527 | * @note For conversion trigger source to be effective, DAC trigger |
527 | * @note Availability of parameters of trigger sources from timer |
| 528 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
528 | * depends on timers availability on the selected device. |
| 529 | * @note Availability of parameters of trigger sources from timer |
529 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
| 530 | * depends on timers availability on the selected device. |
530 | * CR TSEL2 LL_DAC_GetTriggerSource |
| 531 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
531 | * @param DACx DAC instance |
| 532 | * CR TSEL2 LL_DAC_GetTriggerSource |
532 | * @param DAC_Channel This parameter can be one of the following values: |
| 533 | * @param DACx DAC instance |
533 | * @arg @ref LL_DAC_CHANNEL_1 |
| 534 | * @param DAC_Channel This parameter can be one of the following values: |
534 | * @arg @ref LL_DAC_CHANNEL_2 |
| 535 | * @arg @ref LL_DAC_CHANNEL_1 |
535 | * @retval Returned value can be one of the following values: |
| 536 | * @arg @ref LL_DAC_CHANNEL_2 |
536 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
| 537 | * @retval Returned value can be one of the following values: |
537 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
| 538 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
538 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
| 539 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
539 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
| 540 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
540 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
| 541 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
541 | * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO |
| 542 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
542 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
| 543 | * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO |
543 | */ |
| 544 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
544 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 545 | */ |
545 | { |
| 546 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
546 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 547 | { |
547 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
| 548 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
548 | ); |
| 549 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
549 | } |
| 550 | ); |
550 | |
| 551 | } |
551 | /** |
| 552 | 552 | * @brief Set the waveform automatic generation mode |
|
| 553 | /** |
553 | * for the selected DAC channel. |
| 554 | * @brief Set the waveform automatic generation mode |
554 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
| 555 | * for the selected DAC channel. |
555 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
| 556 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
556 | * @param DACx DAC instance |
| 557 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
557 | * @param DAC_Channel This parameter can be one of the following values: |
| 558 | * @param DACx DAC instance |
558 | * @arg @ref LL_DAC_CHANNEL_1 |
| 559 | * @param DAC_Channel This parameter can be one of the following values: |
559 | * @arg @ref LL_DAC_CHANNEL_2 |
| 560 | * @arg @ref LL_DAC_CHANNEL_1 |
560 | * @param WaveAutoGeneration This parameter can be one of the following values: |
| 561 | * @arg @ref LL_DAC_CHANNEL_2 |
561 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
| 562 | * @param WaveAutoGeneration This parameter can be one of the following values: |
562 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
| 563 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
563 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
| 564 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
564 | * @retval None |
| 565 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
565 | */ |
| 566 | * @retval None |
566 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
| 567 | */ |
567 | { |
| 568 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
568 | MODIFY_REG(DACx->CR, |
| 569 | { |
569 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
| 570 | MODIFY_REG(DACx->CR, |
570 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 571 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
571 | } |
| 572 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
572 | |
| 573 | } |
573 | /** |
| 574 | 574 | * @brief Get the waveform automatic generation mode |
|
| 575 | /** |
575 | * for the selected DAC channel. |
| 576 | * @brief Get the waveform automatic generation mode |
576 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
| 577 | * for the selected DAC channel. |
577 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
| 578 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
578 | * @param DACx DAC instance |
| 579 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
579 | * @param DAC_Channel This parameter can be one of the following values: |
| 580 | * @param DACx DAC instance |
580 | * @arg @ref LL_DAC_CHANNEL_1 |
| 581 | * @param DAC_Channel This parameter can be one of the following values: |
581 | * @arg @ref LL_DAC_CHANNEL_2 |
| 582 | * @arg @ref LL_DAC_CHANNEL_1 |
582 | * @retval Returned value can be one of the following values: |
| 583 | * @arg @ref LL_DAC_CHANNEL_2 |
583 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
| 584 | * @retval Returned value can be one of the following values: |
584 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
| 585 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
585 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
| 586 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
586 | */ |
| 587 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
587 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 588 | */ |
588 | { |
| 589 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
589 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 590 | { |
590 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
| 591 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
591 | ); |
| 592 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
592 | } |
| 593 | ); |
593 | |
| 594 | } |
594 | /** |
| 595 | 595 | * @brief Set the noise waveform generation for the selected DAC channel: |
|
| 596 | /** |
596 | * Noise mode and parameters LFSR (linear feedback shift register). |
| 597 | * @brief Set the noise waveform generation for the selected DAC channel: |
597 | * @note For wave generation to be effective, DAC channel |
| 598 | * Noise mode and parameters LFSR (linear feedback shift register). |
598 | * wave generation mode must be enabled using |
| 599 | * @note For wave generation to be effective, DAC channel |
599 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
| 600 | * wave generation mode must be enabled using |
600 | * @note This setting can be set when the selected DAC channel is disabled |
| 601 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
601 | * (otherwise, the setting operation is ignored). |
| 602 | * @note This setting can be set when the selected DAC channel is disabled |
602 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
| 603 | * (otherwise, the setting operation is ignored). |
603 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
| 604 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
604 | * @param DACx DAC instance |
| 605 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
605 | * @param DAC_Channel This parameter can be one of the following values: |
| 606 | * @param DACx DAC instance |
606 | * @arg @ref LL_DAC_CHANNEL_1 |
| 607 | * @param DAC_Channel This parameter can be one of the following values: |
607 | * @arg @ref LL_DAC_CHANNEL_2 |
| 608 | * @arg @ref LL_DAC_CHANNEL_1 |
608 | * @param NoiseLFSRMask This parameter can be one of the following values: |
| 609 | * @arg @ref LL_DAC_CHANNEL_2 |
609 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
| 610 | * @param NoiseLFSRMask This parameter can be one of the following values: |
610 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
| 611 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
611 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
| 612 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
612 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
| 613 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
613 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
| 614 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
614 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
| 615 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
615 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
| 616 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
616 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
| 617 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
617 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
| 618 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
618 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
| 619 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
619 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
| 620 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
620 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
| 621 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
621 | * @retval None |
| 622 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
622 | */ |
| 623 | * @retval None |
623 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
| 624 | */ |
624 | { |
| 625 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
625 | MODIFY_REG(DACx->CR, |
| 626 | { |
626 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
| 627 | MODIFY_REG(DACx->CR, |
627 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 628 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
628 | } |
| 629 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
629 | |
| 630 | } |
630 | /** |
| 631 | 631 | * @brief Get the noise waveform generation for the selected DAC channel: |
|
| 632 | /** |
632 | * Noise mode and parameters LFSR (linear feedback shift register). |
| 633 | * @brief Get the noise waveform generation for the selected DAC channel: |
633 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
| 634 | * Noise mode and parameters LFSR (linear feedback shift register). |
634 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
| 635 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
635 | * @param DACx DAC instance |
| 636 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
636 | * @param DAC_Channel This parameter can be one of the following values: |
| 637 | * @param DACx DAC instance |
637 | * @arg @ref LL_DAC_CHANNEL_1 |
| 638 | * @param DAC_Channel This parameter can be one of the following values: |
638 | * @arg @ref LL_DAC_CHANNEL_2 |
| 639 | * @arg @ref LL_DAC_CHANNEL_1 |
639 | * @retval Returned value can be one of the following values: |
| 640 | * @arg @ref LL_DAC_CHANNEL_2 |
640 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
| 641 | * @retval Returned value can be one of the following values: |
641 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
| 642 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
642 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
| 643 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
643 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
| 644 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
644 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
| 645 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
645 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
| 646 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
646 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
| 647 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
647 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
| 648 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
648 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
| 649 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
649 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
| 650 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
650 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
| 651 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
651 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
| 652 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
652 | */ |
| 653 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
653 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 654 | */ |
654 | { |
| 655 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
655 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 656 | { |
656 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
| 657 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
657 | ); |
| 658 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
658 | } |
| 659 | ); |
659 | |
| 660 | } |
660 | /** |
| 661 | 661 | * @brief Set the triangle waveform generation for the selected DAC channel: |
|
| 662 | /** |
662 | * triangle mode and amplitude. |
| 663 | * @brief Set the triangle waveform generation for the selected DAC channel: |
663 | * @note For wave generation to be effective, DAC channel |
| 664 | * triangle mode and amplitude. |
664 | * wave generation mode must be enabled using |
| 665 | * @note For wave generation to be effective, DAC channel |
665 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
| 666 | * wave generation mode must be enabled using |
666 | * @note This setting can be set when the selected DAC channel is disabled |
| 667 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
667 | * (otherwise, the setting operation is ignored). |
| 668 | * @note This setting can be set when the selected DAC channel is disabled |
668 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
| 669 | * (otherwise, the setting operation is ignored). |
669 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
| 670 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
670 | * @param DACx DAC instance |
| 671 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
671 | * @param DAC_Channel This parameter can be one of the following values: |
| 672 | * @param DACx DAC instance |
672 | * @arg @ref LL_DAC_CHANNEL_1 |
| 673 | * @param DAC_Channel This parameter can be one of the following values: |
673 | * @arg @ref LL_DAC_CHANNEL_2 |
| 674 | * @arg @ref LL_DAC_CHANNEL_1 |
674 | * @param TriangleAmplitude This parameter can be one of the following values: |
| 675 | * @arg @ref LL_DAC_CHANNEL_2 |
675 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
| 676 | * @param TriangleAmplitude This parameter can be one of the following values: |
676 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
| 677 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
677 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
| 678 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
678 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
| 679 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
679 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
| 680 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
680 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
| 681 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
681 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
| 682 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
682 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
| 683 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
683 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
| 684 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
684 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
| 685 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
685 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
| 686 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
686 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
| 687 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
687 | * @retval None |
| 688 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
688 | */ |
| 689 | * @retval None |
689 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, |
| 690 | */ |
690 | uint32_t TriangleAmplitude) |
| 691 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, |
691 | { |
| 692 | uint32_t TriangleAmplitude) |
692 | MODIFY_REG(DACx->CR, |
| 693 | { |
693 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
| 694 | MODIFY_REG(DACx->CR, |
694 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 695 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
695 | } |
| 696 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
696 | |
| 697 | } |
697 | /** |
| 698 | 698 | * @brief Get the triangle waveform generation for the selected DAC channel: |
|
| 699 | /** |
699 | * triangle mode and amplitude. |
| 700 | * @brief Get the triangle waveform generation for the selected DAC channel: |
700 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
| 701 | * triangle mode and amplitude. |
701 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
| 702 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
702 | * @param DACx DAC instance |
| 703 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
703 | * @param DAC_Channel This parameter can be one of the following values: |
| 704 | * @param DACx DAC instance |
704 | * @arg @ref LL_DAC_CHANNEL_1 |
| 705 | * @param DAC_Channel This parameter can be one of the following values: |
705 | * @arg @ref LL_DAC_CHANNEL_2 |
| 706 | * @arg @ref LL_DAC_CHANNEL_1 |
706 | * @retval Returned value can be one of the following values: |
| 707 | * @arg @ref LL_DAC_CHANNEL_2 |
707 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
| 708 | * @retval Returned value can be one of the following values: |
708 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
| 709 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
709 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
| 710 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
710 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
| 711 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
711 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
| 712 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
712 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
| 713 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
713 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
| 714 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
714 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
| 715 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
715 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
| 716 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
716 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
| 717 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
717 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
| 718 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
718 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
| 719 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
719 | */ |
| 720 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
720 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 721 | */ |
721 | { |
| 722 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
722 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 723 | { |
723 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
| 724 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
724 | ); |
| 725 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
725 | } |
| 726 | ); |
726 | |
| 727 | } |
727 | /** |
| 728 | 728 | * @brief Set the output buffer for the selected DAC channel. |
|
| 729 | /** |
729 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
| 730 | * @brief Set the output buffer for the selected DAC channel. |
730 | * CR BOFF2 LL_DAC_SetOutputBuffer |
| 731 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
731 | * @param DACx DAC instance |
| 732 | * CR BOFF2 LL_DAC_SetOutputBuffer |
732 | * @param DAC_Channel This parameter can be one of the following values: |
| 733 | * @param DACx DAC instance |
733 | * @arg @ref LL_DAC_CHANNEL_1 |
| 734 | * @param DAC_Channel This parameter can be one of the following values: |
734 | * @arg @ref LL_DAC_CHANNEL_2 |
| 735 | * @arg @ref LL_DAC_CHANNEL_1 |
735 | * @param OutputBuffer This parameter can be one of the following values: |
| 736 | * @arg @ref LL_DAC_CHANNEL_2 |
736 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
| 737 | * @param OutputBuffer This parameter can be one of the following values: |
737 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
| 738 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
738 | * @retval None |
| 739 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
739 | */ |
| 740 | * @retval None |
740 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
| 741 | */ |
741 | { |
| 742 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
742 | MODIFY_REG(DACx->CR, |
| 743 | { |
743 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
| 744 | MODIFY_REG(DACx->CR, |
744 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 745 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
745 | } |
| 746 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
746 | |
| 747 | } |
747 | /** |
| 748 | 748 | * @brief Get the output buffer state for the selected DAC channel. |
|
| 749 | /** |
749 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
| 750 | * @brief Get the output buffer state for the selected DAC channel. |
750 | * CR BOFF2 LL_DAC_GetOutputBuffer |
| 751 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
751 | * @param DACx DAC instance |
| 752 | * CR BOFF2 LL_DAC_GetOutputBuffer |
752 | * @param DAC_Channel This parameter can be one of the following values: |
| 753 | * @param DACx DAC instance |
753 | * @arg @ref LL_DAC_CHANNEL_1 |
| 754 | * @param DAC_Channel This parameter can be one of the following values: |
754 | * @arg @ref LL_DAC_CHANNEL_2 |
| 755 | * @arg @ref LL_DAC_CHANNEL_1 |
755 | * @retval Returned value can be one of the following values: |
| 756 | * @arg @ref LL_DAC_CHANNEL_2 |
756 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
| 757 | * @retval Returned value can be one of the following values: |
757 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
| 758 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
758 | */ |
| 759 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
759 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 760 | */ |
760 | { |
| 761 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
761 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 762 | { |
762 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
| 763 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
763 | ); |
| 764 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
764 | } |
| 765 | ); |
765 | |
| 766 | } |
766 | /** |
| 767 | 767 | * @} |
|
| 768 | /** |
768 | */ |
| 769 | * @} |
769 | |
| 770 | */ |
770 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
| 771 | 771 | * @{ |
|
| 772 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
772 | */ |
| 773 | * @{ |
773 | |
| 774 | */ |
774 | /** |
| 775 | 775 | * @brief Enable DAC DMA transfer request of the selected channel. |
|
| 776 | /** |
776 | * @note To configure DMA source address (peripheral address), |
| 777 | * @brief Enable DAC DMA transfer request of the selected channel. |
777 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
| 778 | * @note To configure DMA source address (peripheral address), |
778 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
| 779 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
779 | * CR DMAEN2 LL_DAC_EnableDMAReq |
| 780 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
780 | * @param DACx DAC instance |
| 781 | * CR DMAEN2 LL_DAC_EnableDMAReq |
781 | * @param DAC_Channel This parameter can be one of the following values: |
| 782 | * @param DACx DAC instance |
782 | * @arg @ref LL_DAC_CHANNEL_1 |
| 783 | * @param DAC_Channel This parameter can be one of the following values: |
783 | * @arg @ref LL_DAC_CHANNEL_2 |
| 784 | * @arg @ref LL_DAC_CHANNEL_1 |
784 | * @retval None |
| 785 | * @arg @ref LL_DAC_CHANNEL_2 |
785 | */ |
| 786 | * @retval None |
786 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 787 | */ |
787 | { |
| 788 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
788 | SET_BIT(DACx->CR, |
| 789 | { |
789 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 790 | SET_BIT(DACx->CR, |
790 | } |
| 791 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
791 | |
| 792 | } |
792 | /** |
| 793 | 793 | * @brief Disable DAC DMA transfer request of the selected channel. |
|
| 794 | /** |
794 | * @note To configure DMA source address (peripheral address), |
| 795 | * @brief Disable DAC DMA transfer request of the selected channel. |
795 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
| 796 | * @note To configure DMA source address (peripheral address), |
796 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
| 797 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
797 | * CR DMAEN2 LL_DAC_DisableDMAReq |
| 798 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
798 | * @param DACx DAC instance |
| 799 | * CR DMAEN2 LL_DAC_DisableDMAReq |
799 | * @param DAC_Channel This parameter can be one of the following values: |
| 800 | * @param DACx DAC instance |
800 | * @arg @ref LL_DAC_CHANNEL_1 |
| 801 | * @param DAC_Channel This parameter can be one of the following values: |
801 | * @arg @ref LL_DAC_CHANNEL_2 |
| 802 | * @arg @ref LL_DAC_CHANNEL_1 |
802 | * @retval None |
| 803 | * @arg @ref LL_DAC_CHANNEL_2 |
803 | */ |
| 804 | * @retval None |
804 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 805 | */ |
805 | { |
| 806 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
806 | CLEAR_BIT(DACx->CR, |
| 807 | { |
807 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 808 | CLEAR_BIT(DACx->CR, |
808 | } |
| 809 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
809 | |
| 810 | } |
810 | /** |
| 811 | 811 | * @brief Get DAC DMA transfer request state of the selected channel. |
|
| 812 | /** |
812 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
| 813 | * @brief Get DAC DMA transfer request state of the selected channel. |
813 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
| 814 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
814 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
| 815 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
815 | * @param DACx DAC instance |
| 816 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
816 | * @param DAC_Channel This parameter can be one of the following values: |
| 817 | * @param DACx DAC instance |
817 | * @arg @ref LL_DAC_CHANNEL_1 |
| 818 | * @param DAC_Channel This parameter can be one of the following values: |
818 | * @arg @ref LL_DAC_CHANNEL_2 |
| 819 | * @arg @ref LL_DAC_CHANNEL_1 |
819 | * @retval State of bit (1 or 0). |
| 820 | * @arg @ref LL_DAC_CHANNEL_2 |
820 | */ |
| 821 | * @retval State of bit (1 or 0). |
821 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 822 | */ |
822 | { |
| 823 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
823 | return ((READ_BIT(DACx->CR, |
| 824 | { |
824 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 825 | return ((READ_BIT(DACx->CR, |
825 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
| 826 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
826 | } |
| 827 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
827 | |
| 828 | } |
828 | /** |
| 829 | 829 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
|
| 830 | /** |
830 | * DAC register address from DAC instance and a list of DAC registers |
| 831 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
831 | * intended to be used (most commonly) with DMA transfer. |
| 832 | * DAC register address from DAC instance and a list of DAC registers |
832 | * @note These DAC registers are data holding registers: |
| 833 | * intended to be used (most commonly) with DMA transfer. |
833 | * when DAC conversion is requested, DAC generates a DMA transfer |
| 834 | * @note These DAC registers are data holding registers: |
834 | * request to have data available in DAC data holding registers. |
| 835 | * when DAC conversion is requested, DAC generates a DMA transfer |
835 | * @note This macro is intended to be used with LL DMA driver, refer to |
| 836 | * request to have data available in DAC data holding registers. |
836 | * function "LL_DMA_ConfigAddresses()". |
| 837 | * @note This macro is intended to be used with LL DMA driver, refer to |
837 | * Example: |
| 838 | * function "LL_DMA_ConfigAddresses()". |
838 | * LL_DMA_ConfigAddresses(DMA1, |
| 839 | * Example: |
839 | * LL_DMA_CHANNEL_1, |
| 840 | * LL_DMA_ConfigAddresses(DMA1, |
840 | * (uint32_t)&< array or variable >, |
| 841 | * LL_DMA_CHANNEL_1, |
841 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, |
| 842 | * (uint32_t)&< array or variable >, |
842 | * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
| 843 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, |
843 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
| 844 | * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
844 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
| 845 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
845 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
| 846 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
846 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
| 847 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
847 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
| 848 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
848 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
| 849 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
849 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
| 850 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
850 | * @param DACx DAC instance |
| 851 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
851 | * @param DAC_Channel This parameter can be one of the following values: |
| 852 | * @param DACx DAC instance |
852 | * @arg @ref LL_DAC_CHANNEL_1 |
| 853 | * @param DAC_Channel This parameter can be one of the following values: |
853 | * @arg @ref LL_DAC_CHANNEL_2 |
| 854 | * @arg @ref LL_DAC_CHANNEL_1 |
854 | * @param Register This parameter can be one of the following values: |
| 855 | * @arg @ref LL_DAC_CHANNEL_2 |
855 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
| 856 | * @param Register This parameter can be one of the following values: |
856 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
| 857 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
857 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
| 858 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
858 | * @retval DAC register address |
| 859 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
859 | */ |
| 860 | * @retval DAC register address |
860 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
| 861 | */ |
861 | { |
| 862 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
862 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
| 863 | { |
863 | /* DAC channel selected. */ |
| 864 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
864 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) |
| 865 | /* DAC channel selected. */ |
865 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); |
| 866 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) |
866 | } |
| 867 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); |
867 | /** |
| 868 | } |
868 | * @} |
| 869 | /** |
869 | */ |
| 870 | * @} |
870 | |
| 871 | */ |
871 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
| 872 | 872 | * @{ |
|
| 873 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
873 | */ |
| 874 | * @{ |
874 | |
| 875 | */ |
875 | /** |
| 876 | 876 | * @brief Enable DAC selected channel. |
|
| 877 | /** |
877 | * @rmtoll CR EN1 LL_DAC_Enable\n |
| 878 | * @brief Enable DAC selected channel. |
878 | * CR EN2 LL_DAC_Enable |
| 879 | * @rmtoll CR EN1 LL_DAC_Enable\n |
879 | * @note After enable from off state, DAC channel requires a delay |
| 880 | * CR EN2 LL_DAC_Enable |
880 | * for output voltage to reach accuracy +/- 1 LSB. |
| 881 | * @note After enable from off state, DAC channel requires a delay |
881 | * Refer to device datasheet, parameter "tWAKEUP". |
| 882 | * for output voltage to reach accuracy +/- 1 LSB. |
882 | * @param DACx DAC instance |
| 883 | * Refer to device datasheet, parameter "tWAKEUP". |
883 | * @param DAC_Channel This parameter can be one of the following values: |
| 884 | * @param DACx DAC instance |
884 | * @arg @ref LL_DAC_CHANNEL_1 |
| 885 | * @param DAC_Channel This parameter can be one of the following values: |
885 | * @arg @ref LL_DAC_CHANNEL_2 |
| 886 | * @arg @ref LL_DAC_CHANNEL_1 |
886 | * @retval None |
| 887 | * @arg @ref LL_DAC_CHANNEL_2 |
887 | */ |
| 888 | * @retval None |
888 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 889 | */ |
889 | { |
| 890 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
890 | SET_BIT(DACx->CR, |
| 891 | { |
891 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 892 | SET_BIT(DACx->CR, |
892 | } |
| 893 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
893 | |
| 894 | } |
894 | /** |
| 895 | 895 | * @brief Disable DAC selected channel. |
|
| 896 | /** |
896 | * @rmtoll CR EN1 LL_DAC_Disable\n |
| 897 | * @brief Disable DAC selected channel. |
897 | * CR EN2 LL_DAC_Disable |
| 898 | * @rmtoll CR EN1 LL_DAC_Disable\n |
898 | * @param DACx DAC instance |
| 899 | * CR EN2 LL_DAC_Disable |
899 | * @param DAC_Channel This parameter can be one of the following values: |
| 900 | * @param DACx DAC instance |
900 | * @arg @ref LL_DAC_CHANNEL_1 |
| 901 | * @param DAC_Channel This parameter can be one of the following values: |
901 | * @arg @ref LL_DAC_CHANNEL_2 |
| 902 | * @arg @ref LL_DAC_CHANNEL_1 |
902 | * @retval None |
| 903 | * @arg @ref LL_DAC_CHANNEL_2 |
903 | */ |
| 904 | * @retval None |
904 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 905 | */ |
905 | { |
| 906 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
906 | CLEAR_BIT(DACx->CR, |
| 907 | { |
907 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 908 | CLEAR_BIT(DACx->CR, |
908 | } |
| 909 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
909 | |
| 910 | } |
910 | /** |
| 911 | 911 | * @brief Get DAC enable state of the selected channel. |
|
| 912 | /** |
912 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
| 913 | * @brief Get DAC enable state of the selected channel. |
913 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
| 914 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
914 | * CR EN2 LL_DAC_IsEnabled |
| 915 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
915 | * @param DACx DAC instance |
| 916 | * CR EN2 LL_DAC_IsEnabled |
916 | * @param DAC_Channel This parameter can be one of the following values: |
| 917 | * @param DACx DAC instance |
917 | * @arg @ref LL_DAC_CHANNEL_1 |
| 918 | * @param DAC_Channel This parameter can be one of the following values: |
918 | * @arg @ref LL_DAC_CHANNEL_2 |
| 919 | * @arg @ref LL_DAC_CHANNEL_1 |
919 | * @retval State of bit (1 or 0). |
| 920 | * @arg @ref LL_DAC_CHANNEL_2 |
920 | */ |
| 921 | * @retval State of bit (1 or 0). |
921 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 922 | */ |
922 | { |
| 923 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
923 | return ((READ_BIT(DACx->CR, |
| 924 | { |
924 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 925 | return ((READ_BIT(DACx->CR, |
925 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
| 926 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
926 | } |
| 927 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
927 | |
| 928 | } |
928 | /** |
| 929 | 929 | * @brief Enable DAC trigger of the selected channel. |
|
| 930 | /** |
930 | * @note - If DAC trigger is disabled, DAC conversion is performed |
| 931 | * @brief Enable DAC trigger of the selected channel. |
931 | * automatically once the data holding register is updated, |
| 932 | * @note - If DAC trigger is disabled, DAC conversion is performed |
932 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
| 933 | * automatically once the data holding register is updated, |
933 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
| 934 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
934 | * - If DAC trigger is enabled, DAC conversion is performed |
| 935 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
935 | * only when a hardware of software trigger event is occurring. |
| 936 | * - If DAC trigger is enabled, DAC conversion is performed |
936 | * Select trigger source using |
| 937 | * only when a hardware of software trigger event is occurring. |
937 | * function @ref LL_DAC_SetTriggerSource(). |
| 938 | * Select trigger source using |
938 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
| 939 | * function @ref LL_DAC_SetTriggerSource(). |
939 | * CR TEN2 LL_DAC_EnableTrigger |
| 940 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
940 | * @param DACx DAC instance |
| 941 | * CR TEN2 LL_DAC_EnableTrigger |
941 | * @param DAC_Channel This parameter can be one of the following values: |
| 942 | * @param DACx DAC instance |
942 | * @arg @ref LL_DAC_CHANNEL_1 |
| 943 | * @param DAC_Channel This parameter can be one of the following values: |
943 | * @arg @ref LL_DAC_CHANNEL_2 |
| 944 | * @arg @ref LL_DAC_CHANNEL_1 |
944 | * @retval None |
| 945 | * @arg @ref LL_DAC_CHANNEL_2 |
945 | */ |
| 946 | * @retval None |
946 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 947 | */ |
947 | { |
| 948 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
948 | SET_BIT(DACx->CR, |
| 949 | { |
949 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 950 | SET_BIT(DACx->CR, |
950 | } |
| 951 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
951 | |
| 952 | } |
952 | /** |
| 953 | 953 | * @brief Disable DAC trigger of the selected channel. |
|
| 954 | /** |
954 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
| 955 | * @brief Disable DAC trigger of the selected channel. |
955 | * CR TEN2 LL_DAC_DisableTrigger |
| 956 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
956 | * @param DACx DAC instance |
| 957 | * CR TEN2 LL_DAC_DisableTrigger |
957 | * @param DAC_Channel This parameter can be one of the following values: |
| 958 | * @param DACx DAC instance |
958 | * @arg @ref LL_DAC_CHANNEL_1 |
| 959 | * @param DAC_Channel This parameter can be one of the following values: |
959 | * @arg @ref LL_DAC_CHANNEL_2 |
| 960 | * @arg @ref LL_DAC_CHANNEL_1 |
960 | * @retval None |
| 961 | * @arg @ref LL_DAC_CHANNEL_2 |
961 | */ |
| 962 | * @retval None |
962 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 963 | */ |
963 | { |
| 964 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
964 | CLEAR_BIT(DACx->CR, |
| 965 | { |
965 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
| 966 | CLEAR_BIT(DACx->CR, |
966 | } |
| 967 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
967 | |
| 968 | } |
968 | /** |
| 969 | 969 | * @brief Get DAC trigger state of the selected channel. |
|
| 970 | /** |
970 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
| 971 | * @brief Get DAC trigger state of the selected channel. |
971 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
| 972 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
972 | * CR TEN2 LL_DAC_IsTriggerEnabled |
| 973 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
973 | * @param DACx DAC instance |
| 974 | * CR TEN2 LL_DAC_IsTriggerEnabled |
974 | * @param DAC_Channel This parameter can be one of the following values: |
| 975 | * @param DACx DAC instance |
975 | * @arg @ref LL_DAC_CHANNEL_1 |
| 976 | * @param DAC_Channel This parameter can be one of the following values: |
976 | * @arg @ref LL_DAC_CHANNEL_2 |
| 977 | * @arg @ref LL_DAC_CHANNEL_1 |
977 | * @retval State of bit (1 or 0). |
| 978 | * @arg @ref LL_DAC_CHANNEL_2 |
978 | */ |
| 979 | * @retval State of bit (1 or 0). |
979 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 980 | */ |
980 | { |
| 981 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
981 | return ((READ_BIT(DACx->CR, |
| 982 | { |
982 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
| 983 | return ((READ_BIT(DACx->CR, |
983 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
| 984 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
984 | } |
| 985 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
985 | |
| 986 | } |
986 | /** |
| 987 | 987 | * @brief Trig DAC conversion by software for the selected DAC channel. |
|
| 988 | /** |
988 | * @note Preliminarily, DAC trigger must be set to software trigger |
| 989 | * @brief Trig DAC conversion by software for the selected DAC channel. |
989 | * using function |
| 990 | * @note Preliminarily, DAC trigger must be set to software trigger |
990 | * @ref LL_DAC_Init() |
| 991 | * using function |
991 | * @ref LL_DAC_SetTriggerSource() |
| 992 | * @ref LL_DAC_Init() |
992 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
| 993 | * @ref LL_DAC_SetTriggerSource() |
993 | * and DAC trigger must be enabled using |
| 994 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
994 | * function @ref LL_DAC_EnableTrigger(). |
| 995 | * and DAC trigger must be enabled using |
995 | * @note For devices featuring DAC with 2 channels: this function |
| 996 | * function @ref LL_DAC_EnableTrigger(). |
996 | * can perform a SW start of both DAC channels simultaneously. |
| 997 | * @note For devices featuring DAC with 2 channels: this function |
997 | * Two channels can be selected as parameter. |
| 998 | * can perform a SW start of both DAC channels simultaneously. |
998 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
| 999 | * Two channels can be selected as parameter. |
999 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
| 1000 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
1000 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
| 1001 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
1001 | * @param DACx DAC instance |
| 1002 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
1002 | * @param DAC_Channel This parameter can a combination of the following values: |
| 1003 | * @param DACx DAC instance |
1003 | * @arg @ref LL_DAC_CHANNEL_1 |
| 1004 | * @param DAC_Channel This parameter can a combination of the following values: |
1004 | * @arg @ref LL_DAC_CHANNEL_2 |
| 1005 | * @arg @ref LL_DAC_CHANNEL_1 |
1005 | * @retval None |
| 1006 | * @arg @ref LL_DAC_CHANNEL_2 |
1006 | */ |
| 1007 | * @retval None |
1007 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 1008 | */ |
1008 | { |
| 1009 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
1009 | SET_BIT(DACx->SWTRIGR, |
| 1010 | { |
1010 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
| 1011 | SET_BIT(DACx->SWTRIGR, |
1011 | } |
| 1012 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
1012 | |
| 1013 | } |
1013 | /** |
| 1014 | 1014 | * @brief Set the data to be loaded in the data holding register |
|
| 1015 | /** |
1015 | * in format 12 bits left alignment (LSB aligned on bit 0), |
| 1016 | * @brief Set the data to be loaded in the data holding register |
1016 | * for the selected DAC channel. |
| 1017 | * in format 12 bits left alignment (LSB aligned on bit 0), |
1017 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
| 1018 | * for the selected DAC channel. |
1018 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
| 1019 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
1019 | * @param DACx DAC instance |
| 1020 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
1020 | * @param DAC_Channel This parameter can be one of the following values: |
| 1021 | * @param DACx DAC instance |
1021 | * @arg @ref LL_DAC_CHANNEL_1 |
| 1022 | * @param DAC_Channel This parameter can be one of the following values: |
1022 | * @arg @ref LL_DAC_CHANNEL_2 |
| 1023 | * @arg @ref LL_DAC_CHANNEL_1 |
1023 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1024 | * @arg @ref LL_DAC_CHANNEL_2 |
1024 | * @retval None |
| 1025 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
1025 | */ |
| 1026 | * @retval None |
1026 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
| 1027 | */ |
1027 | { |
| 1028 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
1028 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) |
| 1029 | { |
1029 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
| 1030 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) |
1030 | |
| 1031 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
1031 | MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); |
| 1032 | 1032 | } |
|
| 1033 | MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); |
1033 | |
| 1034 | } |
1034 | /** |
| 1035 | 1035 | * @brief Set the data to be loaded in the data holding register |
|
| 1036 | /** |
1036 | * in format 12 bits left alignment (MSB aligned on bit 15), |
| 1037 | * @brief Set the data to be loaded in the data holding register |
1037 | * for the selected DAC channel. |
| 1038 | * in format 12 bits left alignment (MSB aligned on bit 15), |
1038 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
| 1039 | * for the selected DAC channel. |
1039 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
| 1040 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
1040 | * @param DACx DAC instance |
| 1041 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
1041 | * @param DAC_Channel This parameter can be one of the following values: |
| 1042 | * @param DACx DAC instance |
1042 | * @arg @ref LL_DAC_CHANNEL_1 |
| 1043 | * @param DAC_Channel This parameter can be one of the following values: |
1043 | * @arg @ref LL_DAC_CHANNEL_2 |
| 1044 | * @arg @ref LL_DAC_CHANNEL_1 |
1044 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1045 | * @arg @ref LL_DAC_CHANNEL_2 |
1045 | * @retval None |
| 1046 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
1046 | */ |
| 1047 | * @retval None |
1047 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
| 1048 | */ |
1048 | { |
| 1049 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
1049 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) |
| 1050 | { |
1050 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
| 1051 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) |
1051 | |
| 1052 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
1052 | MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); |
| 1053 | 1053 | } |
|
| 1054 | MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); |
1054 | |
| 1055 | } |
1055 | /** |
| 1056 | 1056 | * @brief Set the data to be loaded in the data holding register |
|
| 1057 | /** |
1057 | * in format 8 bits left alignment (LSB aligned on bit 0), |
| 1058 | * @brief Set the data to be loaded in the data holding register |
1058 | * for the selected DAC channel. |
| 1059 | * in format 8 bits left alignment (LSB aligned on bit 0), |
1059 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
| 1060 | * for the selected DAC channel. |
1060 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
| 1061 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
1061 | * @param DACx DAC instance |
| 1062 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
1062 | * @param DAC_Channel This parameter can be one of the following values: |
| 1063 | * @param DACx DAC instance |
1063 | * @arg @ref LL_DAC_CHANNEL_1 |
| 1064 | * @param DAC_Channel This parameter can be one of the following values: |
1064 | * @arg @ref LL_DAC_CHANNEL_2 |
| 1065 | * @arg @ref LL_DAC_CHANNEL_1 |
1065 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
| 1066 | * @arg @ref LL_DAC_CHANNEL_2 |
1066 | * @retval None |
| 1067 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
1067 | */ |
| 1068 | * @retval None |
1068 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
| 1069 | */ |
1069 | { |
| 1070 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
1070 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) |
| 1071 | { |
1071 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
| 1072 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) |
1072 | |
| 1073 | & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
1073 | MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); |
| 1074 | 1074 | } |
|
| 1075 | MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); |
1075 | |
| 1076 | } |
1076 | |
| 1077 | 1077 | /** |
|
| 1078 | 1078 | * @brief Set the data to be loaded in the data holding register |
|
| 1079 | /** |
1079 | * in format 12 bits left alignment (LSB aligned on bit 0), |
| 1080 | * @brief Set the data to be loaded in the data holding register |
1080 | * for both DAC channels. |
| 1081 | * in format 12 bits left alignment (LSB aligned on bit 0), |
1081 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
| 1082 | * for both DAC channels. |
1082 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
| 1083 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
1083 | * @param DACx DAC instance |
| 1084 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
1084 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1085 | * @param DACx DAC instance |
1085 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1086 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
1086 | * @retval None |
| 1087 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
1087 | */ |
| 1088 | * @retval None |
1088 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
| 1089 | */ |
1089 | uint32_t DataChannel2) |
| 1090 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
1090 | { |
| 1091 | uint32_t DataChannel2) |
1091 | MODIFY_REG(DACx->DHR12RD, |
| 1092 | { |
1092 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
| 1093 | MODIFY_REG(DACx->DHR12RD, |
1093 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
| 1094 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
1094 | } |
| 1095 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
1095 | |
| 1096 | } |
1096 | /** |
| 1097 | 1097 | * @brief Set the data to be loaded in the data holding register |
|
| 1098 | /** |
1098 | * in format 12 bits left alignment (MSB aligned on bit 15), |
| 1099 | * @brief Set the data to be loaded in the data holding register |
1099 | * for both DAC channels. |
| 1100 | * in format 12 bits left alignment (MSB aligned on bit 15), |
1100 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
| 1101 | * for both DAC channels. |
1101 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
| 1102 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
1102 | * @param DACx DAC instance |
| 1103 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
1103 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1104 | * @param DACx DAC instance |
1104 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1105 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
1105 | * @retval None |
| 1106 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
1106 | */ |
| 1107 | * @retval None |
1107 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
| 1108 | */ |
1108 | uint32_t DataChannel2) |
| 1109 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
1109 | { |
| 1110 | uint32_t DataChannel2) |
1110 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
| 1111 | { |
1111 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
| 1112 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
1112 | /* the 4 LSB must be taken into account for the shift value. */ |
| 1113 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
1113 | MODIFY_REG(DACx->DHR12LD, |
| 1114 | /* the 4 LSB must be taken into account for the shift value. */ |
1114 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
| 1115 | MODIFY_REG(DACx->DHR12LD, |
1115 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
| 1116 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
1116 | } |
| 1117 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
1117 | |
| 1118 | } |
1118 | /** |
| 1119 | 1119 | * @brief Set the data to be loaded in the data holding register |
|
| 1120 | /** |
1120 | * in format 8 bits left alignment (LSB aligned on bit 0), |
| 1121 | * @brief Set the data to be loaded in the data holding register |
1121 | * for both DAC channels. |
| 1122 | * in format 8 bits left alignment (LSB aligned on bit 0), |
1122 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
| 1123 | * for both DAC channels. |
1123 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
| 1124 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
1124 | * @param DACx DAC instance |
| 1125 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
1125 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
| 1126 | * @param DACx DAC instance |
1126 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
| 1127 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
1127 | * @retval None |
| 1128 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
1128 | */ |
| 1129 | * @retval None |
1129 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
| 1130 | */ |
1130 | uint32_t DataChannel2) |
| 1131 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
1131 | { |
| 1132 | uint32_t DataChannel2) |
1132 | MODIFY_REG(DACx->DHR8RD, |
| 1133 | { |
1133 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
| 1134 | MODIFY_REG(DACx->DHR8RD, |
1134 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
| 1135 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
1135 | } |
| 1136 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
1136 | |
| 1137 | } |
1137 | |
| 1138 | 1138 | /** |
|
| 1139 | 1139 | * @brief Retrieve output data currently generated for the selected DAC channel. |
|
| 1140 | /** |
1140 | * @note Whatever alignment and resolution settings |
| 1141 | * @brief Retrieve output data currently generated for the selected DAC channel. |
1141 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
| 1142 | * @note Whatever alignment and resolution settings |
1142 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
| 1143 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
1143 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
| 1144 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
1144 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
| 1145 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
1145 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
| 1146 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
1146 | * @param DACx DAC instance |
| 1147 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
1147 | * @param DAC_Channel This parameter can be one of the following values: |
| 1148 | * @param DACx DAC instance |
1148 | * @arg @ref LL_DAC_CHANNEL_1 |
| 1149 | * @param DAC_Channel This parameter can be one of the following values: |
1149 | * @arg @ref LL_DAC_CHANNEL_2 |
| 1150 | * @arg @ref LL_DAC_CHANNEL_1 |
1150 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
| 1151 | * @arg @ref LL_DAC_CHANNEL_2 |
1151 | */ |
| 1152 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
1152 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) |
| 1153 | */ |
1153 | { |
| 1154 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
1154 | __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) |
| 1155 | { |
1155 | & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); |
| 1156 | __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) |
1156 | |
| 1157 | & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); |
1157 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
| 1158 | 1158 | } |
|
| 1159 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
1159 | |
| 1160 | } |
1160 | /** |
| 1161 | 1161 | * @} |
|
| 1162 | /** |
1162 | */ |
| 1163 | * @} |
1163 | |
| 1164 | */ |
1164 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
| 1165 | 1165 | * @{ |
|
| 1166 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
1166 | */ |
| 1167 | * @{ |
1167 | |
| 1168 | */ |
1168 | /** |
| 1169 | 1169 | * @brief Get DAC underrun flag for DAC channel 1 |
|
| 1170 | /** |
1170 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
| 1171 | * @brief Get DAC underrun flag for DAC channel 1 |
1171 | * @param DACx DAC instance |
| 1172 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
1172 | * @retval State of bit (1 or 0). |
| 1173 | * @param DACx DAC instance |
1173 | */ |
| 1174 | * @retval State of bit (1 or 0). |
1174 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) |
| 1175 | */ |
1175 | { |
| 1176 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) |
1176 | return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); |
| 1177 | { |
1177 | } |
| 1178 | return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); |
1178 | |
| 1179 | } |
1179 | |
| 1180 | 1180 | /** |
|
| 1181 | 1181 | * @brief Get DAC underrun flag for DAC channel 2 |
|
| 1182 | /** |
1182 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
| 1183 | * @brief Get DAC underrun flag for DAC channel 2 |
1183 | * @param DACx DAC instance |
| 1184 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
1184 | * @retval State of bit (1 or 0). |
| 1185 | * @param DACx DAC instance |
1185 | */ |
| 1186 | * @retval State of bit (1 or 0). |
1186 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) |
| 1187 | */ |
1187 | { |
| 1188 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) |
1188 | return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); |
| 1189 | { |
1189 | } |
| 1190 | return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); |
1190 | |
| 1191 | } |
1191 | |
| 1192 | 1192 | /** |
|
| 1193 | 1193 | * @brief Clear DAC underrun flag for DAC channel 1 |
|
| 1194 | /** |
1194 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
| 1195 | * @brief Clear DAC underrun flag for DAC channel 1 |
1195 | * @param DACx DAC instance |
| 1196 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
1196 | * @retval None |
| 1197 | * @param DACx DAC instance |
1197 | */ |
| 1198 | * @retval None |
1198 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
| 1199 | */ |
1199 | { |
| 1200 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
1200 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
| 1201 | { |
1201 | } |
| 1202 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
1202 | |
| 1203 | } |
1203 | |
| 1204 | 1204 | /** |
|
| 1205 | 1205 | * @brief Clear DAC underrun flag for DAC channel 2 |
|
| 1206 | /** |
1206 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
| 1207 | * @brief Clear DAC underrun flag for DAC channel 2 |
1207 | * @param DACx DAC instance |
| 1208 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
1208 | * @retval None |
| 1209 | * @param DACx DAC instance |
1209 | */ |
| 1210 | * @retval None |
1210 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
| 1211 | */ |
1211 | { |
| 1212 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
1212 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
| 1213 | { |
1213 | } |
| 1214 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
1214 | |
| 1215 | } |
1215 | |
| 1216 | 1216 | /** |
|
| 1217 | 1217 | * @} |
|
| 1218 | /** |
1218 | */ |
| 1219 | * @} |
1219 | |
| 1220 | */ |
1220 | /** @defgroup DAC_LL_EF_IT_Management IT management |
| 1221 | 1221 | * @{ |
|
| 1222 | /** @defgroup DAC_LL_EF_IT_Management IT management |
1222 | */ |
| 1223 | * @{ |
1223 | |
| 1224 | */ |
1224 | /** |
| 1225 | 1225 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
|
| 1226 | /** |
1226 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
| 1227 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
1227 | * @param DACx DAC instance |
| 1228 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
1228 | * @retval None |
| 1229 | * @param DACx DAC instance |
1229 | */ |
| 1230 | * @retval None |
1230 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
| 1231 | */ |
1231 | { |
| 1232 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
1232 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
| 1233 | { |
1233 | } |
| 1234 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
1234 | |
| 1235 | } |
1235 | |
| 1236 | 1236 | /** |
|
| 1237 | 1237 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
|
| 1238 | /** |
1238 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
| 1239 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
1239 | * @param DACx DAC instance |
| 1240 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
1240 | * @retval None |
| 1241 | * @param DACx DAC instance |
1241 | */ |
| 1242 | * @retval None |
1242 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
| 1243 | */ |
1243 | { |
| 1244 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
1244 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
| 1245 | { |
1245 | } |
| 1246 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
1246 | |
| 1247 | } |
1247 | |
| 1248 | 1248 | /** |
|
| 1249 | 1249 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
|
| 1250 | /** |
1250 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
| 1251 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
1251 | * @param DACx DAC instance |
| 1252 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
1252 | * @retval None |
| 1253 | * @param DACx DAC instance |
1253 | */ |
| 1254 | * @retval None |
1254 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
| 1255 | */ |
1255 | { |
| 1256 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
1256 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
| 1257 | { |
1257 | } |
| 1258 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
1258 | |
| 1259 | } |
1259 | |
| 1260 | 1260 | /** |
|
| 1261 | 1261 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
|
| 1262 | /** |
1262 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
| 1263 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
1263 | * @param DACx DAC instance |
| 1264 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
1264 | * @retval None |
| 1265 | * @param DACx DAC instance |
1265 | */ |
| 1266 | * @retval None |
1266 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
| 1267 | */ |
1267 | { |
| 1268 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
1268 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
| 1269 | { |
1269 | } |
| 1270 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
1270 | |
| 1271 | } |
1271 | |
| 1272 | 1272 | /** |
|
| 1273 | 1273 | * @brief Get DMA underrun interrupt for DAC channel 1 |
|
| 1274 | /** |
1274 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
| 1275 | * @brief Get DMA underrun interrupt for DAC channel 1 |
1275 | * @param DACx DAC instance |
| 1276 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
1276 | * @retval State of bit (1 or 0). |
| 1277 | * @param DACx DAC instance |
1277 | */ |
| 1278 | * @retval State of bit (1 or 0). |
1278 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) |
| 1279 | */ |
1279 | { |
| 1280 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) |
1280 | return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); |
| 1281 | { |
1281 | } |
| 1282 | return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); |
1282 | |
| 1283 | } |
1283 | |
| 1284 | 1284 | /** |
|
| 1285 | 1285 | * @brief Get DMA underrun interrupt for DAC channel 2 |
|
| 1286 | /** |
1286 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
| 1287 | * @brief Get DMA underrun interrupt for DAC channel 2 |
1287 | * @param DACx DAC instance |
| 1288 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
1288 | * @retval State of bit (1 or 0). |
| 1289 | * @param DACx DAC instance |
1289 | */ |
| 1290 | * @retval State of bit (1 or 0). |
1290 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) |
| 1291 | */ |
1291 | { |
| 1292 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) |
1292 | return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); |
| 1293 | { |
1293 | } |
| 1294 | return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); |
1294 | |
| 1295 | } |
1295 | |
| 1296 | 1296 | /** |
|
| 1297 | 1297 | * @} |
|
| 1298 | /** |
1298 | */ |
| 1299 | * @} |
1299 | |
| 1300 | */ |
1300 | #if defined(USE_FULL_LL_DRIVER) |
| 1301 | 1301 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
|
| 1302 | #if defined(USE_FULL_LL_DRIVER) |
1302 | * @{ |
| 1303 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
1303 | */ |
| 1304 | * @{ |
1304 | |
| 1305 | */ |
1305 | ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); |
| 1306 | 1306 | ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); |
|
| 1307 | ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); |
1307 | void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); |
| 1308 | ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); |
1308 | |
| 1309 | void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); |
1309 | /** |
| 1310 | 1310 | * @} |
|
| 1311 | /** |
1311 | */ |
| 1312 | * @} |
1312 | #endif /* USE_FULL_LL_DRIVER */ |
| 1313 | */ |
1313 | |
| 1314 | #endif /* USE_FULL_LL_DRIVER */ |
1314 | /** |
| 1315 | 1315 | * @} |
|
| 1316 | /** |
1316 | */ |
| 1317 | * @} |
1317 | |
| 1318 | */ |
1318 | /** |
| 1319 | 1319 | * @} |
|
| 1320 | /** |
1320 | */ |
| 1321 | * @} |
1321 | |
| 1322 | */ |
1322 | #endif /* DAC1 */ |
| 1323 | 1323 | ||
| 1324 | #endif /* DAC1 */ |
1324 | /** |
| 1325 | 1325 | * @} |
|
| 1326 | /** |
1326 | */ |
| 1327 | * @} |
1327 | |
| 1328 | */ |
1328 | #ifdef __cplusplus |
| 1329 | 1329 | } |
|
| 1330 | #ifdef __cplusplus |
1330 | #endif |
| 1331 | } |
1331 | |
| 1332 | #endif |
1332 | #endif /* STM32L1xx_LL_DAC_H */ |
| 1333 | - | ||
| 1334 | #endif /* STM32L1xx_LL_DAC_H */ |
- | |
| 1335 | - | ||
| 1336 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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