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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_hal_tim.h |
3 | * @file stm32l1xx_hal_tim.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of TIM HAL module. |
5 | * @brief Header file of TIM HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32L1xx_HAL_TIM_H |
| 21 | #ifndef STM32L1xx_HAL_TIM_H |
21 | #define STM32L1xx_HAL_TIM_H |
| 22 | #define STM32L1xx_HAL_TIM_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32l1xx_hal_def.h" |
| 29 | #include "stm32l1xx_hal_def.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_HAL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | /** @addtogroup TIM |
|
| 35 | /** @addtogroup TIM |
35 | * @{ |
| 36 | * @{ |
36 | */ |
| 37 | */ |
37 | |
| 38 | 38 | /* Exported types ------------------------------------------------------------*/ |
|
| 39 | /* Exported types ------------------------------------------------------------*/ |
39 | /** @defgroup TIM_Exported_Types TIM Exported Types |
| 40 | /** @defgroup TIM_Exported_Types TIM Exported Types |
40 | * @{ |
| 41 | * @{ |
41 | */ |
| 42 | */ |
42 | |
| 43 | 43 | /** |
|
| 44 | /** |
44 | * @brief TIM Time base Configuration Structure definition |
| 45 | * @brief TIM Time base Configuration Structure definition |
45 | */ |
| 46 | */ |
46 | typedef struct |
| 47 | typedef struct |
47 | { |
| 48 | { |
48 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
| 49 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
49 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| 50 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
50 | |
| 51 | 51 | uint32_t CounterMode; /*!< Specifies the counter mode. |
|
| 52 | uint32_t CounterMode; /*!< Specifies the counter mode. |
52 | This parameter can be a value of @ref TIM_Counter_Mode */ |
| 53 | This parameter can be a value of @ref TIM_Counter_Mode */ |
53 | |
| 54 | 54 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
|
| 55 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
55 | Auto-Reload Register at the next update event. |
| 56 | Auto-Reload Register at the next update event. |
56 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
| 57 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
57 | |
| 58 | 58 | uint32_t ClockDivision; /*!< Specifies the clock division. |
|
| 59 | uint32_t ClockDivision; /*!< Specifies the clock division. |
59 | This parameter can be a value of @ref TIM_ClockDivision */ |
| 60 | This parameter can be a value of @ref TIM_ClockDivision */ |
60 | |
| 61 | 61 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
|
| 62 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
62 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
| 63 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
63 | } TIM_Base_InitTypeDef; |
| 64 | } TIM_Base_InitTypeDef; |
64 | |
| 65 | 65 | /** |
|
| 66 | /** |
66 | * @brief TIM Output Compare Configuration Structure definition |
| 67 | * @brief TIM Output Compare Configuration Structure definition |
67 | */ |
| 68 | */ |
68 | typedef struct |
| 69 | typedef struct |
69 | { |
| 70 | { |
70 | uint32_t OCMode; /*!< Specifies the TIM mode. |
| 71 | uint32_t OCMode; /*!< Specifies the TIM mode. |
71 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
| 72 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
72 | |
| 73 | 73 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
|
| 74 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
74 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| 75 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
75 | |
| 76 | 76 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
|
| 77 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
77 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
| 78 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
78 | |
| 79 | 79 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
|
| 80 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
80 | This parameter can be a value of @ref TIM_Output_Fast_State |
| 81 | This parameter can be a value of @ref TIM_Output_Fast_State |
81 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
| 82 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
82 | } TIM_OC_InitTypeDef; |
| 83 | } TIM_OC_InitTypeDef; |
83 | |
| 84 | 84 | /** |
|
| 85 | /** |
85 | * @brief TIM One Pulse Mode Configuration Structure definition |
| 86 | * @brief TIM One Pulse Mode Configuration Structure definition |
86 | */ |
| 87 | */ |
87 | typedef struct |
| 88 | typedef struct |
88 | { |
| 89 | { |
89 | uint32_t OCMode; /*!< Specifies the TIM mode. |
| 90 | uint32_t OCMode; /*!< Specifies the TIM mode. |
90 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
| 91 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
91 | |
| 92 | 92 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
|
| 93 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
93 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| 94 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
94 | |
| 95 | 95 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
|
| 96 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
96 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
| 97 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
97 | |
| 98 | 98 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
|
| 99 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
99 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| 100 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
100 | |
| 101 | 101 | uint32_t ICSelection; /*!< Specifies the input. |
|
| 102 | uint32_t ICSelection; /*!< Specifies the input. |
102 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 103 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
103 | |
| 104 | 104 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
|
| 105 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
105 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 106 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
106 | } TIM_OnePulse_InitTypeDef; |
| 107 | } TIM_OnePulse_InitTypeDef; |
107 | |
| 108 | 108 | /** |
|
| 109 | /** |
109 | * @brief TIM Input Capture Configuration Structure definition |
| 110 | * @brief TIM Input Capture Configuration Structure definition |
110 | */ |
| 111 | */ |
111 | typedef struct |
| 112 | typedef struct |
112 | { |
| 113 | { |
113 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
| 114 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
114 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| 115 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
115 | |
| 116 | 116 | uint32_t ICSelection; /*!< Specifies the input. |
|
| 117 | uint32_t ICSelection; /*!< Specifies the input. |
117 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 118 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
118 | |
| 119 | 119 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
|
| 120 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
120 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| 121 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
121 | |
| 122 | 122 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
|
| 123 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
123 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 124 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
124 | } TIM_IC_InitTypeDef; |
| 125 | } TIM_IC_InitTypeDef; |
125 | |
| 126 | 126 | /** |
|
| 127 | /** |
127 | * @brief TIM Encoder Configuration Structure definition |
| 128 | * @brief TIM Encoder Configuration Structure definition |
128 | */ |
| 129 | */ |
129 | typedef struct |
| 130 | typedef struct |
130 | { |
| 131 | { |
131 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
| 132 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
132 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
| 133 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
133 | |
| 134 | 134 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
|
| 135 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
135 | This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ |
| 136 | This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ |
136 | |
| 137 | 137 | uint32_t IC1Selection; /*!< Specifies the input. |
|
| 138 | uint32_t IC1Selection; /*!< Specifies the input. |
138 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 139 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
139 | |
| 140 | 140 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
|
| 141 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
141 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| 142 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
142 | |
| 143 | 143 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
|
| 144 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
144 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 145 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
145 | |
| 146 | 146 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
|
| 147 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
147 | This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ |
| 148 | This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ |
148 | |
| 149 | 149 | uint32_t IC2Selection; /*!< Specifies the input. |
|
| 150 | uint32_t IC2Selection; /*!< Specifies the input. |
150 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 151 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
151 | |
| 152 | 152 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
|
| 153 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
153 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| 154 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
154 | |
| 155 | 155 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
|
| 156 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
156 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 157 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
157 | } TIM_Encoder_InitTypeDef; |
| 158 | } TIM_Encoder_InitTypeDef; |
158 | |
| 159 | 159 | /** |
|
| 160 | /** |
160 | * @brief Clock Configuration Handle Structure definition |
| 161 | * @brief Clock Configuration Handle Structure definition |
161 | */ |
| 162 | */ |
162 | typedef struct |
| 163 | typedef struct |
163 | { |
| 164 | { |
164 | uint32_t ClockSource; /*!< TIM clock sources |
| 165 | uint32_t ClockSource; /*!< TIM clock sources |
165 | This parameter can be a value of @ref TIM_Clock_Source */ |
| 166 | This parameter can be a value of @ref TIM_Clock_Source */ |
166 | uint32_t ClockPolarity; /*!< TIM clock polarity |
| 167 | uint32_t ClockPolarity; /*!< TIM clock polarity |
167 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
| 168 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
168 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
| 169 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
169 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
| 170 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
170 | uint32_t ClockFilter; /*!< TIM clock filter |
| 171 | uint32_t ClockFilter; /*!< TIM clock filter |
171 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 172 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
172 | } TIM_ClockConfigTypeDef; |
| 173 | } TIM_ClockConfigTypeDef; |
173 | |
| 174 | 174 | /** |
|
| 175 | /** |
175 | * @brief TIM Clear Input Configuration Handle Structure definition |
| 176 | * @brief TIM Clear Input Configuration Handle Structure definition |
176 | */ |
| 177 | */ |
177 | typedef struct |
| 178 | typedef struct |
178 | { |
| 179 | { |
179 | uint32_t ClearInputState; /*!< TIM clear Input state |
| 180 | uint32_t ClearInputState; /*!< TIM clear Input state |
180 | This parameter can be ENABLE or DISABLE */ |
| 181 | This parameter can be ENABLE or DISABLE */ |
181 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
| 182 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
182 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
| 183 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
183 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
| 184 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
184 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
| 185 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
185 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
| 186 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
186 | This parameter must be 0: When OCRef clear feature is used with ETR source, |
| 187 | This parameter must be 0: When OCRef clear feature is used with ETR source, |
187 | ETR prescaler must be off */ |
| 188 | ETR prescaler must be off */ |
188 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
| 189 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
189 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 190 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
190 | } TIM_ClearInputConfigTypeDef; |
| 191 | } TIM_ClearInputConfigTypeDef; |
191 | |
| 192 | 192 | /** |
|
| 193 | /** |
193 | * @brief TIM Master configuration Structure definition |
| 194 | * @brief TIM Master configuration Structure definition |
194 | */ |
| 195 | */ |
195 | typedef struct |
| 196 | typedef struct |
196 | { |
| 197 | { |
197 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
| 198 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
198 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
| 199 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
199 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
| 200 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
200 | This parameter can be a value of @ref TIM_Master_Slave_Mode |
| 201 | This parameter can be a value of @ref TIM_Master_Slave_Mode |
201 | @note When the Master/slave mode is enabled, the effect of |
| 202 | @note When the Master/slave mode is enabled, the effect of |
202 | an event on the trigger input (TRGI) is delayed to allow a |
| 203 | an event on the trigger input (TRGI) is delayed to allow a |
203 | perfect synchronization between the current timer and its |
| 204 | perfect synchronization between the current timer and its |
204 | slaves (through TRGO). It is not mandatory in case of timer |
| 205 | slaves (through TRGO). It is not mandatory in case of timer |
205 | synchronization mode. */ |
| 206 | synchronization mode. */ |
206 | } TIM_MasterConfigTypeDef; |
| 207 | } TIM_MasterConfigTypeDef; |
207 | |
| 208 | 208 | /** |
|
| 209 | /** |
209 | * @brief TIM Slave configuration Structure definition |
| 210 | * @brief TIM Slave configuration Structure definition |
210 | */ |
| 211 | */ |
211 | typedef struct |
| 212 | typedef struct |
212 | { |
| 213 | { |
213 | uint32_t SlaveMode; /*!< Slave mode selection |
| 214 | uint32_t SlaveMode; /*!< Slave mode selection |
214 | This parameter can be a value of @ref TIM_Slave_Mode */ |
| 215 | This parameter can be a value of @ref TIM_Slave_Mode */ |
215 | uint32_t InputTrigger; /*!< Input Trigger source |
| 216 | uint32_t InputTrigger; /*!< Input Trigger source |
216 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
| 217 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
217 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
| 218 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
218 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
| 219 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
219 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
| 220 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
220 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
| 221 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
221 | uint32_t TriggerFilter; /*!< Input trigger filter |
| 222 | uint32_t TriggerFilter; /*!< Input trigger filter |
222 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 223 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
223 | |
| 224 | 224 | } TIM_SlaveConfigTypeDef; |
|
| 225 | } TIM_SlaveConfigTypeDef; |
225 | |
| 226 | 226 | /** |
|
| 227 | /** |
227 | * @brief HAL State structures definition |
| 228 | * @brief HAL State structures definition |
228 | */ |
| 229 | */ |
229 | typedef enum |
| 230 | typedef enum |
230 | { |
| 231 | { |
231 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
| 232 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
232 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| 233 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
233 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
| 234 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
234 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
| 235 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
235 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
| 236 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
236 | } HAL_TIM_StateTypeDef; |
| 237 | } HAL_TIM_StateTypeDef; |
237 | |
| 238 | 238 | /** |
|
| 239 | /** |
239 | * @brief TIM Channel States definition |
| 240 | * @brief TIM Channel States definition |
240 | */ |
| 241 | */ |
241 | typedef enum |
| 242 | typedef enum |
242 | { |
| 243 | { |
243 | HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ |
| 244 | HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ |
244 | HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ |
| 245 | HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ |
245 | HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ |
| 246 | HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ |
246 | } HAL_TIM_ChannelStateTypeDef; |
| 247 | } HAL_TIM_ChannelStateTypeDef; |
247 | |
| 248 | 248 | /** |
|
| 249 | /** |
249 | * @brief DMA Burst States definition |
| 250 | * @brief DMA Burst States definition |
250 | */ |
| 251 | */ |
251 | typedef enum |
| 252 | typedef enum |
252 | { |
| 253 | { |
253 | HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ |
| 254 | HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ |
254 | HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ |
| 255 | HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ |
255 | HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ |
| 256 | HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ |
256 | } HAL_TIM_DMABurstStateTypeDef; |
| 257 | } HAL_TIM_DMABurstStateTypeDef; |
257 | |
| 258 | 258 | /** |
|
| 259 | /** |
259 | * @brief HAL Active channel structures definition |
| 260 | * @brief HAL Active channel structures definition |
260 | */ |
| 261 | */ |
261 | typedef enum |
| 262 | typedef enum |
262 | { |
| 263 | { |
263 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
| 264 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
264 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
| 265 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
265 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
| 266 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
266 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
| 267 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
267 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
| 268 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
268 | } HAL_TIM_ActiveChannel; |
| 269 | } HAL_TIM_ActiveChannel; |
269 | |
| 270 | 270 | /** |
|
| 271 | /** |
271 | * @brief TIM Time Base Handle Structure definition |
| 272 | * @brief TIM Time Base Handle Structure definition |
272 | */ |
| 273 | */ |
273 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 274 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
274 | typedef struct __TIM_HandleTypeDef |
| 275 | typedef struct __TIM_HandleTypeDef |
275 | #else |
| 276 | #else |
276 | typedef struct |
| 277 | typedef struct |
277 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 278 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
278 | { |
| 279 | { |
279 | TIM_TypeDef *Instance; /*!< Register base address */ |
| 280 | TIM_TypeDef *Instance; /*!< Register base address */ |
280 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
| 281 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
281 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
| 282 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
282 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
| 283 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
283 | This array is accessed by a @ref DMA_Handle_index */ |
| 284 | This array is accessed by a @ref DMA_Handle_index */ |
284 | HAL_LockTypeDef Lock; /*!< Locking object */ |
| 285 | HAL_LockTypeDef Lock; /*!< Locking object */ |
285 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
| 286 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
286 | __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ |
| 287 | __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ |
287 | __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ |
| 288 | __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ |
288 | |
| 289 | 289 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
| 290 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
290 | void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ |
| 291 | void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ |
291 | void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ |
| 292 | void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ |
292 | void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ |
| 293 | void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ |
293 | void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ |
| 294 | void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ |
294 | void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ |
| 295 | void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ |
295 | void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ |
| 296 | void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ |
296 | void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ |
| 297 | void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ |
297 | void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ |
| 298 | void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ |
298 | void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ |
| 299 | void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ |
299 | void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ |
| 300 | void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ |
300 | void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ |
| 301 | void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ |
301 | void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ |
| 302 | void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ |
302 | void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ |
| 303 | void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ |
303 | void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ |
| 304 | void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ |
304 | void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ |
| 305 | void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ |
305 | void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ |
| 306 | void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ |
306 | void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ |
| 307 | void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ |
307 | void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ |
| 308 | void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ |
308 | void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ |
| 309 | void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ |
309 | void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ |
| 310 | void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ |
310 | void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ |
| 311 | void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ |
311 | void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ |
| 312 | void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ |
312 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 313 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
313 | } TIM_HandleTypeDef; |
| 314 | } TIM_HandleTypeDef; |
314 | |
| 315 | 315 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
| 316 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
316 | /** |
| 317 | /** |
317 | * @brief HAL TIM Callback ID enumeration definition |
| 318 | * @brief HAL TIM Callback ID enumeration definition |
318 | */ |
| 319 | */ |
319 | typedef enum |
| 320 | typedef enum |
320 | { |
| 321 | { |
321 | HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ |
| 322 | HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ |
322 | , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ |
| 323 | , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ |
323 | , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ |
| 324 | , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ |
324 | , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ |
| 325 | , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ |
325 | , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ |
| 326 | , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ |
326 | , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ |
| 327 | , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ |
327 | , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ |
| 328 | , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ |
328 | , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ |
| 329 | , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ |
329 | , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ |
| 330 | , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ |
330 | , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ |
| 331 | , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ |
331 | , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ |
| 332 | , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ |
332 | , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ |
| 333 | , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ |
333 | , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ |
| 334 | , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ |
334 | , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ |
| 335 | , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ |
335 | , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ |
| 336 | , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ |
336 | , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ |
| 337 | , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ |
337 | |
| 338 | 338 | , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ |
|
| 339 | , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ |
339 | , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ |
| 340 | , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ |
340 | , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ |
| 341 | , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ |
341 | , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ |
| 342 | , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ |
342 | , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ |
| 343 | , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ |
343 | , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ |
| 344 | , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ |
344 | } HAL_TIM_CallbackIDTypeDef; |
| 345 | } HAL_TIM_CallbackIDTypeDef; |
345 | |
| 346 | 346 | /** |
|
| 347 | /** |
347 | * @brief HAL TIM Callback pointer definition |
| 348 | * @brief HAL TIM Callback pointer definition |
348 | */ |
| 349 | */ |
349 | typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ |
| 350 | typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ |
350 | |
| 351 | 351 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
| 352 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
352 | |
| 353 | 353 | /** |
|
| 354 | /** |
354 | * @} |
| 355 | * @} |
355 | */ |
| 356 | */ |
356 | /* End of exported types -----------------------------------------------------*/ |
| 357 | /* End of exported types -----------------------------------------------------*/ |
357 | |
| 358 | 358 | /* Exported constants --------------------------------------------------------*/ |
|
| 359 | /* Exported constants --------------------------------------------------------*/ |
359 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
| 360 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
360 | * @{ |
| 361 | * @{ |
361 | */ |
| 362 | */ |
362 | |
| 363 | 363 | /** @defgroup TIM_ClearInput_Source TIM Clear Input Source |
|
| 364 | /** @defgroup TIM_ClearInput_Source TIM Clear Input Source |
364 | * @{ |
| 365 | * @{ |
365 | */ |
| 366 | */ |
366 | #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ |
| 367 | #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ |
367 | #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ |
| 368 | #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ |
368 | #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ |
| 369 | #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ |
369 | /** |
| 370 | /** |
370 | * @} |
| 371 | * @} |
371 | */ |
| 372 | */ |
372 | |
| 373 | 373 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
|
| 374 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
374 | * @{ |
| 375 | * @{ |
375 | */ |
| 376 | */ |
376 | #define TIM_DMABASE_CR1 0x00000000U |
| 377 | #define TIM_DMABASE_CR1 0x00000000U |
377 | #define TIM_DMABASE_CR2 0x00000001U |
| 378 | #define TIM_DMABASE_CR2 0x00000001U |
378 | #define TIM_DMABASE_SMCR 0x00000002U |
| 379 | #define TIM_DMABASE_SMCR 0x00000002U |
379 | #define TIM_DMABASE_DIER 0x00000003U |
| 380 | #define TIM_DMABASE_DIER 0x00000003U |
380 | #define TIM_DMABASE_SR 0x00000004U |
| 381 | #define TIM_DMABASE_SR 0x00000004U |
381 | #define TIM_DMABASE_EGR 0x00000005U |
| 382 | #define TIM_DMABASE_EGR 0x00000005U |
382 | #define TIM_DMABASE_CCMR1 0x00000006U |
| 383 | #define TIM_DMABASE_CCMR1 0x00000006U |
383 | #define TIM_DMABASE_CCMR2 0x00000007U |
| 384 | #define TIM_DMABASE_CCMR2 0x00000007U |
384 | #define TIM_DMABASE_CCER 0x00000008U |
| 385 | #define TIM_DMABASE_CCER 0x00000008U |
385 | #define TIM_DMABASE_CNT 0x00000009U |
| 386 | #define TIM_DMABASE_CNT 0x00000009U |
386 | #define TIM_DMABASE_PSC 0x0000000AU |
| 387 | #define TIM_DMABASE_PSC 0x0000000AU |
387 | #define TIM_DMABASE_ARR 0x0000000BU |
| 388 | #define TIM_DMABASE_ARR 0x0000000BU |
388 | #define TIM_DMABASE_CCR1 0x0000000DU |
| 389 | #define TIM_DMABASE_CCR1 0x0000000DU |
389 | #define TIM_DMABASE_CCR2 0x0000000EU |
| 390 | #define TIM_DMABASE_CCR2 0x0000000EU |
390 | #define TIM_DMABASE_CCR3 0x0000000FU |
| 391 | #define TIM_DMABASE_CCR3 0x0000000FU |
391 | #define TIM_DMABASE_CCR4 0x00000010U |
| 392 | #define TIM_DMABASE_CCR4 0x00000010U |
392 | #define TIM_DMABASE_DCR 0x00000012U |
| 393 | #define TIM_DMABASE_DCR 0x00000012U |
393 | #define TIM_DMABASE_DMAR 0x00000013U |
| 394 | #define TIM_DMABASE_DMAR 0x00000013U |
394 | #define TIM_DMABASE_OR 0x00000014U |
| 395 | #define TIM_DMABASE_OR 0x00000014U |
395 | /** |
| 396 | /** |
396 | * @} |
| 397 | * @} |
397 | */ |
| 398 | */ |
398 | |
| 399 | 399 | /** @defgroup TIM_Event_Source TIM Event Source |
|
| 400 | /** @defgroup TIM_Event_Source TIM Event Source |
400 | * @{ |
| 401 | * @{ |
401 | */ |
| 402 | */ |
402 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
| 403 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
403 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ |
| 404 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ |
404 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ |
| 405 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ |
405 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ |
| 406 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ |
406 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ |
| 407 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ |
407 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ |
| 408 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ |
408 | /** |
| 409 | /** |
409 | * @} |
| 410 | * @} |
410 | */ |
| 411 | */ |
411 | |
| 412 | 412 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity |
|
| 413 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity |
413 | * @{ |
| 414 | * @{ |
414 | */ |
| 415 | */ |
415 | #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ |
| 416 | #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ |
416 | #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ |
| 417 | #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ |
417 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
| 418 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
418 | /** |
| 419 | /** |
419 | * @} |
| 420 | * @} |
420 | */ |
| 421 | */ |
421 | |
| 422 | 422 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
|
| 423 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
423 | * @{ |
| 424 | * @{ |
424 | */ |
| 425 | */ |
425 | #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ |
| 426 | #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ |
426 | #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ |
| 427 | #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ |
427 | /** |
| 428 | /** |
428 | * @} |
| 429 | * @} |
429 | */ |
| 430 | */ |
430 | |
| 431 | 431 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
|
| 432 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
432 | * @{ |
| 433 | * @{ |
433 | */ |
| 434 | */ |
434 | #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ |
| 435 | #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ |
435 | #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ |
| 436 | #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ |
436 | #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ |
| 437 | #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ |
437 | #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ |
| 438 | #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ |
438 | /** |
| 439 | /** |
439 | * @} |
| 440 | * @} |
440 | */ |
| 441 | */ |
441 | |
| 442 | 442 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
|
| 443 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
443 | * @{ |
| 444 | * @{ |
444 | */ |
| 445 | */ |
445 | #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ |
| 446 | #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ |
446 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ |
| 447 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ |
447 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ |
| 448 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ |
448 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ |
| 449 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ |
449 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ |
| 450 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ |
450 | /** |
| 451 | /** |
451 | * @} |
| 452 | * @} |
452 | */ |
| 453 | */ |
453 | |
| 454 | 454 | /** @defgroup TIM_ClockDivision TIM Clock Division |
|
| 455 | /** @defgroup TIM_ClockDivision TIM Clock Division |
455 | * @{ |
| 456 | * @{ |
456 | */ |
| 457 | */ |
457 | #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ |
| 458 | #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ |
458 | #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ |
| 459 | #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ |
459 | #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ |
| 460 | #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ |
460 | /** |
| 461 | /** |
461 | * @} |
| 462 | * @} |
462 | */ |
| 463 | */ |
463 | |
| 464 | 464 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
|
| 465 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
465 | * @{ |
| 466 | * @{ |
466 | */ |
| 467 | */ |
467 | #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ |
| 468 | #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ |
468 | #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ |
| 469 | #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ |
469 | /** |
| 470 | /** |
470 | * @} |
| 471 | * @} |
471 | */ |
| 472 | */ |
472 | |
| 473 | 473 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
|
| 474 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
474 | * @{ |
| 475 | * @{ |
475 | */ |
| 476 | */ |
476 | #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ |
| 477 | #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ |
477 | #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ |
| 478 | #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ |
478 | |
| 479 | 479 | /** |
|
| 480 | /** |
480 | * @} |
| 481 | * @} |
481 | */ |
| 482 | */ |
482 | |
| 483 | 483 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
|
| 484 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
484 | * @{ |
| 485 | * @{ |
485 | */ |
| 486 | */ |
486 | #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ |
| 487 | #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ |
487 | #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ |
| 488 | #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ |
488 | /** |
| 489 | /** |
489 | * @} |
| 490 | * @} |
490 | */ |
| 491 | */ |
491 | |
| 492 | 492 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
|
| 493 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
493 | * @{ |
| 494 | * @{ |
494 | */ |
| 495 | */ |
495 | #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ |
| 496 | #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ |
496 | #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ |
| 497 | #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ |
497 | /** |
| 498 | /** |
498 | * @} |
| 499 | * @} |
499 | */ |
| 500 | */ |
500 | |
| 501 | 501 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
|
| 502 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
502 | * @{ |
| 503 | * @{ |
503 | */ |
| 504 | */ |
504 | #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ |
| 505 | #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ |
505 | #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ |
| 506 | #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ |
506 | /** |
| 507 | /** |
507 | * @} |
| 508 | * @} |
508 | */ |
| 509 | */ |
509 | |
| 510 | 510 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
|
| 511 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
511 | * @{ |
| 512 | * @{ |
512 | */ |
| 513 | */ |
513 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ |
| 514 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ |
514 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ |
| 515 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ |
515 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ |
| 516 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ |
516 | /** |
| 517 | /** |
517 | * @} |
| 518 | * @} |
518 | */ |
| 519 | */ |
519 | |
| 520 | 520 | /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity |
|
| 521 | /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity |
521 | * @{ |
| 522 | * @{ |
522 | */ |
| 523 | */ |
523 | #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ |
| 524 | #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ |
524 | #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ |
| 525 | #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ |
525 | /** |
| 526 | /** |
526 | * @} |
| 527 | * @} |
527 | */ |
| 528 | */ |
528 | |
| 529 | 529 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
|
| 530 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
530 | * @{ |
| 531 | * @{ |
531 | */ |
| 532 | */ |
532 | #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ |
| 533 | #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ |
533 | #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ |
| 534 | #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ |
534 | #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
| 535 | #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
535 | /** |
| 536 | /** |
536 | * @} |
| 537 | * @} |
537 | */ |
| 538 | */ |
538 | |
| 539 | 539 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
|
| 540 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
540 | * @{ |
| 541 | * @{ |
541 | */ |
| 542 | */ |
542 | #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ |
| 543 | #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ |
543 | #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ |
| 544 | #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ |
544 | #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ |
| 545 | #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ |
545 | #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ |
| 546 | #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ |
546 | /** |
| 547 | /** |
547 | * @} |
| 548 | * @} |
548 | */ |
| 549 | */ |
549 | |
| 550 | 550 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
|
| 551 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
551 | * @{ |
| 552 | * @{ |
552 | */ |
| 553 | */ |
553 | #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
| 554 | #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
554 | #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
| 555 | #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
555 | /** |
| 556 | /** |
556 | * @} |
| 557 | * @} |
557 | */ |
| 558 | */ |
558 | |
| 559 | 559 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
|
| 560 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
560 | * @{ |
| 561 | * @{ |
561 | */ |
| 562 | */ |
562 | #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
| 563 | #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
563 | #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ |
| 564 | #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ |
564 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ |
| 565 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ |
565 | /** |
| 566 | /** |
566 | * @} |
| 567 | * @} |
567 | */ |
| 568 | */ |
568 | |
| 569 | 569 | /** @defgroup TIM_Interrupt_definition TIM interrupt Definition |
|
| 570 | /** @defgroup TIM_Interrupt_definition TIM interrupt Definition |
570 | * @{ |
| 571 | * @{ |
571 | */ |
| 572 | */ |
572 | #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ |
| 573 | #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ |
573 | #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ |
| 574 | #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ |
574 | #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ |
| 575 | #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ |
575 | #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ |
| 576 | #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ |
576 | #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ |
| 577 | #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ |
577 | #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ |
| 578 | #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ |
578 | /** |
| 579 | /** |
579 | * @} |
| 580 | * @} |
580 | */ |
| 581 | */ |
581 | |
| 582 | 582 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
|
| 583 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
583 | * @{ |
| 584 | * @{ |
584 | */ |
| 585 | */ |
585 | #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ |
| 586 | #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ |
586 | #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ |
| 587 | #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ |
587 | #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ |
| 588 | #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ |
588 | #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ |
| 589 | #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ |
589 | #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ |
| 590 | #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ |
590 | #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ |
| 591 | #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ |
591 | /** |
| 592 | /** |
592 | * @} |
| 593 | * @} |
593 | */ |
| 594 | */ |
594 | |
| 595 | 595 | /** @defgroup TIM_CC_DMA_Request CCx DMA request selection |
|
| 596 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
596 | * @{ |
| 597 | * @{ |
597 | */ |
| 598 | */ |
598 | #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ |
| 599 | #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ |
599 | #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
| 600 | #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ |
600 | /** |
| 601 | #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ |
601 | * @} |
| 602 | #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ |
602 | */ |
| 603 | #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ |
603 | |
| 604 | #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ |
604 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
| 605 | #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ |
605 | * @{ |
| 606 | #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ |
606 | */ |
| 607 | #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ |
607 | #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ |
| 608 | #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ |
608 | #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ |
| 609 | /** |
609 | #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ |
| 610 | * @} |
610 | #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ |
| 611 | */ |
611 | #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ |
| 612 | 612 | #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ |
|
| 613 | /** @defgroup TIM_Channel TIM Channel |
613 | #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ |
| 614 | * @{ |
614 | #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ |
| 615 | */ |
615 | #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ |
| 616 | #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ |
616 | #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ |
| 617 | #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ |
617 | /** |
| 618 | #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ |
618 | * @} |
| 619 | #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ |
619 | */ |
| 620 | #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ |
620 | |
| 621 | /** |
621 | /** @defgroup TIM_Channel TIM Channel |
| 622 | * @} |
622 | * @{ |
| 623 | */ |
623 | */ |
| 624 | 624 | #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ |
|
| 625 | /** @defgroup TIM_Clock_Source TIM Clock Source |
625 | #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ |
| 626 | * @{ |
626 | #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ |
| 627 | */ |
627 | #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ |
| 628 | #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ |
628 | #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ |
| 629 | #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ |
629 | /** |
| 630 | #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ |
630 | * @} |
| 631 | #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ |
631 | */ |
| 632 | #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ |
632 | |
| 633 | #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ |
633 | /** @defgroup TIM_Clock_Source TIM Clock Source |
| 634 | #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ |
634 | * @{ |
| 635 | #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ |
635 | */ |
| 636 | #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ |
636 | #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ |
| 637 | #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ |
637 | #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ |
| 638 | /** |
638 | #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ |
| 639 | * @} |
639 | #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ |
| 640 | */ |
640 | #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ |
| 641 | 641 | #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ |
|
| 642 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
642 | #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ |
| 643 | * @{ |
643 | #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ |
| 644 | */ |
644 | #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ |
| 645 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
645 | #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ |
| 646 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
646 | /** |
| 647 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
647 | * @} |
| 648 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
648 | */ |
| 649 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
649 | |
| 650 | /** |
650 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
| 651 | * @} |
651 | * @{ |
| 652 | */ |
652 | */ |
| 653 | 653 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
|
| 654 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
654 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
| 655 | * @{ |
655 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
| 656 | */ |
656 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
| 657 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
657 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
| 658 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
658 | /** |
| 659 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
659 | * @} |
| 660 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
660 | */ |
| 661 | /** |
661 | |
| 662 | * @} |
662 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
| 663 | */ |
663 | * @{ |
| 664 | 664 | */ |
|
| 665 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
665 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
| 666 | * @{ |
666 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
| 667 | */ |
667 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
| 668 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
668 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
| 669 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
669 | /** |
| 670 | /** |
670 | * @} |
| 671 | * @} |
671 | */ |
| 672 | */ |
672 | |
| 673 | 673 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
|
| 674 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
674 | * @{ |
| 675 | * @{ |
675 | */ |
| 676 | */ |
676 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
| 677 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
677 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
| 678 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
678 | /** |
| 679 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
679 | * @} |
| 680 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
680 | */ |
| 681 | /** |
681 | |
| 682 | * @} |
682 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
| 683 | */ |
683 | * @{ |
| 684 | 684 | */ |
|
| 685 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
685 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
| 686 | * @{ |
686 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
| 687 | */ |
687 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
| 688 | #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ |
688 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
| 689 | #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ |
689 | /** |
| 690 | #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ |
690 | * @} |
| 691 | #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ |
691 | */ |
| 692 | #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ |
692 | |
| 693 | #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ |
693 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
| 694 | #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ |
694 | * @{ |
| 695 | #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ |
695 | */ |
| 696 | /** |
696 | #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ |
| 697 | * @} |
697 | #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ |
| 698 | */ |
698 | #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ |
| 699 | 699 | #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ |
|
| 700 | /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode |
700 | #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ |
| 701 | * @{ |
701 | #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ |
| 702 | */ |
702 | #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ |
| 703 | #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ |
703 | #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ |
| 704 | #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ |
704 | /** |
| 705 | /** |
705 | * @} |
| 706 | * @} |
706 | */ |
| 707 | */ |
707 | |
| 708 | 708 | /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode |
|
| 709 | /** @defgroup TIM_Slave_Mode TIM Slave mode |
709 | * @{ |
| 710 | * @{ |
710 | */ |
| 711 | */ |
711 | #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ |
| 712 | #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ |
712 | #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ |
| 713 | #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ |
713 | /** |
| 714 | #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ |
714 | * @} |
| 715 | #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ |
715 | */ |
| 716 | #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ |
716 | |
| 717 | /** |
717 | /** @defgroup TIM_Slave_Mode TIM Slave mode |
| 718 | * @} |
718 | * @{ |
| 719 | */ |
719 | */ |
| 720 | 720 | #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ |
|
| 721 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes |
721 | #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ |
| 722 | * @{ |
722 | #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ |
| 723 | */ |
723 | #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ |
| 724 | #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ |
724 | #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ |
| 725 | #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ |
725 | /** |
| 726 | #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ |
726 | * @} |
| 727 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ |
727 | */ |
| 728 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ |
728 | |
| 729 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ |
729 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes |
| 730 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ |
730 | * @{ |
| 731 | #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ |
731 | */ |
| 732 | /** |
732 | #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ |
| 733 | * @} |
733 | #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ |
| 734 | */ |
734 | #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ |
| 735 | 735 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ |
|
| 736 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
736 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ |
| 737 | * @{ |
737 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ |
| 738 | */ |
738 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ |
| 739 | #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ |
739 | #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ |
| 740 | #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ |
740 | /** |
| 741 | #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ |
741 | * @} |
| 742 | #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ |
742 | */ |
| 743 | #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ |
743 | |
| 744 | #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ |
744 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
| 745 | #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ |
745 | * @{ |
| 746 | #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ |
746 | */ |
| 747 | #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ |
747 | #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ |
| 748 | /** |
748 | #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ |
| 749 | * @} |
749 | #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ |
| 750 | */ |
750 | #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ |
| 751 | 751 | #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ |
|
| 752 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
752 | #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ |
| 753 | * @{ |
753 | #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ |
| 754 | */ |
754 | #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ |
| 755 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
755 | #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ |
| 756 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
756 | /** |
| 757 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
757 | * @} |
| 758 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
758 | */ |
| 759 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
759 | |
| 760 | /** |
760 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
| 761 | * @} |
761 | * @{ |
| 762 | */ |
762 | */ |
| 763 | 763 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
|
| 764 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
764 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
| 765 | * @{ |
765 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
| 766 | */ |
766 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
| 767 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
767 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
| 768 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
768 | /** |
| 769 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
769 | * @} |
| 770 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
770 | */ |
| 771 | /** |
771 | |
| 772 | * @} |
772 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
| 773 | */ |
773 | * @{ |
| 774 | 774 | */ |
|
| 775 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
775 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
| 776 | * @{ |
776 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
| 777 | */ |
777 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
| 778 | #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ |
778 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
| 779 | #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ |
779 | /** |
| 780 | /** |
780 | * @} |
| 781 | * @} |
781 | */ |
| 782 | */ |
782 | |
| 783 | 783 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
|
| 784 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
784 | * @{ |
| 785 | * @{ |
785 | */ |
| 786 | */ |
786 | #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ |
| 787 | #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ |
787 | #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ |
| 788 | #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
788 | /** |
| 789 | #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
789 | * @} |
| 790 | #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
790 | */ |
| 791 | #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
791 | |
| 792 | #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
792 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
| 793 | #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
793 | * @{ |
| 794 | #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
794 | */ |
| 795 | #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
795 | #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 796 | #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
796 | #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 797 | #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
797 | #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 798 | #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
798 | #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 799 | #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
799 | #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 800 | #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
800 | #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 801 | #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
801 | #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 802 | #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
802 | #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 803 | #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
803 | #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 804 | #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
804 | #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 805 | /** |
805 | #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 806 | * @} |
806 | #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 807 | */ |
807 | #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 808 | 808 | #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
|
| 809 | /** @defgroup DMA_Handle_index TIM DMA Handle Index |
809 | #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 810 | * @{ |
810 | #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 811 | */ |
811 | #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 812 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ |
812 | #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 813 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
813 | /** |
| 814 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
814 | * @} |
| 815 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
815 | */ |
| 816 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
816 | |
| 817 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ |
817 | /** @defgroup DMA_Handle_index TIM DMA Handle Index |
| 818 | /** |
818 | * @{ |
| 819 | * @} |
819 | */ |
| 820 | */ |
820 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ |
| 821 | 821 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
|
| 822 | /** @defgroup Channel_CC_State TIM Capture/Compare Channel State |
822 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
| 823 | * @{ |
823 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
| 824 | */ |
824 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
| 825 | #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ |
825 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ |
| 826 | #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ |
826 | /** |
| 827 | /** |
827 | * @} |
| 828 | * @} |
828 | */ |
| 829 | */ |
829 | |
| 830 | 830 | /** @defgroup Channel_CC_State TIM Capture/Compare Channel State |
|
| 831 | /** |
831 | * @{ |
| 832 | * @} |
832 | */ |
| 833 | */ |
833 | #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ |
| 834 | /* End of exported constants -------------------------------------------------*/ |
834 | #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ |
| 835 | 835 | /** |
|
| 836 | /* Exported macros -----------------------------------------------------------*/ |
836 | * @} |
| 837 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
837 | */ |
| 838 | * @{ |
838 | |
| 839 | */ |
839 | /** |
| 840 | 840 | * @} |
|
| 841 | /** @brief Reset TIM handle state. |
841 | */ |
| 842 | * @param __HANDLE__ TIM handle. |
842 | /* End of exported constants -------------------------------------------------*/ |
| 843 | * @retval None |
843 | |
| 844 | */ |
844 | /* Exported macros -----------------------------------------------------------*/ |
| 845 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
845 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
| 846 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
846 | * @{ |
| 847 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
847 | */ |
| 848 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
848 | |
| 849 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
849 | /** @brief Reset TIM handle state. |
| 850 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
850 | * @param __HANDLE__ TIM handle. |
| 851 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
851 | * @retval None |
| 852 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
852 | */ |
| 853 | (__HANDLE__)->Base_MspInitCallback = NULL; \ |
853 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 854 | (__HANDLE__)->Base_MspDeInitCallback = NULL; \ |
854 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
| 855 | (__HANDLE__)->IC_MspInitCallback = NULL; \ |
855 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
| 856 | (__HANDLE__)->IC_MspDeInitCallback = NULL; \ |
856 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 857 | (__HANDLE__)->OC_MspInitCallback = NULL; \ |
857 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 858 | (__HANDLE__)->OC_MspDeInitCallback = NULL; \ |
858 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 859 | (__HANDLE__)->PWM_MspInitCallback = NULL; \ |
859 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 860 | (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ |
860 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
| 861 | (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ |
861 | (__HANDLE__)->Base_MspInitCallback = NULL; \ |
| 862 | (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ |
862 | (__HANDLE__)->Base_MspDeInitCallback = NULL; \ |
| 863 | (__HANDLE__)->Encoder_MspInitCallback = NULL; \ |
863 | (__HANDLE__)->IC_MspInitCallback = NULL; \ |
| 864 | (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ |
864 | (__HANDLE__)->IC_MspDeInitCallback = NULL; \ |
| 865 | } while(0) |
865 | (__HANDLE__)->OC_MspInitCallback = NULL; \ |
| 866 | #else |
866 | (__HANDLE__)->OC_MspDeInitCallback = NULL; \ |
| 867 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
867 | (__HANDLE__)->PWM_MspInitCallback = NULL; \ |
| 868 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
868 | (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ |
| 869 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
869 | (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ |
| 870 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
870 | (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ |
| 871 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
871 | (__HANDLE__)->Encoder_MspInitCallback = NULL; \ |
| 872 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
872 | (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ |
| 873 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
873 | } while(0) |
| 874 | } while(0) |
874 | #else |
| 875 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
875 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
| 876 | 876 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
|
| 877 | /** |
877 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 878 | * @brief Enable the TIM peripheral. |
878 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 879 | * @param __HANDLE__ TIM handle |
879 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 880 | * @retval None |
880 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 881 | */ |
881 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
| 882 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
882 | } while(0) |
| 883 | 883 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
| 884 | /** |
884 | |
| 885 | * @brief Disable the TIM peripheral. |
885 | /** |
| 886 | * @param __HANDLE__ TIM handle |
886 | * @brief Enable the TIM peripheral. |
| 887 | * @retval None |
887 | * @param __HANDLE__ TIM handle |
| 888 | */ |
888 | * @retval None |
| 889 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
889 | */ |
| 890 | do { \ |
890 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
| 891 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ |
891 | |
| 892 | { \ |
892 | /** |
| 893 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
893 | * @brief Disable the TIM peripheral. |
| 894 | } \ |
894 | * @param __HANDLE__ TIM handle |
| 895 | } while(0) |
895 | * @retval None |
| 896 | 896 | */ |
|
| 897 | /** @brief Enable the specified TIM interrupt. |
897 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
| 898 | * @param __HANDLE__ specifies the TIM Handle. |
898 | do { \ |
| 899 | * @param __INTERRUPT__ specifies the TIM interrupt source to enable. |
899 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ |
| 900 | * This parameter can be one of the following values: |
900 | { \ |
| 901 | * @arg TIM_IT_UPDATE: Update interrupt |
901 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
| 902 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
902 | } \ |
| 903 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
903 | } while(0) |
| 904 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
904 | |
| 905 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
905 | /** @brief Enable the specified TIM interrupt. |
| 906 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
906 | * @param __HANDLE__ specifies the TIM Handle. |
| 907 | * @retval None |
907 | * @param __INTERRUPT__ specifies the TIM interrupt source to enable. |
| 908 | */ |
908 | * This parameter can be one of the following values: |
| 909 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
909 | * @arg TIM_IT_UPDATE: Update interrupt |
| 910 | 910 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
|
| 911 | /** @brief Disable the specified TIM interrupt. |
911 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 912 | * @param __HANDLE__ specifies the TIM Handle. |
912 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 913 | * @param __INTERRUPT__ specifies the TIM interrupt source to disable. |
913 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 914 | * This parameter can be one of the following values: |
914 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 915 | * @arg TIM_IT_UPDATE: Update interrupt |
915 | * @retval None |
| 916 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
916 | */ |
| 917 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
917 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
| 918 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
918 | |
| 919 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
919 | /** @brief Disable the specified TIM interrupt. |
| 920 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
920 | * @param __HANDLE__ specifies the TIM Handle. |
| 921 | * @retval None |
921 | * @param __INTERRUPT__ specifies the TIM interrupt source to disable. |
| 922 | */ |
922 | * This parameter can be one of the following values: |
| 923 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
923 | * @arg TIM_IT_UPDATE: Update interrupt |
| 924 | 924 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
|
| 925 | /** @brief Enable the specified DMA request. |
925 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 926 | * @param __HANDLE__ specifies the TIM Handle. |
926 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 927 | * @param __DMA__ specifies the TIM DMA request to enable. |
927 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 928 | * This parameter can be one of the following values: |
928 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 929 | * @arg TIM_DMA_UPDATE: Update DMA request |
929 | * @retval None |
| 930 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
930 | */ |
| 931 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
931 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
| 932 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
932 | |
| 933 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
933 | /** @brief Enable the specified DMA request. |
| 934 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
934 | * @param __HANDLE__ specifies the TIM Handle. |
| 935 | * @retval None |
935 | * @param __DMA__ specifies the TIM DMA request to enable. |
| 936 | */ |
936 | * This parameter can be one of the following values: |
| 937 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
937 | * @arg TIM_DMA_UPDATE: Update DMA request |
| 938 | 938 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
|
| 939 | /** @brief Disable the specified DMA request. |
939 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
| 940 | * @param __HANDLE__ specifies the TIM Handle. |
940 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
| 941 | * @param __DMA__ specifies the TIM DMA request to disable. |
941 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
| 942 | * This parameter can be one of the following values: |
942 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
| 943 | * @arg TIM_DMA_UPDATE: Update DMA request |
943 | * @retval None |
| 944 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
944 | */ |
| 945 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
945 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
| 946 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
946 | |
| 947 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
947 | /** @brief Disable the specified DMA request. |
| 948 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
948 | * @param __HANDLE__ specifies the TIM Handle. |
| 949 | * @retval None |
949 | * @param __DMA__ specifies the TIM DMA request to disable. |
| 950 | */ |
950 | * This parameter can be one of the following values: |
| 951 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
951 | * @arg TIM_DMA_UPDATE: Update DMA request |
| 952 | 952 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
|
| 953 | /** @brief Check whether the specified TIM interrupt flag is set or not. |
953 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
| 954 | * @param __HANDLE__ specifies the TIM Handle. |
954 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
| 955 | * @param __FLAG__ specifies the TIM interrupt flag to check. |
955 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
| 956 | * This parameter can be one of the following values: |
956 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
| 957 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
957 | * @retval None |
| 958 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
958 | */ |
| 959 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
959 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
| 960 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
960 | |
| 961 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
961 | /** @brief Check whether the specified TIM interrupt flag is set or not. |
| 962 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
962 | * @param __HANDLE__ specifies the TIM Handle. |
| 963 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
963 | * @param __FLAG__ specifies the TIM interrupt flag to check. |
| 964 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
964 | * This parameter can be one of the following values: |
| 965 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
965 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
| 966 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
966 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
| 967 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
967 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
| 968 | */ |
968 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
| 969 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
969 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
| 970 | 970 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
|
| 971 | /** @brief Clear the specified TIM interrupt flag. |
971 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
| 972 | * @param __HANDLE__ specifies the TIM Handle. |
972 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
| 973 | * @param __FLAG__ specifies the TIM interrupt flag to clear. |
973 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
| 974 | * This parameter can be one of the following values: |
974 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
| 975 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
975 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 976 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
976 | */ |
| 977 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
977 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
| 978 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
978 | |
| 979 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
979 | /** @brief Clear the specified TIM interrupt flag. |
| 980 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
980 | * @param __HANDLE__ specifies the TIM Handle. |
| 981 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
981 | * @param __FLAG__ specifies the TIM interrupt flag to clear. |
| 982 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
982 | * This parameter can be one of the following values: |
| 983 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
983 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
| 984 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
984 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
| 985 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
985 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
| 986 | */ |
986 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
| 987 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
987 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
| 988 | 988 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
|
| 989 | /** |
989 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
| 990 | * @brief Check whether the specified TIM interrupt source is enabled or not. |
990 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
| 991 | * @param __HANDLE__ TIM handle |
991 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
| 992 | * @param __INTERRUPT__ specifies the TIM interrupt source to check. |
992 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
| 993 | * This parameter can be one of the following values: |
993 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 994 | * @arg TIM_IT_UPDATE: Update interrupt |
994 | */ |
| 995 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
995 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
| 996 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
996 | |
| 997 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
997 | /** |
| 998 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
998 | * @brief Check whether the specified TIM interrupt source is enabled or not. |
| 999 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
999 | * @param __HANDLE__ TIM handle |
| 1000 | * @retval The state of TIM_IT (SET or RESET). |
1000 | * @param __INTERRUPT__ specifies the TIM interrupt source to check. |
| 1001 | */ |
1001 | * This parameter can be one of the following values: |
| 1002 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ |
1002 | * @arg TIM_IT_UPDATE: Update interrupt |
| 1003 | == (__INTERRUPT__)) ? SET : RESET) |
1003 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
| 1004 | 1004 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
|
| 1005 | /** @brief Clear the TIM interrupt pending bits. |
1005 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 1006 | * @param __HANDLE__ TIM handle |
1006 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 1007 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
1007 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 1008 | * This parameter can be one of the following values: |
1008 | * @retval The state of TIM_IT (SET or RESET). |
| 1009 | * @arg TIM_IT_UPDATE: Update interrupt |
1009 | */ |
| 1010 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
1010 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ |
| 1011 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
1011 | == (__INTERRUPT__)) ? SET : RESET) |
| 1012 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
1012 | |
| 1013 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
1013 | /** @brief Clear the TIM interrupt pending bits. |
| 1014 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
1014 | * @param __HANDLE__ TIM handle |
| 1015 | * @retval None |
1015 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
| 1016 | */ |
1016 | * This parameter can be one of the following values: |
| 1017 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
1017 | * @arg TIM_IT_UPDATE: Update interrupt |
| 1018 | 1018 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
|
| 1019 | /** |
1019 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 1020 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
1020 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 1021 | * @param __HANDLE__ TIM handle. |
1021 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 1022 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
1022 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 1023 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode |
1023 | * @retval None |
| 1024 | * or Encoder mode. |
1024 | */ |
| 1025 | */ |
1025 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
| 1026 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
1026 | |
| 1027 | 1027 | /** |
|
| 1028 | /** |
1028 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
| 1029 | * @brief Set the TIM Prescaler on runtime. |
1029 | * @param __HANDLE__ TIM handle. |
| 1030 | * @param __HANDLE__ TIM handle. |
1030 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
| 1031 | * @param __PRESC__ specifies the Prescaler new value. |
1031 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode |
| 1032 | * @retval None |
1032 | * or Encoder mode. |
| 1033 | */ |
1033 | */ |
| 1034 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
1034 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
| 1035 | 1035 | ||
| 1036 | /** |
1036 | /** |
| 1037 | * @brief Set the TIM Counter Register value on runtime. |
1037 | * @brief Set the TIM Prescaler on runtime. |
| 1038 | * @param __HANDLE__ TIM handle. |
1038 | * @param __HANDLE__ TIM handle. |
| 1039 | * @param __COUNTER__ specifies the Counter register new value. |
1039 | * @param __PRESC__ specifies the Prescaler new value. |
| 1040 | * @retval None |
1040 | * @retval None |
| 1041 | */ |
1041 | */ |
| 1042 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
1042 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
| 1043 | 1043 | ||
| 1044 | /** |
1044 | /** |
| 1045 | * @brief Get the TIM Counter Register value on runtime. |
1045 | * @brief Set the TIM Counter Register value on runtime. |
| 1046 | * @param __HANDLE__ TIM handle. |
1046 | * @param __HANDLE__ TIM handle. |
| 1047 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
1047 | * @param __COUNTER__ specifies the Counter register new value. |
| 1048 | */ |
1048 | * @retval None |
| 1049 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
1049 | */ |
| 1050 | 1050 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
|
| 1051 | /** |
1051 | |
| 1052 | * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. |
1052 | /** |
| 1053 | * @param __HANDLE__ TIM handle. |
1053 | * @brief Get the TIM Counter Register value on runtime. |
| 1054 | * @param __AUTORELOAD__ specifies the Counter register new value. |
1054 | * @param __HANDLE__ TIM handle. |
| 1055 | * @retval None |
1055 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
| 1056 | */ |
1056 | */ |
| 1057 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
1057 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
| 1058 | do{ \ |
1058 | |
| 1059 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
1059 | /** |
| 1060 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
1060 | * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. |
| 1061 | } while(0) |
1061 | * @param __HANDLE__ TIM handle. |
| 1062 | 1062 | * @param __AUTORELOAD__ specifies the Counter register new value. |
|
| 1063 | /** |
1063 | * @retval None |
| 1064 | * @brief Get the TIM Autoreload Register value on runtime. |
1064 | */ |
| 1065 | * @param __HANDLE__ TIM handle. |
1065 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
| 1066 | * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
1066 | do{ \ |
| 1067 | */ |
1067 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
| 1068 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
1068 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
| 1069 | 1069 | } while(0) |
|
| 1070 | /** |
1070 | |
| 1071 | * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. |
1071 | /** |
| 1072 | * @param __HANDLE__ TIM handle. |
1072 | * @brief Get the TIM Autoreload Register value on runtime. |
| 1073 | * @param __CKD__ specifies the clock division value. |
1073 | * @param __HANDLE__ TIM handle. |
| 1074 | * This parameter can be one of the following value: |
1074 | * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
| 1075 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
1075 | */ |
| 1076 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
1076 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
| 1077 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
1077 | |
| 1078 | * @retval None |
1078 | /** |
| 1079 | */ |
1079 | * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. |
| 1080 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
1080 | * @param __HANDLE__ TIM handle. |
| 1081 | do{ \ |
1081 | * @param __CKD__ specifies the clock division value. |
| 1082 | (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ |
1082 | * This parameter can be one of the following value: |
| 1083 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
1083 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
| 1084 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
1084 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
| 1085 | } while(0) |
1085 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
| 1086 | 1086 | * @retval None |
|
| 1087 | /** |
1087 | */ |
| 1088 | * @brief Get the TIM Clock Division value on runtime. |
1088 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
| 1089 | * @param __HANDLE__ TIM handle. |
1089 | do{ \ |
| 1090 | * @retval The clock division can be one of the following values: |
1090 | (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ |
| 1091 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
1091 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
| 1092 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
1092 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
| 1093 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
1093 | } while(0) |
| 1094 | */ |
1094 | |
| 1095 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
1095 | /** |
| 1096 | 1096 | * @brief Get the TIM Clock Division value on runtime. |
|
| 1097 | /** |
1097 | * @param __HANDLE__ TIM handle. |
| 1098 | * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() |
1098 | * @retval The clock division can be one of the following values: |
| 1099 | * function. |
1099 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
| 1100 | * @param __HANDLE__ TIM handle. |
1100 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
| 1101 | * @param __CHANNEL__ TIM Channels to be configured. |
1101 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
| 1102 | * This parameter can be one of the following values: |
1102 | */ |
| 1103 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1103 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
| 1104 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1104 | |
| 1105 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1105 | /** |
| 1106 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1106 | * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() |
| 1107 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
1107 | * function. |
| 1108 | * This parameter can be one of the following values: |
1108 | * @param __HANDLE__ TIM handle. |
| 1109 | * @arg TIM_ICPSC_DIV1: no prescaler |
1109 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1110 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
1110 | * This parameter can be one of the following values: |
| 1111 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
1111 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1112 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
1112 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1113 | * @retval None |
1113 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1114 | */ |
1114 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1115 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
1115 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
| 1116 | do{ \ |
1116 | * This parameter can be one of the following values: |
| 1117 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
1117 | * @arg TIM_ICPSC_DIV1: no prescaler |
| 1118 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
1118 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
| 1119 | } while(0) |
1119 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
| 1120 | 1120 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
|
| 1121 | /** |
1121 | * @retval None |
| 1122 | * @brief Get the TIM Input Capture prescaler on runtime. |
1122 | */ |
| 1123 | * @param __HANDLE__ TIM handle. |
1123 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
| 1124 | * @param __CHANNEL__ TIM Channels to be configured. |
1124 | do{ \ |
| 1125 | * This parameter can be one of the following values: |
1125 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
| 1126 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
1126 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
| 1127 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
1127 | } while(0) |
| 1128 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
1128 | |
| 1129 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
1129 | /** |
| 1130 | * @retval The input capture prescaler can be one of the following values: |
1130 | * @brief Get the TIM Input Capture prescaler on runtime. |
| 1131 | * @arg TIM_ICPSC_DIV1: no prescaler |
1131 | * @param __HANDLE__ TIM handle. |
| 1132 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
1132 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1133 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
1133 | * This parameter can be one of the following values: |
| 1134 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
1134 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
| 1135 | */ |
1135 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
| 1136 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
1136 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
| 1137 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
1137 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
| 1138 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ |
1138 | * @retval The input capture prescaler can be one of the following values: |
| 1139 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
1139 | * @arg TIM_ICPSC_DIV1: no prescaler |
| 1140 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
1140 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
| 1141 | 1141 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
|
| 1142 | /** |
1142 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
| 1143 | * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. |
1143 | */ |
| 1144 | * @param __HANDLE__ TIM handle. |
1144 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
| 1145 | * @param __CHANNEL__ TIM Channels to be configured. |
1145 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
| 1146 | * This parameter can be one of the following values: |
1146 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ |
| 1147 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1147 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
| 1148 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1148 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
| 1149 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1149 | |
| 1150 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1150 | /** |
| 1151 | * @param __COMPARE__ specifies the Capture Compare register new value. |
1151 | * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. |
| 1152 | * @retval None |
1152 | * @param __HANDLE__ TIM handle. |
| 1153 | */ |
1153 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1154 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
1154 | * This parameter can be one of the following values: |
| 1155 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
1155 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1156 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
1156 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1157 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
1157 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1158 | ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) |
1158 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1159 | 1159 | * @param __COMPARE__ specifies the Capture Compare register new value. |
|
| 1160 | /** |
1160 | * @retval None |
| 1161 | * @brief Get the TIM Capture Compare Register value on runtime. |
1161 | */ |
| 1162 | * @param __HANDLE__ TIM handle. |
1162 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
| 1163 | * @param __CHANNEL__ TIM Channel associated with the capture compare register |
1163 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
| 1164 | * This parameter can be one of the following values: |
1164 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
| 1165 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
1165 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
| 1166 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
1166 | ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) |
| 1167 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
1167 | |
| 1168 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
1168 | /** |
| 1169 | * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) |
1169 | * @brief Get the TIM Capture Compare Register value on runtime. |
| 1170 | */ |
1170 | * @param __HANDLE__ TIM handle. |
| 1171 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
1171 | * @param __CHANNEL__ TIM Channel associated with the capture compare register |
| 1172 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
1172 | * This parameter can be one of the following values: |
| 1173 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
1173 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
| 1174 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
1174 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
| 1175 | ((__HANDLE__)->Instance->CCR4)) |
1175 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
| 1176 | 1176 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
|
| 1177 | /** |
1177 | * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) |
| 1178 | * @brief Set the TIM Output compare preload. |
1178 | */ |
| 1179 | * @param __HANDLE__ TIM handle. |
1179 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
| 1180 | * @param __CHANNEL__ TIM Channels to be configured. |
1180 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
| 1181 | * This parameter can be one of the following values: |
1181 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
| 1182 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1182 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
| 1183 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1183 | ((__HANDLE__)->Instance->CCR4)) |
| 1184 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1184 | |
| 1185 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1185 | /** |
| 1186 | * @retval None |
1186 | * @brief Set the TIM Output compare preload. |
| 1187 | */ |
1187 | * @param __HANDLE__ TIM handle. |
| 1188 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
1188 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1189 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
1189 | * This parameter can be one of the following values: |
| 1190 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
1190 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1191 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
1191 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1192 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) |
1192 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1193 | 1193 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
|
| 1194 | /** |
1194 | * @retval None |
| 1195 | * @brief Reset the TIM Output compare preload. |
1195 | */ |
| 1196 | * @param __HANDLE__ TIM handle. |
1196 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
| 1197 | * @param __CHANNEL__ TIM Channels to be configured. |
1197 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
| 1198 | * This parameter can be one of the following values: |
1198 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
| 1199 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1199 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
| 1200 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1200 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) |
| 1201 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1201 | |
| 1202 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1202 | /** |
| 1203 | * @retval None |
1203 | * @brief Reset the TIM Output compare preload. |
| 1204 | */ |
1204 | * @param __HANDLE__ TIM handle. |
| 1205 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
1205 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1206 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ |
1206 | * This parameter can be one of the following values: |
| 1207 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ |
1207 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1208 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ |
1208 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1209 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) |
1209 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1210 | 1210 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
|
| 1211 | /** |
1211 | * @retval None |
| 1212 | * @brief Enable fast mode for a given channel. |
1212 | */ |
| 1213 | * @param __HANDLE__ TIM handle. |
1213 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
| 1214 | * @param __CHANNEL__ TIM Channels to be configured. |
1214 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ |
| 1215 | * This parameter can be one of the following values: |
1215 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ |
| 1216 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1216 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ |
| 1217 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1217 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) |
| 1218 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1218 | |
| 1219 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1219 | /** |
| 1220 | * @note When fast mode is enabled an active edge on the trigger input acts |
1220 | * @brief Enable fast mode for a given channel. |
| 1221 | * like a compare match on CCx output. Delay to sample the trigger |
1221 | * @param __HANDLE__ TIM handle. |
| 1222 | * input and to activate CCx output is reduced to 3 clock cycles. |
1222 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1223 | * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. |
1223 | * This parameter can be one of the following values: |
| 1224 | * @retval None |
1224 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1225 | */ |
1225 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1226 | #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ |
1226 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1227 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ |
1227 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1228 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ |
1228 | * @note When fast mode is enabled an active edge on the trigger input acts |
| 1229 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ |
1229 | * like a compare match on CCx output. Delay to sample the trigger |
| 1230 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) |
1230 | * input and to activate CCx output is reduced to 3 clock cycles. |
| 1231 | 1231 | * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. |
|
| 1232 | /** |
1232 | * @retval None |
| 1233 | * @brief Disable fast mode for a given channel. |
1233 | */ |
| 1234 | * @param __HANDLE__ TIM handle. |
1234 | #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ |
| 1235 | * @param __CHANNEL__ TIM Channels to be configured. |
1235 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ |
| 1236 | * This parameter can be one of the following values: |
1236 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ |
| 1237 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1237 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ |
| 1238 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1238 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) |
| 1239 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1239 | |
| 1240 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1240 | /** |
| 1241 | * @note When fast mode is disabled CCx output behaves normally depending |
1241 | * @brief Disable fast mode for a given channel. |
| 1242 | * on counter and CCRx values even when the trigger is ON. The minimum |
1242 | * @param __HANDLE__ TIM handle. |
| 1243 | * delay to activate CCx output when an active edge occurs on the |
1243 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1244 | * trigger input is 5 clock cycles. |
1244 | * This parameter can be one of the following values: |
| 1245 | * @retval None |
1245 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1246 | */ |
1246 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1247 | #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ |
1247 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1248 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ |
1248 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1249 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ |
1249 | * @note When fast mode is disabled CCx output behaves normally depending |
| 1250 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ |
1250 | * on counter and CCRx values even when the trigger is ON. The minimum |
| 1251 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) |
1251 | * delay to activate CCx output when an active edge occurs on the |
| 1252 | 1252 | * trigger input is 5 clock cycles. |
|
| 1253 | /** |
1253 | * @retval None |
| 1254 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. |
1254 | */ |
| 1255 | * @param __HANDLE__ TIM handle. |
1255 | #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ |
| 1256 | * @note When the URS bit of the TIMx_CR1 register is set, only counter |
1256 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ |
| 1257 | * overflow/underflow generates an update interrupt or DMA request (if |
1257 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ |
| 1258 | * enabled) |
1258 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ |
| 1259 | * @retval None |
1259 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) |
| 1260 | */ |
1260 | |
| 1261 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) |
1261 | /** |
| 1262 | 1262 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. |
|
| 1263 | /** |
1263 | * @param __HANDLE__ TIM handle. |
| 1264 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. |
1264 | * @note When the URS bit of the TIMx_CR1 register is set, only counter |
| 1265 | * @param __HANDLE__ TIM handle. |
1265 | * overflow/underflow generates an update interrupt or DMA request (if |
| 1266 | * @note When the URS bit of the TIMx_CR1 register is reset, any of the |
1266 | * enabled) |
| 1267 | * following events generate an update interrupt or DMA request (if |
1267 | * @retval None |
| 1268 | * enabled): |
1268 | */ |
| 1269 | * _ Counter overflow underflow |
1269 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) |
| 1270 | * _ Setting the UG bit |
1270 | |
| 1271 | * _ Update generation through the slave mode controller |
1271 | /** |
| 1272 | * @retval None |
1272 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. |
| 1273 | */ |
1273 | * @param __HANDLE__ TIM handle. |
| 1274 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) |
1274 | * @note When the URS bit of the TIMx_CR1 register is reset, any of the |
| 1275 | 1275 | * following events generate an update interrupt or DMA request (if |
|
| 1276 | /** |
1276 | * enabled): |
| 1277 | * @brief Set the TIM Capture x input polarity on runtime. |
1277 | * _ Counter overflow underflow |
| 1278 | * @param __HANDLE__ TIM handle. |
1278 | * _ Setting the UG bit |
| 1279 | * @param __CHANNEL__ TIM Channels to be configured. |
1279 | * _ Update generation through the slave mode controller |
| 1280 | * This parameter can be one of the following values: |
1280 | * @retval None |
| 1281 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1281 | */ |
| 1282 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1282 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) |
| 1283 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1283 | |
| 1284 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
1284 | /** |
| 1285 | * @param __POLARITY__ Polarity for TIx source |
1285 | * @brief Set the TIM Capture x input polarity on runtime. |
| 1286 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
1286 | * @param __HANDLE__ TIM handle. |
| 1287 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
1287 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1288 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
1288 | * This parameter can be one of the following values: |
| 1289 | * @retval None |
1289 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1290 | */ |
1290 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1291 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
1291 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1292 | do{ \ |
1292 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1293 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
1293 | * @param __POLARITY__ Polarity for TIx source |
| 1294 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
1294 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
| 1295 | }while(0) |
1295 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
| 1296 | 1296 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
|
| 1297 | /** |
1297 | * @retval None |
| 1298 | * @} |
1298 | */ |
| 1299 | */ |
1299 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
| 1300 | /* End of exported macros ----------------------------------------------------*/ |
1300 | do{ \ |
| 1301 | 1301 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
|
| 1302 | /* Private constants ---------------------------------------------------------*/ |
1302 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
| 1303 | /** @defgroup TIM_Private_Constants TIM Private Constants |
1303 | }while(0) |
| 1304 | * @{ |
1304 | |
| 1305 | */ |
1305 | /** @brief Select the Capture/compare DMA request source. |
| 1306 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
1306 | * @param __HANDLE__ specifies the TIM Handle. |
| 1307 | channels have been disabled */ |
1307 | * @param __CCDMA__ specifies Capture/compare DMA request source |
| 1308 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
1308 | * This parameter can be one of the following values: |
| 1309 | /** |
1309 | * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event |
| 1310 | * @} |
1310 | * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event |
| 1311 | */ |
1311 | * @retval None |
| 1312 | /* End of private constants --------------------------------------------------*/ |
1312 | */ |
| 1313 | 1313 | #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ |
|
| 1314 | /* Private macros ------------------------------------------------------------*/ |
1314 | MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) |
| 1315 | /** @defgroup TIM_Private_Macros TIM Private Macros |
1315 | |
| 1316 | * @{ |
1316 | /** |
| 1317 | */ |
1317 | * @} |
| 1318 | #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ |
1318 | */ |
| 1319 | ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ |
1319 | /* End of exported macros ----------------------------------------------------*/ |
| 1320 | ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) |
1320 | |
| 1321 | 1321 | /* Private constants ---------------------------------------------------------*/ |
|
| 1322 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
1322 | /** @defgroup TIM_Private_Constants TIM Private Constants |
| 1323 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
1323 | * @{ |
| 1324 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
1324 | */ |
| 1325 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
1325 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
| 1326 | ((__BASE__) == TIM_DMABASE_SR) || \ |
1326 | channels have been disabled */ |
| 1327 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
1327 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
| 1328 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
1328 | /** |
| 1329 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
1329 | * @} |
| 1330 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
1330 | */ |
| 1331 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
1331 | /* End of private constants --------------------------------------------------*/ |
| 1332 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
1332 | |
| 1333 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
1333 | /* Private macros ------------------------------------------------------------*/ |
| 1334 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
1334 | /** @defgroup TIM_Private_Macros TIM Private Macros |
| 1335 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
1335 | * @{ |
| 1336 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
1336 | */ |
| 1337 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
1337 | #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ |
| 1338 | ((__BASE__) == TIM_DMABASE_OR)) |
1338 | ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ |
| 1339 | 1339 | ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) |
|
| 1340 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
1340 | |
| 1341 | 1341 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
|
| 1342 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
1342 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
| 1343 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
1343 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
| 1344 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
1344 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
| 1345 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
1345 | ((__BASE__) == TIM_DMABASE_SR) || \ |
| 1346 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
1346 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
| 1347 | 1347 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
|
| 1348 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
1348 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
| 1349 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
1349 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
| 1350 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
1350 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
| 1351 | 1351 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
|
| 1352 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
1352 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
| 1353 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
1353 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
| 1354 | 1354 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
|
| 1355 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
1355 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
| 1356 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
1356 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
| 1357 | 1357 | ((__BASE__) == TIM_DMABASE_OR)) |
|
| 1358 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
1358 | |
| 1359 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
1359 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
| 1360 | 1360 | ||
| 1361 | #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ |
1361 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
| 1362 | ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) |
1362 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
| 1363 | 1363 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
|
| 1364 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
1364 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
| 1365 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
1365 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
| 1366 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
1366 | |
| 1367 | 1367 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
|
| 1368 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
1368 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
| 1369 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
1369 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
| 1370 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
1370 | |
| 1371 | 1371 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
|
| 1372 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
1372 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
| 1373 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
1373 | |
| 1374 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
1374 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
| 1375 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
1375 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
| 1376 | 1376 | ||
| 1377 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
1377 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
| 1378 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
1378 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
| 1379 | 1379 | ||
| 1380 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
1380 | #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ |
| 1381 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
1381 | ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) |
| 1382 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
1382 | |
| 1383 | 1383 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
|
| 1384 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
1384 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
| 1385 | 1385 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
|
| 1386 | #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
1386 | |
| 1387 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
1387 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
| 1388 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
1388 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
| 1389 | ((__CHANNEL__) == TIM_CHANNEL_4) || \ |
1389 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
| 1390 | ((__CHANNEL__) == TIM_CHANNEL_ALL)) |
1390 | |
| 1391 | 1391 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
|
| 1392 | #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
1392 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
| 1393 | ((__CHANNEL__) == TIM_CHANNEL_2)) |
1393 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
| 1394 | 1394 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
|
| 1395 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
1395 | |
| 1396 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
1396 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
| 1397 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
1397 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
| 1398 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
1398 | |
| 1399 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
1399 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
| 1400 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
1400 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
| 1401 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
1401 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
| 1402 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
1402 | |
| 1403 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
1403 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
| 1404 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
1404 | |
| 1405 | 1405 | #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
|
| 1406 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
1406 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
| 1407 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
1407 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
| 1408 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
1408 | ((__CHANNEL__) == TIM_CHANNEL_4) || \ |
| 1409 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
1409 | ((__CHANNEL__) == TIM_CHANNEL_ALL)) |
| 1410 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
1410 | |
| 1411 | 1411 | #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
|
| 1412 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
1412 | ((__CHANNEL__) == TIM_CHANNEL_2)) |
| 1413 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
1413 | |
| 1414 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
1414 | #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ |
| 1415 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
1415 | ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) |
| 1416 | 1416 | ||
| 1417 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
1417 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
| 1418 | 1418 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ |
|
| 1419 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
1419 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
| 1420 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
1420 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
| 1421 | 1421 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
|
| 1422 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
1422 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
| 1423 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
1423 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
| 1424 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
1424 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
| 1425 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
1425 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
| 1426 | 1426 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) |
|
| 1427 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
1427 | |
| 1428 | 1428 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
|
| 1429 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
1429 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
| 1430 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
1430 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
| 1431 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
1431 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
| 1432 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
1432 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
| 1433 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
1433 | |
| 1434 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
1434 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
| 1435 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
1435 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
| 1436 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
1436 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
| 1437 | 1437 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
|
| 1438 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
1438 | |
| 1439 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
1439 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1440 | 1440 | ||
| 1441 | #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ |
1441 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
| 1442 | ((__MODE__) == TIM_SLAVEMODE_RESET) || \ |
1442 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
| 1443 | ((__MODE__) == TIM_SLAVEMODE_GATED) || \ |
1443 | |
| 1444 | ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ |
1444 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
| 1445 | ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) |
1445 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
| 1446 | 1446 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
|
| 1447 | #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ |
1447 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
| 1448 | ((__MODE__) == TIM_OCMODE_PWM2)) |
1448 | |
| 1449 | 1449 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
|
| 1450 | #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ |
1450 | |
| 1451 | ((__MODE__) == TIM_OCMODE_ACTIVE) || \ |
1451 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
| 1452 | ((__MODE__) == TIM_OCMODE_INACTIVE) || \ |
1452 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
| 1453 | ((__MODE__) == TIM_OCMODE_TOGGLE) || \ |
1453 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
| 1454 | ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ |
1454 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
| 1455 | ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) |
1455 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
| 1456 | 1456 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
|
| 1457 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
1457 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
| 1458 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
1458 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
| 1459 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
1459 | |
| 1460 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
1460 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
| 1461 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
1461 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
| 1462 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
1462 | |
| 1463 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
1463 | #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ |
| 1464 | ((__SELECTION__) == TIM_TS_ETRF)) |
1464 | ((__MODE__) == TIM_SLAVEMODE_RESET) || \ |
| 1465 | 1465 | ((__MODE__) == TIM_SLAVEMODE_GATED) || \ |
|
| 1466 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
1466 | ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ |
| 1467 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
1467 | ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) |
| 1468 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
1468 | |
| 1469 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
1469 | #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ |
| 1470 | ((__SELECTION__) == TIM_TS_NONE)) |
1470 | ((__MODE__) == TIM_OCMODE_PWM2)) |
| 1471 | 1471 | ||
| 1472 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
1472 | #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ |
| 1473 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
1473 | ((__MODE__) == TIM_OCMODE_ACTIVE) || \ |
| 1474 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
1474 | ((__MODE__) == TIM_OCMODE_INACTIVE) || \ |
| 1475 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
1475 | ((__MODE__) == TIM_OCMODE_TOGGLE) || \ |
| 1476 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
1476 | ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ |
| 1477 | 1477 | ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) |
|
| 1478 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
1478 | |
| 1479 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
1479 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
| 1480 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
1480 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
| 1481 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
1481 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
| 1482 | 1482 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
|
| 1483 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
1483 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
| 1484 | 1484 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
|
| 1485 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
1485 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
| 1486 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
1486 | ((__SELECTION__) == TIM_TS_ETRF)) |
| 1487 | 1487 | ||
| 1488 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
1488 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
| 1489 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
1489 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
| 1490 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
1490 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
| 1491 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
1491 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
| 1492 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
1492 | ((__SELECTION__) == TIM_TS_NONE)) |
| 1493 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
1493 | |
| 1494 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
1494 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
| 1495 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
1495 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
| 1496 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
1496 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
| 1497 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
1497 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
| 1498 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
1498 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
| 1499 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
1499 | |
| 1500 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
1500 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
| 1501 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
1501 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
| 1502 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
1502 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
| 1503 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
1503 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
| 1504 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
1504 | |
| 1505 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
1505 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1506 | 1506 | ||
| 1507 | #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) |
1507 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
| 1508 | 1508 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
|
| 1509 | #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
1509 | |
| 1510 | 1510 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
|
| 1511 | #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) |
1511 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
| 1512 | 1512 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
|
| 1513 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
1513 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
| 1514 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
1514 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
| 1515 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
1515 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
| 1516 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
1516 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
| 1517 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) |
1517 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
| 1518 | 1518 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
|
| 1519 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
1519 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
| 1520 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
1520 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
| 1521 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
1521 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
| 1522 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
1522 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
| 1523 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
1523 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
| 1524 | 1524 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
|
| 1525 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
1525 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
| 1526 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
1526 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
| 1527 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
1527 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
| 1528 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
1528 | |
| 1529 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) |
1529 | #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) |
| 1530 | 1530 | ||
| 1531 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
1531 | #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1532 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
1532 | |
| 1533 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
1533 | #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) |
| 1534 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
1534 | |
| 1535 | ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
1535 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
| 1536 | 1536 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
|
| 1537 | #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ |
1537 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
| 1538 | (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ |
1538 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
| 1539 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ |
1539 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) |
| 1540 | ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ |
1540 | |
| 1541 | (__HANDLE__)->ChannelState[3]) |
1541 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
| 1542 | 1542 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
|
| 1543 | #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ |
1543 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
| 1544 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ |
1544 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
| 1545 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ |
1545 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
| 1546 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ |
1546 | |
| 1547 | ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) |
1547 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
| 1548 | 1548 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
|
| 1549 | #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ |
1549 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
| 1550 | (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ |
1550 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
| 1551 | (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ |
1551 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) |
| 1552 | (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ |
1552 | |
| 1553 | (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ |
1553 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
| 1554 | } while(0) |
1554 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
| 1555 | 1555 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
|
| 1556 | /** |
1556 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
| 1557 | * @} |
1557 | ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
| 1558 | */ |
1558 | |
| 1559 | /* End of private macros -----------------------------------------------------*/ |
1559 | #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ |
| 1560 | 1560 | (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ |
|
| 1561 | /* Include TIM HAL Extended module */ |
1561 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ |
| 1562 | #include "stm32l1xx_hal_tim_ex.h" |
1562 | ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ |
| 1563 | 1563 | (__HANDLE__)->ChannelState[3]) |
|
| 1564 | /* Exported functions --------------------------------------------------------*/ |
1564 | |
| 1565 | /** @addtogroup TIM_Exported_Functions TIM Exported Functions |
1565 | #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ |
| 1566 | * @{ |
1566 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ |
| 1567 | */ |
1567 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ |
| 1568 | 1568 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ |
|
| 1569 | /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions |
1569 | ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) |
| 1570 | * @brief Time Base functions |
1570 | |
| 1571 | * @{ |
1571 | #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ |
| 1572 | */ |
1572 | (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ |
| 1573 | /* Time Base functions ********************************************************/ |
1573 | (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ |
| 1574 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
1574 | (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ |
| 1575 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
1575 | (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ |
| 1576 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
1576 | } while(0) |
| 1577 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
1577 | |
| 1578 | /* Blocking mode: Polling */ |
1578 | /** |
| 1579 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
1579 | * @} |
| 1580 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
1580 | */ |
| 1581 | /* Non-Blocking mode: Interrupt */ |
1581 | /* End of private macros -----------------------------------------------------*/ |
| 1582 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
1582 | |
| 1583 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
1583 | /* Include TIM HAL Extended module */ |
| 1584 | /* Non-Blocking mode: DMA */ |
1584 | #include "stm32l1xx_hal_tim_ex.h" |
| 1585 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
1585 | |
| 1586 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
1586 | /* Exported functions --------------------------------------------------------*/ |
| 1587 | /** |
1587 | /** @addtogroup TIM_Exported_Functions TIM Exported Functions |
| 1588 | * @} |
1588 | * @{ |
| 1589 | */ |
1589 | */ |
| 1590 | 1590 | ||
| 1591 | /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions |
1591 | /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions |
| 1592 | * @brief TIM Output Compare functions |
1592 | * @brief Time Base functions |
| 1593 | * @{ |
1593 | * @{ |
| 1594 | */ |
1594 | */ |
| 1595 | /* Timer Output Compare functions *********************************************/ |
1595 | /* Time Base functions ********************************************************/ |
| 1596 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
1596 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
| 1597 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
1597 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
| 1598 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
1598 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
| 1599 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
1599 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
| 1600 | /* Blocking mode: Polling */ |
1600 | /* Blocking mode: Polling */ |
| 1601 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
1601 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
| 1602 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
1602 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
| 1603 | /* Non-Blocking mode: Interrupt */ |
1603 | /* Non-Blocking mode: Interrupt */ |
| 1604 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1604 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
| 1605 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1605 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
| 1606 | /* Non-Blocking mode: DMA */ |
1606 | /* Non-Blocking mode: DMA */ |
| 1607 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
1607 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); |
| 1608 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
1608 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
| 1609 | /** |
1609 | /** |
| 1610 | * @} |
1610 | * @} |
| 1611 | */ |
1611 | */ |
| 1612 | 1612 | ||
| 1613 | /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions |
1613 | /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions |
| 1614 | * @brief TIM PWM functions |
1614 | * @brief TIM Output Compare functions |
| 1615 | * @{ |
1615 | * @{ |
| 1616 | */ |
1616 | */ |
| 1617 | /* Timer PWM functions ********************************************************/ |
1617 | /* Timer Output Compare functions *********************************************/ |
| 1618 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
1618 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
| 1619 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
1619 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
| 1620 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
1620 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
| 1621 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
1621 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
| 1622 | /* Blocking mode: Polling */ |
1622 | /* Blocking mode: Polling */ |
| 1623 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
1623 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1624 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
1624 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1625 | /* Non-Blocking mode: Interrupt */ |
1625 | /* Non-Blocking mode: Interrupt */ |
| 1626 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1626 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1627 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1627 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1628 | /* Non-Blocking mode: DMA */ |
1628 | /* Non-Blocking mode: DMA */ |
| 1629 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
1629 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, |
| 1630 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
1630 | uint16_t Length); |
| 1631 | /** |
1631 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1632 | * @} |
1632 | /** |
| 1633 | */ |
1633 | * @} |
| 1634 | 1634 | */ |
|
| 1635 | /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions |
1635 | |
| 1636 | * @brief TIM Input Capture functions |
1636 | /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions |
| 1637 | * @{ |
1637 | * @brief TIM PWM functions |
| 1638 | */ |
1638 | * @{ |
| 1639 | /* Timer Input Capture functions **********************************************/ |
1639 | */ |
| 1640 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
1640 | /* Timer PWM functions ********************************************************/ |
| 1641 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
1641 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
| 1642 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
1642 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
| 1643 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
1643 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
| 1644 | /* Blocking mode: Polling */ |
1644 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
| 1645 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
1645 | /* Blocking mode: Polling */ |
| 1646 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
1646 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1647 | /* Non-Blocking mode: Interrupt */ |
1647 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1648 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1648 | /* Non-Blocking mode: Interrupt */ |
| 1649 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1649 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1650 | /* Non-Blocking mode: DMA */ |
1650 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1651 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
1651 | /* Non-Blocking mode: DMA */ |
| 1652 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
1652 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, |
| 1653 | /** |
1653 | uint16_t Length); |
| 1654 | * @} |
1654 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1655 | */ |
1655 | /** |
| 1656 | 1656 | * @} |
|
| 1657 | /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions |
1657 | */ |
| 1658 | * @brief TIM One Pulse functions |
1658 | |
| 1659 | * @{ |
1659 | /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions |
| 1660 | */ |
1660 | * @brief TIM Input Capture functions |
| 1661 | /* Timer One Pulse functions **************************************************/ |
1661 | * @{ |
| 1662 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
1662 | */ |
| 1663 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
1663 | /* Timer Input Capture functions **********************************************/ |
| 1664 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
1664 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
| 1665 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
1665 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
| 1666 | /* Blocking mode: Polling */ |
1666 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
| 1667 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
1667 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
| 1668 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
1668 | /* Blocking mode: Polling */ |
| 1669 | /* Non-Blocking mode: Interrupt */ |
1669 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1670 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
1670 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1671 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
1671 | /* Non-Blocking mode: Interrupt */ |
| 1672 | /** |
1672 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1673 | * @} |
1673 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1674 | */ |
1674 | /* Non-Blocking mode: DMA */ |
| 1675 | 1675 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
|
| 1676 | /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions |
1676 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1677 | * @brief TIM Encoder functions |
1677 | /** |
| 1678 | * @{ |
1678 | * @} |
| 1679 | */ |
1679 | */ |
| 1680 | /* Timer Encoder functions ****************************************************/ |
1680 | |
| 1681 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); |
1681 | /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions |
| 1682 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
1682 | * @brief TIM One Pulse functions |
| 1683 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
1683 | * @{ |
| 1684 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
1684 | */ |
| 1685 | /* Blocking mode: Polling */ |
1685 | /* Timer One Pulse functions **************************************************/ |
| 1686 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
1686 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
| 1687 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
1687 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
| 1688 | /* Non-Blocking mode: Interrupt */ |
1688 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
| 1689 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1689 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
| 1690 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
1690 | /* Blocking mode: Polling */ |
| 1691 | /* Non-Blocking mode: DMA */ |
1691 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1692 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, |
1692 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1693 | uint32_t *pData2, uint16_t Length); |
1693 | /* Non-Blocking mode: Interrupt */ |
| 1694 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
1694 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1695 | /** |
1695 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1696 | * @} |
1696 | /** |
| 1697 | */ |
1697 | * @} |
| 1698 | 1698 | */ |
|
| 1699 | /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management |
1699 | |
| 1700 | * @brief IRQ handler management |
1700 | /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions |
| 1701 | * @{ |
1701 | * @brief TIM Encoder functions |
| 1702 | */ |
1702 | * @{ |
| 1703 | /* Interrupt Handler functions ***********************************************/ |
1703 | */ |
| 1704 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
1704 | /* Timer Encoder functions ****************************************************/ |
| 1705 | /** |
1705 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); |
| 1706 | * @} |
1706 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
| 1707 | */ |
1707 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
| 1708 | 1708 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
|
| 1709 | /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions |
1709 | /* Blocking mode: Polling */ |
| 1710 | * @brief Peripheral Control functions |
1710 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1711 | * @{ |
1711 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1712 | */ |
1712 | /* Non-Blocking mode: Interrupt */ |
| 1713 | /* Control functions *********************************************************/ |
1713 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1714 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); |
1714 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1715 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); |
1715 | /* Non-Blocking mode: DMA */ |
| 1716 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); |
1716 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, |
| 1717 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, |
1717 | uint32_t *pData2, uint16_t Length); |
| 1718 | uint32_t OutputChannel, uint32_t InputChannel); |
1718 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1719 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, |
1719 | /** |
| 1720 | uint32_t Channel); |
1720 | * @} |
| 1721 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); |
1721 | */ |
| 1722 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
1722 | |
| 1723 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); |
1723 | /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management |
| 1724 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); |
1724 | * @brief IRQ handler management |
| 1725 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
1725 | * @{ |
| 1726 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
1726 | */ |
| 1727 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
1727 | /* Interrupt Handler functions ***********************************************/ |
| 1728 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, |
1728 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
| 1729 | uint32_t BurstLength, uint32_t DataLength); |
1729 | /** |
| 1730 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
1730 | * @} |
| 1731 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
1731 | */ |
| 1732 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
1732 | |
| 1733 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
1733 | /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions |
| 1734 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, |
1734 | * @brief Peripheral Control functions |
| 1735 | uint32_t BurstLength, uint32_t DataLength); |
1735 | * @{ |
| 1736 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
1736 | */ |
| 1737 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
1737 | /* Control functions *********************************************************/ |
| 1738 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
1738 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, |
| 1739 | /** |
1739 | uint32_t Channel); |
| 1740 | * @} |
1740 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, |
| 1741 | */ |
1741 | uint32_t Channel); |
| 1742 | 1742 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, |
|
| 1743 | /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions |
1743 | uint32_t Channel); |
| 1744 | * @brief TIM Callbacks functions |
1744 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, |
| 1745 | * @{ |
1745 | uint32_t OutputChannel, uint32_t InputChannel); |
| 1746 | */ |
1746 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, |
| 1747 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
1747 | const TIM_ClearInputConfigTypeDef *sClearInputConfig, |
| 1748 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
1748 | uint32_t Channel); |
| 1749 | void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); |
1749 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); |
| 1750 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
1750 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
| 1751 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
1751 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); |
| 1752 | void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); |
1752 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); |
| 1753 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
1753 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1754 | void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); |
1754 | uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); |
| 1755 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
1755 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1756 | void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); |
1756 | uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, |
| 1757 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
1757 | uint32_t BurstLength, uint32_t DataLength); |
| 1758 | 1758 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
|
| 1759 | /* Callbacks Register/UnRegister functions ***********************************/ |
1759 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1760 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
1760 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
| 1761 | HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, |
1761 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1762 | pTIM_CallbackTypeDef pCallback); |
1762 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, |
| 1763 | HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); |
1763 | uint32_t BurstLength, uint32_t DataLength); |
| 1764 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
1764 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
| 1765 | 1765 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
|
| 1766 | /** |
1766 | uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1767 | * @} |
1767 | /** |
| 1768 | */ |
1768 | * @} |
| 1769 | 1769 | */ |
|
| 1770 | /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions |
1770 | |
| 1771 | * @brief Peripheral State functions |
1771 | /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions |
| 1772 | * @{ |
1772 | * @brief TIM Callbacks functions |
| 1773 | */ |
1773 | * @{ |
| 1774 | /* Peripheral State functions ************************************************/ |
1774 | */ |
| 1775 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
1775 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
| 1776 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
1776 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
| 1777 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
1777 | void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 1778 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
1778 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
| 1779 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
1779 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
| 1780 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
1780 | void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 1781 | 1781 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
|
| 1782 | /* Peripheral Channel state functions ************************************************/ |
1782 | void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 1783 | HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); |
1783 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
| 1784 | HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); |
1784 | void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 1785 | HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); |
1785 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
| 1786 | /** |
1786 | |
| 1787 | * @} |
1787 | /* Callbacks Register/UnRegister functions ***********************************/ |
| 1788 | */ |
1788 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 1789 | 1789 | HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, |
|
| 1790 | /** |
1790 | pTIM_CallbackTypeDef pCallback); |
| 1791 | * @} |
1791 | HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); |
| 1792 | */ |
1792 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 1793 | /* End of exported functions -------------------------------------------------*/ |
1793 | |
| 1794 | 1794 | /** |
|
| 1795 | /* Private functions----------------------------------------------------------*/ |
1795 | * @} |
| 1796 | /** @defgroup TIM_Private_Functions TIM Private Functions |
1796 | */ |
| 1797 | * @{ |
1797 | |
| 1798 | */ |
1798 | /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions |
| 1799 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
1799 | * @brief Peripheral State functions |
| 1800 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
1800 | * @{ |
| 1801 | void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); |
1801 | */ |
| 1802 | 1802 | /* Peripheral State functions ************************************************/ |
|
| 1803 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
1803 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); |
| 1804 | void TIM_ResetCallback(TIM_HandleTypeDef *htim); |
1804 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); |
| 1805 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
1805 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); |
| 1806 | 1806 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); |
|
| 1807 | /** |
1807 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); |
| 1808 | * @} |
1808 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); |
| 1809 | */ |
1809 | |
| 1810 | /* End of private functions --------------------------------------------------*/ |
1810 | /* Peripheral Channel state functions ************************************************/ |
| 1811 | 1811 | HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); |
|
| 1812 | /** |
1812 | HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1813 | * @} |
1813 | HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); |
| 1814 | */ |
1814 | /** |
| 1815 | 1815 | * @} |
|
| 1816 | /** |
1816 | */ |
| 1817 | * @} |
1817 | |
| 1818 | */ |
1818 | /** |
| 1819 | 1819 | * @} |
|
| 1820 | #ifdef __cplusplus |
1820 | */ |
| 1821 | } |
1821 | /* End of exported functions -------------------------------------------------*/ |
| 1822 | #endif |
1822 | |
| 1823 | 1823 | /* Private functions----------------------------------------------------------*/ |
|
| 1824 | #endif /* STM32L1xx_HAL_TIM_H */ |
1824 | /** @defgroup TIM_Private_Functions TIM Private Functions |
| 1825 | 1825 | * @{ |
|
| 1826 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
1826 | */ |
| - | 1827 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
|
| - | 1828 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
|
| - | 1829 | void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); |
|
| - | 1830 | ||
| - | 1831 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
| - | 1832 | void TIM_ResetCallback(TIM_HandleTypeDef *htim); |
|
| - | 1833 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
| - | 1834 | ||
| - | 1835 | /** |
|
| - | 1836 | * @} |
|
| - | 1837 | */ |
|
| - | 1838 | /* End of private functions --------------------------------------------------*/ |
|
| - | 1839 | ||
| - | 1840 | /** |
|
| - | 1841 | * @} |
|
| - | 1842 | */ |
|
| - | 1843 | ||
| - | 1844 | /** |
|
| - | 1845 | * @} |
|
| - | 1846 | */ |
|
| - | 1847 | ||
| - | 1848 | #ifdef __cplusplus |
|
| - | 1849 | } |
|
| - | 1850 | #endif |
|
| - | 1851 | ||
| - | 1852 | #endif /* STM32L1xx_HAL_TIM_H */ |
|