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4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
5 | * @brief Header file of SRAM HAL module. |
5 | * @brief Header file of SRAM HAL module. |
6 | ****************************************************************************** |
6 | ****************************************************************************** |
7 | * @attention |
7 | * @attention |
8 | * |
8 | * |
9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
10 | * All rights reserved.</center></h2> |
10 | * All rights reserved.</center></h2> |
11 | * |
11 | * |
12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software component is licensed by ST under BSD 3-Clause license, |
13 | * the "License"; You may not use this file except in compliance with the |
13 | * the "License"; You may not use this file except in compliance with the |
14 | * License. You may obtain a copy of the License at: |
14 | * License. You may obtain a copy of the License at: |
15 | * opensource.org/licenses/BSD-3-Clause |
15 | * opensource.org/licenses/BSD-3-Clause |
16 | * |
16 | * |
17 | ****************************************************************************** |
17 | ****************************************************************************** |
18 | */ |
18 | */ |
19 | 19 | ||
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
21 | #ifndef __STM32L1xx_HAL_SRAM_H |
21 | #ifndef STM32L1xx_HAL_SRAM_H |
22 | #define __STM32L1xx_HAL_SRAM_H |
22 | #define STM32L1xx_HAL_SRAM_H |
23 | 23 | ||
24 | #ifdef __cplusplus |
24 | #ifdef __cplusplus |
25 | extern "C" { |
25 | extern "C" { |
26 | #endif |
26 | #endif |
27 | 27 | ||
- | 28 | #if defined(FSMC_BANK1) |
|
- | 29 | ||
28 | /* Includes ------------------------------------------------------------------*/ |
30 | /* Includes ------------------------------------------------------------------*/ |
29 | #include "stm32l1xx_ll_fsmc.h" |
31 | #include "stm32l1xx_ll_fsmc.h" |
30 | 32 | ||
31 | /** @addtogroup STM32L1xx_HAL_Driver |
33 | /** @addtogroup STM32L1xx_HAL_Driver |
32 | * @{ |
34 | * @{ |
33 | */ |
35 | */ |
34 | - | ||
35 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
- | |
36 | - | ||
37 | /** @addtogroup SRAM |
36 | /** @addtogroup SRAM |
38 | * @{ |
37 | * @{ |
39 | */ |
38 | */ |
40 | 39 | ||
41 | /* Exported typedef ----------------------------------------------------------*/ |
40 | /* Exported typedef ----------------------------------------------------------*/ |
42 | 41 | ||
43 | /** @defgroup SRAM_Exported_Types SRAM Exported Types |
42 | /** @defgroup SRAM_Exported_Types SRAM Exported Types |
44 | * @{ |
43 | * @{ |
45 | */ |
44 | */ |
46 | /** |
45 | /** |
47 | * @brief HAL SRAM State structures definition |
46 | * @brief HAL SRAM State structures definition |
48 | */ |
47 | */ |
49 | typedef enum |
48 | typedef enum |
50 | { |
49 | { |
51 | HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ |
50 | HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ |
52 | HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ |
51 | HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ |
53 | HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ |
52 | HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ |
54 | HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ |
53 | HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ |
55 | HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ |
54 | HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ |
56 | 55 | ||
57 | }HAL_SRAM_StateTypeDef; |
56 | } HAL_SRAM_StateTypeDef; |
58 | 57 | ||
59 | /** |
58 | /** |
60 | * @brief SRAM handle Structure definition |
59 | * @brief SRAM handle Structure definition |
61 | */ |
60 | */ |
- | 61 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|
- | 62 | typedef struct __SRAM_HandleTypeDef |
|
- | 63 | #else |
|
62 | typedef struct |
64 | typedef struct |
- | 65 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|
63 | { |
66 | { |
64 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
67 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
65 | 68 | ||
66 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
69 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
67 | 70 | ||
68 | FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
71 | FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
69 | 72 | ||
70 | HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
73 | HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
71 | 74 | ||
72 | __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
75 | __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
73 | 76 | ||
74 | DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
77 | DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
75 | - | ||
76 | }SRAM_HandleTypeDef; |
- | |
77 | 78 | ||
- | 79 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|
- | 80 | void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ |
|
- | 81 | void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ |
|
- | 82 | void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ |
|
- | 83 | void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ |
|
- | 84 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|
- | 85 | } SRAM_HandleTypeDef; |
|
- | 86 | ||
- | 87 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|
- | 88 | /** |
|
- | 89 | * @brief HAL SRAM Callback ID enumeration definition |
|
- | 90 | */ |
|
- | 91 | typedef enum |
|
- | 92 | { |
|
- | 93 | HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ |
|
- | 94 | HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ |
|
- | 95 | HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ |
|
- | 96 | HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ |
|
- | 97 | } HAL_SRAM_CallbackIDTypeDef; |
|
- | 98 | ||
- | 99 | /** |
|
- | 100 | * @brief HAL SRAM Callback pointer definition |
|
- | 101 | */ |
|
- | 102 | typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); |
|
- | 103 | typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); |
|
- | 104 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|
78 | /** |
105 | /** |
79 | * @} |
106 | * @} |
80 | */ |
107 | */ |
81 | 108 | ||
82 | /* Exported constants --------------------------------------------------------*/ |
109 | /* Exported constants --------------------------------------------------------*/ |
83 | /* Exported macro ------------------------------------------------------------*/ |
110 | /* Exported macro ------------------------------------------------------------*/ |
84 | 111 | ||
85 | /** @defgroup SRAM_Exported_Macros SRAM Exported Macros |
112 | /** @defgroup SRAM_Exported_Macros SRAM Exported Macros |
86 | * @{ |
113 | * @{ |
87 | */ |
114 | */ |
88 | 115 | ||
89 | /** @brief Reset SRAM handle state |
116 | /** @brief Reset SRAM handle state |
90 | * @param __HANDLE__ SRAM handle |
117 | * @param __HANDLE__ SRAM handle |
91 | * @retval None |
118 | * @retval None |
92 | */ |
119 | */ |
- | 120 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|
- | 121 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|
- | 122 | (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ |
|
- | 123 | (__HANDLE__)->MspInitCallback = NULL; \ |
|
- | 124 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
|
- | 125 | } while(0) |
|
- | 126 | #else |
|
93 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
127 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
- | 128 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|
94 | 129 | ||
95 | /** |
130 | /** |
96 | * @} |
131 | * @} |
97 | */ |
132 | */ |
98 | 133 | ||
99 | /* Exported functions --------------------------------------------------------*/ |
134 | /* Exported functions --------------------------------------------------------*/ |
- | 135 | /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions |
|
- | 136 | * @{ |
|
- | 137 | */ |
|
100 | 138 | ||
101 | /** @addtogroup SRAM_Exported_Functions |
- | |
102 | * @{ |
- | |
103 | */ |
- | |
104 | - | ||
105 | /** @addtogroup SRAM_Exported_Functions_Group1 |
139 | /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
106 | * @{ |
140 | * @{ |
107 | */ |
141 | */ |
108 | - | ||
109 | /* Initialization/de-initialization functions **********************************/ |
- | |
110 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
- | |
111 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
- | |
112 | void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
- | |
113 | void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
- | |
114 | 142 | ||
- | 143 | /* Initialization/de-initialization functions ********************************/ |
|
- | 144 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, |
|
- | 145 | FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
|
115 | void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
146 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
- | 147 | void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
|
116 | void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
148 | void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
117 | 149 | ||
118 | /** |
150 | /** |
119 | * @} |
151 | * @} |
120 | */ |
152 | */ |
- | 153 | ||
- | 154 | /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions |
|
- | 155 | * @{ |
|
- | 156 | */ |
|
121 | 157 | ||
122 | /** @addtogroup SRAM_Exported_Functions_Group2 |
- | |
123 | * @{ |
- | |
124 | */ |
- | |
125 | - | ||
126 | /* I/O operation functions *****************************************************/ |
158 | /* I/O operation functions ***************************************************/ |
127 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); |
159 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, |
- | 160 | uint32_t BufferSize); |
|
128 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); |
161 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, |
- | 162 | uint32_t BufferSize); |
|
129 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); |
163 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, |
- | 164 | uint32_t BufferSize); |
|
130 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); |
165 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, |
- | 166 | uint32_t BufferSize); |
|
131 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
167 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, |
- | 168 | uint32_t BufferSize); |
|
132 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
169 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
- | 170 | uint32_t BufferSize); |
|
133 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
171 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, |
- | 172 | uint32_t BufferSize); |
|
134 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
173 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
- | 174 | uint32_t BufferSize); |
|
- | 175 | ||
- | 176 | void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
|
- | 177 | void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
|
- | 178 | ||
- | 179 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|
- | 180 | /* SRAM callback registering/unregistering */ |
|
- | 181 | HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, |
|
- | 182 | pSRAM_CallbackTypeDef pCallback); |
|
- | 183 | HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); |
|
- | 184 | HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, |
|
- | 185 | pSRAM_DmaCallbackTypeDef pCallback); |
|
- | 186 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|
135 | 187 | ||
136 | /** |
188 | /** |
137 | * @} |
189 | * @} |
138 | */ |
190 | */ |
139 | 191 | ||
140 | /** @addtogroup SRAM_Exported_Functions_Group3 |
192 | /** @addtogroup SRAM_Exported_Functions_Group3 Control functions |
141 | * @{ |
193 | * @{ |
142 | */ |
194 | */ |
143 | 195 | ||
144 | /* SRAM Control functions ******************************************************/ |
196 | /* SRAM Control functions ****************************************************/ |
145 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
197 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
146 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
198 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
147 | 199 | ||
148 | /** |
200 | /** |
149 | * @} |
201 | * @} |
150 | */ |
202 | */ |
- | 203 | ||
- | 204 | /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions |
|
- | 205 | * @{ |
|
- | 206 | */ |
|
151 | 207 | ||
152 | /** @addtogroup SRAM_Exported_Functions_Group4 |
- | |
153 | * @{ |
- | |
154 | */ |
- | |
155 | - | ||
156 | /* SRAM State functions *********************************************************/ |
208 | /* SRAM State functions ******************************************************/ |
157 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
209 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
158 | 210 | ||
159 | /** |
211 | /** |
160 | * @} |
212 | * @} |
161 | */ |
213 | */ |
162 | 214 | ||
163 | /** |
215 | /** |
164 | * @} |
216 | * @} |
165 | */ |
217 | */ |
166 | 218 | ||
167 | /** |
219 | /** |
168 | * @} |
220 | * @} |
169 | */ |
221 | */ |
170 | - | ||
171 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
- | |
172 | 222 | ||
173 | /** |
223 | /** |
174 | * @} |
224 | * @} |
175 | */ |
225 | */ |
- | 226 | ||
- | 227 | #endif /* FSMC_BANK1 */ |
|
176 | 228 | ||
177 | #ifdef __cplusplus |
229 | #ifdef __cplusplus |
178 | } |
230 | } |
179 | #endif |
231 | #endif |
180 | 232 | ||
181 | #endif /* __STM32L1xx_HAL_SRAM_H */ |
233 | #endif /* STM32L1xx_HAL_SRAM_H */ |
182 | 234 | ||
183 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
235 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |