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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_hal_spi.h |
3 | * @file stm32l1xx_hal_spi.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of SPI HAL module. |
5 | * @brief Header file of SPI HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32L1xx_HAL_SPI_H |
| 21 | #ifndef STM32L1xx_HAL_SPI_H |
21 | #define STM32L1xx_HAL_SPI_H |
| 22 | #define STM32L1xx_HAL_SPI_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32l1xx_hal_def.h" |
| 29 | #include "stm32l1xx_hal_def.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_HAL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | /** @addtogroup SPI |
|
| 35 | /** @addtogroup SPI |
35 | * @{ |
| 36 | * @{ |
36 | */ |
| 37 | */ |
37 | |
| 38 | 38 | /* Exported types ------------------------------------------------------------*/ |
|
| 39 | /* Exported types ------------------------------------------------------------*/ |
39 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| 40 | /** @defgroup SPI_Exported_Types SPI Exported Types |
40 | * @{ |
| 41 | * @{ |
41 | */ |
| 42 | */ |
42 | |
| 43 | 43 | /** |
|
| 44 | /** |
44 | * @brief SPI Configuration Structure definition |
| 45 | * @brief SPI Configuration Structure definition |
45 | */ |
| 46 | */ |
46 | typedef struct |
| 47 | typedef struct |
47 | { |
| 48 | { |
48 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| 49 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
49 | This parameter can be a value of @ref SPI_Mode */ |
| 50 | This parameter can be a value of @ref SPI_Mode */ |
50 | |
| 51 | 51 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
|
| 52 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
52 | This parameter can be a value of @ref SPI_Direction */ |
| 53 | This parameter can be a value of @ref SPI_Direction */ |
53 | |
| 54 | 54 | uint32_t DataSize; /*!< Specifies the SPI data size. |
|
| 55 | uint32_t DataSize; /*!< Specifies the SPI data size. |
55 | This parameter can be a value of @ref SPI_Data_Size */ |
| 56 | This parameter can be a value of @ref SPI_Data_Size */ |
56 | |
| 57 | 57 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
|
| 58 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
58 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| 59 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
59 | |
| 60 | 60 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
|
| 61 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
61 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| 62 | This parameter can be a value of @ref SPI_Clock_Phase */ |
62 | |
| 63 | 63 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
|
| 64 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
64 | hardware (NSS pin) or by software using the SSI bit. |
| 65 | hardware (NSS pin) or by software using the SSI bit. |
65 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| 66 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
66 | |
| 67 | 67 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
|
| 68 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
68 | used to configure the transmit and receive SCK clock. |
| 69 | used to configure the transmit and receive SCK clock. |
69 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| 70 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
70 | @note The communication clock is derived from the master |
| 71 | @note The communication clock is derived from the master |
71 | clock. The slave clock does not need to be set. */ |
| 72 | clock. The slave clock does not need to be set. */ |
72 | |
| 73 | 73 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
|
| 74 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
74 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| 75 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
75 | |
| 76 | 76 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
|
| 77 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
77 | This parameter can be a value of @ref SPI_TI_mode */ |
| 78 | This parameter can be a value of @ref SPI_TI_mode */ |
78 | |
| 79 | 79 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
|
| 80 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
80 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| 81 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
81 | |
| 82 | 82 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
|
| 83 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
83 | This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ |
| 84 | This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ |
84 | } SPI_InitTypeDef; |
| 85 | } SPI_InitTypeDef; |
85 | |
| 86 | 86 | /** |
|
| 87 | /** |
87 | * @brief HAL SPI State structure definition |
| 88 | * @brief HAL SPI State structure definition |
88 | */ |
| 89 | */ |
89 | typedef enum |
| 90 | typedef enum |
90 | { |
| 91 | { |
91 | HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
| 92 | HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
92 | HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| 93 | HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
93 | HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
| 94 | HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
94 | HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
| 95 | HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
95 | HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
| 96 | HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
96 | HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
| 97 | HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
97 | HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
| 98 | HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
98 | HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
| 99 | HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
99 | } HAL_SPI_StateTypeDef; |
| 100 | } HAL_SPI_StateTypeDef; |
100 | |
| 101 | 101 | /** |
|
| 102 | /** |
102 | * @brief SPI handle Structure definition |
| 103 | * @brief SPI handle Structure definition |
103 | */ |
| 104 | */ |
104 | typedef struct __SPI_HandleTypeDef |
| 105 | typedef struct __SPI_HandleTypeDef |
105 | { |
| 106 | { |
106 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
| 107 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
107 | |
| 108 | 108 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
|
| 109 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
109 | |
| 110 | 110 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
|
| 111 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
111 | |
| 112 | 112 | uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
|
| 113 | uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
113 | |
| 114 | 114 | __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
|
| 115 | __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
115 | |
| 116 | 116 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
|
| 117 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
117 | |
| 118 | 118 | uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
|
| 119 | uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
119 | |
| 120 | 120 | __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
|
| 121 | __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
121 | |
| 122 | 122 | void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
|
| 123 | void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
123 | |
| 124 | 124 | void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
|
| 125 | void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
125 | |
| 126 | 126 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
|
| 127 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
127 | |
| 128 | 128 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
|
| 129 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
129 | |
| 130 | 130 | HAL_LockTypeDef Lock; /*!< Locking object */ |
|
| 131 | HAL_LockTypeDef Lock; /*!< Locking object */ |
131 | |
| 132 | 132 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
|
| 133 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
133 | |
| 134 | 134 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
|
| 135 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
135 | |
| 136 | 136 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|
| 137 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
137 | void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ |
| 138 | void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ |
138 | void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ |
| 139 | void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ |
139 | void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ |
| 140 | void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ |
140 | void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ |
| 141 | void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ |
141 | void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ |
| 142 | void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ |
142 | void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ |
| 143 | void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ |
143 | void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ |
| 144 | void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ |
144 | void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ |
| 145 | void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ |
145 | void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ |
| 146 | void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ |
146 | void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ |
| 147 | void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ |
147 | |
| 148 | 148 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|
| 149 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
149 | } SPI_HandleTypeDef; |
| 150 | } SPI_HandleTypeDef; |
150 | |
| 151 | 151 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|
| 152 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
152 | /** |
| 153 | /** |
153 | * @brief HAL SPI Callback ID enumeration definition |
| 154 | * @brief HAL SPI Callback ID enumeration definition |
154 | */ |
| 155 | */ |
155 | typedef enum |
| 156 | typedef enum |
156 | { |
| 157 | { |
157 | HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ |
| 158 | HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ |
158 | HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ |
| 159 | HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ |
159 | HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ |
| 160 | HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ |
160 | HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ |
| 161 | HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ |
161 | HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ |
| 162 | HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ |
162 | HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ |
| 163 | HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ |
163 | HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ |
| 164 | HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ |
164 | HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ |
| 165 | HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ |
165 | HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ |
| 166 | HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ |
166 | HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ |
| 167 | HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ |
167 | |
| 168 | 168 | } HAL_SPI_CallbackIDTypeDef; |
|
| 169 | } HAL_SPI_CallbackIDTypeDef; |
169 | |
| 170 | 170 | /** |
|
| 171 | /** |
171 | * @brief HAL SPI Callback pointer definition |
| 172 | * @brief HAL SPI Callback pointer definition |
172 | */ |
| 173 | */ |
173 | typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ |
| 174 | typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ |
174 | |
| 175 | 175 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|
| 176 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
176 | /** |
| 177 | /** |
177 | * @} |
| 178 | * @} |
178 | */ |
| 179 | */ |
179 | |
| 180 | 180 | /* Exported constants --------------------------------------------------------*/ |
|
| 181 | /* Exported constants --------------------------------------------------------*/ |
181 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| 182 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
182 | * @{ |
| 183 | * @{ |
183 | */ |
| 184 | */ |
184 | |
| 185 | 185 | /** @defgroup SPI_Error_Code SPI Error Code |
|
| 186 | /** @defgroup SPI_Error_Code SPI Error Code |
186 | * @{ |
| 187 | * @{ |
187 | */ |
| 188 | */ |
188 | #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ |
| 189 | #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ |
189 | #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ |
| 190 | #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ |
190 | #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ |
| 191 | #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ |
191 | #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ |
| 192 | #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ |
192 | #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ |
| 193 | #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ |
193 | #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
| 194 | #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
194 | #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ |
| 195 | #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ |
195 | #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ |
| 196 | #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ |
196 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
| 197 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
197 | #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ |
| 198 | #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ |
198 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
| 199 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
199 | /** |
| 200 | /** |
200 | * @} |
| 201 | * @} |
201 | */ |
| 202 | */ |
202 | |
| 203 | 203 | /** @defgroup SPI_Mode SPI Mode |
|
| 204 | /** @defgroup SPI_Mode SPI Mode |
204 | * @{ |
| 205 | * @{ |
205 | */ |
| 206 | */ |
206 | #define SPI_MODE_SLAVE (0x00000000U) |
| 207 | #define SPI_MODE_SLAVE (0x00000000U) |
207 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| 208 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
208 | /** |
| 209 | /** |
209 | * @} |
| 210 | * @} |
210 | */ |
| 211 | */ |
211 | |
| 212 | 212 | /** @defgroup SPI_Direction SPI Direction Mode |
|
| 213 | /** @defgroup SPI_Direction SPI Direction Mode |
213 | * @{ |
| 214 | * @{ |
214 | */ |
| 215 | */ |
215 | #define SPI_DIRECTION_2LINES (0x00000000U) |
| 216 | #define SPI_DIRECTION_2LINES (0x00000000U) |
216 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| 217 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
217 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| 218 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
218 | /** |
| 219 | /** |
219 | * @} |
| 220 | * @} |
220 | */ |
| 221 | */ |
221 | |
| 222 | 222 | /** @defgroup SPI_Data_Size SPI Data Size |
|
| 223 | /** @defgroup SPI_Data_Size SPI Data Size |
223 | * @{ |
| 224 | * @{ |
224 | */ |
| 225 | */ |
225 | #define SPI_DATASIZE_8BIT (0x00000000U) |
| 226 | #define SPI_DATASIZE_8BIT (0x00000000U) |
226 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
| 227 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
227 | /** |
| 228 | /** |
228 | * @} |
| 229 | * @} |
229 | */ |
| 230 | */ |
230 | |
| 231 | 231 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
|
| 232 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
232 | * @{ |
| 233 | * @{ |
233 | */ |
| 234 | */ |
234 | #define SPI_POLARITY_LOW (0x00000000U) |
| 235 | #define SPI_POLARITY_LOW (0x00000000U) |
235 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| 236 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
236 | /** |
| 237 | /** |
237 | * @} |
| 238 | * @} |
238 | */ |
| 239 | */ |
239 | |
| 240 | 240 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
|
| 241 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
241 | * @{ |
| 242 | * @{ |
242 | */ |
| 243 | */ |
243 | #define SPI_PHASE_1EDGE (0x00000000U) |
| 244 | #define SPI_PHASE_1EDGE (0x00000000U) |
244 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| 245 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
245 | /** |
| 246 | /** |
246 | * @} |
| 247 | * @} |
247 | */ |
| 248 | */ |
248 | |
| 249 | 249 | /** @defgroup SPI_Slave_Select_management SPI Slave Select Management |
|
| 250 | /** @defgroup SPI_Slave_Select_management SPI Slave Select Management |
250 | * @{ |
| 251 | * @{ |
251 | */ |
| 252 | */ |
252 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| 253 | #define SPI_NSS_SOFT SPI_CR1_SSM |
253 | #define SPI_NSS_HARD_INPUT (0x00000000U) |
| 254 | #define SPI_NSS_HARD_INPUT (0x00000000U) |
254 | #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) |
| 255 | #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) |
255 | /** |
| 256 | /** |
256 | * @} |
| 257 | * @} |
257 | */ |
| 258 | */ |
258 | |
| 259 | 259 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
|
| 260 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
260 | * @{ |
| 261 | * @{ |
261 | */ |
| 262 | */ |
262 | #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
| 263 | #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
263 | #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) |
| 264 | #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) |
264 | #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) |
| 265 | #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) |
265 | #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| 266 | #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) |
266 | #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) |
| 267 | #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) |
267 | #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) |
| 268 | #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) |
268 | #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) |
| 269 | #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) |
269 | #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| 270 | #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
270 | /** |
| 271 | /** |
271 | * @} |
| 272 | * @} |
272 | */ |
| 273 | */ |
273 | |
| 274 | 274 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission |
|
| 275 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission |
275 | * @{ |
| 276 | * @{ |
276 | */ |
| 277 | */ |
277 | #define SPI_FIRSTBIT_MSB (0x00000000U) |
| 278 | #define SPI_FIRSTBIT_MSB (0x00000000U) |
278 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| 279 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
279 | /** |
| 280 | /** |
280 | * @} |
| 281 | * @} |
281 | */ |
| 282 | */ |
282 | |
| 283 | 283 | /** @defgroup SPI_TI_mode SPI TI Mode |
|
| 284 | /** @defgroup SPI_TI_mode SPI TI Mode |
284 | * @brief SPI TI Mode not supported for Category 1 and 2 |
| 285 | * @brief SPI TI Mode not supported for Category 1 and 2 |
285 | * @{ |
| 286 | * @{ |
286 | */ |
| 287 | */ |
287 | #define SPI_TIMODE_DISABLE (0x00000000U) |
| 288 | #define SPI_TIMODE_DISABLE (0x00000000U) |
288 | #if defined(SPI_CR2_FRF) |
| 289 | #if defined(SPI_CR2_FRF) |
289 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
| 290 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
290 | #endif /* SPI_CR2_FRF */ |
| 291 | #endif |
291 | /** |
| 292 | /** |
292 | * @} |
| 293 | * @} |
293 | */ |
| 294 | */ |
294 | |
| 295 | 295 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
|
| 296 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
296 | * @{ |
| 297 | * @{ |
297 | */ |
| 298 | */ |
298 | #define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
| 299 | #define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
299 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| 300 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
300 | /** |
| 301 | /** |
301 | * @} |
| 302 | * @} |
302 | */ |
| 303 | */ |
303 | |
| 304 | 304 | /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition |
|
| 305 | /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition |
305 | * @{ |
| 306 | * @{ |
306 | */ |
| 307 | */ |
307 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| 308 | #define SPI_IT_TXE SPI_CR2_TXEIE |
308 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| 309 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
309 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| 310 | #define SPI_IT_ERR SPI_CR2_ERRIE |
310 | /** |
| 311 | /** |
311 | * @} |
| 312 | * @} |
312 | */ |
| 313 | */ |
313 | |
| 314 | 314 | /** @defgroup SPI_Flags_definition SPI Flags Definition |
|
| 315 | /** @defgroup SPI_Flags_definition SPI Flags Definition |
315 | * @{ |
| 316 | * @{ |
316 | */ |
| 317 | */ |
317 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
| 318 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
318 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
| 319 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
319 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
| 320 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
320 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
| 321 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
321 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
| 322 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
322 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
| 323 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
323 | #if defined(SPI_CR2_FRF) |
| 324 | #if defined(SPI_CR2_FRF) |
324 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
| 325 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
325 | #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ |
| 326 | #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ |
326 | | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) |
| 327 | | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) |
327 | #else |
| 328 | #else |
328 | #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\ |
| 329 | #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\ |
329 | | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR) |
| 330 | | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR) |
330 | #endif |
| 331 | #endif |
331 | /** |
| 332 | /** |
332 | * @} |
| 333 | * @} |
333 | */ |
| 334 | */ |
334 | |
| 335 | 335 | /** |
|
| 336 | /** |
336 | * @} |
| 337 | * @} |
337 | */ |
| 338 | */ |
338 | |
| 339 | 339 | /* Exported macros -----------------------------------------------------------*/ |
|
| 340 | /* Exported macros -----------------------------------------------------------*/ |
340 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| 341 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
341 | * @{ |
| 342 | * @{ |
342 | */ |
| 343 | */ |
343 | |
| 344 | 344 | /** @brief Reset SPI handle state. |
|
| 345 | /** @brief Reset SPI handle state. |
345 | * @param __HANDLE__ specifies the SPI Handle. |
| 346 | * @param __HANDLE__ specifies the SPI Handle. |
346 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 347 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
347 | * @retval None |
| 348 | * @retval None |
348 | */ |
| 349 | */ |
349 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
| 350 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
350 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
| 351 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
351 | (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ |
| 352 | (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ |
352 | (__HANDLE__)->MspInitCallback = NULL; \ |
| 353 | (__HANDLE__)->MspInitCallback = NULL; \ |
353 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
| 354 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
354 | } while(0) |
| 355 | } while(0) |
355 | #else |
| 356 | #else |
356 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| 357 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
357 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
| 358 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
358 | |
| 359 | 359 | /** @brief Enable the specified SPI interrupts. |
|
| 360 | /** @brief Enable the specified SPI interrupts. |
360 | * @param __HANDLE__ specifies the SPI Handle. |
| 361 | * @param __HANDLE__ specifies the SPI Handle. |
361 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 362 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
362 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
| 363 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
363 | * This parameter can be one of the following values: |
| 364 | * This parameter can be one of the following values: |
364 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| 365 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
365 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| 366 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
366 | * @arg SPI_IT_ERR: Error interrupt enable |
| 367 | * @arg SPI_IT_ERR: Error interrupt enable |
367 | * @retval None |
| 368 | * @retval None |
368 | */ |
| 369 | */ |
369 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| 370 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
370 | |
| 371 | 371 | /** @brief Disable the specified SPI interrupts. |
|
| 372 | /** @brief Disable the specified SPI interrupts. |
372 | * @param __HANDLE__ specifies the SPI handle. |
| 373 | * @param __HANDLE__ specifies the SPI handle. |
373 | * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. |
| 374 | * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. |
374 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
| 375 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
375 | * This parameter can be one of the following values: |
| 376 | * This parameter can be one of the following values: |
376 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| 377 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
377 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| 378 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
378 | * @arg SPI_IT_ERR: Error interrupt enable |
| 379 | * @arg SPI_IT_ERR: Error interrupt enable |
379 | * @retval None |
| 380 | * @retval None |
380 | */ |
| 381 | */ |
381 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| 382 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
382 | |
| 383 | 383 | /** @brief Check whether the specified SPI interrupt source is enabled or not. |
|
| 384 | /** @brief Check whether the specified SPI interrupt source is enabled or not. |
384 | * @param __HANDLE__ specifies the SPI Handle. |
| 385 | * @param __HANDLE__ specifies the SPI Handle. |
385 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 386 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
386 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
| 387 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
387 | * This parameter can be one of the following values: |
| 388 | * This parameter can be one of the following values: |
388 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| 389 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
389 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| 390 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
390 | * @arg SPI_IT_ERR: Error interrupt enable |
| 391 | * @arg SPI_IT_ERR: Error interrupt enable |
391 | * @retval The new state of __IT__ (TRUE or FALSE). |
| 392 | * @retval The new state of __IT__ (TRUE or FALSE). |
392 | */ |
| 393 | */ |
393 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
| 394 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
394 | & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| 395 | & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
395 | |
| 396 | 396 | /** @brief Check whether the specified SPI flag is set or not. |
|
| 397 | /** @brief Check whether the specified SPI flag is set or not. |
397 | * @param __HANDLE__ specifies the SPI Handle. |
| 398 | * @param __HANDLE__ specifies the SPI Handle. |
398 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 399 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
399 | * @param __FLAG__ specifies the flag to check. |
| 400 | * @param __FLAG__ specifies the flag to check. |
400 | * This parameter can be one of the following values: |
| 401 | * This parameter can be one of the following values: |
401 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| 402 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
402 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| 403 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
403 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| 404 | * @arg SPI_FLAG_CRCERR: CRC error flag |
404 | * @arg SPI_FLAG_MODF: Mode fault flag |
| 405 | * @arg SPI_FLAG_MODF: Mode fault flag |
405 | * @arg SPI_FLAG_OVR: Overrun flag |
| 406 | * @arg SPI_FLAG_OVR: Overrun flag |
406 | * @arg SPI_FLAG_BSY: Busy flag |
| 407 | * @arg SPI_FLAG_BSY: Busy flag |
407 | * @arg SPI_FLAG_FRE: Frame format error flag |
| 408 | * @arg SPI_FLAG_FRE: Frame format error flag |
408 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 409 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
409 | */ |
| 410 | */ |
410 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| 411 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
411 | |
| 412 | 412 | /** @brief Clear the SPI CRCERR pending flag. |
|
| 413 | /** @brief Clear the SPI CRCERR pending flag. |
413 | * @param __HANDLE__ specifies the SPI Handle. |
| 414 | * @param __HANDLE__ specifies the SPI Handle. |
414 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 415 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
415 | * @retval None |
| 416 | * @retval None |
416 | */ |
| 417 | */ |
417 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
| 418 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
418 | |
| 419 | 419 | /** @brief Clear the SPI MODF pending flag. |
|
| 420 | /** @brief Clear the SPI MODF pending flag. |
420 | * @param __HANDLE__ specifies the SPI Handle. |
| 421 | * @param __HANDLE__ specifies the SPI Handle. |
421 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 422 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
422 | * @retval None |
| 423 | * @retval None |
423 | */ |
| 424 | */ |
424 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| 425 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
425 | do{ \ |
| 426 | do{ \ |
426 | __IO uint32_t tmpreg_modf = 0x00U; \ |
| 427 | __IO uint32_t tmpreg_modf = 0x00U; \ |
427 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
| 428 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
428 | CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
| 429 | CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
429 | UNUSED(tmpreg_modf); \ |
| 430 | UNUSED(tmpreg_modf); \ |
430 | } while(0U) |
| 431 | } while(0U) |
431 | |
| 432 | 432 | /** @brief Clear the SPI OVR pending flag. |
|
| 433 | /** @brief Clear the SPI OVR pending flag. |
433 | * @param __HANDLE__ specifies the SPI Handle. |
| 434 | * @param __HANDLE__ specifies the SPI Handle. |
434 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 435 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
435 | * @retval None |
| 436 | * @retval None |
436 | */ |
| 437 | */ |
437 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| 438 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
438 | do{ \ |
| 439 | do{ \ |
439 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
| 440 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
440 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| 441 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
441 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| 442 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
442 | UNUSED(tmpreg_ovr); \ |
| 443 | UNUSED(tmpreg_ovr); \ |
443 | } while(0U) |
| 444 | } while(0U) |
444 | |
| 445 | 445 | /** @brief Clear the SPI FRE pending flag. |
|
| 446 | /** @brief Clear the SPI FRE pending flag. |
446 | * @param __HANDLE__ specifies the SPI Handle. |
| 447 | * @param __HANDLE__ specifies the SPI Handle. |
447 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 448 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
448 | * @retval None |
| 449 | * @retval None |
449 | */ |
| 450 | */ |
450 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| 451 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
451 | do{ \ |
| 452 | do{ \ |
452 | __IO uint32_t tmpreg_fre = 0x00U; \ |
| 453 | __IO uint32_t tmpreg_fre = 0x00U; \ |
453 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
| 454 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
454 | UNUSED(tmpreg_fre); \ |
| 455 | UNUSED(tmpreg_fre); \ |
455 | }while(0U) |
| 456 | }while(0U) |
456 | |
| 457 | 457 | /** @brief Enable the SPI peripheral. |
|
| 458 | /** @brief Enable the SPI peripheral. |
458 | * @param __HANDLE__ specifies the SPI Handle. |
| 459 | * @param __HANDLE__ specifies the SPI Handle. |
459 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 460 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
460 | * @retval None |
| 461 | * @retval None |
461 | */ |
| 462 | */ |
462 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| 463 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
463 | |
| 464 | 464 | /** @brief Disable the SPI peripheral. |
|
| 465 | /** @brief Disable the SPI peripheral. |
465 | * @param __HANDLE__ specifies the SPI Handle. |
| 466 | * @param __HANDLE__ specifies the SPI Handle. |
466 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 467 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
467 | * @retval None |
| 468 | * @retval None |
468 | */ |
| 469 | */ |
469 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| 470 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
470 | |
| 471 | 471 | /** |
|
| 472 | /** |
472 | * @} |
| 473 | * @} |
473 | */ |
| 474 | */ |
474 | |
| 475 | 475 | /* Private macros ------------------------------------------------------------*/ |
|
| 476 | /* Private macros ------------------------------------------------------------*/ |
476 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| 477 | /** @defgroup SPI_Private_Macros SPI Private Macros |
477 | * @{ |
| 478 | * @{ |
478 | */ |
| 479 | */ |
479 | |
| 480 | 480 | /** @brief Set the SPI transmit-only mode. |
|
| 481 | /** @brief Set the SPI transmit-only mode. |
481 | * @param __HANDLE__ specifies the SPI Handle. |
| 482 | * @param __HANDLE__ specifies the SPI Handle. |
482 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 483 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
483 | * @retval None |
| 484 | * @retval None |
484 | */ |
| 485 | */ |
485 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| 486 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
486 | |
| 487 | 487 | /** @brief Set the SPI receive-only mode. |
|
| 488 | /** @brief Set the SPI receive-only mode. |
488 | * @param __HANDLE__ specifies the SPI Handle. |
| 489 | * @param __HANDLE__ specifies the SPI Handle. |
489 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 490 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
490 | * @retval None |
| 491 | * @retval None |
491 | */ |
| 492 | */ |
492 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| 493 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
493 | |
| 494 | 494 | /** @brief Reset the CRC calculation of the SPI. |
|
| 495 | /** @brief Reset the CRC calculation of the SPI. |
495 | * @param __HANDLE__ specifies the SPI Handle. |
| 496 | * @param __HANDLE__ specifies the SPI Handle. |
496 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| 497 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
497 | * @retval None |
| 498 | * @retval None |
498 | */ |
| 499 | */ |
499 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
| 500 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
500 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) |
| 501 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) |
501 | |
| 502 | 502 | /** @brief Check whether the specified SPI flag is set or not. |
|
| 503 | /** @brief Check whether the specified SPI flag is set or not. |
503 | * @param __SR__ copy of SPI SR register. |
| 504 | * @param __SR__ copy of SPI SR register. |
504 | * @param __FLAG__ specifies the flag to check. |
| 505 | * @param __FLAG__ specifies the flag to check. |
505 | * This parameter can be one of the following values: |
| 506 | * This parameter can be one of the following values: |
506 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| 507 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
507 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| 508 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
508 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| 509 | * @arg SPI_FLAG_CRCERR: CRC error flag |
509 | * @arg SPI_FLAG_MODF: Mode fault flag |
| 510 | * @arg SPI_FLAG_MODF: Mode fault flag |
510 | * @arg SPI_FLAG_OVR: Overrun flag |
| 511 | * @arg SPI_FLAG_OVR: Overrun flag |
511 | * @arg SPI_FLAG_BSY: Busy flag |
| 512 | * @arg SPI_FLAG_BSY: Busy flag |
512 | * @arg SPI_FLAG_FRE: Frame format error flag |
| 513 | * @arg SPI_FLAG_FRE: Frame format error flag |
513 | * @retval SET or RESET. |
| 514 | * @retval SET or RESET. |
514 | */ |
| 515 | */ |
515 | #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ |
| 516 | #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ |
516 | ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) |
| 517 | ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) |
517 | |
| 518 | 518 | /** @brief Check whether the specified SPI Interrupt is set or not. |
|
| 519 | /** @brief Check whether the specified SPI Interrupt is set or not. |
519 | * @param __CR2__ copy of SPI CR2 register. |
| 520 | * @param __CR2__ copy of SPI CR2 register. |
520 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
| 521 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
521 | * This parameter can be one of the following values: |
| 522 | * This parameter can be one of the following values: |
522 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| 523 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
523 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| 524 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
524 | * @arg SPI_IT_ERR: Error interrupt enable |
| 525 | * @arg SPI_IT_ERR: Error interrupt enable |
525 | * @retval SET or RESET. |
| 526 | * @retval SET or RESET. |
526 | */ |
| 527 | */ |
527 | #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ |
| 528 | #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ |
528 | (__INTERRUPT__)) ? SET : RESET) |
| 529 | (__INTERRUPT__)) ? SET : RESET) |
529 | |
| 530 | 530 | /** @brief Checks if SPI Mode parameter is in allowed range. |
|
| 531 | /** @brief Checks if SPI Mode parameter is in allowed range. |
531 | * @param __MODE__ specifies the SPI Mode. |
| 532 | * @param __MODE__ specifies the SPI Mode. |
532 | * This parameter can be a value of @ref SPI_Mode |
| 533 | * This parameter can be a value of @ref SPI_Mode |
533 | * @retval None |
| 534 | * @retval None |
534 | */ |
| 535 | */ |
535 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ |
| 536 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ |
536 | ((__MODE__) == SPI_MODE_MASTER)) |
| 537 | ((__MODE__) == SPI_MODE_MASTER)) |
537 | |
| 538 | 538 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
|
| 539 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
539 | * @param __MODE__ specifies the SPI Direction Mode. |
| 540 | * @param __MODE__ specifies the SPI Direction Mode. |
540 | * This parameter can be a value of @ref SPI_Direction |
| 541 | * This parameter can be a value of @ref SPI_Direction |
541 | * @retval None |
| 542 | * @retval None |
542 | */ |
| 543 | */ |
543 | #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| 544 | #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
544 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| 545 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
545 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| 546 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
546 | |
| 547 | 547 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
|
| 548 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
548 | * @param __MODE__ specifies the SPI Direction Mode. |
| 549 | * @param __MODE__ specifies the SPI Direction Mode. |
549 | * @retval None |
| 550 | * @retval None |
550 | */ |
| 551 | */ |
551 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
| 552 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
552 | |
| 553 | 553 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
|
| 554 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
554 | * @param __MODE__ specifies the SPI Direction Mode. |
| 555 | * @param __MODE__ specifies the SPI Direction Mode. |
555 | * @retval None |
| 556 | * @retval None |
556 | */ |
| 557 | */ |
557 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| 558 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
558 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| 559 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
559 | |
| 560 | 560 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
|
| 561 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
561 | * @param __DATASIZE__ specifies the SPI Data Size. |
| 562 | * @param __DATASIZE__ specifies the SPI Data Size. |
562 | * This parameter can be a value of @ref SPI_Data_Size |
| 563 | * This parameter can be a value of @ref SPI_Data_Size |
563 | * @retval None |
| 564 | * @retval None |
564 | */ |
| 565 | */ |
565 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
| 566 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
566 | ((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
| 567 | ((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
567 | |
| 568 | 568 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
|
| 569 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
569 | * @param __CPOL__ specifies the SPI serial clock steady state. |
| 570 | * @param __CPOL__ specifies the SPI serial clock steady state. |
570 | * This parameter can be a value of @ref SPI_Clock_Polarity |
| 571 | * This parameter can be a value of @ref SPI_Clock_Polarity |
571 | * @retval None |
| 572 | * @retval None |
572 | */ |
| 573 | */ |
573 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
| 574 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
574 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
| 575 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
575 | |
| 576 | 576 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
|
| 577 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
577 | * @param __CPHA__ specifies the SPI Clock Phase. |
| 578 | * @param __CPHA__ specifies the SPI Clock Phase. |
578 | * This parameter can be a value of @ref SPI_Clock_Phase |
| 579 | * This parameter can be a value of @ref SPI_Clock_Phase |
579 | * @retval None |
| 580 | * @retval None |
580 | */ |
| 581 | */ |
581 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
| 582 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
582 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
| 583 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
583 | |
| 584 | 584 | /** @brief Checks if SPI Slave Select parameter is in allowed range. |
|
| 585 | /** @brief Checks if SPI Slave Select parameter is in allowed range. |
585 | * @param __NSS__ specifies the SPI Slave Select management parameter. |
| 586 | * @param __NSS__ specifies the SPI Slave Select management parameter. |
586 | * This parameter can be a value of @ref SPI_Slave_Select_management |
| 587 | * This parameter can be a value of @ref SPI_Slave_Select_management |
587 | * @retval None |
| 588 | * @retval None |
588 | */ |
| 589 | */ |
589 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
| 590 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
590 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
| 591 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
591 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
| 592 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
592 | |
| 593 | 593 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
|
| 594 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
594 | * @param __PRESCALER__ specifies the SPI Baudrate prescaler. |
| 595 | * @param __PRESCALER__ specifies the SPI Baudrate prescaler. |
595 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| 596 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
596 | * @retval None |
| 597 | * @retval None |
597 | */ |
| 598 | */ |
598 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
| 599 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
599 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
| 600 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
600 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
| 601 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
601 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
| 602 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
602 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
| 603 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
603 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
| 604 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
604 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
| 605 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
605 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
| 606 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
606 | |
| 607 | 607 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
|
| 608 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
608 | * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
| 609 | * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
609 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
| 610 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
610 | * @retval None |
| 611 | * @retval None |
611 | */ |
| 612 | */ |
612 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
| 613 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
613 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
| 614 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
614 | |
| 615 | 615 | #if defined(SPI_I2SCFGR_I2SMOD) |
|
| 616 | #if defined(SPI_I2SCFGR_I2SMOD) |
616 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
| 617 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
617 | * @param __MODE__ specifies the SPI TI mode. |
| 618 | * @param __MODE__ specifies the SPI TI mode. |
618 | * This parameter can be a value of @ref SPI_TI_mode |
| 619 | * This parameter can be a value of @ref SPI_TI_mode |
619 | * @retval None |
| 620 | * @retval None |
620 | */ |
| 621 | */ |
621 | #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
| 622 | #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
622 | ((__MODE__) == SPI_TIMODE_ENABLE)) |
| 623 | ((__MODE__) == SPI_TIMODE_ENABLE)) |
623 | #else |
| 624 | #else |
624 | /** @defgroup SPI_TI_mode SPI TI mode disable |
| 625 | /** @defgroup SPI_TI_mode SPI TI mode disable |
625 | * @brief SPI TI Mode not supported for Category 1 and 2 |
| 626 | * @brief SPI TI Mode not supported for Category 1 and 2 |
626 | * @{ |
| 627 | * @{ |
627 | */ |
| 628 | */ |
628 | #define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) |
| 629 | #define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) |
629 | |
| 630 | 630 | #endif /* SPI_I2SCFGR_I2SMOD */ |
|
| 631 | #endif |
631 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
| 632 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
632 | * @param __CALCULATION__ specifies the SPI CRC calculation enable state. |
| 633 | * @param __CALCULATION__ specifies the SPI CRC calculation enable state. |
633 | * This parameter can be a value of @ref SPI_CRC_Calculation |
| 634 | * This parameter can be a value of @ref SPI_CRC_Calculation |
634 | * @retval None |
| 635 | * @retval None |
635 | */ |
| 636 | */ |
636 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
| 637 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
637 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
| 638 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
638 | |
| 639 | 639 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
|
| 640 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
640 | * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. |
| 641 | * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. |
641 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
| 642 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
642 | * @retval None |
| 643 | * @retval None |
643 | */ |
| 644 | */ |
644 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ |
| 645 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ |
645 | ((__POLYNOMIAL__) <= 0xFFFFU) && \ |
| 646 | ((__POLYNOMIAL__) <= 0xFFFFU) && \ |
646 | (((__POLYNOMIAL__)&0x1U) != 0U)) |
| 647 | (((__POLYNOMIAL__)&0x1U) != 0U)) |
647 | |
| 648 | 648 | /** @brief Checks if DMA handle is valid. |
|
| 649 | /** @brief Checks if DMA handle is valid. |
649 | * @param __HANDLE__ specifies a DMA Handle. |
| 650 | * @param __HANDLE__ specifies a DMA Handle. |
650 | * @retval None |
| 651 | * @retval None |
651 | */ |
| 652 | */ |
652 | #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) |
| 653 | #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) |
653 | |
| 654 | 654 | /** |
|
| 655 | /** |
655 | * @} |
| 656 | * @} |
656 | */ |
| 657 | */ |
657 | |
| 658 | 658 | /* Exported functions --------------------------------------------------------*/ |
|
| 659 | /* Exported functions --------------------------------------------------------*/ |
659 | /** @addtogroup SPI_Exported_Functions |
| 660 | /** @addtogroup SPI_Exported_Functions |
660 | * @{ |
| 661 | * @{ |
661 | */ |
| 662 | */ |
662 | |
| 663 | 663 | /** @addtogroup SPI_Exported_Functions_Group1 |
|
| 664 | /** @addtogroup SPI_Exported_Functions_Group1 |
664 | * @{ |
| 665 | * @{ |
665 | */ |
| 666 | */ |
666 | /* Initialization/de-initialization functions ********************************/ |
| 667 | /* Initialization/de-initialization functions ********************************/ |
667 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| 668 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
668 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
| 669 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
669 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| 670 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
670 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| 671 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
671 | |
| 672 | 672 | /* Callbacks Register/UnRegister functions ***********************************/ |
|
| 673 | /* Callbacks Register/UnRegister functions ***********************************/ |
673 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
| 674 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
674 | HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, |
| 675 | HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); |
675 | pSPI_CallbackTypeDef pCallback); |
| 676 | HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); |
676 | HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); |
| 677 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
677 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
| 678 | /** |
678 | /** |
| 679 | * @} |
679 | * @} |
| 680 | */ |
680 | */ |
| 681 | 681 | ||
| 682 | /** @addtogroup SPI_Exported_Functions_Group2 |
682 | /** @addtogroup SPI_Exported_Functions_Group2 |
| 683 | * @{ |
683 | * @{ |
| 684 | */ |
684 | */ |
| 685 | /* I/O operation functions ***************************************************/ |
685 | /* I/O operation functions ***************************************************/ |
| 686 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
686 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| 687 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
687 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| 688 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
688 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
| 689 | uint32_t Timeout); |
689 | uint32_t Timeout); |
| 690 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
690 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| 691 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
691 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| 692 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
692 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
| 693 | uint16_t Size); |
693 | uint16_t Size); |
| 694 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
694 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| 695 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
695 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| 696 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
696 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
| 697 | uint16_t Size); |
697 | uint16_t Size); |
| 698 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
698 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| 699 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
699 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| 700 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
700 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| 701 | /* Transfer Abort functions */ |
701 | /* Transfer Abort functions */ |
| 702 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
702 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
| 703 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
703 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
| 704 | 704 | ||
| 705 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
705 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| 706 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
706 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| 707 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
707 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| 708 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
708 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| 709 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
709 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| 710 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
710 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| 711 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
711 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| 712 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
712 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| 713 | void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
713 | void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
| 714 | /** |
714 | /** |
| 715 | * @} |
715 | * @} |
| 716 | */ |
716 | */ |
| 717 | 717 | ||
| 718 | /** @addtogroup SPI_Exported_Functions_Group3 |
718 | /** @addtogroup SPI_Exported_Functions_Group3 |
| 719 | * @{ |
719 | * @{ |
| 720 | */ |
720 | */ |
| 721 | /* Peripheral State and Error functions ***************************************/ |
721 | /* Peripheral State and Error functions ***************************************/ |
| 722 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
722 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| 723 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
723 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| 724 | /** |
724 | /** |
| 725 | * @} |
725 | * @} |
| 726 | */ |
726 | */ |
| 727 | 727 | ||
| 728 | /** |
728 | /** |
| 729 | * @} |
729 | * @} |
| 730 | */ |
730 | */ |
| 731 | 731 | ||
| 732 | /** |
732 | /** |
| 733 | * @} |
733 | * @} |
| 734 | */ |
734 | */ |
| 735 | 735 | ||
| 736 | /** |
736 | /** |
| 737 | * @} |
737 | * @} |
| 738 | */ |
738 | */ |
| 739 | 739 | ||
| 740 | #ifdef __cplusplus |
740 | #ifdef __cplusplus |
| 741 | } |
741 | } |
| 742 | #endif |
742 | #endif |
| 743 | 743 | ||
| 744 | #endif /* STM32L1xx_HAL_SPI_H */ |
744 | #endif /* STM32L1xx_HAL_SPI_H */ |
| 745 | 745 | ||
| 746 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |