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1 
/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32l1xx_hal_rcc_ex.h
 3 
  * @file    stm32l1xx_hal_rcc_ex.h
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Header file of RCC HAL Extension module.
 5 
  * @brief   Header file of RCC HAL Extension module.
6 
  ******************************************************************************
 6 
  ******************************************************************************
7 
  * @attention
 7 
  * @attention
8 
  *
 8 
  *
9 
  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
 9 
  * Copyright (c) 2017 STMicroelectronics.
10 
  * All rights reserved.</center></h2>
 10 
  * All rights reserved.
11 
  *
 11 
  *
12 
  * This software component is licensed by ST under BSD 3-Clause license,
 12 
  * This software is licensed under terms that can be found in the LICENSE file in
13 
  * the "License"; You may not use this file except in compliance with the
 13 
  * the root directory of this software component.
14 
  * License. You may obtain a copy of the License at:
 14 
  * If no LICENSE file comes with this software, it is provided AS-IS.
15 
  *                        opensource.org/licenses/BSD-3-Clause
 15 
  ******************************************************************************
16 
  *
 16 
  */
17 
  ******************************************************************************
 17 
 
18 
  */
 18 
/* Define to prevent recursive inclusion -------------------------------------*/
19 
 
 19 
#ifndef __STM32L1xx_HAL_RCC_EX_H
20 
/* Define to prevent recursive inclusion -------------------------------------*/
 20 
#define __STM32L1xx_HAL_RCC_EX_H
21 
#ifndef __STM32L1xx_HAL_RCC_EX_H
 21 
 
22 
#define __STM32L1xx_HAL_RCC_EX_H
 22 
#ifdef __cplusplus
23 
 
 23 
 extern "C" {
24 
#ifdef __cplusplus
 24 
#endif
25 
 extern "C" {
 25 
 
26 
#endif
 26 
/* Includes ------------------------------------------------------------------*/
27 
 
 27 
#include "stm32l1xx_hal_def.h"
28 
/* Includes ------------------------------------------------------------------*/
 28 
 
29 
#include "stm32l1xx_hal_def.h"
 29 
/** @addtogroup STM32L1xx_HAL_Driver
30 
 
 30 
  * @{
31 
/** @addtogroup STM32L1xx_HAL_Driver
 31 
  */
32 
  * @{
 32 
 
33 
  */
 33 
/** @addtogroup RCCEx
34 
 
 34 
  * @{
35 
/** @addtogroup RCCEx
 35 
  */
36 
  * @{
 36 
 
37 
  */
 37 
/** @addtogroup RCCEx_Private_Constants
38 
 
 38 
 * @{
39 
/** @addtogroup RCCEx_Private_Constants
 39 
 */
40 
 * @{
 40 
 
41 
 */
 41 
#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
42 
 
 42 
 || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
43 
#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
 43 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
44 
 || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 44 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
45 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 45 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\
46 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 46 
 || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
47 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\
 47 
 
48 
 || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 48 
/* Alias word address of LSECSSON bit */
49 
 
 49 
#define LSECSSON_BITNUMBER      RCC_CSR_LSECSSON_Pos
50 
/* Alias word address of LSECSSON bit */
 50 
#define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))
51 
#define LSECSSON_BITNUMBER      RCC_CSR_LSECSSON_Pos
 51 
 
52 
#define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))
 52 
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
53 
 
 53 
 
54 
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
 54 
/**
55 
 
 55 
  * @}
56 
/**
 56 
  */
57 
  * @}
 57 
 
58 
  */
 58 
/** @addtogroup RCCEx_Private_Macros
59 
 
 59 
  * @{
60 
/** @addtogroup RCCEx_Private_Macros
 60 
  */
61 
  * @{
 61 
#if defined(LCD)
62 
  */
 62 
 
63 
#if defined(LCD)
 63 
#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
64 
 
 64 
 
65 
#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
 65 
#else /* Not LCD LINE */
66 
 
 66 
 
67 
#else /* Not LCD LINE */
 67 
#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
68 
 
 68 
 
69 
#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
 69 
#endif /* LCD */
70 
 
 70 
 
71 
#endif /* LCD */
 71 
/**
72 
 
 72 
  * @}
73 
/**
 73 
  */
74 
  * @}
 74 
 
75 
  */
 75 
/* Exported types ------------------------------------------------------------*/
76 
 
 76 
 
77 
/* Exported types ------------------------------------------------------------*/
 77 
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
78 
 
 78 
  * @{
79 
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
 79 
  */
80 
  * @{
 80 
 
81 
  */
 81 
/**
82 
 
 82 
  * @brief  RCC extended clocks structure definition
83 
/**
 83 
  */
84 
  * @brief  RCC extended clocks structure definition
 84 
typedef struct
85 
  */
 85 
{
86 
typedef struct
 86 
  uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.
87 
{
 87 
                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
88 
  uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.
 88 
 
89 
                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 89 
  uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
90 
 
 90 
                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
91 
  uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
 91 
 
92 
                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
 92 
#if defined(LCD)
93 
 
 93 
 
94 
#if defined(LCD)
 94 
  uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.
95 
 
 95 
                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
96 
  uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.
 96 
 
97 
                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
 97 
#endif /* LCD */
98 
 
 98 
} RCC_PeriphCLKInitTypeDef;
99 
#endif /* LCD */
 99 
 
100 
} RCC_PeriphCLKInitTypeDef;
 100 
/**
101 
 
 101 
  * @}
102 
/**
 102 
  */
103 
  * @}
 103 
 
104 
  */
 104 
/* Exported constants --------------------------------------------------------*/
105 
 
 105 
 
106 
/* Exported constants --------------------------------------------------------*/
 106 
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
107 
 
 107 
  * @{
108 
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
 108 
  */
109 
  * @{
 109 
 
110 
  */
 110 
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
111 
 
 111 
  * @{
112 
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
 112 
  */
113 
  * @{
 113 
#define RCC_PERIPHCLK_RTC           (0x00000001U)
114 
  */
 114 
 
115 
#define RCC_PERIPHCLK_RTC           (0x00000001U)
 115 
#if defined(LCD)
116 
 
 116 
 
117 
#if defined(LCD)
 117 
#define RCC_PERIPHCLK_LCD           (0x00000002U)
118 
 
 118 
 
119 
#define RCC_PERIPHCLK_LCD           (0x00000002U)
 119 
#endif /* LCD */
120 
 
 120 
 
121 
#endif /* LCD */
 121 
/**
122 
 
 122 
  * @}
123 
/**
 123 
  */
124 
  * @}
 124 
 
125 
  */
 125 
#if defined(RCC_LSECSS_SUPPORT)
126 
 
 126 
/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
127 
#if defined(RCC_LSECSS_SUPPORT)
 127 
  * @{
128 
/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
 128 
  */
129 
  * @{
 129 
#define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
130 
  */
 130 
/**
131 
#define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
 131 
  * @}
132 
/**
 132 
  */
133 
  * @}
 133 
#endif /* RCC_LSECSS_SUPPORT */
134 
  */
 134 
 
135 
#endif /* RCC_LSECSS_SUPPORT */
 135 
/**
136 
 
 136 
  * @}
137 
/**
 137 
  */
138 
  * @}
 138 
 
139 
  */
 139 
/* Exported macro ------------------------------------------------------------*/
140 
 
 140 
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
141 
/* Exported macro ------------------------------------------------------------*/
 141 
 * @{
142 
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
 142 
 */
143 
 * @{
 143 
 
144 
 */
 144 
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
145 
 
 145 
  * @brief  Enables or disables the AHB1 peripheral clock.
146 
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
 146 
  * @note   After reset, the peripheral clock (used for registers read/write access)
147 
  * @brief  Enables or disables the AHB1 peripheral clock.
 147 
  *         is disabled and the application software has to enable this clock before
148 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 148 
  *         using it.
149 
  *         is disabled and the application software has to enable this clock before
 149 
  * @{
150 
  *         using it.
 150 
  */
151 
  * @{
 151 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
152 
  */
 152 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
153 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
 153 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
154 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
 154 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
155 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 155 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
156 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 156 
 || defined(STM32L162xE) || defined(STM32L162xDX)
157 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 157 
 
158 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 158 
#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
159 
 
 159 
                                        __IO uint32_t tmpreg; \
160 
#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
 160 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
161 
                                        __IO uint32_t tmpreg; \
 161 
                                        /* Delay after an RCC peripheral clock enabling */ \
162 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
 162 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
163 
                                        /* Delay after an RCC peripheral clock enabling */ \
 163 
                                        UNUSED(tmpreg); \
164 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
 164 
                                      } while(0U)
165 
                                        UNUSED(tmpreg); \
 165 
#define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
166 
                                      } while(0U)
 166 
 
167 
#define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
 167 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
168 
 
 168 
 
169 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 169 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
170 
 
 170 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
171 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 171 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
172 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 172 
 
173 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 173 
#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
174 
 
 174 
                                        __IO uint32_t tmpreg; \
175 
#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
 175 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
176 
                                        __IO uint32_t tmpreg; \
 176 
                                        /* Delay after an RCC peripheral clock enabling */ \
177 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
 177 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
178 
                                        /* Delay after an RCC peripheral clock enabling */ \
 178 
                                        UNUSED(tmpreg); \
179 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
 179 
                                      } while(0U)
180 
                                        UNUSED(tmpreg); \
 180 
#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
181 
                                      } while(0U)
 181 
                                        __IO uint32_t tmpreg; \
182 
#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
 182 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
183 
                                        __IO uint32_t tmpreg; \
 183 
                                        /* Delay after an RCC peripheral clock enabling */ \
184 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
 184 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
185 
                                        /* Delay after an RCC peripheral clock enabling */ \
 185 
                                        UNUSED(tmpreg); \
186 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
 186 
                                      } while(0U)
187 
                                        UNUSED(tmpreg); \
 187 
 
188 
                                      } while(0U)
 188 
#define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
189 
 
 189 
#define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
190 
#define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
 190 
 
191 
#define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
 191 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
192 
 
 192 
 
193 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 193 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
194 
 
 194 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
195 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 195 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
196 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 196 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
197 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 197 
 || defined(STM32L162xE) || defined(STM32L162xDX)
198 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 198 
 
199 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 199 
#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
200 
 
 200 
                                        __IO uint32_t tmpreg; \
201 
#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
 201 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
202 
                                        __IO uint32_t tmpreg; \
 202 
                                        /* Delay after an RCC peripheral clock enabling */ \
203 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
 203 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
204 
                                        /* Delay after an RCC peripheral clock enabling */ \
 204 
                                        UNUSED(tmpreg); \
205 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
 205 
                                      } while(0U)
206 
                                        UNUSED(tmpreg); \
 206 
 
207 
                                      } while(0U)
 207 
#define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
208 
 
 208 
 
209 
#define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
 209 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
210 
 
 210 
 
211 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 211 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
212 
 
 212 
 || defined(STM32L162xE) || defined(STM32L162xDX)
213 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
 213 
 
214 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 214 
#define __HAL_RCC_AES_CLK_ENABLE()    do { \
215 
 
 215 
                                        __IO uint32_t tmpreg; \
216 
#define __HAL_RCC_AES_CLK_ENABLE()    do { \
 216 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
217 
                                        __IO uint32_t tmpreg; \
 217 
                                        /* Delay after an RCC peripheral clock enabling */ \
218 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
 218 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
219 
                                        /* Delay after an RCC peripheral clock enabling */ \
 219 
                                        UNUSED(tmpreg); \
220 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
 220 
                                      } while(0U)
221 
                                        UNUSED(tmpreg); \
 221 
#define __HAL_RCC_AES_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
222 
                                      } while(0U)
 222 
 
223 
#define __HAL_RCC_AES_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
 223 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
224 
 
 224 
 
225 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
 225 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
226 
 
 226 
 
227 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 227 
#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
228 
 
 228 
                                        __IO uint32_t tmpreg; \
229 
#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
 229 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
230 
                                        __IO uint32_t tmpreg; \
 230 
                                        /* Delay after an RCC peripheral clock enabling */ \
231 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
 231 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
232 
                                        /* Delay after an RCC peripheral clock enabling */ \
 232 
                                        UNUSED(tmpreg); \
233 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
 233 
                                      } while(0U)
234 
                                        UNUSED(tmpreg); \
 234 
#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
235 
                                      } while(0U)
 235 
 
236 
#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
 236 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
237 
 
 237 
 
238 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 238 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
239 
 
 239 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
240 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
 240 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
241 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
 241 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
242 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
 242 
 || defined(STM32L162xE) || defined(STM32L162xDX)
243 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
 243 
 
244 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 244 
#define __HAL_RCC_LCD_CLK_ENABLE()   do { \
245 
 
 245 
                                        __IO uint32_t tmpreg; \
246 
#define __HAL_RCC_LCD_CLK_ENABLE()   do { \
 246 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
247 
                                        __IO uint32_t tmpreg; \
 247 
                                        /* Delay after an RCC peripheral clock enabling */ \
248 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
 248 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
249 
                                        /* Delay after an RCC peripheral clock enabling */ \
 249 
                                        UNUSED(tmpreg); \
250 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
 250 
                                      } while(0U)
251 
                                        UNUSED(tmpreg); \
 251 
#define __HAL_RCC_LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
252 
                                      } while(0U)
 252 
 
253 
#define __HAL_RCC_LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
 253 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
254 
 
 254 
 
255 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 255 
/** @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
256 
 
 256 
  * @note   After reset, the peripheral clock (used for registers read/write access)
257 
/** @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
 257 
  *         is disabled and the application software has to enable this clock before
258 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 258 
  *         using it.
259 
  *         is disabled and the application software has to enable this clock before
 259 
  */
260 
  *         using it.
 260 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
261 
  */
 261 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
262 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
 262 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
263 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 263 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
264 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 264 
 
265 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 265 
#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
266 
 
 266 
                                        __IO uint32_t tmpreg; \
267 
#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
 267 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
268 
                                        __IO uint32_t tmpreg; \
 268 
                                        /* Delay after an RCC peripheral clock enabling */ \
269 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
 269 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
270 
                                        /* Delay after an RCC peripheral clock enabling */ \
 270 
                                        UNUSED(tmpreg); \
271 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
 271 
                                      } while(0U)
272 
                                        UNUSED(tmpreg); \
 272 
#define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
273 
                                      } while(0U)
 273 
 
274 
#define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 274 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
275 
 
 275 
 
276 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 276 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
277 
 
 277 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
278 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 278 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
279 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 279 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
280 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 280 
 || defined(STM32L162xE) || defined(STM32L162xDX)
281 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 281 
 
282 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 282 
#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
283 
 
 283 
                                        __IO uint32_t tmpreg; \
284 
#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
 284 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
285 
                                        __IO uint32_t tmpreg; \
 285 
                                        /* Delay after an RCC peripheral clock enabling */ \
286 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
 286 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
287 
                                        /* Delay after an RCC peripheral clock enabling */ \
 287 
                                        UNUSED(tmpreg); \
288 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
 288 
                                      } while(0U)
289 
                                        UNUSED(tmpreg); \
 289 
#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
290 
                                      } while(0U)
 290 
 
291 
#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
 291 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
292 
 
 292 
 
293 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 293 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
294 
 
 294 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
295 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
 295 
 
296 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 296 
#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
297 
 
 297 
                                        __IO uint32_t tmpreg; \
298 
#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
 298 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
299 
                                        __IO uint32_t tmpreg; \
 299 
                                        /* Delay after an RCC peripheral clock enabling */ \
300 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
 300 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
301 
                                        /* Delay after an RCC peripheral clock enabling */ \
 301 
                                        UNUSED(tmpreg); \
302 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
 302 
                                      } while(0U)
303 
                                        UNUSED(tmpreg); \
 303 
#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
304 
                                      } while(0U)
 304 
                                        __IO uint32_t tmpreg; \
305 
#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
 305 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
306 
                                        __IO uint32_t tmpreg; \
 306 
                                        /* Delay after an RCC peripheral clock enabling */ \
307 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
 307 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
308 
                                        /* Delay after an RCC peripheral clock enabling */ \
 308 
                                        UNUSED(tmpreg); \
309 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
 309 
                                      } while(0U)
310 
                                        UNUSED(tmpreg); \
 310 
 
311 
                                      } while(0U)
 311 
#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
312 
 
 312 
#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
313 
#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 313 
 
314 
#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 314 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */
315 
 
 315 
 
316 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */
 316 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
317 
 
 317 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
318 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 318 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\
319 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 319 
 || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
320 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\
 320 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
321 
 || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
 321 
 
322 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
 322 
#define __HAL_RCC_OPAMP_CLK_ENABLE()      __HAL_RCC_COMP_CLK_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
323 
 
 323 
#define __HAL_RCC_OPAMP_CLK_DISABLE()     __HAL_RCC_COMP_CLK_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
324 
#define __HAL_RCC_OPAMP_CLK_ENABLE()      __HAL_RCC_COMP_CLK_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
 324 
 
325 
#define __HAL_RCC_OPAMP_CLK_DISABLE()     __HAL_RCC_COMP_CLK_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
 325 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */
326 
 
 326 
 
327 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */
 327 
/** @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
328 
 
 328 
  * @note   After reset, the peripheral clock (used for registers read/write access)
329 
/** @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
 329 
  *         is disabled and the application software has to enable this clock before
330 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 330 
  *         using it.
331 
  *         is disabled and the application software has to enable this clock before
 331 
  */
332 
  *         using it.
 332 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
333 
  */
 333 
 
334 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 334 
#define __HAL_RCC_SDIO_CLK_ENABLE()   do { \
335 
 
 335 
                                        __IO uint32_t tmpreg; \
336 
#define __HAL_RCC_SDIO_CLK_ENABLE()   do { \
 336 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
337 
                                        __IO uint32_t tmpreg; \
 337 
                                        /* Delay after an RCC peripheral clock enabling */ \
338 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
 338 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
339 
                                        /* Delay after an RCC peripheral clock enabling */ \
 339 
                                        UNUSED(tmpreg); \
340 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
 340 
                                      } while(0U)
341 
                                        UNUSED(tmpreg); \
 341 
#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
342 
                                      } while(0U)
 342 
 
343 
#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
 343 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
344 
 
 344 
 
345 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 345 
/**
346 
 
 346 
    * @}
347 
/**
 347 
    */
348 
    * @}
 348 
 
349 
    */
 349 
 
350 
 
 350 
/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
351 
 
 351 
  * @brief  Forces or releases AHB peripheral reset.
352 
/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
 352 
  * @{
353 
  * @brief  Forces or releases AHB peripheral reset.
 353 
  */
354 
  * @{
 354 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
355 
  */
 355 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
356 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
 356 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
357 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
 357 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
358 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 358 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
359 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 359 
 || defined(STM32L162xE) || defined(STM32L162xDX)
360 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 360 
 
361 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 361 
#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
362 
 
 362 
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
363 
#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
 363 
 
364 
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
 364 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
365 
 
 365 
 
366 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 366 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
367 
 
 367 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
368 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 368 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
369 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 369 
 
370 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 370 
#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
371 
 
 371 
#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
372 
#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
 372 
 
373 
#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
 373 
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
374 
 
 374 
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
375 
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
 375 
 
376 
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
 376 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
377 
 
 377 
 
378 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 378 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
379 
 
 379 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
380 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 380 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
381 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 381 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
382 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 382 
 || defined(STM32L162xE) || defined(STM32L162xDX)
383 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 383 
 
384 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 384 
#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
385 
 
 385 
#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
386 
#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
 386 
 
387 
#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
 387 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
388 
 
 388 
 
389 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 389 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
390 
 
 390 
 || defined(STM32L162xE) || defined(STM32L162xDX)
391 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
 391 
 
392 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 392 
#define __HAL_RCC_AES_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
393 
 
 393 
#define __HAL_RCC_AES_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
394 
#define __HAL_RCC_AES_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
 394 
 
395 
#define __HAL_RCC_AES_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
 395 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
396 
 
 396 
 
397 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
 397 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
398 
 
 398 
 
399 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 399 
#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
400 
 
 400 
#define __HAL_RCC_FSMC_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
401 
#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
 401 
 
402 
#define __HAL_RCC_FSMC_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
 402 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
403 
 
 403 
 
404 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 404 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
405 
 
 405 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
406 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
 406 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
407 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
 407 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
408 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
 408 
 || defined(STM32L162xE) || defined(STM32L162xDX)
409 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
 409 
 
410 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 410 
#define __HAL_RCC_LCD_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
411 
 
 411 
#define __HAL_RCC_LCD_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
412 
#define __HAL_RCC_LCD_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
 412 
 
413 
#define __HAL_RCC_LCD_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
 413 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
414 
 
 414 
 
415 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 415 
/** @brief  Forces or releases APB1 peripheral reset.
416 
 
 416 
  */
417 
/** @brief  Forces or releases APB1 peripheral reset.
 417 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
418 
  */
 418 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
419 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
 419 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
420 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 420 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
421 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 421 
 
422 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 422 
#define __HAL_RCC_TIM5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
423 
 
 423 
#define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
424 
#define __HAL_RCC_TIM5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
 424 
 
425 
#define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
 425 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
426 
 
 426 
 
427 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 427 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
428 
 
 428 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
429 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 429 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
430 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 430 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
431 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 431 
 || defined(STM32L162xE) || defined(STM32L162xDX)
432 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 432 
 
433 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 433 
#define __HAL_RCC_SPI3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
434 
 
 434 
#define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
435 
#define __HAL_RCC_SPI3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
 435 
 
436 
#define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
 436 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
437 
 
 437 
 
438 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 438 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
439 
 
 439 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
440 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
 440 
 
441 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 441 
#define __HAL_RCC_UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
442 
 
 442 
#define __HAL_RCC_UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
443 
#define __HAL_RCC_UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
 443 
 
444 
#define __HAL_RCC_UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
 444 
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
445 
 
 445 
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
446 
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
 446 
 
447 
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
 447 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
448 
 
 448 
 
449 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 449 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
450 
 
 450 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
451 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 451 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
452 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 452 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
453 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
 453 
 
454 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
 454 
#define __HAL_RCC_OPAMP_FORCE_RESET()     __HAL_RCC_COMP_FORCE_RESET()   /* Peripherals COMP and OPAMP share the same clock domain */
455 
 
 455 
#define __HAL_RCC_OPAMP_RELEASE_RESET()   __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
456 
#define __HAL_RCC_OPAMP_FORCE_RESET()     __HAL_RCC_COMP_FORCE_RESET()   /* Peripherals COMP and OPAMP share the same clock domain */
 456 
 
457 
#define __HAL_RCC_OPAMP_RELEASE_RESET()   __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
 457 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
458 
 
 458 
 
459 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
 459 
/** @brief  Forces or releases APB2 peripheral reset.
460 
 
 460 
  */
461 
/** @brief  Forces or releases APB2 peripheral reset.
 461 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
462 
  */
 462 
 
463 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 463 
#define __HAL_RCC_SDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
464 
 
 464 
#define __HAL_RCC_SDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
465 
#define __HAL_RCC_SDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
 465 
 
466 
#define __HAL_RCC_SDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
 466 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
467 
 
 467 
 
468 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 468 
/**
469 
 
 469 
  * @}
470 
/**
 470 
  */
471 
  * @}
 471 
 
472 
  */
 472 
/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
473 
 
 473 
  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
474 
/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
 474 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
475 
  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
 475 
  *         power consumption.
476 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 476 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
477 
  *         power consumption.
 477 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
478 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 478 
  * @{
479 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 479 
  */
480 
  * @{
 480 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
481 
  */
 481 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
482 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
 482 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
483 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
 483 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
484 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 484 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
485 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 485 
 || defined(STM32L162xE) || defined(STM32L162xDX)
486 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 486 
 
487 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 487 
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
488 
 
 488 
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
489 
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
 489 
 
490 
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
 490 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
491 
 
 491 
 
492 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 492 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
493 
 
 493 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
494 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 494 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
495 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 495 
 
496 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 496 
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
497 
 
 497 
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
498 
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
 498 
 
499 
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
 499 
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
500 
 
 500 
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
501 
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
 501 
 
502 
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
 502 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
503 
 
 503 
 
504 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 504 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
505 
 
 505 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
506 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 506 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
507 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 507 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
508 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 508 
 || defined(STM32L162xE) || defined(STM32L162xDX)
509 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 509 
 
510 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 510 
#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
511 
 
 511 
#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
512 
#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
 512 
 
513 
#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
 513 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
514 
 
 514 
 
515 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 515 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
516 
 
 516 
 
517 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
 517 
#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
518 
 
 518 
#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
519 
#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
 519 
 
520 
#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
 520 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
521 
 
 521 
 
522 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
 522 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
523 
 
 523 
 
524 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 524 
#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
525 
 
 525 
#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
526 
#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
 526 
 
527 
#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
 527 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
528 
 
 528 
 
529 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 529 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
530 
 
 530 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
531 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
 531 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
532 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
 532 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
533 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
 533 
 || defined(STM32L162xE) || defined(STM32L162xDX)
534 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
 534 
 
535 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 535 
#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
536 
 
 536 
#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
537 
#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
 537 
 
538 
#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
 538 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
539 
 
 539 
 
540 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 540 
/** @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
541 
 
 541 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
542 
/** @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
 542 
  *           power consumption.
543 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 543 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
544 
  *           power consumption.
 544 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
545 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 545 
  */
546 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 546 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
547 
  */
 547 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
548 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
 548 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
549 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 549 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
550 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 550 
 
551 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 551 
#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
552 
 
 552 
#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
553 
#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
 553 
 
554 
#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
 554 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
555 
 
 555 
 
556 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 556 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
557 
 
 557 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
558 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 558 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
559 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 559 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
560 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 560 
 || defined(STM32L162xE) || defined(STM32L162xDX)
561 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 561 
 
562 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 562 
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
563 
 
 563 
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
564 
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
 564 
 
565 
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
 565 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
566 
 
 566 
 
567 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 567 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
568 
 
 568 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
569 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
 569 
 
570 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 570 
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
571 
 
 571 
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
572 
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
 572 
 
573 
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
 573 
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
574 
 
 574 
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
575 
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
 575 
 
576 
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
 576 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
577 
 
 577 
 
578 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 578 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
579 
 
 579 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
580 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 580 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
581 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 581 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
582 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
 582 
 
583 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
 583 
#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()      __HAL_RCC_COMP_CLK_SLEEP_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
584 
 
 584 
#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()     __HAL_RCC_COMP_CLK_SLEEP_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
585 
#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()      __HAL_RCC_COMP_CLK_SLEEP_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
 585 
 
586 
#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()     __HAL_RCC_COMP_CLK_SLEEP_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
 586 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
587 
 
 587 
 
588 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
 588 
/** @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
589 
 
 589 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
590 
/** @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
 590 
  *           power consumption.
591 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 591 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
592 
  *           power consumption.
 592 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
593 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 593 
  */
594 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 594 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
595 
  */
 595 
 
596 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 596 
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
597 
 
 597 
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
598 
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
 598 
 
599 
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
 599 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
600 
 
 600 
 
601 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 601 
/**
602 
 
 602 
  * @}
603 
/**
 603 
  */
604 
  * @}
 604 
 
605 
  */
 605 
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
606 
 
 606 
  * @brief  Get the enable or disable status of peripheral clock.
607 
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
 607 
  * @note   After reset, the peripheral clock (used for registers read/write access)
608 
  * @brief  Get the enable or disable status of peripheral clock.
 608 
  *         is disabled and the application software has to enable this clock before
609 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 609 
  *         using it.
610 
  *         is disabled and the application software has to enable this clock before
 610 
  * @{
611 
  *         using it.
 611 
  */
612 
  * @{
 612 
 
613 
  */
 613 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
614 
 
 614 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
615 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
 615 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
616 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
 616 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
617 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 617 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
618 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 618 
 || defined(STM32L162xE) || defined(STM32L162xDX)
619 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 619 
 
620 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 620 
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U)
621 
 
 621 
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U)
622 
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U)
 622 
 
623 
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U)
 623 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
624 
 
 624 
 
625 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 625 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
626 
 
 626 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
627 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 627 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
628 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 628 
 
629 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 629 
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U)
630 
 
 630 
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U)
631 
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U)
 631 
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U)
632 
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U)
 632 
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U)
633 
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U)
 633 
 
634 
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U)
 634 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
635 
 
 635 
 
636 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 636 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
637 
 
 637 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
638 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 638 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
639 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 639 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
640 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 640 
 || defined(STM32L162xE) || defined(STM32L162xDX)
641 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 641 
 
642 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 642 
#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)
643 
 
 643 
#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)
644 
#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)
 644 
 
645 
#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)
 645 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
646 
 
 646 
 
647 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 647 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
648 
 
 648 
 || defined(STM32L162xE) || defined(STM32L162xDX)
649 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
 649 
 
650 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 650 
#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U)
651 
 
 651 
#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U)
652 
#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U)
 652 
 
653 
#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U)
 653 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
654 
 
 654 
 
655 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
 655 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
656 
 
 656 
 
657 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 657 
#define __HAL_RCC_FSMC_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U)
658 
 
 658 
#define __HAL_RCC_FSMC_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U)
659 
#define __HAL_RCC_FSMC_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U)
 659 
 
660 
#define __HAL_RCC_FSMC_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U)
 660 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
661 
 
 661 
 
662 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 662 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
663 
 
 663 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
664 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
 664 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
665 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
 665 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
666 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
 666 
 || defined(STM32L162xE) || defined(STM32L162xDX)
667 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
 667 
 
668 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 668 
#define __HAL_RCC_LCD_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U)
669 
 
 669 
#define __HAL_RCC_LCD_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U)
670 
#define __HAL_RCC_LCD_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U)
 670 
 
671 
#define __HAL_RCC_LCD_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U)
 671 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
672 
 
 672 
 
673 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 673 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
674 
 
 674 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
675 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
 675 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
676 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 676 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
677 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 677 
 
678 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 678 
#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)
679 
 
 679 
#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)
680 
#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)
 680 
 
681 
#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)
 681 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
682 
 
 682 
 
683 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 683 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
684 
 
 684 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
685 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 685 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
686 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 686 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
687 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 687 
 || defined(STM32L162xE) || defined(STM32L162xDX)
688 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 688 
 
689 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 689 
#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)
690 
 
 690 
#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)
691 
#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)
 691 
 
692 
#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)
 692 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
693 
 
 693 
 
694 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 694 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
695 
 
 695 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
696 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
 696 
 
697 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 697 
#define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U)
698 
 
 698 
#define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U)
699 
#define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U)
 699 
#define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U)
700 
#define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U)
 700 
#define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U)
701 
#define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U)
 701 
 
702 
#define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U)
 702 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
703 
 
 703 
 
704 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 704 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
705 
 
 705 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
706 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 706 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
707 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 707 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
708 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
 708 
 
709 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
 709 
#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       __HAL_RCC_COMP_IS_CLK_ENABLED()
710 
 
 710 
#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      __HAL_RCC_COMP_IS_CLK_DISABLED()
711 
#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       __HAL_RCC_COMP_IS_CLK_ENABLED()
 711 
 
712 
#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      __HAL_RCC_COMP_IS_CLK_DISABLED()
 712 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
713 
 
 713 
 
714 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
 714 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
715 
 
 715 
 
716 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 716 
#define __HAL_RCC_SDIO_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U)
717 
 
 717 
#define __HAL_RCC_SDIO_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U)
718 
#define __HAL_RCC_SDIO_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U)
 718 
 
719 
#define __HAL_RCC_SDIO_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U)
 719 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
720 
 
 720 
 
721 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 721 
/**
722 
 
 722 
  * @}
723 
/**
 723 
  */
724 
  * @}
 724 
 
725 
  */
 725 
/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status
726 
 
 726 
  * @brief  Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.
727 
/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status
 727 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
728 
  * @brief  Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.
 728 
  *         power consumption.
729 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 729 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
730 
  *         power consumption.
 730 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
731 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 731 
  * @{
732 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 732 
  */
733 
  * @{
 733 
 
734 
  */
 734 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
735 
 
 735 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
736 
#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
 736 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
737 
 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
 737 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
738 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 738 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
739 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 739 
 || defined(STM32L162xE) || defined(STM32L162xDX)
740 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 740 
 
741 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 741 
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U)
742 
 
 742 
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U)
743 
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U)
 743 
 
744 
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U)
 744 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
745 
 
 745 
 
746 
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 746 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
747 
 
 747 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
748 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 748 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
749 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 749 
 
750 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 750 
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U)
751 
 
 751 
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U)
752 
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U)
 752 
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U)
753 
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U)
 753 
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U)
754 
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U)
 754 
 
755 
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U)
 755 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
756 
 
 756 
 
757 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 757 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
758 
 
 758 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
759 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 759 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
760 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 760 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
761 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 761 
 || defined(STM32L162xE) || defined(STM32L162xDX)
762 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 762 
 
763 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 763 
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U)
764 
 
 764 
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U)
765 
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U)
 765 
 
766 
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U)
 766 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
767 
 
 767 
 
768 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 768 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
769 
 
 769 
 || defined(STM32L162xE) || defined(STM32L162xDX)
770 
#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
 770 
 
771 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 771 
#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U)
772 
 
 772 
#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U)
773 
#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U)
 773 
 
774 
#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U)
 774 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
775 
 
 775 
 
776 
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
 776 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
777 
 
 777 
 
778 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 778 
#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U)
779 
 
 779 
#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U)
780 
#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U)
 780 
 
781 
#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U)
 781 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
782 
 
 782 
 
783 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 783 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
784 
 
 784 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
785 
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
 785 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
786 
 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
 786 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
787 
 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
 787 
 || defined(STM32L162xE) || defined(STM32L162xDX)
788 
 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
 788 
 
789 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 789 
#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U)
790 
 
 790 
#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U)
791 
#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U)
 791 
 
792 
#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U)
 792 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
793 
 
 793 
 
794 
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 794 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
795 
 
 795 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
796 
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
 796 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
797 
 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 797 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
798 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 798 
 
799 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 799 
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U)
800 
 
 800 
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U)
801 
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U)
 801 
 
802 
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U)
 802 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
803 
 
 803 
 
804 
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 804 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
805 
 
 805 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
806 
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
 806 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
807 
 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
 807 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
808 
 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
 808 
 || defined(STM32L162xE) || defined(STM32L162xDX)
809 
 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
 809 
 
810 
 || defined(STM32L162xE) || defined(STM32L162xDX)
 810 
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U)
811 
 
 811 
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U)
812 
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U)
 812 
 
813 
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U)
 813 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
814 
 
 814 
 
815 
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 815 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
816 
 
 816 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
817 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
 817 
 
818 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
 818 
#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U)
819 
 
 819 
#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U)
820 
#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U)
 820 
#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U)
821 
#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U)
 821 
#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U)
822 
#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U)
 822 
 
823 
#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U)
 823 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
824 
 
 824 
 
825 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 825 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
826 
 
 826 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
827 
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
 827 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
828 
 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
 828 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
829 
 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
 829 
 
830 
 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
 830 
#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()       __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()
831 
 
 831 
#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()      __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()
832 
#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()       __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()
 832 
 
833 
#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()      __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()
 833 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
834 
 
 834 
 
835 
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
 835 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
836 
 
 836 
 
837 
#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
 837 
#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U)
838 
 
 838 
#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U)
839 
#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U)
 839 
 
840 
#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U)
 840 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
841 
 
 841 
 
842 
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 842 
/**
843 
 
 843 
  * @}
844 
/**
 844 
  */
845 
  * @}
 845 
 
846 
  */
 846 
 
847 
 
 847 
#if defined(RCC_LSECSS_SUPPORT)
848 
 
 848 
 
849 
#if defined(RCC_LSECSS_SUPPORT)
 849 
/**
850 
 
 850 
  * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
851 
/**
 851 
  * @retval None
852 
  * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
 852 
  */
853 
  * @retval None
 853 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
854 
  */
 854 
 
855 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
 855 
/**
856 
 
 856 
  * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
857 
/**
 857 
  * @retval None
858 
  * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
 858 
  */
859 
  * @retval None
 859 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
860 
  */
 860 
 
861 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
 861 
/**
862 
 
 862 
  * @brief Enable event on RCC LSE CSS EXTI Line 19.
863 
/**
 863 
  * @retval None.
864 
  * @brief Enable event on RCC LSE CSS EXTI Line 19.
 864 
  */
865 
  * @retval None.
 865 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
866 
  */
 866 
 
867 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
 867 
/**
868 
 
 868 
  * @brief Disable event on RCC LSE CSS EXTI Line 19.
869 
/**
 869 
  * @retval None.
870 
  * @brief Disable event on RCC LSE CSS EXTI Line 19.
 870 
  */
871 
  * @retval None.
 871 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
872 
  */
 872 
 
873 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
 873 
 
874 
 
 874 
/**
875 
 
 875 
  * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.
876 
/**
 876 
  * @retval None.
877 
  * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.
 877 
  */
878 
  * @retval None.
 878 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
879 
  */
 879 
 
880 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
 880 
 
881 
 
 881 
/**
882 
 
 882 
  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
883 
/**
 883 
  * @retval None.
884 
  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
 884 
  */
885 
  * @retval None.
 885 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
886 
  */
 886 
 
887 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
 887 
 
888 
 
 888 
/**
889 
 
 889 
  * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.
890 
/**
 890 
  * @retval None.
891 
  * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.
 891 
  */
892 
  * @retval None.
 892 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
893 
  */
 893 
 
894 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
 894 
/**
895 
 
 895 
  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
896 
/**
 896 
  * @retval None.
897 
  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
 897 
  */
898 
  * @retval None.
 898 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
899 
  */
 899 
 
900 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
 900 
/**
901 
 
 901 
  * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
902 
/**
 902 
  * @retval None.
903 
  * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
 903 
  */
904 
  * @retval None.
 904 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
905 
  */
 905 
  do {                                                      \
906 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
 906 
    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
907 
  do {                                                      \
 907 
    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
908 
    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
 908 
  } while(0U)
909 
    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
 909 
 
910 
  } while(0U)
 910 
/**
911 
 
 911 
  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
912 
/**
 912 
  * @retval None.
913 
  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
 913 
  */
914 
  * @retval None.
 914 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
915 
  */
 915 
  do {                                                       \
916 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
 916 
    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
917 
  do {                                                       \
 917 
    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
918 
    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
 918 
  } while(0U)
919 
    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
 919 
 
920 
  } while(0U)
 920 
/**
921 
 
 921 
  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
922 
/**
 922 
  * @retval EXTI RCC LSE CSS Line Status.
923 
  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
 923 
  */
924 
  * @retval EXTI RCC LSE CSS Line Status.
 924 
#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
925 
  */
 925 
 
926 
#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
 926 
/**
927 
 
 927 
  * @brief Clear the RCC LSE CSS EXTI flag.
928 
/**
 928 
  * @retval None.
929 
  * @brief Clear the RCC LSE CSS EXTI flag.
 929 
  */
930 
  * @retval None.
 930 
#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
931 
  */
 931 
 
932 
#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
 932 
/**
933 
 
 933 
  * @brief Generate a Software interrupt on selected EXTI line.
934 
/**
 934 
  * @retval None.
935 
  * @brief Generate a Software interrupt on selected EXTI line.
 935 
  */
936 
  * @retval None.
 936 
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
937 
  */
 937 
 
938 
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
 938 
#endif /* RCC_LSECSS_SUPPORT */
939 
 
 939 
 
940 
#endif /* RCC_LSECSS_SUPPORT */
 940 
#if defined(LCD)
941 
 
 941 
 
942 
#if defined(LCD)
 942 
/** @defgroup RCCEx_LCD_Configuration LCD Configuration
943 
 
 943 
  * @brief  Macros to configure clock source of LCD peripherals.
944 
/** @defgroup RCCEx_LCD_Configuration LCD Configuration
 944 
  * @{
945 
  * @brief  Macros to configure clock source of LCD peripherals.
 945 
  */
946 
  * @{
 946 
 
947 
  */
 947 
/** @brief Macro to configures LCD clock (LCDCLK).
948 
 
 948 
  *  @note   LCD and RTC use the same configuration
949 
/** @brief Macro to configures LCD clock (LCDCLK).
 949 
  *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
950 
  *  @note   LCD and RTC use the same configuration
 950 
  *          LCD clock source.
951 
  *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
 951 
  *
952 
  *          LCD clock source.
 952 
  *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.
953 
  *
 953 
  *          This parameter can be one of the following values:
954 
  *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.
 954 
  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
955 
  *          This parameter can be one of the following values:
 955 
  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
956 
  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
 956 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
957 
  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
 957 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
958 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
 958 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
959 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
 959 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
960 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
 960 
  */
961 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
 961 
#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
962 
  */
 962 
 
963 
#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
 963 
/** @brief Macro to get the LCD clock source.
964 
 
 964 
  */
965 
/** @brief Macro to get the LCD clock source.
 965 
#define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
966 
  */
 966 
 
967 
#define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
 967 
/** @brief Macro to get the LCD clock pre-scaler.
968 
 
 968 
  */
969 
/** @brief Macro to get the LCD clock pre-scaler.
 969 
#define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()
970 
  */
 970 
 
971 
#define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()
 971 
/**
972 
 
 972 
  * @}
973 
/**
 973 
  */
974 
  * @}
 974 
 
975 
  */
 975 
#endif /* LCD */
976 
 
 976 
 
977 
#endif /* LCD */
 977 
 
978 
 
 978 
/**
979 
 
 979 
  * @}
980 
/**
 980 
  */
981 
  * @}
 981 
 
982 
  */
 982 
/* Exported functions --------------------------------------------------------*/
983 
 
 983 
/** @addtogroup RCCEx_Exported_Functions
984 
/* Exported functions --------------------------------------------------------*/
 984 
  * @{
985 
/** @addtogroup RCCEx_Exported_Functions
 985 
  */
986 
  * @{
 986 
 
987 
  */
 987 
/** @addtogroup RCCEx_Exported_Functions_Group1
988 
 
 988 
  * @{
989 
/** @addtogroup RCCEx_Exported_Functions_Group1
 989 
  */
990 
  * @{
 990 
 
991 
  */
 991 
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
992 
 
 992 
void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
993 
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
 993 
uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
994 
void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
 994 
 
995 
uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
 995 
#if defined(RCC_LSECSS_SUPPORT)
996 
 
 996 
 
997 
#if defined(RCC_LSECSS_SUPPORT)
 997 
void              HAL_RCCEx_EnableLSECSS(void);
998 
 
 998 
void              HAL_RCCEx_DisableLSECSS(void);
999 
void              HAL_RCCEx_EnableLSECSS(void);
 999 
void              HAL_RCCEx_EnableLSECSS_IT(void);
1000 
void              HAL_RCCEx_DisableLSECSS(void);
 1000 
void              HAL_RCCEx_LSECSS_IRQHandler(void);
1001 
void              HAL_RCCEx_EnableLSECSS_IT(void);
 1001 
void              HAL_RCCEx_LSECSS_Callback(void);
1002 
void              HAL_RCCEx_LSECSS_IRQHandler(void);
 1002 
 
1003 
void              HAL_RCCEx_LSECSS_Callback(void);
 1003 
#endif /* RCC_LSECSS_SUPPORT */
1004 
 
 1004 
 
1005 
#endif /* RCC_LSECSS_SUPPORT */
 1005 
/**
1006 
 
 1006 
  * @}
1007 
/**
 1007 
  */
1008 
  * @}
 1008 
 
1009 
  */
 1009 
/**
1010 
 
 1010 
  * @}
1011 
/**
 1011 
  */
1012 
  * @}
 1012 
 
1013 
  */
 1013 
/**
1014 
 
 1014 
  * @}
1015 
/**
 1015 
  */
1016 
  * @}
 1016 
 
1017 
  */
 1017 
/**
1018 
 
 1018 
  * @}
1019 
/**
 1019 
  */
1020 
  * @}
 1020 
 
1021 
  */
 1021 
#ifdef __cplusplus
1022 
 
 1022 
}
1023 
#ifdef __cplusplus
 1023 
#endif
1024 
}
 1024 
 
1025 
#endif
 1025 
#endif /* __STM32L1xx_HAL_RCC_EX_H */
1026 
 
 1026 
 
1027 
#endif /* __STM32L1xx_HAL_RCC_EX_H */
 1027 
 
1028 
 
 - 
 
1029 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 - 
 
1030 
 
 -