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1 
/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32l1xx_hal_rcc.h
 3 
  * @file    stm32l1xx_hal_rcc.h
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Header file of RCC HAL module.
 5 
  * @brief   Header file of RCC HAL module.
6 
  ******************************************************************************
 6 
  ******************************************************************************
7 
  * @attention
 7 
  * @attention
8 
  *
 8 
  *
9 
  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
 9 
  * Copyright (c) 2017 STMicroelectronics.
10 
  * All rights reserved.</center></h2>
 10 
  * All rights reserved.
11 
  *
 11 
  *
12 
  * This software component is licensed by ST under BSD 3-Clause license,
 12 
  * This software is licensed under terms that can be found in the LICENSE file in
13 
  * the "License"; You may not use this file except in compliance with the
 13 
  * the root directory of this software component.
14 
  * License. You may obtain a copy of the License at:
 14 
  * If no LICENSE file comes with this software, it is provided AS-IS.
15 
  *                        opensource.org/licenses/BSD-3-Clause
 15 
  ******************************************************************************
16 
  *
 16 
  */
17 
  ******************************************************************************
 17 
 
18 
  */
 18 
/* Define to prevent recursive inclusion -------------------------------------*/
19 
 
 19 
#ifndef __STM32L1xx_HAL_RCC_H
20 
/* Define to prevent recursive inclusion -------------------------------------*/
 20 
#define __STM32L1xx_HAL_RCC_H
21 
#ifndef __STM32L1xx_HAL_RCC_H
 21 
 
22 
#define __STM32L1xx_HAL_RCC_H
 22 
#ifdef __cplusplus
23 
 
 23 
 extern "C" {
24 
#ifdef __cplusplus
 24 
#endif
25 
 extern "C" {
 25 
 
26 
#endif
 26 
/* Includes ------------------------------------------------------------------*/
27 
 
 27 
#include "stm32l1xx_hal_def.h"
28 
/* Includes ------------------------------------------------------------------*/
 28 
 
29 
#include "stm32l1xx_hal_def.h"
 29 
/** @addtogroup STM32L1xx_HAL_Driver
30 
 
 30 
  * @{
31 
/** @addtogroup STM32L1xx_HAL_Driver
 31 
  */
32 
  * @{
 32 
 
33 
  */
 33 
/** @addtogroup RCC
34 
 
 34 
  * @{
35 
/** @addtogroup RCC
 35 
  */
36 
  * @{
 36 
 
37 
  */
 37 
/** @addtogroup RCC_Private_Constants
38 
 
 38 
  * @{
39 
/** @addtogroup RCC_Private_Constants
 39 
  */
40 
  * @{
 40 
 
41 
  */
 41 
/** @defgroup RCC_Timeout RCC Timeout
42 
 
 42 
  * @{
43 
/** @defgroup RCC_Timeout RCC Timeout
 43 
  */
44 
  * @{
 44 
 
45 
  */
 45 
/* Disable Backup domain write protection state change timeout */
46 
 
 46 
#define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
47 
/* Disable Backup domain write protection state change timeout */
 47 
/* LSE state change timeout */
48 
#define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
 48 
#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
49 
/* LSE state change timeout */
 49 
#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
50 
#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
 50 
#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
51 
#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
 51 
#define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
52 
#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
 52 
#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
53 
#define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
 53 
#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
54 
#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
 54 
#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
55 
#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
 55 
/**
56 
#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
 56 
  * @}
57 
/**
 57 
  */
58 
  * @}
 58 
 
59 
  */
 59 
/** @defgroup RCC_Register_Offset Register offsets
60 
 
 60 
  * @{
61 
/** @defgroup RCC_Register_Offset Register offsets
 61 
  */
62 
  * @{
 62 
#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
63 
  */
 63 
#define RCC_CR_OFFSET             0x00
64 
#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
 64 
#define RCC_CFGR_OFFSET           0x08
65 
#define RCC_CR_OFFSET             0x00
 65 
#define RCC_CIR_OFFSET            0x0C
66 
#define RCC_CFGR_OFFSET           0x08
 66 
#define RCC_CSR_OFFSET            0x34
67 
#define RCC_CIR_OFFSET            0x0C
 67 
/**
68 
#define RCC_CSR_OFFSET            0x34
 68 
  * @}
69 
/**
 69 
  */
70 
  * @}
 70 
 
71 
  */
 71 
/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
72 
 
 72 
  * @brief RCC registers bit address in the alias region
73 
/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
 73 
  * @{
74 
  * @brief RCC registers bit address in the alias region
 74 
  */
75 
  * @{
 75 
#define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
76 
  */
 76 
#define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
77 
#define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
 77 
#define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
78 
#define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
 78 
#define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
79 
#define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
 79 
 
80 
#define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
 80 
/* --- CR Register ---*/
81 
 
 81 
/* Alias word address of HSION bit */
82 
/* --- CR Register ---*/
 82 
#define RCC_HSION_BIT_NUMBER      RCC_CR_HSION_Pos
83 
/* Alias word address of HSION bit */
 83 
#define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
84 
#define RCC_HSION_BIT_NUMBER      RCC_CR_HSION_Pos
 84 
/* Alias word address of MSION bit */
85 
#define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
 85 
#define RCC_MSION_BIT_NUMBER      RCC_CR_MSION_Pos
86 
/* Alias word address of MSION bit */
 86 
#define RCC_CR_MSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
87 
#define RCC_MSION_BIT_NUMBER      RCC_CR_MSION_Pos
 87 
/* Alias word address of HSEON bit */
88 
#define RCC_CR_MSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
 88 
#define RCC_HSEON_BIT_NUMBER      RCC_CR_HSEON_Pos
89 
/* Alias word address of HSEON bit */
 89 
#define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
90 
#define RCC_HSEON_BIT_NUMBER      RCC_CR_HSEON_Pos
 90 
/* Alias word address of CSSON bit */
91 
#define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
 91 
#define RCC_CSSON_BIT_NUMBER      RCC_CR_CSSON_Pos
92 
/* Alias word address of CSSON bit */
 92 
#define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
93 
#define RCC_CSSON_BIT_NUMBER      RCC_CR_CSSON_Pos
 93 
/* Alias word address of PLLON bit */
94 
#define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
 94 
#define RCC_PLLON_BIT_NUMBER      RCC_CR_PLLON_Pos
95 
/* Alias word address of PLLON bit */
 95 
#define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
96 
#define RCC_PLLON_BIT_NUMBER      RCC_CR_PLLON_Pos
 96 
 
97 
#define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
 97 
/* --- CSR Register ---*/
98 
 
 98 
/* Alias word address of LSION bit */
99 
/* --- CSR Register ---*/
 99 
#define RCC_LSION_BIT_NUMBER      RCC_CSR_LSION_Pos
100 
/* Alias word address of LSION bit */
 100 
#define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
101 
#define RCC_LSION_BIT_NUMBER      RCC_CSR_LSION_Pos
 101 
 
102 
#define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
 102 
/* Alias word address of RMVF bit */
103 
 
 103 
#define RCC_RMVF_BIT_NUMBER       RCC_CSR_RMVF_Pos
104 
/* Alias word address of RMVF bit */
 104 
#define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
105 
#define RCC_RMVF_BIT_NUMBER       RCC_CSR_RMVF_Pos
 105 
 
106 
#define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
 106 
/* Alias word address of LSEON bit */
107 
 
 107 
#define RCC_LSEON_BIT_NUMBER      RCC_CSR_LSEON_Pos
108 
/* Alias word address of LSEON bit */
 108 
#define RCC_CSR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
109 
#define RCC_LSEON_BIT_NUMBER      RCC_CSR_LSEON_Pos
 109 
 
110 
#define RCC_CSR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
 110 
/* Alias word address of LSEON bit */
111 
 
 111 
#define RCC_LSEBYP_BIT_NUMBER     RCC_CSR_LSEBYP_Pos
112 
/* Alias word address of LSEON bit */
 112 
#define RCC_CSR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
113 
#define RCC_LSEBYP_BIT_NUMBER     RCC_CSR_LSEBYP_Pos
 113 
 
114 
#define RCC_CSR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
 114 
/* Alias word address of RTCEN bit */
115 
 
 115 
#define RCC_RTCEN_BIT_NUMBER      RCC_CSR_RTCEN_Pos
116 
/* Alias word address of RTCEN bit */
 116 
#define RCC_CSR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
117 
#define RCC_RTCEN_BIT_NUMBER      RCC_CSR_RTCEN_Pos
 117 
 
118 
#define RCC_CSR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
 118 
/* Alias word address of RTCRST bit */
119 
 
 119 
#define RCC_RTCRST_BIT_NUMBER     RCC_CSR_RTCRST_Pos
120 
/* Alias word address of RTCRST bit */
 120 
#define RCC_CSR_RTCRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
121 
#define RCC_RTCRST_BIT_NUMBER     RCC_CSR_RTCRST_Pos
 121 
 
122 
#define RCC_CSR_RTCRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
 122 
/**
123 
 
 123 
  * @}
124 
/**
 124 
  */
125 
  * @}
 125 
 
126 
  */
 126 
/* CR register byte 2 (Bits[23:16]) base address */
127 
 
 127 
#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
128 
/* CR register byte 2 (Bits[23:16]) base address */
 128 
 
129 
#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
 129 
/* CIR register byte 1 (Bits[15:8]) base address */
130 
 
 130 
#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
131 
/* CIR register byte 1 (Bits[15:8]) base address */
 131 
 
132 
#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
 132 
/* CIR register byte 2 (Bits[23:16]) base address */
133 
 
 133 
#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
134 
/* CIR register byte 2 (Bits[23:16]) base address */
 134 
 
135 
#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
 135 
/* Defines used for Flags */
136 
 
 136 
#define CR_REG_INDEX                     ((uint8_t)1U)
137 
/* Defines used for Flags */
 137 
#define CSR_REG_INDEX                    ((uint8_t)2U)
138 
#define CR_REG_INDEX                     ((uint8_t)1U)
 138 
 
139 
#define CSR_REG_INDEX                    ((uint8_t)2U)
 139 
#define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
140 
 
 140 
 
141 
#define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
 141 
/**
142 
 
 142 
  * @}
143 
/**
 143 
  */
144 
  * @}
 144 
 
145 
  */
 145 
/** @addtogroup RCC_Private_Macros
146 
 
 146 
  * @{
147 
/** @addtogroup RCC_Private_Macros
 147 
  */
148 
  * @{
 148 
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
149 
  */
 149 
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
150 
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
 150 
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
151 
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
 151 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
152 
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
 152 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
153 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
 153 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
154 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
 154 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
155 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
 155 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
156 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
 156 
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
157 
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
 157 
                             ((__HSE__) == RCC_HSE_BYPASS))
158 
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
 158 
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
159 
                             ((__HSE__) == RCC_HSE_BYPASS))
 159 
                             ((__LSE__) == RCC_LSE_BYPASS))
160 
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
 160 
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
161 
                             ((__LSE__) == RCC_LSE_BYPASS))
 161 
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
162 
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
 162 
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
163 
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
 163 
#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
164 
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
 164 
                                            ((__RANGE__) == RCC_MSIRANGE_1) || \
165 
#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
 165 
                                            ((__RANGE__) == RCC_MSIRANGE_2) || \
166 
                                            ((__RANGE__) == RCC_MSIRANGE_1) || \
 166 
                                            ((__RANGE__) == RCC_MSIRANGE_3) || \
167 
                                            ((__RANGE__) == RCC_MSIRANGE_2) || \
 167 
                                            ((__RANGE__) == RCC_MSIRANGE_4) || \
168 
                                            ((__RANGE__) == RCC_MSIRANGE_3) || \
 168 
                                            ((__RANGE__) == RCC_MSIRANGE_5) || \
169 
                                            ((__RANGE__) == RCC_MSIRANGE_4) || \
 169 
                                            ((__RANGE__) == RCC_MSIRANGE_6))
170 
                                            ((__RANGE__) == RCC_MSIRANGE_5) || \
 170 
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
171 
                                            ((__RANGE__) == RCC_MSIRANGE_6))
 171 
#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
172 
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
 172 
 
173 
#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
 173 
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
174 
 
 174 
                             ((__PLL__) == RCC_PLL_ON))
175 
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
 175 
#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
176 
                             ((__PLL__) == RCC_PLL_ON))
 176 
                                 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
177 
#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
 177 
 
178 
                                 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
 178 
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3)  || ((__MUL__) == RCC_PLL_MUL4)  || \
179 
 
 179 
                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL8)  || \
180 
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3)  || ((__MUL__) == RCC_PLL_MUL4)  || \
 180 
                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
181 
                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL8)  || \
 181 
                                 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
182 
                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
 182 
                                 ((__MUL__) == RCC_PLL_MUL48))
183 
                                 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
 183 
#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
184 
                                 ((__MUL__) == RCC_PLL_MUL48))
 184 
                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
185 
#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
 185 
                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
186 
                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
 186 
                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
187 
                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
 187 
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
188 
                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
 188 
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
189 
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
 189 
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
190 
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
 190 
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
191 
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
 191 
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \
192 
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
 192 
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
193 
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \
 193 
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
194 
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
 194 
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
195 
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
 195 
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
196 
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
 196 
                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
197 
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
 197 
                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
198 
                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
 198 
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
199 
                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
 199 
                               ((__HCLK__) == RCC_SYSCLK_DIV512))
200 
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
 200 
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
201 
                               ((__HCLK__) == RCC_SYSCLK_DIV512))
 201 
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
202 
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
 202 
                               ((__PCLK__) == RCC_HCLK_DIV16))
203 
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
 203 
#define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
204 
                               ((__PCLK__) == RCC_HCLK_DIV16))
 204 
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
205 
#define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
 205 
                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
206 
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
 206 
                                ((__DIV__) == RCC_MCODIV_16))
207 
                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
 207 
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
208 
                                ((__DIV__) == RCC_MCODIV_16))
 208 
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
209 
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
 209 
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_LSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
210 
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
 210 
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
211 
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_LSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
 211 
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK)   || \
212 
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
 212 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)      || \
213 
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK)   || \
 213 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)      || \
214 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)      || \
 214 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
215 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)      || \
 215 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
216 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
 216 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
217 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
 217 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
218 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
 218 
 
219 
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
 219 
/**
220 
 
 220 
  * @}
221 
/**
 221 
  */
222 
  * @}
 222 
 
223 
  */
 223 
/* Exported types ------------------------------------------------------------*/
224 
 
 224 
 
225 
/* Exported types ------------------------------------------------------------*/
 225 
/** @defgroup RCC_Exported_Types RCC Exported Types
226 
 
 226 
  * @{
227 
/** @defgroup RCC_Exported_Types RCC Exported Types
 227 
  */
228 
  * @{
 228 
 
229 
  */
 229 
/**
230 
 
 230 
  * @brief  RCC PLL configuration structure definition
231 
/**
 231 
  */
232 
  * @brief  RCC PLL configuration structure definition
 232 
typedef struct
233 
  */
 233 
{
234 
typedef struct
 234 
  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
235 
{
 235 
                              This parameter can be a value of @ref RCC_PLL_Config */
236 
  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
 236 
 
237 
                              This parameter can be a value of @ref RCC_PLL_Config */
 237 
  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
238 
 
 238 
                              This parameter must be a value of @ref RCC_PLL_Clock_Source */
239 
  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
 239 
 
240 
                              This parameter must be a value of @ref RCC_PLL_Clock_Source */
 240 
  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
241 
 
 241 
                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
242 
  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
 242 
 
243 
                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
 243 
  uint32_t PLLDIV;        /*!< PLLDIV: Division factor for PLL VCO input clock
244 
 
 244 
                              This parameter must be a value of @ref RCC_PLL_Division_Factor*/
245 
  uint32_t PLLDIV;        /*!< PLLDIV: Division factor for PLL VCO input clock
 245 
} RCC_PLLInitTypeDef;
246 
                              This parameter must be a value of @ref RCC_PLL_Division_Factor*/
 246 
 
247 
} RCC_PLLInitTypeDef;
 247 
/**
248 
 
 248 
  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
249 
/**
 249 
  */
250 
  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
 250 
typedef struct
251 
  */
 251 
{
252 
typedef struct
 252 
  uint32_t OscillatorType;        /*!< The oscillators to be configured.
253 
{
 253 
                                       This parameter can be a value of @ref RCC_Oscillator_Type */
254 
  uint32_t OscillatorType;        /*!< The oscillators to be configured.
 254 
 
255 
                                       This parameter can be a value of @ref RCC_Oscillator_Type */
 255 
  uint32_t HSEState;              /*!< The new state of the HSE.
256 
 
 256 
                                       This parameter can be a value of @ref RCC_HSE_Config */
257 
  uint32_t HSEState;              /*!< The new state of the HSE.
 257 
 
258 
                                       This parameter can be a value of @ref RCC_HSE_Config */
 258 
  uint32_t LSEState;              /*!< The new state of the LSE.
259 
 
 259 
                                       This parameter can be a value of @ref RCC_LSE_Config */
260 
  uint32_t LSEState;              /*!< The new state of the LSE.
 260 
 
261 
                                       This parameter can be a value of @ref RCC_LSE_Config */
 261 
  uint32_t HSIState;              /*!< The new state of the HSI.
262 
 
 262 
                                       This parameter can be a value of @ref RCC_HSI_Config */
263 
  uint32_t HSIState;              /*!< The new state of the HSI.
 263 
 
264 
                                       This parameter can be a value of @ref RCC_HSI_Config */
 264 
  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
265 
 
 265 
                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
266 
  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
 266 
 
267 
                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
 267 
  uint32_t LSIState;              /*!< The new state of the LSI.
268 
 
 268 
                                       This parameter can be a value of @ref RCC_LSI_Config */
269 
  uint32_t LSIState;              /*!< The new state of the LSI.
 269 
 
270 
                                       This parameter can be a value of @ref RCC_LSI_Config */
 270 
  uint32_t MSIState;              /*!< The new state of the MSI.
271 
 
 271 
                                       This parameter can be a value of @ref RCC_MSI_Config */
272 
  uint32_t MSIState;              /*!< The new state of the MSI.
 272 
 
273 
                                       This parameter can be a value of @ref RCC_MSI_Config */
 273 
  uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
274 
 
 274 
                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
275 
  uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
 275 
 
276 
                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
 276 
  uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
277 
 
 277 
                                        This parameter can be a value of @ref RCC_MSI_Clock_Range */
278 
  uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
 278 
 
279 
                                        This parameter can be a value of @ref RCC_MSI_Clock_Range */
 279 
  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
280 
 
 280 
 
281 
  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
 281 
} RCC_OscInitTypeDef;
282 
 
 282 
 
283 
} RCC_OscInitTypeDef;
 283 
/**
284 
 
 284 
  * @brief  RCC System, AHB and APB busses clock configuration structure definition
285 
/**
 285 
  */
286 
  * @brief  RCC System, AHB and APB busses clock configuration structure definition
 286 
typedef struct
287 
  */
 287 
{
288 
typedef struct
 288 
  uint32_t ClockType;             /*!< The clock to be configured.
289 
{
 289 
                                       This parameter can be a value of @ref RCC_System_Clock_Type */
290 
  uint32_t ClockType;             /*!< The clock to be configured.
 290 
 
291 
                                       This parameter can be a value of @ref RCC_System_Clock_Type */
 291 
  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
292 
 
 292 
                                       This parameter can be a value of @ref RCC_System_Clock_Source */
293 
  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
 293 
 
294 
                                       This parameter can be a value of @ref RCC_System_Clock_Source */
 294 
  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
295 
 
 295 
                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
296 
  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
 296 
 
297 
                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
 297 
  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
298 
 
 298 
                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
299 
  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
 299 
 
300 
                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 300 
  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
301 
 
 301 
                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
302 
  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
 302 
} RCC_ClkInitTypeDef;
303 
                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 303 
 
304 
} RCC_ClkInitTypeDef;
 304 
/**
305 
 
 305 
  * @}
306 
/**
 306 
  */
307 
  * @}
 307 
 
308 
  */
 308 
/* Exported constants --------------------------------------------------------*/
309 
 
 309 
/** @defgroup RCC_Exported_Constants RCC Exported Constants
310 
/* Exported constants --------------------------------------------------------*/
 310 
  * @{
311 
/** @defgroup RCC_Exported_Constants RCC Exported Constants
 311 
  */
312 
  * @{
 312 
 
313 
  */
 313 
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
314 
 
 314 
  * @{
315 
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
 315 
  */
316 
  * @{
 316 
 
317 
  */
 317 
#define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI        /*!< HSI clock selected as PLL entry clock source */
318 
 
 318 
#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE        /*!< HSE clock selected as PLL entry clock source */
319 
#define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI        /*!< HSI clock selected as PLL entry clock source */
 319 
 
320 
#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE        /*!< HSE clock selected as PLL entry clock source */
 320 
/**
321 
 
 321 
  * @}
322 
/**
 322 
  */
323 
  * @}
 323 
 
324 
  */
 324 
/** @defgroup RCC_Oscillator_Type Oscillator Type
325 
 
 325 
  * @{
326 
/** @defgroup RCC_Oscillator_Type Oscillator Type
 326 
  */
327 
  * @{
 327 
#define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
328 
  */
 328 
#define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
329 
#define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
 329 
#define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
330 
#define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
 330 
#define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
331 
#define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
 331 
#define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
332 
#define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
 332 
#define RCC_OSCILLATORTYPE_MSI             (0x00000010U)
333 
#define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
 333 
/**
334 
#define RCC_OSCILLATORTYPE_MSI             (0x00000010U)
 334 
  * @}
335 
/**
 335 
  */
336 
  * @}
 336 
 
337 
  */
 337 
/** @defgroup RCC_HSE_Config HSE Config
338 
 
 338 
  * @{
339 
/** @defgroup RCC_HSE_Config HSE Config
 339 
  */
340 
  * @{
 340 
#define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
341 
  */
 341 
#define RCC_HSE_ON                       (0x00000001U)                     /*!< HSE clock activation */
342 
#define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
 342 
#define RCC_HSE_BYPASS                   (0x00000005U)                     /*!< External clock source for HSE clock */
343 
#define RCC_HSE_ON                       (0x00000001U)                     /*!< HSE clock activation */
 343 
/**
344 
#define RCC_HSE_BYPASS                   (0x00000005U)                     /*!< External clock source for HSE clock */
 344 
  * @}
345 
/**
 345 
  */
346 
  * @}
 346 
 
347 
  */
 347 
/** @defgroup RCC_LSE_Config LSE Config
348 
 
 348 
  * @{
349 
/** @defgroup RCC_LSE_Config LSE Config
 349 
  */
350 
  * @{
 350 
#define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
351 
  */
 351 
#define RCC_LSE_ON                       (0x00000001U)                       /*!< LSE clock activation */
352 
#define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
 352 
#define RCC_LSE_BYPASS                   (0x00000005U)                       /*!< External clock source for LSE clock */
353 
#define RCC_LSE_ON                       (0x00000001U)                       /*!< LSE clock activation */
 353 
 
354 
#define RCC_LSE_BYPASS                   (0x00000005U)                       /*!< External clock source for LSE clock */
 354 
/**
355 
 
 355 
  * @}
356 
/**
 356 
  */
357 
  * @}
 357 
 
358 
  */
 358 
/** @defgroup RCC_HSI_Config HSI Config
359 
 
 359 
  * @{
360 
/** @defgroup RCC_HSI_Config HSI Config
 360 
  */
361 
  * @{
 361 
#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
362 
  */
 362 
#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
363 
#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
 363 
 
364 
#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
 364 
#define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
365 
 
 365 
 
366 
#define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
 366 
/**
367 
 
 367 
  * @}
368 
/**
 368 
  */
369 
  * @}
 369 
 
370 
  */
 370 
/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
371 
 
 371 
  * @{
372 
/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
 372 
  */
373 
  * @{
 373 
 
374 
  */
 374 
#define RCC_MSIRANGE_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
375 
 
 375 
#define RCC_MSIRANGE_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
376 
#define RCC_MSIRANGE_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
 376 
#define RCC_MSIRANGE_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
377 
#define RCC_MSIRANGE_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
 377 
#define RCC_MSIRANGE_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
378 
#define RCC_MSIRANGE_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
 378 
#define RCC_MSIRANGE_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
379 
#define RCC_MSIRANGE_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
 379 
#define RCC_MSIRANGE_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
380 
#define RCC_MSIRANGE_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
 380 
#define RCC_MSIRANGE_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
381 
#define RCC_MSIRANGE_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
 381 
 
382 
#define RCC_MSIRANGE_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
 382 
/**
383 
 
 383 
  * @}
384 
/**
 384 
  */
385 
  * @}
 385 
 
386 
  */
 386 
/** @defgroup RCC_LSI_Config LSI Config
387 
 
 387 
  * @{
388 
/** @defgroup RCC_LSI_Config LSI Config
 388 
  */
389 
  * @{
 389 
#define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
390 
  */
 390 
#define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
391 
#define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
 391 
 
392 
#define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
 392 
/**
393 
 
 393 
  * @}
394 
/**
 394 
  */
395 
  * @}
 395 
 
396 
  */
 396 
/** @defgroup RCC_MSI_Config MSI Config
397 
 
 397 
  * @{
398 
/** @defgroup RCC_MSI_Config MSI Config
 398 
  */
399 
  * @{
 399 
#define RCC_MSI_OFF                      (0x00000000U)
400 
  */
 400 
#define RCC_MSI_ON                       (0x00000001U)
401 
#define RCC_MSI_OFF                      (0x00000000U)
 401 
 
402 
#define RCC_MSI_ON                       (0x00000001U)
 402 
#define RCC_MSICALIBRATION_DEFAULT       (0x00000000U)   /* Default MSI calibration trimming value */
403 
 
 403 
 
404 
#define RCC_MSICALIBRATION_DEFAULT       (0x00000000U)   /* Default MSI calibration trimming value */
 404 
/**
405 
 
 405 
  * @}
406 
/**
 406 
  */
407 
  * @}
 407 
 
408 
  */
 408 
/** @defgroup RCC_PLL_Config PLL Config
409 
 
 409 
  * @{
410 
/** @defgroup RCC_PLL_Config PLL Config
 410 
  */
411 
  * @{
 411 
#define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
412 
  */
 412 
#define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
413 
#define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
 413 
#define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
414 
#define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
 414 
 
415 
#define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
 415 
/**
416 
 
 416 
  * @}
417 
/**
 417 
  */
418 
  * @}
 418 
 
419 
  */
 419 
/** @defgroup RCC_System_Clock_Type System Clock Type
420 
 
 420 
  * @{
421 
/** @defgroup RCC_System_Clock_Type System Clock Type
 421 
  */
422 
  * @{
 422 
#define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
423 
  */
 423 
#define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
424 
#define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
 424 
#define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
425 
#define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
 425 
#define RCC_CLOCKTYPE_PCLK2              (0x00000008U) /*!< PCLK2 to configure */
426 
#define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
 426 
 
427 
#define RCC_CLOCKTYPE_PCLK2              (0x00000008U) /*!< PCLK2 to configure */
 427 
/**
428 
 
 428 
  * @}
429 
/**
 429 
  */
430 
  * @}
 430 
 
431 
  */
 431 
/** @defgroup RCC_System_Clock_Source System Clock Source
432 
 
 432 
  * @{
433 
/** @defgroup RCC_System_Clock_Source System Clock Source
 433 
  */
434 
  * @{
 434 
#define RCC_SYSCLKSOURCE_MSI             RCC_CFGR_SW_MSI /*!< MSI selected as system clock */
435 
  */
 435 
#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
436 
#define RCC_SYSCLKSOURCE_MSI             RCC_CFGR_SW_MSI /*!< MSI selected as system clock */
 436 
#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
437 
#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
 437 
#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
438 
#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
 438 
 
439 
#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
 439 
/**
440 
 
 440 
  * @}
441 
/**
 441 
  */
442 
  * @}
 442 
 
443 
  */
 443 
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
444 
 
 444 
  * @{
445 
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
 445 
  */
446 
  * @{
 446 
#define RCC_SYSCLKSOURCE_STATUS_MSI      RCC_CFGR_SWS_MSI            /*!< MSI used as system clock */
447 
  */
 447 
#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
448 
#define RCC_SYSCLKSOURCE_STATUS_MSI      RCC_CFGR_SWS_MSI            /*!< MSI used as system clock */
 448 
#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
449 
#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
 449 
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
450 
#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
 450 
 
451 
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
 451 
/**
452 
 
 452 
  * @}
453 
/**
 453 
  */
454 
  * @}
 454 
 
455 
  */
 455 
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
456 
 
 456 
  * @{
457 
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
 457 
  */
458 
  * @{
 458 
#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
459 
  */
 459 
#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
460 
#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
 460 
#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
461 
#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
 461 
#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
462 
#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
 462 
#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
463 
#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
 463 
#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
464 
#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
 464 
#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
465 
#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
 465 
#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
466 
#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
 466 
#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
467 
#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
 467 
 
468 
#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
 468 
/**
469 
 
 469 
  * @}
470 
/**
 470 
  */
471 
  * @}
 471 
 
472 
  */
 472 
/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
473 
 
 473 
  * @{
474 
/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
 474 
  */
475 
  * @{
 475 
#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
476 
  */
 476 
#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
477 
#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
 477 
#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
478 
#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
 478 
#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
479 
#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
 479 
#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
480 
#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
 480 
 
481 
#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
 481 
/**
482 
 
 482 
  * @}
483 
/**
 483 
  */
484 
  * @}
 484 
 
485 
  */
 485 
/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
486 
 
 486 
  * @{
487 
/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
 487 
  */
488 
  * @{
 488 
#define RCC_RTC_HSE_DIV_2               0x00000000U /*!< HSE is divided by 2 for RTC clock  */
489 
  */
 489 
#define RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0       /*!< HSE is divided by 4 for RTC clock  */
490 
#define RCC_RTC_HSE_DIV_2               0x00000000U /*!< HSE is divided by 2 for RTC clock  */
 490 
#define RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1       /*!< HSE is divided by 8 for RTC clock  */
491 
#define RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0       /*!< HSE is divided by 4 for RTC clock  */
 491 
#define RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE         /*!< HSE is divided by 16 for RTC clock */
492 
#define RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1       /*!< HSE is divided by 8 for RTC clock  */
 492 
/**
493 
#define RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE         /*!< HSE is divided by 16 for RTC clock */
 493 
  * @}
494 
/**
 494 
  */
495 
  * @}
 495 
 
496 
  */
 496 
/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
497 
 
 497 
  * @{
498 
/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
 498 
  */
499 
  * @{
 499 
#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)                 /*!< No clock */
500 
  */
 500 
#define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
501 
#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)                 /*!< No clock */
 501 
#define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
502 
#define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
 502 
#define RCC_RTCCLKSOURCE_HSE_DIVX        RCC_CSR_RTCSEL_HSE                         /*!< HSE oscillator clock divided by X used as RTC clock */
503 
#define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
 503 
#define RCC_RTCCLKSOURCE_HSE_DIV2        (RCC_RTC_HSE_DIV_2  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 2 used as RTC clock */
504 
#define RCC_RTCCLKSOURCE_HSE_DIVX        RCC_CSR_RTCSEL_HSE                         /*!< HSE oscillator clock divided by X used as RTC clock */
 504 
#define RCC_RTCCLKSOURCE_HSE_DIV4        (RCC_RTC_HSE_DIV_4  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 4 used as RTC clock */
505 
#define RCC_RTCCLKSOURCE_HSE_DIV2        (RCC_RTC_HSE_DIV_2  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 2 used as RTC clock */
 505 
#define RCC_RTCCLKSOURCE_HSE_DIV8        (RCC_RTC_HSE_DIV_8  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 8 used as RTC clock */
506 
#define RCC_RTCCLKSOURCE_HSE_DIV4        (RCC_RTC_HSE_DIV_4  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 4 used as RTC clock */
 506 
#define RCC_RTCCLKSOURCE_HSE_DIV16       (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 16 used as RTC clock */
507 
#define RCC_RTCCLKSOURCE_HSE_DIV8        (RCC_RTC_HSE_DIV_8  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 8 used as RTC clock */
 507 
/**
508 
#define RCC_RTCCLKSOURCE_HSE_DIV16       (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 16 used as RTC clock */
 508 
  * @}
509 
/**
 509 
  */
510 
  * @}
 510 
 
511 
  */
 511 
/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
512 
 
 512 
  * @{
513 
/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
 513 
  */
514 
  * @{
 514 
 
515 
  */
 515 
#define RCC_PLL_DIV2                    RCC_CFGR_PLLDIV2
516 
 
 516 
#define RCC_PLL_DIV3                    RCC_CFGR_PLLDIV3
517 
#define RCC_PLL_DIV2                    RCC_CFGR_PLLDIV2
 517 
#define RCC_PLL_DIV4                    RCC_CFGR_PLLDIV4
518 
#define RCC_PLL_DIV3                    RCC_CFGR_PLLDIV3
 518 
 
519 
#define RCC_PLL_DIV4                    RCC_CFGR_PLLDIV4
 519 
/**
520 
 
 520 
  * @}
521 
/**
 521 
  */
522 
  * @}
 522 
 
523 
  */
 523 
/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
524 
 
 524 
  * @{
525 
/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
 525 
  */
526 
  * @{
 526 
 
527 
  */
 527 
#define RCC_PLL_MUL3                    RCC_CFGR_PLLMUL3
528 
 
 528 
#define RCC_PLL_MUL4                    RCC_CFGR_PLLMUL4
529 
#define RCC_PLL_MUL3                    RCC_CFGR_PLLMUL3
 529 
#define RCC_PLL_MUL6                    RCC_CFGR_PLLMUL6
530 
#define RCC_PLL_MUL4                    RCC_CFGR_PLLMUL4
 530 
#define RCC_PLL_MUL8                    RCC_CFGR_PLLMUL8
531 
#define RCC_PLL_MUL6                    RCC_CFGR_PLLMUL6
 531 
#define RCC_PLL_MUL12                   RCC_CFGR_PLLMUL12
532 
#define RCC_PLL_MUL8                    RCC_CFGR_PLLMUL8
 532 
#define RCC_PLL_MUL16                   RCC_CFGR_PLLMUL16
533 
#define RCC_PLL_MUL12                   RCC_CFGR_PLLMUL12
 533 
#define RCC_PLL_MUL24                   RCC_CFGR_PLLMUL24
534 
#define RCC_PLL_MUL16                   RCC_CFGR_PLLMUL16
 534 
#define RCC_PLL_MUL32                   RCC_CFGR_PLLMUL32
535 
#define RCC_PLL_MUL24                   RCC_CFGR_PLLMUL24
 535 
#define RCC_PLL_MUL48                   RCC_CFGR_PLLMUL48
536 
#define RCC_PLL_MUL32                   RCC_CFGR_PLLMUL32
 536 
 
537 
#define RCC_PLL_MUL48                   RCC_CFGR_PLLMUL48
 537 
/**
538 
 
 538 
  * @}
539 
/**
 539 
  */
540 
  * @}
 540 
 
541 
  */
 541 
/** @defgroup RCC_MCO_Index MCO Index
542 
 
 542 
  * @{
543 
/** @defgroup RCC_MCO_Index MCO Index
 543 
  */
544 
  * @{
 544 
#define RCC_MCO1                         (0x00000000U)
545 
  */
 545 
#define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
546 
#define RCC_MCO1                         (0x00000000U)
 546 
 
547 
#define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
 547 
/**
548 
 
 548 
  * @}
549 
/**
 549 
  */
550 
  * @}
 550 
 
551 
  */
 551 
/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
552 
 
 552 
  * @{
553 
/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
 553 
  */
554 
  * @{
 554 
#define RCC_MCODIV_1                    ((uint32_t)RCC_CFGR_MCO_DIV1)
555 
  */
 555 
#define RCC_MCODIV_2                    ((uint32_t)RCC_CFGR_MCO_DIV2)
556 
#define RCC_MCODIV_1                    ((uint32_t)RCC_CFGR_MCO_DIV1)
 556 
#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO_DIV4)
557 
#define RCC_MCODIV_2                    ((uint32_t)RCC_CFGR_MCO_DIV2)
 557 
#define RCC_MCODIV_8                    ((uint32_t)RCC_CFGR_MCO_DIV8)
558 
#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO_DIV4)
 558 
#define RCC_MCODIV_16                   ((uint32_t)RCC_CFGR_MCO_DIV16)
559 
#define RCC_MCODIV_8                    ((uint32_t)RCC_CFGR_MCO_DIV8)
 559 
 
560 
#define RCC_MCODIV_16                   ((uint32_t)RCC_CFGR_MCO_DIV16)
 560 
/**
561 
 
 561 
  * @}
562 
/**
 562 
  */
563 
  * @}
 563 
 
564 
  */
 564 
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
565 
 
 565 
  * @{
566 
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
 566 
  */
567 
  * @{
 567 
#define RCC_MCO1SOURCE_NOCLOCK           RCC_CFGR_MCO_NOCLOCK
568 
  */
 568 
#define RCC_MCO1SOURCE_SYSCLK            RCC_CFGR_MCO_SYSCLK
569 
#define RCC_MCO1SOURCE_NOCLOCK           RCC_CFGR_MCO_NOCLOCK
 569 
#define RCC_MCO1SOURCE_MSI               RCC_CFGR_MCO_MSI
570 
#define RCC_MCO1SOURCE_SYSCLK            RCC_CFGR_MCO_SYSCLK
 570 
#define RCC_MCO1SOURCE_HSI               RCC_CFGR_MCO_HSI
571 
#define RCC_MCO1SOURCE_MSI               RCC_CFGR_MCO_MSI
 571 
#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO_LSE
572 
#define RCC_MCO1SOURCE_HSI               RCC_CFGR_MCO_HSI
 572 
#define RCC_MCO1SOURCE_LSI               RCC_CFGR_MCO_LSI
573 
#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO_LSE
 573 
#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO_HSE
574 
#define RCC_MCO1SOURCE_LSI               RCC_CFGR_MCO_LSI
 574 
#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO_PLL
575 
#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO_HSE
 575 
 
576 
#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO_PLL
 576 
/**
577 
 
 577 
  * @}
578 
/**
 578 
  */
579 
  * @}
 579 
/** @defgroup RCC_Interrupt Interrupts
580 
  */
 580 
  * @{
581 
/** @defgroup RCC_Interrupt Interrupts
 581 
  */
582 
  * @{
 582 
#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
583 
  */
 583 
#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
584 
#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
 584 
#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
585 
#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
 585 
#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
586 
#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
 586 
#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
587 
#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
 587 
#define RCC_IT_MSIRDY                    ((uint8_t)RCC_CIR_MSIRDYF)   /*!< MSI Ready Interrupt flag */
588 
#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
 588 
#define RCC_IT_LSECSS                    ((uint8_t)RCC_CIR_LSECSSF)   /*!< LSE Clock Security System Interrupt flag */
589 
#define RCC_IT_MSIRDY                    ((uint8_t)RCC_CIR_MSIRDYF)   /*!< MSI Ready Interrupt flag */
 589 
#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
590 
#define RCC_IT_LSECSS                    ((uint8_t)RCC_CIR_LSECSSF)   /*!< LSE Clock Security System Interrupt flag */
 590 
/**
591 
#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
 591 
  * @}
592 
/**
 592 
  */
593 
  * @}
 593 
 
594 
  */
 594 
/** @defgroup RCC_Flag Flags
595 
 
 595 
  *        Elements values convention: XXXYYYYYb
596 
/** @defgroup RCC_Flag Flags
 596 
  *           - YYYYY  : Flag position in the register
597 
  *        Elements values convention: XXXYYYYYb
 597 
  *           - XXX  : Register index
598 
  *           - YYYYY  : Flag position in the register
 598 
  *                 - 001: CR register
599 
  *           - XXX  : Register index
 599 
  *                 - 010: CSR register
600 
  *                 - 001: CR register
 600 
  * @{
601 
  *                 - 010: CSR register
 601 
  */
602 
  * @{
 602 
/* Flags in the CR register */
603 
  */
 603 
#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
604 
/* Flags in the CR register */
 604 
#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */
605 
#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
 605 
#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
606 
#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */
 606 
#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
607 
#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
 607 
 
608 
#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
 608 
/* Flags in the CSR register */
609 
 
 609 
#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
610 
/* Flags in the CSR register */
 610 
#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSECSSD_Pos))  /*!< CSS on LSE failure Detection */
611 
#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
 611 
#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos))  /*!< Options bytes loading reset flag */
612 
#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSECSSD_Pos))  /*!< CSS on LSE failure Detection */
 612 
#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
613 
#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos))  /*!< Options bytes loading reset flag */
 613 
#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
614 
#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
 614 
#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
615 
#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
 615 
#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
616 
#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
 616 
#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
617 
#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
 617 
#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
618 
#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
 618 
#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
619 
#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
 619 
 
620 
#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
 620 
/**
621 
 
 621 
  * @}
622 
/**
 622 
  */
623 
  * @}
 623 
 
624 
  */
 624 
/**
625 
 
 625 
  * @}
626 
/**
 626 
  */
627 
  * @}
 627 
 
628 
  */
 628 
/* Exported macro ------------------------------------------------------------*/
629 
 
 629 
 
630 
/* Exported macro ------------------------------------------------------------*/
 630 
/** @defgroup RCC_Exported_Macros RCC Exported Macros
631 
 
 631 
  * @{
632 
/** @defgroup RCC_Exported_Macros RCC Exported Macros
 632 
  */
633 
  * @{
 633 
 
634 
  */
 634 
/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
635 
 
 635 
  * @brief  Enable or disable the AHB1 peripheral clock.
636 
/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
 636 
  * @note   After reset, the peripheral clock (used for registers read/write access)
637 
  * @brief  Enable or disable the AHB1 peripheral clock.
 637 
  *         is disabled and the application software has to enable this clock before
638 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 638 
  *         using it.
639 
  *         is disabled and the application software has to enable this clock before
 639 
  * @{
640 
  *         using it.
 640 
  */
641 
  * @{
 641 
#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
642 
  */
 642 
                                        __IO uint32_t tmpreg; \
643 
#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
 643 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
644 
                                        __IO uint32_t tmpreg; \
 644 
                                        /* Delay after an RCC peripheral clock enabling */\
645 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
 645 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
646 
                                        /* Delay after an RCC peripheral clock enabling */\
 646 
                                        UNUSED(tmpreg); \
647 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
 647 
                                      } while(0U)
648 
                                        UNUSED(tmpreg); \
 648 
#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
649 
                                      } while(0U)
 649 
                                        __IO uint32_t tmpreg; \
650 
#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
 650 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
651 
                                        __IO uint32_t tmpreg; \
 651 
                                        /* Delay after an RCC peripheral clock enabling */\
652 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
 652 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
653 
                                        /* Delay after an RCC peripheral clock enabling */\
 653 
                                        UNUSED(tmpreg); \
654 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
 654 
                                      } while(0U)
655 
                                        UNUSED(tmpreg); \
 655 
#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
656 
                                      } while(0U)
 656 
                                        __IO uint32_t tmpreg; \
657 
#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
 657 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
658 
                                        __IO uint32_t tmpreg; \
 658 
                                        /* Delay after an RCC peripheral clock enabling */\
659 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
 659 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
660 
                                        /* Delay after an RCC peripheral clock enabling */\
 660 
                                        UNUSED(tmpreg); \
661 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
 661 
                                      } while(0U)
662 
                                        UNUSED(tmpreg); \
 662 
#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
663 
                                      } while(0U)
 663 
                                        __IO uint32_t tmpreg; \
664 
#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
 664 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
665 
                                        __IO uint32_t tmpreg; \
 665 
                                        /* Delay after an RCC peripheral clock enabling */\
666 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
 666 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
667 
                                        /* Delay after an RCC peripheral clock enabling */\
 667 
                                        UNUSED(tmpreg); \
668 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
 668 
                                      } while(0U)
669 
                                        UNUSED(tmpreg); \
 669 
#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
670 
                                      } while(0U)
 670 
                                        __IO uint32_t tmpreg; \
671 
#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
 671 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
672 
                                        __IO uint32_t tmpreg; \
 672 
                                        /* Delay after an RCC peripheral clock enabling */\
673 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
 673 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
674 
                                        /* Delay after an RCC peripheral clock enabling */\
 674 
                                        UNUSED(tmpreg); \
675 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
 675 
                                      } while(0U)
676 
                                        UNUSED(tmpreg); \
 676 
#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
677 
                                      } while(0U)
 677 
                                        __IO uint32_t tmpreg; \
678 
#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
 678 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
679 
                                        __IO uint32_t tmpreg; \
 679 
                                        /* Delay after an RCC peripheral clock enabling */\
680 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
 680 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
681 
                                        /* Delay after an RCC peripheral clock enabling */\
 681 
                                        UNUSED(tmpreg); \
682 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
 682 
                                      } while(0U)
683 
                                        UNUSED(tmpreg); \
 683 
#define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
684 
                                      } while(0U)
 684 
                                        __IO uint32_t tmpreg; \
685 
#define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
 685 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
686 
                                        __IO uint32_t tmpreg; \
 686 
                                        /* Delay after an RCC peripheral clock enabling */\
687 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
 687 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
688 
                                        /* Delay after an RCC peripheral clock enabling */\
 688 
                                        UNUSED(tmpreg); \
689 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
 689 
                                      } while(0U)
690 
                                        UNUSED(tmpreg); \
 690 
#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
691 
                                      } while(0U)
 691 
                                        __IO uint32_t tmpreg; \
692 
#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
 692 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
693 
                                        __IO uint32_t tmpreg; \
 693 
                                        /* Delay after an RCC peripheral clock enabling */\
694 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
 694 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
695 
                                        /* Delay after an RCC peripheral clock enabling */\
 695 
                                        UNUSED(tmpreg); \
696 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
 696 
                                      } while(0U)
697 
                                        UNUSED(tmpreg); \
 697 
 
698 
                                      } while(0U)
 698 
#define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
699 
 
 699 
#define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
700 
#define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
 700 
#define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
701 
#define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
 701 
#define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
702 
#define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
 702 
#define __HAL_RCC_GPIOH_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
703 
#define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
 703 
 
704 
#define __HAL_RCC_GPIOH_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
 704 
#define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
705 
 
 705 
#define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
706 
#define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
 706 
#define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
707 
#define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
 707 
 
708 
#define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
 708 
/**
709 
 
 709 
  * @}
710 
/**
 710 
  */
711 
  * @}
 711 
 
712 
  */
 712 
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
713 
 
 713 
  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
714 
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
 714 
  * @note   After reset, the peripheral clock (used for registers read/write access)
715 
  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 715 
  *         is disabled and the application software has to enable this clock before
716 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 716 
  *         using it.
717 
  *         is disabled and the application software has to enable this clock before
 717 
  * @{
718 
  *         using it.
 718 
  */
719 
  * @{
 719 
#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
720 
  */
 720 
                                        __IO uint32_t tmpreg; \
721 
#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
 721 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
722 
                                        __IO uint32_t tmpreg; \
 722 
                                        /* Delay after an RCC peripheral clock enabling */\
723 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
 723 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
724 
                                        /* Delay after an RCC peripheral clock enabling */\
 724 
                                        UNUSED(tmpreg); \
725 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
 725 
                                      } while(0U)
726 
                                        UNUSED(tmpreg); \
 726 
#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
727 
                                      } while(0U)
 727 
                                        __IO uint32_t tmpreg; \
728 
#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
 728 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
729 
                                        __IO uint32_t tmpreg; \
 729 
                                        /* Delay after an RCC peripheral clock enabling */\
730 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
 730 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
731 
                                        /* Delay after an RCC peripheral clock enabling */\
 731 
                                        UNUSED(tmpreg); \
732 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
 732 
                                      } while(0U)
733 
                                        UNUSED(tmpreg); \
 733 
#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
734 
                                      } while(0U)
 734 
                                        __IO uint32_t tmpreg; \
735 
#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
 735 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
736 
                                        __IO uint32_t tmpreg; \
 736 
                                        /* Delay after an RCC peripheral clock enabling */\
737 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
 737 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
738 
                                        /* Delay after an RCC peripheral clock enabling */\
 738 
                                        UNUSED(tmpreg); \
739 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
 739 
                                      } while(0U)
740 
                                        UNUSED(tmpreg); \
 740 
#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
741 
                                      } while(0U)
 741 
                                        __IO uint32_t tmpreg; \
742 
#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
 742 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
743 
                                        __IO uint32_t tmpreg; \
 743 
                                        /* Delay after an RCC peripheral clock enabling */\
744 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
 744 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
745 
                                        /* Delay after an RCC peripheral clock enabling */\
 745 
                                        UNUSED(tmpreg); \
746 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
 746 
                                      } while(0U)
747 
                                        UNUSED(tmpreg); \
 747 
#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
748 
                                      } while(0U)
 748 
                                        __IO uint32_t tmpreg; \
749 
#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
 749 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
750 
                                        __IO uint32_t tmpreg; \
 750 
                                        /* Delay after an RCC peripheral clock enabling */\
751 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
 751 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
752 
                                        /* Delay after an RCC peripheral clock enabling */\
 752 
                                        UNUSED(tmpreg); \
753 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
 753 
                                      } while(0U)
754 
                                        UNUSED(tmpreg); \
 754 
#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
755 
                                      } while(0U)
 755 
                                        __IO uint32_t tmpreg; \
756 
#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
 756 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
757 
                                        __IO uint32_t tmpreg; \
 757 
                                        /* Delay after an RCC peripheral clock enabling */\
758 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
 758 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
759 
                                        /* Delay after an RCC peripheral clock enabling */\
 759 
                                        UNUSED(tmpreg); \
760 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
 760 
                                      } while(0U)
761 
                                        UNUSED(tmpreg); \
 761 
#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
762 
                                      } while(0U)
 762 
                                        __IO uint32_t tmpreg; \
763 
#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
 763 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
764 
                                        __IO uint32_t tmpreg; \
 764 
                                        /* Delay after an RCC peripheral clock enabling */\
765 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
 765 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
766 
                                        /* Delay after an RCC peripheral clock enabling */\
 766 
                                        UNUSED(tmpreg); \
767 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
 767 
                                      } while(0U)
768 
                                        UNUSED(tmpreg); \
 768 
#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
769 
                                      } while(0U)
 769 
                                        __IO uint32_t tmpreg; \
770 
#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
 770 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
771 
                                        __IO uint32_t tmpreg; \
 771 
                                        /* Delay after an RCC peripheral clock enabling */\
772 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
 772 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
773 
                                        /* Delay after an RCC peripheral clock enabling */\
 773 
                                        UNUSED(tmpreg); \
774 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
 774 
                                      } while(0U)
775 
                                        UNUSED(tmpreg); \
 775 
#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
776 
                                      } while(0U)
 776 
                                        __IO uint32_t tmpreg; \
777 
#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
 777 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
778 
                                        __IO uint32_t tmpreg; \
 778 
                                        /* Delay after an RCC peripheral clock enabling */\
779 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
 779 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
780 
                                        /* Delay after an RCC peripheral clock enabling */\
 780 
                                        UNUSED(tmpreg); \
781 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
 781 
                                      } while(0U)
782 
                                        UNUSED(tmpreg); \
 782 
#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
783 
                                      } while(0U)
 783 
                                        __IO uint32_t tmpreg; \
784 
#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
 784 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
785 
                                        __IO uint32_t tmpreg; \
 785 
                                        /* Delay after an RCC peripheral clock enabling */\
786 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
 786 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
787 
                                        /* Delay after an RCC peripheral clock enabling */\
 787 
                                        UNUSED(tmpreg); \
788 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
 788 
                                      } while(0U)
789 
                                        UNUSED(tmpreg); \
 789 
#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
790 
                                      } while(0U)
 790 
                                        __IO uint32_t tmpreg; \
791 
#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
 791 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
792 
                                        __IO uint32_t tmpreg; \
 792 
                                        /* Delay after an RCC peripheral clock enabling */\
793 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
 793 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
794 
                                        /* Delay after an RCC peripheral clock enabling */\
 794 
                                        UNUSED(tmpreg); \
795 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
 795 
                                      } while(0U)
796 
                                        UNUSED(tmpreg); \
 796 
#define __HAL_RCC_USB_CLK_ENABLE()   do { \
797 
                                      } while(0U)
 797 
                                        __IO uint32_t tmpreg; \
798 
#define __HAL_RCC_USB_CLK_ENABLE()   do { \
 798 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
799 
                                        __IO uint32_t tmpreg; \
 799 
                                        /* Delay after an RCC peripheral clock enabling */\
800 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
 800 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
801 
                                        /* Delay after an RCC peripheral clock enabling */\
 801 
                                        UNUSED(tmpreg); \
802 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
 802 
                                      } while(0U)
803 
                                        UNUSED(tmpreg); \
 803 
#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
804 
                                      } while(0U)
 804 
                                        __IO uint32_t tmpreg; \
805 
#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
 805 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
806 
                                        __IO uint32_t tmpreg; \
 806 
                                        /* Delay after an RCC peripheral clock enabling */\
807 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
 807 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
808 
                                        /* Delay after an RCC peripheral clock enabling */\
 808 
                                        UNUSED(tmpreg); \
809 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
 809 
                                      } while(0U)
810 
                                        UNUSED(tmpreg); \
 810 
#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
811 
                                      } while(0U)
 811 
                                        __IO uint32_t tmpreg; \
812 
#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
 812 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
813 
                                        __IO uint32_t tmpreg; \
 813 
                                        /* Delay after an RCC peripheral clock enabling */\
814 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
 814 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
815 
                                        /* Delay after an RCC peripheral clock enabling */\
 815 
                                        UNUSED(tmpreg); \
816 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
 816 
                                      } while(0U)
817 
                                        UNUSED(tmpreg); \
 817 
#define __HAL_RCC_COMP_CLK_ENABLE()   do { \
818 
                                      } while(0U)
 818 
                                        __IO uint32_t tmpreg; \
819 
#define __HAL_RCC_COMP_CLK_ENABLE()   do { \
 819 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
820 
                                        __IO uint32_t tmpreg; \
 820 
                                        /* Delay after an RCC peripheral clock enabling */\
821 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
 821 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
822 
                                        /* Delay after an RCC peripheral clock enabling */\
 822 
                                        UNUSED(tmpreg); \
823 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
 823 
                                      } while(0U)
824 
                                        UNUSED(tmpreg); \
 824 
 
825 
                                      } while(0U)
 825 
 
826 
 
 826 
#define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
827 
 
 827 
#define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
828 
#define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 828 
#define __HAL_RCC_TIM4_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
829 
#define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 829 
#define __HAL_RCC_TIM6_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
830 
#define __HAL_RCC_TIM4_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
 830 
#define __HAL_RCC_TIM7_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
831 
#define __HAL_RCC_TIM6_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 831 
#define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
832 
#define __HAL_RCC_TIM7_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 832 
#define __HAL_RCC_SPI2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
833 
#define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 833 
#define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
834 
#define __HAL_RCC_SPI2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 834 
#define __HAL_RCC_USART3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
835 
#define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 835 
#define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
836 
#define __HAL_RCC_USART3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 836 
#define __HAL_RCC_I2C2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
837 
#define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 837 
#define __HAL_RCC_USB_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
838 
#define __HAL_RCC_I2C2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 838 
#define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
839 
#define __HAL_RCC_USB_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
 839 
#define __HAL_RCC_DAC_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
840 
#define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 840 
#define __HAL_RCC_COMP_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
841 
#define __HAL_RCC_DAC_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 841 
 
842 
#define __HAL_RCC_COMP_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
 842 
/**
843 
 
 843 
  * @}
844 
/**
 844 
  */
845 
  * @}
 845 
 
846 
  */
 846 
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
847 
 
 847 
  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
848 
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
 848 
  * @note   After reset, the peripheral clock (used for registers read/write access)
849 
  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 849 
  *         is disabled and the application software has to enable this clock before
850 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 850 
  *         using it.
851 
  *         is disabled and the application software has to enable this clock before
 851 
  * @{
852 
  *         using it.
 852 
  */
853 
  * @{
 853 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
854 
  */
 854 
                                        __IO uint32_t tmpreg; \
855 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
 855 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
856 
                                        __IO uint32_t tmpreg; \
 856 
                                        /* Delay after an RCC peripheral clock enabling */\
857 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
 857 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
858 
                                        /* Delay after an RCC peripheral clock enabling */\
 858 
                                        UNUSED(tmpreg); \
859 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
 859 
                                      } while(0U)
860 
                                        UNUSED(tmpreg); \
 860 
#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
861 
                                      } while(0U)
 861 
                                        __IO uint32_t tmpreg; \
862 
#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
 862 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
863 
                                        __IO uint32_t tmpreg; \
 863 
                                        /* Delay after an RCC peripheral clock enabling */\
864 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
 864 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
865 
                                        /* Delay after an RCC peripheral clock enabling */\
 865 
                                        UNUSED(tmpreg); \
866 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
 866 
                                      } while(0U)
867 
                                        UNUSED(tmpreg); \
 867 
#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
868 
                                      } while(0U)
 868 
                                        __IO uint32_t tmpreg; \
869 
#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
 869 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
870 
                                        __IO uint32_t tmpreg; \
 870 
                                        /* Delay after an RCC peripheral clock enabling */\
871 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
 871 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
872 
                                        /* Delay after an RCC peripheral clock enabling */\
 872 
                                        UNUSED(tmpreg); \
873 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
 873 
                                      } while(0U)
874 
                                        UNUSED(tmpreg); \
 874 
#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
875 
                                      } while(0U)
 875 
                                        __IO uint32_t tmpreg; \
876 
#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
 876 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
877 
                                        __IO uint32_t tmpreg; \
 877 
                                        /* Delay after an RCC peripheral clock enabling */\
878 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
 878 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
879 
                                        /* Delay after an RCC peripheral clock enabling */\
 879 
                                        UNUSED(tmpreg); \
880 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
 880 
                                      } while(0U)
881 
                                        UNUSED(tmpreg); \
 881 
#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
882 
                                      } while(0U)
 882 
                                        __IO uint32_t tmpreg; \
883 
#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
 883 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
884 
                                        __IO uint32_t tmpreg; \
 884 
                                        /* Delay after an RCC peripheral clock enabling */\
885 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
 885 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
886 
                                        /* Delay after an RCC peripheral clock enabling */\
 886 
                                        UNUSED(tmpreg); \
887 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
 887 
                                      } while(0U)
888 
                                        UNUSED(tmpreg); \
 888 
#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
889 
                                      } while(0U)
 889 
                                        __IO uint32_t tmpreg; \
890 
#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
 890 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
891 
                                        __IO uint32_t tmpreg; \
 891 
                                        /* Delay after an RCC peripheral clock enabling */\
892 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
 892 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
893 
                                        /* Delay after an RCC peripheral clock enabling */\
 893 
                                        UNUSED(tmpreg); \
894 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
 894 
                                      } while(0U)
895 
                                        UNUSED(tmpreg); \
 895 
#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
896 
                                      } while(0U)
 896 
                                        __IO uint32_t tmpreg; \
897 
#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
 897 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
898 
                                        __IO uint32_t tmpreg; \
 898 
                                        /* Delay after an RCC peripheral clock enabling */\
899 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
 899 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
900 
                                        /* Delay after an RCC peripheral clock enabling */\
 900 
                                        UNUSED(tmpreg); \
901 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
 901 
                                      } while(0U)
902 
                                        UNUSED(tmpreg); \
 902 
 
903 
                                      } while(0U)
 903 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
904 
 
 904 
#define __HAL_RCC_TIM9_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
905 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 905 
#define __HAL_RCC_TIM10_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
906 
#define __HAL_RCC_TIM9_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 906 
#define __HAL_RCC_TIM11_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
907 
#define __HAL_RCC_TIM10_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
 907 
#define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
908 
#define __HAL_RCC_TIM11_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 908 
#define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
909 
#define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 909 
#define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
910 
#define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 910 
 
911 
#define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 911 
/**
912 
 
 912 
  * @}
913 
/**
 913 
  */
914 
  * @}
 914 
 
915 
  */
 915 
/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
916 
 
 916 
  * @brief  Force or release AHB peripheral reset.
917 
/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
 917 
  * @{
918 
  * @brief  Force or release AHB peripheral reset.
 918 
  */
919 
  * @{
 919 
#define __HAL_RCC_AHB_FORCE_RESET()       (RCC->AHBRSTR = 0xFFFFFFFFU)
920 
  */
 920 
#define __HAL_RCC_GPIOA_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
921 
#define __HAL_RCC_AHB_FORCE_RESET()       (RCC->AHBRSTR = 0xFFFFFFFFU)
 921 
#define __HAL_RCC_GPIOB_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
922 
#define __HAL_RCC_GPIOA_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
 922 
#define __HAL_RCC_GPIOC_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
923 
#define __HAL_RCC_GPIOB_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
 923 
#define __HAL_RCC_GPIOD_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
924 
#define __HAL_RCC_GPIOC_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
 924 
#define __HAL_RCC_GPIOH_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
925 
#define __HAL_RCC_GPIOD_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
 925 
 
926 
#define __HAL_RCC_GPIOH_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
 926 
#define __HAL_RCC_CRC_FORCE_RESET()       (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
927 
 
 927 
#define __HAL_RCC_FLITF_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
928 
#define __HAL_RCC_CRC_FORCE_RESET()       (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
 928 
#define __HAL_RCC_DMA1_FORCE_RESET()      (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
929 
#define __HAL_RCC_FLITF_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
 929 
 
930 
#define __HAL_RCC_DMA1_FORCE_RESET()      (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
 930 
#define __HAL_RCC_AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00000000U)
931 
 
 931 
#define __HAL_RCC_GPIOA_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
932 
#define __HAL_RCC_AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00000000U)
 932 
#define __HAL_RCC_GPIOB_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
933 
#define __HAL_RCC_GPIOA_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
 933 
#define __HAL_RCC_GPIOC_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
934 
#define __HAL_RCC_GPIOB_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
 934 
#define __HAL_RCC_GPIOD_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
935 
#define __HAL_RCC_GPIOC_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
 935 
#define __HAL_RCC_GPIOH_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
936 
#define __HAL_RCC_GPIOD_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
 936 
 
937 
#define __HAL_RCC_GPIOH_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
 937 
#define __HAL_RCC_CRC_RELEASE_RESET()     (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
938 
 
 938 
#define __HAL_RCC_FLITF_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
939 
#define __HAL_RCC_CRC_RELEASE_RESET()     (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
 939 
#define __HAL_RCC_DMA1_RELEASE_RESET()    (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
940 
#define __HAL_RCC_FLITF_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
 940 
 
941 
#define __HAL_RCC_DMA1_RELEASE_RESET()    (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
 941 
/**
942 
 
 942 
  * @}
943 
/**
 943 
  */
944 
  * @}
 944 
 
945 
  */
 945 
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
946 
 
 946 
  * @brief  Force or release APB1 peripheral reset.
947 
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
 947 
  * @{
948 
  * @brief  Force or release APB1 peripheral reset.
 948 
  */
949 
  * @{
 949 
#define __HAL_RCC_APB1_FORCE_RESET()      (RCC->APB1RSTR = 0xFFFFFFFFU)
950 
  */
 950 
#define __HAL_RCC_TIM2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
951 
#define __HAL_RCC_APB1_FORCE_RESET()      (RCC->APB1RSTR = 0xFFFFFFFFU)
 951 
#define __HAL_RCC_TIM3_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
952 
#define __HAL_RCC_TIM2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
 952 
#define __HAL_RCC_TIM4_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
953 
#define __HAL_RCC_TIM3_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
 953 
#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
954 
#define __HAL_RCC_TIM4_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
 954 
#define __HAL_RCC_TIM7_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
955 
#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
 955 
#define __HAL_RCC_WWDG_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
956 
#define __HAL_RCC_TIM7_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
 956 
#define __HAL_RCC_SPI2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
957 
#define __HAL_RCC_WWDG_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
 957 
#define __HAL_RCC_USART2_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
958 
#define __HAL_RCC_SPI2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
 958 
#define __HAL_RCC_USART3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
959 
#define __HAL_RCC_USART2_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
 959 
#define __HAL_RCC_I2C1_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
960 
#define __HAL_RCC_USART3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
 960 
#define __HAL_RCC_I2C2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
961 
#define __HAL_RCC_I2C1_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
 961 
#define __HAL_RCC_USB_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
962 
#define __HAL_RCC_I2C2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
 962 
#define __HAL_RCC_PWR_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
963 
#define __HAL_RCC_USB_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
 963 
#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
964 
#define __HAL_RCC_PWR_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
 964 
#define __HAL_RCC_COMP_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
965 
#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
 965 
 
966 
#define __HAL_RCC_COMP_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
 966 
#define __HAL_RCC_APB1_RELEASE_RESET()    (RCC->APB1RSTR = 0x00000000U)
967 
 
 967 
#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
968 
#define __HAL_RCC_APB1_RELEASE_RESET()    (RCC->APB1RSTR = 0x00000000U)
 968 
#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
969 
#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
 969 
#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
970 
#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
 970 
#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
971 
#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
 971 
#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
972 
#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
 972 
#define __HAL_RCC_WWDG_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
973 
#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
 973 
#define __HAL_RCC_SPI2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
974 
#define __HAL_RCC_WWDG_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
 974 
#define __HAL_RCC_USART2_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
975 
#define __HAL_RCC_SPI2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
 975 
#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
976 
#define __HAL_RCC_USART2_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
 976 
#define __HAL_RCC_I2C1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
977 
#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
 977 
#define __HAL_RCC_I2C2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
978 
#define __HAL_RCC_I2C1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
 978 
#define __HAL_RCC_USB_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
979 
#define __HAL_RCC_I2C2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
 979 
#define __HAL_RCC_PWR_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
980 
#define __HAL_RCC_USB_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
 980 
#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
981 
#define __HAL_RCC_PWR_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
 981 
#define __HAL_RCC_COMP_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
982 
#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
 982 
 
983 
#define __HAL_RCC_COMP_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
 983 
/**
984 
 
 984 
  * @}
985 
/**
 985 
  */
986 
  * @}
 986 
 
987 
  */
 987 
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
988 
 
 988 
  * @brief  Force or release APB1 peripheral reset.
989 
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
 989 
  * @{
990 
  * @brief  Force or release APB1 peripheral reset.
 990 
  */
991 
  * @{
 991 
#define __HAL_RCC_APB2_FORCE_RESET()      (RCC->APB2RSTR = 0xFFFFFFFFU)
992 
  */
 992 
#define __HAL_RCC_SYSCFG_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
993 
#define __HAL_RCC_APB2_FORCE_RESET()      (RCC->APB2RSTR = 0xFFFFFFFFU)
 993 
#define __HAL_RCC_TIM9_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
994 
#define __HAL_RCC_SYSCFG_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
 994 
#define __HAL_RCC_TIM10_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
995 
#define __HAL_RCC_TIM9_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
 995 
#define __HAL_RCC_TIM11_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
996 
#define __HAL_RCC_TIM10_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
 996 
#define __HAL_RCC_ADC1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
997 
#define __HAL_RCC_TIM11_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
 997 
#define __HAL_RCC_SPI1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
998 
#define __HAL_RCC_ADC1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
 998 
#define __HAL_RCC_USART1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
999 
#define __HAL_RCC_SPI1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
 999 
 
1000 
#define __HAL_RCC_USART1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
 1000 
#define __HAL_RCC_APB2_RELEASE_RESET()    (RCC->APB2RSTR = 0x00000000U)
1001 
 
 1001 
#define __HAL_RCC_SYSCFG_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
1002 
#define __HAL_RCC_APB2_RELEASE_RESET()    (RCC->APB2RSTR = 0x00000000U)
 1002 
#define __HAL_RCC_TIM9_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1003 
#define __HAL_RCC_SYSCFG_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
 1003 
#define __HAL_RCC_TIM10_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1004 
#define __HAL_RCC_TIM9_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
 1004 
#define __HAL_RCC_TIM11_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1005 
#define __HAL_RCC_TIM10_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
 1005 
#define __HAL_RCC_ADC1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
1006 
#define __HAL_RCC_TIM11_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
 1006 
#define __HAL_RCC_SPI1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
1007 
#define __HAL_RCC_ADC1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
 1007 
#define __HAL_RCC_USART1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
1008 
#define __HAL_RCC_SPI1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
 1008 
 
1009 
#define __HAL_RCC_USART1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
 1009 
/**
1010 
 
 1010 
  * @}
1011 
/**
 1011 
  */
1012 
  * @}
 1012 
 
1013 
  */
 1013 
/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
1014 
 
 1014 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1015 
/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
 1015 
  *         power consumption.
1016 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 1016 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1017 
  *         power consumption.
 1017 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1018 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 1018 
  * @{
1019 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 1019 
  */
1020 
  * @{
 1020 
#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))
1021 
  */
 1021 
#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))
1022 
#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))
 1022 
#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))
1023 
#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))
 1023 
#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))
1024 
#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))
 1024 
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))
1025 
#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))
 1025 
 
1026 
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))
 1026 
#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))
1027 
 
 1027 
#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))
1028 
#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))
 1028 
#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))
1029 
#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))
 1029 
 
1030 
#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))
 1030 
#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
1031 
 
 1031 
#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
1032 
#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
 1032 
#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
1033 
#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
 1033 
#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
1034 
#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
 1034 
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
1035 
#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
 1035 
 
1036 
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
 1036 
#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
1037 
 
 1037 
#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
1038 
#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
 1038 
#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
1039 
#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
 1039 
 
1040 
#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
 1040 
/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
1041 
 
 1041 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1042 
/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
 1042 
  *           power consumption.
1043 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 1043 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1044 
  *           power consumption.
 1044 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1045 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 1045 
  */
1046 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 1046 
#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1047 
  */
 1047 
#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1048 
#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
 1048 
#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1049 
#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
 1049 
#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1050 
#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
 1050 
#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1051 
#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
 1051 
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
1052 
#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
 1052 
#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
1053 
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
 1053 
#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
1054 
#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
 1054 
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1055 
#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
 1055 
#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
1056 
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
 1056 
#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
1057 
#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
 1057 
#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))
1058 
#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
 1058 
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
1059 
#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))
 1059 
#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1060 
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
 1060 
#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))
1061 
#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
 1061 
 
1062 
#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))
 1062 
#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1063 
 
 1063 
#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1064 
#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
 1064 
#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1065 
#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
 1065 
#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1066 
#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
 1066 
#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1067 
#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
 1067 
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
1068 
#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
 1068 
#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
1069 
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
 1069 
#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
1070 
#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
 1070 
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1071 
#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
 1071 
#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
1072 
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
 1072 
#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
1073 
#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
 1073 
#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
1074 
#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
 1074 
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
1075 
#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
 1075 
#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1076 
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
 1076 
#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
1077 
#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
 1077 
 
1078 
#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
 1078 
/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
1079 
 
 1079 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1080 
/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
 1080 
  *           power consumption.
1081 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 1081 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1082 
  *           power consumption.
 1082 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1083 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 1083 
  */
1084 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 1084 
#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
1085 
  */
 1085 
#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
1086 
#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
 1086 
#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
1087 
#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
 1087 
#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
1088 
#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
 1088 
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
1089 
#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
 1089 
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
1090 
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
 1090 
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
1091 
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
 1091 
 
1092 
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
 1092 
#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
1093 
 
 1093 
#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
1094 
#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
 1094 
#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
1095 
#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
 1095 
#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
1096 
#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
 1096 
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
1097 
#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
 1097 
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
1098 
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
 1098 
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
1099 
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
 1099 
 
1100 
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
 1100 
/**
1101 
 
 1101 
  * @}
1102 
/**
 1102 
  */
1103 
  * @}
 1103 
 
1104 
  */
 1104 
/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
1105 
 
 1105 
  * @brief  Get the enable or disable status of the AHB peripheral clock.
1106 
/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
 1106 
  * @note   After reset, the peripheral clock (used for registers read/write access)
1107 
  * @brief  Get the enable or disable status of the AHB peripheral clock.
 1107 
  *         is disabled and the application software has to enable this clock before
1108 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 1108 
  *         using it.
1109 
  *         is disabled and the application software has to enable this clock before
 1109 
  * @{
1110 
  *         using it.
 1110 
  */
1111 
  * @{
 1111 
 
1112 
  */
 1112 
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U)
1113 
 
 1113 
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U)
1114 
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U)
 1114 
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U)
1115 
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U)
 1115 
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U)
1116 
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U)
 1116 
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U)
1117 
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U)
 1117 
#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U)
1118 
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U)
 1118 
#define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U)
1119 
#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U)
 1119 
#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U)
1120 
#define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U)
 1120 
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U)
1121 
#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U)
 1121 
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U)
1122 
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U)
 1122 
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U)
1123 
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U)
 1123 
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U)
1124 
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U)
 1124 
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U)
1125 
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U)
 1125 
#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U)
1126 
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U)
 1126 
#define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U)
1127 
#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U)
 1127 
#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U)
1128 
#define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U)
 1128 
 
1129 
#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U)
 1129 
/**
1130 
 
 1130 
  * @}
1131 
/**
 1131 
  */
1132 
  * @}
 1132 
 
1133 
  */
 1133 
/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
1134 
 
 1134 
  * @brief  Get the enable or disable status of the APB1 peripheral clock.
1135 
/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
 1135 
  * @note   After reset, the peripheral clock (used for registers read/write access)
1136 
  * @brief  Get the enable or disable status of the APB1 peripheral clock.
 1136 
  *         is disabled and the application software has to enable this clock before
1137 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 1137 
  *         using it.
1138 
  *         is disabled and the application software has to enable this clock before
 1138 
  * @{
1139 
  *         using it.
 1139 
  */
1140 
  * @{
 1140 
 
1141 
  */
 1141 
#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U)
1142 
 
 1142 
#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U)
1143 
#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U)
 1143 
#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U)
1144 
#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U)
 1144 
#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U)
1145 
#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U)
 1145 
#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U)
1146 
#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U)
 1146 
#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U)
1147 
#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U)
 1147 
#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U)
1148 
#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U)
 1148 
#define __HAL_RCC_USART2_IS_CLK_ENABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U)
1149 
#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U)
 1149 
#define __HAL_RCC_USART3_IS_CLK_ENABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U)
1150 
#define __HAL_RCC_USART2_IS_CLK_ENABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U)
 1150 
#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U)
1151 
#define __HAL_RCC_USART3_IS_CLK_ENABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U)
 1151 
#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U)
1152 
#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U)
 1152 
#define __HAL_RCC_USB_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U)
1153 
#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U)
 1153 
#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U)
1154 
#define __HAL_RCC_USB_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U)
 1154 
#define __HAL_RCC_DAC_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U)
1155 
#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U)
 1155 
#define __HAL_RCC_COMP_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U)
1156 
#define __HAL_RCC_DAC_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U)
 1156 
#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U)
1157 
#define __HAL_RCC_COMP_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U)
 1157 
#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U)
1158 
#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U)
 1158 
#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U)
1159 
#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U)
 1159 
#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U)
1160 
#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U)
 1160 
#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U)
1161 
#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U)
 1161 
#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U)
1162 
#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U)
 1162 
#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U)
1163 
#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U)
 1163 
#define __HAL_RCC_USART2_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U)
1164 
#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U)
 1164 
#define __HAL_RCC_USART3_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U)
1165 
#define __HAL_RCC_USART2_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U)
 1165 
#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U)
1166 
#define __HAL_RCC_USART3_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U)
 1166 
#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U)
1167 
#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U)
 1167 
#define __HAL_RCC_USB_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U)
1168 
#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U)
 1168 
#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U)
1169 
#define __HAL_RCC_USB_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U)
 1169 
#define __HAL_RCC_DAC_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U)
1170 
#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U)
 1170 
#define __HAL_RCC_COMP_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U)
1171 
#define __HAL_RCC_DAC_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U)
 1171 
 
1172 
#define __HAL_RCC_COMP_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U)
 1172 
/**
1173 
 
 1173 
  * @}
1174 
/**
 1174 
  */
1175 
  * @}
 1175 
 
1176 
  */
 1176 
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
1177 
 
 1177 
  * @brief  Get the enable or disable status of the APB2 peripheral clock.
1178 
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
 1178 
  * @note   After reset, the peripheral clock (used for registers read/write access)
1179 
  * @brief  Get the enable or disable status of the APB2 peripheral clock.
 1179 
  *         is disabled and the application software has to enable this clock before
1180 
  * @note   After reset, the peripheral clock (used for registers read/write access)
 1180 
  *         using it.
1181 
  *         is disabled and the application software has to enable this clock before
 1181 
  * @{
1182 
  *         using it.
 1182 
  */
1183 
  * @{
 1183 
 
1184 
  */
 1184 
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U)
1185 
 
 1185 
#define __HAL_RCC_TIM9_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U)
1186 
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U)
 1186 
#define __HAL_RCC_TIM10_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U)
1187 
#define __HAL_RCC_TIM9_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U)
 1187 
#define __HAL_RCC_TIM11_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U)
1188 
#define __HAL_RCC_TIM10_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U)
 1188 
#define __HAL_RCC_ADC1_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U)
1189 
#define __HAL_RCC_TIM11_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U)
 1189 
#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U)
1190 
#define __HAL_RCC_ADC1_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U)
 1190 
#define __HAL_RCC_USART1_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U)
1191 
#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U)
 1191 
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U)
1192 
#define __HAL_RCC_USART1_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U)
 1192 
#define __HAL_RCC_TIM9_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U)
1193 
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U)
 1193 
#define __HAL_RCC_TIM10_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U)
1194 
#define __HAL_RCC_TIM9_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U)
 1194 
#define __HAL_RCC_TIM11_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U)
1195 
#define __HAL_RCC_TIM10_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U)
 1195 
#define __HAL_RCC_ADC1_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U)
1196 
#define __HAL_RCC_TIM11_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U)
 1196 
#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U)
1197 
#define __HAL_RCC_ADC1_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U)
 1197 
#define __HAL_RCC_USART1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U)
1198 
#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U)
 1198 
 
1199 
#define __HAL_RCC_USART1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U)
 1199 
/**
1200 
 
 1200 
  * @}
1201 
/**
 1201 
  */
1202 
  * @}
 1202 
 
1203 
  */
 1203 
/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status
1204 
 
 1204 
  * @brief  Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.
1205 
/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status
 1205 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1206 
  * @brief  Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.
 1206 
  *         power consumption.
1207 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 1207 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1208 
  *         power consumption.
 1208 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1209 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 1209 
  * @{
1210 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 1210 
  */
1211 
  * @{
 1211 
 
1212 
  */
 1212 
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U)
1213 
 
 1213 
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U)
1214 
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U)
 1214 
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U)
1215 
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U)
 1215 
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U)
1216 
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U)
 1216 
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U)
1217 
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U)
 1217 
#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()         ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U)
1218 
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U)
 1218 
#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U)
1219 
#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()         ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U)
 1219 
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U)
1220 
#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U)
 1220 
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U)
1221 
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U)
 1221 
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U)
1222 
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U)
 1222 
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U)
1223 
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U)
 1223 
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U)
1224 
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U)
 1224 
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U)
1225 
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U)
 1225 
#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U)
1226 
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U)
 1226 
#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U)
1227 
#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U)
 1227 
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U)
1228 
#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U)
 1228 
 
1229 
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U)
 1229 
/**
1230 
 
 1230 
  * @}
1231 
/**
 1231 
  */
1232 
  * @}
 1232 
 
1233 
  */
 1233 
/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
1234 
 
 1234 
  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
1235 
/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
 1235 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1236 
  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
 1236 
  *         power consumption.
1237 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 1237 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1238 
  *         power consumption.
 1238 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1239 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 1239 
  * @{
1240 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 1240 
  */
1241 
  * @{
 1241 
 
1242 
  */
 1242 
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U)
1243 
 
 1243 
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U)
1244 
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U)
 1244 
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U)
1245 
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U)
 1245 
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U)
1246 
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U)
 1246 
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U)
1247 
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U)
 1247 
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U)
1248 
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U)
 1248 
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U)
1249 
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U)
 1249 
#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U)
1250 
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U)
 1250 
#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U)
1251 
#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U)
 1251 
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U)
1252 
#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U)
 1252 
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U)
1253 
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U)
 1253 
#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U)
1254 
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U)
 1254 
#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U)
1255 
#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U)
 1255 
#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U)
1256 
#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U)
 1256 
#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U)
1257 
#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U)
 1257 
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U)
1258 
#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U)
 1258 
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U)
1259 
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U)
 1259 
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U)
1260 
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U)
 1260 
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U)
1261 
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U)
 1261 
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U)
1262 
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U)
 1262 
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U)
1263 
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U)
 1263 
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U)
1264 
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U)
 1264 
#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U)
1265 
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U)
 1265 
#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U)
1266 
#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U)
 1266 
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U)
1267 
#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U)
 1267 
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U)
1268 
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U)
 1268 
#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U)
1269 
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U)
 1269 
#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U)
1270 
#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U)
 1270 
#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U)
1271 
#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U)
 1271 
#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U)
1272 
#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U)
 1272 
 
1273 
#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U)
 1273 
/**
1274 
 
 1274 
  * @}
1275 
/**
 1275 
  */
1276 
  * @}
 1276 
 
1277 
  */
 1277 
/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
1278 
 
 1278 
  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
1279 
/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
 1279 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1280 
  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
 1280 
  *         power consumption.
1281 
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 1281 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1282 
  *         power consumption.
 1282 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1283 
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 1283 
  * @{
1284 
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 1284 
  */
1285 
  * @{
 1285 
 
1286 
  */
 1286 
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U)
1287 
 
 1287 
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U)
1288 
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U)
 1288 
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U)
1289 
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U)
 1289 
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U)
1290 
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U)
 1290 
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U)
1291 
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U)
 1291 
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
1292 
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U)
 1292 
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
1293 
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
 1293 
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U)
1294 
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
 1294 
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U)
1295 
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U)
 1295 
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U)
1296 
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U)
 1296 
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U)
1297 
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U)
 1297 
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U)
1298 
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U)
 1298 
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
1299 
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U)
 1299 
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
1300 
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
 1300 
 
1301 
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
 1301 
/**
1302 
 
 1302 
  * @}
1303 
/**
 1303 
  */
1304 
  * @}
 1304 
 
1305 
  */
 1305 
/** @defgroup RCC_HSI_Configuration HSI Configuration
1306 
 
 1306 
  * @{
1307 
/** @defgroup RCC_HSI_Configuration HSI Configuration
 1307 
  */
1308 
  * @{
 1308 
 
1309 
  */
 1309 
/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
1310 
 
 1310 
  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
1311 
/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
 1311 
  * @note   HSI can not be stopped if it is used as system clock source. In this case,
1312 
  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
 1312 
  *         you have to select another source of the system clock then stop the HSI.
1313 
  * @note   HSI can not be stopped if it is used as system clock source. In this case,
 1313 
  * @note   After enabling the HSI, the application software should wait on HSIRDY
1314 
  *         you have to select another source of the system clock then stop the HSI.
 1314 
  *         flag to be set indicating that HSI clock is stable and can be used as
1315 
  * @note   After enabling the HSI, the application software should wait on HSIRDY
 1315 
  *         system clock source.
1316 
  *         flag to be set indicating that HSI clock is stable and can be used as
 1316 
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
1317 
  *         system clock source.
 1317 
  *         clock cycles.
1318 
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
 1318 
  */
1319 
  *         clock cycles.
 1319 
#define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
1320 
  */
 1320 
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
1321 
#define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
 1321 
 
1322 
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
 1322 
/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
1323 
 
 1323 
  * @note   The calibration is used to compensate for the variations in voltage
1324 
/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
 1324 
  *         and temperature that influence the frequency of the internal HSI RC.
1325 
  * @note   The calibration is used to compensate for the variations in voltage
 1325 
  * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
1326 
  *         and temperature that influence the frequency of the internal HSI RC.
 1326 
  *         (default is RCC_HSICALIBRATION_DEFAULT).
1327 
  * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
 1327 
  *         This parameter must be a number between 0 and 0x1F.
1328 
  *         (default is RCC_HSICALIBRATION_DEFAULT).
 1328 
  */
1329 
  *         This parameter must be a number between 0 and 0x1F.
 1329 
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
1330 
  */
 1330 
          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
1331 
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
 1331 
 
1332 
          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
 1332 
/**
1333 
 
 1333 
  * @}
1334 
/**
 1334 
  */
1335 
  * @}
 1335 
 
1336 
  */
 1336 
/** @defgroup RCC_LSI_Configuration  LSI Configuration
1337 
 
 1337 
  * @{
1338 
/** @defgroup RCC_LSI_Configuration  LSI Configuration
 1338 
  */
1339 
  * @{
 1339 
 
1340 
  */
 1340 
/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
1341 
 
 1341 
  * @note   After enabling the LSI, the application software should wait on
1342 
/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
 1342 
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
1343 
  * @note   After enabling the LSI, the application software should wait on
 1343 
  *         be used to clock the IWDG and/or the RTC.
1344 
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
 1344 
  */
1345 
  *         be used to clock the IWDG and/or the RTC.
 1345 
#define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
1346 
  */
 1346 
 
1347 
#define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
 1347 
/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
1348 
 
 1348 
  * @note   LSI can not be disabled if the IWDG is running.
1349 
/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
 1349 
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
1350 
  * @note   LSI can not be disabled if the IWDG is running.
 1350 
  *         clock cycles.
1351 
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
 1351 
  */
1352 
  *         clock cycles.
 1352 
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
1353 
  */
 1353 
 
1354 
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
 1354 
/**
1355 
 
 1355 
  * @}
1356 
/**
 1356 
  */
1357 
  * @}
 1357 
 
1358 
  */
 1358 
/** @defgroup RCC_HSE_Configuration HSE Configuration
1359 
 
 1359 
  * @{
1360 
/** @defgroup RCC_HSE_Configuration HSE Configuration
 1360 
  */
1361 
  * @{
 1361 
 
1362 
  */
 1362 
/**
1363 
 
 1363 
  * @brief  Macro to configure the External High Speed oscillator (HSE).
1364 
/**
 1364 
  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
1365 
  * @brief  Macro to configure the External High Speed oscillator (HSE).
 1365 
  *         supported by this macro. User should request a transition to HSE Off
1366 
  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
 1366 
  *         first and then HSE On or HSE Bypass.
1367 
  *         supported by this macro. User should request a transition to HSE Off
 1367 
  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
1368 
  *         first and then HSE On or HSE Bypass.
 1368 
  *         software should wait on HSERDY flag to be set indicating that HSE clock
1369 
  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
 1369 
  *         is stable and can be used to clock the PLL and/or system clock.
1370 
  *         software should wait on HSERDY flag to be set indicating that HSE clock
 1370 
  * @note   HSE state can not be changed if it is used directly or through the
1371 
  *         is stable and can be used to clock the PLL and/or system clock.
 1371 
  *         PLL as system clock. In this case, you have to select another source
1372 
  * @note   HSE state can not be changed if it is used directly or through the
 1372 
  *         of the system clock then change the HSE state (ex. disable it).
1373 
  *         PLL as system clock. In this case, you have to select another source
 1373 
  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
1374 
  *         of the system clock then change the HSE state (ex. disable it).
 1374 
  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
1375 
  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
 1375 
  *         was previously enabled you have to enable it again after calling this
1376 
  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
 1376 
  *         function.
1377 
  *         was previously enabled you have to enable it again after calling this
 1377 
  * @param  __STATE__ specifies the new state of the HSE.
1378 
  *         function.
 1378 
  *          This parameter can be one of the following values:
1379 
  * @param  __STATE__ specifies the new state of the HSE.
 1379 
  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
1380 
  *          This parameter can be one of the following values:
 1380 
  *                              6 HSE oscillator clock cycles.
1381 
  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
 1381 
  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
1382 
  *                              6 HSE oscillator clock cycles.
 1382 
  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
1383 
  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
 1383 
  */
1384 
  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
 1384 
#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
1385 
  */
 1385 
                    do{                                                     \
1386 
#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
 1386 
                      if ((__STATE__) == RCC_HSE_ON)                        \
1387 
                    do{                                                     \
 1387 
                      {                                                     \
1388 
                      if ((__STATE__) == RCC_HSE_ON)                        \
 1388 
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
1389 
                      {                                                     \
 1389 
                      }                                                     \
1390 
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
 1390 
                      else if ((__STATE__) == RCC_HSE_OFF)                  \
1391 
                      }                                                     \
 1391 
                      {                                                     \
1392 
                      else if ((__STATE__) == RCC_HSE_OFF)                  \
 1392 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
1393 
                      {                                                     \
 1393 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
1394 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
 1394 
                      }                                                     \
1395 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
 1395 
                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
1396 
                      }                                                     \
 1396 
                      {                                                     \
1397 
                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
 1397 
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
1398 
                      {                                                     \
 1398 
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
1399 
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
 1399 
                      }                                                     \
1400 
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
 1400 
                      else                                                  \
1401 
                      }                                                     \
 1401 
                      {                                                     \
1402 
                      else                                                  \
 1402 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
1403 
                      {                                                     \
 1403 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
1404 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
 1404 
                      }                                                     \
1405 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
 1405 
                    }while(0U)
1406 
                      }                                                     \
 1406 
 
1407 
                    }while(0U)
 1407 
/**
1408 
 
 1408 
  * @}
1409 
/**
 1409 
  */
1410 
  * @}
 1410 
 
1411 
  */
 1411 
/** @defgroup RCC_LSE_Configuration LSE Configuration
1412 
 
 1412 
  * @{
1413 
/** @defgroup RCC_LSE_Configuration LSE Configuration
 1413 
  */
1414 
  * @{
 1414 
 
1415 
  */
 1415 
/**
1416 
 
 1416 
  * @brief  Macro to configure the External Low Speed oscillator (LSE).
1417 
/**
 1417 
  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
1418 
  * @brief  Macro to configure the External Low Speed oscillator (LSE).
 1418 
  * @note   As the LSE is in the Backup domain and write access is denied to
1419 
  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
 1419 
  *         this domain after reset, you have to enable write access using
1420 
  * @note   As the LSE is in the Backup domain and write access is denied to
 1420 
  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
1421 
  *         this domain after reset, you have to enable write access using
 1421 
  *         (to be done once after reset).
1422 
  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
 1422 
  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
1423 
  *         (to be done once after reset).
 1423 
  *         software should wait on LSERDY flag to be set indicating that LSE clock
1424 
  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
 1424 
  *         is stable and can be used to clock the RTC.
1425 
  *         software should wait on LSERDY flag to be set indicating that LSE clock
 1425 
  * @param  __STATE__ specifies the new state of the LSE.
1426 
  *         is stable and can be used to clock the RTC.
 1426 
  *         This parameter can be one of the following values:
1427 
  * @param  __STATE__ specifies the new state of the LSE.
 1427 
  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
1428 
  *         This parameter can be one of the following values:
 1428 
  *                              6 LSE oscillator clock cycles.
1429 
  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
 1429 
  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
1430 
  *                              6 LSE oscillator clock cycles.
 1430 
  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
1431 
  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
 1431 
  */
1432 
  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
 1432 
#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
1433 
  */
 1433 
                    do{                                                     \
1434 
#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
 1434 
                      if ((__STATE__) == RCC_LSE_ON)                        \
1435 
                    do{                                                     \
 1435 
                      {                                                     \
1436 
                      if ((__STATE__) == RCC_LSE_ON)                        \
 1436 
                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
1437 
                      {                                                     \
 1437 
                      }                                                     \
1438 
                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
 1438 
                      else if ((__STATE__) == RCC_LSE_OFF)                  \
1439 
                      }                                                     \
 1439 
                      {                                                     \
1440 
                      else if ((__STATE__) == RCC_LSE_OFF)                  \
 1440 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
1441 
                      {                                                     \
 1441 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
1442 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
 1442 
                      }                                                     \
1443 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
 1443 
                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
1444 
                      }                                                     \
 1444 
                      {                                                     \
1445 
                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
 1445 
                        SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);                  \
1446 
                      {                                                     \
 1446 
                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
1447 
                        SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);                  \
 1447 
                      }                                                     \
1448 
                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
 1448 
                      else                                                  \
1449 
                      }                                                     \
 1449 
                      {                                                     \
1450 
                      else                                                  \
 1450 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
1451 
                      {                                                     \
 1451 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
1452 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
 1452 
                      }                                                     \
1453 
                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
 1453 
                    }while(0U)
1454 
                      }                                                     \
 1454 
 
1455 
                    }while(0U)
 1455 
/**
1456 
 
 1456 
  * @}
1457 
/**
 1457 
  */
1458 
  * @}
 1458 
 
1459 
  */
 1459 
/** @defgroup RCC_MSI_Configuration  MSI Configuration
1460 
 
 1460 
  * @{
1461 
/** @defgroup RCC_MSI_Configuration  MSI Configuration
 1461 
  */
1462 
  * @{
 1462 
 
1463 
  */
 1463 
/** @brief  Macro to enable Internal Multi Speed oscillator (MSI).
1464 
 
 1464 
  * @note   After enabling the MSI, the application software should wait on MSIRDY
1465 
/** @brief  Macro to enable Internal Multi Speed oscillator (MSI).
 1465 
  *         flag to be set indicating that MSI clock is stable and can be used as
1466 
  * @note   After enabling the MSI, the application software should wait on MSIRDY
 1466 
  *         system clock source.
1467 
  *         flag to be set indicating that MSI clock is stable and can be used as
 1467 
  */
1468 
  *         system clock source.
 1468 
#define __HAL_RCC_MSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE)
1469 
  */
 1469 
 
1470 
#define __HAL_RCC_MSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE)
 1470 
/** @brief  Macro to disable the Internal Multi Speed oscillator (MSI).
1471 
 
 1471 
  * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
1472 
/** @brief  Macro to disable the Internal Multi Speed oscillator (MSI).
 1472 
  *         It is used (enabled by hardware) as system clock source after startup
1473 
  * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
 1473 
  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
1474 
  *         It is used (enabled by hardware) as system clock source after startup
 1474 
  *         of the HSE used directly or indirectly as system clock (if the Clock
1475 
  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
 1475 
  *         Security System CSS is enabled).
1476 
  *         of the HSE used directly or indirectly as system clock (if the Clock
 1476 
  * @note   MSI can not be stopped if it is used as system clock source. In this case,
1477 
  *         Security System CSS is enabled).
 1477 
  *         you have to select another source of the system clock then stop the MSI.
1478 
  * @note   MSI can not be stopped if it is used as system clock source. In this case,
 1478 
  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
1479 
  *         you have to select another source of the system clock then stop the MSI.
 1479 
  *         clock cycles.
1480 
  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
 1480 
  */
1481 
  *         clock cycles.
 1481 
#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE)
1482 
  */
 1482 
 
1483 
#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE)
 1483 
/** @brief  Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
1484 
 
 1484 
  * @note   The calibration is used to compensate for the variations in voltage
1485 
/** @brief  Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
 1485 
  *         and temperature that influence the frequency of the internal MSI RC.
1486 
  * @note   The calibration is used to compensate for the variations in voltage
 1486 
  * @param  _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
1487 
  *         and temperature that influence the frequency of the internal MSI RC.
 1487 
  *         (default is RCC_MSICALIBRATION_DEFAULT).
1488 
  * @param  _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
 1488 
  *         This parameter must be a number between 0 and 0xFF.
1489 
  *         (default is RCC_MSICALIBRATION_DEFAULT).
 1489 
  */
1490 
  *         This parameter must be a number between 0 and 0xFF.
 1490 
#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
1491 
  */
 1491 
          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
1492 
#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
 1492 
 
1493 
          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
 1493 
/* @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
1494 
 
 1494 
  * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
1495 
/* @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
 1495 
  *           around 2.097 MHz. The MSI clock does not change after wake-up from
1496 
  * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
 1496 
  *           STOP mode.
1497 
  *           around 2.097 MHz. The MSI clock does not change after wake-up from
 1497 
  * @note    The MSI clock range can be modified on the fly.
1498 
  *           STOP mode.
 1498 
  * @param  _MSIRANGEVALUE_ specifies the MSI Clock range.
1499 
  * @note    The MSI clock range can be modified on the fly.
 1499 
  *   This parameter must be one of the following values:
1500 
  * @param  _MSIRANGEVALUE_ specifies the MSI Clock range.
 1500 
  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
1501 
  *   This parameter must be one of the following values:
 1501 
  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
1502 
  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
 1502 
  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
1503 
  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
 1503 
  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
1504 
  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
 1504 
  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
1505 
  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
 1505 
  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
1506 
  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
 1506 
  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
1507 
  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
 1507 
  */
1508 
  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
 1508 
#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
1509 
  */
 1509 
          RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
1510 
#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
 1510 
 
1511 
          RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
 1511 
/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
1512 
 
 1512 
  * @retval MSI clock range.
1513 
/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
 1513 
  *         This parameter must be one of the following values:
1514 
  * @retval MSI clock range.
 1514 
  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
1515 
  *         This parameter must be one of the following values:
 1515 
  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
1516 
  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
 1516 
  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
1517 
  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
 1517 
  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
1518 
  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
 1518 
  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
1519 
  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
 1519 
  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
1520 
  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
 1520 
  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
1521 
  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
 1521 
  */
1522 
  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
 1522 
#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
1523 
  */
 1523 
 
1524 
#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
 1524 
/**
1525 
 
 1525 
  * @}
1526 
/**
 1526 
  */
1527 
  * @}
 1527 
 
1528 
  */
 1528 
/** @defgroup RCC_PLL_Configuration PLL Configuration
1529 
 
 1529 
  * @{
1530 
/** @defgroup RCC_PLL_Configuration PLL Configuration
 1530 
  */
1531 
  * @{
 1531 
 
1532 
  */
 1532 
/** @brief Macro to enable the main PLL.
1533 
 
 1533 
  * @note   After enabling the main PLL, the application software should wait on
1534 
/** @brief Macro to enable the main PLL.
 1534 
  *         PLLRDY flag to be set indicating that PLL clock is stable and can
1535 
  * @note   After enabling the main PLL, the application software should wait on
 1535 
  *         be used as system clock source.
1536 
  *         PLLRDY flag to be set indicating that PLL clock is stable and can
 1536 
  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1537 
  *         be used as system clock source.
 1537 
  */
1538 
  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
 1538 
#define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1539 
  */
 1539 
 
1540 
#define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
 1540 
/** @brief Macro to disable the main PLL.
1541 
 
 1541 
  * @note   The main PLL can not be disabled if it is used as system clock source
1542 
/** @brief Macro to disable the main PLL.
 1542 
  */
1543 
  * @note   The main PLL can not be disabled if it is used as system clock source
 1543 
#define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1544 
  */
 1544 
 
1545 
#define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
 1545 
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
1546 
 
 1546 
  * @note   This function must be used only when the main PLL is disabled.
1547 
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
 1547 
  *
1548 
  * @note   This function must be used only when the main PLL is disabled.
 1548 
  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
1549 
  *
 1549 
  *          This parameter can be one of the following values:
1550 
  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
 1550 
  *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
1551 
  *          This parameter can be one of the following values:
 1551 
  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
1552 
  *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
 1552 
  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
1553 
  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
 1553 
  *          This parameter can be one of the following values:
1554 
  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
 1554 
  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
1555 
  *          This parameter can be one of the following values:
 1555 
  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
1556 
  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
 1556 
  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
1557 
  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
 1557 
  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
1558 
  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
 1558 
  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
1559 
  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
 1559 
  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
1560 
  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
 1560 
  *             @arg @ref RCC_PLL_MUL24  PLLVCO = PLL clock entry x 24
1561 
  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
 1561 
  *             @arg @ref RCC_PLL_MUL32  PLLVCO = PLL clock entry x 32
1562 
  *             @arg @ref RCC_PLL_MUL24  PLLVCO = PLL clock entry x 24
 1562 
  *             @arg @ref RCC_PLL_MUL48  PLLVCO = PLL clock entry x 48
1563 
  *             @arg @ref RCC_PLL_MUL32  PLLVCO = PLL clock entry x 32
 1563 
  * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
1564 
  *             @arg @ref RCC_PLL_MUL48  PLLVCO = PLL clock entry x 48
 1564 
  *          Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
1565 
  * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
 1565 
  *          in Range 3.
1566 
  *          Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
 1566 
  *
1567 
  *          in Range 3.
 1567 
  * @param  __PLLDIV__ specifies the division factor for PLL VCO input clock
1568 
  *
 1568 
  *          This parameter can be one of the following values:
1569 
  * @param  __PLLDIV__ specifies the division factor for PLL VCO input clock
 1569 
  *             @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
1570 
  *          This parameter can be one of the following values:
 1570 
  *             @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
1571 
  *             @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
 1571 
  *             @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
1572 
  *             @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
 1572 
  *
1573 
  *             @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
 1573 
  */
1574 
  *
 1574 
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
1575 
  */
 1575 
          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
1576 
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
 1576 
 
1577 
          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
 1577 
/** @brief  Get oscillator clock selected as PLL input clock
1578 
 
 1578 
  * @retval The clock source used for PLL entry. The returned value can be one
1579 
/** @brief  Get oscillator clock selected as PLL input clock
 1579 
  *         of the following:
1580 
  * @retval The clock source used for PLL entry. The returned value can be one
 1580 
  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
1581 
  *         of the following:
 1581 
  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
1582 
  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
 1582 
  */
1583 
  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
 1583 
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
1584 
  */
 1584 
 
1585 
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
 1585 
/**
1586 
 
 1586 
  * @}
1587 
/**
 1587 
  */
1588 
  * @}
 1588 
 
1589 
  */
 1589 
/** @defgroup RCC_Get_Clock_source Get Clock source
1590 
 
 1590 
  * @{
1591 
/** @defgroup RCC_Get_Clock_source Get Clock source
 1591 
  */
1592 
  * @{
 1592 
 
1593 
  */
 1593 
/**
1594 
 
 1594 
  * @brief  Macro to configure the system clock source.
1595 
/**
 1595 
  * @param  __SYSCLKSOURCE__ specifies the system clock source.
1596 
  * @brief  Macro to configure the system clock source.
 1596 
  *          This parameter can be one of the following values:
1597 
  * @param  __SYSCLKSOURCE__ specifies the system clock source.
 1597 
  *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
1598 
  *          This parameter can be one of the following values:
 1598 
  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
1599 
  *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
 1599 
  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
1600 
  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
 1600 
  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
1601 
  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
 1601 
  */
1602 
  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
 1602 
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
1603 
  */
 1603 
                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
1604 
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
 1604 
 
1605 
                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
 1605 
/** @brief  Macro to get the clock source used as system clock.
1606 
 
 1606 
  * @retval The clock source used as system clock. The returned value can be one
1607 
/** @brief  Macro to get the clock source used as system clock.
 1607 
  *         of the following:
1608 
  * @retval The clock source used as system clock. The returned value can be one
 1608 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
1609 
  *         of the following:
 1609 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
1610 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
 1610 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
1611 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
 1611 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
1612 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
 1612 
  */
1613 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
 1613 
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
1614 
  */
 1614 
 
1615 
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
 1615 
/**
1616 
 
 1616 
  * @}
1617 
/**
 1617 
  */
1618 
  * @}
 1618 
 
1619 
  */
 1619 
/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
1620 
 
 1620 
  * @{
1621 
/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
 1621 
  */
1622 
  * @{
 1622 
 
1623 
  */
 1623 
/** @brief  Macro to configure the MCO clock.
1624 
 
 1624 
  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
1625 
/** @brief  Macro to configure the MCO clock.
 1625 
  *          This parameter can be one of the following values:
1626 
  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
 1626 
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
1627 
  *          This parameter can be one of the following values:
 1627 
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
1628 
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
 1628 
  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
1629 
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
 1629 
  *            @arg @ref RCC_MCO1SOURCE_MSI          MSI oscillator clock selected as MCO clock
1630 
  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
 1630 
  *            @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
1631 
  *            @arg @ref RCC_MCO1SOURCE_MSI          MSI oscillator clock selected as MCO clock
 1631 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock selected as MCO clock
1632 
  *            @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
 1632 
  *            @arg @ref RCC_MCO1SOURCE_LSI          LSI clock selected as MCO clock
1633 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock selected as MCO clock
 1633 
  *            @arg @ref RCC_MCO1SOURCE_LSE          LSE clock selected as MCO clock
1634 
  *            @arg @ref RCC_MCO1SOURCE_LSI          LSI clock selected as MCO clock
 1634 
  * @param  __MCODIV__ specifies the MCO clock prescaler.
1635 
  *            @arg @ref RCC_MCO1SOURCE_LSE          LSE clock selected as MCO clock
 1635 
  *          This parameter can be one of the following values:
1636 
  * @param  __MCODIV__ specifies the MCO clock prescaler.
 1636 
  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
1637 
  *          This parameter can be one of the following values:
 1637 
  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
1638 
  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
 1638 
  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
1639 
  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
 1639 
  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
1640 
  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
 1640 
  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
1641 
  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
 1641 
  */
1642 
  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
 1642 
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1643 
  */
 1643 
                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1644 
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
 1644 
 
1645 
                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
 1645 
/**
1646 
 
 1646 
  * @}
1647 
/**
 1647 
  */
1648 
  * @}
 1648 
 
1649 
  */
 1649 
  /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
1650 
 
 1650 
  * @{
1651 
  /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
 1651 
  */
1652 
  * @{
 1652 
 
1653 
  */
 1653 
/** @brief Macro to configure the RTC clock (RTCCLK).
1654 
 
 1654 
  * @note   As the RTC clock configuration bits are in the Backup domain and write
1655 
/** @brief Macro to configure the RTC clock (RTCCLK).
 1655 
  *         access is denied to this domain after reset, you have to enable write
1656 
  * @note   As the RTC clock configuration bits are in the Backup domain and write
 1656 
  *         access using the Power Backup Access macro before to configure
1657 
  *         access is denied to this domain after reset, you have to enable write
 1657 
  *         the RTC clock source (to be done once after reset).
1658 
  *         access using the Power Backup Access macro before to configure
 1658 
  * @note   Once the RTC clock is configured it cannot be changed unless the
1659 
  *         the RTC clock source (to be done once after reset).
 1659 
  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
1660 
  * @note   Once the RTC clock is configured it cannot be changed unless the
 1660 
  *         a Power On Reset (POR).
1661 
  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
 1661 
  * @note   RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
1662 
  *         a Power On Reset (POR).
 1662 
  *
1663 
  * @note   RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
 1663 
  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
1664 
  *
 1664 
  *          This parameter can be one of the following values:
1665 
  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
 1665 
  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1666 
  *          This parameter can be one of the following values:
 1666 
  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1667 
  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
 1667 
  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1668 
  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
 1668 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
1669 
  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
 1669 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
1670 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
 1670 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
1671 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
 1671 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
1672 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
 1672 
  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
1673 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
 1673 
  *         work in STOP and STANDBY modes, and can be used as wakeup source.
1674 
  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
 1674 
  *         However, when the HSE clock is used as RTC clock source, the RTC
1675 
  *         work in STOP and STANDBY modes, and can be used as wakeup source.
 1675 
  *         cannot be used in STOP and STANDBY modes.
1676 
  *         However, when the HSE clock is used as RTC clock source, the RTC
 1676 
  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
1677 
  *         cannot be used in STOP and STANDBY modes.
 1677 
  *         RTC clock source).
1678 
  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
 1678 
  */
1679 
  *         RTC clock source).
 1679 
#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
1680 
  */
 1680 
            if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)          \
1681 
#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
 1681 
            {                                                                             \
1682 
            if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)          \
 1682 
              MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
1683 
            {                                                                             \
 1683 
            }                                                                             \
1684 
              MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
 1684 
          } while (0U)
1685 
            }                                                                             \
 1685 
 
1686 
          } while (0U)
 1686 
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
1687 
 
 1687 
                                      __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
1688 
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
 1688 
                                      RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
1689 
                                      __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
 1689 
                                    } while (0U)
1690 
                                      RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
 1690 
 
1691 
                                    } while (0U)
 1691 
/** @brief Macro to get the RTC clock source.
1692 
 
 1692 
  * @retval The clock source can be one of the following values:
1693 
/** @brief Macro to get the RTC clock source.
 1693 
  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1694 
  * @retval The clock source can be one of the following values:
 1694 
  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1695 
  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
 1695 
  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1696 
  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
 1696 
  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
1697 
  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
 1697 
  */
1698 
  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
 1698 
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
1699 
  */
 1699 
 
1700 
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
 1700 
/**
1701 
 
 1701 
  * @brief   Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
1702 
/**
 1702 
  *
1703 
  * @brief   Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
 1703 
  * @retval Returned value can be one of the following values:
1704 
  *
 1704 
  *         @arg @ref RCC_RTC_HSE_DIV_2  HSE divided by 2 selected as RTC clock
1705 
  * @retval Returned value can be one of the following values:
 1705 
  *         @arg @ref RCC_RTC_HSE_DIV_4  HSE divided by 4 selected as RTC clock
1706 
  *         @arg @ref RCC_RTC_HSE_DIV_2  HSE divided by 2 selected as RTC clock
 1706 
  *         @arg @ref RCC_RTC_HSE_DIV_8  HSE divided by 8 selected as RTC clock
1707 
  *         @arg @ref RCC_RTC_HSE_DIV_4  HSE divided by 4 selected as RTC clock
 1707 
  *         @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
1708 
  *         @arg @ref RCC_RTC_HSE_DIV_8  HSE divided by 8 selected as RTC clock
 1708 
  *
1709 
  *         @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
 1709 
  */
1710 
  *
 1710 
#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
1711 
  */
 1711 
 
1712 
#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
 1712 
/** @brief Macro to enable the the RTC clock.
1713 
 
 1713 
  * @note   These macros must be used only after the RTC clock source was selected.
1714 
/** @brief Macro to enable the the RTC clock.
 1714 
  */
1715 
  * @note   These macros must be used only after the RTC clock source was selected.
 1715 
#define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE)
1716 
  */
 1716 
 
1717 
#define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE)
 1717 
/** @brief Macro to disable the the RTC clock.
1718 
 
 1718 
  * @note  These macros must be used only after the RTC clock source was selected.
1719 
/** @brief Macro to disable the the RTC clock.
 1719 
  */
1720 
  * @note  These macros must be used only after the RTC clock source was selected.
 1720 
#define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE)
1721 
  */
 1721 
 
1722 
#define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE)
 1722 
/** @brief  Macro to force the Backup domain reset.
1723 
 
 1723 
  * @note   This function resets the RTC peripheral (including the backup registers)
1724 
/** @brief  Macro to force the Backup domain reset.
 1724 
  *         and the RTC clock source selection in RCC_CSR register.
1725 
  * @note   This function resets the RTC peripheral (including the backup registers)
 1725 
  * @note   The BKPSRAM is not affected by this reset.
1726 
  *         and the RTC clock source selection in RCC_CSR register.
 1726 
  */
1727 
  * @note   The BKPSRAM is not affected by this reset.
 1727 
#define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE)
1728 
  */
 1728 
 
1729 
#define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE)
 1729 
/** @brief  Macros to release the Backup domain reset.
1730 
 
 1730 
  */
1731 
/** @brief  Macros to release the Backup domain reset.
 1731 
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE)
1732 
  */
 1732 
 
1733 
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE)
 1733 
/**
1734 
 
 1734 
  * @}
1735 
/**
 1735 
  */
1736 
  * @}
 1736 
 
1737 
  */
 1737 
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1738 
 
 1738 
  * @brief macros to manage the specified RCC Flags and interrupts.
1739 
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
 1739 
  * @{
1740 
  * @brief macros to manage the specified RCC Flags and interrupts.
 1740 
  */
1741 
  * @{
 1741 
 
1742 
  */
 1742 
/** @brief Enable RCC interrupt.
1743 
 
 1743 
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1744 
/** @brief Enable RCC interrupt.
 1744 
  *          This parameter can be any combination of the following values:
1745 
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
 1745 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1746 
  *          This parameter can be any combination of the following values:
 1746 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
1747 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
 1747 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1748 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
 1748 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
1749 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
 1749 
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1750 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
 1750 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1751 
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
 1751 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
1752 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
 1752 
  */
1753 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
 1753 
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1754 
  */
 1754 
 
1755 
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
 1755 
/** @brief Disable RCC interrupt.
1756 
 
 1756 
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1757 
/** @brief Disable RCC interrupt.
 1757 
  *          This parameter can be any combination of the following values:
1758 
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
 1758 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1759 
  *          This parameter can be any combination of the following values:
 1759 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
1760 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
 1760 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1761 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
 1761 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
1762 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
 1762 
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1763 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
 1763 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1764 
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
 1764 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
1765 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
 1765 
  */
1766 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
 1766 
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1767 
  */
 1767 
 
1768 
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
 1768 
/** @brief Clear the RCC's interrupt pending bits.
1769 
 
 1769 
  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
1770 
/** @brief Clear the RCC's interrupt pending bits.
 1770 
  *          This parameter can be any combination of the following values:
1771 
  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
 1771 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1772 
  *          This parameter can be any combination of the following values:
 1772 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1773 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
 1773 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1774 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
 1774 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1775 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
 1775 
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1776 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
 1776 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1777 
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
 1777 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
1778 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
 1778 
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
1779 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
 1779 
  */
1780 
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
 1780 
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1781 
  */
 1781 
 
1782 
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
 1782 
/** @brief Check the RCC's interrupt has occurred or not.
1783 
 
 1783 
  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
1784 
/** @brief Check the RCC's interrupt has occurred or not.
 1784 
  *          This parameter can be one of the following values:
1785 
  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
 1785 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1786 
  *          This parameter can be one of the following values:
 1786 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1787 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
 1787 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1788 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
 1788 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1789 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
 1789 
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1790 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
 1790 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1791 
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
 1791 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
1792 
  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
 1792 
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
1793 
  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
 1793 
  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1794 
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
 1794 
  */
1795 
  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
 1795 
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1796 
  */
 1796 
 
1797 
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
 1797 
/** @brief Set RMVF bit to clear the reset flags.
1798 
 
 1798 
  *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1799 
/** @brief Set RMVF bit to clear the reset flags.
 1799 
  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1800 
  *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
 1800 
  */
1801 
  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
 1801 
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1802 
  */
 1802 
 
1803 
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
 1803 
/** @brief  Check RCC flag is set or not.
1804 
 
 1804 
  * @param  __FLAG__ specifies the flag to check.
1805 
/** @brief  Check RCC flag is set or not.
 1805 
  *          This parameter can be one of the following values:
1806 
  * @param  __FLAG__ specifies the flag to check.
 1806 
  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
1807 
  *          This parameter can be one of the following values:
 1807 
  *            @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.
1808 
  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
 1808 
  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
1809 
  *            @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.
 1809 
  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
1810 
  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
 1810 
  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
1811 
  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
 1811 
  *            @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)
1812 
  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
 1812 
  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
1813 
  *            @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)
 1813 
  *            @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
1814 
  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
 1814 
  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
1815 
  *            @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
 1815 
  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
1816 
  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
 1816 
  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
1817 
  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
 1817 
  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
1818 
  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
 1818 
  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
1819 
  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
 1819 
  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
1820 
  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
 1820 
  * @note (*) This bit is available in high and medium+ density devices only.
1821 
  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
 1821 
  * @retval The new state of __FLAG__ (TRUE or FALSE).
1822 
  * @note (*) This bit is available in high and medium+ density devices only.
 1822 
  */
1823 
  * @retval The new state of __FLAG__ (TRUE or FALSE).
 1823 
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1824 
  */
 1824 
 
1825 
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
 1825 
/**
1826 
 
 1826 
  * @}
1827 
/**
 1827 
  */
1828 
  * @}
 1828 
 
1829 
  */
 1829 
/**
1830 
 
 1830 
  * @}
1831 
/**
 1831 
  */
1832 
  * @}
 1832 
 
1833 
  */
 1833 
/* Include RCC HAL Extension module */
1834 
 
 1834 
#include "stm32l1xx_hal_rcc_ex.h"
1835 
/* Include RCC HAL Extension module */
 1835 
 
1836 
#include "stm32l1xx_hal_rcc_ex.h"
 1836 
/* Exported functions --------------------------------------------------------*/
1837 
 
 1837 
/** @addtogroup RCC_Exported_Functions
1838 
/* Exported functions --------------------------------------------------------*/
 1838 
  * @{
1839 
/** @addtogroup RCC_Exported_Functions
 1839 
  */
1840 
  * @{
 1840 
 
1841 
  */
 1841 
/** @addtogroup RCC_Exported_Functions_Group1
1842 
 
 1842 
  * @{
1843 
/** @addtogroup RCC_Exported_Functions_Group1
 1843 
  */
1844 
  * @{
 1844 
 
1845 
  */
 1845 
/* Initialization and de-initialization functions  ******************************/
1846 
 
 1846 
HAL_StatusTypeDef HAL_RCC_DeInit(void);
1847 
/* Initialization and de-initialization functions  ******************************/
 1847 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1848 
HAL_StatusTypeDef HAL_RCC_DeInit(void);
 1848 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
1849 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
 1849 
 
1850 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
 1850 
/**
1851 
 
 1851 
  * @}
1852 
/**
 1852 
  */
1853 
  * @}
 1853 
 
1854 
  */
 1854 
/** @addtogroup RCC_Exported_Functions_Group2
1855 
 
 1855 
  * @{
1856 
/** @addtogroup RCC_Exported_Functions_Group2
 1856 
  */
1857 
  * @{
 1857 
 
1858 
  */
 1858 
/* Peripheral Control functions  ************************************************/
1859 
 
 1859 
void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1860 
/* Peripheral Control functions  ************************************************/
 1860 
void              HAL_RCC_EnableCSS(void);
1861 
void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
 1861 
/* CSS NMI IRQ handler */
1862 
void              HAL_RCC_EnableCSS(void);
 1862 
void              HAL_RCC_NMI_IRQHandler(void);
1863 
/* CSS NMI IRQ handler */
 1863 
/* User Callbacks in non blocking mode (IT mode) */
1864 
void              HAL_RCC_NMI_IRQHandler(void);
 1864 
void              HAL_RCC_CSSCallback(void);
1865 
/* User Callbacks in non blocking mode (IT mode) */
 1865 
void              HAL_RCC_DisableCSS(void);
1866 
void              HAL_RCC_CSSCallback(void);
 1866 
uint32_t          HAL_RCC_GetSysClockFreq(void);
1867 
void              HAL_RCC_DisableCSS(void);
 1867 
uint32_t          HAL_RCC_GetHCLKFreq(void);
1868 
uint32_t          HAL_RCC_GetSysClockFreq(void);
 1868 
uint32_t          HAL_RCC_GetPCLK1Freq(void);
1869 
uint32_t          HAL_RCC_GetHCLKFreq(void);
 1869 
uint32_t          HAL_RCC_GetPCLK2Freq(void);
1870 
uint32_t          HAL_RCC_GetPCLK1Freq(void);
 1870 
void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1871 
uint32_t          HAL_RCC_GetPCLK2Freq(void);
 1871 
void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
1872 
void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
 1872 
 
1873 
void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
 1873 
/**
1874 
 
 1874 
  * @}
1875 
/**
 1875 
  */
1876 
  * @}
 1876 
 
1877 
  */
 1877 
/**
1878 
 
 1878 
  * @}
1879 
/**
 1879 
  */
1880 
  * @}
 1880 
 
1881 
  */
 1881 
/**
1882 
 
 1882 
  * @}
1883 
/**
 1883 
  */
1884 
  * @}
 1884 
 
1885 
  */
 1885 
/**
1886 
 
 1886 
  * @}
1887 
/**
 1887 
  */
1888 
  * @}
 1888 
 
1889 
  */
 1889 
#ifdef __cplusplus
1890 
 
 1890 
}
1891 
#ifdef __cplusplus
 1891 
#endif
1892 
}
 1892 
 
1893 
#endif
 1893 
#endif /* __STM32L1xx_HAL_RCC_H */
1894 
 
 1894 
 
1895 
#endif /* __STM32L1xx_HAL_RCC_H */
 1895 
 
1896 
 
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1897 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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1898 
 
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