WebSVN – DashDisplay – Diff – /branches/Dashboard_L152_v2/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c

 /**
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from
   *   user application:
   *      - SystemInit(): This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32l1xx.s" file.
   *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
   *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
   *
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software is licensed under terms that can be found in the LICENSE file
-  * the "License"; You may not use this file except in compliance with the
+  * in the root directory of this software component.
-  * License. You may obtain a copy of the License at:
+  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *                        opensource.org/licenses/BSD-3-Clause
+  *
-  *
+  ******************************************************************************
-  ******************************************************************************
+  */
-  */
+/** @addtogroup CMSIS
-/** @addtogroup CMSIS
+  * @{
-  * @{
+  */
-  */
+/** @addtogroup stm32l1xx_system
-/** @addtogroup stm32l1xx_system
+  * @{
-  * @{
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_Includes
-/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
-  * @{
+  */
-  */
+#include "stm32l1xx.h"
-#include "stm32l1xx.h"
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
-  * @{
+  */
-  */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_Defines
-/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
-  * @{
+  */
-  */
+#if !defined  (HSE_VALUE)
-#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
-                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
-#endif /* HSE_VALUE */
+#if !defined  (HSI_VALUE)
-#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Default value of the Internal oscillator in Hz.
-  #define HSI_VALUE    ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
-                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
-#endif /* HSI_VALUE */
+/*!< Uncomment the following line if you need to use external SRAM mounted
-/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
-     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
-/* #define DATA_IN_ExtSRAM */
+/* Note: Following vector table addresses must be defined in line with linker
-/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
-         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
-/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
-     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
-     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
-/* #define USER_VECT_TAB_ADDRESS */
+#if defined(USER_VECT_TAB_ADDRESS)
-#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
-/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
-     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
-/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
-#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
-#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
-                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
-                                                     This value must be a multiple of 0x200. */
+#else
-#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
-#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
-                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
-                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
-#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
-#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
-/******************************************************************************/
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_Macros
-/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
-  * @{
+  */
-  */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_Variables
-/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
-  * @{
+  */
-  */
+  /* This variable is updated in three ways:
-  /* This variable is updated in three ways:
+) by calling CMSIS function SystemCoreClockUpdate()
-) by calling CMSIS function SystemCoreClockUpdate()
+) by calling HAL API function HAL_RCC_GetHCLKFreq()
-) by calling HAL API function HAL_RCC_GetHCLKFreq()
+) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
-         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
-               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
-               variable is updated automatically.
+  */
-  */
+uint32_t SystemCoreClock        = 2097000U;
-uint32_t SystemCoreClock        = 2097000U;
+const uint8_t PLLMulTable[9]    = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-const uint8_t PLLMulTable[9]    = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+const uint8_t APBPrescTable[8]  = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-const uint8_t APBPrescTable[8]  = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
-  * @{
+  */
-  */
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
-#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void);
-  static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
-#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/** @addtogroup STM32L1xx_System_Private_Functions
-/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
-  * @{
+  */
-  */
+/**
-/**
+  * @brief  Setup the microcontroller system.
-  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
-  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
-  *         SystemCoreClock variable.
+  * @param  None
-  * @param  None
+  * @retval None
-  * @retval None
+  */
-  */
+void SystemInit (void)
-void SystemInit (void)
+{
-{
+#ifdef DATA_IN_ExtSRAM
-#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl();
-  SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
-#endif /* DATA_IN_ExtSRAM */
+  /* Configure the Vector Table location -------------------------------------*/
-  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
-#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#endif /* USER_VECT_TAB_ADDRESS */
-#endif /* USER_VECT_TAB_ADDRESS */
+}
-}
+/**
-/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
-  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
-  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
-  *         other parameters.
+  *
-  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
-  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
-  *         based on this variable will be incorrect.
+  *
-  *
+  * @note   - The system frequency computed by this function is not the real
-  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
-  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
-  *           constant and the selected clock source:
+  *
-  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+  *             value as defined by the MSI range.
-  *             value as defined by the MSI range.
+  *
-  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
-  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
-  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
-  *
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
-  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
-  *             in voltage and temperature.
+  *
-  *
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
-  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
-  *              have wrong result.
+  *
-  *
+  *         - The result of this function could be not correct when using fractional
-  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
-  *           value for HSE crystal.
+  * @param  None
-  * @param  None
+  * @retval None
-  * @retval None
+  */
-  */
+void SystemCoreClockUpdate (void)
-void SystemCoreClockUpdate (void)
+{
-{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+  /* Get SYSCLK source -------------------------------------------------------*/
-  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  switch (tmp)
-  switch (tmp)
+  {
-  {
+    case 0x00:  /* MSI used as system clock */
-    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
-      break;
+    case 0x04:  /* HSI used as system clock */
-    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
-      SystemCoreClock = HSI_VALUE;
+      break;
-      break;
+    case 0x08:  /* HSE used as system clock */
-    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
-      SystemCoreClock = HSE_VALUE;
+      break;
-      break;
+    case 0x0C:  /* PLL used as system clock */
-    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
-      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
-      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
-      plldiv = (plldiv >> 22) + 1;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      if (pllsource == 0x00)
-      if (pllsource == 0x00)
+      {
-      {
+        /* HSI oscillator clock selected as PLL clock entry */
-        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
-      }
+      else
-      else
+      {
-      {
+        /* HSE selected as PLL clock entry */
-        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
-      }
+      break;
-      break;
+    default: /* MSI used as system clock */
-    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
-      break;
+  }
-  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
-  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
-  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
-  SystemCoreClock >>= tmp;
+}
-}
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
-#ifdef DATA_IN_ExtSRAM
+/**
-/**
+  * @brief  Setup the external memory controller.
-  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
-  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
-  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
-  * @param  None
+  * @retval None
-  * @retval None
+  */
-  */
+void SystemInit_ExtMemCtl(void)
-void SystemInit_ExtMemCtl(void)
+{
-{
+  __IO uint32_t tmpreg = 0;
-  __IO uint32_t tmpreg = 0;
+  /* Flash 1 wait state */
-  /* Flash 1 wait state */
+  FLASH->ACR |= FLASH_ACR_LATENCY;
-  FLASH->ACR |= FLASH_ACR_LATENCY;
+  /* Power enable */
-  /* Power enable */
+  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  /* Delay after an RCC peripheral clock enabling */
-  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
-  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
+  /* Select the Voltage Range 1 (1.8 V) */
-  /* Select the Voltage Range 1 (1.8 V) */
+  PWR->CR = PWR_CR_VOS_0;
-  PWR->CR = PWR_CR_VOS_0;
+  /* Wait Until the Voltage Regulator is ready */
-  /* Wait Until the Voltage Regulator is ready */
+  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
-  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+  {
-  {
+  }
-  }
+/*-- GPIOs Configuration -----------------------------------------------------*/
-/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
-/*
+ +-------------------+--------------------+------------------+------------------+
- +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
- +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
- +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 |
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 |
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 |
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 |
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+
- | PD15 <-> FSMC_D1  |--------------------+
+ +-------------------+
- +-------------------+
+*/
-*/
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
-  RCC->AHBENR   = 0x000080D8;
+  /* Delay after an RCC peripheral clock enabling */
-  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
+  /* Connect PDx pins to FSMC Alternate function */
-  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */
-  /* Configure PDx pins in Alternate function mode */
+  GPIOD->MODER   = 0xAAAA0A0A;
-  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */
-  /* Configure PDx pins speed to 40 MHz */
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */
-  /* Configure PDx pins Output type to push-pull */
+  GPIOD->OTYPER  = 0x00000000;
-  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
-  /* No pull-up, pull-down for PDx pins */
+  GPIOD->PUPDR   = 0x00000000;
-  GPIOD->PUPDR   = 0x00000000;
+  /* Connect PEx pins to FSMC Alternate function */
-  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */
-  /* Configure PEx pins in Alternate function mode */
+  GPIOE->MODER   = 0xAAAA800A;
-  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */
-  /* Configure PEx pins speed to 40 MHz */
+  GPIOE->OSPEEDR = 0xFFFFC00F;
-  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */
-  /* Configure PEx pins Output type to push-pull */
+  GPIOE->OTYPER  = 0x00000000;
-  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */
-  /* No pull-up, pull-down for PEx pins */
+  GPIOE->PUPDR   = 0x00000000;
-  GPIOE->PUPDR   = 0x00000000;
+  /* Connect PFx pins to FSMC Alternate function */
-  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
-  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */
-  /* Configure PFx pins in Alternate function mode */
+  GPIOF->MODER   = 0xAA000AAA;
-  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */
-  /* Configure PFx pins speed to 40 MHz */
+  GPIOF->OSPEEDR = 0xFF000FFF;
-  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */
-  /* Configure PFx pins Output type to push-pull */
+  GPIOF->OTYPER  = 0x00000000;
-  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */
-  /* No pull-up, pull-down for PFx pins */
+  GPIOF->PUPDR   = 0x00000000;
-  GPIOF->PUPDR   = 0x00000000;
+  /* Connect PGx pins to FSMC Alternate function */
-  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
-  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */
-  /* Configure PGx pins in Alternate function mode */
+  GPIOG->MODER   = 0x00200AAA;
-  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */
-  /* Configure PGx pins speed to 40 MHz */
+  GPIOG->OSPEEDR = 0x00300FFF;
-  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */
-  /* Configure PGx pins Output type to push-pull */
+  GPIOG->OTYPER  = 0x00000000;
-  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */
-  /* No pull-up, pull-down for PGx pins */
+  GPIOG->PUPDR   = 0x00000000;
-  GPIOG->PUPDR   = 0x00000000;
+/*-- FSMC Configuration ------------------------------------------------------*/
-/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
-  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
-  RCC->AHBENR    = 0x400080D8;
+  /* Delay after an RCC peripheral clock enabling */
-  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+  (void)(tmpreg);
-  (void)(tmpreg);
+  /* Configure and enable Bank1_SRAM3 */
-  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
-/*
+  Bank1_SRAM3 is configured as follow:
-  Bank1_SRAM3 is configured as follow:
+  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
-  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
-  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
-  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
-*/
+}
-}
+#endif /* DATA_IN_ExtSRAM */
-#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
+/**
-/**
+  * @}
-  * @}
+  */
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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(root)/branches/Dashboard_L152_v2/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c – Rev 61 → 77