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68 
  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
 68 
  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
69 
  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */
 69 
  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */
70 
  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
 70 
  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
71 
  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
 71 
  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
72 
  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
 72 
  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
73 
  /* #define STM32L151xDX  */  /*!< STM32L151VD-X Devices */
 73 
  /* #define STM32L151xDX */   /*!< STM32L151VD-X Devices */
74 
  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
 74 
  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
75 
  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
 75 
  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
76 
  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
 76 
  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
77 
  /* #define STM32L152xC  */   /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
 77 
  /* #define STM32L152xC  */   /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
78 
  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
 78 
  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
79 
  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
 79 
  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
80 
  /* #define STM32L152xDX  */  /*!< STM32L152VD-X Devices */
 80 
  /* #define STM32L152xDX */   /*!< STM32L152VD-X Devices */
81 
  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
 81 
  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
82 
  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
 82 
  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
83 
  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
 83 
  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
84 
  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
 84 
  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
85 
  /* #define STM32L162xDX  */  /*!< STM32L162VD-X Devices */
 85 
  /* #define STM32L162xDX */   /*!< STM32L162VD-X Devices */
86 
  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
 86 
  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
87 
#endif
 87 
#endif
88 
 
 88 
 
89 
/*  Tip: To avoid modifying this file each time you need to switch between these
 89 
/*  Tip: To avoid modifying this file each time you need to switch between these
90 
        devices, you can define the device in your toolchain compiler preprocessor.
 90 
        devices, you can define the device in your toolchain compiler preprocessor.
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98 
   */
 98 
   */
99 
  /*#define USE_HAL_DRIVER */
 99 
  /*#define USE_HAL_DRIVER */
100 
#endif /* USE_HAL_DRIVER */
 100 
#endif /* USE_HAL_DRIVER */
101 
 
 101 
 
102 
/**
 102 
/**
103 
  * @brief CMSIS Device version number V2.3.1
 103 
  * @brief CMSIS Device version number V2.3.2
104 
  */
 104 
  */
105 
#define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */
 105 
#define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */
106 
#define __STM32L1xx_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
 106 
#define __STM32L1xx_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
107 
#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
 107 
#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
108 
#define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
108 
#define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
109 
#define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
 109 
#define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
110 
                                         |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
 110 
                                         |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
111 
                                         |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\
 111 
                                         |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\
112 
                                         |(__STM32L1xx_CMSIS_VERSION_RC))
 112 
                                         |(__STM32L1xx_CMSIS_VERSION_RC))
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213 
 
 213 
 
214 
#define READ_REG(REG)         ((REG))
 214 
#define READ_REG(REG)         ((REG))
215 
 
 215 
 
216 
#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 216 
#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
217 
 
 217 
 
- 
 
 218 
/* Use of CMSIS compiler intrinsics for register exclusive access */
- 
 
 219 
/* Atomic 32-bit register access macro to set one or several bits */
- 
 
 220 
#define ATOMIC_SET_BIT(REG, BIT)                             \
- 
 
 221 
  do {                                                       \
- 
 
 222 
    uint32_t val;                                            \
- 
 
 223 
    do {                                                     \
- 
 
 224 
      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
- 
 
 225 
    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
- 
 
 226 
  } while(0)
- 
 
 227 
 
- 
 
 228 
/* Atomic 32-bit register access macro to clear one or several bits */
- 
 
 229 
#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
- 
 
 230 
  do {                                                       \
- 
 
 231 
    uint32_t val;                                            \
- 
 
 232 
    do {                                                     \
- 
 
 233 
      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
- 
 
 234 
    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
- 
 
 235 
  } while(0)
- 
 
 236 
 
- 
 
 237 
/* Atomic 32-bit register access macro to clear and set one or several bits */
- 
 
 238 
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
- 
 
 239 
  do {                                                                     \
- 
 
 240 
    uint32_t val;                                                          \
- 
 
 241 
    do {                                                                   \
- 
 
 242 
      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
- 
 
 243 
    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
- 
 
 244 
  } while(0)
- 
 
 245 
 
- 
 
 246 
/* Atomic 16-bit register access macro to set one or several bits */
- 
 
 247 
#define ATOMIC_SETH_BIT(REG, BIT)                            \
- 
 
 248 
  do {                                                       \
- 
 
 249 
    uint16_t val;                                            \
- 
 
 250 
    do {                                                     \
- 
 
 251 
      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
- 
 
 252 
    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
- 
 
 253 
  } while(0)
- 
 
 254 
 
- 
 
 255 
/* Atomic 16-bit register access macro to clear one or several bits */
- 
 
 256 
#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
- 
 
 257 
  do {                                                       \
- 
 
 258 
    uint16_t val;                                            \
- 
 
 259 
    do {                                                     \
- 
 
 260 
      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
- 
 
 261 
    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
- 
 
 262 
  } while(0)
- 
 
 263 
 
- 
 
 264 
/* Atomic 16-bit register access macro to clear and set one or several bits */
- 
 
 265 
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
- 
 
 266 
  do {                                                                     \
- 
 
 267 
    uint16_t val;                                                          \
- 
 
 268 
    do {                                                                   \
- 
 
 269 
      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
- 
 
 270 
    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
- 
 
 271 
  } while(0)
- 
 
 272 
 
218 
#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
273 
#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
219 
 
 274 
 
220 
 
 275 
 
221 
/**
 276 
/**
222 
  * @}
 277 
  * @}