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| Rev 50 | Rev 61 | ||
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| 669 | #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ |
669 | #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ |
| 670 | #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
670 | #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
| 671 | #define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */ |
671 | #define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */ |
| 672 | #define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */ |
672 | #define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */ |
| 673 | #define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */ |
673 | #define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */ |
| - | 674 | #define FLASH_END (0x0807FFFFUL) /*!< Program end FLASH address for Cat5 */ |
|
| 674 | #define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */ |
675 | #define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */ |
| 675 | 676 | ||
| 676 | /*!< Peripheral memory map */ |
677 | /*!< Peripheral memory map */ |
| 677 | #define APB1PERIPH_BASE PERIPH_BASE |
678 | #define APB1PERIPH_BASE PERIPH_BASE |
| 678 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
679 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| Line 846... | Line 847... | ||
| 846 | 847 | ||
| 847 | /** @addtogroup Exported_constants |
848 | /** @addtogroup Exported_constants |
| 848 | * @{ |
849 | * @{ |
| 849 | */ |
850 | */ |
| 850 | 851 | ||
| - | 852 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 853 | * @{ |
|
| - | 854 | */ |
|
| - | 855 | #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ |
|
| - | 856 | ||
| - | 857 | /** |
|
| - | 858 | * @} |
|
| - | 859 | */ |
|
| - | 860 | ||
| 851 | /** @addtogroup Peripheral_Registers_Bits_Definition |
861 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 852 | * @{ |
862 | * @{ |
| 853 | */ |
863 | */ |
| 854 | 864 | ||
| 855 | /******************************************************************************/ |
865 | /******************************************************************************/ |
| Line 3189... | Line 3199... | ||
| 3189 | /* */ |
3199 | /* */ |
| 3190 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
3200 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
| 3191 | /* (FLASH, DATA_EEPROM, OB) */ |
3201 | /* (FLASH, DATA_EEPROM, OB) */ |
| 3192 | /* */ |
3202 | /* */ |
| 3193 | /******************************************************************************/ |
3203 | /******************************************************************************/ |
| - | 3204 | /* |
|
| - | 3205 | * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie) |
|
| - | 3206 | */ |
|
| - | 3207 | #define FLASH_CUT5 |
|
| 3194 | 3208 | ||
| 3195 | /******************* Bit definition for FLASH_ACR register ******************/ |
3209 | /******************* Bit definition for FLASH_ACR register ******************/ |
| 3196 | #define FLASH_ACR_LATENCY_Pos (0U) |
3210 | #define FLASH_ACR_LATENCY_Pos (0U) |
| 3197 | #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
3211 | #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| 3198 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
3212 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
| Line 6097... | Line 6111... | ||
| 6097 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
6111 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
| 6098 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
6112 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
| 6099 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
6113 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
| 6100 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
6114 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
| 6101 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
6115 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
| 6102 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */ |
6116 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */ |
| 6103 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */ |
6117 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */ |
| 6104 | 6118 | ||
| 6105 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
6119 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
| 6106 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
6120 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
| 6107 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
6121 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| 6108 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
6122 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
| Line 6273... | Line 6287... | ||
| 6273 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
6287 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
| 6274 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
6288 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
| 6275 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
6289 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
| 6276 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
6290 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
| 6277 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
6291 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
| 6278 | 6292 | ||
| 6279 | /******************************************************************************/ |
6293 | /******************************************************************************/ |
| 6280 | /* */ |
6294 | /* */ |
| 6281 | /* Routing Interface (RI) */ |
6295 | /* Routing Interface (RI) */ |
| 6282 | /* */ |
6296 | /* */ |
| 6283 | /******************************************************************************/ |
6297 | /******************************************************************************/ |