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| Rev 50 | Rev 61 | ||
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| Line 648... | Line 648... | ||
| 648 | #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ |
648 | #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ |
| 649 | #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
649 | #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
| 650 | #define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */ |
650 | #define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */ |
| 651 | #define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */ |
651 | #define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */ |
| 652 | #define FLASH_BANK2_END (0x0806FFFFUL) /*!< Program end FLASH BANK2 address */ |
652 | #define FLASH_BANK2_END (0x0806FFFFUL) /*!< Program end FLASH BANK2 address */ |
| - | 653 | #define FLASH_END (0x0806FFFFUL) /*!< Program end FLASH address for Cat6 */ |
|
| 653 | #define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */ |
654 | #define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */ |
| 654 | 655 | ||
| 655 | /*!< Peripheral memory map */ |
656 | /*!< Peripheral memory map */ |
| 656 | #define APB1PERIPH_BASE PERIPH_BASE |
657 | #define APB1PERIPH_BASE PERIPH_BASE |
| 657 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
658 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| Line 823... | Line 824... | ||
| 823 | 824 | ||
| 824 | /** @addtogroup Exported_constants |
825 | /** @addtogroup Exported_constants |
| 825 | * @{ |
826 | * @{ |
| 826 | */ |
827 | */ |
| 827 | 828 | ||
| - | 829 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 830 | * @{ |
|
| - | 831 | */ |
|
| - | 832 | #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ |
|
| - | 833 | ||
| - | 834 | /** |
|
| - | 835 | * @} |
|
| - | 836 | */ |
|
| - | 837 | ||
| 828 | /** @addtogroup Peripheral_Registers_Bits_Definition |
838 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 829 | * @{ |
839 | * @{ |
| 830 | */ |
840 | */ |
| 831 | 841 | ||
| 832 | /******************************************************************************/ |
842 | /******************************************************************************/ |
| Line 3059... | Line 3069... | ||
| 3059 | /* */ |
3069 | /* */ |
| 3060 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
3070 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
| 3061 | /* (FLASH, DATA_EEPROM, OB) */ |
3071 | /* (FLASH, DATA_EEPROM, OB) */ |
| 3062 | /* */ |
3072 | /* */ |
| 3063 | /******************************************************************************/ |
3073 | /******************************************************************************/ |
| - | 3074 | /* |
|
| - | 3075 | * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie) |
|
| - | 3076 | */ |
|
| - | 3077 | #define FLASH_CUT6 |
|
| 3064 | 3078 | ||
| 3065 | /******************* Bit definition for FLASH_ACR register ******************/ |
3079 | /******************* Bit definition for FLASH_ACR register ******************/ |
| 3066 | #define FLASH_ACR_LATENCY_Pos (0U) |
3080 | #define FLASH_ACR_LATENCY_Pos (0U) |
| 3067 | #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
3081 | #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| 3068 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
3082 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
| Line 5958... | Line 5972... | ||
| 5958 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
5972 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
| 5959 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
5973 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
| 5960 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
5974 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
| 5961 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
5975 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
| 5962 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
5976 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
| 5963 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */ |
5977 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */ |
| 5964 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */ |
5978 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */ |
| 5965 | 5979 | ||
| 5966 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
5980 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
| 5967 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
5981 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
| 5968 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
5982 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| 5969 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
5983 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
| Line 6134... | Line 6148... | ||
| 6134 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
6148 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
| 6135 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
6149 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
| 6136 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
6150 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
| 6137 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
6151 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
| 6138 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
6152 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
| 6139 | 6153 | ||
| 6140 | /******************************************************************************/ |
6154 | /******************************************************************************/ |
| 6141 | /* */ |
6155 | /* */ |
| 6142 | /* Routing Interface (RI) */ |
6156 | /* Routing Interface (RI) */ |
| 6143 | /* */ |
6157 | /* */ |
| 6144 | /******************************************************************************/ |
6158 | /******************************************************************************/ |