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| Rev 50 | Rev 61 | ||
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| Line 690... | Line 690... | ||
| 690 | #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ |
690 | #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ |
| 691 | #define FSMC_BASE (0x60000000UL) /*!< FSMC base address */ |
691 | #define FSMC_BASE (0x60000000UL) /*!< FSMC base address */ |
| 692 | #define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */ |
692 | #define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */ |
| 693 | #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ |
693 | #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ |
| 694 | #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
694 | #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
| - | 695 | #define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */ |
|
| 695 | #define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */ |
696 | #define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */ |
| 696 | #define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */ |
697 | #define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */ |
| 697 | #define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */ |
698 | #define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */ |
| 698 | #define FLASH_EEPROM_END (0x08082FFFUL) /*!< FLASH EEPROM end address (12KB) */ |
699 | #define FLASH_EEPROM_END (0x08082FFFUL) /*!< FLASH EEPROM end address (12KB) */ |
| 699 | 700 | ||
| Line 880... | Line 881... | ||
| 880 | 881 | ||
| 881 | /** @addtogroup Exported_constants |
882 | /** @addtogroup Exported_constants |
| 882 | * @{ |
883 | * @{ |
| 883 | */ |
884 | */ |
| 884 | 885 | ||
| - | 886 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 887 | * @{ |
|
| - | 888 | */ |
|
| - | 889 | #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ |
|
| - | 890 | ||
| - | 891 | /** |
|
| - | 892 | * @} |
|
| - | 893 | */ |
|
| - | 894 | ||
| 885 | /** @addtogroup Peripheral_Registers_Bits_Definition |
895 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 886 | * @{ |
896 | * @{ |
| 887 | */ |
897 | */ |
| 888 | 898 | ||
| 889 | /******************************************************************************/ |
899 | /******************************************************************************/ |
| Line 3158... | Line 3168... | ||
| 3158 | /* */ |
3168 | /* */ |
| 3159 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
3169 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
| 3160 | /* (FLASH, DATA_EEPROM, OB) */ |
3170 | /* (FLASH, DATA_EEPROM, OB) */ |
| 3161 | /* */ |
3171 | /* */ |
| 3162 | /******************************************************************************/ |
3172 | /******************************************************************************/ |
| - | 3173 | /* |
|
| - | 3174 | * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie) |
|
| - | 3175 | */ |
|
| - | 3176 | #define FLASH_CUT4 |
|
| 3163 | 3177 | ||
| 3164 | /******************* Bit definition for FLASH_ACR register ******************/ |
3178 | /******************* Bit definition for FLASH_ACR register ******************/ |
| 3165 | #define FLASH_ACR_LATENCY_Pos (0U) |
3179 | #define FLASH_ACR_LATENCY_Pos (0U) |
| 3166 | #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
3180 | #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| 3167 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
3181 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
| Line 3350... | Line 3364... | ||
| 3350 | #define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ |
3364 | #define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ |
| 3351 | #define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */ |
3365 | #define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */ |
| 3352 | #define FSMC_BCRx_ASYNCWAIT_Pos (15U) |
3366 | #define FSMC_BCRx_ASYNCWAIT_Pos (15U) |
| 3353 | #define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
3367 | #define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
| 3354 | #define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */ |
3368 | #define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */ |
| - | 3369 | #define FSMC_BCRx_CPSIZE_Pos (16U) |
|
| - | 3370 | #define FSMC_BCRx_CPSIZE_Msk (0x7UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */ |
|
| - | 3371 | #define FSMC_BCRx_CPSIZE FSMC_BCRx_CPSIZE_Msk /*!< Cellular RAM page size */ |
|
| - | 3372 | #define FSMC_BCRx_CPSIZE_0 (0x1UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */ |
|
| - | 3373 | #define FSMC_BCRx_CPSIZE_1 (0x2UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */ |
|
| - | 3374 | #define FSMC_BCRx_CPSIZE_2 (0x4UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */ |
|
| 3355 | #define FSMC_BCRx_CBURSTRW_Pos (19U) |
3375 | #define FSMC_BCRx_CBURSTRW_Pos (19U) |
| 3356 | #define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ |
3376 | #define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ |
| 3357 | #define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */ |
3377 | #define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */ |
| 3358 | 3378 | ||
| 3359 | /****************** Bit definition for FSMC_BTRx register (x=1..4) ******************/ |
3379 | /****************** Bit definition for FSMC_BTRx register (x=1..4) ******************/ |
| Line 6587... | Line 6607... | ||
| 6587 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
6607 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
| 6588 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
6608 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
| 6589 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
6609 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
| 6590 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
6610 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
| 6591 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
6611 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
| 6592 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */ |
6612 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */ |
| 6593 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */ |
6613 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */ |
| 6594 | 6614 | ||
| 6595 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
6615 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
| 6596 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
6616 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
| 6597 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
6617 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| 6598 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
6618 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
| Line 6763... | Line 6783... | ||
| 6763 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
6783 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
| 6764 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
6784 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
| 6765 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
6785 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
| 6766 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
6786 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
| 6767 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
6787 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
| 6768 | 6788 | ||
| 6769 | /******************************************************************************/ |
6789 | /******************************************************************************/ |
| 6770 | /* */ |
6790 | /* */ |
| 6771 | /* Routing Interface (RI) */ |
6791 | /* Routing Interface (RI) */ |
| 6772 | /* */ |
6792 | /* */ |
| 6773 | /******************************************************************************/ |
6793 | /******************************************************************************/ |