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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /* |
| 2 | * $Header: c:\\cygwin\\cvsroot/Vert03/vertlib/print_vhdl.h,v 1.1.1.1 2003/11/04 23:34:57 |
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| 3 | * mjames Exp $ |
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| 4 | * |
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| 5 | * $Log: print_vhdl.h,v $ |
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| 6 | * Revision 1.1.1.1 2003/11/04 23:34:57 mjames |
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| 7 | * Imported into local repositrory |
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| 8 | * |
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| 9 | * Revision 1.5 2002/08/23 14:18:24 mjames |
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| 10 | * Removed some constants to the header file |
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| 11 | * |
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| 12 | * Revision 1.4 2001/10/31 22:20:13 mjames |
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| 13 | * Tidying up problematical comments caused by CVS |
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| 14 | * 'intelligent' comment guessing |
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| 15 | * |
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| 16 | * Revision 1.3 2001/06/06 12:10:19 mjames |
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| 17 | * Move from HPUX |
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| 18 | * |
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| 19 | * Revision 1.2 2000/11/29 23:25:39 mjames |
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| 20 | * Corrected a failure to cope with integer type ports on entities |
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| 21 | * in acf_yacc.y |
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| 22 | * |
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| 23 | * Altered the elaborate command to call up the template command aw well |
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| 24 | * |
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| 25 | * Altered equivalent pins handler to cope with the absence of any templates |
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| 26 | * |
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| 27 | * Altered printout routines to use correct datatype for expansion of |
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| 28 | * VHDL constants |
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| 29 | * |
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| 30 | * Revision 1.1.1.1 2000/10/19 21:58:39 mjames |
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| 31 | * Mike put it here |
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| 32 | * |
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| 33 | * |
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| 34 | * Revision 1.13 2000/10/04 10:37:15 10:37:15 mjames (Mike James) |
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| 35 | * Modified for Vertical2 : support COMPONENTS and SIGNALS |
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| 36 | * |
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| 37 | * Revision 1.13 2000/10/04 10:37:15 10:37:15 mjames (Mike James) |
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| 38 | * Part of Release PSAVAT01 |
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| 39 | * |
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| 40 | * Revision 1.12 2000/10/02 11:04:18 11:04:18 mjames (Mike James) |
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| 41 | * new_vhdl |
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| 42 | * |
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| 43 | * Revision 1.11 2000/09/27 14:42:31 14:42:31 mjames (Mike James) |
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| 44 | * Part of Release Sep_27_ST_2000 |
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| 45 | * |
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| 46 | * Revision 1.10 2000/09/21 10:16:00 10:16:00 mjames (Mike James) |
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| 47 | * Part of Release Sep21Alpha |
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| 48 | * |
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| 49 | * Revision 1.9 2000/08/25 09:57:24 09:57:24 mjames (Mike James) |
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| 50 | * Part of Release Aug25_alpha |
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| 51 | * |
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| 52 | * Revision 1.8 2000/08/16 08:57:40 08:57:40 mjames (Mike James) |
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| 53 | * Part of Release CD01_Aug2000 |
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| 54 | * |
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| 55 | * Revision 1.7 2000/08/14 14:45:19 14:45:19 mjames (Mike James) |
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| 56 | * Part of Release Aug_14_2000 |
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| 57 | * |
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| 58 | * Revision 1.6 2000/08/11 08:30:40 08:30:40 mjames (Mike James) |
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| 59 | * Part of Release Aug_11_2000 |
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| 60 | * |
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| 61 | * Revision 1.5 2000/08/09 10:31:57 10:31:57 mjames (Mike James) |
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| 62 | * Part of Release Aug__9_2000 |
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| 63 | * |
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| 64 | * Revision 1.4 2000/05/31 11:43:11 11:43:11 mjames (Mike James) |
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| 65 | * Part of Release May_31_2000 |
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| 66 | * |
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| 67 | * Revision 1.3 2000/05/08 17:01:47 17:01:47 mjames (Mike James) |
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| 68 | * Part of Release May__8_2000 |
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| 69 | * |
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| 70 | * Revision 1.2 2000/05/08 16:59:40 16:59:40 mjames (Mike James) |
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| 71 | * Part of Release May__8_2000 |
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| 72 | * |
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| 73 | * Revision 1.1 99/11/23 13:52:31 13:52:31 mjames (Mike James) |
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| 74 | * Initial revision |
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| 75 | * |
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| 76 | * Revision 1.1 1999/11/02 10:04:23 Mike_on_acorn |
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| 77 | * Initial revision |
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| 78 | */ |
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| 79 | |||
| 80 | /* listing width */ |
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| 81 | #define MAXWIDTH 60 |
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| 82 | |||
| 83 | /* lessthan this pin count, connector pins are seen as wires not busses |
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| 84 | in both VHDL and verilog bundles */ |
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| 85 | |||
| 86 | #define MINBUNDLE 5 |
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| 87 | |||
| 88 | extern char *make_vhdl_name (char *buffer, char *str); |
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| 89 | |||
| 90 | /* prints out the used subrange */ |
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| 91 | extern void decode_vhdl_bus (FILE *f, vhdl_t *vhdl, generic_print_style recurse_generics); |
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| 92 | |||
| 93 | /* prints out the bus type and range if needed */ |
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| 94 | extern void decode_vhdl_type (FILE *f, vhdl_t *vhdl, generic_print_style recurse_generics); |
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| 95 | |||
| 96 | extern void print_VHDL_component (FILE *f, socket_t *dev, int All); |
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| 97 | |||
| 98 | extern void print_VHDL_instance (FILE *f, socket_t *dev, int All); |
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| 99 | |||
| 100 | extern void produce_VHDL (FILE *f, char *entityname, char *template); |