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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | // vertical verilog |
| 2 | /* Altera EPLD / PCB / VHDL tools */ |
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| 3 | /* (c) Philips Semiconductors Southampton 1996-2001 */ |
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| 4 | |||
| 5 | /* by: Mike James (Mike.D.James@philips.com) */ |
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| 6 | /* package version: 15.2a Package compiled: Jan 16 2002 at 22:03:40*/ |
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| 7 | |||
| 8 | /* Produced by WRITE VLOG (PC-CygWin) |
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| 9 | * at 22:06:54 on 16/01/2002 |
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| 10 | |||
| 11 | */ |
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| 12 | module top ( |
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| 13 | ); |
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| 14 | /* synthesis syn_partition = "board" */ |
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| 15 | |||
| 16 | |||
| 17 | /* Bundle signals */ |
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| 18 | |||
| 19 | /* end bundle signals */ |
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| 20 | |||
| 21 | /* Buffered signals */ |
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| 22 | |||
| 23 | /* end Buffered signals */ |
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| 24 | |||
| 25 | endmodule |
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| 26 | |||
| 27 | |||
| 28 | // vertical end; |