WebSVN – Vertical – Blame – /trunk/verilog/d.g

Rev	Author	Line No.	Line
2	mjames	1	// vertical verilog
		2	/* Altera EPLD / PCB / VHDL tools */
		3	/* (c) Philips Semiconductors Southampton 1996-2001 */
		4
		5	/* by: Mike James (Mike.D.James@philips.com) */
		6	/* package version: 14.6a Regexp compiled: Nov 28 2001 at 10:13:27*/
		7
		8	/* Produced by WRITE VLOG (PC-CygWin)
		9	* at 10:59:37 on 28/11/2001
		10
		11	*/
		12	module top (
		13	);
		14	/* synthesis syn_partition = "board" */
		15
		16
		17	/* Bundle signals */
		18
		19	/* end bundle signals */
		20
		21	/* Buffered signals */
		22
		23	/* end Buffered signals */
		24
		25	endmodule
		26
		27
		28	// vertical end;

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