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<?xml version="1.0" encoding="utf-8" standalone="no"?>
2 
<device schemaVersion="1.1"
3 
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
4 
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
5 
  <cpu>                                                           <!-- details about the cpu embedded in the device -->
6 
    <name>CM3</name>
7 
    <revision>r1p1</revision>
8 
    <endian>little</endian>
9 
    <nvicPrioBits>4</nvicPrioBits>
10 
  </cpu>
11 
  <name>STM32F103</name>
12 
  <version>1.0</version>
13 
  <description>STM32F103</description>
14 
  <!--Bus Interface Properties-->
15 
  <!--Cortex-M3 is byte addressable-->
16 
  <addressUnitBits>8</addressUnitBits>
17 
  <!--the maximum data bit width accessible within a single transfer-->
18 
  <width>32</width>
19 
  <!--Register Default Properties-->
20 
  <size>0x20</size>
21 
  <resetValue>0x0</resetValue>
22 
  <resetMask>0xFFFFFFFF</resetMask>
23 
  <peripherals>
24 
    <peripheral>
25 
      <name>FSMC</name>
26 
      <description>Flexible static memory controller</description>
27 
      <groupName>FSMC</groupName>
28 
      <baseAddress>0xA0000000</baseAddress>
29 
      <addressBlock>
30 
        <offset>0x0</offset>
31 
        <size>0x1000</size>
32 
        <usage>registers</usage>
33 
      </addressBlock>
34 
      <interrupt>
35 
        <name>FSMC</name>
36 
        <description>FSMC global interrupt</description>
37 
        <value>48</value>
38 
      </interrupt>
39 
      <registers>
40 
        <register>
41 
          <name>BCR1</name>
42 
          <displayName>BCR1</displayName>
43 
          <description>SRAM/NOR-Flash chip-select control register
44 
          1</description>
45 
          <addressOffset>0x0</addressOffset>
46 
          <size>0x20</size>
47 
          <access>read-write</access>
48 
          <resetValue>0x000030D0</resetValue>
49 
          <fields>
50 
            <field>
51 
              <name>CBURSTRW</name>
52 
              <description>CBURSTRW</description>
53 
              <bitOffset>19</bitOffset>
54 
              <bitWidth>1</bitWidth>
55 
            </field>
56 
            <field>
57 
              <name>ASYNCWAIT</name>
58 
              <description>ASYNCWAIT</description>
59 
              <bitOffset>15</bitOffset>
60 
              <bitWidth>1</bitWidth>
61 
            </field>
62 
            <field>
63 
              <name>EXTMOD</name>
64 
              <description>EXTMOD</description>
65 
              <bitOffset>14</bitOffset>
66 
              <bitWidth>1</bitWidth>
67 
            </field>
68 
            <field>
69 
              <name>WAITEN</name>
70 
              <description>WAITEN</description>
71 
              <bitOffset>13</bitOffset>
72 
              <bitWidth>1</bitWidth>
73 
            </field>
74 
            <field>
75 
              <name>WREN</name>
76 
              <description>WREN</description>
77 
              <bitOffset>12</bitOffset>
78 
              <bitWidth>1</bitWidth>
79 
            </field>
80 
            <field>
81 
              <name>WAITCFG</name>
82 
              <description>WAITCFG</description>
83 
              <bitOffset>11</bitOffset>
84 
              <bitWidth>1</bitWidth>
85 
            </field>
86 
            <field>
87 
              <name>WAITPOL</name>
88 
              <description>WAITPOL</description>
89 
              <bitOffset>9</bitOffset>
90 
              <bitWidth>1</bitWidth>
91 
            </field>
92 
            <field>
93 
              <name>BURSTEN</name>
94 
              <description>BURSTEN</description>
95 
              <bitOffset>8</bitOffset>
96 
              <bitWidth>1</bitWidth>
97 
            </field>
98 
            <field>
99 
              <name>FACCEN</name>
100 
              <description>FACCEN</description>
101 
              <bitOffset>6</bitOffset>
102 
              <bitWidth>1</bitWidth>
103 
            </field>
104 
            <field>
105 
              <name>MWID</name>
106 
              <description>MWID</description>
107 
              <bitOffset>4</bitOffset>
108 
              <bitWidth>2</bitWidth>
109 
            </field>
110 
            <field>
111 
              <name>MTYP</name>
112 
              <description>MTYP</description>
113 
              <bitOffset>2</bitOffset>
114 
              <bitWidth>2</bitWidth>
115 
            </field>
116 
            <field>
117 
              <name>MUXEN</name>
118 
              <description>MUXEN</description>
119 
              <bitOffset>1</bitOffset>
120 
              <bitWidth>1</bitWidth>
121 
            </field>
122 
            <field>
123 
              <name>MBKEN</name>
124 
              <description>MBKEN</description>
125 
              <bitOffset>0</bitOffset>
126 
              <bitWidth>1</bitWidth>
127 
            </field>
128 
          </fields>
129 
        </register>
130 
        <register>
131 
          <name>BTR1</name>
132 
          <displayName>BTR1</displayName>
133 
          <description>SRAM/NOR-Flash chip-select timing register
134 
          1</description>
135 
          <addressOffset>0x4</addressOffset>
136 
          <size>0x20</size>
137 
          <access>read-write</access>
138 
          <resetValue>0xFFFFFFFF</resetValue>
139 
          <fields>
140 
            <field>
141 
              <name>ACCMOD</name>
142 
              <description>ACCMOD</description>
143 
              <bitOffset>28</bitOffset>
144 
              <bitWidth>2</bitWidth>
145 
            </field>
146 
            <field>
147 
              <name>DATLAT</name>
148 
              <description>DATLAT</description>
149 
              <bitOffset>24</bitOffset>
150 
              <bitWidth>4</bitWidth>
151 
            </field>
152 
            <field>
153 
              <name>CLKDIV</name>
154 
              <description>CLKDIV</description>
155 
              <bitOffset>20</bitOffset>
156 
              <bitWidth>4</bitWidth>
157 
            </field>
158 
            <field>
159 
              <name>BUSTURN</name>
160 
              <description>BUSTURN</description>
161 
              <bitOffset>16</bitOffset>
162 
              <bitWidth>4</bitWidth>
163 
            </field>
164 
            <field>
165 
              <name>DATAST</name>
166 
              <description>DATAST</description>
167 
              <bitOffset>8</bitOffset>
168 
              <bitWidth>8</bitWidth>
169 
            </field>
170 
            <field>
171 
              <name>ADDHLD</name>
172 
              <description>ADDHLD</description>
173 
              <bitOffset>4</bitOffset>
174 
              <bitWidth>4</bitWidth>
175 
            </field>
176 
            <field>
177 
              <name>ADDSET</name>
178 
              <description>ADDSET</description>
179 
              <bitOffset>0</bitOffset>
180 
              <bitWidth>4</bitWidth>
181 
            </field>
182 
          </fields>
183 
        </register>
184 
        <register>
185 
          <name>BCR2</name>
186 
          <displayName>BCR2</displayName>
187 
          <description>SRAM/NOR-Flash chip-select control register
188 
          2</description>
189 
          <addressOffset>0x8</addressOffset>
190 
          <size>0x20</size>
191 
          <access>read-write</access>
192 
          <resetValue>0x000030D0</resetValue>
193 
          <fields>
194 
            <field>
195 
              <name>CBURSTRW</name>
196 
              <description>CBURSTRW</description>
197 
              <bitOffset>19</bitOffset>
198 
              <bitWidth>1</bitWidth>
199 
            </field>
200 
            <field>
201 
              <name>ASYNCWAIT</name>
202 
              <description>ASYNCWAIT</description>
203 
              <bitOffset>15</bitOffset>
204 
              <bitWidth>1</bitWidth>
205 
            </field>
206 
            <field>
207 
              <name>EXTMOD</name>
208 
              <description>EXTMOD</description>
209 
              <bitOffset>14</bitOffset>
210 
              <bitWidth>1</bitWidth>
211 
            </field>
212 
            <field>
213 
              <name>WAITEN</name>
214 
              <description>WAITEN</description>
215 
              <bitOffset>13</bitOffset>
216 
              <bitWidth>1</bitWidth>
217 
            </field>
218 
            <field>
219 
              <name>WREN</name>
220 
              <description>WREN</description>
221 
              <bitOffset>12</bitOffset>
222 
              <bitWidth>1</bitWidth>
223 
            </field>
224 
            <field>
225 
              <name>WAITCFG</name>
226 
              <description>WAITCFG</description>
227 
              <bitOffset>11</bitOffset>
228 
              <bitWidth>1</bitWidth>
229 
            </field>
230 
            <field>
231 
              <name>WRAPMOD</name>
232 
              <description>WRAPMOD</description>
233 
              <bitOffset>10</bitOffset>
234 
              <bitWidth>1</bitWidth>
235 
            </field>
236 
            <field>
237 
              <name>WAITPOL</name>
238 
              <description>WAITPOL</description>
239 
              <bitOffset>9</bitOffset>
240 
              <bitWidth>1</bitWidth>
241 
            </field>
242 
            <field>
243 
              <name>BURSTEN</name>
244 
              <description>BURSTEN</description>
245 
              <bitOffset>8</bitOffset>
246 
              <bitWidth>1</bitWidth>
247 
            </field>
248 
            <field>
249 
              <name>FACCEN</name>
250 
              <description>FACCEN</description>
251 
              <bitOffset>6</bitOffset>
252 
              <bitWidth>1</bitWidth>
253 
            </field>
254 
            <field>
255 
              <name>MWID</name>
256 
              <description>MWID</description>
257 
              <bitOffset>4</bitOffset>
258 
              <bitWidth>2</bitWidth>
259 
            </field>
260 
            <field>
261 
              <name>MTYP</name>
262 
              <description>MTYP</description>
263 
              <bitOffset>2</bitOffset>
264 
              <bitWidth>2</bitWidth>
265 
            </field>
266 
            <field>
267 
              <name>MUXEN</name>
268 
              <description>MUXEN</description>
269 
              <bitOffset>1</bitOffset>
270 
              <bitWidth>1</bitWidth>
271 
            </field>
272 
            <field>
273 
              <name>MBKEN</name>
274 
              <description>MBKEN</description>
275 
              <bitOffset>0</bitOffset>
276 
              <bitWidth>1</bitWidth>
277 
            </field>
278 
          </fields>
279 
        </register>
280 
        <register>
281 
          <name>BTR2</name>
282 
          <displayName>BTR2</displayName>
283 
          <description>SRAM/NOR-Flash chip-select timing register
284 
          2</description>
285 
          <addressOffset>0xC</addressOffset>
286 
          <size>0x20</size>
287 
          <access>read-write</access>
288 
          <resetValue>0xFFFFFFFF</resetValue>
289 
          <fields>
290 
            <field>
291 
              <name>ACCMOD</name>
292 
              <description>ACCMOD</description>
293 
              <bitOffset>28</bitOffset>
294 
              <bitWidth>2</bitWidth>
295 
            </field>
296 
            <field>
297 
              <name>DATLAT</name>
298 
              <description>DATLAT</description>
299 
              <bitOffset>24</bitOffset>
300 
              <bitWidth>4</bitWidth>
301 
            </field>
302 
            <field>
303 
              <name>CLKDIV</name>
304 
              <description>CLKDIV</description>
305 
              <bitOffset>20</bitOffset>
306 
              <bitWidth>4</bitWidth>
307 
            </field>
308 
            <field>
309 
              <name>BUSTURN</name>
310 
              <description>BUSTURN</description>
311 
              <bitOffset>16</bitOffset>
312 
              <bitWidth>4</bitWidth>
313 
            </field>
314 
            <field>
315 
              <name>DATAST</name>
316 
              <description>DATAST</description>
317 
              <bitOffset>8</bitOffset>
318 
              <bitWidth>8</bitWidth>
319 
            </field>
320 
            <field>
321 
              <name>ADDHLD</name>
322 
              <description>ADDHLD</description>
323 
              <bitOffset>4</bitOffset>
324 
              <bitWidth>4</bitWidth>
325 
            </field>
326 
            <field>
327 
              <name>ADDSET</name>
328 
              <description>ADDSET</description>
329 
              <bitOffset>0</bitOffset>
330 
              <bitWidth>4</bitWidth>
331 
            </field>
332 
          </fields>
333 
        </register>
334 
        <register>
335 
          <name>BCR3</name>
336 
          <displayName>BCR3</displayName>
337 
          <description>SRAM/NOR-Flash chip-select control register
338 
          3</description>
339 
          <addressOffset>0x10</addressOffset>
340 
          <size>0x20</size>
341 
          <access>read-write</access>
342 
          <resetValue>0x000030D0</resetValue>
343 
          <fields>
344 
            <field>
345 
              <name>CBURSTRW</name>
346 
              <description>CBURSTRW</description>
347 
              <bitOffset>19</bitOffset>
348 
              <bitWidth>1</bitWidth>
349 
            </field>
350 
            <field>
351 
              <name>ASYNCWAIT</name>
352 
              <description>ASYNCWAIT</description>
353 
              <bitOffset>15</bitOffset>
354 
              <bitWidth>1</bitWidth>
355 
            </field>
356 
            <field>
357 
              <name>EXTMOD</name>
358 
              <description>EXTMOD</description>
359 
              <bitOffset>14</bitOffset>
360 
              <bitWidth>1</bitWidth>
361 
            </field>
362 
            <field>
363 
              <name>WAITEN</name>
364 
              <description>WAITEN</description>
365 
              <bitOffset>13</bitOffset>
366 
              <bitWidth>1</bitWidth>
367 
            </field>
368 
            <field>
369 
              <name>WREN</name>
370 
              <description>WREN</description>
371 
              <bitOffset>12</bitOffset>
372 
              <bitWidth>1</bitWidth>
373 
            </field>
374 
            <field>
375 
              <name>WAITCFG</name>
376 
              <description>WAITCFG</description>
377 
              <bitOffset>11</bitOffset>
378 
              <bitWidth>1</bitWidth>
379 
            </field>
380 
            <field>
381 
              <name>WRAPMOD</name>
382 
              <description>WRAPMOD</description>
383 
              <bitOffset>10</bitOffset>
384 
              <bitWidth>1</bitWidth>
385 
            </field>
386 
            <field>
387 
              <name>WAITPOL</name>
388 
              <description>WAITPOL</description>
389 
              <bitOffset>9</bitOffset>
390 
              <bitWidth>1</bitWidth>
391 
            </field>
392 
            <field>
393 
              <name>BURSTEN</name>
394 
              <description>BURSTEN</description>
395 
              <bitOffset>8</bitOffset>
396 
              <bitWidth>1</bitWidth>
397 
            </field>
398 
            <field>
399 
              <name>FACCEN</name>
400 
              <description>FACCEN</description>
401 
              <bitOffset>6</bitOffset>
402 
              <bitWidth>1</bitWidth>
403 
            </field>
404 
            <field>
405 
              <name>MWID</name>
406 
              <description>MWID</description>
407 
              <bitOffset>4</bitOffset>
408 
              <bitWidth>2</bitWidth>
409 
            </field>
410 
            <field>
411 
              <name>MTYP</name>
412 
              <description>MTYP</description>
413 
              <bitOffset>2</bitOffset>
414 
              <bitWidth>2</bitWidth>
415 
            </field>
416 
            <field>
417 
              <name>MUXEN</name>
418 
              <description>MUXEN</description>
419 
              <bitOffset>1</bitOffset>
420 
              <bitWidth>1</bitWidth>
421 
            </field>
422 
            <field>
423 
              <name>MBKEN</name>
424 
              <description>MBKEN</description>
425 
              <bitOffset>0</bitOffset>
426 
              <bitWidth>1</bitWidth>
427 
            </field>
428 
          </fields>
429 
        </register>
430 
        <register>
431 
          <name>BTR3</name>
432 
          <displayName>BTR3</displayName>
433 
          <description>SRAM/NOR-Flash chip-select timing register
434 
          3</description>
435 
          <addressOffset>0x14</addressOffset>
436 
          <size>0x20</size>
437 
          <access>read-write</access>
438 
          <resetValue>0xFFFFFFFF</resetValue>
439 
          <fields>
440 
            <field>
441 
              <name>ACCMOD</name>
442 
              <description>ACCMOD</description>
443 
              <bitOffset>28</bitOffset>
444 
              <bitWidth>2</bitWidth>
445 
            </field>
446 
            <field>
447 
              <name>DATLAT</name>
448 
              <description>DATLAT</description>
449 
              <bitOffset>24</bitOffset>
450 
              <bitWidth>4</bitWidth>
451 
            </field>
452 
            <field>
453 
              <name>CLKDIV</name>
454 
              <description>CLKDIV</description>
455 
              <bitOffset>20</bitOffset>
456 
              <bitWidth>4</bitWidth>
457 
            </field>
458 
            <field>
459 
              <name>BUSTURN</name>
460 
              <description>BUSTURN</description>
461 
              <bitOffset>16</bitOffset>
462 
              <bitWidth>4</bitWidth>
463 
            </field>
464 
            <field>
465 
              <name>DATAST</name>
466 
              <description>DATAST</description>
467 
              <bitOffset>8</bitOffset>
468 
              <bitWidth>8</bitWidth>
469 
            </field>
470 
            <field>
471 
              <name>ADDHLD</name>
472 
              <description>ADDHLD</description>
473 
              <bitOffset>4</bitOffset>
474 
              <bitWidth>4</bitWidth>
475 
            </field>
476 
            <field>
477 
              <name>ADDSET</name>
478 
              <description>ADDSET</description>
479 
              <bitOffset>0</bitOffset>
480 
              <bitWidth>4</bitWidth>
481 
            </field>
482 
          </fields>
483 
        </register>
484 
        <register>
485 
          <name>BCR4</name>
486 
          <displayName>BCR4</displayName>
487 
          <description>SRAM/NOR-Flash chip-select control register
488 
          4</description>
489 
          <addressOffset>0x18</addressOffset>
490 
          <size>0x20</size>
491 
          <access>read-write</access>
492 
          <resetValue>0x000030D0</resetValue>
493 
          <fields>
494 
            <field>
495 
              <name>CBURSTRW</name>
496 
              <description>CBURSTRW</description>
497 
              <bitOffset>19</bitOffset>
498 
              <bitWidth>1</bitWidth>
499 
            </field>
500 
            <field>
501 
              <name>ASYNCWAIT</name>
502 
              <description>ASYNCWAIT</description>
503 
              <bitOffset>15</bitOffset>
504 
              <bitWidth>1</bitWidth>
505 
            </field>
506 
            <field>
507 
              <name>EXTMOD</name>
508 
              <description>EXTMOD</description>
509 
              <bitOffset>14</bitOffset>
510 
              <bitWidth>1</bitWidth>
511 
            </field>
512 
            <field>
513 
              <name>WAITEN</name>
514 
              <description>WAITEN</description>
515 
              <bitOffset>13</bitOffset>
516 
              <bitWidth>1</bitWidth>
517 
            </field>
518 
            <field>
519 
              <name>WREN</name>
520 
              <description>WREN</description>
521 
              <bitOffset>12</bitOffset>
522 
              <bitWidth>1</bitWidth>
523 
            </field>
524 
            <field>
525 
              <name>WAITCFG</name>
526 
              <description>WAITCFG</description>
527 
              <bitOffset>11</bitOffset>
528 
              <bitWidth>1</bitWidth>
529 
            </field>
530 
            <field>
531 
              <name>WRAPMOD</name>
532 
              <description>WRAPMOD</description>
533 
              <bitOffset>10</bitOffset>
534 
              <bitWidth>1</bitWidth>
535 
            </field>
536 
            <field>
537 
              <name>WAITPOL</name>
538 
              <description>WAITPOL</description>
539 
              <bitOffset>9</bitOffset>
540 
              <bitWidth>1</bitWidth>
541 
            </field>
542 
            <field>
543 
              <name>BURSTEN</name>
544 
              <description>BURSTEN</description>
545 
              <bitOffset>8</bitOffset>
546 
              <bitWidth>1</bitWidth>
547 
            </field>
548 
            <field>
549 
              <name>FACCEN</name>
550 
              <description>FACCEN</description>
551 
              <bitOffset>6</bitOffset>
552 
              <bitWidth>1</bitWidth>
553 
            </field>
554 
            <field>
555 
              <name>MWID</name>
556 
              <description>MWID</description>
557 
              <bitOffset>4</bitOffset>
558 
              <bitWidth>2</bitWidth>
559 
            </field>
560 
            <field>
561 
              <name>MTYP</name>
562 
              <description>MTYP</description>
563 
              <bitOffset>2</bitOffset>
564 
              <bitWidth>2</bitWidth>
565 
            </field>
566 
            <field>
567 
              <name>MUXEN</name>
568 
              <description>MUXEN</description>
569 
              <bitOffset>1</bitOffset>
570 
              <bitWidth>1</bitWidth>
571 
            </field>
572 
            <field>
573 
              <name>MBKEN</name>
574 
              <description>MBKEN</description>
575 
              <bitOffset>0</bitOffset>
576 
              <bitWidth>1</bitWidth>
577 
            </field>
578 
          </fields>
579 
        </register>
580 
        <register>
581 
          <name>BTR4</name>
582 
          <displayName>BTR4</displayName>
583 
          <description>SRAM/NOR-Flash chip-select timing register
584 
          4</description>
585 
          <addressOffset>0x1C</addressOffset>
586 
          <size>0x20</size>
587 
          <access>read-write</access>
588 
          <resetValue>0xFFFFFFFF</resetValue>
589 
          <fields>
590 
            <field>
591 
              <name>ACCMOD</name>
592 
              <description>ACCMOD</description>
593 
              <bitOffset>28</bitOffset>
594 
              <bitWidth>2</bitWidth>
595 
            </field>
596 
            <field>
597 
              <name>DATLAT</name>
598 
              <description>DATLAT</description>
599 
              <bitOffset>24</bitOffset>
600 
              <bitWidth>4</bitWidth>
601 
            </field>
602 
            <field>
603 
              <name>CLKDIV</name>
604 
              <description>CLKDIV</description>
605 
              <bitOffset>20</bitOffset>
606 
              <bitWidth>4</bitWidth>
607 
            </field>
608 
            <field>
609 
              <name>BUSTURN</name>
610 
              <description>BUSTURN</description>
611 
              <bitOffset>16</bitOffset>
612 
              <bitWidth>4</bitWidth>
613 
            </field>
614 
            <field>
615 
              <name>DATAST</name>
616 
              <description>DATAST</description>
617 
              <bitOffset>8</bitOffset>
618 
              <bitWidth>8</bitWidth>
619 
            </field>
620 
            <field>
621 
              <name>ADDHLD</name>
622 
              <description>ADDHLD</description>
623 
              <bitOffset>4</bitOffset>
624 
              <bitWidth>4</bitWidth>
625 
            </field>
626 
            <field>
627 
              <name>ADDSET</name>
628 
              <description>ADDSET</description>
629 
              <bitOffset>0</bitOffset>
630 
              <bitWidth>4</bitWidth>
631 
            </field>
632 
          </fields>
633 
        </register>
634 
        <register>
635 
          <name>PCR2</name>
636 
          <displayName>PCR2</displayName>
637 
          <description>PC Card/NAND Flash control register
638 
          2</description>
639 
          <addressOffset>0x60</addressOffset>
640 
          <size>0x20</size>
641 
          <access>read-write</access>
642 
          <resetValue>0x00000018</resetValue>
643 
          <fields>
644 
            <field>
645 
              <name>ECCPS</name>
646 
              <description>ECCPS</description>
647 
              <bitOffset>17</bitOffset>
648 
              <bitWidth>3</bitWidth>
649 
            </field>
650 
            <field>
651 
              <name>TAR</name>
652 
              <description>TAR</description>
653 
              <bitOffset>13</bitOffset>
654 
              <bitWidth>4</bitWidth>
655 
            </field>
656 
            <field>
657 
              <name>TCLR</name>
658 
              <description>TCLR</description>
659 
              <bitOffset>9</bitOffset>
660 
              <bitWidth>4</bitWidth>
661 
            </field>
662 
            <field>
663 
              <name>ECCEN</name>
664 
              <description>ECCEN</description>
665 
              <bitOffset>6</bitOffset>
666 
              <bitWidth>1</bitWidth>
667 
            </field>
668 
            <field>
669 
              <name>PWID</name>
670 
              <description>PWID</description>
671 
              <bitOffset>4</bitOffset>
672 
              <bitWidth>2</bitWidth>
673 
            </field>
674 
            <field>
675 
              <name>PTYP</name>
676 
              <description>PTYP</description>
677 
              <bitOffset>3</bitOffset>
678 
              <bitWidth>1</bitWidth>
679 
            </field>
680 
            <field>
681 
              <name>PBKEN</name>
682 
              <description>PBKEN</description>
683 
              <bitOffset>2</bitOffset>
684 
              <bitWidth>1</bitWidth>
685 
            </field>
686 
            <field>
687 
              <name>PWAITEN</name>
688 
              <description>PWAITEN</description>
689 
              <bitOffset>1</bitOffset>
690 
              <bitWidth>1</bitWidth>
691 
            </field>
692 
          </fields>
693 
        </register>
694 
        <register>
695 
          <name>SR2</name>
696 
          <displayName>SR2</displayName>
697 
          <description>FIFO status and interrupt register
698 
          2</description>
699 
          <addressOffset>0x64</addressOffset>
700 
          <size>0x20</size>
701 
          <resetValue>0x00000040</resetValue>
702 
          <fields>
703 
            <field>
704 
              <name>FEMPT</name>
705 
              <description>FEMPT</description>
706 
              <bitOffset>6</bitOffset>
707 
              <bitWidth>1</bitWidth>
708 
              <access>read-only</access>
709 
            </field>
710 
            <field>
711 
              <name>IFEN</name>
712 
              <description>IFEN</description>
713 
              <bitOffset>5</bitOffset>
714 
              <bitWidth>1</bitWidth>
715 
              <access>read-write</access>
716 
            </field>
717 
            <field>
718 
              <name>ILEN</name>
719 
              <description>ILEN</description>
720 
              <bitOffset>4</bitOffset>
721 
              <bitWidth>1</bitWidth>
722 
              <access>read-write</access>
723 
            </field>
724 
            <field>
725 
              <name>IREN</name>
726 
              <description>IREN</description>
727 
              <bitOffset>3</bitOffset>
728 
              <bitWidth>1</bitWidth>
729 
              <access>read-write</access>
730 
            </field>
731 
            <field>
732 
              <name>IFS</name>
733 
              <description>IFS</description>
734 
              <bitOffset>2</bitOffset>
735 
              <bitWidth>1</bitWidth>
736 
              <access>read-write</access>
737 
            </field>
738 
            <field>
739 
              <name>ILS</name>
740 
              <description>ILS</description>
741 
              <bitOffset>1</bitOffset>
742 
              <bitWidth>1</bitWidth>
743 
              <access>read-write</access>
744 
            </field>
745 
            <field>
746 
              <name>IRS</name>
747 
              <description>IRS</description>
748 
              <bitOffset>0</bitOffset>
749 
              <bitWidth>1</bitWidth>
750 
              <access>read-write</access>
751 
            </field>
752 
          </fields>
753 
        </register>
754 
        <register>
755 
          <name>PMEM2</name>
756 
          <displayName>PMEM2</displayName>
757 
          <description>Common memory space timing register
758 
          2</description>
759 
          <addressOffset>0x68</addressOffset>
760 
          <size>0x20</size>
761 
          <access>read-write</access>
762 
          <resetValue>0xFCFCFCFC</resetValue>
763 
          <fields>
764 
            <field>
765 
              <name>MEMHIZx</name>
766 
              <description>MEMHIZx</description>
767 
              <bitOffset>24</bitOffset>
768 
              <bitWidth>8</bitWidth>
769 
            </field>
770 
            <field>
771 
              <name>MEMHOLDx</name>
772 
              <description>MEMHOLDx</description>
773 
              <bitOffset>16</bitOffset>
774 
              <bitWidth>8</bitWidth>
775 
            </field>
776 
            <field>
777 
              <name>MEMWAITx</name>
778 
              <description>MEMWAITx</description>
779 
              <bitOffset>8</bitOffset>
780 
              <bitWidth>8</bitWidth>
781 
            </field>
782 
            <field>
783 
              <name>MEMSETx</name>
784 
              <description>MEMSETx</description>
785 
              <bitOffset>0</bitOffset>
786 
              <bitWidth>8</bitWidth>
787 
            </field>
788 
          </fields>
789 
        </register>
790 
        <register>
791 
          <name>PATT2</name>
792 
          <displayName>PATT2</displayName>
793 
          <description>Attribute memory space timing register
794 
          2</description>
795 
          <addressOffset>0x6C</addressOffset>
796 
          <size>0x20</size>
797 
          <access>read-write</access>
798 
          <resetValue>0xFCFCFCFC</resetValue>
799 
          <fields>
800 
            <field>
801 
              <name>ATTHIZx</name>
802 
              <description>Attribute memory x databus HiZ
803 
              time</description>
804 
              <bitOffset>24</bitOffset>
805 
              <bitWidth>8</bitWidth>
806 
            </field>
807 
            <field>
808 
              <name>ATTHOLDx</name>
809 
              <description>Attribute memory x hold
810 
              time</description>
811 
              <bitOffset>16</bitOffset>
812 
              <bitWidth>8</bitWidth>
813 
            </field>
814 
            <field>
815 
              <name>ATTWAITx</name>
816 
              <description>Attribute memory x wait
817 
              time</description>
818 
              <bitOffset>8</bitOffset>
819 
              <bitWidth>8</bitWidth>
820 
            </field>
821 
            <field>
822 
              <name>ATTSETx</name>
823 
              <description>Attribute memory x setup
824 
              time</description>
825 
              <bitOffset>0</bitOffset>
826 
              <bitWidth>8</bitWidth>
827 
            </field>
828 
          </fields>
829 
        </register>
830 
        <register>
831 
          <name>ECCR2</name>
832 
          <displayName>ECCR2</displayName>
833 
          <description>ECC result register 2</description>
834 
          <addressOffset>0x74</addressOffset>
835 
          <size>0x20</size>
836 
          <access>read-only</access>
837 
          <resetValue>0x00000000</resetValue>
838 
          <fields>
839 
            <field>
840 
              <name>ECCx</name>
841 
              <description>ECC result</description>
842 
              <bitOffset>0</bitOffset>
843 
              <bitWidth>32</bitWidth>
844 
            </field>
845 
          </fields>
846 
        </register>
847 
        <register>
848 
          <name>PCR3</name>
849 
          <displayName>PCR3</displayName>
850 
          <description>PC Card/NAND Flash control register
851 
          3</description>
852 
          <addressOffset>0x80</addressOffset>
853 
          <size>0x20</size>
854 
          <access>read-write</access>
855 
          <resetValue>0x00000018</resetValue>
856 
          <fields>
857 
            <field>
858 
              <name>ECCPS</name>
859 
              <description>ECCPS</description>
860 
              <bitOffset>17</bitOffset>
861 
              <bitWidth>3</bitWidth>
862 
            </field>
863 
            <field>
864 
              <name>TAR</name>
865 
              <description>TAR</description>
866 
              <bitOffset>13</bitOffset>
867 
              <bitWidth>4</bitWidth>
868 
            </field>
869 
            <field>
870 
              <name>TCLR</name>
871 
              <description>TCLR</description>
872 
              <bitOffset>9</bitOffset>
873 
              <bitWidth>4</bitWidth>
874 
            </field>
875 
            <field>
876 
              <name>ECCEN</name>
877 
              <description>ECCEN</description>
878 
              <bitOffset>6</bitOffset>
879 
              <bitWidth>1</bitWidth>
880 
            </field>
881 
            <field>
882 
              <name>PWID</name>
883 
              <description>PWID</description>
884 
              <bitOffset>4</bitOffset>
885 
              <bitWidth>2</bitWidth>
886 
            </field>
887 
            <field>
888 
              <name>PTYP</name>
889 
              <description>PTYP</description>
890 
              <bitOffset>3</bitOffset>
891 
              <bitWidth>1</bitWidth>
892 
            </field>
893 
            <field>
894 
              <name>PBKEN</name>
895 
              <description>PBKEN</description>
896 
              <bitOffset>2</bitOffset>
897 
              <bitWidth>1</bitWidth>
898 
            </field>
899 
            <field>
900 
              <name>PWAITEN</name>
901 
              <description>PWAITEN</description>
902 
              <bitOffset>1</bitOffset>
903 
              <bitWidth>1</bitWidth>
904 
            </field>
905 
          </fields>
906 
        </register>
907 
        <register>
908 
          <name>SR3</name>
909 
          <displayName>SR3</displayName>
910 
          <description>FIFO status and interrupt register
911 
          3</description>
912 
          <addressOffset>0x84</addressOffset>
913 
          <size>0x20</size>
914 
          <resetValue>0x00000040</resetValue>
915 
          <fields>
916 
            <field>
917 
              <name>FEMPT</name>
918 
              <description>FEMPT</description>
919 
              <bitOffset>6</bitOffset>
920 
              <bitWidth>1</bitWidth>
921 
              <access>read-only</access>
922 
            </field>
923 
            <field>
924 
              <name>IFEN</name>
925 
              <description>IFEN</description>
926 
              <bitOffset>5</bitOffset>
927 
              <bitWidth>1</bitWidth>
928 
              <access>read-write</access>
929 
            </field>
930 
            <field>
931 
              <name>ILEN</name>
932 
              <description>ILEN</description>
933 
              <bitOffset>4</bitOffset>
934 
              <bitWidth>1</bitWidth>
935 
              <access>read-write</access>
936 
            </field>
937 
            <field>
938 
              <name>IREN</name>
939 
              <description>IREN</description>
940 
              <bitOffset>3</bitOffset>
941 
              <bitWidth>1</bitWidth>
942 
              <access>read-write</access>
943 
            </field>
944 
            <field>
945 
              <name>IFS</name>
946 
              <description>IFS</description>
947 
              <bitOffset>2</bitOffset>
948 
              <bitWidth>1</bitWidth>
949 
              <access>read-write</access>
950 
            </field>
951 
            <field>
952 
              <name>ILS</name>
953 
              <description>ILS</description>
954 
              <bitOffset>1</bitOffset>
955 
              <bitWidth>1</bitWidth>
956 
              <access>read-write</access>
957 
            </field>
958 
            <field>
959 
              <name>IRS</name>
960 
              <description>IRS</description>
961 
              <bitOffset>0</bitOffset>
962 
              <bitWidth>1</bitWidth>
963 
              <access>read-write</access>
964 
            </field>
965 
          </fields>
966 
        </register>
967 
        <register>
968 
          <name>PMEM3</name>
969 
          <displayName>PMEM3</displayName>
970 
          <description>Common memory space timing register
971 
          3</description>
972 
          <addressOffset>0x88</addressOffset>
973 
          <size>0x20</size>
974 
          <access>read-write</access>
975 
          <resetValue>0xFCFCFCFC</resetValue>
976 
          <fields>
977 
            <field>
978 
              <name>MEMHIZx</name>
979 
              <description>MEMHIZx</description>
980 
              <bitOffset>24</bitOffset>
981 
              <bitWidth>8</bitWidth>
982 
            </field>
983 
            <field>
984 
              <name>MEMHOLDx</name>
985 
              <description>MEMHOLDx</description>
986 
              <bitOffset>16</bitOffset>
987 
              <bitWidth>8</bitWidth>
988 
            </field>
989 
            <field>
990 
              <name>MEMWAITx</name>
991 
              <description>MEMWAITx</description>
992 
              <bitOffset>8</bitOffset>
993 
              <bitWidth>8</bitWidth>
994 
            </field>
995 
            <field>
996 
              <name>MEMSETx</name>
997 
              <description>MEMSETx</description>
998 
              <bitOffset>0</bitOffset>
999 
              <bitWidth>8</bitWidth>
1000 
            </field>
1001 
          </fields>
1002 
        </register>
1003 
        <register>
1004 
          <name>PATT3</name>
1005 
          <displayName>PATT3</displayName>
1006 
          <description>Attribute memory space timing register
1007 
          3</description>
1008 
          <addressOffset>0x8C</addressOffset>
1009 
          <size>0x20</size>
1010 
          <access>read-write</access>
1011 
          <resetValue>0xFCFCFCFC</resetValue>
1012 
          <fields>
1013 
            <field>
1014 
              <name>ATTHIZx</name>
1015 
              <description>ATTHIZx</description>
1016 
              <bitOffset>24</bitOffset>
1017 
              <bitWidth>8</bitWidth>
1018 
            </field>
1019 
            <field>
1020 
              <name>ATTHOLDx</name>
1021 
              <description>ATTHOLDx</description>
1022 
              <bitOffset>16</bitOffset>
1023 
              <bitWidth>8</bitWidth>
1024 
            </field>
1025 
            <field>
1026 
              <name>ATTWAITx</name>
1027 
              <description>ATTWAITx</description>
1028 
              <bitOffset>8</bitOffset>
1029 
              <bitWidth>8</bitWidth>
1030 
            </field>
1031 
            <field>
1032 
              <name>ATTSETx</name>
1033 
              <description>ATTSETx</description>
1034 
              <bitOffset>0</bitOffset>
1035 
              <bitWidth>8</bitWidth>
1036 
            </field>
1037 
          </fields>
1038 
        </register>
1039 
        <register>
1040 
          <name>ECCR3</name>
1041 
          <displayName>ECCR3</displayName>
1042 
          <description>ECC result register 3</description>
1043 
          <addressOffset>0x94</addressOffset>
1044 
          <size>0x20</size>
1045 
          <access>read-only</access>
1046 
          <resetValue>0x00000000</resetValue>
1047 
          <fields>
1048 
            <field>
1049 
              <name>ECCx</name>
1050 
              <description>ECCx</description>
1051 
              <bitOffset>0</bitOffset>
1052 
              <bitWidth>32</bitWidth>
1053 
            </field>
1054 
          </fields>
1055 
        </register>
1056 
        <register>
1057 
          <name>PCR4</name>
1058 
          <displayName>PCR4</displayName>
1059 
          <description>PC Card/NAND Flash control register
1060 
          4</description>
1061 
          <addressOffset>0xA0</addressOffset>
1062 
          <size>0x20</size>
1063 
          <access>read-write</access>
1064 
          <resetValue>0x00000018</resetValue>
1065 
          <fields>
1066 
            <field>
1067 
              <name>ECCPS</name>
1068 
              <description>ECCPS</description>
1069 
              <bitOffset>17</bitOffset>
1070 
              <bitWidth>3</bitWidth>
1071 
            </field>
1072 
            <field>
1073 
              <name>TAR</name>
1074 
              <description>TAR</description>
1075 
              <bitOffset>13</bitOffset>
1076 
              <bitWidth>4</bitWidth>
1077 
            </field>
1078 
            <field>
1079 
              <name>TCLR</name>
1080 
              <description>TCLR</description>
1081 
              <bitOffset>9</bitOffset>
1082 
              <bitWidth>4</bitWidth>
1083 
            </field>
1084 
            <field>
1085 
              <name>ECCEN</name>
1086 
              <description>ECCEN</description>
1087 
              <bitOffset>6</bitOffset>
1088 
              <bitWidth>1</bitWidth>
1089 
            </field>
1090 
            <field>
1091 
              <name>PWID</name>
1092 
              <description>PWID</description>
1093 
              <bitOffset>4</bitOffset>
1094 
              <bitWidth>2</bitWidth>
1095 
            </field>
1096 
            <field>
1097 
              <name>PTYP</name>
1098 
              <description>PTYP</description>
1099 
              <bitOffset>3</bitOffset>
1100 
              <bitWidth>1</bitWidth>
1101 
            </field>
1102 
            <field>
1103 
              <name>PBKEN</name>
1104 
              <description>PBKEN</description>
1105 
              <bitOffset>2</bitOffset>
1106 
              <bitWidth>1</bitWidth>
1107 
            </field>
1108 
            <field>
1109 
              <name>PWAITEN</name>
1110 
              <description>PWAITEN</description>
1111 
              <bitOffset>1</bitOffset>
1112 
              <bitWidth>1</bitWidth>
1113 
            </field>
1114 
          </fields>
1115 
        </register>
1116 
        <register>
1117 
          <name>SR4</name>
1118 
          <displayName>SR4</displayName>
1119 
          <description>FIFO status and interrupt register
1120 
          4</description>
1121 
          <addressOffset>0xA4</addressOffset>
1122 
          <size>0x20</size>
1123 
          <resetValue>0x00000040</resetValue>
1124 
          <fields>
1125 
            <field>
1126 
              <name>FEMPT</name>
1127 
              <description>FEMPT</description>
1128 
              <bitOffset>6</bitOffset>
1129 
              <bitWidth>1</bitWidth>
1130 
              <access>read-only</access>
1131 
            </field>
1132 
            <field>
1133 
              <name>IFEN</name>
1134 
              <description>IFEN</description>
1135 
              <bitOffset>5</bitOffset>
1136 
              <bitWidth>1</bitWidth>
1137 
              <access>read-write</access>
1138 
            </field>
1139 
            <field>
1140 
              <name>ILEN</name>
1141 
              <description>ILEN</description>
1142 
              <bitOffset>4</bitOffset>
1143 
              <bitWidth>1</bitWidth>
1144 
              <access>read-write</access>
1145 
            </field>
1146 
            <field>
1147 
              <name>IREN</name>
1148 
              <description>IREN</description>
1149 
              <bitOffset>3</bitOffset>
1150 
              <bitWidth>1</bitWidth>
1151 
              <access>read-write</access>
1152 
            </field>
1153 
            <field>
1154 
              <name>IFS</name>
1155 
              <description>IFS</description>
1156 
              <bitOffset>2</bitOffset>
1157 
              <bitWidth>1</bitWidth>
1158 
              <access>read-write</access>
1159 
            </field>
1160 
            <field>
1161 
              <name>ILS</name>
1162 
              <description>ILS</description>
1163 
              <bitOffset>1</bitOffset>
1164 
              <bitWidth>1</bitWidth>
1165 
              <access>read-write</access>
1166 
            </field>
1167 
            <field>
1168 
              <name>IRS</name>
1169 
              <description>IRS</description>
1170 
              <bitOffset>0</bitOffset>
1171 
              <bitWidth>1</bitWidth>
1172 
              <access>read-write</access>
1173 
            </field>
1174 
          </fields>
1175 
        </register>
1176 
        <register>
1177 
          <name>PMEM4</name>
1178 
          <displayName>PMEM4</displayName>
1179 
          <description>Common memory space timing register
1180 
          4</description>
1181 
          <addressOffset>0xA8</addressOffset>
1182 
          <size>0x20</size>
1183 
          <access>read-write</access>
1184 
          <resetValue>0xFCFCFCFC</resetValue>
1185 
          <fields>
1186 
            <field>
1187 
              <name>MEMHIZx</name>
1188 
              <description>MEMHIZx</description>
1189 
              <bitOffset>24</bitOffset>
1190 
              <bitWidth>8</bitWidth>
1191 
            </field>
1192 
            <field>
1193 
              <name>MEMHOLDx</name>
1194 
              <description>MEMHOLDx</description>
1195 
              <bitOffset>16</bitOffset>
1196 
              <bitWidth>8</bitWidth>
1197 
            </field>
1198 
            <field>
1199 
              <name>MEMWAITx</name>
1200 
              <description>MEMWAITx</description>
1201 
              <bitOffset>8</bitOffset>
1202 
              <bitWidth>8</bitWidth>
1203 
            </field>
1204 
            <field>
1205 
              <name>MEMSETx</name>
1206 
              <description>MEMSETx</description>
1207 
              <bitOffset>0</bitOffset>
1208 
              <bitWidth>8</bitWidth>
1209 
            </field>
1210 
          </fields>
1211 
        </register>
1212 
        <register>
1213 
          <name>PATT4</name>
1214 
          <displayName>PATT4</displayName>
1215 
          <description>Attribute memory space timing register
1216 
          4</description>
1217 
          <addressOffset>0xAC</addressOffset>
1218 
          <size>0x20</size>
1219 
          <access>read-write</access>
1220 
          <resetValue>0xFCFCFCFC</resetValue>
1221 
          <fields>
1222 
            <field>
1223 
              <name>ATTHIZx</name>
1224 
              <description>ATTHIZx</description>
1225 
              <bitOffset>24</bitOffset>
1226 
              <bitWidth>8</bitWidth>
1227 
            </field>
1228 
            <field>
1229 
              <name>ATTHOLDx</name>
1230 
              <description>ATTHOLDx</description>
1231 
              <bitOffset>16</bitOffset>
1232 
              <bitWidth>8</bitWidth>
1233 
            </field>
1234 
            <field>
1235 
              <name>ATTWAITx</name>
1236 
              <description>ATTWAITx</description>
1237 
              <bitOffset>8</bitOffset>
1238 
              <bitWidth>8</bitWidth>
1239 
            </field>
1240 
            <field>
1241 
              <name>ATTSETx</name>
1242 
              <description>ATTSETx</description>
1243 
              <bitOffset>0</bitOffset>
1244 
              <bitWidth>8</bitWidth>
1245 
            </field>
1246 
          </fields>
1247 
        </register>
1248 
        <register>
1249 
          <name>PIO4</name>
1250 
          <displayName>PIO4</displayName>
1251 
          <description>I/O space timing register 4</description>
1252 
          <addressOffset>0xB0</addressOffset>
1253 
          <size>0x20</size>
1254 
          <access>read-write</access>
1255 
          <resetValue>0xFCFCFCFC</resetValue>
1256 
          <fields>
1257 
            <field>
1258 
              <name>IOHIZx</name>
1259 
              <description>IOHIZx</description>
1260 
              <bitOffset>24</bitOffset>
1261 
              <bitWidth>8</bitWidth>
1262 
            </field>
1263 
            <field>
1264 
              <name>IOHOLDx</name>
1265 
              <description>IOHOLDx</description>
1266 
              <bitOffset>16</bitOffset>
1267 
              <bitWidth>8</bitWidth>
1268 
            </field>
1269 
            <field>
1270 
              <name>IOWAITx</name>
1271 
              <description>IOWAITx</description>
1272 
              <bitOffset>8</bitOffset>
1273 
              <bitWidth>8</bitWidth>
1274 
            </field>
1275 
            <field>
1276 
              <name>IOSETx</name>
1277 
              <description>IOSETx</description>
1278 
              <bitOffset>0</bitOffset>
1279 
              <bitWidth>8</bitWidth>
1280 
            </field>
1281 
          </fields>
1282 
        </register>
1283 
        <register>
1284 
          <name>BWTR1</name>
1285 
          <displayName>BWTR1</displayName>
1286 
          <description>SRAM/NOR-Flash write timing registers
1287 
          1</description>
1288 
          <addressOffset>0x104</addressOffset>
1289 
          <size>0x20</size>
1290 
          <access>read-write</access>
1291 
          <resetValue>0x0FFFFFFF</resetValue>
1292 
          <fields>
1293 
            <field>
1294 
              <name>ACCMOD</name>
1295 
              <description>ACCMOD</description>
1296 
              <bitOffset>28</bitOffset>
1297 
              <bitWidth>2</bitWidth>
1298 
            </field>
1299 
            <field>
1300 
              <name>DATLAT</name>
1301 
              <description>DATLAT</description>
1302 
              <bitOffset>24</bitOffset>
1303 
              <bitWidth>4</bitWidth>
1304 
            </field>
1305 
            <field>
1306 
              <name>CLKDIV</name>
1307 
              <description>CLKDIV</description>
1308 
              <bitOffset>20</bitOffset>
1309 
              <bitWidth>4</bitWidth>
1310 
            </field>
1311 
            <field>
1312 
              <name>DATAST</name>
1313 
              <description>DATAST</description>
1314 
              <bitOffset>8</bitOffset>
1315 
              <bitWidth>8</bitWidth>
1316 
            </field>
1317 
            <field>
1318 
              <name>ADDHLD</name>
1319 
              <description>ADDHLD</description>
1320 
              <bitOffset>4</bitOffset>
1321 
              <bitWidth>4</bitWidth>
1322 
            </field>
1323 
            <field>
1324 
              <name>ADDSET</name>
1325 
              <description>ADDSET</description>
1326 
              <bitOffset>0</bitOffset>
1327 
              <bitWidth>4</bitWidth>
1328 
            </field>
1329 
          </fields>
1330 
        </register>
1331 
        <register>
1332 
          <name>BWTR2</name>
1333 
          <displayName>BWTR2</displayName>
1334 
          <description>SRAM/NOR-Flash write timing registers
1335 
          2</description>
1336 
          <addressOffset>0x10C</addressOffset>
1337 
          <size>0x20</size>
1338 
          <access>read-write</access>
1339 
          <resetValue>0x0FFFFFFF</resetValue>
1340 
          <fields>
1341 
            <field>
1342 
              <name>ACCMOD</name>
1343 
              <description>ACCMOD</description>
1344 
              <bitOffset>28</bitOffset>
1345 
              <bitWidth>2</bitWidth>
1346 
            </field>
1347 
            <field>
1348 
              <name>DATLAT</name>
1349 
              <description>DATLAT</description>
1350 
              <bitOffset>24</bitOffset>
1351 
              <bitWidth>4</bitWidth>
1352 
            </field>
1353 
            <field>
1354 
              <name>CLKDIV</name>
1355 
              <description>CLKDIV</description>
1356 
              <bitOffset>20</bitOffset>
1357 
              <bitWidth>4</bitWidth>
1358 
            </field>
1359 
            <field>
1360 
              <name>DATAST</name>
1361 
              <description>DATAST</description>
1362 
              <bitOffset>8</bitOffset>
1363 
              <bitWidth>8</bitWidth>
1364 
            </field>
1365 
            <field>
1366 
              <name>ADDHLD</name>
1367 
              <description>ADDHLD</description>
1368 
              <bitOffset>4</bitOffset>
1369 
              <bitWidth>4</bitWidth>
1370 
            </field>
1371 
            <field>
1372 
              <name>ADDSET</name>
1373 
              <description>ADDSET</description>
1374 
              <bitOffset>0</bitOffset>
1375 
              <bitWidth>4</bitWidth>
1376 
            </field>
1377 
          </fields>
1378 
        </register>
1379 
        <register>
1380 
          <name>BWTR3</name>
1381 
          <displayName>BWTR3</displayName>
1382 
          <description>SRAM/NOR-Flash write timing registers
1383 
          3</description>
1384 
          <addressOffset>0x114</addressOffset>
1385 
          <size>0x20</size>
1386 
          <access>read-write</access>
1387 
          <resetValue>0x0FFFFFFF</resetValue>
1388 
          <fields>
1389 
            <field>
1390 
              <name>ACCMOD</name>
1391 
              <description>ACCMOD</description>
1392 
              <bitOffset>28</bitOffset>
1393 
              <bitWidth>2</bitWidth>
1394 
            </field>
1395 
            <field>
1396 
              <name>DATLAT</name>
1397 
              <description>DATLAT</description>
1398 
              <bitOffset>24</bitOffset>
1399 
              <bitWidth>4</bitWidth>
1400 
            </field>
1401 
            <field>
1402 
              <name>CLKDIV</name>
1403 
              <description>CLKDIV</description>
1404 
              <bitOffset>20</bitOffset>
1405 
              <bitWidth>4</bitWidth>
1406 
            </field>
1407 
            <field>
1408 
              <name>DATAST</name>
1409 
              <description>DATAST</description>
1410 
              <bitOffset>8</bitOffset>
1411 
              <bitWidth>8</bitWidth>
1412 
            </field>
1413 
            <field>
1414 
              <name>ADDHLD</name>
1415 
              <description>ADDHLD</description>
1416 
              <bitOffset>4</bitOffset>
1417 
              <bitWidth>4</bitWidth>
1418 
            </field>
1419 
            <field>
1420 
              <name>ADDSET</name>
1421 
              <description>ADDSET</description>
1422 
              <bitOffset>0</bitOffset>
1423 
              <bitWidth>4</bitWidth>
1424 
            </field>
1425 
          </fields>
1426 
        </register>
1427 
        <register>
1428 
          <name>BWTR4</name>
1429 
          <displayName>BWTR4</displayName>
1430 
          <description>SRAM/NOR-Flash write timing registers
1431 
          4</description>
1432 
          <addressOffset>0x11C</addressOffset>
1433 
          <size>0x20</size>
1434 
          <access>read-write</access>
1435 
          <resetValue>0x0FFFFFFF</resetValue>
1436 
          <fields>
1437 
            <field>
1438 
              <name>ACCMOD</name>
1439 
              <description>ACCMOD</description>
1440 
              <bitOffset>28</bitOffset>
1441 
              <bitWidth>2</bitWidth>
1442 
            </field>
1443 
            <field>
1444 
              <name>DATLAT</name>
1445 
              <description>DATLAT</description>
1446 
              <bitOffset>24</bitOffset>
1447 
              <bitWidth>4</bitWidth>
1448 
            </field>
1449 
            <field>
1450 
              <name>CLKDIV</name>
1451 
              <description>CLKDIV</description>
1452 
              <bitOffset>20</bitOffset>
1453 
              <bitWidth>4</bitWidth>
1454 
            </field>
1455 
            <field>
1456 
              <name>DATAST</name>
1457 
              <description>DATAST</description>
1458 
              <bitOffset>8</bitOffset>
1459 
              <bitWidth>8</bitWidth>
1460 
            </field>
1461 
            <field>
1462 
              <name>ADDHLD</name>
1463 
              <description>ADDHLD</description>
1464 
              <bitOffset>4</bitOffset>
1465 
              <bitWidth>4</bitWidth>
1466 
            </field>
1467 
            <field>
1468 
              <name>ADDSET</name>
1469 
              <description>ADDSET</description>
1470 
              <bitOffset>0</bitOffset>
1471 
              <bitWidth>4</bitWidth>
1472 
            </field>
1473 
          </fields>
1474 
        </register>
1475 
      </registers>
1476 
    </peripheral>
1477 
    <peripheral>
1478 
      <name>PWR</name>
1479 
      <description>Power control</description>
1480 
      <groupName>PWR</groupName>
1481 
      <baseAddress>0x40007000</baseAddress>
1482 
      <addressBlock>
1483 
        <offset>0x0</offset>
1484 
        <size>0x400</size>
1485 
        <usage>registers</usage>
1486 
      </addressBlock>
1487 
      <interrupt>
1488 
        <name>PVD</name>
1489 
        <description>PVD through EXTI line detection
1490 
        interrupt</description>
1491 
        <value>1</value>
1492 
      </interrupt>
1493 
      <registers>
1494 
        <register>
1495 
          <name>CR</name>
1496 
          <displayName>CR</displayName>
1497 
          <description>Power control register
1498 
          (PWR_CR)</description>
1499 
          <addressOffset>0x0</addressOffset>
1500 
          <size>0x20</size>
1501 
          <access>read-write</access>
1502 
          <resetValue>0x00000000</resetValue>
1503 
          <fields>
1504 
            <field>
1505 
              <name>LPDS</name>
1506 
              <description>Low Power Deep Sleep</description>
1507 
              <bitOffset>0</bitOffset>
1508 
              <bitWidth>1</bitWidth>
1509 
            </field>
1510 
            <field>
1511 
              <name>PDDS</name>
1512 
              <description>Power Down Deep Sleep</description>
1513 
              <bitOffset>1</bitOffset>
1514 
              <bitWidth>1</bitWidth>
1515 
            </field>
1516 
            <field>
1517 
              <name>CWUF</name>
1518 
              <description>Clear Wake-up Flag</description>
1519 
              <bitOffset>2</bitOffset>
1520 
              <bitWidth>1</bitWidth>
1521 
            </field>
1522 
            <field>
1523 
              <name>CSBF</name>
1524 
              <description>Clear STANDBY Flag</description>
1525 
              <bitOffset>3</bitOffset>
1526 
              <bitWidth>1</bitWidth>
1527 
            </field>
1528 
            <field>
1529 
              <name>PVDE</name>
1530 
              <description>Power Voltage Detector
1531 
              Enable</description>
1532 
              <bitOffset>4</bitOffset>
1533 
              <bitWidth>1</bitWidth>
1534 
            </field>
1535 
            <field>
1536 
              <name>PLS</name>
1537 
              <description>PVD Level Selection</description>
1538 
              <bitOffset>5</bitOffset>
1539 
              <bitWidth>3</bitWidth>
1540 
            </field>
1541 
            <field>
1542 
              <name>DBP</name>
1543 
              <description>Disable Backup Domain write
1544 
              protection</description>
1545 
              <bitOffset>8</bitOffset>
1546 
              <bitWidth>1</bitWidth>
1547 
            </field>
1548 
          </fields>
1549 
        </register>
1550 
        <register>
1551 
          <name>CSR</name>
1552 
          <displayName>CSR</displayName>
1553 
          <description>Power control register
1554 
          (PWR_CR)</description>
1555 
          <addressOffset>0x4</addressOffset>
1556 
          <size>0x20</size>
1557 
          <resetValue>0x00000000</resetValue>
1558 
          <fields>
1559 
            <field>
1560 
              <name>WUF</name>
1561 
              <description>Wake-Up Flag</description>
1562 
              <bitOffset>0</bitOffset>
1563 
              <bitWidth>1</bitWidth>
1564 
              <access>read-only</access>
1565 
            </field>
1566 
            <field>
1567 
              <name>SBF</name>
1568 
              <description>STANDBY Flag</description>
1569 
              <bitOffset>1</bitOffset>
1570 
              <bitWidth>1</bitWidth>
1571 
              <access>read-only</access>
1572 
            </field>
1573 
            <field>
1574 
              <name>PVDO</name>
1575 
              <description>PVD Output</description>
1576 
              <bitOffset>2</bitOffset>
1577 
              <bitWidth>1</bitWidth>
1578 
              <access>read-only</access>
1579 
            </field>
1580 
            <field>
1581 
              <name>EWUP</name>
1582 
              <description>Enable WKUP pin</description>
1583 
              <bitOffset>8</bitOffset>
1584 
              <bitWidth>1</bitWidth>
1585 
              <access>read-write</access>
1586 
            </field>
1587 
          </fields>
1588 
        </register>
1589 
      </registers>
1590 
    </peripheral>
1591 
    <peripheral>
1592 
      <name>RCC</name>
1593 
      <description>Reset and clock control</description>
1594 
      <groupName>RCC</groupName>
1595 
      <baseAddress>0x40021000</baseAddress>
1596 
      <addressBlock>
1597 
        <offset>0x0</offset>
1598 
        <size>0x400</size>
1599 
        <usage>registers</usage>
1600 
      </addressBlock>
1601 
      <interrupt>
1602 
        <name>RCC</name>
1603 
        <description>RCC global interrupt</description>
1604 
        <value>5</value>
1605 
      </interrupt>
1606 
      <registers>
1607 
        <register>
1608 
          <name>CR</name>
1609 
          <displayName>CR</displayName>
1610 
          <description>Clock control register</description>
1611 
          <addressOffset>0x0</addressOffset>
1612 
          <size>0x20</size>
1613 
          <resetValue>0x00000083</resetValue>
1614 
          <fields>
1615 
            <field>
1616 
              <name>HSION</name>
1617 
              <description>Internal High Speed clock
1618 
              enable</description>
1619 
              <bitOffset>0</bitOffset>
1620 
              <bitWidth>1</bitWidth>
1621 
              <access>read-write</access>
1622 
            </field>
1623 
            <field>
1624 
              <name>HSIRDY</name>
1625 
              <description>Internal High Speed clock ready
1626 
              flag</description>
1627 
              <bitOffset>1</bitOffset>
1628 
              <bitWidth>1</bitWidth>
1629 
              <access>read-only</access>
1630 
            </field>
1631 
            <field>
1632 
              <name>HSITRIM</name>
1633 
              <description>Internal High Speed clock
1634 
              trimming</description>
1635 
              <bitOffset>3</bitOffset>
1636 
              <bitWidth>5</bitWidth>
1637 
              <access>read-write</access>
1638 
            </field>
1639 
            <field>
1640 
              <name>HSICAL</name>
1641 
              <description>Internal High Speed clock
1642 
              Calibration</description>
1643 
              <bitOffset>8</bitOffset>
1644 
              <bitWidth>8</bitWidth>
1645 
              <access>read-only</access>
1646 
            </field>
1647 
            <field>
1648 
              <name>HSEON</name>
1649 
              <description>External High Speed clock
1650 
              enable</description>
1651 
              <bitOffset>16</bitOffset>
1652 
              <bitWidth>1</bitWidth>
1653 
              <access>read-write</access>
1654 
            </field>
1655 
            <field>
1656 
              <name>HSERDY</name>
1657 
              <description>External High Speed clock ready
1658 
              flag</description>
1659 
              <bitOffset>17</bitOffset>
1660 
              <bitWidth>1</bitWidth>
1661 
              <access>read-only</access>
1662 
            </field>
1663 
            <field>
1664 
              <name>HSEBYP</name>
1665 
              <description>External High Speed clock
1666 
              Bypass</description>
1667 
              <bitOffset>18</bitOffset>
1668 
              <bitWidth>1</bitWidth>
1669 
              <access>read-write</access>
1670 
            </field>
1671 
            <field>
1672 
              <name>CSSON</name>
1673 
              <description>Clock Security System
1674 
              enable</description>
1675 
              <bitOffset>19</bitOffset>
1676 
              <bitWidth>1</bitWidth>
1677 
              <access>read-write</access>
1678 
            </field>
1679 
            <field>
1680 
              <name>PLLON</name>
1681 
              <description>PLL enable</description>
1682 
              <bitOffset>24</bitOffset>
1683 
              <bitWidth>1</bitWidth>
1684 
              <access>read-write</access>
1685 
            </field>
1686 
            <field>
1687 
              <name>PLLRDY</name>
1688 
              <description>PLL clock ready flag</description>
1689 
              <bitOffset>25</bitOffset>
1690 
              <bitWidth>1</bitWidth>
1691 
              <access>read-only</access>
1692 
            </field>
1693 
          </fields>
1694 
        </register>
1695 
        <register>
1696 
          <name>CFGR</name>
1697 
          <displayName>CFGR</displayName>
1698 
          <description>Clock configuration register
1699 
          (RCC_CFGR)</description>
1700 
          <addressOffset>0x4</addressOffset>
1701 
          <size>0x20</size>
1702 
          <resetValue>0x00000000</resetValue>
1703 
          <fields>
1704 
            <field>
1705 
              <name>SW</name>
1706 
              <description>System clock Switch</description>
1707 
              <bitOffset>0</bitOffset>
1708 
              <bitWidth>2</bitWidth>
1709 
              <access>read-write</access>
1710 
            </field>
1711 
            <field>
1712 
              <name>SWS</name>
1713 
              <description>System Clock Switch Status</description>
1714 
              <bitOffset>2</bitOffset>
1715 
              <bitWidth>2</bitWidth>
1716 
              <access>read-only</access>
1717 
            </field>
1718 
            <field>
1719 
              <name>HPRE</name>
1720 
              <description>AHB prescaler</description>
1721 
              <bitOffset>4</bitOffset>
1722 
              <bitWidth>4</bitWidth>
1723 
              <access>read-write</access>
1724 
            </field>
1725 
            <field>
1726 
              <name>PPRE1</name>
1727 
              <description>APB Low speed prescaler
1728 
              (APB1)</description>
1729 
              <bitOffset>8</bitOffset>
1730 
              <bitWidth>3</bitWidth>
1731 
              <access>read-write</access>
1732 
            </field>
1733 
            <field>
1734 
              <name>PPRE2</name>
1735 
              <description>APB High speed prescaler
1736 
              (APB2)</description>
1737 
              <bitOffset>11</bitOffset>
1738 
              <bitWidth>3</bitWidth>
1739 
              <access>read-write</access>
1740 
            </field>
1741 
            <field>
1742 
              <name>ADCPRE</name>
1743 
              <description>ADC prescaler</description>
1744 
              <bitOffset>14</bitOffset>
1745 
              <bitWidth>2</bitWidth>
1746 
              <access>read-write</access>
1747 
            </field>
1748 
            <field>
1749 
              <name>PLLSRC</name>
1750 
              <description>PLL entry clock source</description>
1751 
              <bitOffset>16</bitOffset>
1752 
              <bitWidth>1</bitWidth>
1753 
              <access>read-write</access>
1754 
            </field>
1755 
            <field>
1756 
              <name>PLLXTPRE</name>
1757 
              <description>HSE divider for PLL entry</description>
1758 
              <bitOffset>17</bitOffset>
1759 
              <bitWidth>1</bitWidth>
1760 
              <access>read-write</access>
1761 
            </field>
1762 
            <field>
1763 
              <name>PLLMUL</name>
1764 
              <description>PLL Multiplication Factor</description>
1765 
              <bitOffset>18</bitOffset>
1766 
              <bitWidth>4</bitWidth>
1767 
              <access>read-write</access>
1768 
            </field>
1769 
            <field>
1770 
              <name>OTGFSPRE</name>
1771 
              <description>USB OTG FS prescaler</description>
1772 
              <bitOffset>22</bitOffset>
1773 
              <bitWidth>1</bitWidth>
1774 
              <access>read-write</access>
1775 
            </field>
1776 
            <field>
1777 
              <name>MCO</name>
1778 
              <description>Microcontroller clock
1779 
              output</description>
1780 
              <bitOffset>24</bitOffset>
1781 
              <bitWidth>3</bitWidth>
1782 
              <access>read-write</access>
1783 
            </field>
1784 
          </fields>
1785 
        </register>
1786 
        <register>
1787 
          <name>CIR</name>
1788 
          <displayName>CIR</displayName>
1789 
          <description>Clock interrupt register
1790 
          (RCC_CIR)</description>
1791 
          <addressOffset>0x8</addressOffset>
1792 
          <size>0x20</size>
1793 
          <resetValue>0x00000000</resetValue>
1794 
          <fields>
1795 
            <field>
1796 
              <name>LSIRDYF</name>
1797 
              <description>LSI Ready Interrupt flag</description>
1798 
              <bitOffset>0</bitOffset>
1799 
              <bitWidth>1</bitWidth>
1800 
              <access>read-only</access>
1801 
            </field>
1802 
            <field>
1803 
              <name>LSERDYF</name>
1804 
              <description>LSE Ready Interrupt flag</description>
1805 
              <bitOffset>1</bitOffset>
1806 
              <bitWidth>1</bitWidth>
1807 
              <access>read-only</access>
1808 
            </field>
1809 
            <field>
1810 
              <name>HSIRDYF</name>
1811 
              <description>HSI Ready Interrupt flag</description>
1812 
              <bitOffset>2</bitOffset>
1813 
              <bitWidth>1</bitWidth>
1814 
              <access>read-only</access>
1815 
            </field>
1816 
            <field>
1817 
              <name>HSERDYF</name>
1818 
              <description>HSE Ready Interrupt flag</description>
1819 
              <bitOffset>3</bitOffset>
1820 
              <bitWidth>1</bitWidth>
1821 
              <access>read-only</access>
1822 
            </field>
1823 
            <field>
1824 
              <name>PLLRDYF</name>
1825 
              <description>PLL Ready Interrupt flag</description>
1826 
              <bitOffset>4</bitOffset>
1827 
              <bitWidth>1</bitWidth>
1828 
              <access>read-only</access>
1829 
            </field>
1830 
            <field>
1831 
              <name>CSSF</name>
1832 
              <description>Clock Security System Interrupt
1833 
              flag</description>
1834 
              <bitOffset>7</bitOffset>
1835 
              <bitWidth>1</bitWidth>
1836 
              <access>read-only</access>
1837 
            </field>
1838 
            <field>
1839 
              <name>LSIRDYIE</name>
1840 
              <description>LSI Ready Interrupt Enable</description>
1841 
              <bitOffset>8</bitOffset>
1842 
              <bitWidth>1</bitWidth>
1843 
              <access>read-write</access>
1844 
            </field>
1845 
            <field>
1846 
              <name>LSERDYIE</name>
1847 
              <description>LSE Ready Interrupt Enable</description>
1848 
              <bitOffset>9</bitOffset>
1849 
              <bitWidth>1</bitWidth>
1850 
              <access>read-write</access>
1851 
            </field>
1852 
            <field>
1853 
              <name>HSIRDYIE</name>
1854 
              <description>HSI Ready Interrupt Enable</description>
1855 
              <bitOffset>10</bitOffset>
1856 
              <bitWidth>1</bitWidth>
1857 
              <access>read-write</access>
1858 
            </field>
1859 
            <field>
1860 
              <name>HSERDYIE</name>
1861 
              <description>HSE Ready Interrupt Enable</description>
1862 
              <bitOffset>11</bitOffset>
1863 
              <bitWidth>1</bitWidth>
1864 
              <access>read-write</access>
1865 
            </field>
1866 
            <field>
1867 
              <name>PLLRDYIE</name>
1868 
              <description>PLL Ready Interrupt Enable</description>
1869 
              <bitOffset>12</bitOffset>
1870 
              <bitWidth>1</bitWidth>
1871 
              <access>read-write</access>
1872 
            </field>
1873 
            <field>
1874 
              <name>LSIRDYC</name>
1875 
              <description>LSI Ready Interrupt Clear</description>
1876 
              <bitOffset>16</bitOffset>
1877 
              <bitWidth>1</bitWidth>
1878 
              <access>write-only</access>
1879 
            </field>
1880 
            <field>
1881 
              <name>LSERDYC</name>
1882 
              <description>LSE Ready Interrupt Clear</description>
1883 
              <bitOffset>17</bitOffset>
1884 
              <bitWidth>1</bitWidth>
1885 
              <access>write-only</access>
1886 
            </field>
1887 
            <field>
1888 
              <name>HSIRDYC</name>
1889 
              <description>HSI Ready Interrupt Clear</description>
1890 
              <bitOffset>18</bitOffset>
1891 
              <bitWidth>1</bitWidth>
1892 
              <access>write-only</access>
1893 
            </field>
1894 
            <field>
1895 
              <name>HSERDYC</name>
1896 
              <description>HSE Ready Interrupt Clear</description>
1897 
              <bitOffset>19</bitOffset>
1898 
              <bitWidth>1</bitWidth>
1899 
              <access>write-only</access>
1900 
            </field>
1901 
            <field>
1902 
              <name>PLLRDYC</name>
1903 
              <description>PLL Ready Interrupt Clear</description>
1904 
              <bitOffset>20</bitOffset>
1905 
              <bitWidth>1</bitWidth>
1906 
              <access>write-only</access>
1907 
            </field>
1908 
            <field>
1909 
              <name>CSSC</name>
1910 
              <description>Clock security system interrupt
1911 
              clear</description>
1912 
              <bitOffset>23</bitOffset>
1913 
              <bitWidth>1</bitWidth>
1914 
              <access>write-only</access>
1915 
            </field>
1916 
          </fields>
1917 
        </register>
1918 
        <register>
1919 
          <name>APB2RSTR</name>
1920 
          <displayName>APB2RSTR</displayName>
1921 
          <description>APB2 peripheral reset register
1922 
          (RCC_APB2RSTR)</description>
1923 
          <addressOffset>0xC</addressOffset>
1924 
          <size>0x20</size>
1925 
          <access>read-write</access>
1926 
          <resetValue>0x000000000</resetValue>
1927 
          <fields>
1928 
            <field>
1929 
              <name>AFIORST</name>
1930 
              <description>Alternate function I/O
1931 
              reset</description>
1932 
              <bitOffset>0</bitOffset>
1933 
              <bitWidth>1</bitWidth>
1934 
            </field>
1935 
            <field>
1936 
              <name>IOPARST</name>
1937 
              <description>IO port A reset</description>
1938 
              <bitOffset>2</bitOffset>
1939 
              <bitWidth>1</bitWidth>
1940 
            </field>
1941 
            <field>
1942 
              <name>IOPBRST</name>
1943 
              <description>IO port B reset</description>
1944 
              <bitOffset>3</bitOffset>
1945 
              <bitWidth>1</bitWidth>
1946 
            </field>
1947 
            <field>
1948 
              <name>IOPCRST</name>
1949 
              <description>IO port C reset</description>
1950 
              <bitOffset>4</bitOffset>
1951 
              <bitWidth>1</bitWidth>
1952 
            </field>
1953 
            <field>
1954 
              <name>IOPDRST</name>
1955 
              <description>IO port D reset</description>
1956 
              <bitOffset>5</bitOffset>
1957 
              <bitWidth>1</bitWidth>
1958 
            </field>
1959 
            <field>
1960 
              <name>IOPERST</name>
1961 
              <description>IO port E reset</description>
1962 
              <bitOffset>6</bitOffset>
1963 
              <bitWidth>1</bitWidth>
1964 
            </field>
1965 
            <field>
1966 
              <name>IOPFRST</name>
1967 
              <description>IO port F reset</description>
1968 
              <bitOffset>7</bitOffset>
1969 
              <bitWidth>1</bitWidth>
1970 
            </field>
1971 
            <field>
1972 
              <name>IOPGRST</name>
1973 
              <description>IO port G reset</description>
1974 
              <bitOffset>8</bitOffset>
1975 
              <bitWidth>1</bitWidth>
1976 
            </field>
1977 
            <field>
1978 
              <name>ADC1RST</name>
1979 
              <description>ADC 1 interface reset</description>
1980 
              <bitOffset>9</bitOffset>
1981 
              <bitWidth>1</bitWidth>
1982 
            </field>
1983 
            <field>
1984 
              <name>ADC2RST</name>
1985 
              <description>ADC 2 interface reset</description>
1986 
              <bitOffset>10</bitOffset>
1987 
              <bitWidth>1</bitWidth>
1988 
            </field>
1989 
            <field>
1990 
              <name>TIM1RST</name>
1991 
              <description>TIM1 timer reset</description>
1992 
              <bitOffset>11</bitOffset>
1993 
              <bitWidth>1</bitWidth>
1994 
            </field>
1995 
            <field>
1996 
              <name>SPI1RST</name>
1997 
              <description>SPI 1 reset</description>
1998 
              <bitOffset>12</bitOffset>
1999 
              <bitWidth>1</bitWidth>
2000 
            </field>
2001 
            <field>
2002 
              <name>TIM8RST</name>
2003 
              <description>TIM8 timer reset</description>
2004 
              <bitOffset>13</bitOffset>
2005 
              <bitWidth>1</bitWidth>
2006 
            </field>
2007 
            <field>
2008 
              <name>USART1RST</name>
2009 
              <description>USART1 reset</description>
2010 
              <bitOffset>14</bitOffset>
2011 
              <bitWidth>1</bitWidth>
2012 
            </field>
2013 
            <field>
2014 
              <name>ADC3RST</name>
2015 
              <description>ADC 3 interface reset</description>
2016 
              <bitOffset>15</bitOffset>
2017 
              <bitWidth>1</bitWidth>
2018 
            </field>
2019 
            <field>
2020 
              <name>TIM9RST</name>
2021 
              <description>TIM9 timer reset</description>
2022 
              <bitOffset>19</bitOffset>
2023 
              <bitWidth>1</bitWidth>
2024 
            </field>
2025 
            <field>
2026 
              <name>TIM10RST</name>
2027 
              <description>TIM10 timer reset</description>
2028 
              <bitOffset>20</bitOffset>
2029 
              <bitWidth>1</bitWidth>
2030 
            </field>
2031 
            <field>
2032 
              <name>TIM11RST</name>
2033 
              <description>TIM11 timer reset</description>
2034 
              <bitOffset>21</bitOffset>
2035 
              <bitWidth>1</bitWidth>
2036 
            </field>
2037 
          </fields>
2038 
        </register>
2039 
        <register>
2040 
          <name>APB1RSTR</name>
2041 
          <displayName>APB1RSTR</displayName>
2042 
          <description>APB1 peripheral reset register
2043 
          (RCC_APB1RSTR)</description>
2044 
          <addressOffset>0x10</addressOffset>
2045 
          <size>0x20</size>
2046 
          <access>read-write</access>
2047 
          <resetValue>0x00000000</resetValue>
2048 
          <fields>
2049 
            <field>
2050 
              <name>TIM2RST</name>
2051 
              <description>Timer 2 reset</description>
2052 
              <bitOffset>0</bitOffset>
2053 
              <bitWidth>1</bitWidth>
2054 
            </field>
2055 
            <field>
2056 
              <name>TIM3RST</name>
2057 
              <description>Timer 3 reset</description>
2058 
              <bitOffset>1</bitOffset>
2059 
              <bitWidth>1</bitWidth>
2060 
            </field>
2061 
            <field>
2062 
              <name>TIM4RST</name>
2063 
              <description>Timer 4 reset</description>
2064 
              <bitOffset>2</bitOffset>
2065 
              <bitWidth>1</bitWidth>
2066 
            </field>
2067 
            <field>
2068 
              <name>TIM5RST</name>
2069 
              <description>Timer 5 reset</description>
2070 
              <bitOffset>3</bitOffset>
2071 
              <bitWidth>1</bitWidth>
2072 
            </field>
2073 
            <field>
2074 
              <name>TIM6RST</name>
2075 
              <description>Timer 6 reset</description>
2076 
              <bitOffset>4</bitOffset>
2077 
              <bitWidth>1</bitWidth>
2078 
            </field>
2079 
            <field>
2080 
              <name>TIM7RST</name>
2081 
              <description>Timer 7 reset</description>
2082 
              <bitOffset>5</bitOffset>
2083 
              <bitWidth>1</bitWidth>
2084 
            </field>
2085 
            <field>
2086 
              <name>TIM12RST</name>
2087 
              <description>Timer 12 reset</description>
2088 
              <bitOffset>6</bitOffset>
2089 
              <bitWidth>1</bitWidth>
2090 
            </field>
2091 
            <field>
2092 
              <name>TIM13RST</name>
2093 
              <description>Timer 13 reset</description>
2094 
              <bitOffset>7</bitOffset>
2095 
              <bitWidth>1</bitWidth>
2096 
            </field>
2097 
            <field>
2098 
              <name>TIM14RST</name>
2099 
              <description>Timer 14 reset</description>
2100 
              <bitOffset>8</bitOffset>
2101 
              <bitWidth>1</bitWidth>
2102 
            </field>
2103 
            <field>
2104 
              <name>WWDGRST</name>
2105 
              <description>Window watchdog reset</description>
2106 
              <bitOffset>11</bitOffset>
2107 
              <bitWidth>1</bitWidth>
2108 
            </field>
2109 
            <field>
2110 
              <name>SPI2RST</name>
2111 
              <description>SPI2 reset</description>
2112 
              <bitOffset>14</bitOffset>
2113 
              <bitWidth>1</bitWidth>
2114 
            </field>
2115 
            <field>
2116 
              <name>SPI3RST</name>
2117 
              <description>SPI3 reset</description>
2118 
              <bitOffset>15</bitOffset>
2119 
              <bitWidth>1</bitWidth>
2120 
            </field>
2121 
            <field>
2122 
              <name>USART2RST</name>
2123 
              <description>USART 2 reset</description>
2124 
              <bitOffset>17</bitOffset>
2125 
              <bitWidth>1</bitWidth>
2126 
            </field>
2127 
            <field>
2128 
              <name>USART3RST</name>
2129 
              <description>USART 3 reset</description>
2130 
              <bitOffset>18</bitOffset>
2131 
              <bitWidth>1</bitWidth>
2132 
            </field>
2133 
            <field>
2134 
              <name>UART4RST</name>
2135 
              <description>UART 4 reset</description>
2136 
              <bitOffset>19</bitOffset>
2137 
              <bitWidth>1</bitWidth>
2138 
            </field>
2139 
            <field>
2140 
              <name>UART5RST</name>
2141 
              <description>UART 5 reset</description>
2142 
              <bitOffset>20</bitOffset>
2143 
              <bitWidth>1</bitWidth>
2144 
            </field>
2145 
            <field>
2146 
              <name>I2C1RST</name>
2147 
              <description>I2C1 reset</description>
2148 
              <bitOffset>21</bitOffset>
2149 
              <bitWidth>1</bitWidth>
2150 
            </field>
2151 
            <field>
2152 
              <name>I2C2RST</name>
2153 
              <description>I2C2 reset</description>
2154 
              <bitOffset>22</bitOffset>
2155 
              <bitWidth>1</bitWidth>
2156 
            </field>
2157 
            <field>
2158 
              <name>USBRST</name>
2159 
              <description>USB reset</description>
2160 
              <bitOffset>23</bitOffset>
2161 
              <bitWidth>1</bitWidth>
2162 
            </field>
2163 
            <field>
2164 
              <name>CANRST</name>
2165 
              <description>CAN reset</description>
2166 
              <bitOffset>25</bitOffset>
2167 
              <bitWidth>1</bitWidth>
2168 
            </field>
2169 
            <field>
2170 
              <name>BKPRST</name>
2171 
              <description>Backup interface reset</description>
2172 
              <bitOffset>27</bitOffset>
2173 
              <bitWidth>1</bitWidth>
2174 
            </field>
2175 
            <field>
2176 
              <name>PWRRST</name>
2177 
              <description>Power interface reset</description>
2178 
              <bitOffset>28</bitOffset>
2179 
              <bitWidth>1</bitWidth>
2180 
            </field>
2181 
            <field>
2182 
              <name>DACRST</name>
2183 
              <description>DAC interface reset</description>
2184 
              <bitOffset>29</bitOffset>
2185 
              <bitWidth>1</bitWidth>
2186 
            </field>
2187 
          </fields>
2188 
        </register>
2189 
        <register>
2190 
          <name>AHBENR</name>
2191 
          <displayName>AHBENR</displayName>
2192 
          <description>AHB Peripheral Clock enable register
2193 
          (RCC_AHBENR)</description>
2194 
          <addressOffset>0x14</addressOffset>
2195 
          <size>0x20</size>
2196 
          <access>read-write</access>
2197 
          <resetValue>0x00000014</resetValue>
2198 
          <fields>
2199 
            <field>
2200 
              <name>DMA1EN</name>
2201 
              <description>DMA1 clock enable</description>
2202 
              <bitOffset>0</bitOffset>
2203 
              <bitWidth>1</bitWidth>
2204 
            </field>
2205 
            <field>
2206 
              <name>DMA2EN</name>
2207 
              <description>DMA2 clock enable</description>
2208 
              <bitOffset>1</bitOffset>
2209 
              <bitWidth>1</bitWidth>
2210 
            </field>
2211 
            <field>
2212 
              <name>SRAMEN</name>
2213 
              <description>SRAM interface clock
2214 
              enable</description>
2215 
              <bitOffset>2</bitOffset>
2216 
              <bitWidth>1</bitWidth>
2217 
            </field>
2218 
            <field>
2219 
              <name>FLITFEN</name>
2220 
              <description>FLITF clock enable</description>
2221 
              <bitOffset>4</bitOffset>
2222 
              <bitWidth>1</bitWidth>
2223 
            </field>
2224 
            <field>
2225 
              <name>CRCEN</name>
2226 
              <description>CRC clock enable</description>
2227 
              <bitOffset>6</bitOffset>
2228 
              <bitWidth>1</bitWidth>
2229 
            </field>
2230 
            <field>
2231 
              <name>FSMCEN</name>
2232 
              <description>FSMC clock enable</description>
2233 
              <bitOffset>8</bitOffset>
2234 
              <bitWidth>1</bitWidth>
2235 
            </field>
2236 
            <field>
2237 
              <name>SDIOEN</name>
2238 
              <description>SDIO clock enable</description>
2239 
              <bitOffset>10</bitOffset>
2240 
              <bitWidth>1</bitWidth>
2241 
            </field>
2242 
          </fields>
2243 
        </register>
2244 
        <register>
2245 
          <name>APB2ENR</name>
2246 
          <displayName>APB2ENR</displayName>
2247 
          <description>APB2 peripheral clock enable register
2248 
          (RCC_APB2ENR)</description>
2249 
          <addressOffset>0x18</addressOffset>
2250 
          <size>0x20</size>
2251 
          <access>read-write</access>
2252 
          <resetValue>0x00000000</resetValue>
2253 
          <fields>
2254 
            <field>
2255 
              <name>AFIOEN</name>
2256 
              <description>Alternate function I/O clock
2257 
              enable</description>
2258 
              <bitOffset>0</bitOffset>
2259 
              <bitWidth>1</bitWidth>
2260 
            </field>
2261 
            <field>
2262 
              <name>IOPAEN</name>
2263 
              <description>I/O port A clock enable</description>
2264 
              <bitOffset>2</bitOffset>
2265 
              <bitWidth>1</bitWidth>
2266 
            </field>
2267 
            <field>
2268 
              <name>IOPBEN</name>
2269 
              <description>I/O port B clock enable</description>
2270 
              <bitOffset>3</bitOffset>
2271 
              <bitWidth>1</bitWidth>
2272 
            </field>
2273 
            <field>
2274 
              <name>IOPCEN</name>
2275 
              <description>I/O port C clock enable</description>
2276 
              <bitOffset>4</bitOffset>
2277 
              <bitWidth>1</bitWidth>
2278 
            </field>
2279 
            <field>
2280 
              <name>IOPDEN</name>
2281 
              <description>I/O port D clock enable</description>
2282 
              <bitOffset>5</bitOffset>
2283 
              <bitWidth>1</bitWidth>
2284 
            </field>
2285 
            <field>
2286 
              <name>IOPEEN</name>
2287 
              <description>I/O port E clock enable</description>
2288 
              <bitOffset>6</bitOffset>
2289 
              <bitWidth>1</bitWidth>
2290 
            </field>
2291 
            <field>
2292 
              <name>IOPFEN</name>
2293 
              <description>I/O port F clock enable</description>
2294 
              <bitOffset>7</bitOffset>
2295 
              <bitWidth>1</bitWidth>
2296 
            </field>
2297 
            <field>
2298 
              <name>IOPGEN</name>
2299 
              <description>I/O port G clock enable</description>
2300 
              <bitOffset>8</bitOffset>
2301 
              <bitWidth>1</bitWidth>
2302 
            </field>
2303 
            <field>
2304 
              <name>ADC1EN</name>
2305 
              <description>ADC 1 interface clock
2306 
              enable</description>
2307 
              <bitOffset>9</bitOffset>
2308 
              <bitWidth>1</bitWidth>
2309 
            </field>
2310 
            <field>
2311 
              <name>ADC2EN</name>
2312 
              <description>ADC 2 interface clock
2313 
              enable</description>
2314 
              <bitOffset>10</bitOffset>
2315 
              <bitWidth>1</bitWidth>
2316 
            </field>
2317 
            <field>
2318 
              <name>TIM1EN</name>
2319 
              <description>TIM1 Timer clock enable</description>
2320 
              <bitOffset>11</bitOffset>
2321 
              <bitWidth>1</bitWidth>
2322 
            </field>
2323 
            <field>
2324 
              <name>SPI1EN</name>
2325 
              <description>SPI 1 clock enable</description>
2326 
              <bitOffset>12</bitOffset>
2327 
              <bitWidth>1</bitWidth>
2328 
            </field>
2329 
            <field>
2330 
              <name>TIM8EN</name>
2331 
              <description>TIM8 Timer clock enable</description>
2332 
              <bitOffset>13</bitOffset>
2333 
              <bitWidth>1</bitWidth>
2334 
            </field>
2335 
            <field>
2336 
              <name>USART1EN</name>
2337 
              <description>USART1 clock enable</description>
2338 
              <bitOffset>14</bitOffset>
2339 
              <bitWidth>1</bitWidth>
2340 
            </field>
2341 
            <field>
2342 
              <name>ADC3EN</name>
2343 
              <description>ADC3 interface clock
2344 
              enable</description>
2345 
              <bitOffset>15</bitOffset>
2346 
              <bitWidth>1</bitWidth>
2347 
            </field>
2348 
            <field>
2349 
              <name>TIM9EN</name>
2350 
              <description>TIM9 Timer clock enable</description>
2351 
              <bitOffset>19</bitOffset>
2352 
              <bitWidth>1</bitWidth>
2353 
            </field>
2354 
            <field>
2355 
              <name>TIM10EN</name>
2356 
              <description>TIM10 Timer clock enable</description>
2357 
              <bitOffset>20</bitOffset>
2358 
              <bitWidth>1</bitWidth>
2359 
            </field>
2360 
            <field>
2361 
              <name>TIM11EN</name>
2362 
              <description>TIM11 Timer clock enable</description>
2363 
              <bitOffset>21</bitOffset>
2364 
              <bitWidth>1</bitWidth>
2365 
            </field>
2366 
          </fields>
2367 
        </register>
2368 
        <register>
2369 
          <name>APB1ENR</name>
2370 
          <displayName>APB1ENR</displayName>
2371 
          <description>APB1 peripheral clock enable register
2372 
          (RCC_APB1ENR)</description>
2373 
          <addressOffset>0x1C</addressOffset>
2374 
          <size>0x20</size>
2375 
          <access>read-write</access>
2376 
          <resetValue>0x00000000</resetValue>
2377 
          <fields>
2378 
            <field>
2379 
              <name>TIM2EN</name>
2380 
              <description>Timer 2 clock enable</description>
2381 
              <bitOffset>0</bitOffset>
2382 
              <bitWidth>1</bitWidth>
2383 
            </field>
2384 
            <field>
2385 
              <name>TIM3EN</name>
2386 
              <description>Timer 3 clock enable</description>
2387 
              <bitOffset>1</bitOffset>
2388 
              <bitWidth>1</bitWidth>
2389 
            </field>
2390 
            <field>
2391 
              <name>TIM4EN</name>
2392 
              <description>Timer 4 clock enable</description>
2393 
              <bitOffset>2</bitOffset>
2394 
              <bitWidth>1</bitWidth>
2395 
            </field>
2396 
            <field>
2397 
              <name>TIM5EN</name>
2398 
              <description>Timer 5 clock enable</description>
2399 
              <bitOffset>3</bitOffset>
2400 
              <bitWidth>1</bitWidth>
2401 
            </field>
2402 
            <field>
2403 
              <name>TIM6EN</name>
2404 
              <description>Timer 6 clock enable</description>
2405 
              <bitOffset>4</bitOffset>
2406 
              <bitWidth>1</bitWidth>
2407 
            </field>
2408 
            <field>
2409 
              <name>TIM7EN</name>
2410 
              <description>Timer 7 clock enable</description>
2411 
              <bitOffset>5</bitOffset>
2412 
              <bitWidth>1</bitWidth>
2413 
            </field>
2414 
            <field>
2415 
              <name>TIM12EN</name>
2416 
              <description>Timer 12 clock enable</description>
2417 
              <bitOffset>6</bitOffset>
2418 
              <bitWidth>1</bitWidth>
2419 
            </field>
2420 
            <field>
2421 
              <name>TIM13EN</name>
2422 
              <description>Timer 13 clock enable</description>
2423 
              <bitOffset>7</bitOffset>
2424 
              <bitWidth>1</bitWidth>
2425 
            </field>
2426 
            <field>
2427 
              <name>TIM14EN</name>
2428 
              <description>Timer 14 clock enable</description>
2429 
              <bitOffset>8</bitOffset>
2430 
              <bitWidth>1</bitWidth>
2431 
            </field>
2432 
            <field>
2433 
              <name>WWDGEN</name>
2434 
              <description>Window watchdog clock
2435 
              enable</description>
2436 
              <bitOffset>11</bitOffset>
2437 
              <bitWidth>1</bitWidth>
2438 
            </field>
2439 
            <field>
2440 
              <name>SPI2EN</name>
2441 
              <description>SPI 2 clock enable</description>
2442 
              <bitOffset>14</bitOffset>
2443 
              <bitWidth>1</bitWidth>
2444 
            </field>
2445 
            <field>
2446 
              <name>SPI3EN</name>
2447 
              <description>SPI 3 clock enable</description>
2448 
              <bitOffset>15</bitOffset>
2449 
              <bitWidth>1</bitWidth>
2450 
            </field>
2451 
            <field>
2452 
              <name>USART2EN</name>
2453 
              <description>USART 2 clock enable</description>
2454 
              <bitOffset>17</bitOffset>
2455 
              <bitWidth>1</bitWidth>
2456 
            </field>
2457 
            <field>
2458 
              <name>USART3EN</name>
2459 
              <description>USART 3 clock enable</description>
2460 
              <bitOffset>18</bitOffset>
2461 
              <bitWidth>1</bitWidth>
2462 
            </field>
2463 
            <field>
2464 
              <name>UART4EN</name>
2465 
              <description>UART 4 clock enable</description>
2466 
              <bitOffset>19</bitOffset>
2467 
              <bitWidth>1</bitWidth>
2468 
            </field>
2469 
            <field>
2470 
              <name>UART5EN</name>
2471 
              <description>UART 5 clock enable</description>
2472 
              <bitOffset>20</bitOffset>
2473 
              <bitWidth>1</bitWidth>
2474 
            </field>
2475 
            <field>
2476 
              <name>I2C1EN</name>
2477 
              <description>I2C 1 clock enable</description>
2478 
              <bitOffset>21</bitOffset>
2479 
              <bitWidth>1</bitWidth>
2480 
            </field>
2481 
            <field>
2482 
              <name>I2C2EN</name>
2483 
              <description>I2C 2 clock enable</description>
2484 
              <bitOffset>22</bitOffset>
2485 
              <bitWidth>1</bitWidth>
2486 
            </field>
2487 
            <field>
2488 
              <name>USBEN</name>
2489 
              <description>USB clock enable</description>
2490 
              <bitOffset>23</bitOffset>
2491 
              <bitWidth>1</bitWidth>
2492 
            </field>
2493 
            <field>
2494 
              <name>CANEN</name>
2495 
              <description>CAN clock enable</description>
2496 
              <bitOffset>25</bitOffset>
2497 
              <bitWidth>1</bitWidth>
2498 
            </field>
2499 
            <field>
2500 
              <name>BKPEN</name>
2501 
              <description>Backup interface clock
2502 
              enable</description>
2503 
              <bitOffset>27</bitOffset>
2504 
              <bitWidth>1</bitWidth>
2505 
            </field>
2506 
            <field>
2507 
              <name>PWREN</name>
2508 
              <description>Power interface clock
2509 
              enable</description>
2510 
              <bitOffset>28</bitOffset>
2511 
              <bitWidth>1</bitWidth>
2512 
            </field>
2513 
            <field>
2514 
              <name>DACEN</name>
2515 
              <description>DAC interface clock enable</description>
2516 
              <bitOffset>29</bitOffset>
2517 
              <bitWidth>1</bitWidth>
2518 
            </field>
2519 
          </fields>
2520 
        </register>
2521 
        <register>
2522 
          <name>BDCR</name>
2523 
          <displayName>BDCR</displayName>
2524 
          <description>Backup domain control register
2525 
          (RCC_BDCR)</description>
2526 
          <addressOffset>0x20</addressOffset>
2527 
          <size>0x20</size>
2528 
          <resetValue>0x00000000</resetValue>
2529 
          <fields>
2530 
            <field>
2531 
              <name>LSEON</name>
2532 
              <description>External Low Speed oscillator
2533 
              enable</description>
2534 
              <bitOffset>0</bitOffset>
2535 
              <bitWidth>1</bitWidth>
2536 
              <access>read-write</access>
2537 
            </field>
2538 
            <field>
2539 
              <name>LSERDY</name>
2540 
              <description>External Low Speed oscillator
2541 
              ready</description>
2542 
              <bitOffset>1</bitOffset>
2543 
              <bitWidth>1</bitWidth>
2544 
              <access>read-only</access>
2545 
            </field>
2546 
            <field>
2547 
              <name>LSEBYP</name>
2548 
              <description>External Low Speed oscillator
2549 
              bypass</description>
2550 
              <bitOffset>2</bitOffset>
2551 
              <bitWidth>1</bitWidth>
2552 
              <access>read-write</access>
2553 
            </field>
2554 
            <field>
2555 
              <name>RTCSEL</name>
2556 
              <description>RTC clock source selection</description>
2557 
              <bitOffset>8</bitOffset>
2558 
              <bitWidth>2</bitWidth>
2559 
              <access>read-write</access>
2560 
            </field>
2561 
            <field>
2562 
              <name>RTCEN</name>
2563 
              <description>RTC clock enable</description>
2564 
              <bitOffset>15</bitOffset>
2565 
              <bitWidth>1</bitWidth>
2566 
              <access>read-write</access>
2567 
            </field>
2568 
            <field>
2569 
              <name>BDRST</name>
2570 
              <description>Backup domain software
2571 
              reset</description>
2572 
              <bitOffset>16</bitOffset>
2573 
              <bitWidth>1</bitWidth>
2574 
              <access>read-write</access>
2575 
            </field>
2576 
          </fields>
2577 
        </register>
2578 
        <register>
2579 
          <name>CSR</name>
2580 
          <displayName>CSR</displayName>
2581 
          <description>Control/status register
2582 
          (RCC_CSR)</description>
2583 
          <addressOffset>0x24</addressOffset>
2584 
          <size>0x20</size>
2585 
          <resetValue>0x0C000000</resetValue>
2586 
          <fields>
2587 
            <field>
2588 
              <name>LSION</name>
2589 
              <description>Internal low speed oscillator
2590 
              enable</description>
2591 
              <bitOffset>0</bitOffset>
2592 
              <bitWidth>1</bitWidth>
2593 
              <access>read-write</access>
2594 
            </field>
2595 
            <field>
2596 
              <name>LSIRDY</name>
2597 
              <description>Internal low speed oscillator
2598 
              ready</description>
2599 
              <bitOffset>1</bitOffset>
2600 
              <bitWidth>1</bitWidth>
2601 
              <access>read-only</access>
2602 
            </field>
2603 
            <field>
2604 
              <name>RMVF</name>
2605 
              <description>Remove reset flag</description>
2606 
              <bitOffset>24</bitOffset>
2607 
              <bitWidth>1</bitWidth>
2608 
              <access>read-write</access>
2609 
            </field>
2610 
            <field>
2611 
              <name>PINRSTF</name>
2612 
              <description>PIN reset flag</description>
2613 
              <bitOffset>26</bitOffset>
2614 
              <bitWidth>1</bitWidth>
2615 
              <access>read-write</access>
2616 
            </field>
2617 
            <field>
2618 
              <name>PORRSTF</name>
2619 
              <description>POR/PDR reset flag</description>
2620 
              <bitOffset>27</bitOffset>
2621 
              <bitWidth>1</bitWidth>
2622 
              <access>read-write</access>
2623 
            </field>
2624 
            <field>
2625 
              <name>SFTRSTF</name>
2626 
              <description>Software reset flag</description>
2627 
              <bitOffset>28</bitOffset>
2628 
              <bitWidth>1</bitWidth>
2629 
              <access>read-write</access>
2630 
            </field>
2631 
            <field>
2632 
              <name>IWDGRSTF</name>
2633 
              <description>Independent watchdog reset
2634 
              flag</description>
2635 
              <bitOffset>29</bitOffset>
2636 
              <bitWidth>1</bitWidth>
2637 
              <access>read-write</access>
2638 
            </field>
2639 
            <field>
2640 
              <name>WWDGRSTF</name>
2641 
              <description>Window watchdog reset flag</description>
2642 
              <bitOffset>30</bitOffset>
2643 
              <bitWidth>1</bitWidth>
2644 
              <access>read-write</access>
2645 
            </field>
2646 
            <field>
2647 
              <name>LPWRRSTF</name>
2648 
              <description>Low-power reset flag</description>
2649 
              <bitOffset>31</bitOffset>
2650 
              <bitWidth>1</bitWidth>
2651 
              <access>read-write</access>
2652 
            </field>
2653 
          </fields>
2654 
        </register>
2655 
      </registers>
2656 
    </peripheral>
2657 
    <peripheral>
2658 
      <name>GPIOA</name>
2659 
      <description>General purpose I/O</description>
2660 
      <groupName>GPIO</groupName>
2661 
      <baseAddress>0x40010800</baseAddress>
2662 
      <addressBlock>
2663 
        <offset>0x0</offset>
2664 
        <size>0x400</size>
2665 
        <usage>registers</usage>
2666 
      </addressBlock>
2667 
      <registers>
2668 
        <register>
2669 
          <name>CRL</name>
2670 
          <displayName>CRL</displayName>
2671 
          <description>Port configuration register low
2672 
          (GPIOn_CRL)</description>
2673 
          <addressOffset>0x0</addressOffset>
2674 
          <size>0x20</size>
2675 
          <access>read-write</access>
2676 
          <resetValue>0x44444444</resetValue>
2677 
          <fields>
2678 
            <field>
2679 
              <name>MODE0</name>
2680 
              <description>Port n.0 mode bits</description>
2681 
              <bitOffset>0</bitOffset>
2682 
              <bitWidth>2</bitWidth>
2683 
            </field>
2684 
            <field>
2685 
              <name>CNF0</name>
2686 
              <description>Port n.0 configuration
2687 
              bits</description>
2688 
              <bitOffset>2</bitOffset>
2689 
              <bitWidth>2</bitWidth>
2690 
            </field>
2691 
            <field>
2692 
              <name>MODE1</name>
2693 
              <description>Port n.1 mode bits</description>
2694 
              <bitOffset>4</bitOffset>
2695 
              <bitWidth>2</bitWidth>
2696 
            </field>
2697 
            <field>
2698 
              <name>CNF1</name>
2699 
              <description>Port n.1 configuration
2700 
              bits</description>
2701 
              <bitOffset>6</bitOffset>
2702 
              <bitWidth>2</bitWidth>
2703 
            </field>
2704 
            <field>
2705 
              <name>MODE2</name>
2706 
              <description>Port n.2 mode bits</description>
2707 
              <bitOffset>8</bitOffset>
2708 
              <bitWidth>2</bitWidth>
2709 
            </field>
2710 
            <field>
2711 
              <name>CNF2</name>
2712 
              <description>Port n.2 configuration
2713 
              bits</description>
2714 
              <bitOffset>10</bitOffset>
2715 
              <bitWidth>2</bitWidth>
2716 
            </field>
2717 
            <field>
2718 
              <name>MODE3</name>
2719 
              <description>Port n.3 mode bits</description>
2720 
              <bitOffset>12</bitOffset>
2721 
              <bitWidth>2</bitWidth>
2722 
            </field>
2723 
            <field>
2724 
              <name>CNF3</name>
2725 
              <description>Port n.3 configuration
2726 
              bits</description>
2727 
              <bitOffset>14</bitOffset>
2728 
              <bitWidth>2</bitWidth>
2729 
            </field>
2730 
            <field>
2731 
              <name>MODE4</name>
2732 
              <description>Port n.4 mode bits</description>
2733 
              <bitOffset>16</bitOffset>
2734 
              <bitWidth>2</bitWidth>
2735 
            </field>
2736 
            <field>
2737 
              <name>CNF4</name>
2738 
              <description>Port n.4 configuration
2739 
              bits</description>
2740 
              <bitOffset>18</bitOffset>
2741 
              <bitWidth>2</bitWidth>
2742 
            </field>
2743 
            <field>
2744 
              <name>MODE5</name>
2745 
              <description>Port n.5 mode bits</description>
2746 
              <bitOffset>20</bitOffset>
2747 
              <bitWidth>2</bitWidth>
2748 
            </field>
2749 
            <field>
2750 
              <name>CNF5</name>
2751 
              <description>Port n.5 configuration
2752 
              bits</description>
2753 
              <bitOffset>22</bitOffset>
2754 
              <bitWidth>2</bitWidth>
2755 
            </field>
2756 
            <field>
2757 
              <name>MODE6</name>
2758 
              <description>Port n.6 mode bits</description>
2759 
              <bitOffset>24</bitOffset>
2760 
              <bitWidth>2</bitWidth>
2761 
            </field>
2762 
            <field>
2763 
              <name>CNF6</name>
2764 
              <description>Port n.6 configuration
2765 
              bits</description>
2766 
              <bitOffset>26</bitOffset>
2767 
              <bitWidth>2</bitWidth>
2768 
            </field>
2769 
            <field>
2770 
              <name>MODE7</name>
2771 
              <description>Port n.7 mode bits</description>
2772 
              <bitOffset>28</bitOffset>
2773 
              <bitWidth>2</bitWidth>
2774 
            </field>
2775 
            <field>
2776 
              <name>CNF7</name>
2777 
              <description>Port n.7 configuration
2778 
              bits</description>
2779 
              <bitOffset>30</bitOffset>
2780 
              <bitWidth>2</bitWidth>
2781 
            </field>
2782 
          </fields>
2783 
        </register>
2784 
        <register>
2785 
          <name>CRH</name>
2786 
          <displayName>CRH</displayName>
2787 
          <description>Port configuration register high
2788 
          (GPIOn_CRL)</description>
2789 
          <addressOffset>0x4</addressOffset>
2790 
          <size>0x20</size>
2791 
          <access>read-write</access>
2792 
          <resetValue>0x44444444</resetValue>
2793 
          <fields>
2794 
            <field>
2795 
              <name>MODE8</name>
2796 
              <description>Port n.8 mode bits</description>
2797 
              <bitOffset>0</bitOffset>
2798 
              <bitWidth>2</bitWidth>
2799 
            </field>
2800 
            <field>
2801 
              <name>CNF8</name>
2802 
              <description>Port n.8 configuration
2803 
              bits</description>
2804 
              <bitOffset>2</bitOffset>
2805 
              <bitWidth>2</bitWidth>
2806 
            </field>
2807 
            <field>
2808 
              <name>MODE9</name>
2809 
              <description>Port n.9 mode bits</description>
2810 
              <bitOffset>4</bitOffset>
2811 
              <bitWidth>2</bitWidth>
2812 
            </field>
2813 
            <field>
2814 
              <name>CNF9</name>
2815 
              <description>Port n.9 configuration
2816 
              bits</description>
2817 
              <bitOffset>6</bitOffset>
2818 
              <bitWidth>2</bitWidth>
2819 
            </field>
2820 
            <field>
2821 
              <name>MODE10</name>
2822 
              <description>Port n.10 mode bits</description>
2823 
              <bitOffset>8</bitOffset>
2824 
              <bitWidth>2</bitWidth>
2825 
            </field>
2826 
            <field>
2827 
              <name>CNF10</name>
2828 
              <description>Port n.10 configuration
2829 
              bits</description>
2830 
              <bitOffset>10</bitOffset>
2831 
              <bitWidth>2</bitWidth>
2832 
            </field>
2833 
            <field>
2834 
              <name>MODE11</name>
2835 
              <description>Port n.11 mode bits</description>
2836 
              <bitOffset>12</bitOffset>
2837 
              <bitWidth>2</bitWidth>
2838 
            </field>
2839 
            <field>
2840 
              <name>CNF11</name>
2841 
              <description>Port n.11 configuration
2842 
              bits</description>
2843 
              <bitOffset>14</bitOffset>
2844 
              <bitWidth>2</bitWidth>
2845 
            </field>
2846 
            <field>
2847 
              <name>MODE12</name>
2848 
              <description>Port n.12 mode bits</description>
2849 
              <bitOffset>16</bitOffset>
2850 
              <bitWidth>2</bitWidth>
2851 
            </field>
2852 
            <field>
2853 
              <name>CNF12</name>
2854 
              <description>Port n.12 configuration
2855 
              bits</description>
2856 
              <bitOffset>18</bitOffset>
2857 
              <bitWidth>2</bitWidth>
2858 
            </field>
2859 
            <field>
2860 
              <name>MODE13</name>
2861 
              <description>Port n.13 mode bits</description>
2862 
              <bitOffset>20</bitOffset>
2863 
              <bitWidth>2</bitWidth>
2864 
            </field>
2865 
            <field>
2866 
              <name>CNF13</name>
2867 
              <description>Port n.13 configuration
2868 
              bits</description>
2869 
              <bitOffset>22</bitOffset>
2870 
              <bitWidth>2</bitWidth>
2871 
            </field>
2872 
            <field>
2873 
              <name>MODE14</name>
2874 
              <description>Port n.14 mode bits</description>
2875 
              <bitOffset>24</bitOffset>
2876 
              <bitWidth>2</bitWidth>
2877 
            </field>
2878 
            <field>
2879 
              <name>CNF14</name>
2880 
              <description>Port n.14 configuration
2881 
              bits</description>
2882 
              <bitOffset>26</bitOffset>
2883 
              <bitWidth>2</bitWidth>
2884 
            </field>
2885 
            <field>
2886 
              <name>MODE15</name>
2887 
              <description>Port n.15 mode bits</description>
2888 
              <bitOffset>28</bitOffset>
2889 
              <bitWidth>2</bitWidth>
2890 
            </field>
2891 
            <field>
2892 
              <name>CNF15</name>
2893 
              <description>Port n.15 configuration
2894 
              bits</description>
2895 
              <bitOffset>30</bitOffset>
2896 
              <bitWidth>2</bitWidth>
2897 
            </field>
2898 
          </fields>
2899 
        </register>
2900 
        <register>
2901 
          <name>IDR</name>
2902 
          <displayName>IDR</displayName>
2903 
          <description>Port input data register
2904 
          (GPIOn_IDR)</description>
2905 
          <addressOffset>0x8</addressOffset>
2906 
          <size>0x20</size>
2907 
          <access>read-only</access>
2908 
          <resetValue>0x00000000</resetValue>
2909 
          <fields>
2910 
            <field>
2911 
              <name>IDR0</name>
2912 
              <description>Port input data</description>
2913 
              <bitOffset>0</bitOffset>
2914 
              <bitWidth>1</bitWidth>
2915 
            </field>
2916 
            <field>
2917 
              <name>IDR1</name>
2918 
              <description>Port input data</description>
2919 
              <bitOffset>1</bitOffset>
2920 
              <bitWidth>1</bitWidth>
2921 
            </field>
2922 
            <field>
2923 
              <name>IDR2</name>
2924 
              <description>Port input data</description>
2925 
              <bitOffset>2</bitOffset>
2926 
              <bitWidth>1</bitWidth>
2927 
            </field>
2928 
            <field>
2929 
              <name>IDR3</name>
2930 
              <description>Port input data</description>
2931 
              <bitOffset>3</bitOffset>
2932 
              <bitWidth>1</bitWidth>
2933 
            </field>
2934 
            <field>
2935 
              <name>IDR4</name>
2936 
              <description>Port input data</description>
2937 
              <bitOffset>4</bitOffset>
2938 
              <bitWidth>1</bitWidth>
2939 
            </field>
2940 
            <field>
2941 
              <name>IDR5</name>
2942 
              <description>Port input data</description>
2943 
              <bitOffset>5</bitOffset>
2944 
              <bitWidth>1</bitWidth>
2945 
            </field>
2946 
            <field>
2947 
              <name>IDR6</name>
2948 
              <description>Port input data</description>
2949 
              <bitOffset>6</bitOffset>
2950 
              <bitWidth>1</bitWidth>
2951 
            </field>
2952 
            <field>
2953 
              <name>IDR7</name>
2954 
              <description>Port input data</description>
2955 
              <bitOffset>7</bitOffset>
2956 
              <bitWidth>1</bitWidth>
2957 
            </field>
2958 
            <field>
2959 
              <name>IDR8</name>
2960 
              <description>Port input data</description>
2961 
              <bitOffset>8</bitOffset>
2962 
              <bitWidth>1</bitWidth>
2963 
            </field>
2964 
            <field>
2965 
              <name>IDR9</name>
2966 
              <description>Port input data</description>
2967 
              <bitOffset>9</bitOffset>
2968 
              <bitWidth>1</bitWidth>
2969 
            </field>
2970 
            <field>
2971 
              <name>IDR10</name>
2972 
              <description>Port input data</description>
2973 
              <bitOffset>10</bitOffset>
2974 
              <bitWidth>1</bitWidth>
2975 
            </field>
2976 
            <field>
2977 
              <name>IDR11</name>
2978 
              <description>Port input data</description>
2979 
              <bitOffset>11</bitOffset>
2980 
              <bitWidth>1</bitWidth>
2981 
            </field>
2982 
            <field>
2983 
              <name>IDR12</name>
2984 
              <description>Port input data</description>
2985 
              <bitOffset>12</bitOffset>
2986 
              <bitWidth>1</bitWidth>
2987 
            </field>
2988 
            <field>
2989 
              <name>IDR13</name>
2990 
              <description>Port input data</description>
2991 
              <bitOffset>13</bitOffset>
2992 
              <bitWidth>1</bitWidth>
2993 
            </field>
2994 
            <field>
2995 
              <name>IDR14</name>
2996 
              <description>Port input data</description>
2997 
              <bitOffset>14</bitOffset>
2998 
              <bitWidth>1</bitWidth>
2999 
            </field>
3000 
            <field>
3001 
              <name>IDR15</name>
3002 
              <description>Port input data</description>
3003 
              <bitOffset>15</bitOffset>
3004 
              <bitWidth>1</bitWidth>
3005 
            </field>
3006 
          </fields>
3007 
        </register>
3008 
        <register>
3009 
          <name>ODR</name>
3010 
          <displayName>ODR</displayName>
3011 
          <description>Port output data register
3012 
          (GPIOn_ODR)</description>
3013 
          <addressOffset>0xC</addressOffset>
3014 
          <size>0x20</size>
3015 
          <access>read-write</access>
3016 
          <resetValue>0x00000000</resetValue>
3017 
          <fields>
3018 
            <field>
3019 
              <name>ODR0</name>
3020 
              <description>Port output data</description>
3021 
              <bitOffset>0</bitOffset>
3022 
              <bitWidth>1</bitWidth>
3023 
            </field>
3024 
            <field>
3025 
              <name>ODR1</name>
3026 
              <description>Port output data</description>
3027 
              <bitOffset>1</bitOffset>
3028 
              <bitWidth>1</bitWidth>
3029 
            </field>
3030 
            <field>
3031 
              <name>ODR2</name>
3032 
              <description>Port output data</description>
3033 
              <bitOffset>2</bitOffset>
3034 
              <bitWidth>1</bitWidth>
3035 
            </field>
3036 
            <field>
3037 
              <name>ODR3</name>
3038 
              <description>Port output data</description>
3039 
              <bitOffset>3</bitOffset>
3040 
              <bitWidth>1</bitWidth>
3041 
            </field>
3042 
            <field>
3043 
              <name>ODR4</name>
3044 
              <description>Port output data</description>
3045 
              <bitOffset>4</bitOffset>
3046 
              <bitWidth>1</bitWidth>
3047 
            </field>
3048 
            <field>
3049 
              <name>ODR5</name>
3050 
              <description>Port output data</description>
3051 
              <bitOffset>5</bitOffset>
3052 
              <bitWidth>1</bitWidth>
3053 
            </field>
3054 
            <field>
3055 
              <name>ODR6</name>
3056 
              <description>Port output data</description>
3057 
              <bitOffset>6</bitOffset>
3058 
              <bitWidth>1</bitWidth>
3059 
            </field>
3060 
            <field>
3061 
              <name>ODR7</name>
3062 
              <description>Port output data</description>
3063 
              <bitOffset>7</bitOffset>
3064 
              <bitWidth>1</bitWidth>
3065 
            </field>
3066 
            <field>
3067 
              <name>ODR8</name>
3068 
              <description>Port output data</description>
3069 
              <bitOffset>8</bitOffset>
3070 
              <bitWidth>1</bitWidth>
3071 
            </field>
3072 
            <field>
3073 
              <name>ODR9</name>
3074 
              <description>Port output data</description>
3075 
              <bitOffset>9</bitOffset>
3076 
              <bitWidth>1</bitWidth>
3077 
            </field>
3078 
            <field>
3079 
              <name>ODR10</name>
3080 
              <description>Port output data</description>
3081 
              <bitOffset>10</bitOffset>
3082 
              <bitWidth>1</bitWidth>
3083 
            </field>
3084 
            <field>
3085 
              <name>ODR11</name>
3086 
              <description>Port output data</description>
3087 
              <bitOffset>11</bitOffset>
3088 
              <bitWidth>1</bitWidth>
3089 
            </field>
3090 
            <field>
3091 
              <name>ODR12</name>
3092 
              <description>Port output data</description>
3093 
              <bitOffset>12</bitOffset>
3094 
              <bitWidth>1</bitWidth>
3095 
            </field>
3096 
            <field>
3097 
              <name>ODR13</name>
3098 
              <description>Port output data</description>
3099 
              <bitOffset>13</bitOffset>
3100 
              <bitWidth>1</bitWidth>
3101 
            </field>
3102 
            <field>
3103 
              <name>ODR14</name>
3104 
              <description>Port output data</description>
3105 
              <bitOffset>14</bitOffset>
3106 
              <bitWidth>1</bitWidth>
3107 
            </field>
3108 
            <field>
3109 
              <name>ODR15</name>
3110 
              <description>Port output data</description>
3111 
              <bitOffset>15</bitOffset>
3112 
              <bitWidth>1</bitWidth>
3113 
            </field>
3114 
          </fields>
3115 
        </register>
3116 
        <register>
3117 
          <name>BSRR</name>
3118 
          <displayName>BSRR</displayName>
3119 
          <description>Port bit set/reset register
3120 
          (GPIOn_BSRR)</description>
3121 
          <addressOffset>0x10</addressOffset>
3122 
          <size>0x20</size>
3123 
          <access>write-only</access>
3124 
          <resetValue>0x00000000</resetValue>
3125 
          <fields>
3126 
            <field>
3127 
              <name>BS0</name>
3128 
              <description>Set bit 0</description>
3129 
              <bitOffset>0</bitOffset>
3130 
              <bitWidth>1</bitWidth>
3131 
            </field>
3132 
            <field>
3133 
              <name>BS1</name>
3134 
              <description>Set bit 1</description>
3135 
              <bitOffset>1</bitOffset>
3136 
              <bitWidth>1</bitWidth>
3137 
            </field>
3138 
            <field>
3139 
              <name>BS2</name>
3140 
              <description>Set bit 1</description>
3141 
              <bitOffset>2</bitOffset>
3142 
              <bitWidth>1</bitWidth>
3143 
            </field>
3144 
            <field>
3145 
              <name>BS3</name>
3146 
              <description>Set bit 3</description>
3147 
              <bitOffset>3</bitOffset>
3148 
              <bitWidth>1</bitWidth>
3149 
            </field>
3150 
            <field>
3151 
              <name>BS4</name>
3152 
              <description>Set bit 4</description>
3153 
              <bitOffset>4</bitOffset>
3154 
              <bitWidth>1</bitWidth>
3155 
            </field>
3156 
            <field>
3157 
              <name>BS5</name>
3158 
              <description>Set bit 5</description>
3159 
              <bitOffset>5</bitOffset>
3160 
              <bitWidth>1</bitWidth>
3161 
            </field>
3162 
            <field>
3163 
              <name>BS6</name>
3164 
              <description>Set bit 6</description>
3165 
              <bitOffset>6</bitOffset>
3166 
              <bitWidth>1</bitWidth>
3167 
            </field>
3168 
            <field>
3169 
              <name>BS7</name>
3170 
              <description>Set bit 7</description>
3171 
              <bitOffset>7</bitOffset>
3172 
              <bitWidth>1</bitWidth>
3173 
            </field>
3174 
            <field>
3175 
              <name>BS8</name>
3176 
              <description>Set bit 8</description>
3177 
              <bitOffset>8</bitOffset>
3178 
              <bitWidth>1</bitWidth>
3179 
            </field>
3180 
            <field>
3181 
              <name>BS9</name>
3182 
              <description>Set bit 9</description>
3183 
              <bitOffset>9</bitOffset>
3184 
              <bitWidth>1</bitWidth>
3185 
            </field>
3186 
            <field>
3187 
              <name>BS10</name>
3188 
              <description>Set bit 10</description>
3189 
              <bitOffset>10</bitOffset>
3190 
              <bitWidth>1</bitWidth>
3191 
            </field>
3192 
            <field>
3193 
              <name>BS11</name>
3194 
              <description>Set bit 11</description>
3195 
              <bitOffset>11</bitOffset>
3196 
              <bitWidth>1</bitWidth>
3197 
            </field>
3198 
            <field>
3199 
              <name>BS12</name>
3200 
              <description>Set bit 12</description>
3201 
              <bitOffset>12</bitOffset>
3202 
              <bitWidth>1</bitWidth>
3203 
            </field>
3204 
            <field>
3205 
              <name>BS13</name>
3206 
              <description>Set bit 13</description>
3207 
              <bitOffset>13</bitOffset>
3208 
              <bitWidth>1</bitWidth>
3209 
            </field>
3210 
            <field>
3211 
              <name>BS14</name>
3212 
              <description>Set bit 14</description>
3213 
              <bitOffset>14</bitOffset>
3214 
              <bitWidth>1</bitWidth>
3215 
            </field>
3216 
            <field>
3217 
              <name>BS15</name>
3218 
              <description>Set bit 15</description>
3219 
              <bitOffset>15</bitOffset>
3220 
              <bitWidth>1</bitWidth>
3221 
            </field>
3222 
            <field>
3223 
              <name>BR0</name>
3224 
              <description>Reset bit 0</description>
3225 
              <bitOffset>16</bitOffset>
3226 
              <bitWidth>1</bitWidth>
3227 
            </field>
3228 
            <field>
3229 
              <name>BR1</name>
3230 
              <description>Reset bit 1</description>
3231 
              <bitOffset>17</bitOffset>
3232 
              <bitWidth>1</bitWidth>
3233 
            </field>
3234 
            <field>
3235 
              <name>BR2</name>
3236 
              <description>Reset bit 2</description>
3237 
              <bitOffset>18</bitOffset>
3238 
              <bitWidth>1</bitWidth>
3239 
            </field>
3240 
            <field>
3241 
              <name>BR3</name>
3242 
              <description>Reset bit 3</description>
3243 
              <bitOffset>19</bitOffset>
3244 
              <bitWidth>1</bitWidth>
3245 
            </field>
3246 
            <field>
3247 
              <name>BR4</name>
3248 
              <description>Reset bit 4</description>
3249 
              <bitOffset>20</bitOffset>
3250 
              <bitWidth>1</bitWidth>
3251 
            </field>
3252 
            <field>
3253 
              <name>BR5</name>
3254 
              <description>Reset bit 5</description>
3255 
              <bitOffset>21</bitOffset>
3256 
              <bitWidth>1</bitWidth>
3257 
            </field>
3258 
            <field>
3259 
              <name>BR6</name>
3260 
              <description>Reset bit 6</description>
3261 
              <bitOffset>22</bitOffset>
3262 
              <bitWidth>1</bitWidth>
3263 
            </field>
3264 
            <field>
3265 
              <name>BR7</name>
3266 
              <description>Reset bit 7</description>
3267 
              <bitOffset>23</bitOffset>
3268 
              <bitWidth>1</bitWidth>
3269 
            </field>
3270 
            <field>
3271 
              <name>BR8</name>
3272 
              <description>Reset bit 8</description>
3273 
              <bitOffset>24</bitOffset>
3274 
              <bitWidth>1</bitWidth>
3275 
            </field>
3276 
            <field>
3277 
              <name>BR9</name>
3278 
              <description>Reset bit 9</description>
3279 
              <bitOffset>25</bitOffset>
3280 
              <bitWidth>1</bitWidth>
3281 
            </field>
3282 
            <field>
3283 
              <name>BR10</name>
3284 
              <description>Reset bit 10</description>
3285 
              <bitOffset>26</bitOffset>
3286 
              <bitWidth>1</bitWidth>
3287 
            </field>
3288 
            <field>
3289 
              <name>BR11</name>
3290 
              <description>Reset bit 11</description>
3291 
              <bitOffset>27</bitOffset>
3292 
              <bitWidth>1</bitWidth>
3293 
            </field>
3294 
            <field>
3295 
              <name>BR12</name>
3296 
              <description>Reset bit 12</description>
3297 
              <bitOffset>28</bitOffset>
3298 
              <bitWidth>1</bitWidth>
3299 
            </field>
3300 
            <field>
3301 
              <name>BR13</name>
3302 
              <description>Reset bit 13</description>
3303 
              <bitOffset>29</bitOffset>
3304 
              <bitWidth>1</bitWidth>
3305 
            </field>
3306 
            <field>
3307 
              <name>BR14</name>
3308 
              <description>Reset bit 14</description>
3309 
              <bitOffset>30</bitOffset>
3310 
              <bitWidth>1</bitWidth>
3311 
            </field>
3312 
            <field>
3313 
              <name>BR15</name>
3314 
              <description>Reset bit 15</description>
3315 
              <bitOffset>31</bitOffset>
3316 
              <bitWidth>1</bitWidth>
3317 
            </field>
3318 
          </fields>
3319 
        </register>
3320 
        <register>
3321 
          <name>BRR</name>
3322 
          <displayName>BRR</displayName>
3323 
          <description>Port bit reset register
3324 
          (GPIOn_BRR)</description>
3325 
          <addressOffset>0x14</addressOffset>
3326 
          <size>0x20</size>
3327 
          <access>write-only</access>
3328 
          <resetValue>0x00000000</resetValue>
3329 
          <fields>
3330 
            <field>
3331 
              <name>BR0</name>
3332 
              <description>Reset bit 0</description>
3333 
              <bitOffset>0</bitOffset>
3334 
              <bitWidth>1</bitWidth>
3335 
            </field>
3336 
            <field>
3337 
              <name>BR1</name>
3338 
              <description>Reset bit 1</description>
3339 
              <bitOffset>1</bitOffset>
3340 
              <bitWidth>1</bitWidth>
3341 
            </field>
3342 
            <field>
3343 
              <name>BR2</name>
3344 
              <description>Reset bit 1</description>
3345 
              <bitOffset>2</bitOffset>
3346 
              <bitWidth>1</bitWidth>
3347 
            </field>
3348 
            <field>
3349 
              <name>BR3</name>
3350 
              <description>Reset bit 3</description>
3351 
              <bitOffset>3</bitOffset>
3352 
              <bitWidth>1</bitWidth>
3353 
            </field>
3354 
            <field>
3355 
              <name>BR4</name>
3356 
              <description>Reset bit 4</description>
3357 
              <bitOffset>4</bitOffset>
3358 
              <bitWidth>1</bitWidth>
3359 
            </field>
3360 
            <field>
3361 
              <name>BR5</name>
3362 
              <description>Reset bit 5</description>
3363 
              <bitOffset>5</bitOffset>
3364 
              <bitWidth>1</bitWidth>
3365 
            </field>
3366 
            <field>
3367 
              <name>BR6</name>
3368 
              <description>Reset bit 6</description>
3369 
              <bitOffset>6</bitOffset>
3370 
              <bitWidth>1</bitWidth>
3371 
            </field>
3372 
            <field>
3373 
              <name>BR7</name>
3374 
              <description>Reset bit 7</description>
3375 
              <bitOffset>7</bitOffset>
3376 
              <bitWidth>1</bitWidth>
3377 
            </field>
3378 
            <field>
3379 
              <name>BR8</name>
3380 
              <description>Reset bit 8</description>
3381 
              <bitOffset>8</bitOffset>
3382 
              <bitWidth>1</bitWidth>
3383 
            </field>
3384 
            <field>
3385 
              <name>BR9</name>
3386 
              <description>Reset bit 9</description>
3387 
              <bitOffset>9</bitOffset>
3388 
              <bitWidth>1</bitWidth>
3389 
            </field>
3390 
            <field>
3391 
              <name>BR10</name>
3392 
              <description>Reset bit 10</description>
3393 
              <bitOffset>10</bitOffset>
3394 
              <bitWidth>1</bitWidth>
3395 
            </field>
3396 
            <field>
3397 
              <name>BR11</name>
3398 
              <description>Reset bit 11</description>
3399 
              <bitOffset>11</bitOffset>
3400 
              <bitWidth>1</bitWidth>
3401 
            </field>
3402 
            <field>
3403 
              <name>BR12</name>
3404 
              <description>Reset bit 12</description>
3405 
              <bitOffset>12</bitOffset>
3406 
              <bitWidth>1</bitWidth>
3407 
            </field>
3408 
            <field>
3409 
              <name>BR13</name>
3410 
              <description>Reset bit 13</description>
3411 
              <bitOffset>13</bitOffset>
3412 
              <bitWidth>1</bitWidth>
3413 
            </field>
3414 
            <field>
3415 
              <name>BR14</name>
3416 
              <description>Reset bit 14</description>
3417 
              <bitOffset>14</bitOffset>
3418 
              <bitWidth>1</bitWidth>
3419 
            </field>
3420 
            <field>
3421 
              <name>BR15</name>
3422 
              <description>Reset bit 15</description>
3423 
              <bitOffset>15</bitOffset>
3424 
              <bitWidth>1</bitWidth>
3425 
            </field>
3426 
          </fields>
3427 
        </register>
3428 
        <register>
3429 
          <name>LCKR</name>
3430 
          <displayName>LCKR</displayName>
3431 
          <description>Port configuration lock
3432 
          register</description>
3433 
          <addressOffset>0x18</addressOffset>
3434 
          <size>0x20</size>
3435 
          <access>read-write</access>
3436 
          <resetValue>0x00000000</resetValue>
3437 
          <fields>
3438 
            <field>
3439 
              <name>LCK0</name>
3440 
              <description>Port A Lock bit 0</description>
3441 
              <bitOffset>0</bitOffset>
3442 
              <bitWidth>1</bitWidth>
3443 
            </field>
3444 
            <field>
3445 
              <name>LCK1</name>
3446 
              <description>Port A Lock bit 1</description>
3447 
              <bitOffset>1</bitOffset>
3448 
              <bitWidth>1</bitWidth>
3449 
            </field>
3450 
            <field>
3451 
              <name>LCK2</name>
3452 
              <description>Port A Lock bit 2</description>
3453 
              <bitOffset>2</bitOffset>
3454 
              <bitWidth>1</bitWidth>
3455 
            </field>
3456 
            <field>
3457 
              <name>LCK3</name>
3458 
              <description>Port A Lock bit 3</description>
3459 
              <bitOffset>3</bitOffset>
3460 
              <bitWidth>1</bitWidth>
3461 
            </field>
3462 
            <field>
3463 
              <name>LCK4</name>
3464 
              <description>Port A Lock bit 4</description>
3465 
              <bitOffset>4</bitOffset>
3466 
              <bitWidth>1</bitWidth>
3467 
            </field>
3468 
            <field>
3469 
              <name>LCK5</name>
3470 
              <description>Port A Lock bit 5</description>
3471 
              <bitOffset>5</bitOffset>
3472 
              <bitWidth>1</bitWidth>
3473 
            </field>
3474 
            <field>
3475 
              <name>LCK6</name>
3476 
              <description>Port A Lock bit 6</description>
3477 
              <bitOffset>6</bitOffset>
3478 
              <bitWidth>1</bitWidth>
3479 
            </field>
3480 
            <field>
3481 
              <name>LCK7</name>
3482 
              <description>Port A Lock bit 7</description>
3483 
              <bitOffset>7</bitOffset>
3484 
              <bitWidth>1</bitWidth>
3485 
            </field>
3486 
            <field>
3487 
              <name>LCK8</name>
3488 
              <description>Port A Lock bit 8</description>
3489 
              <bitOffset>8</bitOffset>
3490 
              <bitWidth>1</bitWidth>
3491 
            </field>
3492 
            <field>
3493 
              <name>LCK9</name>
3494 
              <description>Port A Lock bit 9</description>
3495 
              <bitOffset>9</bitOffset>
3496 
              <bitWidth>1</bitWidth>
3497 
            </field>
3498 
            <field>
3499 
              <name>LCK10</name>
3500 
              <description>Port A Lock bit 10</description>
3501 
              <bitOffset>10</bitOffset>
3502 
              <bitWidth>1</bitWidth>
3503 
            </field>
3504 
            <field>
3505 
              <name>LCK11</name>
3506 
              <description>Port A Lock bit 11</description>
3507 
              <bitOffset>11</bitOffset>
3508 
              <bitWidth>1</bitWidth>
3509 
            </field>
3510 
            <field>
3511 
              <name>LCK12</name>
3512 
              <description>Port A Lock bit 12</description>
3513 
              <bitOffset>12</bitOffset>
3514 
              <bitWidth>1</bitWidth>
3515 
            </field>
3516 
            <field>
3517 
              <name>LCK13</name>
3518 
              <description>Port A Lock bit 13</description>
3519 
              <bitOffset>13</bitOffset>
3520 
              <bitWidth>1</bitWidth>
3521 
            </field>
3522 
            <field>
3523 
              <name>LCK14</name>
3524 
              <description>Port A Lock bit 14</description>
3525 
              <bitOffset>14</bitOffset>
3526 
              <bitWidth>1</bitWidth>
3527 
            </field>
3528 
            <field>
3529 
              <name>LCK15</name>
3530 
              <description>Port A Lock bit 15</description>
3531 
              <bitOffset>15</bitOffset>
3532 
              <bitWidth>1</bitWidth>
3533 
            </field>
3534 
            <field>
3535 
              <name>LCKK</name>
3536 
              <description>Lock key</description>
3537 
              <bitOffset>16</bitOffset>
3538 
              <bitWidth>1</bitWidth>
3539 
            </field>
3540 
          </fields>
3541 
        </register>
3542 
      </registers>
3543 
    </peripheral>
3544 
    <peripheral derivedFrom="GPIOA">
3545 
      <name>GPIOB</name>
3546 
      <baseAddress>0x40010C00</baseAddress>
3547 
    </peripheral>
3548 
    <peripheral derivedFrom="GPIOA">
3549 
      <name>GPIOC</name>
3550 
      <baseAddress>0x40011000</baseAddress>
3551 
    </peripheral>
3552 
    <peripheral derivedFrom="GPIOA">
3553 
      <name>GPIOD</name>
3554 
      <baseAddress>0x40011400</baseAddress>
3555 
    </peripheral>
3556 
    <peripheral derivedFrom="GPIOA">
3557 
      <name>GPIOE</name>
3558 
      <baseAddress>0x40011800</baseAddress>
3559 
    </peripheral>
3560 
    <peripheral derivedFrom="GPIOA">
3561 
      <name>GPIOF</name>
3562 
      <baseAddress>0x40011C00</baseAddress>
3563 
    </peripheral>
3564 
    <peripheral derivedFrom="GPIOA">
3565 
      <name>GPIOG</name>
3566 
      <baseAddress>0x40012000</baseAddress>
3567 
    </peripheral>
3568 
    <peripheral>
3569 
      <name>AFIO</name>
3570 
      <description>Alternate function I/O</description>
3571 
      <groupName>AFIO</groupName>
3572 
      <baseAddress>0x40010000</baseAddress>
3573 
      <addressBlock>
3574 
        <offset>0x0</offset>
3575 
        <size>0x400</size>
3576 
        <usage>registers</usage>
3577 
      </addressBlock>
3578 
      <registers>
3579 
        <register>
3580 
          <name>EVCR</name>
3581 
          <displayName>EVCR</displayName>
3582 
          <description>Event Control Register
3583 
          (AFIO_EVCR)</description>
3584 
          <addressOffset>0x0</addressOffset>
3585 
          <size>0x20</size>
3586 
          <access>read-write</access>
3587 
          <resetValue>0x00000000</resetValue>
3588 
          <fields>
3589 
            <field>
3590 
              <name>PIN</name>
3591 
              <description>Pin selection</description>
3592 
              <bitOffset>0</bitOffset>
3593 
              <bitWidth>4</bitWidth>
3594 
            </field>
3595 
            <field>
3596 
              <name>PORT</name>
3597 
              <description>Port selection</description>
3598 
              <bitOffset>4</bitOffset>
3599 
              <bitWidth>3</bitWidth>
3600 
            </field>
3601 
            <field>
3602 
              <name>EVOE</name>
3603 
              <description>Event Output Enable</description>
3604 
              <bitOffset>7</bitOffset>
3605 
              <bitWidth>1</bitWidth>
3606 
            </field>
3607 
          </fields>
3608 
        </register>
3609 
        <register>
3610 
          <name>MAPR</name>
3611 
          <displayName>MAPR</displayName>
3612 
          <description>AF remap and debug I/O configuration
3613 
          register (AFIO_MAPR)</description>
3614 
          <addressOffset>0x4</addressOffset>
3615 
          <size>0x20</size>
3616 
          <resetValue>0x00000000</resetValue>
3617 
          <fields>
3618 
            <field>
3619 
              <name>SPI1_REMAP</name>
3620 
              <description>SPI1 remapping</description>
3621 
              <bitOffset>0</bitOffset>
3622 
              <bitWidth>1</bitWidth>
3623 
              <access>read-write</access>
3624 
            </field>
3625 
            <field>
3626 
              <name>I2C1_REMAP</name>
3627 
              <description>I2C1 remapping</description>
3628 
              <bitOffset>1</bitOffset>
3629 
              <bitWidth>1</bitWidth>
3630 
              <access>read-write</access>
3631 
            </field>
3632 
            <field>
3633 
              <name>USART1_REMAP</name>
3634 
              <description>USART1 remapping</description>
3635 
              <bitOffset>2</bitOffset>
3636 
              <bitWidth>1</bitWidth>
3637 
              <access>read-write</access>
3638 
            </field>
3639 
            <field>
3640 
              <name>USART2_REMAP</name>
3641 
              <description>USART2 remapping</description>
3642 
              <bitOffset>3</bitOffset>
3643 
              <bitWidth>1</bitWidth>
3644 
              <access>read-write</access>
3645 
            </field>
3646 
            <field>
3647 
              <name>USART3_REMAP</name>
3648 
              <description>USART3 remapping</description>
3649 
              <bitOffset>4</bitOffset>
3650 
              <bitWidth>2</bitWidth>
3651 
              <access>read-write</access>
3652 
            </field>
3653 
            <field>
3654 
              <name>TIM1_REMAP</name>
3655 
              <description>TIM1 remapping</description>
3656 
              <bitOffset>6</bitOffset>
3657 
              <bitWidth>2</bitWidth>
3658 
              <access>read-write</access>
3659 
            </field>
3660 
            <field>
3661 
              <name>TIM2_REMAP</name>
3662 
              <description>TIM2 remapping</description>
3663 
              <bitOffset>8</bitOffset>
3664 
              <bitWidth>2</bitWidth>
3665 
              <access>read-write</access>
3666 
            </field>
3667 
            <field>
3668 
              <name>TIM3_REMAP</name>
3669 
              <description>TIM3 remapping</description>
3670 
              <bitOffset>10</bitOffset>
3671 
              <bitWidth>2</bitWidth>
3672 
              <access>read-write</access>
3673 
            </field>
3674 
            <field>
3675 
              <name>TIM4_REMAP</name>
3676 
              <description>TIM4 remapping</description>
3677 
              <bitOffset>12</bitOffset>
3678 
              <bitWidth>1</bitWidth>
3679 
              <access>read-write</access>
3680 
            </field>
3681 
            <field>
3682 
              <name>CAN_REMAP</name>
3683 
              <description>CAN1 remapping</description>
3684 
              <bitOffset>13</bitOffset>
3685 
              <bitWidth>2</bitWidth>
3686 
              <access>read-write</access>
3687 
            </field>
3688 
            <field>
3689 
              <name>PD01_REMAP</name>
3690 
              <description>Port D0/Port D1 mapping on
3691 
              OSCIN/OSCOUT</description>
3692 
              <bitOffset>15</bitOffset>
3693 
              <bitWidth>1</bitWidth>
3694 
              <access>read-write</access>
3695 
            </field>
3696 
            <field>
3697 
              <name>TIM5CH4_IREMAP</name>
3698 
              <description>Set and cleared by
3699 
              software</description>
3700 
              <bitOffset>16</bitOffset>
3701 
              <bitWidth>1</bitWidth>
3702 
              <access>read-write</access>
3703 
            </field>
3704 
            <field>
3705 
              <name>ADC1_ETRGINJ_REMAP</name>
3706 
              <description>ADC 1 External trigger injected
3707 
              conversion remapping</description>
3708 
              <bitOffset>17</bitOffset>
3709 
              <bitWidth>1</bitWidth>
3710 
              <access>read-write</access>
3711 
            </field>
3712 
            <field>
3713 
              <name>ADC1_ETRGREG_REMAP</name>
3714 
              <description>ADC 1 external trigger regular
3715 
              conversion remapping</description>
3716 
              <bitOffset>18</bitOffset>
3717 
              <bitWidth>1</bitWidth>
3718 
              <access>read-write</access>
3719 
            </field>
3720 
            <field>
3721 
              <name>ADC2_ETRGINJ_REMAP</name>
3722 
              <description>ADC 2 external trigger injected
3723 
              conversion remapping</description>
3724 
              <bitOffset>19</bitOffset>
3725 
              <bitWidth>1</bitWidth>
3726 
              <access>read-write</access>
3727 
            </field>
3728 
            <field>
3729 
              <name>ADC2_ETRGREG_REMAP</name>
3730 
              <description>ADC 2 external trigger regular
3731 
              conversion remapping</description>
3732 
              <bitOffset>20</bitOffset>
3733 
              <bitWidth>1</bitWidth>
3734 
              <access>read-write</access>
3735 
            </field>
3736 
            <field>
3737 
              <name>SWJ_CFG</name>
3738 
              <description>Serial wire JTAG
3739 
              configuration</description>
3740 
              <bitOffset>24</bitOffset>
3741 
              <bitWidth>3</bitWidth>
3742 
              <access>write-only</access>
3743 
            </field>
3744 
          </fields>
3745 
        </register>
3746 
        <register>
3747 
          <name>EXTICR1</name>
3748 
          <displayName>EXTICR1</displayName>
3749 
          <description>External interrupt configuration register 1
3750 
          (AFIO_EXTICR1)</description>
3751 
          <addressOffset>0x8</addressOffset>
3752 
          <size>0x20</size>
3753 
          <access>read-write</access>
3754 
          <resetValue>0x00000000</resetValue>
3755 
          <fields>
3756 
            <field>
3757 
              <name>EXTI0</name>
3758 
              <description>EXTI0 configuration</description>
3759 
              <bitOffset>0</bitOffset>
3760 
              <bitWidth>4</bitWidth>
3761 
            </field>
3762 
            <field>
3763 
              <name>EXTI1</name>
3764 
              <description>EXTI1 configuration</description>
3765 
              <bitOffset>4</bitOffset>
3766 
              <bitWidth>4</bitWidth>
3767 
            </field>
3768 
            <field>
3769 
              <name>EXTI2</name>
3770 
              <description>EXTI2 configuration</description>
3771 
              <bitOffset>8</bitOffset>
3772 
              <bitWidth>4</bitWidth>
3773 
            </field>
3774 
            <field>
3775 
              <name>EXTI3</name>
3776 
              <description>EXTI3 configuration</description>
3777 
              <bitOffset>12</bitOffset>
3778 
              <bitWidth>4</bitWidth>
3779 
            </field>
3780 
          </fields>
3781 
        </register>
3782 
        <register>
3783 
          <name>EXTICR2</name>
3784 
          <displayName>EXTICR2</displayName>
3785 
          <description>External interrupt configuration register 2
3786 
          (AFIO_EXTICR2)</description>
3787 
          <addressOffset>0xC</addressOffset>
3788 
          <size>0x20</size>
3789 
          <access>read-write</access>
3790 
          <resetValue>0x00000000</resetValue>
3791 
          <fields>
3792 
            <field>
3793 
              <name>EXTI4</name>
3794 
              <description>EXTI4 configuration</description>
3795 
              <bitOffset>0</bitOffset>
3796 
              <bitWidth>4</bitWidth>
3797 
            </field>
3798 
            <field>
3799 
              <name>EXTI5</name>
3800 
              <description>EXTI5 configuration</description>
3801 
              <bitOffset>4</bitOffset>
3802 
              <bitWidth>4</bitWidth>
3803 
            </field>
3804 
            <field>
3805 
              <name>EXTI6</name>
3806 
              <description>EXTI6 configuration</description>
3807 
              <bitOffset>8</bitOffset>
3808 
              <bitWidth>4</bitWidth>
3809 
            </field>
3810 
            <field>
3811 
              <name>EXTI7</name>
3812 
              <description>EXTI7 configuration</description>
3813 
              <bitOffset>12</bitOffset>
3814 
              <bitWidth>4</bitWidth>
3815 
            </field>
3816 
          </fields>
3817 
        </register>
3818 
        <register>
3819 
          <name>EXTICR3</name>
3820 
          <displayName>EXTICR3</displayName>
3821 
          <description>External interrupt configuration register 3
3822 
          (AFIO_EXTICR3)</description>
3823 
          <addressOffset>0x10</addressOffset>
3824 
          <size>0x20</size>
3825 
          <access>read-write</access>
3826 
          <resetValue>0x00000000</resetValue>
3827 
          <fields>
3828 
            <field>
3829 
              <name>EXTI8</name>
3830 
              <description>EXTI8 configuration</description>
3831 
              <bitOffset>0</bitOffset>
3832 
              <bitWidth>4</bitWidth>
3833 
            </field>
3834 
            <field>
3835 
              <name>EXTI9</name>
3836 
              <description>EXTI9 configuration</description>
3837 
              <bitOffset>4</bitOffset>
3838 
              <bitWidth>4</bitWidth>
3839 
            </field>
3840 
            <field>
3841 
              <name>EXTI10</name>
3842 
              <description>EXTI10 configuration</description>
3843 
              <bitOffset>8</bitOffset>
3844 
              <bitWidth>4</bitWidth>
3845 
            </field>
3846 
            <field>
3847 
              <name>EXTI11</name>
3848 
              <description>EXTI11 configuration</description>
3849 
              <bitOffset>12</bitOffset>
3850 
              <bitWidth>4</bitWidth>
3851 
            </field>
3852 
          </fields>
3853 
        </register>
3854 
        <register>
3855 
          <name>EXTICR4</name>
3856 
          <displayName>EXTICR4</displayName>
3857 
          <description>External interrupt configuration register 4
3858 
          (AFIO_EXTICR4)</description>
3859 
          <addressOffset>0x14</addressOffset>
3860 
          <size>0x20</size>
3861 
          <access>read-write</access>
3862 
          <resetValue>0x00000000</resetValue>
3863 
          <fields>
3864 
            <field>
3865 
              <name>EXTI12</name>
3866 
              <description>EXTI12 configuration</description>
3867 
              <bitOffset>0</bitOffset>
3868 
              <bitWidth>4</bitWidth>
3869 
            </field>
3870 
            <field>
3871 
              <name>EXTI13</name>
3872 
              <description>EXTI13 configuration</description>
3873 
              <bitOffset>4</bitOffset>
3874 
              <bitWidth>4</bitWidth>
3875 
            </field>
3876 
            <field>
3877 
              <name>EXTI14</name>
3878 
              <description>EXTI14 configuration</description>
3879 
              <bitOffset>8</bitOffset>
3880 
              <bitWidth>4</bitWidth>
3881 
            </field>
3882 
            <field>
3883 
              <name>EXTI15</name>
3884 
              <description>EXTI15 configuration</description>
3885 
              <bitOffset>12</bitOffset>
3886 
              <bitWidth>4</bitWidth>
3887 
            </field>
3888 
          </fields>
3889 
        </register>
3890 
        <register>
3891 
          <name>MAPR2</name>
3892 
          <displayName>MAPR2</displayName>
3893 
          <description>AF remap and debug I/O configuration
3894 
          register</description>
3895 
          <addressOffset>0x1C</addressOffset>
3896 
          <size>0x20</size>
3897 
          <access>read-write</access>
3898 
          <resetValue>0x00000000</resetValue>
3899 
          <fields>
3900 
            <field>
3901 
              <name>TIM9_REMAP</name>
3902 
              <description>TIM9 remapping</description>
3903 
              <bitOffset>5</bitOffset>
3904 
              <bitWidth>1</bitWidth>
3905 
            </field>
3906 
            <field>
3907 
              <name>TIM10_REMAP</name>
3908 
              <description>TIM10 remapping</description>
3909 
              <bitOffset>6</bitOffset>
3910 
              <bitWidth>1</bitWidth>
3911 
            </field>
3912 
            <field>
3913 
              <name>TIM11_REMAP</name>
3914 
              <description>TIM11 remapping</description>
3915 
              <bitOffset>7</bitOffset>
3916 
              <bitWidth>1</bitWidth>
3917 
            </field>
3918 
            <field>
3919 
              <name>TIM13_REMAP</name>
3920 
              <description>TIM13 remapping</description>
3921 
              <bitOffset>8</bitOffset>
3922 
              <bitWidth>1</bitWidth>
3923 
            </field>
3924 
            <field>
3925 
              <name>TIM14_REMAP</name>
3926 
              <description>TIM14 remapping</description>
3927 
              <bitOffset>9</bitOffset>
3928 
              <bitWidth>1</bitWidth>
3929 
            </field>
3930 
            <field>
3931 
              <name>FSMC_NADV</name>
3932 
              <description>NADV connect/disconnect</description>
3933 
              <bitOffset>10</bitOffset>
3934 
              <bitWidth>1</bitWidth>
3935 
            </field>
3936 
          </fields>
3937 
        </register>
3938 
      </registers>
3939 
    </peripheral>
3940 
    <peripheral>
3941 
      <name>EXTI</name>
3942 
      <description>EXTI</description>
3943 
      <groupName>EXTI</groupName>
3944 
      <baseAddress>0x40010400</baseAddress>
3945 
      <addressBlock>
3946 
        <offset>0x0</offset>
3947 
        <size>0x400</size>
3948 
        <usage>registers</usage>
3949 
      </addressBlock>
3950 
      <interrupt>
3951 
        <name>TAMPER</name>
3952 
        <description>Tamper interrupt</description>
3953 
        <value>2</value>
3954 
      </interrupt>
3955 
      <interrupt>
3956 
        <name>EXTI0</name>
3957 
        <description>EXTI Line0 interrupt</description>
3958 
        <value>6</value>
3959 
      </interrupt>
3960 
      <interrupt>
3961 
        <name>EXTI1</name>
3962 
        <description>EXTI Line1 interrupt</description>
3963 
        <value>7</value>
3964 
      </interrupt>
3965 
      <interrupt>
3966 
        <name>EXTI2</name>
3967 
        <description>EXTI Line2 interrupt</description>
3968 
        <value>8</value>
3969 
      </interrupt>
3970 
      <interrupt>
3971 
        <name>EXTI3</name>
3972 
        <description>EXTI Line3 interrupt</description>
3973 
        <value>9</value>
3974 
      </interrupt>
3975 
      <interrupt>
3976 
        <name>EXTI4</name>
3977 
        <description>EXTI Line4 interrupt</description>
3978 
        <value>10</value>
3979 
      </interrupt>
3980 
      <interrupt>
3981 
        <name>EXTI9_5</name>
3982 
        <description>EXTI Line[9:5] interrupts</description>
3983 
        <value>23</value>
3984 
      </interrupt>
3985 
      <interrupt>
3986 
        <name>EXTI15_10</name>
3987 
        <description>EXTI Line[15:10] interrupts</description>
3988 
        <value>40</value>
3989 
      </interrupt>
3990 
      <registers>
3991 
        <register>
3992 
          <name>IMR</name>
3993 
          <displayName>IMR</displayName>
3994 
          <description>Interrupt mask register
3995 
          (EXTI_IMR)</description>
3996 
          <addressOffset>0x0</addressOffset>
3997 
          <size>0x20</size>
3998 
          <access>read-write</access>
3999 
          <resetValue>0x00000000</resetValue>
4000 
          <fields>
4001 
            <field>
4002 
              <name>MR0</name>
4003 
              <description>Interrupt Mask on line 0</description>
4004 
              <bitOffset>0</bitOffset>
4005 
              <bitWidth>1</bitWidth>
4006 
            </field>
4007 
            <field>
4008 
              <name>MR1</name>
4009 
              <description>Interrupt Mask on line 1</description>
4010 
              <bitOffset>1</bitOffset>
4011 
              <bitWidth>1</bitWidth>
4012 
            </field>
4013 
            <field>
4014 
              <name>MR2</name>
4015 
              <description>Interrupt Mask on line 2</description>
4016 
              <bitOffset>2</bitOffset>
4017 
              <bitWidth>1</bitWidth>
4018 
            </field>
4019 
            <field>
4020 
              <name>MR3</name>
4021 
              <description>Interrupt Mask on line 3</description>
4022 
              <bitOffset>3</bitOffset>
4023 
              <bitWidth>1</bitWidth>
4024 
            </field>
4025 
            <field>
4026 
              <name>MR4</name>
4027 
              <description>Interrupt Mask on line 4</description>
4028 
              <bitOffset>4</bitOffset>
4029 
              <bitWidth>1</bitWidth>
4030 
            </field>
4031 
            <field>
4032 
              <name>MR5</name>
4033 
              <description>Interrupt Mask on line 5</description>
4034 
              <bitOffset>5</bitOffset>
4035 
              <bitWidth>1</bitWidth>
4036 
            </field>
4037 
            <field>
4038 
              <name>MR6</name>
4039 
              <description>Interrupt Mask on line 6</description>
4040 
              <bitOffset>6</bitOffset>
4041 
              <bitWidth>1</bitWidth>
4042 
            </field>
4043 
            <field>
4044 
              <name>MR7</name>
4045 
              <description>Interrupt Mask on line 7</description>
4046 
              <bitOffset>7</bitOffset>
4047 
              <bitWidth>1</bitWidth>
4048 
            </field>
4049 
            <field>
4050 
              <name>MR8</name>
4051 
              <description>Interrupt Mask on line 8</description>
4052 
              <bitOffset>8</bitOffset>
4053 
              <bitWidth>1</bitWidth>
4054 
            </field>
4055 
            <field>
4056 
              <name>MR9</name>
4057 
              <description>Interrupt Mask on line 9</description>
4058 
              <bitOffset>9</bitOffset>
4059 
              <bitWidth>1</bitWidth>
4060 
            </field>
4061 
            <field>
4062 
              <name>MR10</name>
4063 
              <description>Interrupt Mask on line 10</description>
4064 
              <bitOffset>10</bitOffset>
4065 
              <bitWidth>1</bitWidth>
4066 
            </field>
4067 
            <field>
4068 
              <name>MR11</name>
4069 
              <description>Interrupt Mask on line 11</description>
4070 
              <bitOffset>11</bitOffset>
4071 
              <bitWidth>1</bitWidth>
4072 
            </field>
4073 
            <field>
4074 
              <name>MR12</name>
4075 
              <description>Interrupt Mask on line 12</description>
4076 
              <bitOffset>12</bitOffset>
4077 
              <bitWidth>1</bitWidth>
4078 
            </field>
4079 
            <field>
4080 
              <name>MR13</name>
4081 
              <description>Interrupt Mask on line 13</description>
4082 
              <bitOffset>13</bitOffset>
4083 
              <bitWidth>1</bitWidth>
4084 
            </field>
4085 
            <field>
4086 
              <name>MR14</name>
4087 
              <description>Interrupt Mask on line 14</description>
4088 
              <bitOffset>14</bitOffset>
4089 
              <bitWidth>1</bitWidth>
4090 
            </field>
4091 
            <field>
4092 
              <name>MR15</name>
4093 
              <description>Interrupt Mask on line 15</description>
4094 
              <bitOffset>15</bitOffset>
4095 
              <bitWidth>1</bitWidth>
4096 
            </field>
4097 
            <field>
4098 
              <name>MR16</name>
4099 
              <description>Interrupt Mask on line 16</description>
4100 
              <bitOffset>16</bitOffset>
4101 
              <bitWidth>1</bitWidth>
4102 
            </field>
4103 
            <field>
4104 
              <name>MR17</name>
4105 
              <description>Interrupt Mask on line 17</description>
4106 
              <bitOffset>17</bitOffset>
4107 
              <bitWidth>1</bitWidth>
4108 
            </field>
4109 
            <field>
4110 
              <name>MR18</name>
4111 
              <description>Interrupt Mask on line 18</description>
4112 
              <bitOffset>18</bitOffset>
4113 
              <bitWidth>1</bitWidth>
4114 
            </field>
4115 
          </fields>
4116 
        </register>
4117 
        <register>
4118 
          <name>EMR</name>
4119 
          <displayName>EMR</displayName>
4120 
          <description>Event mask register (EXTI_EMR)</description>
4121 
          <addressOffset>0x4</addressOffset>
4122 
          <size>0x20</size>
4123 
          <access>read-write</access>
4124 
          <resetValue>0x00000000</resetValue>
4125 
          <fields>
4126 
            <field>
4127 
              <name>MR0</name>
4128 
              <description>Event Mask on line 0</description>
4129 
              <bitOffset>0</bitOffset>
4130 
              <bitWidth>1</bitWidth>
4131 
            </field>
4132 
            <field>
4133 
              <name>MR1</name>
4134 
              <description>Event Mask on line 1</description>
4135 
              <bitOffset>1</bitOffset>
4136 
              <bitWidth>1</bitWidth>
4137 
            </field>
4138 
            <field>
4139 
              <name>MR2</name>
4140 
              <description>Event Mask on line 2</description>
4141 
              <bitOffset>2</bitOffset>
4142 
              <bitWidth>1</bitWidth>
4143 
            </field>
4144 
            <field>
4145 
              <name>MR3</name>
4146 
              <description>Event Mask on line 3</description>
4147 
              <bitOffset>3</bitOffset>
4148 
              <bitWidth>1</bitWidth>
4149 
            </field>
4150 
            <field>
4151 
              <name>MR4</name>
4152 
              <description>Event Mask on line 4</description>
4153 
              <bitOffset>4</bitOffset>
4154 
              <bitWidth>1</bitWidth>
4155 
            </field>
4156 
            <field>
4157 
              <name>MR5</name>
4158 
              <description>Event Mask on line 5</description>
4159 
              <bitOffset>5</bitOffset>
4160 
              <bitWidth>1</bitWidth>
4161 
            </field>
4162 
            <field>
4163 
              <name>MR6</name>
4164 
              <description>Event Mask on line 6</description>
4165 
              <bitOffset>6</bitOffset>
4166 
              <bitWidth>1</bitWidth>
4167 
            </field>
4168 
            <field>
4169 
              <name>MR7</name>
4170 
              <description>Event Mask on line 7</description>
4171 
              <bitOffset>7</bitOffset>
4172 
              <bitWidth>1</bitWidth>
4173 
            </field>
4174 
            <field>
4175 
              <name>MR8</name>
4176 
              <description>Event Mask on line 8</description>
4177 
              <bitOffset>8</bitOffset>
4178 
              <bitWidth>1</bitWidth>
4179 
            </field>
4180 
            <field>
4181 
              <name>MR9</name>
4182 
              <description>Event Mask on line 9</description>
4183 
              <bitOffset>9</bitOffset>
4184 
              <bitWidth>1</bitWidth>
4185 
            </field>
4186 
            <field>
4187 
              <name>MR10</name>
4188 
              <description>Event Mask on line 10</description>
4189 
              <bitOffset>10</bitOffset>
4190 
              <bitWidth>1</bitWidth>
4191 
            </field>
4192 
            <field>
4193 
              <name>MR11</name>
4194 
              <description>Event Mask on line 11</description>
4195 
              <bitOffset>11</bitOffset>
4196 
              <bitWidth>1</bitWidth>
4197 
            </field>
4198 
            <field>
4199 
              <name>MR12</name>
4200 
              <description>Event Mask on line 12</description>
4201 
              <bitOffset>12</bitOffset>
4202 
              <bitWidth>1</bitWidth>
4203 
            </field>
4204 
            <field>
4205 
              <name>MR13</name>
4206 
              <description>Event Mask on line 13</description>
4207 
              <bitOffset>13</bitOffset>
4208 
              <bitWidth>1</bitWidth>
4209 
            </field>
4210 
            <field>
4211 
              <name>MR14</name>
4212 
              <description>Event Mask on line 14</description>
4213 
              <bitOffset>14</bitOffset>
4214 
              <bitWidth>1</bitWidth>
4215 
            </field>
4216 
            <field>
4217 
              <name>MR15</name>
4218 
              <description>Event Mask on line 15</description>
4219 
              <bitOffset>15</bitOffset>
4220 
              <bitWidth>1</bitWidth>
4221 
            </field>
4222 
            <field>
4223 
              <name>MR16</name>
4224 
              <description>Event Mask on line 16</description>
4225 
              <bitOffset>16</bitOffset>
4226 
              <bitWidth>1</bitWidth>
4227 
            </field>
4228 
            <field>
4229 
              <name>MR17</name>
4230 
              <description>Event Mask on line 17</description>
4231 
              <bitOffset>17</bitOffset>
4232 
              <bitWidth>1</bitWidth>
4233 
            </field>
4234 
            <field>
4235 
              <name>MR18</name>
4236 
              <description>Event Mask on line 18</description>
4237 
              <bitOffset>18</bitOffset>
4238 
              <bitWidth>1</bitWidth>
4239 
            </field>
4240 
          </fields>
4241 
        </register>
4242 
        <register>
4243 
          <name>RTSR</name>
4244 
          <displayName>RTSR</displayName>
4245 
          <description>Rising Trigger selection register
4246 
          (EXTI_RTSR)</description>
4247 
          <addressOffset>0x8</addressOffset>
4248 
          <size>0x20</size>
4249 
          <access>read-write</access>
4250 
          <resetValue>0x00000000</resetValue>
4251 
          <fields>
4252 
            <field>
4253 
              <name>TR0</name>
4254 
              <description>Rising trigger event configuration of
4255 
              line 0</description>
4256 
              <bitOffset>0</bitOffset>
4257 
              <bitWidth>1</bitWidth>
4258 
            </field>
4259 
            <field>
4260 
              <name>TR1</name>
4261 
              <description>Rising trigger event configuration of
4262 
              line 1</description>
4263 
              <bitOffset>1</bitOffset>
4264 
              <bitWidth>1</bitWidth>
4265 
            </field>
4266 
            <field>
4267 
              <name>TR2</name>
4268 
              <description>Rising trigger event configuration of
4269 
              line 2</description>
4270 
              <bitOffset>2</bitOffset>
4271 
              <bitWidth>1</bitWidth>
4272 
            </field>
4273 
            <field>
4274 
              <name>TR3</name>
4275 
              <description>Rising trigger event configuration of
4276 
              line 3</description>
4277 
              <bitOffset>3</bitOffset>
4278 
              <bitWidth>1</bitWidth>
4279 
            </field>
4280 
            <field>
4281 
              <name>TR4</name>
4282 
              <description>Rising trigger event configuration of
4283 
              line 4</description>
4284 
              <bitOffset>4</bitOffset>
4285 
              <bitWidth>1</bitWidth>
4286 
            </field>
4287 
            <field>
4288 
              <name>TR5</name>
4289 
              <description>Rising trigger event configuration of
4290 
              line 5</description>
4291 
              <bitOffset>5</bitOffset>
4292 
              <bitWidth>1</bitWidth>
4293 
            </field>
4294 
            <field>
4295 
              <name>TR6</name>
4296 
              <description>Rising trigger event configuration of
4297 
              line 6</description>
4298 
              <bitOffset>6</bitOffset>
4299 
              <bitWidth>1</bitWidth>
4300 
            </field>
4301 
            <field>
4302 
              <name>TR7</name>
4303 
              <description>Rising trigger event configuration of
4304 
              line 7</description>
4305 
              <bitOffset>7</bitOffset>
4306 
              <bitWidth>1</bitWidth>
4307 
            </field>
4308 
            <field>
4309 
              <name>TR8</name>
4310 
              <description>Rising trigger event configuration of
4311 
              line 8</description>
4312 
              <bitOffset>8</bitOffset>
4313 
              <bitWidth>1</bitWidth>
4314 
            </field>
4315 
            <field>
4316 
              <name>TR9</name>
4317 
              <description>Rising trigger event configuration of
4318 
              line 9</description>
4319 
              <bitOffset>9</bitOffset>
4320 
              <bitWidth>1</bitWidth>
4321 
            </field>
4322 
            <field>
4323 
              <name>TR10</name>
4324 
              <description>Rising trigger event configuration of
4325 
              line 10</description>
4326 
              <bitOffset>10</bitOffset>
4327 
              <bitWidth>1</bitWidth>
4328 
            </field>
4329 
            <field>
4330 
              <name>TR11</name>
4331 
              <description>Rising trigger event configuration of
4332 
              line 11</description>
4333 
              <bitOffset>11</bitOffset>
4334 
              <bitWidth>1</bitWidth>
4335 
            </field>
4336 
            <field>
4337 
              <name>TR12</name>
4338 
              <description>Rising trigger event configuration of
4339 
              line 12</description>
4340 
              <bitOffset>12</bitOffset>
4341 
              <bitWidth>1</bitWidth>
4342 
            </field>
4343 
            <field>
4344 
              <name>TR13</name>
4345 
              <description>Rising trigger event configuration of
4346 
              line 13</description>
4347 
              <bitOffset>13</bitOffset>
4348 
              <bitWidth>1</bitWidth>
4349 
            </field>
4350 
            <field>
4351 
              <name>TR14</name>
4352 
              <description>Rising trigger event configuration of
4353 
              line 14</description>
4354 
              <bitOffset>14</bitOffset>
4355 
              <bitWidth>1</bitWidth>
4356 
            </field>
4357 
            <field>
4358 
              <name>TR15</name>
4359 
              <description>Rising trigger event configuration of
4360 
              line 15</description>
4361 
              <bitOffset>15</bitOffset>
4362 
              <bitWidth>1</bitWidth>
4363 
            </field>
4364 
            <field>
4365 
              <name>TR16</name>
4366 
              <description>Rising trigger event configuration of
4367 
              line 16</description>
4368 
              <bitOffset>16</bitOffset>
4369 
              <bitWidth>1</bitWidth>
4370 
            </field>
4371 
            <field>
4372 
              <name>TR17</name>
4373 
              <description>Rising trigger event configuration of
4374 
              line 17</description>
4375 
              <bitOffset>17</bitOffset>
4376 
              <bitWidth>1</bitWidth>
4377 
            </field>
4378 
            <field>
4379 
              <name>TR18</name>
4380 
              <description>Rising trigger event configuration of
4381 
              line 18</description>
4382 
              <bitOffset>18</bitOffset>
4383 
              <bitWidth>1</bitWidth>
4384 
            </field>
4385 
          </fields>
4386 
        </register>
4387 
        <register>
4388 
          <name>FTSR</name>
4389 
          <displayName>FTSR</displayName>
4390 
          <description>Falling Trigger selection register
4391 
          (EXTI_FTSR)</description>
4392 
          <addressOffset>0xC</addressOffset>
4393 
          <size>0x20</size>
4394 
          <access>read-write</access>
4395 
          <resetValue>0x00000000</resetValue>
4396 
          <fields>
4397 
            <field>
4398 
              <name>TR0</name>
4399 
              <description>Falling trigger event configuration of
4400 
              line 0</description>
4401 
              <bitOffset>0</bitOffset>
4402 
              <bitWidth>1</bitWidth>
4403 
            </field>
4404 
            <field>
4405 
              <name>TR1</name>
4406 
              <description>Falling trigger event configuration of
4407 
              line 1</description>
4408 
              <bitOffset>1</bitOffset>
4409 
              <bitWidth>1</bitWidth>
4410 
            </field>
4411 
            <field>
4412 
              <name>TR2</name>
4413 
              <description>Falling trigger event configuration of
4414 
              line 2</description>
4415 
              <bitOffset>2</bitOffset>
4416 
              <bitWidth>1</bitWidth>
4417 
            </field>
4418 
            <field>
4419 
              <name>TR3</name>
4420 
              <description>Falling trigger event configuration of
4421 
              line 3</description>
4422 
              <bitOffset>3</bitOffset>
4423 
              <bitWidth>1</bitWidth>
4424 
            </field>
4425 
            <field>
4426 
              <name>TR4</name>
4427 
              <description>Falling trigger event configuration of
4428 
              line 4</description>
4429 
              <bitOffset>4</bitOffset>
4430 
              <bitWidth>1</bitWidth>
4431 
            </field>
4432 
            <field>
4433 
              <name>TR5</name>
4434 
              <description>Falling trigger event configuration of
4435 
              line 5</description>
4436 
              <bitOffset>5</bitOffset>
4437 
              <bitWidth>1</bitWidth>
4438 
            </field>
4439 
            <field>
4440 
              <name>TR6</name>
4441 
              <description>Falling trigger event configuration of
4442 
              line 6</description>
4443 
              <bitOffset>6</bitOffset>
4444 
              <bitWidth>1</bitWidth>
4445 
            </field>
4446 
            <field>
4447 
              <name>TR7</name>
4448 
              <description>Falling trigger event configuration of
4449 
              line 7</description>
4450 
              <bitOffset>7</bitOffset>
4451 
              <bitWidth>1</bitWidth>
4452 
            </field>
4453 
            <field>
4454 
              <name>TR8</name>
4455 
              <description>Falling trigger event configuration of
4456 
              line 8</description>
4457 
              <bitOffset>8</bitOffset>
4458 
              <bitWidth>1</bitWidth>
4459 
            </field>
4460 
            <field>
4461 
              <name>TR9</name>
4462 
              <description>Falling trigger event configuration of
4463 
              line 9</description>
4464 
              <bitOffset>9</bitOffset>
4465 
              <bitWidth>1</bitWidth>
4466 
            </field>
4467 
            <field>
4468 
              <name>TR10</name>
4469 
              <description>Falling trigger event configuration of
4470 
              line 10</description>
4471 
              <bitOffset>10</bitOffset>
4472 
              <bitWidth>1</bitWidth>
4473 
            </field>
4474 
            <field>
4475 
              <name>TR11</name>
4476 
              <description>Falling trigger event configuration of
4477 
              line 11</description>
4478 
              <bitOffset>11</bitOffset>
4479 
              <bitWidth>1</bitWidth>
4480 
            </field>
4481 
            <field>
4482 
              <name>TR12</name>
4483 
              <description>Falling trigger event configuration of
4484 
              line 12</description>
4485 
              <bitOffset>12</bitOffset>
4486 
              <bitWidth>1</bitWidth>
4487 
            </field>
4488 
            <field>
4489 
              <name>TR13</name>
4490 
              <description>Falling trigger event configuration of
4491 
              line 13</description>
4492 
              <bitOffset>13</bitOffset>
4493 
              <bitWidth>1</bitWidth>
4494 
            </field>
4495 
            <field>
4496 
              <name>TR14</name>
4497 
              <description>Falling trigger event configuration of
4498 
              line 14</description>
4499 
              <bitOffset>14</bitOffset>
4500 
              <bitWidth>1</bitWidth>
4501 
            </field>
4502 
            <field>
4503 
              <name>TR15</name>
4504 
              <description>Falling trigger event configuration of
4505 
              line 15</description>
4506 
              <bitOffset>15</bitOffset>
4507 
              <bitWidth>1</bitWidth>
4508 
            </field>
4509 
            <field>
4510 
              <name>TR16</name>
4511 
              <description>Falling trigger event configuration of
4512 
              line 16</description>
4513 
              <bitOffset>16</bitOffset>
4514 
              <bitWidth>1</bitWidth>
4515 
            </field>
4516 
            <field>
4517 
              <name>TR17</name>
4518 
              <description>Falling trigger event configuration of
4519 
              line 17</description>
4520 
              <bitOffset>17</bitOffset>
4521 
              <bitWidth>1</bitWidth>
4522 
            </field>
4523 
            <field>
4524 
              <name>TR18</name>
4525 
              <description>Falling trigger event configuration of
4526 
              line 18</description>
4527 
              <bitOffset>18</bitOffset>
4528 
              <bitWidth>1</bitWidth>
4529 
            </field>
4530 
          </fields>
4531 
        </register>
4532 
        <register>
4533 
          <name>SWIER</name>
4534 
          <displayName>SWIER</displayName>
4535 
          <description>Software interrupt event register
4536 
          (EXTI_SWIER)</description>
4537 
          <addressOffset>0x10</addressOffset>
4538 
          <size>0x20</size>
4539 
          <access>read-write</access>
4540 
          <resetValue>0x00000000</resetValue>
4541 
          <fields>
4542 
            <field>
4543 
              <name>SWIER0</name>
4544 
              <description>Software Interrupt on line
4545 
              0</description>
4546 
              <bitOffset>0</bitOffset>
4547 
              <bitWidth>1</bitWidth>
4548 
            </field>
4549 
            <field>
4550 
              <name>SWIER1</name>
4551 
              <description>Software Interrupt on line
4552 
              1</description>
4553 
              <bitOffset>1</bitOffset>
4554 
              <bitWidth>1</bitWidth>
4555 
            </field>
4556 
            <field>
4557 
              <name>SWIER2</name>
4558 
              <description>Software Interrupt on line
4559 
              2</description>
4560 
              <bitOffset>2</bitOffset>
4561 
              <bitWidth>1</bitWidth>
4562 
            </field>
4563 
            <field>
4564 
              <name>SWIER3</name>
4565 
              <description>Software Interrupt on line
4566 
              3</description>
4567 
              <bitOffset>3</bitOffset>
4568 
              <bitWidth>1</bitWidth>
4569 
            </field>
4570 
            <field>
4571 
              <name>SWIER4</name>
4572 
              <description>Software Interrupt on line
4573 
              4</description>
4574 
              <bitOffset>4</bitOffset>
4575 
              <bitWidth>1</bitWidth>
4576 
            </field>
4577 
            <field>
4578 
              <name>SWIER5</name>
4579 
              <description>Software Interrupt on line
4580 
              5</description>
4581 
              <bitOffset>5</bitOffset>
4582 
              <bitWidth>1</bitWidth>
4583 
            </field>
4584 
            <field>
4585 
              <name>SWIER6</name>
4586 
              <description>Software Interrupt on line
4587 
              6</description>
4588 
              <bitOffset>6</bitOffset>
4589 
              <bitWidth>1</bitWidth>
4590 
            </field>
4591 
            <field>
4592 
              <name>SWIER7</name>
4593 
              <description>Software Interrupt on line
4594 
              7</description>
4595 
              <bitOffset>7</bitOffset>
4596 
              <bitWidth>1</bitWidth>
4597 
            </field>
4598 
            <field>
4599 
              <name>SWIER8</name>
4600 
              <description>Software Interrupt on line
4601 
              8</description>
4602 
              <bitOffset>8</bitOffset>
4603 
              <bitWidth>1</bitWidth>
4604 
            </field>
4605 
            <field>
4606 
              <name>SWIER9</name>
4607 
              <description>Software Interrupt on line
4608 
              9</description>
4609 
              <bitOffset>9</bitOffset>
4610 
              <bitWidth>1</bitWidth>
4611 
            </field>
4612 
            <field>
4613 
              <name>SWIER10</name>
4614 
              <description>Software Interrupt on line
4615 
              10</description>
4616 
              <bitOffset>10</bitOffset>
4617 
              <bitWidth>1</bitWidth>
4618 
            </field>
4619 
            <field>
4620 
              <name>SWIER11</name>
4621 
              <description>Software Interrupt on line
4622 
              11</description>
4623 
              <bitOffset>11</bitOffset>
4624 
              <bitWidth>1</bitWidth>
4625 
            </field>
4626 
            <field>
4627 
              <name>SWIER12</name>
4628 
              <description>Software Interrupt on line
4629 
              12</description>
4630 
              <bitOffset>12</bitOffset>
4631 
              <bitWidth>1</bitWidth>
4632 
            </field>
4633 
            <field>
4634 
              <name>SWIER13</name>
4635 
              <description>Software Interrupt on line
4636 
              13</description>
4637 
              <bitOffset>13</bitOffset>
4638 
              <bitWidth>1</bitWidth>
4639 
            </field>
4640 
            <field>
4641 
              <name>SWIER14</name>
4642 
              <description>Software Interrupt on line
4643 
              14</description>
4644 
              <bitOffset>14</bitOffset>
4645 
              <bitWidth>1</bitWidth>
4646 
            </field>
4647 
            <field>
4648 
              <name>SWIER15</name>
4649 
              <description>Software Interrupt on line
4650 
              15</description>
4651 
              <bitOffset>15</bitOffset>
4652 
              <bitWidth>1</bitWidth>
4653 
            </field>
4654 
            <field>
4655 
              <name>SWIER16</name>
4656 
              <description>Software Interrupt on line
4657 
              16</description>
4658 
              <bitOffset>16</bitOffset>
4659 
              <bitWidth>1</bitWidth>
4660 
            </field>
4661 
            <field>
4662 
              <name>SWIER17</name>
4663 
              <description>Software Interrupt on line
4664 
              17</description>
4665 
              <bitOffset>17</bitOffset>
4666 
              <bitWidth>1</bitWidth>
4667 
            </field>
4668 
            <field>
4669 
              <name>SWIER18</name>
4670 
              <description>Software Interrupt on line
4671 
              18</description>
4672 
              <bitOffset>18</bitOffset>
4673 
              <bitWidth>1</bitWidth>
4674 
            </field>
4675 
          </fields>
4676 
        </register>
4677 
        <register>
4678 
          <name>PR</name>
4679 
          <displayName>PR</displayName>
4680 
          <description>Pending register (EXTI_PR)</description>
4681 
          <addressOffset>0x14</addressOffset>
4682 
          <size>0x20</size>
4683 
          <access>read-write</access>
4684 
          <resetValue>0x00000000</resetValue>
4685 
          <fields>
4686 
            <field>
4687 
              <name>PR0</name>
4688 
              <description>Pending bit 0</description>
4689 
              <bitOffset>0</bitOffset>
4690 
              <bitWidth>1</bitWidth>
4691 
            </field>
4692 
            <field>
4693 
              <name>PR1</name>
4694 
              <description>Pending bit 1</description>
4695 
              <bitOffset>1</bitOffset>
4696 
              <bitWidth>1</bitWidth>
4697 
            </field>
4698 
            <field>
4699 
              <name>PR2</name>
4700 
              <description>Pending bit 2</description>
4701 
              <bitOffset>2</bitOffset>
4702 
              <bitWidth>1</bitWidth>
4703 
            </field>
4704 
            <field>
4705 
              <name>PR3</name>
4706 
              <description>Pending bit 3</description>
4707 
              <bitOffset>3</bitOffset>
4708 
              <bitWidth>1</bitWidth>
4709 
            </field>
4710 
            <field>
4711 
              <name>PR4</name>
4712 
              <description>Pending bit 4</description>
4713 
              <bitOffset>4</bitOffset>
4714 
              <bitWidth>1</bitWidth>
4715 
            </field>
4716 
            <field>
4717 
              <name>PR5</name>
4718 
              <description>Pending bit 5</description>
4719 
              <bitOffset>5</bitOffset>
4720 
              <bitWidth>1</bitWidth>
4721 
            </field>
4722 
            <field>
4723 
              <name>PR6</name>
4724 
              <description>Pending bit 6</description>
4725 
              <bitOffset>6</bitOffset>
4726 
              <bitWidth>1</bitWidth>
4727 
            </field>
4728 
            <field>
4729 
              <name>PR7</name>
4730 
              <description>Pending bit 7</description>
4731 
              <bitOffset>7</bitOffset>
4732 
              <bitWidth>1</bitWidth>
4733 
            </field>
4734 
            <field>
4735 
              <name>PR8</name>
4736 
              <description>Pending bit 8</description>
4737 
              <bitOffset>8</bitOffset>
4738 
              <bitWidth>1</bitWidth>
4739 
            </field>
4740 
            <field>
4741 
              <name>PR9</name>
4742 
              <description>Pending bit 9</description>
4743 
              <bitOffset>9</bitOffset>
4744 
              <bitWidth>1</bitWidth>
4745 
            </field>
4746 
            <field>
4747 
              <name>PR10</name>
4748 
              <description>Pending bit 10</description>
4749 
              <bitOffset>10</bitOffset>
4750 
              <bitWidth>1</bitWidth>
4751 
            </field>
4752 
            <field>
4753 
              <name>PR11</name>
4754 
              <description>Pending bit 11</description>
4755 
              <bitOffset>11</bitOffset>
4756 
              <bitWidth>1</bitWidth>
4757 
            </field>
4758 
            <field>
4759 
              <name>PR12</name>
4760 
              <description>Pending bit 12</description>
4761 
              <bitOffset>12</bitOffset>
4762 
              <bitWidth>1</bitWidth>
4763 
            </field>
4764 
            <field>
4765 
              <name>PR13</name>
4766 
              <description>Pending bit 13</description>
4767 
              <bitOffset>13</bitOffset>
4768 
              <bitWidth>1</bitWidth>
4769 
            </field>
4770 
            <field>
4771 
              <name>PR14</name>
4772 
              <description>Pending bit 14</description>
4773 
              <bitOffset>14</bitOffset>
4774 
              <bitWidth>1</bitWidth>
4775 
            </field>
4776 
            <field>
4777 
              <name>PR15</name>
4778 
              <description>Pending bit 15</description>
4779 
              <bitOffset>15</bitOffset>
4780 
              <bitWidth>1</bitWidth>
4781 
            </field>
4782 
            <field>
4783 
              <name>PR16</name>
4784 
              <description>Pending bit 16</description>
4785 
              <bitOffset>16</bitOffset>
4786 
              <bitWidth>1</bitWidth>
4787 
            </field>
4788 
            <field>
4789 
              <name>PR17</name>
4790 
              <description>Pending bit 17</description>
4791 
              <bitOffset>17</bitOffset>
4792 
              <bitWidth>1</bitWidth>
4793 
            </field>
4794 
            <field>
4795 
              <name>PR18</name>
4796 
              <description>Pending bit 18</description>
4797 
              <bitOffset>18</bitOffset>
4798 
              <bitWidth>1</bitWidth>
4799 
            </field>
4800 
          </fields>
4801 
        </register>
4802 
      </registers>
4803 
    </peripheral>
4804 
    <peripheral>
4805 
      <name>DMA1</name>
4806 
      <description>DMA controller</description>
4807 
      <groupName>DMA</groupName>
4808 
      <baseAddress>0x40020000</baseAddress>
4809 
      <addressBlock>
4810 
        <offset>0x0</offset>
4811 
        <size>0x400</size>
4812 
        <usage>registers</usage>
4813 
      </addressBlock>
4814 
      <interrupt>
4815 
        <name>DMA1_Channel1</name>
4816 
        <description>DMA1 Channel1 global interrupt</description>
4817 
        <value>11</value>
4818 
      </interrupt>
4819 
      <interrupt>
4820 
        <name>DMA1_Channel2</name>
4821 
        <description>DMA1 Channel2 global interrupt</description>
4822 
        <value>12</value>
4823 
      </interrupt>
4824 
      <interrupt>
4825 
        <name>DMA1_Channel3</name>
4826 
        <description>DMA1 Channel3 global interrupt</description>
4827 
        <value>13</value>
4828 
      </interrupt>
4829 
      <interrupt>
4830 
        <name>DMA1_Channel4</name>
4831 
        <description>DMA1 Channel4 global interrupt</description>
4832 
        <value>14</value>
4833 
      </interrupt>
4834 
      <interrupt>
4835 
        <name>DMA1_Channel5</name>
4836 
        <description>DMA1 Channel5 global interrupt</description>
4837 
        <value>15</value>
4838 
      </interrupt>
4839 
      <interrupt>
4840 
        <name>DMA1_Channel6</name>
4841 
        <description>DMA1 Channel6 global interrupt</description>
4842 
        <value>16</value>
4843 
      </interrupt>
4844 
      <interrupt>
4845 
        <name>DMA1_Channel7</name>
4846 
        <description>DMA1 Channel7 global interrupt</description>
4847 
        <value>17</value>
4848 
      </interrupt>
4849 
      <registers>
4850 
        <register>
4851 
          <name>ISR</name>
4852 
          <displayName>ISR</displayName>
4853 
          <description>DMA interrupt status register
4854 
          (DMA_ISR)</description>
4855 
          <addressOffset>0x0</addressOffset>
4856 
          <size>0x20</size>
4857 
          <access>read-only</access>
4858 
          <resetValue>0x00000000</resetValue>
4859 
          <fields>
4860 
            <field>
4861 
              <name>GIF1</name>
4862 
              <description>Channel 1 Global interrupt
4863 
              flag</description>
4864 
              <bitOffset>0</bitOffset>
4865 
              <bitWidth>1</bitWidth>
4866 
            </field>
4867 
            <field>
4868 
              <name>TCIF1</name>
4869 
              <description>Channel 1 Transfer Complete
4870 
              flag</description>
4871 
              <bitOffset>1</bitOffset>
4872 
              <bitWidth>1</bitWidth>
4873 
            </field>
4874 
            <field>
4875 
              <name>HTIF1</name>
4876 
              <description>Channel 1 Half Transfer Complete
4877 
              flag</description>
4878 
              <bitOffset>2</bitOffset>
4879 
              <bitWidth>1</bitWidth>
4880 
            </field>
4881 
            <field>
4882 
              <name>TEIF1</name>
4883 
              <description>Channel 1 Transfer Error
4884 
              flag</description>
4885 
              <bitOffset>3</bitOffset>
4886 
              <bitWidth>1</bitWidth>
4887 
            </field>
4888 
            <field>
4889 
              <name>GIF2</name>
4890 
              <description>Channel 2 Global interrupt
4891 
              flag</description>
4892 
              <bitOffset>4</bitOffset>
4893 
              <bitWidth>1</bitWidth>
4894 
            </field>
4895 
            <field>
4896 
              <name>TCIF2</name>
4897 
              <description>Channel 2 Transfer Complete
4898 
              flag</description>
4899 
              <bitOffset>5</bitOffset>
4900 
              <bitWidth>1</bitWidth>
4901 
            </field>
4902 
            <field>
4903 
              <name>HTIF2</name>
4904 
              <description>Channel 2 Half Transfer Complete
4905 
              flag</description>
4906 
              <bitOffset>6</bitOffset>
4907 
              <bitWidth>1</bitWidth>
4908 
            </field>
4909 
            <field>
4910 
              <name>TEIF2</name>
4911 
              <description>Channel 2 Transfer Error
4912 
              flag</description>
4913 
              <bitOffset>7</bitOffset>
4914 
              <bitWidth>1</bitWidth>
4915 
            </field>
4916 
            <field>
4917 
              <name>GIF3</name>
4918 
              <description>Channel 3 Global interrupt
4919 
              flag</description>
4920 
              <bitOffset>8</bitOffset>
4921 
              <bitWidth>1</bitWidth>
4922 
            </field>
4923 
            <field>
4924 
              <name>TCIF3</name>
4925 
              <description>Channel 3 Transfer Complete
4926 
              flag</description>
4927 
              <bitOffset>9</bitOffset>
4928 
              <bitWidth>1</bitWidth>
4929 
            </field>
4930 
            <field>
4931 
              <name>HTIF3</name>
4932 
              <description>Channel 3 Half Transfer Complete
4933 
              flag</description>
4934 
              <bitOffset>10</bitOffset>
4935 
              <bitWidth>1</bitWidth>
4936 
            </field>
4937 
            <field>
4938 
              <name>TEIF3</name>
4939 
              <description>Channel 3 Transfer Error
4940 
              flag</description>
4941 
              <bitOffset>11</bitOffset>
4942 
              <bitWidth>1</bitWidth>
4943 
            </field>
4944 
            <field>
4945 
              <name>GIF4</name>
4946 
              <description>Channel 4 Global interrupt
4947 
              flag</description>
4948 
              <bitOffset>12</bitOffset>
4949 
              <bitWidth>1</bitWidth>
4950 
            </field>
4951 
            <field>
4952 
              <name>TCIF4</name>
4953 
              <description>Channel 4 Transfer Complete
4954 
              flag</description>
4955 
              <bitOffset>13</bitOffset>
4956 
              <bitWidth>1</bitWidth>
4957 
            </field>
4958 
            <field>
4959 
              <name>HTIF4</name>
4960 
              <description>Channel 4 Half Transfer Complete
4961 
              flag</description>
4962 
              <bitOffset>14</bitOffset>
4963 
              <bitWidth>1</bitWidth>
4964 
            </field>
4965 
            <field>
4966 
              <name>TEIF4</name>
4967 
              <description>Channel 4 Transfer Error
4968 
              flag</description>
4969 
              <bitOffset>15</bitOffset>
4970 
              <bitWidth>1</bitWidth>
4971 
            </field>
4972 
            <field>
4973 
              <name>GIF5</name>
4974 
              <description>Channel 5 Global interrupt
4975 
              flag</description>
4976 
              <bitOffset>16</bitOffset>
4977 
              <bitWidth>1</bitWidth>
4978 
            </field>
4979 
            <field>
4980 
              <name>TCIF5</name>
4981 
              <description>Channel 5 Transfer Complete
4982 
              flag</description>
4983 
              <bitOffset>17</bitOffset>
4984 
              <bitWidth>1</bitWidth>
4985 
            </field>
4986 
            <field>
4987 
              <name>HTIF5</name>
4988 
              <description>Channel 5 Half Transfer Complete
4989 
              flag</description>
4990 
              <bitOffset>18</bitOffset>
4991 
              <bitWidth>1</bitWidth>
4992 
            </field>
4993 
            <field>
4994 
              <name>TEIF5</name>
4995 
              <description>Channel 5 Transfer Error
4996 
              flag</description>
4997 
              <bitOffset>19</bitOffset>
4998 
              <bitWidth>1</bitWidth>
4999 
            </field>
5000 
            <field>
5001 
              <name>GIF6</name>
5002 
              <description>Channel 6 Global interrupt
5003 
              flag</description>
5004 
              <bitOffset>20</bitOffset>
5005 
              <bitWidth>1</bitWidth>
5006 
            </field>
5007 
            <field>
5008 
              <name>TCIF6</name>
5009 
              <description>Channel 6 Transfer Complete
5010 
              flag</description>
5011 
              <bitOffset>21</bitOffset>
5012 
              <bitWidth>1</bitWidth>
5013 
            </field>
5014 
            <field>
5015 
              <name>HTIF6</name>
5016 
              <description>Channel 6 Half Transfer Complete
5017 
              flag</description>
5018 
              <bitOffset>22</bitOffset>
5019 
              <bitWidth>1</bitWidth>
5020 
            </field>
5021 
            <field>
5022 
              <name>TEIF6</name>
5023 
              <description>Channel 6 Transfer Error
5024 
              flag</description>
5025 
              <bitOffset>23</bitOffset>
5026 
              <bitWidth>1</bitWidth>
5027 
            </field>
5028 
            <field>
5029 
              <name>GIF7</name>
5030 
              <description>Channel 7 Global interrupt
5031 
              flag</description>
5032 
              <bitOffset>24</bitOffset>
5033 
              <bitWidth>1</bitWidth>
5034 
            </field>
5035 
            <field>
5036 
              <name>TCIF7</name>
5037 
              <description>Channel 7 Transfer Complete
5038 
              flag</description>
5039 
              <bitOffset>25</bitOffset>
5040 
              <bitWidth>1</bitWidth>
5041 
            </field>
5042 
            <field>
5043 
              <name>HTIF7</name>
5044 
              <description>Channel 7 Half Transfer Complete
5045 
              flag</description>
5046 
              <bitOffset>26</bitOffset>
5047 
              <bitWidth>1</bitWidth>
5048 
            </field>
5049 
            <field>
5050 
              <name>TEIF7</name>
5051 
              <description>Channel 7 Transfer Error
5052 
              flag</description>
5053 
              <bitOffset>27</bitOffset>
5054 
              <bitWidth>1</bitWidth>
5055 
            </field>
5056 
          </fields>
5057 
        </register>
5058 
        <register>
5059 
          <name>IFCR</name>
5060 
          <displayName>IFCR</displayName>
5061 
          <description>DMA interrupt flag clear register
5062 
          (DMA_IFCR)</description>
5063 
          <addressOffset>0x4</addressOffset>
5064 
          <size>0x20</size>
5065 
          <access>write-only</access>
5066 
          <resetValue>0x00000000</resetValue>
5067 
          <fields>
5068 
            <field>
5069 
              <name>CGIF1</name>
5070 
              <description>Channel 1 Global interrupt
5071 
              clear</description>
5072 
              <bitOffset>0</bitOffset>
5073 
              <bitWidth>1</bitWidth>
5074 
            </field>
5075 
            <field>
5076 
              <name>CGIF2</name>
5077 
              <description>Channel 2 Global interrupt
5078 
              clear</description>
5079 
              <bitOffset>4</bitOffset>
5080 
              <bitWidth>1</bitWidth>
5081 
            </field>
5082 
            <field>
5083 
              <name>CGIF3</name>
5084 
              <description>Channel 3 Global interrupt
5085 
              clear</description>
5086 
              <bitOffset>8</bitOffset>
5087 
              <bitWidth>1</bitWidth>
5088 
            </field>
5089 
            <field>
5090 
              <name>CGIF4</name>
5091 
              <description>Channel 4 Global interrupt
5092 
              clear</description>
5093 
              <bitOffset>12</bitOffset>
5094 
              <bitWidth>1</bitWidth>
5095 
            </field>
5096 
            <field>
5097 
              <name>CGIF5</name>
5098 
              <description>Channel 5 Global interrupt
5099 
              clear</description>
5100 
              <bitOffset>16</bitOffset>
5101 
              <bitWidth>1</bitWidth>
5102 
            </field>
5103 
            <field>
5104 
              <name>CGIF6</name>
5105 
              <description>Channel 6 Global interrupt
5106 
              clear</description>
5107 
              <bitOffset>20</bitOffset>
5108 
              <bitWidth>1</bitWidth>
5109 
            </field>
5110 
            <field>
5111 
              <name>CGIF7</name>
5112 
              <description>Channel 7 Global interrupt
5113 
              clear</description>
5114 
              <bitOffset>24</bitOffset>
5115 
              <bitWidth>1</bitWidth>
5116 
            </field>
5117 
            <field>
5118 
              <name>CTCIF1</name>
5119 
              <description>Channel 1 Transfer Complete
5120 
              clear</description>
5121 
              <bitOffset>1</bitOffset>
5122 
              <bitWidth>1</bitWidth>
5123 
            </field>
5124 
            <field>
5125 
              <name>CTCIF2</name>
5126 
              <description>Channel 2 Transfer Complete
5127 
              clear</description>
5128 
              <bitOffset>5</bitOffset>
5129 
              <bitWidth>1</bitWidth>
5130 
            </field>
5131 
            <field>
5132 
              <name>CTCIF3</name>
5133 
              <description>Channel 3 Transfer Complete
5134 
              clear</description>
5135 
              <bitOffset>9</bitOffset>
5136 
              <bitWidth>1</bitWidth>
5137 
            </field>
5138 
            <field>
5139 
              <name>CTCIF4</name>
5140 
              <description>Channel 4 Transfer Complete
5141 
              clear</description>
5142 
              <bitOffset>13</bitOffset>
5143 
              <bitWidth>1</bitWidth>
5144 
            </field>
5145 
            <field>
5146 
              <name>CTCIF5</name>
5147 
              <description>Channel 5 Transfer Complete
5148 
              clear</description>
5149 
              <bitOffset>17</bitOffset>
5150 
              <bitWidth>1</bitWidth>
5151 
            </field>
5152 
            <field>
5153 
              <name>CTCIF6</name>
5154 
              <description>Channel 6 Transfer Complete
5155 
              clear</description>
5156 
              <bitOffset>21</bitOffset>
5157 
              <bitWidth>1</bitWidth>
5158 
            </field>
5159 
            <field>
5160 
              <name>CTCIF7</name>
5161 
              <description>Channel 7 Transfer Complete
5162 
              clear</description>
5163 
              <bitOffset>25</bitOffset>
5164 
              <bitWidth>1</bitWidth>
5165 
            </field>
5166 
            <field>
5167 
              <name>CHTIF1</name>
5168 
              <description>Channel 1 Half Transfer
5169 
              clear</description>
5170 
              <bitOffset>2</bitOffset>
5171 
              <bitWidth>1</bitWidth>
5172 
            </field>
5173 
            <field>
5174 
              <name>CHTIF2</name>
5175 
              <description>Channel 2 Half Transfer
5176 
              clear</description>
5177 
              <bitOffset>6</bitOffset>
5178 
              <bitWidth>1</bitWidth>
5179 
            </field>
5180 
            <field>
5181 
              <name>CHTIF3</name>
5182 
              <description>Channel 3 Half Transfer
5183 
              clear</description>
5184 
              <bitOffset>10</bitOffset>
5185 
              <bitWidth>1</bitWidth>
5186 
            </field>
5187 
            <field>
5188 
              <name>CHTIF4</name>
5189 
              <description>Channel 4 Half Transfer
5190 
              clear</description>
5191 
              <bitOffset>14</bitOffset>
5192 
              <bitWidth>1</bitWidth>
5193 
            </field>
5194 
            <field>
5195 
              <name>CHTIF5</name>
5196 
              <description>Channel 5 Half Transfer
5197 
              clear</description>
5198 
              <bitOffset>18</bitOffset>
5199 
              <bitWidth>1</bitWidth>
5200 
            </field>
5201 
            <field>
5202 
              <name>CHTIF6</name>
5203 
              <description>Channel 6 Half Transfer
5204 
              clear</description>
5205 
              <bitOffset>22</bitOffset>
5206 
              <bitWidth>1</bitWidth>
5207 
            </field>
5208 
            <field>
5209 
              <name>CHTIF7</name>
5210 
              <description>Channel 7 Half Transfer
5211 
              clear</description>
5212 
              <bitOffset>26</bitOffset>
5213 
              <bitWidth>1</bitWidth>
5214 
            </field>
5215 
            <field>
5216 
              <name>CTEIF1</name>
5217 
              <description>Channel 1 Transfer Error
5218 
              clear</description>
5219 
              <bitOffset>3</bitOffset>
5220 
              <bitWidth>1</bitWidth>
5221 
            </field>
5222 
            <field>
5223 
              <name>CTEIF2</name>
5224 
              <description>Channel 2 Transfer Error
5225 
              clear</description>
5226 
              <bitOffset>7</bitOffset>
5227 
              <bitWidth>1</bitWidth>
5228 
            </field>
5229 
            <field>
5230 
              <name>CTEIF3</name>
5231 
              <description>Channel 3 Transfer Error
5232 
              clear</description>
5233 
              <bitOffset>11</bitOffset>
5234 
              <bitWidth>1</bitWidth>
5235 
            </field>
5236 
            <field>
5237 
              <name>CTEIF4</name>
5238 
              <description>Channel 4 Transfer Error
5239 
              clear</description>
5240 
              <bitOffset>15</bitOffset>
5241 
              <bitWidth>1</bitWidth>
5242 
            </field>
5243 
            <field>
5244 
              <name>CTEIF5</name>
5245 
              <description>Channel 5 Transfer Error
5246 
              clear</description>
5247 
              <bitOffset>19</bitOffset>
5248 
              <bitWidth>1</bitWidth>
5249 
            </field>
5250 
            <field>
5251 
              <name>CTEIF6</name>
5252 
              <description>Channel 6 Transfer Error
5253 
              clear</description>
5254 
              <bitOffset>23</bitOffset>
5255 
              <bitWidth>1</bitWidth>
5256 
            </field>
5257 
            <field>
5258 
              <name>CTEIF7</name>
5259 
              <description>Channel 7 Transfer Error
5260 
              clear</description>
5261 
              <bitOffset>27</bitOffset>
5262 
              <bitWidth>1</bitWidth>
5263 
            </field>
5264 
          </fields>
5265 
        </register>
5266 
        <register>
5267 
          <name>CCR1</name>
5268 
          <displayName>CCR1</displayName>
5269 
          <description>DMA channel configuration register
5270 
          (DMA_CCR)</description>
5271 
          <addressOffset>0x8</addressOffset>
5272 
          <size>0x20</size>
5273 
          <access>read-write</access>
5274 
          <resetValue>0x00000000</resetValue>
5275 
          <fields>
5276 
            <field>
5277 
              <name>EN</name>
5278 
              <description>Channel enable</description>
5279 
              <bitOffset>0</bitOffset>
5280 
              <bitWidth>1</bitWidth>
5281 
            </field>
5282 
            <field>
5283 
              <name>TCIE</name>
5284 
              <description>Transfer complete interrupt
5285 
              enable</description>
5286 
              <bitOffset>1</bitOffset>
5287 
              <bitWidth>1</bitWidth>
5288 
            </field>
5289 
            <field>
5290 
              <name>HTIE</name>
5291 
              <description>Half Transfer interrupt
5292 
              enable</description>
5293 
              <bitOffset>2</bitOffset>
5294 
              <bitWidth>1</bitWidth>
5295 
            </field>
5296 
            <field>
5297 
              <name>TEIE</name>
5298 
              <description>Transfer error interrupt
5299 
              enable</description>
5300 
              <bitOffset>3</bitOffset>
5301 
              <bitWidth>1</bitWidth>
5302 
            </field>
5303 
            <field>
5304 
              <name>DIR</name>
5305 
              <description>Data transfer direction</description>
5306 
              <bitOffset>4</bitOffset>
5307 
              <bitWidth>1</bitWidth>
5308 
            </field>
5309 
            <field>
5310 
              <name>CIRC</name>
5311 
              <description>Circular mode</description>
5312 
              <bitOffset>5</bitOffset>
5313 
              <bitWidth>1</bitWidth>
5314 
            </field>
5315 
            <field>
5316 
              <name>PINC</name>
5317 
              <description>Peripheral increment mode</description>
5318 
              <bitOffset>6</bitOffset>
5319 
              <bitWidth>1</bitWidth>
5320 
            </field>
5321 
            <field>
5322 
              <name>MINC</name>
5323 
              <description>Memory increment mode</description>
5324 
              <bitOffset>7</bitOffset>
5325 
              <bitWidth>1</bitWidth>
5326 
            </field>
5327 
            <field>
5328 
              <name>PSIZE</name>
5329 
              <description>Peripheral size</description>
5330 
              <bitOffset>8</bitOffset>
5331 
              <bitWidth>2</bitWidth>
5332 
            </field>
5333 
            <field>
5334 
              <name>MSIZE</name>
5335 
              <description>Memory size</description>
5336 
              <bitOffset>10</bitOffset>
5337 
              <bitWidth>2</bitWidth>
5338 
            </field>
5339 
            <field>
5340 
              <name>PL</name>
5341 
              <description>Channel Priority level</description>
5342 
              <bitOffset>12</bitOffset>
5343 
              <bitWidth>2</bitWidth>
5344 
            </field>
5345 
            <field>
5346 
              <name>MEM2MEM</name>
5347 
              <description>Memory to memory mode</description>
5348 
              <bitOffset>14</bitOffset>
5349 
              <bitWidth>1</bitWidth>
5350 
            </field>
5351 
          </fields>
5352 
        </register>
5353 
        <register>
5354 
          <name>CNDTR1</name>
5355 
          <displayName>CNDTR1</displayName>
5356 
          <description>DMA channel 1 number of data
5357 
          register</description>
5358 
          <addressOffset>0xC</addressOffset>
5359 
          <size>0x20</size>
5360 
          <access>read-write</access>
5361 
          <resetValue>0x00000000</resetValue>
5362 
          <fields>
5363 
            <field>
5364 
              <name>NDT</name>
5365 
              <description>Number of data to transfer</description>
5366 
              <bitOffset>0</bitOffset>
5367 
              <bitWidth>16</bitWidth>
5368 
            </field>
5369 
          </fields>
5370 
        </register>
5371 
        <register>
5372 
          <name>CPAR1</name>
5373 
          <displayName>CPAR1</displayName>
5374 
          <description>DMA channel 1 peripheral address
5375 
          register</description>
5376 
          <addressOffset>0x10</addressOffset>
5377 
          <size>0x20</size>
5378 
          <access>read-write</access>
5379 
          <resetValue>0x00000000</resetValue>
5380 
          <fields>
5381 
            <field>
5382 
              <name>PA</name>
5383 
              <description>Peripheral address</description>
5384 
              <bitOffset>0</bitOffset>
5385 
              <bitWidth>32</bitWidth>
5386 
            </field>
5387 
          </fields>
5388 
        </register>
5389 
        <register>
5390 
          <name>CMAR1</name>
5391 
          <displayName>CMAR1</displayName>
5392 
          <description>DMA channel 1 memory address
5393 
          register</description>
5394 
          <addressOffset>0x14</addressOffset>
5395 
          <size>0x20</size>
5396 
          <access>read-write</access>
5397 
          <resetValue>0x00000000</resetValue>
5398 
          <fields>
5399 
            <field>
5400 
              <name>MA</name>
5401 
              <description>Memory address</description>
5402 
              <bitOffset>0</bitOffset>
5403 
              <bitWidth>32</bitWidth>
5404 
            </field>
5405 
          </fields>
5406 
        </register>
5407 
        <register>
5408 
          <name>CCR2</name>
5409 
          <displayName>CCR2</displayName>
5410 
          <description>DMA channel configuration register
5411 
          (DMA_CCR)</description>
5412 
          <addressOffset>0x1C</addressOffset>
5413 
          <size>0x20</size>
5414 
          <access>read-write</access>
5415 
          <resetValue>0x00000000</resetValue>
5416 
          <fields>
5417 
            <field>
5418 
              <name>EN</name>
5419 
              <description>Channel enable</description>
5420 
              <bitOffset>0</bitOffset>
5421 
              <bitWidth>1</bitWidth>
5422 
            </field>
5423 
            <field>
5424 
              <name>TCIE</name>
5425 
              <description>Transfer complete interrupt
5426 
              enable</description>
5427 
              <bitOffset>1</bitOffset>
5428 
              <bitWidth>1</bitWidth>
5429 
            </field>
5430 
            <field>
5431 
              <name>HTIE</name>
5432 
              <description>Half Transfer interrupt
5433 
              enable</description>
5434 
              <bitOffset>2</bitOffset>
5435 
              <bitWidth>1</bitWidth>
5436 
            </field>
5437 
            <field>
5438 
              <name>TEIE</name>
5439 
              <description>Transfer error interrupt
5440 
              enable</description>
5441 
              <bitOffset>3</bitOffset>
5442 
              <bitWidth>1</bitWidth>
5443 
            </field>
5444 
            <field>
5445 
              <name>DIR</name>
5446 
              <description>Data transfer direction</description>
5447 
              <bitOffset>4</bitOffset>
5448 
              <bitWidth>1</bitWidth>
5449 
            </field>
5450 
            <field>
5451 
              <name>CIRC</name>
5452 
              <description>Circular mode</description>
5453 
              <bitOffset>5</bitOffset>
5454 
              <bitWidth>1</bitWidth>
5455 
            </field>
5456 
            <field>
5457 
              <name>PINC</name>
5458 
              <description>Peripheral increment mode</description>
5459 
              <bitOffset>6</bitOffset>
5460 
              <bitWidth>1</bitWidth>
5461 
            </field>
5462 
            <field>
5463 
              <name>MINC</name>
5464 
              <description>Memory increment mode</description>
5465 
              <bitOffset>7</bitOffset>
5466 
              <bitWidth>1</bitWidth>
5467 
            </field>
5468 
            <field>
5469 
              <name>PSIZE</name>
5470 
              <description>Peripheral size</description>
5471 
              <bitOffset>8</bitOffset>
5472 
              <bitWidth>2</bitWidth>
5473 
            </field>
5474 
            <field>
5475 
              <name>MSIZE</name>
5476 
              <description>Memory size</description>
5477 
              <bitOffset>10</bitOffset>
5478 
              <bitWidth>2</bitWidth>
5479 
            </field>
5480 
            <field>
5481 
              <name>PL</name>
5482 
              <description>Channel Priority level</description>
5483 
              <bitOffset>12</bitOffset>
5484 
              <bitWidth>2</bitWidth>
5485 
            </field>
5486 
            <field>
5487 
              <name>MEM2MEM</name>
5488 
              <description>Memory to memory mode</description>
5489 
              <bitOffset>14</bitOffset>
5490 
              <bitWidth>1</bitWidth>
5491 
            </field>
5492 
          </fields>
5493 
        </register>
5494 
        <register>
5495 
          <name>CNDTR2</name>
5496 
          <displayName>CNDTR2</displayName>
5497 
          <description>DMA channel 2 number of data
5498 
          register</description>
5499 
          <addressOffset>0x20</addressOffset>
5500 
          <size>0x20</size>
5501 
          <access>read-write</access>
5502 
          <resetValue>0x00000000</resetValue>
5503 
          <fields>
5504 
            <field>
5505 
              <name>NDT</name>
5506 
              <description>Number of data to transfer</description>
5507 
              <bitOffset>0</bitOffset>
5508 
              <bitWidth>16</bitWidth>
5509 
            </field>
5510 
          </fields>
5511 
        </register>
5512 
        <register>
5513 
          <name>CPAR2</name>
5514 
          <displayName>CPAR2</displayName>
5515 
          <description>DMA channel 2 peripheral address
5516 
          register</description>
5517 
          <addressOffset>0x24</addressOffset>
5518 
          <size>0x20</size>
5519 
          <access>read-write</access>
5520 
          <resetValue>0x00000000</resetValue>
5521 
          <fields>
5522 
            <field>
5523 
              <name>PA</name>
5524 
              <description>Peripheral address</description>
5525 
              <bitOffset>0</bitOffset>
5526 
              <bitWidth>32</bitWidth>
5527 
            </field>
5528 
          </fields>
5529 
        </register>
5530 
        <register>
5531 
          <name>CMAR2</name>
5532 
          <displayName>CMAR2</displayName>
5533 
          <description>DMA channel 2 memory address
5534 
          register</description>
5535 
          <addressOffset>0x28</addressOffset>
5536 
          <size>0x20</size>
5537 
          <access>read-write</access>
5538 
          <resetValue>0x00000000</resetValue>
5539 
          <fields>
5540 
            <field>
5541 
              <name>MA</name>
5542 
              <description>Memory address</description>
5543 
              <bitOffset>0</bitOffset>
5544 
              <bitWidth>32</bitWidth>
5545 
            </field>
5546 
          </fields>
5547 
        </register>
5548 
        <register>
5549 
          <name>CCR3</name>
5550 
          <displayName>CCR3</displayName>
5551 
          <description>DMA channel configuration register
5552 
          (DMA_CCR)</description>
5553 
          <addressOffset>0x30</addressOffset>
5554 
          <size>0x20</size>
5555 
          <access>read-write</access>
5556 
          <resetValue>0x00000000</resetValue>
5557 
          <fields>
5558 
            <field>
5559 
              <name>EN</name>
5560 
              <description>Channel enable</description>
5561 
              <bitOffset>0</bitOffset>
5562 
              <bitWidth>1</bitWidth>
5563 
            </field>
5564 
            <field>
5565 
              <name>TCIE</name>
5566 
              <description>Transfer complete interrupt
5567 
              enable</description>
5568 
              <bitOffset>1</bitOffset>
5569 
              <bitWidth>1</bitWidth>
5570 
            </field>
5571 
            <field>
5572 
              <name>HTIE</name>
5573 
              <description>Half Transfer interrupt
5574 
              enable</description>
5575 
              <bitOffset>2</bitOffset>
5576 
              <bitWidth>1</bitWidth>
5577 
            </field>
5578 
            <field>
5579 
              <name>TEIE</name>
5580 
              <description>Transfer error interrupt
5581 
              enable</description>
5582 
              <bitOffset>3</bitOffset>
5583 
              <bitWidth>1</bitWidth>
5584 
            </field>
5585 
            <field>
5586 
              <name>DIR</name>
5587 
              <description>Data transfer direction</description>
5588 
              <bitOffset>4</bitOffset>
5589 
              <bitWidth>1</bitWidth>
5590 
            </field>
5591 
            <field>
5592 
              <name>CIRC</name>
5593 
              <description>Circular mode</description>
5594 
              <bitOffset>5</bitOffset>
5595 
              <bitWidth>1</bitWidth>
5596 
            </field>
5597 
            <field>
5598 
              <name>PINC</name>
5599 
              <description>Peripheral increment mode</description>
5600 
              <bitOffset>6</bitOffset>
5601 
              <bitWidth>1</bitWidth>
5602 
            </field>
5603 
            <field>
5604 
              <name>MINC</name>
5605 
              <description>Memory increment mode</description>
5606 
              <bitOffset>7</bitOffset>
5607 
              <bitWidth>1</bitWidth>
5608 
            </field>
5609 
            <field>
5610 
              <name>PSIZE</name>
5611 
              <description>Peripheral size</description>
5612 
              <bitOffset>8</bitOffset>
5613 
              <bitWidth>2</bitWidth>
5614 
            </field>
5615 
            <field>
5616 
              <name>MSIZE</name>
5617 
              <description>Memory size</description>
5618 
              <bitOffset>10</bitOffset>
5619 
              <bitWidth>2</bitWidth>
5620 
            </field>
5621 
            <field>
5622 
              <name>PL</name>
5623 
              <description>Channel Priority level</description>
5624 
              <bitOffset>12</bitOffset>
5625 
              <bitWidth>2</bitWidth>
5626 
            </field>
5627 
            <field>
5628 
              <name>MEM2MEM</name>
5629 
              <description>Memory to memory mode</description>
5630 
              <bitOffset>14</bitOffset>
5631 
              <bitWidth>1</bitWidth>
5632 
            </field>
5633 
          </fields>
5634 
        </register>
5635 
        <register>
5636 
          <name>CNDTR3</name>
5637 
          <displayName>CNDTR3</displayName>
5638 
          <description>DMA channel 3 number of data
5639 
          register</description>
5640 
          <addressOffset>0x34</addressOffset>
5641 
          <size>0x20</size>
5642 
          <access>read-write</access>
5643 
          <resetValue>0x00000000</resetValue>
5644 
          <fields>
5645 
            <field>
5646 
              <name>NDT</name>
5647 
              <description>Number of data to transfer</description>
5648 
              <bitOffset>0</bitOffset>
5649 
              <bitWidth>16</bitWidth>
5650 
            </field>
5651 
          </fields>
5652 
        </register>
5653 
        <register>
5654 
          <name>CPAR3</name>
5655 
          <displayName>CPAR3</displayName>
5656 
          <description>DMA channel 3 peripheral address
5657 
          register</description>
5658 
          <addressOffset>0x38</addressOffset>
5659 
          <size>0x20</size>
5660 
          <access>read-write</access>
5661 
          <resetValue>0x00000000</resetValue>
5662 
          <fields>
5663 
            <field>
5664 
              <name>PA</name>
5665 
              <description>Peripheral address</description>
5666 
              <bitOffset>0</bitOffset>
5667 
              <bitWidth>32</bitWidth>
5668 
            </field>
5669 
          </fields>
5670 
        </register>
5671 
        <register>
5672 
          <name>CMAR3</name>
5673 
          <displayName>CMAR3</displayName>
5674 
          <description>DMA channel 3 memory address
5675 
          register</description>
5676 
          <addressOffset>0x3C</addressOffset>
5677 
          <size>0x20</size>
5678 
          <access>read-write</access>
5679 
          <resetValue>0x00000000</resetValue>
5680 
          <fields>
5681 
            <field>
5682 
              <name>MA</name>
5683 
              <description>Memory address</description>
5684 
              <bitOffset>0</bitOffset>
5685 
              <bitWidth>32</bitWidth>
5686 
            </field>
5687 
          </fields>
5688 
        </register>
5689 
        <register>
5690 
          <name>CCR4</name>
5691 
          <displayName>CCR4</displayName>
5692 
          <description>DMA channel configuration register
5693 
          (DMA_CCR)</description>
5694 
          <addressOffset>0x44</addressOffset>
5695 
          <size>0x20</size>
5696 
          <access>read-write</access>
5697 
          <resetValue>0x00000000</resetValue>
5698 
          <fields>
5699 
            <field>
5700 
              <name>EN</name>
5701 
              <description>Channel enable</description>
5702 
              <bitOffset>0</bitOffset>
5703 
              <bitWidth>1</bitWidth>
5704 
            </field>
5705 
            <field>
5706 
              <name>TCIE</name>
5707 
              <description>Transfer complete interrupt
5708 
              enable</description>
5709 
              <bitOffset>1</bitOffset>
5710 
              <bitWidth>1</bitWidth>
5711 
            </field>
5712 
            <field>
5713 
              <name>HTIE</name>
5714 
              <description>Half Transfer interrupt
5715 
              enable</description>
5716 
              <bitOffset>2</bitOffset>
5717 
              <bitWidth>1</bitWidth>
5718 
            </field>
5719 
            <field>
5720 
              <name>TEIE</name>
5721 
              <description>Transfer error interrupt
5722 
              enable</description>
5723 
              <bitOffset>3</bitOffset>
5724 
              <bitWidth>1</bitWidth>
5725 
            </field>
5726 
            <field>
5727 
              <name>DIR</name>
5728 
              <description>Data transfer direction</description>
5729 
              <bitOffset>4</bitOffset>
5730 
              <bitWidth>1</bitWidth>
5731 
            </field>
5732 
            <field>
5733 
              <name>CIRC</name>
5734 
              <description>Circular mode</description>
5735 
              <bitOffset>5</bitOffset>
5736 
              <bitWidth>1</bitWidth>
5737 
            </field>
5738 
            <field>
5739 
              <name>PINC</name>
5740 
              <description>Peripheral increment mode</description>
5741 
              <bitOffset>6</bitOffset>
5742 
              <bitWidth>1</bitWidth>
5743 
            </field>
5744 
            <field>
5745 
              <name>MINC</name>
5746 
              <description>Memory increment mode</description>
5747 
              <bitOffset>7</bitOffset>
5748 
              <bitWidth>1</bitWidth>
5749 
            </field>
5750 
            <field>
5751 
              <name>PSIZE</name>
5752 
              <description>Peripheral size</description>
5753 
              <bitOffset>8</bitOffset>
5754 
              <bitWidth>2</bitWidth>
5755 
            </field>
5756 
            <field>
5757 
              <name>MSIZE</name>
5758 
              <description>Memory size</description>
5759 
              <bitOffset>10</bitOffset>
5760 
              <bitWidth>2</bitWidth>
5761 
            </field>
5762 
            <field>
5763 
              <name>PL</name>
5764 
              <description>Channel Priority level</description>
5765 
              <bitOffset>12</bitOffset>
5766 
              <bitWidth>2</bitWidth>
5767 
            </field>
5768 
            <field>
5769 
              <name>MEM2MEM</name>
5770 
              <description>Memory to memory mode</description>
5771 
              <bitOffset>14</bitOffset>
5772 
              <bitWidth>1</bitWidth>
5773 
            </field>
5774 
          </fields>
5775 
        </register>
5776 
        <register>
5777 
          <name>CNDTR4</name>
5778 
          <displayName>CNDTR4</displayName>
5779 
          <description>DMA channel 4 number of data
5780 
          register</description>
5781 
          <addressOffset>0x48</addressOffset>
5782 
          <size>0x20</size>
5783 
          <access>read-write</access>
5784 
          <resetValue>0x00000000</resetValue>
5785 
          <fields>
5786 
            <field>
5787 
              <name>NDT</name>
5788 
              <description>Number of data to transfer</description>
5789 
              <bitOffset>0</bitOffset>
5790 
              <bitWidth>16</bitWidth>
5791 
            </field>
5792 
          </fields>
5793 
        </register>
5794 
        <register>
5795 
          <name>CPAR4</name>
5796 
          <displayName>CPAR4</displayName>
5797 
          <description>DMA channel 4 peripheral address
5798 
          register</description>
5799 
          <addressOffset>0x4C</addressOffset>
5800 
          <size>0x20</size>
5801 
          <access>read-write</access>
5802 
          <resetValue>0x00000000</resetValue>
5803 
          <fields>
5804 
            <field>
5805 
              <name>PA</name>
5806 
              <description>Peripheral address</description>
5807 
              <bitOffset>0</bitOffset>
5808 
              <bitWidth>32</bitWidth>
5809 
            </field>
5810 
          </fields>
5811 
        </register>
5812 
        <register>
5813 
          <name>CMAR4</name>
5814 
          <displayName>CMAR4</displayName>
5815 
          <description>DMA channel 4 memory address
5816 
          register</description>
5817 
          <addressOffset>0x50</addressOffset>
5818 
          <size>0x20</size>
5819 
          <access>read-write</access>
5820 
          <resetValue>0x00000000</resetValue>
5821 
          <fields>
5822 
            <field>
5823 
              <name>MA</name>
5824 
              <description>Memory address</description>
5825 
              <bitOffset>0</bitOffset>
5826 
              <bitWidth>32</bitWidth>
5827 
            </field>
5828 
          </fields>
5829 
        </register>
5830 
        <register>
5831 
          <name>CCR5</name>
5832 
          <displayName>CCR5</displayName>
5833 
          <description>DMA channel configuration register
5834 
          (DMA_CCR)</description>
5835 
          <addressOffset>0x58</addressOffset>
5836 
          <size>0x20</size>
5837 
          <access>read-write</access>
5838 
          <resetValue>0x00000000</resetValue>
5839 
          <fields>
5840 
            <field>
5841 
              <name>EN</name>
5842 
              <description>Channel enable</description>
5843 
              <bitOffset>0</bitOffset>
5844 
              <bitWidth>1</bitWidth>
5845 
            </field>
5846 
            <field>
5847 
              <name>TCIE</name>
5848 
              <description>Transfer complete interrupt
5849 
              enable</description>
5850 
              <bitOffset>1</bitOffset>
5851 
              <bitWidth>1</bitWidth>
5852 
            </field>
5853 
            <field>
5854 
              <name>HTIE</name>
5855 
              <description>Half Transfer interrupt
5856 
              enable</description>
5857 
              <bitOffset>2</bitOffset>
5858 
              <bitWidth>1</bitWidth>
5859 
            </field>
5860 
            <field>
5861 
              <name>TEIE</name>
5862 
              <description>Transfer error interrupt
5863 
              enable</description>
5864 
              <bitOffset>3</bitOffset>
5865 
              <bitWidth>1</bitWidth>
5866 
            </field>
5867 
            <field>
5868 
              <name>DIR</name>
5869 
              <description>Data transfer direction</description>
5870 
              <bitOffset>4</bitOffset>
5871 
              <bitWidth>1</bitWidth>
5872 
            </field>
5873 
            <field>
5874 
              <name>CIRC</name>
5875 
              <description>Circular mode</description>
5876 
              <bitOffset>5</bitOffset>
5877 
              <bitWidth>1</bitWidth>
5878 
            </field>
5879 
            <field>
5880 
              <name>PINC</name>
5881 
              <description>Peripheral increment mode</description>
5882 
              <bitOffset>6</bitOffset>
5883 
              <bitWidth>1</bitWidth>
5884 
            </field>
5885 
            <field>
5886 
              <name>MINC</name>
5887 
              <description>Memory increment mode</description>
5888 
              <bitOffset>7</bitOffset>
5889 
              <bitWidth>1</bitWidth>
5890 
            </field>
5891 
            <field>
5892 
              <name>PSIZE</name>
5893 
              <description>Peripheral size</description>
5894 
              <bitOffset>8</bitOffset>
5895 
              <bitWidth>2</bitWidth>
5896 
            </field>
5897 
            <field>
5898 
              <name>MSIZE</name>
5899 
              <description>Memory size</description>
5900 
              <bitOffset>10</bitOffset>
5901 
              <bitWidth>2</bitWidth>
5902 
            </field>
5903 
            <field>
5904 
              <name>PL</name>
5905 
              <description>Channel Priority level</description>
5906 
              <bitOffset>12</bitOffset>
5907 
              <bitWidth>2</bitWidth>
5908 
            </field>
5909 
            <field>
5910 
              <name>MEM2MEM</name>
5911 
              <description>Memory to memory mode</description>
5912 
              <bitOffset>14</bitOffset>
5913 
              <bitWidth>1</bitWidth>
5914 
            </field>
5915 
          </fields>
5916 
        </register>
5917 
        <register>
5918 
          <name>CNDTR5</name>
5919 
          <displayName>CNDTR5</displayName>
5920 
          <description>DMA channel 5 number of data
5921 
          register</description>
5922 
          <addressOffset>0x5C</addressOffset>
5923 
          <size>0x20</size>
5924 
          <access>read-write</access>
5925 
          <resetValue>0x00000000</resetValue>
5926 
          <fields>
5927 
            <field>
5928 
              <name>NDT</name>
5929 
              <description>Number of data to transfer</description>
5930 
              <bitOffset>0</bitOffset>
5931 
              <bitWidth>16</bitWidth>
5932 
            </field>
5933 
          </fields>
5934 
        </register>
5935 
        <register>
5936 
          <name>CPAR5</name>
5937 
          <displayName>CPAR5</displayName>
5938 
          <description>DMA channel 5 peripheral address
5939 
          register</description>
5940 
          <addressOffset>0x60</addressOffset>
5941 
          <size>0x20</size>
5942 
          <access>read-write</access>
5943 
          <resetValue>0x00000000</resetValue>
5944 
          <fields>
5945 
            <field>
5946 
              <name>PA</name>
5947 
              <description>Peripheral address</description>
5948 
              <bitOffset>0</bitOffset>
5949 
              <bitWidth>32</bitWidth>
5950 
            </field>
5951 
          </fields>
5952 
        </register>
5953 
        <register>
5954 
          <name>CMAR5</name>
5955 
          <displayName>CMAR5</displayName>
5956 
          <description>DMA channel 5 memory address
5957 
          register</description>
5958 
          <addressOffset>0x64</addressOffset>
5959 
          <size>0x20</size>
5960 
          <access>read-write</access>
5961 
          <resetValue>0x00000000</resetValue>
5962 
          <fields>
5963 
            <field>
5964 
              <name>MA</name>
5965 
              <description>Memory address</description>
5966 
              <bitOffset>0</bitOffset>
5967 
              <bitWidth>32</bitWidth>
5968 
            </field>
5969 
          </fields>
5970 
        </register>
5971 
        <register>
5972 
          <name>CCR6</name>
5973 
          <displayName>CCR6</displayName>
5974 
          <description>DMA channel configuration register
5975 
          (DMA_CCR)</description>
5976 
          <addressOffset>0x6C</addressOffset>
5977 
          <size>0x20</size>
5978 
          <access>read-write</access>
5979 
          <resetValue>0x00000000</resetValue>
5980 
          <fields>
5981 
            <field>
5982 
              <name>EN</name>
5983 
              <description>Channel enable</description>
5984 
              <bitOffset>0</bitOffset>
5985 
              <bitWidth>1</bitWidth>
5986 
            </field>
5987 
            <field>
5988 
              <name>TCIE</name>
5989 
              <description>Transfer complete interrupt
5990 
              enable</description>
5991 
              <bitOffset>1</bitOffset>
5992 
              <bitWidth>1</bitWidth>
5993 
            </field>
5994 
            <field>
5995 
              <name>HTIE</name>
5996 
              <description>Half Transfer interrupt
5997 
              enable</description>
5998 
              <bitOffset>2</bitOffset>
5999 
              <bitWidth>1</bitWidth>
6000 
            </field>
6001 
            <field>
6002 
              <name>TEIE</name>
6003 
              <description>Transfer error interrupt
6004 
              enable</description>
6005 
              <bitOffset>3</bitOffset>
6006 
              <bitWidth>1</bitWidth>
6007 
            </field>
6008 
            <field>
6009 
              <name>DIR</name>
6010 
              <description>Data transfer direction</description>
6011 
              <bitOffset>4</bitOffset>
6012 
              <bitWidth>1</bitWidth>
6013 
            </field>
6014 
            <field>
6015 
              <name>CIRC</name>
6016 
              <description>Circular mode</description>
6017 
              <bitOffset>5</bitOffset>
6018 
              <bitWidth>1</bitWidth>
6019 
            </field>
6020 
            <field>
6021 
              <name>PINC</name>
6022 
              <description>Peripheral increment mode</description>
6023 
              <bitOffset>6</bitOffset>
6024 
              <bitWidth>1</bitWidth>
6025 
            </field>
6026 
            <field>
6027 
              <name>MINC</name>
6028 
              <description>Memory increment mode</description>
6029 
              <bitOffset>7</bitOffset>
6030 
              <bitWidth>1</bitWidth>
6031 
            </field>
6032 
            <field>
6033 
              <name>PSIZE</name>
6034 
              <description>Peripheral size</description>
6035 
              <bitOffset>8</bitOffset>
6036 
              <bitWidth>2</bitWidth>
6037 
            </field>
6038 
            <field>
6039 
              <name>MSIZE</name>
6040 
              <description>Memory size</description>
6041 
              <bitOffset>10</bitOffset>
6042 
              <bitWidth>2</bitWidth>
6043 
            </field>
6044 
            <field>
6045 
              <name>PL</name>
6046 
              <description>Channel Priority level</description>
6047 
              <bitOffset>12</bitOffset>
6048 
              <bitWidth>2</bitWidth>
6049 
            </field>
6050 
            <field>
6051 
              <name>MEM2MEM</name>
6052 
              <description>Memory to memory mode</description>
6053 
              <bitOffset>14</bitOffset>
6054 
              <bitWidth>1</bitWidth>
6055 
            </field>
6056 
          </fields>
6057 
        </register>
6058 
        <register>
6059 
          <name>CNDTR6</name>
6060 
          <displayName>CNDTR6</displayName>
6061 
          <description>DMA channel 6 number of data
6062 
          register</description>
6063 
          <addressOffset>0x70</addressOffset>
6064 
          <size>0x20</size>
6065 
          <access>read-write</access>
6066 
          <resetValue>0x00000000</resetValue>
6067 
          <fields>
6068 
            <field>
6069 
              <name>NDT</name>
6070 
              <description>Number of data to transfer</description>
6071 
              <bitOffset>0</bitOffset>
6072 
              <bitWidth>16</bitWidth>
6073 
            </field>
6074 
          </fields>
6075 
        </register>
6076 
        <register>
6077 
          <name>CPAR6</name>
6078 
          <displayName>CPAR6</displayName>
6079 
          <description>DMA channel 6 peripheral address
6080 
          register</description>
6081 
          <addressOffset>0x74</addressOffset>
6082 
          <size>0x20</size>
6083 
          <access>read-write</access>
6084 
          <resetValue>0x00000000</resetValue>
6085 
          <fields>
6086 
            <field>
6087 
              <name>PA</name>
6088 
              <description>Peripheral address</description>
6089 
              <bitOffset>0</bitOffset>
6090 
              <bitWidth>32</bitWidth>
6091 
            </field>
6092 
          </fields>
6093 
        </register>
6094 
        <register>
6095 
          <name>CMAR6</name>
6096 
          <displayName>CMAR6</displayName>
6097 
          <description>DMA channel 6 memory address
6098 
          register</description>
6099 
          <addressOffset>0x78</addressOffset>
6100 
          <size>0x20</size>
6101 
          <access>read-write</access>
6102 
          <resetValue>0x00000000</resetValue>
6103 
          <fields>
6104 
            <field>
6105 
              <name>MA</name>
6106 
              <description>Memory address</description>
6107 
              <bitOffset>0</bitOffset>
6108 
              <bitWidth>32</bitWidth>
6109 
            </field>
6110 
          </fields>
6111 
        </register>
6112 
        <register>
6113 
          <name>CCR7</name>
6114 
          <displayName>CCR7</displayName>
6115 
          <description>DMA channel configuration register
6116 
          (DMA_CCR)</description>
6117 
          <addressOffset>0x80</addressOffset>
6118 
          <size>0x20</size>
6119 
          <access>read-write</access>
6120 
          <resetValue>0x00000000</resetValue>
6121 
          <fields>
6122 
            <field>
6123 
              <name>EN</name>
6124 
              <description>Channel enable</description>
6125 
              <bitOffset>0</bitOffset>
6126 
              <bitWidth>1</bitWidth>
6127 
            </field>
6128 
            <field>
6129 
              <name>TCIE</name>
6130 
              <description>Transfer complete interrupt
6131 
              enable</description>
6132 
              <bitOffset>1</bitOffset>
6133 
              <bitWidth>1</bitWidth>
6134 
            </field>
6135 
            <field>
6136 
              <name>HTIE</name>
6137 
              <description>Half Transfer interrupt
6138 
              enable</description>
6139 
              <bitOffset>2</bitOffset>
6140 
              <bitWidth>1</bitWidth>
6141 
            </field>
6142 
            <field>
6143 
              <name>TEIE</name>
6144 
              <description>Transfer error interrupt
6145 
              enable</description>
6146 
              <bitOffset>3</bitOffset>
6147 
              <bitWidth>1</bitWidth>
6148 
            </field>
6149 
            <field>
6150 
              <name>DIR</name>
6151 
              <description>Data transfer direction</description>
6152 
              <bitOffset>4</bitOffset>
6153 
              <bitWidth>1</bitWidth>
6154 
            </field>
6155 
            <field>
6156 
              <name>CIRC</name>
6157 
              <description>Circular mode</description>
6158 
              <bitOffset>5</bitOffset>
6159 
              <bitWidth>1</bitWidth>
6160 
            </field>
6161 
            <field>
6162 
              <name>PINC</name>
6163 
              <description>Peripheral increment mode</description>
6164 
              <bitOffset>6</bitOffset>
6165 
              <bitWidth>1</bitWidth>
6166 
            </field>
6167 
            <field>
6168 
              <name>MINC</name>
6169 
              <description>Memory increment mode</description>
6170 
              <bitOffset>7</bitOffset>
6171 
              <bitWidth>1</bitWidth>
6172 
            </field>
6173 
            <field>
6174 
              <name>PSIZE</name>
6175 
              <description>Peripheral size</description>
6176 
              <bitOffset>8</bitOffset>
6177 
              <bitWidth>2</bitWidth>
6178 
            </field>
6179 
            <field>
6180 
              <name>MSIZE</name>
6181 
              <description>Memory size</description>
6182 
              <bitOffset>10</bitOffset>
6183 
              <bitWidth>2</bitWidth>
6184 
            </field>
6185 
            <field>
6186 
              <name>PL</name>
6187 
              <description>Channel Priority level</description>
6188 
              <bitOffset>12</bitOffset>
6189 
              <bitWidth>2</bitWidth>
6190 
            </field>
6191 
            <field>
6192 
              <name>MEM2MEM</name>
6193 
              <description>Memory to memory mode</description>
6194 
              <bitOffset>14</bitOffset>
6195 
              <bitWidth>1</bitWidth>
6196 
            </field>
6197 
          </fields>
6198 
        </register>
6199 
        <register>
6200 
          <name>CNDTR7</name>
6201 
          <displayName>CNDTR7</displayName>
6202 
          <description>DMA channel 7 number of data
6203 
          register</description>
6204 
          <addressOffset>0x84</addressOffset>
6205 
          <size>0x20</size>
6206 
          <access>read-write</access>
6207 
          <resetValue>0x00000000</resetValue>
6208 
          <fields>
6209 
            <field>
6210 
              <name>NDT</name>
6211 
              <description>Number of data to transfer</description>
6212 
              <bitOffset>0</bitOffset>
6213 
              <bitWidth>16</bitWidth>
6214 
            </field>
6215 
          </fields>
6216 
        </register>
6217 
        <register>
6218 
          <name>CPAR7</name>
6219 
          <displayName>CPAR7</displayName>
6220 
          <description>DMA channel 7 peripheral address
6221 
          register</description>
6222 
          <addressOffset>0x88</addressOffset>
6223 
          <size>0x20</size>
6224 
          <access>read-write</access>
6225 
          <resetValue>0x00000000</resetValue>
6226 
          <fields>
6227 
            <field>
6228 
              <name>PA</name>
6229 
              <description>Peripheral address</description>
6230 
              <bitOffset>0</bitOffset>
6231 
              <bitWidth>32</bitWidth>
6232 
            </field>
6233 
          </fields>
6234 
        </register>
6235 
        <register>
6236 
          <name>CMAR7</name>
6237 
          <displayName>CMAR7</displayName>
6238 
          <description>DMA channel 7 memory address
6239 
          register</description>
6240 
          <addressOffset>0x8C</addressOffset>
6241 
          <size>0x20</size>
6242 
          <access>read-write</access>
6243 
          <resetValue>0x00000000</resetValue>
6244 
          <fields>
6245 
            <field>
6246 
              <name>MA</name>
6247 
              <description>Memory address</description>
6248 
              <bitOffset>0</bitOffset>
6249 
              <bitWidth>32</bitWidth>
6250 
            </field>
6251 
          </fields>
6252 
        </register>
6253 
      </registers>
6254 
    </peripheral>
6255 
    <peripheral derivedFrom="DMA1">
6256 
      <name>DMA2</name>
6257 
      <baseAddress>0x40020400</baseAddress>
6258 
      <interrupt>
6259 
        <name>DMA2_Channel1</name>
6260 
        <description>DMA2 Channel1 global interrupt</description>
6261 
        <value>56</value>
6262 
      </interrupt>
6263 
      <interrupt>
6264 
        <name>DMA2_Channel2</name>
6265 
        <description>DMA2 Channel2 global interrupt</description>
6266 
        <value>57</value>
6267 
      </interrupt>
6268 
      <interrupt>
6269 
        <name>DMA2_Channel3</name>
6270 
        <description>DMA2 Channel3 global interrupt</description>
6271 
        <value>58</value>
6272 
      </interrupt>
6273 
      <interrupt>
6274 
        <name>DMA2_Channel4_5</name>
6275 
        <description>DMA2 Channel4 and DMA2 Channel5 global
6276 
        interrupt</description>
6277 
        <value>59</value>
6278 
      </interrupt>
6279 
    </peripheral>
6280 
    <peripheral>
6281 
      <name>SDIO</name>
6282 
      <description>Secure digital input/output
6283 
      interface</description>
6284 
      <groupName>SDIO</groupName>
6285 
      <baseAddress>0x40018000</baseAddress>
6286 
      <addressBlock>
6287 
        <offset>0x0</offset>
6288 
        <size>0x400</size>
6289 
        <usage>registers</usage>
6290 
      </addressBlock>
6291 
      <interrupt>
6292 
        <name>SDIO</name>
6293 
        <description>SDIO global interrupt</description>
6294 
        <value>49</value>
6295 
      </interrupt>
6296 
      <registers>
6297 
        <register>
6298 
          <name>POWER</name>
6299 
          <displayName>POWER</displayName>
6300 
          <description>Bits 1:0 = PWRCTRL: Power supply control
6301 
          bits</description>
6302 
          <addressOffset>0x0</addressOffset>
6303 
          <size>0x20</size>
6304 
          <access>read-write</access>
6305 
          <resetValue>0x00000000</resetValue>
6306 
          <fields>
6307 
            <field>
6308 
              <name>PWRCTRL</name>
6309 
              <description>PWRCTRL</description>
6310 
              <bitOffset>0</bitOffset>
6311 
              <bitWidth>2</bitWidth>
6312 
            </field>
6313 
          </fields>
6314 
        </register>
6315 
        <register>
6316 
          <name>CLKCR</name>
6317 
          <displayName>CLKCR</displayName>
6318 
          <description>SDI clock control register
6319 
          (SDIO_CLKCR)</description>
6320 
          <addressOffset>0x4</addressOffset>
6321 
          <size>0x20</size>
6322 
          <access>read-write</access>
6323 
          <resetValue>0x00000000</resetValue>
6324 
          <fields>
6325 
            <field>
6326 
              <name>CLKDIV</name>
6327 
              <description>Clock divide factor</description>
6328 
              <bitOffset>0</bitOffset>
6329 
              <bitWidth>8</bitWidth>
6330 
            </field>
6331 
            <field>
6332 
              <name>CLKEN</name>
6333 
              <description>Clock enable bit</description>
6334 
              <bitOffset>8</bitOffset>
6335 
              <bitWidth>1</bitWidth>
6336 
            </field>
6337 
            <field>
6338 
              <name>PWRSAV</name>
6339 
              <description>Power saving configuration
6340 
              bit</description>
6341 
              <bitOffset>9</bitOffset>
6342 
              <bitWidth>1</bitWidth>
6343 
            </field>
6344 
            <field>
6345 
              <name>BYPASS</name>
6346 
              <description>Clock divider bypass enable
6347 
              bit</description>
6348 
              <bitOffset>10</bitOffset>
6349 
              <bitWidth>1</bitWidth>
6350 
            </field>
6351 
            <field>
6352 
              <name>WIDBUS</name>
6353 
              <description>Wide bus mode enable bit</description>
6354 
              <bitOffset>11</bitOffset>
6355 
              <bitWidth>2</bitWidth>
6356 
            </field>
6357 
            <field>
6358 
              <name>NEGEDGE</name>
6359 
              <description>SDIO_CK dephasing selection
6360 
              bit</description>
6361 
              <bitOffset>13</bitOffset>
6362 
              <bitWidth>1</bitWidth>
6363 
            </field>
6364 
            <field>
6365 
              <name>HWFC_EN</name>
6366 
              <description>HW Flow Control enable</description>
6367 
              <bitOffset>14</bitOffset>
6368 
              <bitWidth>1</bitWidth>
6369 
            </field>
6370 
          </fields>
6371 
        </register>
6372 
        <register>
6373 
          <name>ARG</name>
6374 
          <displayName>ARG</displayName>
6375 
          <description>Bits 31:0 = : Command argument</description>
6376 
          <addressOffset>0x8</addressOffset>
6377 
          <size>0x20</size>
6378 
          <access>read-write</access>
6379 
          <resetValue>0x00000000</resetValue>
6380 
          <fields>
6381 
            <field>
6382 
              <name>CMDARG</name>
6383 
              <description>Command argument</description>
6384 
              <bitOffset>0</bitOffset>
6385 
              <bitWidth>32</bitWidth>
6386 
            </field>
6387 
          </fields>
6388 
        </register>
6389 
        <register>
6390 
          <name>CMD</name>
6391 
          <displayName>CMD</displayName>
6392 
          <description>SDIO command register
6393 
          (SDIO_CMD)</description>
6394 
          <addressOffset>0xC</addressOffset>
6395 
          <size>0x20</size>
6396 
          <access>read-write</access>
6397 
          <resetValue>0x00000000</resetValue>
6398 
          <fields>
6399 
            <field>
6400 
              <name>CMDINDEX</name>
6401 
              <description>CMDINDEX</description>
6402 
              <bitOffset>0</bitOffset>
6403 
              <bitWidth>6</bitWidth>
6404 
            </field>
6405 
            <field>
6406 
              <name>WAITRESP</name>
6407 
              <description>WAITRESP</description>
6408 
              <bitOffset>6</bitOffset>
6409 
              <bitWidth>2</bitWidth>
6410 
            </field>
6411 
            <field>
6412 
              <name>WAITINT</name>
6413 
              <description>WAITINT</description>
6414 
              <bitOffset>8</bitOffset>
6415 
              <bitWidth>1</bitWidth>
6416 
            </field>
6417 
            <field>
6418 
              <name>WAITPEND</name>
6419 
              <description>WAITPEND</description>
6420 
              <bitOffset>9</bitOffset>
6421 
              <bitWidth>1</bitWidth>
6422 
            </field>
6423 
            <field>
6424 
              <name>CPSMEN</name>
6425 
              <description>CPSMEN</description>
6426 
              <bitOffset>10</bitOffset>
6427 
              <bitWidth>1</bitWidth>
6428 
            </field>
6429 
            <field>
6430 
              <name>SDIOSuspend</name>
6431 
              <description>SDIOSuspend</description>
6432 
              <bitOffset>11</bitOffset>
6433 
              <bitWidth>1</bitWidth>
6434 
            </field>
6435 
            <field>
6436 
              <name>ENCMDcompl</name>
6437 
              <description>ENCMDcompl</description>
6438 
              <bitOffset>12</bitOffset>
6439 
              <bitWidth>1</bitWidth>
6440 
            </field>
6441 
            <field>
6442 
              <name>nIEN</name>
6443 
              <description>nIEN</description>
6444 
              <bitOffset>13</bitOffset>
6445 
              <bitWidth>1</bitWidth>
6446 
            </field>
6447 
            <field>
6448 
              <name>CE_ATACMD</name>
6449 
              <description>CE_ATACMD</description>
6450 
              <bitOffset>14</bitOffset>
6451 
              <bitWidth>1</bitWidth>
6452 
            </field>
6453 
          </fields>
6454 
        </register>
6455 
        <register>
6456 
          <name>RESPCMD</name>
6457 
          <displayName>RESPCMD</displayName>
6458 
          <description>SDIO command register</description>
6459 
          <addressOffset>0x10</addressOffset>
6460 
          <size>0x20</size>
6461 
          <access>read-only</access>
6462 
          <resetValue>0x00000000</resetValue>
6463 
          <fields>
6464 
            <field>
6465 
              <name>RESPCMD</name>
6466 
              <description>RESPCMD</description>
6467 
              <bitOffset>0</bitOffset>
6468 
              <bitWidth>6</bitWidth>
6469 
            </field>
6470 
          </fields>
6471 
        </register>
6472 
        <register>
6473 
          <name>RESPI1</name>
6474 
          <displayName>RESPI1</displayName>
6475 
          <description>Bits 31:0 = CARDSTATUS1</description>
6476 
          <addressOffset>0x14</addressOffset>
6477 
          <size>0x20</size>
6478 
          <access>read-only</access>
6479 
          <resetValue>0x00000000</resetValue>
6480 
          <fields>
6481 
            <field>
6482 
              <name>CARDSTATUS1</name>
6483 
              <description>CARDSTATUS1</description>
6484 
              <bitOffset>0</bitOffset>
6485 
              <bitWidth>32</bitWidth>
6486 
            </field>
6487 
          </fields>
6488 
        </register>
6489 
        <register>
6490 
          <name>RESP2</name>
6491 
          <displayName>RESP2</displayName>
6492 
          <description>Bits 31:0 = CARDSTATUS2</description>
6493 
          <addressOffset>0x18</addressOffset>
6494 
          <size>0x20</size>
6495 
          <access>read-only</access>
6496 
          <resetValue>0x00000000</resetValue>
6497 
          <fields>
6498 
            <field>
6499 
              <name>CARDSTATUS2</name>
6500 
              <description>CARDSTATUS2</description>
6501 
              <bitOffset>0</bitOffset>
6502 
              <bitWidth>32</bitWidth>
6503 
            </field>
6504 
          </fields>
6505 
        </register>
6506 
        <register>
6507 
          <name>RESP3</name>
6508 
          <displayName>RESP3</displayName>
6509 
          <description>Bits 31:0 = CARDSTATUS3</description>
6510 
          <addressOffset>0x1C</addressOffset>
6511 
          <size>0x20</size>
6512 
          <access>read-only</access>
6513 
          <resetValue>0x00000000</resetValue>
6514 
          <fields>
6515 
            <field>
6516 
              <name>CARDSTATUS3</name>
6517 
              <description>CARDSTATUS3</description>
6518 
              <bitOffset>0</bitOffset>
6519 
              <bitWidth>32</bitWidth>
6520 
            </field>
6521 
          </fields>
6522 
        </register>
6523 
        <register>
6524 
          <name>RESP4</name>
6525 
          <displayName>RESP4</displayName>
6526 
          <description>Bits 31:0 = CARDSTATUS4</description>
6527 
          <addressOffset>0x20</addressOffset>
6528 
          <size>0x20</size>
6529 
          <access>read-only</access>
6530 
          <resetValue>0x00000000</resetValue>
6531 
          <fields>
6532 
            <field>
6533 
              <name>CARDSTATUS4</name>
6534 
              <description>CARDSTATUS4</description>
6535 
              <bitOffset>0</bitOffset>
6536 
              <bitWidth>32</bitWidth>
6537 
            </field>
6538 
          </fields>
6539 
        </register>
6540 
        <register>
6541 
          <name>DTIMER</name>
6542 
          <displayName>DTIMER</displayName>
6543 
          <description>Bits 31:0 = DATATIME: Data timeout
6544 
          period</description>
6545 
          <addressOffset>0x24</addressOffset>
6546 
          <size>0x20</size>
6547 
          <access>read-write</access>
6548 
          <resetValue>0x00000000</resetValue>
6549 
          <fields>
6550 
            <field>
6551 
              <name>DATATIME</name>
6552 
              <description>Data timeout period</description>
6553 
              <bitOffset>0</bitOffset>
6554 
              <bitWidth>32</bitWidth>
6555 
            </field>
6556 
          </fields>
6557 
        </register>
6558 
        <register>
6559 
          <name>DLEN</name>
6560 
          <displayName>DLEN</displayName>
6561 
          <description>Bits 24:0 = DATALENGTH: Data length
6562 
          value</description>
6563 
          <addressOffset>0x28</addressOffset>
6564 
          <size>0x20</size>
6565 
          <access>read-write</access>
6566 
          <resetValue>0x00000000</resetValue>
6567 
          <fields>
6568 
            <field>
6569 
              <name>DATALENGTH</name>
6570 
              <description>Data length value</description>
6571 
              <bitOffset>0</bitOffset>
6572 
              <bitWidth>25</bitWidth>
6573 
            </field>
6574 
          </fields>
6575 
        </register>
6576 
        <register>
6577 
          <name>DCTRL</name>
6578 
          <displayName>DCTRL</displayName>
6579 
          <description>SDIO data control register
6580 
          (SDIO_DCTRL)</description>
6581 
          <addressOffset>0x2C</addressOffset>
6582 
          <size>0x20</size>
6583 
          <access>read-write</access>
6584 
          <resetValue>0x00000000</resetValue>
6585 
          <fields>
6586 
            <field>
6587 
              <name>DTEN</name>
6588 
              <description>DTEN</description>
6589 
              <bitOffset>0</bitOffset>
6590 
              <bitWidth>1</bitWidth>
6591 
            </field>
6592 
            <field>
6593 
              <name>DTDIR</name>
6594 
              <description>DTDIR</description>
6595 
              <bitOffset>1</bitOffset>
6596 
              <bitWidth>1</bitWidth>
6597 
            </field>
6598 
            <field>
6599 
              <name>DTMODE</name>
6600 
              <description>DTMODE</description>
6601 
              <bitOffset>2</bitOffset>
6602 
              <bitWidth>1</bitWidth>
6603 
            </field>
6604 
            <field>
6605 
              <name>DMAEN</name>
6606 
              <description>DMAEN</description>
6607 
              <bitOffset>3</bitOffset>
6608 
              <bitWidth>1</bitWidth>
6609 
            </field>
6610 
            <field>
6611 
              <name>DBLOCKSIZE</name>
6612 
              <description>DBLOCKSIZE</description>
6613 
              <bitOffset>4</bitOffset>
6614 
              <bitWidth>4</bitWidth>
6615 
            </field>
6616 
            <field>
6617 
              <name>PWSTART</name>
6618 
              <description>PWSTART</description>
6619 
              <bitOffset>8</bitOffset>
6620 
              <bitWidth>1</bitWidth>
6621 
            </field>
6622 
            <field>
6623 
              <name>PWSTOP</name>
6624 
              <description>PWSTOP</description>
6625 
              <bitOffset>9</bitOffset>
6626 
              <bitWidth>1</bitWidth>
6627 
            </field>
6628 
            <field>
6629 
              <name>RWMOD</name>
6630 
              <description>RWMOD</description>
6631 
              <bitOffset>10</bitOffset>
6632 
              <bitWidth>1</bitWidth>
6633 
            </field>
6634 
            <field>
6635 
              <name>SDIOEN</name>
6636 
              <description>SDIOEN</description>
6637 
              <bitOffset>11</bitOffset>
6638 
              <bitWidth>1</bitWidth>
6639 
            </field>
6640 
          </fields>
6641 
        </register>
6642 
        <register>
6643 
          <name>DCOUNT</name>
6644 
          <displayName>DCOUNT</displayName>
6645 
          <description>Bits 24:0 = DATACOUNT: Data count
6646 
          value</description>
6647 
          <addressOffset>0x30</addressOffset>
6648 
          <size>0x20</size>
6649 
          <access>read-only</access>
6650 
          <resetValue>0x00000000</resetValue>
6651 
          <fields>
6652 
            <field>
6653 
              <name>DATACOUNT</name>
6654 
              <description>Data count value</description>
6655 
              <bitOffset>0</bitOffset>
6656 
              <bitWidth>25</bitWidth>
6657 
            </field>
6658 
          </fields>
6659 
        </register>
6660 
        <register>
6661 
          <name>STA</name>
6662 
          <displayName>STA</displayName>
6663 
          <description>SDIO status register
6664 
          (SDIO_STA)</description>
6665 
          <addressOffset>0x34</addressOffset>
6666 
          <size>0x20</size>
6667 
          <access>read-only</access>
6668 
          <resetValue>0x00000000</resetValue>
6669 
          <fields>
6670 
            <field>
6671 
              <name>CCRCFAIL</name>
6672 
              <description>CCRCFAIL</description>
6673 
              <bitOffset>0</bitOffset>
6674 
              <bitWidth>1</bitWidth>
6675 
            </field>
6676 
            <field>
6677 
              <name>DCRCFAIL</name>
6678 
              <description>DCRCFAIL</description>
6679 
              <bitOffset>1</bitOffset>
6680 
              <bitWidth>1</bitWidth>
6681 
            </field>
6682 
            <field>
6683 
              <name>CTIMEOUT</name>
6684 
              <description>CTIMEOUT</description>
6685 
              <bitOffset>2</bitOffset>
6686 
              <bitWidth>1</bitWidth>
6687 
            </field>
6688 
            <field>
6689 
              <name>DTIMEOUT</name>
6690 
              <description>DTIMEOUT</description>
6691 
              <bitOffset>3</bitOffset>
6692 
              <bitWidth>1</bitWidth>
6693 
            </field>
6694 
            <field>
6695 
              <name>TXUNDERR</name>
6696 
              <description>TXUNDERR</description>
6697 
              <bitOffset>4</bitOffset>
6698 
              <bitWidth>1</bitWidth>
6699 
            </field>
6700 
            <field>
6701 
              <name>RXOVERR</name>
6702 
              <description>RXOVERR</description>
6703 
              <bitOffset>5</bitOffset>
6704 
              <bitWidth>1</bitWidth>
6705 
            </field>
6706 
            <field>
6707 
              <name>CMDREND</name>
6708 
              <description>CMDREND</description>
6709 
              <bitOffset>6</bitOffset>
6710 
              <bitWidth>1</bitWidth>
6711 
            </field>
6712 
            <field>
6713 
              <name>CMDSENT</name>
6714 
              <description>CMDSENT</description>
6715 
              <bitOffset>7</bitOffset>
6716 
              <bitWidth>1</bitWidth>
6717 
            </field>
6718 
            <field>
6719 
              <name>DATAEND</name>
6720 
              <description>DATAEND</description>
6721 
              <bitOffset>8</bitOffset>
6722 
              <bitWidth>1</bitWidth>
6723 
            </field>
6724 
            <field>
6725 
              <name>STBITERR</name>
6726 
              <description>STBITERR</description>
6727 
              <bitOffset>9</bitOffset>
6728 
              <bitWidth>1</bitWidth>
6729 
            </field>
6730 
            <field>
6731 
              <name>DBCKEND</name>
6732 
              <description>DBCKEND</description>
6733 
              <bitOffset>10</bitOffset>
6734 
              <bitWidth>1</bitWidth>
6735 
            </field>
6736 
            <field>
6737 
              <name>CMDACT</name>
6738 
              <description>CMDACT</description>
6739 
              <bitOffset>11</bitOffset>
6740 
              <bitWidth>1</bitWidth>
6741 
            </field>
6742 
            <field>
6743 
              <name>TXACT</name>
6744 
              <description>TXACT</description>
6745 
              <bitOffset>12</bitOffset>
6746 
              <bitWidth>1</bitWidth>
6747 
            </field>
6748 
            <field>
6749 
              <name>RXACT</name>
6750 
              <description>RXACT</description>
6751 
              <bitOffset>13</bitOffset>
6752 
              <bitWidth>1</bitWidth>
6753 
            </field>
6754 
            <field>
6755 
              <name>TXFIFOHE</name>
6756 
              <description>TXFIFOHE</description>
6757 
              <bitOffset>14</bitOffset>
6758 
              <bitWidth>1</bitWidth>
6759 
            </field>
6760 
            <field>
6761 
              <name>RXFIFOHF</name>
6762 
              <description>RXFIFOHF</description>
6763 
              <bitOffset>15</bitOffset>
6764 
              <bitWidth>1</bitWidth>
6765 
            </field>
6766 
            <field>
6767 
              <name>TXFIFOF</name>
6768 
              <description>TXFIFOF</description>
6769 
              <bitOffset>16</bitOffset>
6770 
              <bitWidth>1</bitWidth>
6771 
            </field>
6772 
            <field>
6773 
              <name>RXFIFOF</name>
6774 
              <description>RXFIFOF</description>
6775 
              <bitOffset>17</bitOffset>
6776 
              <bitWidth>1</bitWidth>
6777 
            </field>
6778 
            <field>
6779 
              <name>TXFIFOE</name>
6780 
              <description>TXFIFOE</description>
6781 
              <bitOffset>18</bitOffset>
6782 
              <bitWidth>1</bitWidth>
6783 
            </field>
6784 
            <field>
6785 
              <name>RXFIFOE</name>
6786 
              <description>RXFIFOE</description>
6787 
              <bitOffset>19</bitOffset>
6788 
              <bitWidth>1</bitWidth>
6789 
            </field>
6790 
            <field>
6791 
              <name>TXDAVL</name>
6792 
              <description>TXDAVL</description>
6793 
              <bitOffset>20</bitOffset>
6794 
              <bitWidth>1</bitWidth>
6795 
            </field>
6796 
            <field>
6797 
              <name>RXDAVL</name>
6798 
              <description>RXDAVL</description>
6799 
              <bitOffset>21</bitOffset>
6800 
              <bitWidth>1</bitWidth>
6801 
            </field>
6802 
            <field>
6803 
              <name>SDIOIT</name>
6804 
              <description>SDIOIT</description>
6805 
              <bitOffset>22</bitOffset>
6806 
              <bitWidth>1</bitWidth>
6807 
            </field>
6808 
            <field>
6809 
              <name>CEATAEND</name>
6810 
              <description>CEATAEND</description>
6811 
              <bitOffset>23</bitOffset>
6812 
              <bitWidth>1</bitWidth>
6813 
            </field>
6814 
          </fields>
6815 
        </register>
6816 
        <register>
6817 
          <name>ICR</name>
6818 
          <displayName>ICR</displayName>
6819 
          <description>SDIO interrupt clear register
6820 
          (SDIO_ICR)</description>
6821 
          <addressOffset>0x38</addressOffset>
6822 
          <size>0x20</size>
6823 
          <access>read-write</access>
6824 
          <resetValue>0x00000000</resetValue>
6825 
          <fields>
6826 
            <field>
6827 
              <name>CCRCFAILC</name>
6828 
              <description>CCRCFAILC</description>
6829 
              <bitOffset>0</bitOffset>
6830 
              <bitWidth>1</bitWidth>
6831 
            </field>
6832 
            <field>
6833 
              <name>DCRCFAILC</name>
6834 
              <description>DCRCFAILC</description>
6835 
              <bitOffset>1</bitOffset>
6836 
              <bitWidth>1</bitWidth>
6837 
            </field>
6838 
            <field>
6839 
              <name>CTIMEOUTC</name>
6840 
              <description>CTIMEOUTC</description>
6841 
              <bitOffset>2</bitOffset>
6842 
              <bitWidth>1</bitWidth>
6843 
            </field>
6844 
            <field>
6845 
              <name>DTIMEOUTC</name>
6846 
              <description>DTIMEOUTC</description>
6847 
              <bitOffset>3</bitOffset>
6848 
              <bitWidth>1</bitWidth>
6849 
            </field>
6850 
            <field>
6851 
              <name>TXUNDERRC</name>
6852 
              <description>TXUNDERRC</description>
6853 
              <bitOffset>4</bitOffset>
6854 
              <bitWidth>1</bitWidth>
6855 
            </field>
6856 
            <field>
6857 
              <name>RXOVERRC</name>
6858 
              <description>RXOVERRC</description>
6859 
              <bitOffset>5</bitOffset>
6860 
              <bitWidth>1</bitWidth>
6861 
            </field>
6862 
            <field>
6863 
              <name>CMDRENDC</name>
6864 
              <description>CMDRENDC</description>
6865 
              <bitOffset>6</bitOffset>
6866 
              <bitWidth>1</bitWidth>
6867 
            </field>
6868 
            <field>
6869 
              <name>CMDSENTC</name>
6870 
              <description>CMDSENTC</description>
6871 
              <bitOffset>7</bitOffset>
6872 
              <bitWidth>1</bitWidth>
6873 
            </field>
6874 
            <field>
6875 
              <name>DATAENDC</name>
6876 
              <description>DATAENDC</description>
6877 
              <bitOffset>8</bitOffset>
6878 
              <bitWidth>1</bitWidth>
6879 
            </field>
6880 
            <field>
6881 
              <name>STBITERRC</name>
6882 
              <description>STBITERRC</description>
6883 
              <bitOffset>9</bitOffset>
6884 
              <bitWidth>1</bitWidth>
6885 
            </field>
6886 
            <field>
6887 
              <name>DBCKENDC</name>
6888 
              <description>DBCKENDC</description>
6889 
              <bitOffset>10</bitOffset>
6890 
              <bitWidth>1</bitWidth>
6891 
            </field>
6892 
            <field>
6893 
              <name>SDIOITC</name>
6894 
              <description>SDIOITC</description>
6895 
              <bitOffset>22</bitOffset>
6896 
              <bitWidth>1</bitWidth>
6897 
            </field>
6898 
            <field>
6899 
              <name>CEATAENDC</name>
6900 
              <description>CEATAENDC</description>
6901 
              <bitOffset>23</bitOffset>
6902 
              <bitWidth>1</bitWidth>
6903 
            </field>
6904 
          </fields>
6905 
        </register>
6906 
        <register>
6907 
          <name>MASK</name>
6908 
          <displayName>MASK</displayName>
6909 
          <description>SDIO mask register (SDIO_MASK)</description>
6910 
          <addressOffset>0x3C</addressOffset>
6911 
          <size>0x20</size>
6912 
          <access>read-write</access>
6913 
          <resetValue>0x00000000</resetValue>
6914 
          <fields>
6915 
            <field>
6916 
              <name>CCRCFAILIE</name>
6917 
              <description>CCRCFAILIE</description>
6918 
              <bitOffset>0</bitOffset>
6919 
              <bitWidth>1</bitWidth>
6920 
            </field>
6921 
            <field>
6922 
              <name>DCRCFAILIE</name>
6923 
              <description>DCRCFAILIE</description>
6924 
              <bitOffset>1</bitOffset>
6925 
              <bitWidth>1</bitWidth>
6926 
            </field>
6927 
            <field>
6928 
              <name>CTIMEOUTIE</name>
6929 
              <description>CTIMEOUTIE</description>
6930 
              <bitOffset>2</bitOffset>
6931 
              <bitWidth>1</bitWidth>
6932 
            </field>
6933 
            <field>
6934 
              <name>DTIMEOUTIE</name>
6935 
              <description>DTIMEOUTIE</description>
6936 
              <bitOffset>3</bitOffset>
6937 
              <bitWidth>1</bitWidth>
6938 
            </field>
6939 
            <field>
6940 
              <name>TXUNDERRIE</name>
6941 
              <description>TXUNDERRIE</description>
6942 
              <bitOffset>4</bitOffset>
6943 
              <bitWidth>1</bitWidth>
6944 
            </field>
6945 
            <field>
6946 
              <name>RXOVERRIE</name>
6947 
              <description>RXOVERRIE</description>
6948 
              <bitOffset>5</bitOffset>
6949 
              <bitWidth>1</bitWidth>
6950 
            </field>
6951 
            <field>
6952 
              <name>CMDRENDIE</name>
6953 
              <description>CMDRENDIE</description>
6954 
              <bitOffset>6</bitOffset>
6955 
              <bitWidth>1</bitWidth>
6956 
            </field>
6957 
            <field>
6958 
              <name>CMDSENTIE</name>
6959 
              <description>CMDSENTIE</description>
6960 
              <bitOffset>7</bitOffset>
6961 
              <bitWidth>1</bitWidth>
6962 
            </field>
6963 
            <field>
6964 
              <name>DATAENDIE</name>
6965 
              <description>DATAENDIE</description>
6966 
              <bitOffset>8</bitOffset>
6967 
              <bitWidth>1</bitWidth>
6968 
            </field>
6969 
            <field>
6970 
              <name>STBITERRIE</name>
6971 
              <description>STBITERRIE</description>
6972 
              <bitOffset>9</bitOffset>
6973 
              <bitWidth>1</bitWidth>
6974 
            </field>
6975 
            <field>
6976 
              <name>DBACKENDIE</name>
6977 
              <description>DBACKENDIE</description>
6978 
              <bitOffset>10</bitOffset>
6979 
              <bitWidth>1</bitWidth>
6980 
            </field>
6981 
            <field>
6982 
              <name>CMDACTIE</name>
6983 
              <description>CMDACTIE</description>
6984 
              <bitOffset>11</bitOffset>
6985 
              <bitWidth>1</bitWidth>
6986 
            </field>
6987 
            <field>
6988 
              <name>TXACTIE</name>
6989 
              <description>TXACTIE</description>
6990 
              <bitOffset>12</bitOffset>
6991 
              <bitWidth>1</bitWidth>
6992 
            </field>
6993 
            <field>
6994 
              <name>RXACTIE</name>
6995 
              <description>RXACTIE</description>
6996 
              <bitOffset>13</bitOffset>
6997 
              <bitWidth>1</bitWidth>
6998 
            </field>
6999 
            <field>
7000 
              <name>TXFIFOHEIE</name>
7001 
              <description>TXFIFOHEIE</description>
7002 
              <bitOffset>14</bitOffset>
7003 
              <bitWidth>1</bitWidth>
7004 
            </field>
7005 
            <field>
7006 
              <name>RXFIFOHFIE</name>
7007 
              <description>RXFIFOHFIE</description>
7008 
              <bitOffset>15</bitOffset>
7009 
              <bitWidth>1</bitWidth>
7010 
            </field>
7011 
            <field>
7012 
              <name>TXFIFOFIE</name>
7013 
              <description>TXFIFOFIE</description>
7014 
              <bitOffset>16</bitOffset>
7015 
              <bitWidth>1</bitWidth>
7016 
            </field>
7017 
            <field>
7018 
              <name>RXFIFOFIE</name>
7019 
              <description>RXFIFOFIE</description>
7020 
              <bitOffset>17</bitOffset>
7021 
              <bitWidth>1</bitWidth>
7022 
            </field>
7023 
            <field>
7024 
              <name>TXFIFOEIE</name>
7025 
              <description>TXFIFOEIE</description>
7026 
              <bitOffset>18</bitOffset>
7027 
              <bitWidth>1</bitWidth>
7028 
            </field>
7029 
            <field>
7030 
              <name>RXFIFOEIE</name>
7031 
              <description>RXFIFOEIE</description>
7032 
              <bitOffset>19</bitOffset>
7033 
              <bitWidth>1</bitWidth>
7034 
            </field>
7035 
            <field>
7036 
              <name>TXDAVLIE</name>
7037 
              <description>TXDAVLIE</description>
7038 
              <bitOffset>20</bitOffset>
7039 
              <bitWidth>1</bitWidth>
7040 
            </field>
7041 
            <field>
7042 
              <name>RXDAVLIE</name>
7043 
              <description>RXDAVLIE</description>
7044 
              <bitOffset>21</bitOffset>
7045 
              <bitWidth>1</bitWidth>
7046 
            </field>
7047 
            <field>
7048 
              <name>SDIOITIE</name>
7049 
              <description>SDIOITIE</description>
7050 
              <bitOffset>22</bitOffset>
7051 
              <bitWidth>1</bitWidth>
7052 
            </field>
7053 
            <field>
7054 
              <name>CEATENDIE</name>
7055 
              <description>CEATENDIE</description>
7056 
              <bitOffset>23</bitOffset>
7057 
              <bitWidth>1</bitWidth>
7058 
            </field>
7059 
          </fields>
7060 
        </register>
7061 
        <register>
7062 
          <name>FIFOCNT</name>
7063 
          <displayName>FIFOCNT</displayName>
7064 
          <description>Bits 23:0 = FIFOCOUNT: Remaining number of
7065 
          words to be written to or read from the
7066 
          FIFO</description>
7067 
          <addressOffset>0x48</addressOffset>
7068 
          <size>0x20</size>
7069 
          <access>read-only</access>
7070 
          <resetValue>0x00000000</resetValue>
7071 
          <fields>
7072 
            <field>
7073 
              <name>FIF0COUNT</name>
7074 
              <description>FIF0COUNT</description>
7075 
              <bitOffset>0</bitOffset>
7076 
              <bitWidth>24</bitWidth>
7077 
            </field>
7078 
          </fields>
7079 
        </register>
7080 
        <register>
7081 
          <name>FIFO</name>
7082 
          <displayName>FIFO</displayName>
7083 
          <description>bits 31:0 = FIFOData: Receive and transmit
7084 
          FIFO data</description>
7085 
          <addressOffset>0x80</addressOffset>
7086 
          <size>0x20</size>
7087 
          <access>read-write</access>
7088 
          <resetValue>0x00000000</resetValue>
7089 
          <fields>
7090 
            <field>
7091 
              <name>FIFOData</name>
7092 
              <description>FIFOData</description>
7093 
              <bitOffset>0</bitOffset>
7094 
              <bitWidth>32</bitWidth>
7095 
            </field>
7096 
          </fields>
7097 
        </register>
7098 
      </registers>
7099 
    </peripheral>
7100 
    <peripheral>
7101 
      <name>RTC</name>
7102 
      <description>Real time clock</description>
7103 
      <groupName>RTC</groupName>
7104 
      <baseAddress>0x40002800</baseAddress>
7105 
      <addressBlock>
7106 
        <offset>0x0</offset>
7107 
        <size>0x400</size>
7108 
        <usage>registers</usage>
7109 
      </addressBlock>
7110 
      <interrupt>
7111 
        <name>RTC</name>
7112 
        <description>RTC global interrupt</description>
7113 
        <value>3</value>
7114 
      </interrupt>
7115 
      <interrupt>
7116 
        <name>RTCAlarm</name>
7117 
        <description>RTC Alarms through EXTI line
7118 
        interrupt</description>
7119 
        <value>41</value>
7120 
      </interrupt>
7121 
      <registers>
7122 
        <register>
7123 
          <name>CRH</name>
7124 
          <displayName>CRH</displayName>
7125 
          <description>RTC Control Register High</description>
7126 
          <addressOffset>0x0</addressOffset>
7127 
          <size>0x20</size>
7128 
          <access>read-write</access>
7129 
          <resetValue>0x00000000</resetValue>
7130 
          <fields>
7131 
            <field>
7132 
              <name>SECIE</name>
7133 
              <description>Second interrupt Enable</description>
7134 
              <bitOffset>0</bitOffset>
7135 
              <bitWidth>1</bitWidth>
7136 
            </field>
7137 
            <field>
7138 
              <name>ALRIE</name>
7139 
              <description>Alarm interrupt Enable</description>
7140 
              <bitOffset>1</bitOffset>
7141 
              <bitWidth>1</bitWidth>
7142 
            </field>
7143 
            <field>
7144 
              <name>OWIE</name>
7145 
              <description>Overflow interrupt Enable</description>
7146 
              <bitOffset>2</bitOffset>
7147 
              <bitWidth>1</bitWidth>
7148 
            </field>
7149 
          </fields>
7150 
        </register>
7151 
        <register>
7152 
          <name>CRL</name>
7153 
          <displayName>CRL</displayName>
7154 
          <description>RTC Control Register Low</description>
7155 
          <addressOffset>0x4</addressOffset>
7156 
          <size>0x20</size>
7157 
          <resetValue>0x00000020</resetValue>
7158 
          <fields>
7159 
            <field>
7160 
              <name>SECF</name>
7161 
              <description>Second Flag</description>
7162 
              <bitOffset>0</bitOffset>
7163 
              <bitWidth>1</bitWidth>
7164 
              <access>read-write</access>
7165 
            </field>
7166 
            <field>
7167 
              <name>ALRF</name>
7168 
              <description>Alarm Flag</description>
7169 
              <bitOffset>1</bitOffset>
7170 
              <bitWidth>1</bitWidth>
7171 
              <access>read-write</access>
7172 
            </field>
7173 
            <field>
7174 
              <name>OWF</name>
7175 
              <description>Overflow Flag</description>
7176 
              <bitOffset>2</bitOffset>
7177 
              <bitWidth>1</bitWidth>
7178 
              <access>read-write</access>
7179 
            </field>
7180 
            <field>
7181 
              <name>RSF</name>
7182 
              <description>Registers Synchronized
7183 
              Flag</description>
7184 
              <bitOffset>3</bitOffset>
7185 
              <bitWidth>1</bitWidth>
7186 
              <access>read-write</access>
7187 
            </field>
7188 
            <field>
7189 
              <name>CNF</name>
7190 
              <description>Configuration Flag</description>
7191 
              <bitOffset>4</bitOffset>
7192 
              <bitWidth>1</bitWidth>
7193 
              <access>read-write</access>
7194 
            </field>
7195 
            <field>
7196 
              <name>RTOFF</name>
7197 
              <description>RTC operation OFF</description>
7198 
              <bitOffset>5</bitOffset>
7199 
              <bitWidth>1</bitWidth>
7200 
              <access>read-only</access>
7201 
            </field>
7202 
          </fields>
7203 
        </register>
7204 
        <register>
7205 
          <name>PRLH</name>
7206 
          <displayName>PRLH</displayName>
7207 
          <description>RTC Prescaler Load Register
7208 
          High</description>
7209 
          <addressOffset>0x8</addressOffset>
7210 
          <size>0x20</size>
7211 
          <access>write-only</access>
7212 
          <resetValue>0x00000000</resetValue>
7213 
          <fields>
7214 
            <field>
7215 
              <name>PRLH</name>
7216 
              <description>RTC Prescaler Load Register
7217 
              High</description>
7218 
              <bitOffset>0</bitOffset>
7219 
              <bitWidth>4</bitWidth>
7220 
            </field>
7221 
          </fields>
7222 
        </register>
7223 
        <register>
7224 
          <name>PRLL</name>
7225 
          <displayName>PRLL</displayName>
7226 
          <description>RTC Prescaler Load Register
7227 
          Low</description>
7228 
          <addressOffset>0xC</addressOffset>
7229 
          <size>0x20</size>
7230 
          <access>write-only</access>
7231 
          <resetValue>0x8000</resetValue>
7232 
          <fields>
7233 
            <field>
7234 
              <name>PRLL</name>
7235 
              <description>RTC Prescaler Divider Register
7236 
              Low</description>
7237 
              <bitOffset>0</bitOffset>
7238 
              <bitWidth>16</bitWidth>
7239 
            </field>
7240 
          </fields>
7241 
        </register>
7242 
        <register>
7243 
          <name>DIVH</name>
7244 
          <displayName>DIVH</displayName>
7245 
          <description>RTC Prescaler Divider Register
7246 
          High</description>
7247 
          <addressOffset>0x10</addressOffset>
7248 
          <size>0x20</size>
7249 
          <access>read-only</access>
7250 
          <resetValue>0x00000000</resetValue>
7251 
          <fields>
7252 
            <field>
7253 
              <name>DIVH</name>
7254 
              <description>RTC prescaler divider register
7255 
              high</description>
7256 
              <bitOffset>0</bitOffset>
7257 
              <bitWidth>4</bitWidth>
7258 
            </field>
7259 
          </fields>
7260 
        </register>
7261 
        <register>
7262 
          <name>DIVL</name>
7263 
          <displayName>DIVL</displayName>
7264 
          <description>RTC Prescaler Divider Register
7265 
          Low</description>
7266 
          <addressOffset>0x14</addressOffset>
7267 
          <size>0x20</size>
7268 
          <access>read-only</access>
7269 
          <resetValue>0x8000</resetValue>
7270 
          <fields>
7271 
            <field>
7272 
              <name>DIVL</name>
7273 
              <description>RTC prescaler divider register
7274 
              Low</description>
7275 
              <bitOffset>0</bitOffset>
7276 
              <bitWidth>16</bitWidth>
7277 
            </field>
7278 
          </fields>
7279 
        </register>
7280 
        <register>
7281 
          <name>CNTH</name>
7282 
          <displayName>CNTH</displayName>
7283 
          <description>RTC Counter Register High</description>
7284 
          <addressOffset>0x18</addressOffset>
7285 
          <size>0x20</size>
7286 
          <access>read-write</access>
7287 
          <resetValue>0x00000000</resetValue>
7288 
          <fields>
7289 
            <field>
7290 
              <name>CNTH</name>
7291 
              <description>RTC counter register high</description>
7292 
              <bitOffset>0</bitOffset>
7293 
              <bitWidth>16</bitWidth>
7294 
            </field>
7295 
          </fields>
7296 
        </register>
7297 
        <register>
7298 
          <name>CNTL</name>
7299 
          <displayName>CNTL</displayName>
7300 
          <description>RTC Counter Register Low</description>
7301 
          <addressOffset>0x1C</addressOffset>
7302 
          <size>0x20</size>
7303 
          <access>read-write</access>
7304 
          <resetValue>0x00000000</resetValue>
7305 
          <fields>
7306 
            <field>
7307 
              <name>CNTL</name>
7308 
              <description>RTC counter register Low</description>
7309 
              <bitOffset>0</bitOffset>
7310 
              <bitWidth>16</bitWidth>
7311 
            </field>
7312 
          </fields>
7313 
        </register>
7314 
        <register>
7315 
          <name>ALRH</name>
7316 
          <displayName>ALRH</displayName>
7317 
          <description>RTC Alarm Register High</description>
7318 
          <addressOffset>0x20</addressOffset>
7319 
          <size>0x20</size>
7320 
          <access>write-only</access>
7321 
          <resetValue>0xFFFF</resetValue>
7322 
          <fields>
7323 
            <field>
7324 
              <name>ALRH</name>
7325 
              <description>RTC alarm register high</description>
7326 
              <bitOffset>0</bitOffset>
7327 
              <bitWidth>16</bitWidth>
7328 
            </field>
7329 
          </fields>
7330 
        </register>
7331 
        <register>
7332 
          <name>ALRL</name>
7333 
          <displayName>ALRL</displayName>
7334 
          <description>RTC Alarm Register Low</description>
7335 
          <addressOffset>0x24</addressOffset>
7336 
          <size>0x20</size>
7337 
          <access>write-only</access>
7338 
          <resetValue>0xFFFF</resetValue>
7339 
          <fields>
7340 
            <field>
7341 
              <name>ALRL</name>
7342 
              <description>RTC alarm register low</description>
7343 
              <bitOffset>0</bitOffset>
7344 
              <bitWidth>16</bitWidth>
7345 
            </field>
7346 
          </fields>
7347 
        </register>
7348 
      </registers>
7349 
    </peripheral>
7350 
    <peripheral>
7351 
      <name>BKP</name>
7352 
      <description>Backup registers</description>
7353 
      <groupName>BKP</groupName>
7354 
      <baseAddress>0x40006C00</baseAddress>
7355 
      <addressBlock>
7356 
        <offset>0x0</offset>
7357 
        <size>0x400</size>
7358 
        <usage>registers</usage>
7359 
      </addressBlock>
7360 
      <registers>
7361 
        <register>
7362 
          <name>DR1</name>
7363 
          <displayName>DR1</displayName>
7364 
          <description>Backup data register (BKP_DR)</description>
7365 
          <addressOffset>0x0</addressOffset>
7366 
          <size>0x20</size>
7367 
          <access>read-write</access>
7368 
          <resetValue>0x00000000</resetValue>
7369 
          <fields>
7370 
            <field>
7371 
              <name>D1</name>
7372 
              <description>Backup data</description>
7373 
              <bitOffset>0</bitOffset>
7374 
              <bitWidth>16</bitWidth>
7375 
            </field>
7376 
          </fields>
7377 
        </register>
7378 
        <register>
7379 
          <name>DR2</name>
7380 
          <displayName>DR2</displayName>
7381 
          <description>Backup data register (BKP_DR)</description>
7382 
          <addressOffset>0x4</addressOffset>
7383 
          <size>0x20</size>
7384 
          <access>read-write</access>
7385 
          <resetValue>0x00000000</resetValue>
7386 
          <fields>
7387 
            <field>
7388 
              <name>D2</name>
7389 
              <description>Backup data</description>
7390 
              <bitOffset>0</bitOffset>
7391 
              <bitWidth>16</bitWidth>
7392 
            </field>
7393 
          </fields>
7394 
        </register>
7395 
        <register>
7396 
          <name>DR3</name>
7397 
          <displayName>DR3</displayName>
7398 
          <description>Backup data register (BKP_DR)</description>
7399 
          <addressOffset>0x8</addressOffset>
7400 
          <size>0x20</size>
7401 
          <access>read-write</access>
7402 
          <resetValue>0x00000000</resetValue>
7403 
          <fields>
7404 
            <field>
7405 
              <name>D3</name>
7406 
              <description>Backup data</description>
7407 
              <bitOffset>0</bitOffset>
7408 
              <bitWidth>16</bitWidth>
7409 
            </field>
7410 
          </fields>
7411 
        </register>
7412 
        <register>
7413 
          <name>DR4</name>
7414 
          <displayName>DR4</displayName>
7415 
          <description>Backup data register (BKP_DR)</description>
7416 
          <addressOffset>0xC</addressOffset>
7417 
          <size>0x20</size>
7418 
          <access>read-write</access>
7419 
          <resetValue>0x00000000</resetValue>
7420 
          <fields>
7421 
            <field>
7422 
              <name>D4</name>
7423 
              <description>Backup data</description>
7424 
              <bitOffset>0</bitOffset>
7425 
              <bitWidth>16</bitWidth>
7426 
            </field>
7427 
          </fields>
7428 
        </register>
7429 
        <register>
7430 
          <name>DR5</name>
7431 
          <displayName>DR5</displayName>
7432 
          <description>Backup data register (BKP_DR)</description>
7433 
          <addressOffset>0x10</addressOffset>
7434 
          <size>0x20</size>
7435 
          <access>read-write</access>
7436 
          <resetValue>0x00000000</resetValue>
7437 
          <fields>
7438 
            <field>
7439 
              <name>D5</name>
7440 
              <description>Backup data</description>
7441 
              <bitOffset>0</bitOffset>
7442 
              <bitWidth>16</bitWidth>
7443 
            </field>
7444 
          </fields>
7445 
        </register>
7446 
        <register>
7447 
          <name>DR6</name>
7448 
          <displayName>DR6</displayName>
7449 
          <description>Backup data register (BKP_DR)</description>
7450 
          <addressOffset>0x14</addressOffset>
7451 
          <size>0x20</size>
7452 
          <access>read-write</access>
7453 
          <resetValue>0x00000000</resetValue>
7454 
          <fields>
7455 
            <field>
7456 
              <name>D6</name>
7457 
              <description>Backup data</description>
7458 
              <bitOffset>0</bitOffset>
7459 
              <bitWidth>16</bitWidth>
7460 
            </field>
7461 
          </fields>
7462 
        </register>
7463 
        <register>
7464 
          <name>DR7</name>
7465 
          <displayName>DR7</displayName>
7466 
          <description>Backup data register (BKP_DR)</description>
7467 
          <addressOffset>0x18</addressOffset>
7468 
          <size>0x20</size>
7469 
          <access>read-write</access>
7470 
          <resetValue>0x00000000</resetValue>
7471 
          <fields>
7472 
            <field>
7473 
              <name>D7</name>
7474 
              <description>Backup data</description>
7475 
              <bitOffset>0</bitOffset>
7476 
              <bitWidth>16</bitWidth>
7477 
            </field>
7478 
          </fields>
7479 
        </register>
7480 
        <register>
7481 
          <name>DR8</name>
7482 
          <displayName>DR8</displayName>
7483 
          <description>Backup data register (BKP_DR)</description>
7484 
          <addressOffset>0x1C</addressOffset>
7485 
          <size>0x20</size>
7486 
          <access>read-write</access>
7487 
          <resetValue>0x00000000</resetValue>
7488 
          <fields>
7489 
            <field>
7490 
              <name>D8</name>
7491 
              <description>Backup data</description>
7492 
              <bitOffset>0</bitOffset>
7493 
              <bitWidth>16</bitWidth>
7494 
            </field>
7495 
          </fields>
7496 
        </register>
7497 
        <register>
7498 
          <name>DR9</name>
7499 
          <displayName>DR9</displayName>
7500 
          <description>Backup data register (BKP_DR)</description>
7501 
          <addressOffset>0x20</addressOffset>
7502 
          <size>0x20</size>
7503 
          <access>read-write</access>
7504 
          <resetValue>0x00000000</resetValue>
7505 
          <fields>
7506 
            <field>
7507 
              <name>D9</name>
7508 
              <description>Backup data</description>
7509 
              <bitOffset>0</bitOffset>
7510 
              <bitWidth>16</bitWidth>
7511 
            </field>
7512 
          </fields>
7513 
        </register>
7514 
        <register>
7515 
          <name>DR10</name>
7516 
          <displayName>DR10</displayName>
7517 
          <description>Backup data register (BKP_DR)</description>
7518 
          <addressOffset>0x24</addressOffset>
7519 
          <size>0x20</size>
7520 
          <access>read-write</access>
7521 
          <resetValue>0x00000000</resetValue>
7522 
          <fields>
7523 
            <field>
7524 
              <name>D10</name>
7525 
              <description>Backup data</description>
7526 
              <bitOffset>0</bitOffset>
7527 
              <bitWidth>16</bitWidth>
7528 
            </field>
7529 
          </fields>
7530 
        </register>
7531 
        <register>
7532 
          <name>DR11</name>
7533 
          <displayName>DR11</displayName>
7534 
          <description>Backup data register (BKP_DR)</description>
7535 
          <addressOffset>0x3C</addressOffset>
7536 
          <size>0x20</size>
7537 
          <access>read-write</access>
7538 
          <resetValue>0x00000000</resetValue>
7539 
          <fields>
7540 
            <field>
7541 
              <name>DR11</name>
7542 
              <description>Backup data</description>
7543 
              <bitOffset>0</bitOffset>
7544 
              <bitWidth>16</bitWidth>
7545 
            </field>
7546 
          </fields>
7547 
        </register>
7548 
        <register>
7549 
          <name>DR12</name>
7550 
          <displayName>DR12</displayName>
7551 
          <description>Backup data register (BKP_DR)</description>
7552 
          <addressOffset>0x40</addressOffset>
7553 
          <size>0x20</size>
7554 
          <access>read-write</access>
7555 
          <resetValue>0x00000000</resetValue>
7556 
          <fields>
7557 
            <field>
7558 
              <name>DR12</name>
7559 
              <description>Backup data</description>
7560 
              <bitOffset>0</bitOffset>
7561 
              <bitWidth>16</bitWidth>
7562 
            </field>
7563 
          </fields>
7564 
        </register>
7565 
        <register>
7566 
          <name>DR13</name>
7567 
          <displayName>DR13</displayName>
7568 
          <description>Backup data register (BKP_DR)</description>
7569 
          <addressOffset>0x44</addressOffset>
7570 
          <size>0x20</size>
7571 
          <access>read-write</access>
7572 
          <resetValue>0x00000000</resetValue>
7573 
          <fields>
7574 
            <field>
7575 
              <name>DR13</name>
7576 
              <description>Backup data</description>
7577 
              <bitOffset>0</bitOffset>
7578 
              <bitWidth>16</bitWidth>
7579 
            </field>
7580 
          </fields>
7581 
        </register>
7582 
        <register>
7583 
          <name>DR14</name>
7584 
          <displayName>DR14</displayName>
7585 
          <description>Backup data register (BKP_DR)</description>
7586 
          <addressOffset>0x48</addressOffset>
7587 
          <size>0x20</size>
7588 
          <access>read-write</access>
7589 
          <resetValue>0x00000000</resetValue>
7590 
          <fields>
7591 
            <field>
7592 
              <name>D14</name>
7593 
              <description>Backup data</description>
7594 
              <bitOffset>0</bitOffset>
7595 
              <bitWidth>16</bitWidth>
7596 
            </field>
7597 
          </fields>
7598 
        </register>
7599 
        <register>
7600 
          <name>DR15</name>
7601 
          <displayName>DR15</displayName>
7602 
          <description>Backup data register (BKP_DR)</description>
7603 
          <addressOffset>0x4C</addressOffset>
7604 
          <size>0x20</size>
7605 
          <access>read-write</access>
7606 
          <resetValue>0x00000000</resetValue>
7607 
          <fields>
7608 
            <field>
7609 
              <name>D15</name>
7610 
              <description>Backup data</description>
7611 
              <bitOffset>0</bitOffset>
7612 
              <bitWidth>16</bitWidth>
7613 
            </field>
7614 
          </fields>
7615 
        </register>
7616 
        <register>
7617 
          <name>DR16</name>
7618 
          <displayName>DR16</displayName>
7619 
          <description>Backup data register (BKP_DR)</description>
7620 
          <addressOffset>0x50</addressOffset>
7621 
          <size>0x20</size>
7622 
          <access>read-write</access>
7623 
          <resetValue>0x00000000</resetValue>
7624 
          <fields>
7625 
            <field>
7626 
              <name>D16</name>
7627 
              <description>Backup data</description>
7628 
              <bitOffset>0</bitOffset>
7629 
              <bitWidth>16</bitWidth>
7630 
            </field>
7631 
          </fields>
7632 
        </register>
7633 
        <register>
7634 
          <name>DR17</name>
7635 
          <displayName>DR17</displayName>
7636 
          <description>Backup data register (BKP_DR)</description>
7637 
          <addressOffset>0x54</addressOffset>
7638 
          <size>0x20</size>
7639 
          <access>read-write</access>
7640 
          <resetValue>0x00000000</resetValue>
7641 
          <fields>
7642 
            <field>
7643 
              <name>D17</name>
7644 
              <description>Backup data</description>
7645 
              <bitOffset>0</bitOffset>
7646 
              <bitWidth>16</bitWidth>
7647 
            </field>
7648 
          </fields>
7649 
        </register>
7650 
        <register>
7651 
          <name>DR18</name>
7652 
          <displayName>DR18</displayName>
7653 
          <description>Backup data register (BKP_DR)</description>
7654 
          <addressOffset>0x58</addressOffset>
7655 
          <size>0x20</size>
7656 
          <access>read-write</access>
7657 
          <resetValue>0x00000000</resetValue>
7658 
          <fields>
7659 
            <field>
7660 
              <name>D18</name>
7661 
              <description>Backup data</description>
7662 
              <bitOffset>0</bitOffset>
7663 
              <bitWidth>16</bitWidth>
7664 
            </field>
7665 
          </fields>
7666 
        </register>
7667 
        <register>
7668 
          <name>DR19</name>
7669 
          <displayName>DR19</displayName>
7670 
          <description>Backup data register (BKP_DR)</description>
7671 
          <addressOffset>0x5C</addressOffset>
7672 
          <size>0x20</size>
7673 
          <access>read-write</access>
7674 
          <resetValue>0x00000000</resetValue>
7675 
          <fields>
7676 
            <field>
7677 
              <name>D19</name>
7678 
              <description>Backup data</description>
7679 
              <bitOffset>0</bitOffset>
7680 
              <bitWidth>16</bitWidth>
7681 
            </field>
7682 
          </fields>
7683 
        </register>
7684 
        <register>
7685 
          <name>DR20</name>
7686 
          <displayName>DR20</displayName>
7687 
          <description>Backup data register (BKP_DR)</description>
7688 
          <addressOffset>0x60</addressOffset>
7689 
          <size>0x20</size>
7690 
          <access>read-write</access>
7691 
          <resetValue>0x00000000</resetValue>
7692 
          <fields>
7693 
            <field>
7694 
              <name>D20</name>
7695 
              <description>Backup data</description>
7696 
              <bitOffset>0</bitOffset>
7697 
              <bitWidth>16</bitWidth>
7698 
            </field>
7699 
          </fields>
7700 
        </register>
7701 
        <register>
7702 
          <name>DR21</name>
7703 
          <displayName>DR21</displayName>
7704 
          <description>Backup data register (BKP_DR)</description>
7705 
          <addressOffset>0x64</addressOffset>
7706 
          <size>0x20</size>
7707 
          <access>read-write</access>
7708 
          <resetValue>0x00000000</resetValue>
7709 
          <fields>
7710 
            <field>
7711 
              <name>D21</name>
7712 
              <description>Backup data</description>
7713 
              <bitOffset>0</bitOffset>
7714 
              <bitWidth>16</bitWidth>
7715 
            </field>
7716 
          </fields>
7717 
        </register>
7718 
        <register>
7719 
          <name>DR22</name>
7720 
          <displayName>DR22</displayName>
7721 
          <description>Backup data register (BKP_DR)</description>
7722 
          <addressOffset>0x68</addressOffset>
7723 
          <size>0x20</size>
7724 
          <access>read-write</access>
7725 
          <resetValue>0x00000000</resetValue>
7726 
          <fields>
7727 
            <field>
7728 
              <name>D22</name>
7729 
              <description>Backup data</description>
7730 
              <bitOffset>0</bitOffset>
7731 
              <bitWidth>16</bitWidth>
7732 
            </field>
7733 
          </fields>
7734 
        </register>
7735 
        <register>
7736 
          <name>DR23</name>
7737 
          <displayName>DR23</displayName>
7738 
          <description>Backup data register (BKP_DR)</description>
7739 
          <addressOffset>0x6C</addressOffset>
7740 
          <size>0x20</size>
7741 
          <access>read-write</access>
7742 
          <resetValue>0x00000000</resetValue>
7743 
          <fields>
7744 
            <field>
7745 
              <name>D23</name>
7746 
              <description>Backup data</description>
7747 
              <bitOffset>0</bitOffset>
7748 
              <bitWidth>16</bitWidth>
7749 
            </field>
7750 
          </fields>
7751 
        </register>
7752 
        <register>
7753 
          <name>DR24</name>
7754 
          <displayName>DR24</displayName>
7755 
          <description>Backup data register (BKP_DR)</description>
7756 
          <addressOffset>0x70</addressOffset>
7757 
          <size>0x20</size>
7758 
          <access>read-write</access>
7759 
          <resetValue>0x00000000</resetValue>
7760 
          <fields>
7761 
            <field>
7762 
              <name>D24</name>
7763 
              <description>Backup data</description>
7764 
              <bitOffset>0</bitOffset>
7765 
              <bitWidth>16</bitWidth>
7766 
            </field>
7767 
          </fields>
7768 
        </register>
7769 
        <register>
7770 
          <name>DR25</name>
7771 
          <displayName>DR25</displayName>
7772 
          <description>Backup data register (BKP_DR)</description>
7773 
          <addressOffset>0x74</addressOffset>
7774 
          <size>0x20</size>
7775 
          <access>read-write</access>
7776 
          <resetValue>0x00000000</resetValue>
7777 
          <fields>
7778 
            <field>
7779 
              <name>D25</name>
7780 
              <description>Backup data</description>
7781 
              <bitOffset>0</bitOffset>
7782 
              <bitWidth>16</bitWidth>
7783 
            </field>
7784 
          </fields>
7785 
        </register>
7786 
        <register>
7787 
          <name>DR26</name>
7788 
          <displayName>DR26</displayName>
7789 
          <description>Backup data register (BKP_DR)</description>
7790 
          <addressOffset>0x78</addressOffset>
7791 
          <size>0x20</size>
7792 
          <access>read-write</access>
7793 
          <resetValue>0x00000000</resetValue>
7794 
          <fields>
7795 
            <field>
7796 
              <name>D26</name>
7797 
              <description>Backup data</description>
7798 
              <bitOffset>0</bitOffset>
7799 
              <bitWidth>16</bitWidth>
7800 
            </field>
7801 
          </fields>
7802 
        </register>
7803 
        <register>
7804 
          <name>DR27</name>
7805 
          <displayName>DR27</displayName>
7806 
          <description>Backup data register (BKP_DR)</description>
7807 
          <addressOffset>0x7C</addressOffset>
7808 
          <size>0x20</size>
7809 
          <access>read-write</access>
7810 
          <resetValue>0x00000000</resetValue>
7811 
          <fields>
7812 
            <field>
7813 
              <name>D27</name>
7814 
              <description>Backup data</description>
7815 
              <bitOffset>0</bitOffset>
7816 
              <bitWidth>16</bitWidth>
7817 
            </field>
7818 
          </fields>
7819 
        </register>
7820 
        <register>
7821 
          <name>DR28</name>
7822 
          <displayName>DR28</displayName>
7823 
          <description>Backup data register (BKP_DR)</description>
7824 
          <addressOffset>0x80</addressOffset>
7825 
          <size>0x20</size>
7826 
          <access>read-write</access>
7827 
          <resetValue>0x00000000</resetValue>
7828 
          <fields>
7829 
            <field>
7830 
              <name>D28</name>
7831 
              <description>Backup data</description>
7832 
              <bitOffset>0</bitOffset>
7833 
              <bitWidth>16</bitWidth>
7834 
            </field>
7835 
          </fields>
7836 
        </register>
7837 
        <register>
7838 
          <name>DR29</name>
7839 
          <displayName>DR29</displayName>
7840 
          <description>Backup data register (BKP_DR)</description>
7841 
          <addressOffset>0x84</addressOffset>
7842 
          <size>0x20</size>
7843 
          <access>read-write</access>
7844 
          <resetValue>0x00000000</resetValue>
7845 
          <fields>
7846 
            <field>
7847 
              <name>D29</name>
7848 
              <description>Backup data</description>
7849 
              <bitOffset>0</bitOffset>
7850 
              <bitWidth>16</bitWidth>
7851 
            </field>
7852 
          </fields>
7853 
        </register>
7854 
        <register>
7855 
          <name>DR30</name>
7856 
          <displayName>DR30</displayName>
7857 
          <description>Backup data register (BKP_DR)</description>
7858 
          <addressOffset>0x88</addressOffset>
7859 
          <size>0x20</size>
7860 
          <access>read-write</access>
7861 
          <resetValue>0x00000000</resetValue>
7862 
          <fields>
7863 
            <field>
7864 
              <name>D30</name>
7865 
              <description>Backup data</description>
7866 
              <bitOffset>0</bitOffset>
7867 
              <bitWidth>16</bitWidth>
7868 
            </field>
7869 
          </fields>
7870 
        </register>
7871 
        <register>
7872 
          <name>DR31</name>
7873 
          <displayName>DR31</displayName>
7874 
          <description>Backup data register (BKP_DR)</description>
7875 
          <addressOffset>0x8C</addressOffset>
7876 
          <size>0x20</size>
7877 
          <access>read-write</access>
7878 
          <resetValue>0x00000000</resetValue>
7879 
          <fields>
7880 
            <field>
7881 
              <name>D31</name>
7882 
              <description>Backup data</description>
7883 
              <bitOffset>0</bitOffset>
7884 
              <bitWidth>16</bitWidth>
7885 
            </field>
7886 
          </fields>
7887 
        </register>
7888 
        <register>
7889 
          <name>DR32</name>
7890 
          <displayName>DR32</displayName>
7891 
          <description>Backup data register (BKP_DR)</description>
7892 
          <addressOffset>0x90</addressOffset>
7893 
          <size>0x20</size>
7894 
          <access>read-write</access>
7895 
          <resetValue>0x00000000</resetValue>
7896 
          <fields>
7897 
            <field>
7898 
              <name>D32</name>
7899 
              <description>Backup data</description>
7900 
              <bitOffset>0</bitOffset>
7901 
              <bitWidth>16</bitWidth>
7902 
            </field>
7903 
          </fields>
7904 
        </register>
7905 
        <register>
7906 
          <name>DR33</name>
7907 
          <displayName>DR33</displayName>
7908 
          <description>Backup data register (BKP_DR)</description>
7909 
          <addressOffset>0x94</addressOffset>
7910 
          <size>0x20</size>
7911 
          <access>read-write</access>
7912 
          <resetValue>0x00000000</resetValue>
7913 
          <fields>
7914 
            <field>
7915 
              <name>D33</name>
7916 
              <description>Backup data</description>
7917 
              <bitOffset>0</bitOffset>
7918 
              <bitWidth>16</bitWidth>
7919 
            </field>
7920 
          </fields>
7921 
        </register>
7922 
        <register>
7923 
          <name>DR34</name>
7924 
          <displayName>DR34</displayName>
7925 
          <description>Backup data register (BKP_DR)</description>
7926 
          <addressOffset>0x98</addressOffset>
7927 
          <size>0x20</size>
7928 
          <access>read-write</access>
7929 
          <resetValue>0x00000000</resetValue>
7930 
          <fields>
7931 
            <field>
7932 
              <name>D34</name>
7933 
              <description>Backup data</description>
7934 
              <bitOffset>0</bitOffset>
7935 
              <bitWidth>16</bitWidth>
7936 
            </field>
7937 
          </fields>
7938 
        </register>
7939 
        <register>
7940 
          <name>DR35</name>
7941 
          <displayName>DR35</displayName>
7942 
          <description>Backup data register (BKP_DR)</description>
7943 
          <addressOffset>0x9C</addressOffset>
7944 
          <size>0x20</size>
7945 
          <access>read-write</access>
7946 
          <resetValue>0x00000000</resetValue>
7947 
          <fields>
7948 
            <field>
7949 
              <name>D35</name>
7950 
              <description>Backup data</description>
7951 
              <bitOffset>0</bitOffset>
7952 
              <bitWidth>16</bitWidth>
7953 
            </field>
7954 
          </fields>
7955 
        </register>
7956 
        <register>
7957 
          <name>DR36</name>
7958 
          <displayName>DR36</displayName>
7959 
          <description>Backup data register (BKP_DR)</description>
7960 
          <addressOffset>0xA0</addressOffset>
7961 
          <size>0x20</size>
7962 
          <access>read-write</access>
7963 
          <resetValue>0x00000000</resetValue>
7964 
          <fields>
7965 
            <field>
7966 
              <name>D36</name>
7967 
              <description>Backup data</description>
7968 
              <bitOffset>0</bitOffset>
7969 
              <bitWidth>16</bitWidth>
7970 
            </field>
7971 
          </fields>
7972 
        </register>
7973 
        <register>
7974 
          <name>DR37</name>
7975 
          <displayName>DR37</displayName>
7976 
          <description>Backup data register (BKP_DR)</description>
7977 
          <addressOffset>0xA4</addressOffset>
7978 
          <size>0x20</size>
7979 
          <access>read-write</access>
7980 
          <resetValue>0x00000000</resetValue>
7981 
          <fields>
7982 
            <field>
7983 
              <name>D37</name>
7984 
              <description>Backup data</description>
7985 
              <bitOffset>0</bitOffset>
7986 
              <bitWidth>16</bitWidth>
7987 
            </field>
7988 
          </fields>
7989 
        </register>
7990 
        <register>
7991 
          <name>DR38</name>
7992 
          <displayName>DR38</displayName>
7993 
          <description>Backup data register (BKP_DR)</description>
7994 
          <addressOffset>0xA8</addressOffset>
7995 
          <size>0x20</size>
7996 
          <access>read-write</access>
7997 
          <resetValue>0x00000000</resetValue>
7998 
          <fields>
7999 
            <field>
8000 
              <name>D38</name>
8001 
              <description>Backup data</description>
8002 
              <bitOffset>0</bitOffset>
8003 
              <bitWidth>16</bitWidth>
8004 
            </field>
8005 
          </fields>
8006 
        </register>
8007 
        <register>
8008 
          <name>DR39</name>
8009 
          <displayName>DR39</displayName>
8010 
          <description>Backup data register (BKP_DR)</description>
8011 
          <addressOffset>0xAC</addressOffset>
8012 
          <size>0x20</size>
8013 
          <access>read-write</access>
8014 
          <resetValue>0x00000000</resetValue>
8015 
          <fields>
8016 
            <field>
8017 
              <name>D39</name>
8018 
              <description>Backup data</description>
8019 
              <bitOffset>0</bitOffset>
8020 
              <bitWidth>16</bitWidth>
8021 
            </field>
8022 
          </fields>
8023 
        </register>
8024 
        <register>
8025 
          <name>DR40</name>
8026 
          <displayName>DR40</displayName>
8027 
          <description>Backup data register (BKP_DR)</description>
8028 
          <addressOffset>0xB0</addressOffset>
8029 
          <size>0x20</size>
8030 
          <access>read-write</access>
8031 
          <resetValue>0x00000000</resetValue>
8032 
          <fields>
8033 
            <field>
8034 
              <name>D40</name>
8035 
              <description>Backup data</description>
8036 
              <bitOffset>0</bitOffset>
8037 
              <bitWidth>16</bitWidth>
8038 
            </field>
8039 
          </fields>
8040 
        </register>
8041 
        <register>
8042 
          <name>DR41</name>
8043 
          <displayName>DR41</displayName>
8044 
          <description>Backup data register (BKP_DR)</description>
8045 
          <addressOffset>0xB4</addressOffset>
8046 
          <size>0x20</size>
8047 
          <access>read-write</access>
8048 
          <resetValue>0x00000000</resetValue>
8049 
          <fields>
8050 
            <field>
8051 
              <name>D41</name>
8052 
              <description>Backup data</description>
8053 
              <bitOffset>0</bitOffset>
8054 
              <bitWidth>16</bitWidth>
8055 
            </field>
8056 
          </fields>
8057 
        </register>
8058 
        <register>
8059 
          <name>DR42</name>
8060 
          <displayName>DR42</displayName>
8061 
          <description>Backup data register (BKP_DR)</description>
8062 
          <addressOffset>0xB8</addressOffset>
8063 
          <size>0x20</size>
8064 
          <access>read-write</access>
8065 
          <resetValue>0x00000000</resetValue>
8066 
          <fields>
8067 
            <field>
8068 
              <name>D42</name>
8069 
              <description>Backup data</description>
8070 
              <bitOffset>0</bitOffset>
8071 
              <bitWidth>16</bitWidth>
8072 
            </field>
8073 
          </fields>
8074 
        </register>
8075 
        <register>
8076 
          <name>RTCCR</name>
8077 
          <displayName>RTCCR</displayName>
8078 
          <description>RTC clock calibration register
8079 
          (BKP_RTCCR)</description>
8080 
          <addressOffset>0x28</addressOffset>
8081 
          <size>0x20</size>
8082 
          <access>read-write</access>
8083 
          <resetValue>0x00000000</resetValue>
8084 
          <fields>
8085 
            <field>
8086 
              <name>CAL</name>
8087 
              <description>Calibration value</description>
8088 
              <bitOffset>0</bitOffset>
8089 
              <bitWidth>7</bitWidth>
8090 
            </field>
8091 
            <field>
8092 
              <name>CCO</name>
8093 
              <description>Calibration Clock Output</description>
8094 
              <bitOffset>7</bitOffset>
8095 
              <bitWidth>1</bitWidth>
8096 
            </field>
8097 
            <field>
8098 
              <name>ASOE</name>
8099 
              <description>Alarm or second output
8100 
              enable</description>
8101 
              <bitOffset>8</bitOffset>
8102 
              <bitWidth>1</bitWidth>
8103 
            </field>
8104 
            <field>
8105 
              <name>ASOS</name>
8106 
              <description>Alarm or second output
8107 
              selection</description>
8108 
              <bitOffset>9</bitOffset>
8109 
              <bitWidth>1</bitWidth>
8110 
            </field>
8111 
          </fields>
8112 
        </register>
8113 
        <register>
8114 
          <name>CR</name>
8115 
          <displayName>CR</displayName>
8116 
          <description>Backup control register
8117 
          (BKP_CR)</description>
8118 
          <addressOffset>0x2C</addressOffset>
8119 
          <size>0x20</size>
8120 
          <access>read-write</access>
8121 
          <resetValue>0x00000000</resetValue>
8122 
          <fields>
8123 
            <field>
8124 
              <name>TPE</name>
8125 
              <description>Tamper pin enable</description>
8126 
              <bitOffset>0</bitOffset>
8127 
              <bitWidth>1</bitWidth>
8128 
            </field>
8129 
            <field>
8130 
              <name>TPAL</name>
8131 
              <description>Tamper pin active level</description>
8132 
              <bitOffset>1</bitOffset>
8133 
              <bitWidth>1</bitWidth>
8134 
            </field>
8135 
          </fields>
8136 
        </register>
8137 
        <register>
8138 
          <name>CSR</name>
8139 
          <displayName>CSR</displayName>
8140 
          <description>BKP_CSR control/status register
8141 
          (BKP_CSR)</description>
8142 
          <addressOffset>0x30</addressOffset>
8143 
          <size>0x20</size>
8144 
          <resetValue>0x00000000</resetValue>
8145 
          <fields>
8146 
            <field>
8147 
              <name>CTE</name>
8148 
              <description>Clear Tamper event</description>
8149 
              <bitOffset>0</bitOffset>
8150 
              <bitWidth>1</bitWidth>
8151 
              <access>write-only</access>
8152 
            </field>
8153 
            <field>
8154 
              <name>CTI</name>
8155 
              <description>Clear Tamper Interrupt</description>
8156 
              <bitOffset>1</bitOffset>
8157 
              <bitWidth>1</bitWidth>
8158 
              <access>write-only</access>
8159 
            </field>
8160 
            <field>
8161 
              <name>TPIE</name>
8162 
              <description>Tamper Pin interrupt
8163 
              enable</description>
8164 
              <bitOffset>2</bitOffset>
8165 
              <bitWidth>1</bitWidth>
8166 
              <access>read-write</access>
8167 
            </field>
8168 
            <field>
8169 
              <name>TEF</name>
8170 
              <description>Tamper Event Flag</description>
8171 
              <bitOffset>8</bitOffset>
8172 
              <bitWidth>1</bitWidth>
8173 
              <access>read-only</access>
8174 
            </field>
8175 
            <field>
8176 
              <name>TIF</name>
8177 
              <description>Tamper Interrupt Flag</description>
8178 
              <bitOffset>9</bitOffset>
8179 
              <bitWidth>1</bitWidth>
8180 
              <access>read-only</access>
8181 
            </field>
8182 
          </fields>
8183 
        </register>
8184 
      </registers>
8185 
    </peripheral>
8186 
    <peripheral>
8187 
      <name>IWDG</name>
8188 
      <description>Independent watchdog</description>
8189 
      <groupName>IWDG</groupName>
8190 
      <baseAddress>0x40003000</baseAddress>
8191 
      <addressBlock>
8192 
        <offset>0x0</offset>
8193 
        <size>0x400</size>
8194 
        <usage>registers</usage>
8195 
      </addressBlock>
8196 
      <registers>
8197 
        <register>
8198 
          <name>KR</name>
8199 
          <displayName>KR</displayName>
8200 
          <description>Key register (IWDG_KR)</description>
8201 
          <addressOffset>0x0</addressOffset>
8202 
          <size>0x20</size>
8203 
          <access>write-only</access>
8204 
          <resetValue>0x00000000</resetValue>
8205 
          <fields>
8206 
            <field>
8207 
              <name>KEY</name>
8208 
              <description>Key value</description>
8209 
              <bitOffset>0</bitOffset>
8210 
              <bitWidth>16</bitWidth>
8211 
            </field>
8212 
          </fields>
8213 
        </register>
8214 
        <register>
8215 
          <name>PR</name>
8216 
          <displayName>PR</displayName>
8217 
          <description>Prescaler register (IWDG_PR)</description>
8218 
          <addressOffset>0x4</addressOffset>
8219 
          <size>0x20</size>
8220 
          <access>read-write</access>
8221 
          <resetValue>0x00000000</resetValue>
8222 
          <fields>
8223 
            <field>
8224 
              <name>PR</name>
8225 
              <description>Prescaler divider</description>
8226 
              <bitOffset>0</bitOffset>
8227 
              <bitWidth>3</bitWidth>
8228 
            </field>
8229 
          </fields>
8230 
        </register>
8231 
        <register>
8232 
          <name>RLR</name>
8233 
          <displayName>RLR</displayName>
8234 
          <description>Reload register (IWDG_RLR)</description>
8235 
          <addressOffset>0x8</addressOffset>
8236 
          <size>0x20</size>
8237 
          <access>read-write</access>
8238 
          <resetValue>0x00000FFF</resetValue>
8239 
          <fields>
8240 
            <field>
8241 
              <name>RL</name>
8242 
              <description>Watchdog counter reload
8243 
              value</description>
8244 
              <bitOffset>0</bitOffset>
8245 
              <bitWidth>12</bitWidth>
8246 
            </field>
8247 
          </fields>
8248 
        </register>
8249 
        <register>
8250 
          <name>SR</name>
8251 
          <displayName>SR</displayName>
8252 
          <description>Status register (IWDG_SR)</description>
8253 
          <addressOffset>0xC</addressOffset>
8254 
          <size>0x20</size>
8255 
          <access>read-only</access>
8256 
          <resetValue>0x00000000</resetValue>
8257 
          <fields>
8258 
            <field>
8259 
              <name>PVU</name>
8260 
              <description>Watchdog prescaler value
8261 
              update</description>
8262 
              <bitOffset>0</bitOffset>
8263 
              <bitWidth>1</bitWidth>
8264 
            </field>
8265 
            <field>
8266 
              <name>RVU</name>
8267 
              <description>Watchdog counter reload value
8268 
              update</description>
8269 
              <bitOffset>1</bitOffset>
8270 
              <bitWidth>1</bitWidth>
8271 
            </field>
8272 
          </fields>
8273 
        </register>
8274 
      </registers>
8275 
    </peripheral>
8276 
    <peripheral>
8277 
      <name>WWDG</name>
8278 
      <description>Window watchdog</description>
8279 
      <groupName>WWDG</groupName>
8280 
      <baseAddress>0x40002C00</baseAddress>
8281 
      <addressBlock>
8282 
        <offset>0x0</offset>
8283 
        <size>0x400</size>
8284 
        <usage>registers</usage>
8285 
      </addressBlock>
8286 
      <interrupt>
8287 
        <name>WWDG</name>
8288 
        <description>Window Watchdog interrupt</description>
8289 
        <value>0</value>
8290 
      </interrupt>
8291 
      <registers>
8292 
        <register>
8293 
          <name>CR</name>
8294 
          <displayName>CR</displayName>
8295 
          <description>Control register (WWDG_CR)</description>
8296 
          <addressOffset>0x0</addressOffset>
8297 
          <size>0x20</size>
8298 
          <access>read-write</access>
8299 
          <resetValue>0x0000007F</resetValue>
8300 
          <fields>
8301 
            <field>
8302 
              <name>T</name>
8303 
              <description>7-bit counter (MSB to LSB)</description>
8304 
              <bitOffset>0</bitOffset>
8305 
              <bitWidth>7</bitWidth>
8306 
            </field>
8307 
            <field>
8308 
              <name>WDGA</name>
8309 
              <description>Activation bit</description>
8310 
              <bitOffset>7</bitOffset>
8311 
              <bitWidth>1</bitWidth>
8312 
            </field>
8313 
          </fields>
8314 
        </register>
8315 
        <register>
8316 
          <name>CFR</name>
8317 
          <displayName>CFR</displayName>
8318 
          <description>Configuration register
8319 
          (WWDG_CFR)</description>
8320 
          <addressOffset>0x4</addressOffset>
8321 
          <size>0x20</size>
8322 
          <access>read-write</access>
8323 
          <resetValue>0x0000007F</resetValue>
8324 
          <fields>
8325 
            <field>
8326 
              <name>W</name>
8327 
              <description>7-bit window value</description>
8328 
              <bitOffset>0</bitOffset>
8329 
              <bitWidth>7</bitWidth>
8330 
            </field>
8331 
            <field>
8332 
              <name>WDGTB</name>
8333 
              <description>Timer Base</description>
8334 
              <bitOffset>7</bitOffset>
8335 
              <bitWidth>2</bitWidth>
8336 
            </field>
8337 
            <field>
8338 
              <name>EWI</name>
8339 
              <description>Early Wakeup Interrupt</description>
8340 
              <bitOffset>9</bitOffset>
8341 
              <bitWidth>1</bitWidth>
8342 
            </field>
8343 
          </fields>
8344 
        </register>
8345 
        <register>
8346 
          <name>SR</name>
8347 
          <displayName>SR</displayName>
8348 
          <description>Status register (WWDG_SR)</description>
8349 
          <addressOffset>0x8</addressOffset>
8350 
          <size>0x20</size>
8351 
          <access>read-write</access>
8352 
          <resetValue>0x00000000</resetValue>
8353 
          <fields>
8354 
            <field>
8355 
              <name>EWI</name>
8356 
              <description>Early Wakeup Interrupt</description>
8357 
              <bitOffset>0</bitOffset>
8358 
              <bitWidth>1</bitWidth>
8359 
            </field>
8360 
          </fields>
8361 
        </register>
8362 
      </registers>
8363 
    </peripheral>
8364 
    <peripheral>
8365 
      <name>TIM1</name>
8366 
      <description>Advanced timer</description>
8367 
      <groupName>TIM</groupName>
8368 
      <baseAddress>0x40012C00</baseAddress>
8369 
      <addressBlock>
8370 
        <offset>0x0</offset>
8371 
        <size>0x400</size>
8372 
        <usage>registers</usage>
8373 
      </addressBlock>
8374 
      <interrupt>
8375 
        <name>TIM1_BRK</name>
8376 
        <description>TIM1 Break interrupt</description>
8377 
        <value>24</value>
8378 
      </interrupt>
8379 
      <interrupt>
8380 
        <name>TIM1_CC</name>
8381 
        <description>TIM1 Capture Compare interrupt</description>
8382 
        <value>27</value>
8383 
      </interrupt>
8384 
      <registers>
8385 
        <register>
8386 
          <name>CR1</name>
8387 
          <displayName>CR1</displayName>
8388 
          <description>control register 1</description>
8389 
          <addressOffset>0x0</addressOffset>
8390 
          <size>0x20</size>
8391 
          <access>read-write</access>
8392 
          <resetValue>0x0000</resetValue>
8393 
          <fields>
8394 
            <field>
8395 
              <name>CKD</name>
8396 
              <description>Clock division</description>
8397 
              <bitOffset>8</bitOffset>
8398 
              <bitWidth>2</bitWidth>
8399 
            </field>
8400 
            <field>
8401 
              <name>ARPE</name>
8402 
              <description>Auto-reload preload enable</description>
8403 
              <bitOffset>7</bitOffset>
8404 
              <bitWidth>1</bitWidth>
8405 
            </field>
8406 
            <field>
8407 
              <name>CMS</name>
8408 
              <description>Center-aligned mode
8409 
              selection</description>
8410 
              <bitOffset>5</bitOffset>
8411 
              <bitWidth>2</bitWidth>
8412 
            </field>
8413 
            <field>
8414 
              <name>DIR</name>
8415 
              <description>Direction</description>
8416 
              <bitOffset>4</bitOffset>
8417 
              <bitWidth>1</bitWidth>
8418 
            </field>
8419 
            <field>
8420 
              <name>OPM</name>
8421 
              <description>One-pulse mode</description>
8422 
              <bitOffset>3</bitOffset>
8423 
              <bitWidth>1</bitWidth>
8424 
            </field>
8425 
            <field>
8426 
              <name>URS</name>
8427 
              <description>Update request source</description>
8428 
              <bitOffset>2</bitOffset>
8429 
              <bitWidth>1</bitWidth>
8430 
            </field>
8431 
            <field>
8432 
              <name>UDIS</name>
8433 
              <description>Update disable</description>
8434 
              <bitOffset>1</bitOffset>
8435 
              <bitWidth>1</bitWidth>
8436 
            </field>
8437 
            <field>
8438 
              <name>CEN</name>
8439 
              <description>Counter enable</description>
8440 
              <bitOffset>0</bitOffset>
8441 
              <bitWidth>1</bitWidth>
8442 
            </field>
8443 
          </fields>
8444 
        </register>
8445 
        <register>
8446 
          <name>CR2</name>
8447 
          <displayName>CR2</displayName>
8448 
          <description>control register 2</description>
8449 
          <addressOffset>0x4</addressOffset>
8450 
          <size>0x20</size>
8451 
          <access>read-write</access>
8452 
          <resetValue>0x0000</resetValue>
8453 
          <fields>
8454 
            <field>
8455 
              <name>OIS4</name>
8456 
              <description>Output Idle state 4</description>
8457 
              <bitOffset>14</bitOffset>
8458 
              <bitWidth>1</bitWidth>
8459 
            </field>
8460 
            <field>
8461 
              <name>OIS3N</name>
8462 
              <description>Output Idle state 3</description>
8463 
              <bitOffset>13</bitOffset>
8464 
              <bitWidth>1</bitWidth>
8465 
            </field>
8466 
            <field>
8467 
              <name>OIS3</name>
8468 
              <description>Output Idle state 3</description>
8469 
              <bitOffset>12</bitOffset>
8470 
              <bitWidth>1</bitWidth>
8471 
            </field>
8472 
            <field>
8473 
              <name>OIS2N</name>
8474 
              <description>Output Idle state 2</description>
8475 
              <bitOffset>11</bitOffset>
8476 
              <bitWidth>1</bitWidth>
8477 
            </field>
8478 
            <field>
8479 
              <name>OIS2</name>
8480 
              <description>Output Idle state 2</description>
8481 
              <bitOffset>10</bitOffset>
8482 
              <bitWidth>1</bitWidth>
8483 
            </field>
8484 
            <field>
8485 
              <name>OIS1N</name>
8486 
              <description>Output Idle state 1</description>
8487 
              <bitOffset>9</bitOffset>
8488 
              <bitWidth>1</bitWidth>
8489 
            </field>
8490 
            <field>
8491 
              <name>OIS1</name>
8492 
              <description>Output Idle state 1</description>
8493 
              <bitOffset>8</bitOffset>
8494 
              <bitWidth>1</bitWidth>
8495 
            </field>
8496 
            <field>
8497 
              <name>TI1S</name>
8498 
              <description>TI1 selection</description>
8499 
              <bitOffset>7</bitOffset>
8500 
              <bitWidth>1</bitWidth>
8501 
            </field>
8502 
            <field>
8503 
              <name>MMS</name>
8504 
              <description>Master mode selection</description>
8505 
              <bitOffset>4</bitOffset>
8506 
              <bitWidth>3</bitWidth>
8507 
            </field>
8508 
            <field>
8509 
              <name>CCDS</name>
8510 
              <description>Capture/compare DMA
8511 
              selection</description>
8512 
              <bitOffset>3</bitOffset>
8513 
              <bitWidth>1</bitWidth>
8514 
            </field>
8515 
            <field>
8516 
              <name>CCUS</name>
8517 
              <description>Capture/compare control update
8518 
              selection</description>
8519 
              <bitOffset>2</bitOffset>
8520 
              <bitWidth>1</bitWidth>
8521 
            </field>
8522 
            <field>
8523 
              <name>CCPC</name>
8524 
              <description>Capture/compare preloaded
8525 
              control</description>
8526 
              <bitOffset>0</bitOffset>
8527 
              <bitWidth>1</bitWidth>
8528 
            </field>
8529 
          </fields>
8530 
        </register>
8531 
        <register>
8532 
          <name>SMCR</name>
8533 
          <displayName>SMCR</displayName>
8534 
          <description>slave mode control register</description>
8535 
          <addressOffset>0x8</addressOffset>
8536 
          <size>0x20</size>
8537 
          <access>read-write</access>
8538 
          <resetValue>0x0000</resetValue>
8539 
          <fields>
8540 
            <field>
8541 
              <name>ETP</name>
8542 
              <description>External trigger polarity</description>
8543 
              <bitOffset>15</bitOffset>
8544 
              <bitWidth>1</bitWidth>
8545 
            </field>
8546 
            <field>
8547 
              <name>ECE</name>
8548 
              <description>External clock enable</description>
8549 
              <bitOffset>14</bitOffset>
8550 
              <bitWidth>1</bitWidth>
8551 
            </field>
8552 
            <field>
8553 
              <name>ETPS</name>
8554 
              <description>External trigger prescaler</description>
8555 
              <bitOffset>12</bitOffset>
8556 
              <bitWidth>2</bitWidth>
8557 
            </field>
8558 
            <field>
8559 
              <name>ETF</name>
8560 
              <description>External trigger filter</description>
8561 
              <bitOffset>8</bitOffset>
8562 
              <bitWidth>4</bitWidth>
8563 
            </field>
8564 
            <field>
8565 
              <name>MSM</name>
8566 
              <description>Master/Slave mode</description>
8567 
              <bitOffset>7</bitOffset>
8568 
              <bitWidth>1</bitWidth>
8569 
            </field>
8570 
            <field>
8571 
              <name>TS</name>
8572 
              <description>Trigger selection</description>
8573 
              <bitOffset>4</bitOffset>
8574 
              <bitWidth>3</bitWidth>
8575 
            </field>
8576 
            <field>
8577 
              <name>SMS</name>
8578 
              <description>Slave mode selection</description>
8579 
              <bitOffset>0</bitOffset>
8580 
              <bitWidth>3</bitWidth>
8581 
            </field>
8582 
          </fields>
8583 
        </register>
8584 
        <register>
8585 
          <name>DIER</name>
8586 
          <displayName>DIER</displayName>
8587 
          <description>DMA/Interrupt enable register</description>
8588 
          <addressOffset>0xC</addressOffset>
8589 
          <size>0x20</size>
8590 
          <access>read-write</access>
8591 
          <resetValue>0x0000</resetValue>
8592 
          <fields>
8593 
            <field>
8594 
              <name>TDE</name>
8595 
              <description>Trigger DMA request enable</description>
8596 
              <bitOffset>14</bitOffset>
8597 
              <bitWidth>1</bitWidth>
8598 
            </field>
8599 
            <field>
8600 
              <name>COMDE</name>
8601 
              <description>COM DMA request enable</description>
8602 
              <bitOffset>13</bitOffset>
8603 
              <bitWidth>1</bitWidth>
8604 
            </field>
8605 
            <field>
8606 
              <name>CC4DE</name>
8607 
              <description>Capture/Compare 4 DMA request
8608 
              enable</description>
8609 
              <bitOffset>12</bitOffset>
8610 
              <bitWidth>1</bitWidth>
8611 
            </field>
8612 
            <field>
8613 
              <name>CC3DE</name>
8614 
              <description>Capture/Compare 3 DMA request
8615 
              enable</description>
8616 
              <bitOffset>11</bitOffset>
8617 
              <bitWidth>1</bitWidth>
8618 
            </field>
8619 
            <field>
8620 
              <name>CC2DE</name>
8621 
              <description>Capture/Compare 2 DMA request
8622 
              enable</description>
8623 
              <bitOffset>10</bitOffset>
8624 
              <bitWidth>1</bitWidth>
8625 
            </field>
8626 
            <field>
8627 
              <name>CC1DE</name>
8628 
              <description>Capture/Compare 1 DMA request
8629 
              enable</description>
8630 
              <bitOffset>9</bitOffset>
8631 
              <bitWidth>1</bitWidth>
8632 
            </field>
8633 
            <field>
8634 
              <name>UDE</name>
8635 
              <description>Update DMA request enable</description>
8636 
              <bitOffset>8</bitOffset>
8637 
              <bitWidth>1</bitWidth>
8638 
            </field>
8639 
            <field>
8640 
              <name>TIE</name>
8641 
              <description>Trigger interrupt enable</description>
8642 
              <bitOffset>6</bitOffset>
8643 
              <bitWidth>1</bitWidth>
8644 
            </field>
8645 
            <field>
8646 
              <name>CC4IE</name>
8647 
              <description>Capture/Compare 4 interrupt
8648 
              enable</description>
8649 
              <bitOffset>4</bitOffset>
8650 
              <bitWidth>1</bitWidth>
8651 
            </field>
8652 
            <field>
8653 
              <name>CC3IE</name>
8654 
              <description>Capture/Compare 3 interrupt
8655 
              enable</description>
8656 
              <bitOffset>3</bitOffset>
8657 
              <bitWidth>1</bitWidth>
8658 
            </field>
8659 
            <field>
8660 
              <name>CC2IE</name>
8661 
              <description>Capture/Compare 2 interrupt
8662 
              enable</description>
8663 
              <bitOffset>2</bitOffset>
8664 
              <bitWidth>1</bitWidth>
8665 
            </field>
8666 
            <field>
8667 
              <name>CC1IE</name>
8668 
              <description>Capture/Compare 1 interrupt
8669 
              enable</description>
8670 
              <bitOffset>1</bitOffset>
8671 
              <bitWidth>1</bitWidth>
8672 
            </field>
8673 
            <field>
8674 
              <name>UIE</name>
8675 
              <description>Update interrupt enable</description>
8676 
              <bitOffset>0</bitOffset>
8677 
              <bitWidth>1</bitWidth>
8678 
            </field>
8679 
            <field>
8680 
              <name>BIE</name>
8681 
              <description>Break interrupt enable</description>
8682 
              <bitOffset>7</bitOffset>
8683 
              <bitWidth>1</bitWidth>
8684 
            </field>
8685 
            <field>
8686 
              <name>COMIE</name>
8687 
              <description>COM interrupt enable</description>
8688 
              <bitOffset>5</bitOffset>
8689 
              <bitWidth>1</bitWidth>
8690 
            </field>
8691 
          </fields>
8692 
        </register>
8693 
        <register>
8694 
          <name>SR</name>
8695 
          <displayName>SR</displayName>
8696 
          <description>status register</description>
8697 
          <addressOffset>0x10</addressOffset>
8698 
          <size>0x20</size>
8699 
          <access>read-write</access>
8700 
          <resetValue>0x0000</resetValue>
8701 
          <fields>
8702 
            <field>
8703 
              <name>CC4OF</name>
8704 
              <description>Capture/Compare 4 overcapture
8705 
              flag</description>
8706 
              <bitOffset>12</bitOffset>
8707 
              <bitWidth>1</bitWidth>
8708 
            </field>
8709 
            <field>
8710 
              <name>CC3OF</name>
8711 
              <description>Capture/Compare 3 overcapture
8712 
              flag</description>
8713 
              <bitOffset>11</bitOffset>
8714 
              <bitWidth>1</bitWidth>
8715 
            </field>
8716 
            <field>
8717 
              <name>CC2OF</name>
8718 
              <description>Capture/compare 2 overcapture
8719 
              flag</description>
8720 
              <bitOffset>10</bitOffset>
8721 
              <bitWidth>1</bitWidth>
8722 
            </field>
8723 
            <field>
8724 
              <name>CC1OF</name>
8725 
              <description>Capture/Compare 1 overcapture
8726 
              flag</description>
8727 
              <bitOffset>9</bitOffset>
8728 
              <bitWidth>1</bitWidth>
8729 
            </field>
8730 
            <field>
8731 
              <name>BIF</name>
8732 
              <description>Break interrupt flag</description>
8733 
              <bitOffset>7</bitOffset>
8734 
              <bitWidth>1</bitWidth>
8735 
            </field>
8736 
            <field>
8737 
              <name>TIF</name>
8738 
              <description>Trigger interrupt flag</description>
8739 
              <bitOffset>6</bitOffset>
8740 
              <bitWidth>1</bitWidth>
8741 
            </field>
8742 
            <field>
8743 
              <name>COMIF</name>
8744 
              <description>COM interrupt flag</description>
8745 
              <bitOffset>5</bitOffset>
8746 
              <bitWidth>1</bitWidth>
8747 
            </field>
8748 
            <field>
8749 
              <name>CC4IF</name>
8750 
              <description>Capture/Compare 4 interrupt
8751 
              flag</description>
8752 
              <bitOffset>4</bitOffset>
8753 
              <bitWidth>1</bitWidth>
8754 
            </field>
8755 
            <field>
8756 
              <name>CC3IF</name>
8757 
              <description>Capture/Compare 3 interrupt
8758 
              flag</description>
8759 
              <bitOffset>3</bitOffset>
8760 
              <bitWidth>1</bitWidth>
8761 
            </field>
8762 
            <field>
8763 
              <name>CC2IF</name>
8764 
              <description>Capture/Compare 2 interrupt
8765 
              flag</description>
8766 
              <bitOffset>2</bitOffset>
8767 
              <bitWidth>1</bitWidth>
8768 
            </field>
8769 
            <field>
8770 
              <name>CC1IF</name>
8771 
              <description>Capture/compare 1 interrupt
8772 
              flag</description>
8773 
              <bitOffset>1</bitOffset>
8774 
              <bitWidth>1</bitWidth>
8775 
            </field>
8776 
            <field>
8777 
              <name>UIF</name>
8778 
              <description>Update interrupt flag</description>
8779 
              <bitOffset>0</bitOffset>
8780 
              <bitWidth>1</bitWidth>
8781 
            </field>
8782 
          </fields>
8783 
        </register>
8784 
        <register>
8785 
          <name>EGR</name>
8786 
          <displayName>EGR</displayName>
8787 
          <description>event generation register</description>
8788 
          <addressOffset>0x14</addressOffset>
8789 
          <size>0x20</size>
8790 
          <access>write-only</access>
8791 
          <resetValue>0x0000</resetValue>
8792 
          <fields>
8793 
            <field>
8794 
              <name>BG</name>
8795 
              <description>Break generation</description>
8796 
              <bitOffset>7</bitOffset>
8797 
              <bitWidth>1</bitWidth>
8798 
            </field>
8799 
            <field>
8800 
              <name>TG</name>
8801 
              <description>Trigger generation</description>
8802 
              <bitOffset>6</bitOffset>
8803 
              <bitWidth>1</bitWidth>
8804 
            </field>
8805 
            <field>
8806 
              <name>COMG</name>
8807 
              <description>Capture/Compare control update
8808 
              generation</description>
8809 
              <bitOffset>5</bitOffset>
8810 
              <bitWidth>1</bitWidth>
8811 
            </field>
8812 
            <field>
8813 
              <name>CC4G</name>
8814 
              <description>Capture/compare 4
8815 
              generation</description>
8816 
              <bitOffset>4</bitOffset>
8817 
              <bitWidth>1</bitWidth>
8818 
            </field>
8819 
            <field>
8820 
              <name>CC3G</name>
8821 
              <description>Capture/compare 3
8822 
              generation</description>
8823 
              <bitOffset>3</bitOffset>
8824 
              <bitWidth>1</bitWidth>
8825 
            </field>
8826 
            <field>
8827 
              <name>CC2G</name>
8828 
              <description>Capture/compare 2
8829 
              generation</description>
8830 
              <bitOffset>2</bitOffset>
8831 
              <bitWidth>1</bitWidth>
8832 
            </field>
8833 
            <field>
8834 
              <name>CC1G</name>
8835 
              <description>Capture/compare 1
8836 
              generation</description>
8837 
              <bitOffset>1</bitOffset>
8838 
              <bitWidth>1</bitWidth>
8839 
            </field>
8840 
            <field>
8841 
              <name>UG</name>
8842 
              <description>Update generation</description>
8843 
              <bitOffset>0</bitOffset>
8844 
              <bitWidth>1</bitWidth>
8845 
            </field>
8846 
          </fields>
8847 
        </register>
8848 
        <register>
8849 
          <name>CCMR1_Output</name>
8850 
          <displayName>CCMR1_Output</displayName>
8851 
          <description>capture/compare mode register (output
8852 
          mode)</description>
8853 
          <addressOffset>0x18</addressOffset>
8854 
          <size>0x20</size>
8855 
          <access>read-write</access>
8856 
          <resetValue>0x00000000</resetValue>
8857 
          <fields>
8858 
            <field>
8859 
              <name>OC2CE</name>
8860 
              <description>Output Compare 2 clear
8861 
              enable</description>
8862 
              <bitOffset>15</bitOffset>
8863 
              <bitWidth>1</bitWidth>
8864 
            </field>
8865 
            <field>
8866 
              <name>OC2M</name>
8867 
              <description>Output Compare 2 mode</description>
8868 
              <bitOffset>12</bitOffset>
8869 
              <bitWidth>3</bitWidth>
8870 
            </field>
8871 
            <field>
8872 
              <name>OC2PE</name>
8873 
              <description>Output Compare 2 preload
8874 
              enable</description>
8875 
              <bitOffset>11</bitOffset>
8876 
              <bitWidth>1</bitWidth>
8877 
            </field>
8878 
            <field>
8879 
              <name>OC2FE</name>
8880 
              <description>Output Compare 2 fast
8881 
              enable</description>
8882 
              <bitOffset>10</bitOffset>
8883 
              <bitWidth>1</bitWidth>
8884 
            </field>
8885 
            <field>
8886 
              <name>CC2S</name>
8887 
              <description>Capture/Compare 2
8888 
              selection</description>
8889 
              <bitOffset>8</bitOffset>
8890 
              <bitWidth>2</bitWidth>
8891 
            </field>
8892 
            <field>
8893 
              <name>OC1CE</name>
8894 
              <description>Output Compare 1 clear
8895 
              enable</description>
8896 
              <bitOffset>7</bitOffset>
8897 
              <bitWidth>1</bitWidth>
8898 
            </field>
8899 
            <field>
8900 
              <name>OC1M</name>
8901 
              <description>Output Compare 1 mode</description>
8902 
              <bitOffset>4</bitOffset>
8903 
              <bitWidth>3</bitWidth>
8904 
            </field>
8905 
            <field>
8906 
              <name>OC1PE</name>
8907 
              <description>Output Compare 1 preload
8908 
              enable</description>
8909 
              <bitOffset>3</bitOffset>
8910 
              <bitWidth>1</bitWidth>
8911 
            </field>
8912 
            <field>
8913 
              <name>OC1FE</name>
8914 
              <description>Output Compare 1 fast
8915 
              enable</description>
8916 
              <bitOffset>2</bitOffset>
8917 
              <bitWidth>1</bitWidth>
8918 
            </field>
8919 
            <field>
8920 
              <name>CC1S</name>
8921 
              <description>Capture/Compare 1
8922 
              selection</description>
8923 
              <bitOffset>0</bitOffset>
8924 
              <bitWidth>2</bitWidth>
8925 
            </field>
8926 
          </fields>
8927 
        </register>
8928 
        <register>
8929 
          <name>CCMR1_Input</name>
8930 
          <displayName>CCMR1_Input</displayName>
8931 
          <description>capture/compare mode register 1 (input
8932 
          mode)</description>
8933 
          <alternateRegister>CCMR1_Output</alternateRegister>
8934 
          <addressOffset>0x18</addressOffset>
8935 
          <size>0x20</size>
8936 
          <access>read-write</access>
8937 
          <resetValue>0x00000000</resetValue>
8938 
          <fields>
8939 
            <field>
8940 
              <name>IC2F</name>
8941 
              <description>Input capture 2 filter</description>
8942 
              <bitOffset>12</bitOffset>
8943 
              <bitWidth>4</bitWidth>
8944 
            </field>
8945 
            <field>
8946 
              <name>IC2PCS</name>
8947 
              <description>Input capture 2 prescaler</description>
8948 
              <bitOffset>10</bitOffset>
8949 
              <bitWidth>2</bitWidth>
8950 
            </field>
8951 
            <field>
8952 
              <name>CC2S</name>
8953 
              <description>Capture/Compare 2
8954 
              selection</description>
8955 
              <bitOffset>8</bitOffset>
8956 
              <bitWidth>2</bitWidth>
8957 
            </field>
8958 
            <field>
8959 
              <name>IC1F</name>
8960 
              <description>Input capture 1 filter</description>
8961 
              <bitOffset>4</bitOffset>
8962 
              <bitWidth>4</bitWidth>
8963 
            </field>
8964 
            <field>
8965 
              <name>ICPCS</name>
8966 
              <description>Input capture 1 prescaler</description>
8967 
              <bitOffset>2</bitOffset>
8968 
              <bitWidth>2</bitWidth>
8969 
            </field>
8970 
            <field>
8971 
              <name>CC1S</name>
8972 
              <description>Capture/Compare 1
8973 
              selection</description>
8974 
              <bitOffset>0</bitOffset>
8975 
              <bitWidth>2</bitWidth>
8976 
            </field>
8977 
          </fields>
8978 
        </register>
8979 
        <register>
8980 
          <name>CCMR2_Output</name>
8981 
          <displayName>CCMR2_Output</displayName>
8982 
          <description>capture/compare mode register (output
8983 
          mode)</description>
8984 
          <addressOffset>0x1C</addressOffset>
8985 
          <size>0x20</size>
8986 
          <access>read-write</access>
8987 
          <resetValue>0x00000000</resetValue>
8988 
          <fields>
8989 
            <field>
8990 
              <name>OC4CE</name>
8991 
              <description>Output compare 4 clear
8992 
              enable</description>
8993 
              <bitOffset>15</bitOffset>
8994 
              <bitWidth>1</bitWidth>
8995 
            </field>
8996 
            <field>
8997 
              <name>OC4M</name>
8998 
              <description>Output compare 4 mode</description>
8999 
              <bitOffset>12</bitOffset>
9000 
              <bitWidth>3</bitWidth>
9001 
            </field>
9002 
            <field>
9003 
              <name>OC4PE</name>
9004 
              <description>Output compare 4 preload
9005 
              enable</description>
9006 
              <bitOffset>11</bitOffset>
9007 
              <bitWidth>1</bitWidth>
9008 
            </field>
9009 
            <field>
9010 
              <name>OC4FE</name>
9011 
              <description>Output compare 4 fast
9012 
              enable</description>
9013 
              <bitOffset>10</bitOffset>
9014 
              <bitWidth>1</bitWidth>
9015 
            </field>
9016 
            <field>
9017 
              <name>CC4S</name>
9018 
              <description>Capture/Compare 4
9019 
              selection</description>
9020 
              <bitOffset>8</bitOffset>
9021 
              <bitWidth>2</bitWidth>
9022 
            </field>
9023 
            <field>
9024 
              <name>OC3CE</name>
9025 
              <description>Output compare 3 clear
9026 
              enable</description>
9027 
              <bitOffset>7</bitOffset>
9028 
              <bitWidth>1</bitWidth>
9029 
            </field>
9030 
            <field>
9031 
              <name>OC3M</name>
9032 
              <description>Output compare 3 mode</description>
9033 
              <bitOffset>4</bitOffset>
9034 
              <bitWidth>3</bitWidth>
9035 
            </field>
9036 
            <field>
9037 
              <name>OC3PE</name>
9038 
              <description>Output compare 3 preload
9039 
              enable</description>
9040 
              <bitOffset>3</bitOffset>
9041 
              <bitWidth>1</bitWidth>
9042 
            </field>
9043 
            <field>
9044 
              <name>OC3FE</name>
9045 
              <description>Output compare 3 fast
9046 
              enable</description>
9047 
              <bitOffset>2</bitOffset>
9048 
              <bitWidth>1</bitWidth>
9049 
            </field>
9050 
            <field>
9051 
              <name>CC3S</name>
9052 
              <description>Capture/Compare 3
9053 
              selection</description>
9054 
              <bitOffset>0</bitOffset>
9055 
              <bitWidth>2</bitWidth>
9056 
            </field>
9057 
          </fields>
9058 
        </register>
9059 
        <register>
9060 
          <name>CCMR2_Input</name>
9061 
          <displayName>CCMR2_Input</displayName>
9062 
          <description>capture/compare mode register 2 (input
9063 
          mode)</description>
9064 
          <alternateRegister>CCMR2_Output</alternateRegister>
9065 
          <addressOffset>0x1C</addressOffset>
9066 
          <size>0x20</size>
9067 
          <access>read-write</access>
9068 
          <resetValue>0x00000000</resetValue>
9069 
          <fields>
9070 
            <field>
9071 
              <name>IC4F</name>
9072 
              <description>Input capture 4 filter</description>
9073 
              <bitOffset>12</bitOffset>
9074 
              <bitWidth>4</bitWidth>
9075 
            </field>
9076 
            <field>
9077 
              <name>IC4PSC</name>
9078 
              <description>Input capture 4 prescaler</description>
9079 
              <bitOffset>10</bitOffset>
9080 
              <bitWidth>2</bitWidth>
9081 
            </field>
9082 
            <field>
9083 
              <name>CC4S</name>
9084 
              <description>Capture/Compare 4
9085 
              selection</description>
9086 
              <bitOffset>8</bitOffset>
9087 
              <bitWidth>2</bitWidth>
9088 
            </field>
9089 
            <field>
9090 
              <name>IC3F</name>
9091 
              <description>Input capture 3 filter</description>
9092 
              <bitOffset>4</bitOffset>
9093 
              <bitWidth>4</bitWidth>
9094 
            </field>
9095 
            <field>
9096 
              <name>IC3PSC</name>
9097 
              <description>Input capture 3 prescaler</description>
9098 
              <bitOffset>2</bitOffset>
9099 
              <bitWidth>2</bitWidth>
9100 
            </field>
9101 
            <field>
9102 
              <name>CC3S</name>
9103 
              <description>Capture/compare 3
9104 
              selection</description>
9105 
              <bitOffset>0</bitOffset>
9106 
              <bitWidth>2</bitWidth>
9107 
            </field>
9108 
          </fields>
9109 
        </register>
9110 
        <register>
9111 
          <name>CCER</name>
9112 
          <displayName>CCER</displayName>
9113 
          <description>capture/compare enable
9114 
          register</description>
9115 
          <addressOffset>0x20</addressOffset>
9116 
          <size>0x20</size>
9117 
          <access>read-write</access>
9118 
          <resetValue>0x0000</resetValue>
9119 
          <fields>
9120 
            <field>
9121 
              <name>CC4P</name>
9122 
              <description>Capture/Compare 3 output
9123 
              Polarity</description>
9124 
              <bitOffset>13</bitOffset>
9125 
              <bitWidth>1</bitWidth>
9126 
            </field>
9127 
            <field>
9128 
              <name>CC4E</name>
9129 
              <description>Capture/Compare 4 output
9130 
              enable</description>
9131 
              <bitOffset>12</bitOffset>
9132 
              <bitWidth>1</bitWidth>
9133 
            </field>
9134 
            <field>
9135 
              <name>CC3NP</name>
9136 
              <description>Capture/Compare 3 output
9137 
              Polarity</description>
9138 
              <bitOffset>11</bitOffset>
9139 
              <bitWidth>1</bitWidth>
9140 
            </field>
9141 
            <field>
9142 
              <name>CC3NE</name>
9143 
              <description>Capture/Compare 3 complementary output
9144 
              enable</description>
9145 
              <bitOffset>10</bitOffset>
9146 
              <bitWidth>1</bitWidth>
9147 
            </field>
9148 
            <field>
9149 
              <name>CC3P</name>
9150 
              <description>Capture/Compare 3 output
9151 
              Polarity</description>
9152 
              <bitOffset>9</bitOffset>
9153 
              <bitWidth>1</bitWidth>
9154 
            </field>
9155 
            <field>
9156 
              <name>CC3E</name>
9157 
              <description>Capture/Compare 3 output
9158 
              enable</description>
9159 
              <bitOffset>8</bitOffset>
9160 
              <bitWidth>1</bitWidth>
9161 
            </field>
9162 
            <field>
9163 
              <name>CC2NP</name>
9164 
              <description>Capture/Compare 2 output
9165 
              Polarity</description>
9166 
              <bitOffset>7</bitOffset>
9167 
              <bitWidth>1</bitWidth>
9168 
            </field>
9169 
            <field>
9170 
              <name>CC2NE</name>
9171 
              <description>Capture/Compare 2 complementary output
9172 
              enable</description>
9173 
              <bitOffset>6</bitOffset>
9174 
              <bitWidth>1</bitWidth>
9175 
            </field>
9176 
            <field>
9177 
              <name>CC2P</name>
9178 
              <description>Capture/Compare 2 output
9179 
              Polarity</description>
9180 
              <bitOffset>5</bitOffset>
9181 
              <bitWidth>1</bitWidth>
9182 
            </field>
9183 
            <field>
9184 
              <name>CC2E</name>
9185 
              <description>Capture/Compare 2 output
9186 
              enable</description>
9187 
              <bitOffset>4</bitOffset>
9188 
              <bitWidth>1</bitWidth>
9189 
            </field>
9190 
            <field>
9191 
              <name>CC1NP</name>
9192 
              <description>Capture/Compare 1 output
9193 
              Polarity</description>
9194 
              <bitOffset>3</bitOffset>
9195 
              <bitWidth>1</bitWidth>
9196 
            </field>
9197 
            <field>
9198 
              <name>CC1NE</name>
9199 
              <description>Capture/Compare 1 complementary output
9200 
              enable</description>
9201 
              <bitOffset>2</bitOffset>
9202 
              <bitWidth>1</bitWidth>
9203 
            </field>
9204 
            <field>
9205 
              <name>CC1P</name>
9206 
              <description>Capture/Compare 1 output
9207 
              Polarity</description>
9208 
              <bitOffset>1</bitOffset>
9209 
              <bitWidth>1</bitWidth>
9210 
            </field>
9211 
            <field>
9212 
              <name>CC1E</name>
9213 
              <description>Capture/Compare 1 output
9214 
              enable</description>
9215 
              <bitOffset>0</bitOffset>
9216 
              <bitWidth>1</bitWidth>
9217 
            </field>
9218 
          </fields>
9219 
        </register>
9220 
        <register>
9221 
          <name>CNT</name>
9222 
          <displayName>CNT</displayName>
9223 
          <description>counter</description>
9224 
          <addressOffset>0x24</addressOffset>
9225 
          <size>0x20</size>
9226 
          <access>read-write</access>
9227 
          <resetValue>0x00000000</resetValue>
9228 
          <fields>
9229 
            <field>
9230 
              <name>CNT</name>
9231 
              <description>counter value</description>
9232 
              <bitOffset>0</bitOffset>
9233 
              <bitWidth>16</bitWidth>
9234 
            </field>
9235 
          </fields>
9236 
        </register>
9237 
        <register>
9238 
          <name>PSC</name>
9239 
          <displayName>PSC</displayName>
9240 
          <description>prescaler</description>
9241 
          <addressOffset>0x28</addressOffset>
9242 
          <size>0x20</size>
9243 
          <access>read-write</access>
9244 
          <resetValue>0x0000</resetValue>
9245 
          <fields>
9246 
            <field>
9247 
              <name>PSC</name>
9248 
              <description>Prescaler value</description>
9249 
              <bitOffset>0</bitOffset>
9250 
              <bitWidth>16</bitWidth>
9251 
            </field>
9252 
          </fields>
9253 
        </register>
9254 
        <register>
9255 
          <name>ARR</name>
9256 
          <displayName>ARR</displayName>
9257 
          <description>auto-reload register</description>
9258 
          <addressOffset>0x2C</addressOffset>
9259 
          <size>0x20</size>
9260 
          <access>read-write</access>
9261 
          <resetValue>0x00000000</resetValue>
9262 
          <fields>
9263 
            <field>
9264 
              <name>ARR</name>
9265 
              <description>Auto-reload value</description>
9266 
              <bitOffset>0</bitOffset>
9267 
              <bitWidth>16</bitWidth>
9268 
            </field>
9269 
          </fields>
9270 
        </register>
9271 
        <register>
9272 
          <name>CCR1</name>
9273 
          <displayName>CCR1</displayName>
9274 
          <description>capture/compare register 1</description>
9275 
          <addressOffset>0x34</addressOffset>
9276 
          <size>0x20</size>
9277 
          <access>read-write</access>
9278 
          <resetValue>0x00000000</resetValue>
9279 
          <fields>
9280 
            <field>
9281 
              <name>CCR1</name>
9282 
              <description>Capture/Compare 1 value</description>
9283 
              <bitOffset>0</bitOffset>
9284 
              <bitWidth>16</bitWidth>
9285 
            </field>
9286 
          </fields>
9287 
        </register>
9288 
        <register>
9289 
          <name>CCR2</name>
9290 
          <displayName>CCR2</displayName>
9291 
          <description>capture/compare register 2</description>
9292 
          <addressOffset>0x38</addressOffset>
9293 
          <size>0x20</size>
9294 
          <access>read-write</access>
9295 
          <resetValue>0x00000000</resetValue>
9296 
          <fields>
9297 
            <field>
9298 
              <name>CCR2</name>
9299 
              <description>Capture/Compare 2 value</description>
9300 
              <bitOffset>0</bitOffset>
9301 
              <bitWidth>16</bitWidth>
9302 
            </field>
9303 
          </fields>
9304 
        </register>
9305 
        <register>
9306 
          <name>CCR3</name>
9307 
          <displayName>CCR3</displayName>
9308 
          <description>capture/compare register 3</description>
9309 
          <addressOffset>0x3C</addressOffset>
9310 
          <size>0x20</size>
9311 
          <access>read-write</access>
9312 
          <resetValue>0x00000000</resetValue>
9313 
          <fields>
9314 
            <field>
9315 
              <name>CCR3</name>
9316 
              <description>Capture/Compare value</description>
9317 
              <bitOffset>0</bitOffset>
9318 
              <bitWidth>16</bitWidth>
9319 
            </field>
9320 
          </fields>
9321 
        </register>
9322 
        <register>
9323 
          <name>CCR4</name>
9324 
          <displayName>CCR4</displayName>
9325 
          <description>capture/compare register 4</description>
9326 
          <addressOffset>0x40</addressOffset>
9327 
          <size>0x20</size>
9328 
          <access>read-write</access>
9329 
          <resetValue>0x00000000</resetValue>
9330 
          <fields>
9331 
            <field>
9332 
              <name>CCR4</name>
9333 
              <description>Capture/Compare value</description>
9334 
              <bitOffset>0</bitOffset>
9335 
              <bitWidth>16</bitWidth>
9336 
            </field>
9337 
          </fields>
9338 
        </register>
9339 
        <register>
9340 
          <name>DCR</name>
9341 
          <displayName>DCR</displayName>
9342 
          <description>DMA control register</description>
9343 
          <addressOffset>0x48</addressOffset>
9344 
          <size>0x20</size>
9345 
          <access>read-write</access>
9346 
          <resetValue>0x0000</resetValue>
9347 
          <fields>
9348 
            <field>
9349 
              <name>DBL</name>
9350 
              <description>DMA burst length</description>
9351 
              <bitOffset>8</bitOffset>
9352 
              <bitWidth>5</bitWidth>
9353 
            </field>
9354 
            <field>
9355 
              <name>DBA</name>
9356 
              <description>DMA base address</description>
9357 
              <bitOffset>0</bitOffset>
9358 
              <bitWidth>5</bitWidth>
9359 
            </field>
9360 
          </fields>
9361 
        </register>
9362 
        <register>
9363 
          <name>DMAR</name>
9364 
          <displayName>DMAR</displayName>
9365 
          <description>DMA address for full transfer</description>
9366 
          <addressOffset>0x4C</addressOffset>
9367 
          <size>0x20</size>
9368 
          <access>read-write</access>
9369 
          <resetValue>0x0000</resetValue>
9370 
          <fields>
9371 
            <field>
9372 
              <name>DMAB</name>
9373 
              <description>DMA register for burst
9374 
              accesses</description>
9375 
              <bitOffset>0</bitOffset>
9376 
              <bitWidth>16</bitWidth>
9377 
            </field>
9378 
          </fields>
9379 
        </register>
9380 
        <register>
9381 
          <name>RCR</name>
9382 
          <displayName>RCR</displayName>
9383 
          <description>repetition counter register</description>
9384 
          <addressOffset>0x30</addressOffset>
9385 
          <size>0x20</size>
9386 
          <access>read-write</access>
9387 
          <resetValue>0x0000</resetValue>
9388 
          <fields>
9389 
            <field>
9390 
              <name>REP</name>
9391 
              <description>Repetition counter value</description>
9392 
              <bitOffset>0</bitOffset>
9393 
              <bitWidth>8</bitWidth>
9394 
            </field>
9395 
          </fields>
9396 
        </register>
9397 
        <register>
9398 
          <name>BDTR</name>
9399 
          <displayName>BDTR</displayName>
9400 
          <description>break and dead-time register</description>
9401 
          <addressOffset>0x44</addressOffset>
9402 
          <size>0x20</size>
9403 
          <access>read-write</access>
9404 
          <resetValue>0x0000</resetValue>
9405 
          <fields>
9406 
            <field>
9407 
              <name>MOE</name>
9408 
              <description>Main output enable</description>
9409 
              <bitOffset>15</bitOffset>
9410 
              <bitWidth>1</bitWidth>
9411 
            </field>
9412 
            <field>
9413 
              <name>AOE</name>
9414 
              <description>Automatic output enable</description>
9415 
              <bitOffset>14</bitOffset>
9416 
              <bitWidth>1</bitWidth>
9417 
            </field>
9418 
            <field>
9419 
              <name>BKP</name>
9420 
              <description>Break polarity</description>
9421 
              <bitOffset>13</bitOffset>
9422 
              <bitWidth>1</bitWidth>
9423 
            </field>
9424 
            <field>
9425 
              <name>BKE</name>
9426 
              <description>Break enable</description>
9427 
              <bitOffset>12</bitOffset>
9428 
              <bitWidth>1</bitWidth>
9429 
            </field>
9430 
            <field>
9431 
              <name>OSSR</name>
9432 
              <description>Off-state selection for Run
9433 
              mode</description>
9434 
              <bitOffset>11</bitOffset>
9435 
              <bitWidth>1</bitWidth>
9436 
            </field>
9437 
            <field>
9438 
              <name>OSSI</name>
9439 
              <description>Off-state selection for Idle
9440 
              mode</description>
9441 
              <bitOffset>10</bitOffset>
9442 
              <bitWidth>1</bitWidth>
9443 
            </field>
9444 
            <field>
9445 
              <name>LOCK</name>
9446 
              <description>Lock configuration</description>
9447 
              <bitOffset>8</bitOffset>
9448 
              <bitWidth>2</bitWidth>
9449 
            </field>
9450 
            <field>
9451 
              <name>DTG</name>
9452 
              <description>Dead-time generator setup</description>
9453 
              <bitOffset>0</bitOffset>
9454 
              <bitWidth>8</bitWidth>
9455 
            </field>
9456 
          </fields>
9457 
        </register>
9458 
      </registers>
9459 
    </peripheral>
9460 
    <peripheral derivedFrom="TIM1">
9461 
      <name>TIM8</name>
9462 
      <baseAddress>0x40013400</baseAddress>
9463 
      <interrupt>
9464 
        <name>TIM8_BRK</name>
9465 
        <description>TIM8 Break interrupt</description>
9466 
        <value>43</value>
9467 
      </interrupt>
9468 
      <interrupt>
9469 
        <name>TIM8_UP</name>
9470 
        <description>TIM8 Update interrupt</description>
9471 
        <value>44</value>
9472 
      </interrupt>
9473 
      <interrupt>
9474 
        <name>TIM8_TRG_COM</name>
9475 
        <description>TIM8 Trigger and Commutation
9476 
        interrupts</description>
9477 
        <value>45</value>
9478 
      </interrupt>
9479 
      <interrupt>
9480 
        <name>TIM8_CC</name>
9481 
        <description>TIM8 Capture Compare interrupt</description>
9482 
        <value>46</value>
9483 
      </interrupt>
9484 
    </peripheral>
9485 
    <peripheral>
9486 
      <name>TIM2</name>
9487 
      <description>General purpose timer</description>
9488 
      <groupName>TIM</groupName>
9489 
      <baseAddress>0x40000000</baseAddress>
9490 
      <addressBlock>
9491 
        <offset>0x0</offset>
9492 
        <size>0x400</size>
9493 
        <usage>registers</usage>
9494 
      </addressBlock>
9495 
      <interrupt>
9496 
        <name>TIM2</name>
9497 
        <description>TIM2 global interrupt</description>
9498 
        <value>28</value>
9499 
      </interrupt>
9500 
      <registers>
9501 
        <register>
9502 
          <name>CR1</name>
9503 
          <displayName>CR1</displayName>
9504 
          <description>control register 1</description>
9505 
          <addressOffset>0x0</addressOffset>
9506 
          <size>0x20</size>
9507 
          <access>read-write</access>
9508 
          <resetValue>0x0000</resetValue>
9509 
          <fields>
9510 
            <field>
9511 
              <name>CKD</name>
9512 
              <description>Clock division</description>
9513 
              <bitOffset>8</bitOffset>
9514 
              <bitWidth>2</bitWidth>
9515 
            </field>
9516 
            <field>
9517 
              <name>ARPE</name>
9518 
              <description>Auto-reload preload enable</description>
9519 
              <bitOffset>7</bitOffset>
9520 
              <bitWidth>1</bitWidth>
9521 
            </field>
9522 
            <field>
9523 
              <name>CMS</name>
9524 
              <description>Center-aligned mode
9525 
              selection</description>
9526 
              <bitOffset>5</bitOffset>
9527 
              <bitWidth>2</bitWidth>
9528 
            </field>
9529 
            <field>
9530 
              <name>DIR</name>
9531 
              <description>Direction</description>
9532 
              <bitOffset>4</bitOffset>
9533 
              <bitWidth>1</bitWidth>
9534 
            </field>
9535 
            <field>
9536 
              <name>OPM</name>
9537 
              <description>One-pulse mode</description>
9538 
              <bitOffset>3</bitOffset>
9539 
              <bitWidth>1</bitWidth>
9540 
            </field>
9541 
            <field>
9542 
              <name>URS</name>
9543 
              <description>Update request source</description>
9544 
              <bitOffset>2</bitOffset>
9545 
              <bitWidth>1</bitWidth>
9546 
            </field>
9547 
            <field>
9548 
              <name>UDIS</name>
9549 
              <description>Update disable</description>
9550 
              <bitOffset>1</bitOffset>
9551 
              <bitWidth>1</bitWidth>
9552 
            </field>
9553 
            <field>
9554 
              <name>CEN</name>
9555 
              <description>Counter enable</description>
9556 
              <bitOffset>0</bitOffset>
9557 
              <bitWidth>1</bitWidth>
9558 
            </field>
9559 
          </fields>
9560 
        </register>
9561 
        <register>
9562 
          <name>CR2</name>
9563 
          <displayName>CR2</displayName>
9564 
          <description>control register 2</description>
9565 
          <addressOffset>0x4</addressOffset>
9566 
          <size>0x20</size>
9567 
          <access>read-write</access>
9568 
          <resetValue>0x0000</resetValue>
9569 
          <fields>
9570 
            <field>
9571 
              <name>TI1S</name>
9572 
              <description>TI1 selection</description>
9573 
              <bitOffset>7</bitOffset>
9574 
              <bitWidth>1</bitWidth>
9575 
            </field>
9576 
            <field>
9577 
              <name>MMS</name>
9578 
              <description>Master mode selection</description>
9579 
              <bitOffset>4</bitOffset>
9580 
              <bitWidth>3</bitWidth>
9581 
            </field>
9582 
            <field>
9583 
              <name>CCDS</name>
9584 
              <description>Capture/compare DMA
9585 
              selection</description>
9586 
              <bitOffset>3</bitOffset>
9587 
              <bitWidth>1</bitWidth>
9588 
            </field>
9589 
          </fields>
9590 
        </register>
9591 
        <register>
9592 
          <name>SMCR</name>
9593 
          <displayName>SMCR</displayName>
9594 
          <description>slave mode control register</description>
9595 
          <addressOffset>0x8</addressOffset>
9596 
          <size>0x20</size>
9597 
          <access>read-write</access>
9598 
          <resetValue>0x0000</resetValue>
9599 
          <fields>
9600 
            <field>
9601 
              <name>ETP</name>
9602 
              <description>External trigger polarity</description>
9603 
              <bitOffset>15</bitOffset>
9604 
              <bitWidth>1</bitWidth>
9605 
            </field>
9606 
            <field>
9607 
              <name>ECE</name>
9608 
              <description>External clock enable</description>
9609 
              <bitOffset>14</bitOffset>
9610 
              <bitWidth>1</bitWidth>
9611 
            </field>
9612 
            <field>
9613 
              <name>ETPS</name>
9614 
              <description>External trigger prescaler</description>
9615 
              <bitOffset>12</bitOffset>
9616 
              <bitWidth>2</bitWidth>
9617 
            </field>
9618 
            <field>
9619 
              <name>ETF</name>
9620 
              <description>External trigger filter</description>
9621 
              <bitOffset>8</bitOffset>
9622 
              <bitWidth>4</bitWidth>
9623 
            </field>
9624 
            <field>
9625 
              <name>MSM</name>
9626 
              <description>Master/Slave mode</description>
9627 
              <bitOffset>7</bitOffset>
9628 
              <bitWidth>1</bitWidth>
9629 
            </field>
9630 
            <field>
9631 
              <name>TS</name>
9632 
              <description>Trigger selection</description>
9633 
              <bitOffset>4</bitOffset>
9634 
              <bitWidth>3</bitWidth>
9635 
            </field>
9636 
            <field>
9637 
              <name>SMS</name>
9638 
              <description>Slave mode selection</description>
9639 
              <bitOffset>0</bitOffset>
9640 
              <bitWidth>3</bitWidth>
9641 
            </field>
9642 
          </fields>
9643 
        </register>
9644 
        <register>
9645 
          <name>DIER</name>
9646 
          <displayName>DIER</displayName>
9647 
          <description>DMA/Interrupt enable register</description>
9648 
          <addressOffset>0xC</addressOffset>
9649 
          <size>0x20</size>
9650 
          <access>read-write</access>
9651 
          <resetValue>0x0000</resetValue>
9652 
          <fields>
9653 
            <field>
9654 
              <name>TDE</name>
9655 
              <description>Trigger DMA request enable</description>
9656 
              <bitOffset>14</bitOffset>
9657 
              <bitWidth>1</bitWidth>
9658 
            </field>
9659 
            <field>
9660 
              <name>CC4DE</name>
9661 
              <description>Capture/Compare 4 DMA request
9662 
              enable</description>
9663 
              <bitOffset>12</bitOffset>
9664 
              <bitWidth>1</bitWidth>
9665 
            </field>
9666 
            <field>
9667 
              <name>CC3DE</name>
9668 
              <description>Capture/Compare 3 DMA request
9669 
              enable</description>
9670 
              <bitOffset>11</bitOffset>
9671 
              <bitWidth>1</bitWidth>
9672 
            </field>
9673 
            <field>
9674 
              <name>CC2DE</name>
9675 
              <description>Capture/Compare 2 DMA request
9676 
              enable</description>
9677 
              <bitOffset>10</bitOffset>
9678 
              <bitWidth>1</bitWidth>
9679 
            </field>
9680 
            <field>
9681 
              <name>CC1DE</name>
9682 
              <description>Capture/Compare 1 DMA request
9683 
              enable</description>
9684 
              <bitOffset>9</bitOffset>
9685 
              <bitWidth>1</bitWidth>
9686 
            </field>
9687 
            <field>
9688 
              <name>UDE</name>
9689 
              <description>Update DMA request enable</description>
9690 
              <bitOffset>8</bitOffset>
9691 
              <bitWidth>1</bitWidth>
9692 
            </field>
9693 
            <field>
9694 
              <name>TIE</name>
9695 
              <description>Trigger interrupt enable</description>
9696 
              <bitOffset>6</bitOffset>
9697 
              <bitWidth>1</bitWidth>
9698 
            </field>
9699 
            <field>
9700 
              <name>CC4IE</name>
9701 
              <description>Capture/Compare 4 interrupt
9702 
              enable</description>
9703 
              <bitOffset>4</bitOffset>
9704 
              <bitWidth>1</bitWidth>
9705 
            </field>
9706 
            <field>
9707 
              <name>CC3IE</name>
9708 
              <description>Capture/Compare 3 interrupt
9709 
              enable</description>
9710 
              <bitOffset>3</bitOffset>
9711 
              <bitWidth>1</bitWidth>
9712 
            </field>
9713 
            <field>
9714 
              <name>CC2IE</name>
9715 
              <description>Capture/Compare 2 interrupt
9716 
              enable</description>
9717 
              <bitOffset>2</bitOffset>
9718 
              <bitWidth>1</bitWidth>
9719 
            </field>
9720 
            <field>
9721 
              <name>CC1IE</name>
9722 
              <description>Capture/Compare 1 interrupt
9723 
              enable</description>
9724 
              <bitOffset>1</bitOffset>
9725 
              <bitWidth>1</bitWidth>
9726 
            </field>
9727 
            <field>
9728 
              <name>UIE</name>
9729 
              <description>Update interrupt enable</description>
9730 
              <bitOffset>0</bitOffset>
9731 
              <bitWidth>1</bitWidth>
9732 
            </field>
9733 
          </fields>
9734 
        </register>
9735 
        <register>
9736 
          <name>SR</name>
9737 
          <displayName>SR</displayName>
9738 
          <description>status register</description>
9739 
          <addressOffset>0x10</addressOffset>
9740 
          <size>0x20</size>
9741 
          <access>read-write</access>
9742 
          <resetValue>0x0000</resetValue>
9743 
          <fields>
9744 
            <field>
9745 
              <name>CC4OF</name>
9746 
              <description>Capture/Compare 4 overcapture
9747 
              flag</description>
9748 
              <bitOffset>12</bitOffset>
9749 
              <bitWidth>1</bitWidth>
9750 
            </field>
9751 
            <field>
9752 
              <name>CC3OF</name>
9753 
              <description>Capture/Compare 3 overcapture
9754 
              flag</description>
9755 
              <bitOffset>11</bitOffset>
9756 
              <bitWidth>1</bitWidth>
9757 
            </field>
9758 
            <field>
9759 
              <name>CC2OF</name>
9760 
              <description>Capture/compare 2 overcapture
9761 
              flag</description>
9762 
              <bitOffset>10</bitOffset>
9763 
              <bitWidth>1</bitWidth>
9764 
            </field>
9765 
            <field>
9766 
              <name>CC1OF</name>
9767 
              <description>Capture/Compare 1 overcapture
9768 
              flag</description>
9769 
              <bitOffset>9</bitOffset>
9770 
              <bitWidth>1</bitWidth>
9771 
            </field>
9772 
            <field>
9773 
              <name>TIF</name>
9774 
              <description>Trigger interrupt flag</description>
9775 
              <bitOffset>6</bitOffset>
9776 
              <bitWidth>1</bitWidth>
9777 
            </field>
9778 
            <field>
9779 
              <name>CC4IF</name>
9780 
              <description>Capture/Compare 4 interrupt
9781 
              flag</description>
9782 
              <bitOffset>4</bitOffset>
9783 
              <bitWidth>1</bitWidth>
9784 
            </field>
9785 
            <field>
9786 
              <name>CC3IF</name>
9787 
              <description>Capture/Compare 3 interrupt
9788 
              flag</description>
9789 
              <bitOffset>3</bitOffset>
9790 
              <bitWidth>1</bitWidth>
9791 
            </field>
9792 
            <field>
9793 
              <name>CC2IF</name>
9794 
              <description>Capture/Compare 2 interrupt
9795 
              flag</description>
9796 
              <bitOffset>2</bitOffset>
9797 
              <bitWidth>1</bitWidth>
9798 
            </field>
9799 
            <field>
9800 
              <name>CC1IF</name>
9801 
              <description>Capture/compare 1 interrupt
9802 
              flag</description>
9803 
              <bitOffset>1</bitOffset>
9804 
              <bitWidth>1</bitWidth>
9805 
            </field>
9806 
            <field>
9807 
              <name>UIF</name>
9808 
              <description>Update interrupt flag</description>
9809 
              <bitOffset>0</bitOffset>
9810 
              <bitWidth>1</bitWidth>
9811 
            </field>
9812 
          </fields>
9813 
        </register>
9814 
        <register>
9815 
          <name>EGR</name>
9816 
          <displayName>EGR</displayName>
9817 
          <description>event generation register</description>
9818 
          <addressOffset>0x14</addressOffset>
9819 
          <size>0x20</size>
9820 
          <access>write-only</access>
9821 
          <resetValue>0x0000</resetValue>
9822 
          <fields>
9823 
            <field>
9824 
              <name>TG</name>
9825 
              <description>Trigger generation</description>
9826 
              <bitOffset>6</bitOffset>
9827 
              <bitWidth>1</bitWidth>
9828 
            </field>
9829 
            <field>
9830 
              <name>CC4G</name>
9831 
              <description>Capture/compare 4
9832 
              generation</description>
9833 
              <bitOffset>4</bitOffset>
9834 
              <bitWidth>1</bitWidth>
9835 
            </field>
9836 
            <field>
9837 
              <name>CC3G</name>
9838 
              <description>Capture/compare 3
9839 
              generation</description>
9840 
              <bitOffset>3</bitOffset>
9841 
              <bitWidth>1</bitWidth>
9842 
            </field>
9843 
            <field>
9844 
              <name>CC2G</name>
9845 
              <description>Capture/compare 2
9846 
              generation</description>
9847 
              <bitOffset>2</bitOffset>
9848 
              <bitWidth>1</bitWidth>
9849 
            </field>
9850 
            <field>
9851 
              <name>CC1G</name>
9852 
              <description>Capture/compare 1
9853 
              generation</description>
9854 
              <bitOffset>1</bitOffset>
9855 
              <bitWidth>1</bitWidth>
9856 
            </field>
9857 
            <field>
9858 
              <name>UG</name>
9859 
              <description>Update generation</description>
9860 
              <bitOffset>0</bitOffset>
9861 
              <bitWidth>1</bitWidth>
9862 
            </field>
9863 
          </fields>
9864 
        </register>
9865 
        <register>
9866 
          <name>CCMR1_Output</name>
9867 
          <displayName>CCMR1_Output</displayName>
9868 
          <description>capture/compare mode register 1 (output
9869 
          mode)</description>
9870 
          <addressOffset>0x18</addressOffset>
9871 
          <size>0x20</size>
9872 
          <access>read-write</access>
9873 
          <resetValue>0x00000000</resetValue>
9874 
          <fields>
9875 
            <field>
9876 
              <name>OC2CE</name>
9877 
              <description>Output compare 2 clear
9878 
              enable</description>
9879 
              <bitOffset>15</bitOffset>
9880 
              <bitWidth>1</bitWidth>
9881 
            </field>
9882 
            <field>
9883 
              <name>OC2M</name>
9884 
              <description>Output compare 2 mode</description>
9885 
              <bitOffset>12</bitOffset>
9886 
              <bitWidth>3</bitWidth>
9887 
            </field>
9888 
            <field>
9889 
              <name>OC2PE</name>
9890 
              <description>Output compare 2 preload
9891 
              enable</description>
9892 
              <bitOffset>11</bitOffset>
9893 
              <bitWidth>1</bitWidth>
9894 
            </field>
9895 
            <field>
9896 
              <name>OC2FE</name>
9897 
              <description>Output compare 2 fast
9898 
              enable</description>
9899 
              <bitOffset>10</bitOffset>
9900 
              <bitWidth>1</bitWidth>
9901 
            </field>
9902 
            <field>
9903 
              <name>CC2S</name>
9904 
              <description>Capture/Compare 2
9905 
              selection</description>
9906 
              <bitOffset>8</bitOffset>
9907 
              <bitWidth>2</bitWidth>
9908 
            </field>
9909 
            <field>
9910 
              <name>OC1CE</name>
9911 
              <description>Output compare 1 clear
9912 
              enable</description>
9913 
              <bitOffset>7</bitOffset>
9914 
              <bitWidth>1</bitWidth>
9915 
            </field>
9916 
            <field>
9917 
              <name>OC1M</name>
9918 
              <description>Output compare 1 mode</description>
9919 
              <bitOffset>4</bitOffset>
9920 
              <bitWidth>3</bitWidth>
9921 
            </field>
9922 
            <field>
9923 
              <name>OC1PE</name>
9924 
              <description>Output compare 1 preload
9925 
              enable</description>
9926 
              <bitOffset>3</bitOffset>
9927 
              <bitWidth>1</bitWidth>
9928 
            </field>
9929 
            <field>
9930 
              <name>OC1FE</name>
9931 
              <description>Output compare 1 fast
9932 
              enable</description>
9933 
              <bitOffset>2</bitOffset>
9934 
              <bitWidth>1</bitWidth>
9935 
            </field>
9936 
            <field>
9937 
              <name>CC1S</name>
9938 
              <description>Capture/Compare 1
9939 
              selection</description>
9940 
              <bitOffset>0</bitOffset>
9941 
              <bitWidth>2</bitWidth>
9942 
            </field>
9943 
          </fields>
9944 
        </register>
9945 
        <register>
9946 
          <name>CCMR1_Input</name>
9947 
          <displayName>CCMR1_Input</displayName>
9948 
          <description>capture/compare mode register 1 (input
9949 
          mode)</description>
9950 
          <alternateRegister>CCMR1_Output</alternateRegister>
9951 
          <addressOffset>0x18</addressOffset>
9952 
          <size>0x20</size>
9953 
          <access>read-write</access>
9954 
          <resetValue>0x00000000</resetValue>
9955 
          <fields>
9956 
            <field>
9957 
              <name>IC2F</name>
9958 
              <description>Input capture 2 filter</description>
9959 
              <bitOffset>12</bitOffset>
9960 
              <bitWidth>4</bitWidth>
9961 
            </field>
9962 
            <field>
9963 
              <name>IC2PSC</name>
9964 
              <description>Input capture 2 prescaler</description>
9965 
              <bitOffset>10</bitOffset>
9966 
              <bitWidth>2</bitWidth>
9967 
            </field>
9968 
            <field>
9969 
              <name>CC2S</name>
9970 
              <description>Capture/compare 2
9971 
              selection</description>
9972 
              <bitOffset>8</bitOffset>
9973 
              <bitWidth>2</bitWidth>
9974 
            </field>
9975 
            <field>
9976 
              <name>IC1F</name>
9977 
              <description>Input capture 1 filter</description>
9978 
              <bitOffset>4</bitOffset>
9979 
              <bitWidth>4</bitWidth>
9980 
            </field>
9981 
            <field>
9982 
              <name>IC1PSC</name>
9983 
              <description>Input capture 1 prescaler</description>
9984 
              <bitOffset>2</bitOffset>
9985 
              <bitWidth>2</bitWidth>
9986 
            </field>
9987 
            <field>
9988 
              <name>CC1S</name>
9989 
              <description>Capture/Compare 1
9990 
              selection</description>
9991 
              <bitOffset>0</bitOffset>
9992 
              <bitWidth>2</bitWidth>
9993 
            </field>
9994 
          </fields>
9995 
        </register>
9996 
        <register>
9997 
          <name>CCMR2_Output</name>
9998 
          <displayName>CCMR2_Output</displayName>
9999 
          <description>capture/compare mode register 2 (output
10000 
          mode)</description>
10001 
          <addressOffset>0x1C</addressOffset>
10002 
          <size>0x20</size>
10003 
          <access>read-write</access>
10004 
          <resetValue>0x00000000</resetValue>
10005 
          <fields>
10006 
            <field>
10007 
              <name>O24CE</name>
10008 
              <description>Output compare 4 clear
10009 
              enable</description>
10010 
              <bitOffset>15</bitOffset>
10011 
              <bitWidth>1</bitWidth>
10012 
            </field>
10013 
            <field>
10014 
              <name>OC4M</name>
10015 
              <description>Output compare 4 mode</description>
10016 
              <bitOffset>12</bitOffset>
10017 
              <bitWidth>3</bitWidth>
10018 
            </field>
10019 
            <field>
10020 
              <name>OC4PE</name>
10021 
              <description>Output compare 4 preload
10022 
              enable</description>
10023 
              <bitOffset>11</bitOffset>
10024 
              <bitWidth>1</bitWidth>
10025 
            </field>
10026 
            <field>
10027 
              <name>OC4FE</name>
10028 
              <description>Output compare 4 fast
10029 
              enable</description>
10030 
              <bitOffset>10</bitOffset>
10031 
              <bitWidth>1</bitWidth>
10032 
            </field>
10033 
            <field>
10034 
              <name>CC4S</name>
10035 
              <description>Capture/Compare 4
10036 
              selection</description>
10037 
              <bitOffset>8</bitOffset>
10038 
              <bitWidth>2</bitWidth>
10039 
            </field>
10040 
            <field>
10041 
              <name>OC3CE</name>
10042 
              <description>Output compare 3 clear
10043 
              enable</description>
10044 
              <bitOffset>7</bitOffset>
10045 
              <bitWidth>1</bitWidth>
10046 
            </field>
10047 
            <field>
10048 
              <name>OC3M</name>
10049 
              <description>Output compare 3 mode</description>
10050 
              <bitOffset>4</bitOffset>
10051 
              <bitWidth>3</bitWidth>
10052 
            </field>
10053 
            <field>
10054 
              <name>OC3PE</name>
10055 
              <description>Output compare 3 preload
10056 
              enable</description>
10057 
              <bitOffset>3</bitOffset>
10058 
              <bitWidth>1</bitWidth>
10059 
            </field>
10060 
            <field>
10061 
              <name>OC3FE</name>
10062 
              <description>Output compare 3 fast
10063 
              enable</description>
10064 
              <bitOffset>2</bitOffset>
10065 
              <bitWidth>1</bitWidth>
10066 
            </field>
10067 
            <field>
10068 
              <name>CC3S</name>
10069 
              <description>Capture/Compare 3
10070 
              selection</description>
10071 
              <bitOffset>0</bitOffset>
10072 
              <bitWidth>2</bitWidth>
10073 
            </field>
10074 
          </fields>
10075 
        </register>
10076 
        <register>
10077 
          <name>CCMR2_Input</name>
10078 
          <displayName>CCMR2_Input</displayName>
10079 
          <description>capture/compare mode register 2 (input
10080 
          mode)</description>
10081 
          <alternateRegister>CCMR2_Output</alternateRegister>
10082 
          <addressOffset>0x1C</addressOffset>
10083 
          <size>0x20</size>
10084 
          <access>read-write</access>
10085 
          <resetValue>0x00000000</resetValue>
10086 
          <fields>
10087 
            <field>
10088 
              <name>IC4F</name>
10089 
              <description>Input capture 4 filter</description>
10090 
              <bitOffset>12</bitOffset>
10091 
              <bitWidth>4</bitWidth>
10092 
            </field>
10093 
            <field>
10094 
              <name>IC4PSC</name>
10095 
              <description>Input capture 4 prescaler</description>
10096 
              <bitOffset>10</bitOffset>
10097 
              <bitWidth>2</bitWidth>
10098 
            </field>
10099 
            <field>
10100 
              <name>CC4S</name>
10101 
              <description>Capture/Compare 4
10102 
              selection</description>
10103 
              <bitOffset>8</bitOffset>
10104 
              <bitWidth>2</bitWidth>
10105 
            </field>
10106 
            <field>
10107 
              <name>IC3F</name>
10108 
              <description>Input capture 3 filter</description>
10109 
              <bitOffset>4</bitOffset>
10110 
              <bitWidth>4</bitWidth>
10111 
            </field>
10112 
            <field>
10113 
              <name>IC3PSC</name>
10114 
              <description>Input capture 3 prescaler</description>
10115 
              <bitOffset>2</bitOffset>
10116 
              <bitWidth>2</bitWidth>
10117 
            </field>
10118 
            <field>
10119 
              <name>CC3S</name>
10120 
              <description>Capture/Compare 3
10121 
              selection</description>
10122 
              <bitOffset>0</bitOffset>
10123 
              <bitWidth>2</bitWidth>
10124 
            </field>
10125 
          </fields>
10126 
        </register>
10127 
        <register>
10128 
          <name>CCER</name>
10129 
          <displayName>CCER</displayName>
10130 
          <description>capture/compare enable
10131 
          register</description>
10132 
          <addressOffset>0x20</addressOffset>
10133 
          <size>0x20</size>
10134 
          <access>read-write</access>
10135 
          <resetValue>0x0000</resetValue>
10136 
          <fields>
10137 
            <field>
10138 
              <name>CC4P</name>
10139 
              <description>Capture/Compare 3 output
10140 
              Polarity</description>
10141 
              <bitOffset>13</bitOffset>
10142 
              <bitWidth>1</bitWidth>
10143 
            </field>
10144 
            <field>
10145 
              <name>CC4E</name>
10146 
              <description>Capture/Compare 4 output
10147 
              enable</description>
10148 
              <bitOffset>12</bitOffset>
10149 
              <bitWidth>1</bitWidth>
10150 
            </field>
10151 
            <field>
10152 
              <name>CC3P</name>
10153 
              <description>Capture/Compare 3 output
10154 
              Polarity</description>
10155 
              <bitOffset>9</bitOffset>
10156 
              <bitWidth>1</bitWidth>
10157 
            </field>
10158 
            <field>
10159 
              <name>CC3E</name>
10160 
              <description>Capture/Compare 3 output
10161 
              enable</description>
10162 
              <bitOffset>8</bitOffset>
10163 
              <bitWidth>1</bitWidth>
10164 
            </field>
10165 
            <field>
10166 
              <name>CC2P</name>
10167 
              <description>Capture/Compare 2 output
10168 
              Polarity</description>
10169 
              <bitOffset>5</bitOffset>
10170 
              <bitWidth>1</bitWidth>
10171 
            </field>
10172 
            <field>
10173 
              <name>CC2E</name>
10174 
              <description>Capture/Compare 2 output
10175 
              enable</description>
10176 
              <bitOffset>4</bitOffset>
10177 
              <bitWidth>1</bitWidth>
10178 
            </field>
10179 
            <field>
10180 
              <name>CC1P</name>
10181 
              <description>Capture/Compare 1 output
10182 
              Polarity</description>
10183 
              <bitOffset>1</bitOffset>
10184 
              <bitWidth>1</bitWidth>
10185 
            </field>
10186 
            <field>
10187 
              <name>CC1E</name>
10188 
              <description>Capture/Compare 1 output
10189 
              enable</description>
10190 
              <bitOffset>0</bitOffset>
10191 
              <bitWidth>1</bitWidth>
10192 
            </field>
10193 
          </fields>
10194 
        </register>
10195 
        <register>
10196 
          <name>CNT</name>
10197 
          <displayName>CNT</displayName>
10198 
          <description>counter</description>
10199 
          <addressOffset>0x24</addressOffset>
10200 
          <size>0x20</size>
10201 
          <access>read-write</access>
10202 
          <resetValue>0x00000000</resetValue>
10203 
          <fields>
10204 
            <field>
10205 
              <name>CNT</name>
10206 
              <description>counter value</description>
10207 
              <bitOffset>0</bitOffset>
10208 
              <bitWidth>16</bitWidth>
10209 
            </field>
10210 
          </fields>
10211 
        </register>
10212 
        <register>
10213 
          <name>PSC</name>
10214 
          <displayName>PSC</displayName>
10215 
          <description>prescaler</description>
10216 
          <addressOffset>0x28</addressOffset>
10217 
          <size>0x20</size>
10218 
          <access>read-write</access>
10219 
          <resetValue>0x0000</resetValue>
10220 
          <fields>
10221 
            <field>
10222 
              <name>PSC</name>
10223 
              <description>Prescaler value</description>
10224 
              <bitOffset>0</bitOffset>
10225 
              <bitWidth>16</bitWidth>
10226 
            </field>
10227 
          </fields>
10228 
        </register>
10229 
        <register>
10230 
          <name>ARR</name>
10231 
          <displayName>ARR</displayName>
10232 
          <description>auto-reload register</description>
10233 
          <addressOffset>0x2C</addressOffset>
10234 
          <size>0x20</size>
10235 
          <access>read-write</access>
10236 
          <resetValue>0x00000000</resetValue>
10237 
          <fields>
10238 
            <field>
10239 
              <name>ARR</name>
10240 
              <description>Auto-reload value</description>
10241 
              <bitOffset>0</bitOffset>
10242 
              <bitWidth>16</bitWidth>
10243 
            </field>
10244 
          </fields>
10245 
        </register>
10246 
        <register>
10247 
          <name>CCR1</name>
10248 
          <displayName>CCR1</displayName>
10249 
          <description>capture/compare register 1</description>
10250 
          <addressOffset>0x34</addressOffset>
10251 
          <size>0x20</size>
10252 
          <access>read-write</access>
10253 
          <resetValue>0x00000000</resetValue>
10254 
          <fields>
10255 
            <field>
10256 
              <name>CCR1</name>
10257 
              <description>Capture/Compare 1 value</description>
10258 
              <bitOffset>0</bitOffset>
10259 
              <bitWidth>16</bitWidth>
10260 
            </field>
10261 
          </fields>
10262 
        </register>
10263 
        <register>
10264 
          <name>CCR2</name>
10265 
          <displayName>CCR2</displayName>
10266 
          <description>capture/compare register 2</description>
10267 
          <addressOffset>0x38</addressOffset>
10268 
          <size>0x20</size>
10269 
          <access>read-write</access>
10270 
          <resetValue>0x00000000</resetValue>
10271 
          <fields>
10272 
            <field>
10273 
              <name>CCR2</name>
10274 
              <description>Capture/Compare 2 value</description>
10275 
              <bitOffset>0</bitOffset>
10276 
              <bitWidth>16</bitWidth>
10277 
            </field>
10278 
          </fields>
10279 
        </register>
10280 
        <register>
10281 
          <name>CCR3</name>
10282 
          <displayName>CCR3</displayName>
10283 
          <description>capture/compare register 3</description>
10284 
          <addressOffset>0x3C</addressOffset>
10285 
          <size>0x20</size>
10286 
          <access>read-write</access>
10287 
          <resetValue>0x00000000</resetValue>
10288 
          <fields>
10289 
            <field>
10290 
              <name>CCR3</name>
10291 
              <description>Capture/Compare value</description>
10292 
              <bitOffset>0</bitOffset>
10293 
              <bitWidth>16</bitWidth>
10294 
            </field>
10295 
          </fields>
10296 
        </register>
10297 
        <register>
10298 
          <name>CCR4</name>
10299 
          <displayName>CCR4</displayName>
10300 
          <description>capture/compare register 4</description>
10301 
          <addressOffset>0x40</addressOffset>
10302 
          <size>0x20</size>
10303 
          <access>read-write</access>
10304 
          <resetValue>0x00000000</resetValue>
10305 
          <fields>
10306 
            <field>
10307 
              <name>CCR4</name>
10308 
              <description>Capture/Compare value</description>
10309 
              <bitOffset>0</bitOffset>
10310 
              <bitWidth>16</bitWidth>
10311 
            </field>
10312 
          </fields>
10313 
        </register>
10314 
        <register>
10315 
          <name>DCR</name>
10316 
          <displayName>DCR</displayName>
10317 
          <description>DMA control register</description>
10318 
          <addressOffset>0x48</addressOffset>
10319 
          <size>0x20</size>
10320 
          <access>read-write</access>
10321 
          <resetValue>0x0000</resetValue>
10322 
          <fields>
10323 
            <field>
10324 
              <name>DBL</name>
10325 
              <description>DMA burst length</description>
10326 
              <bitOffset>8</bitOffset>
10327 
              <bitWidth>5</bitWidth>
10328 
            </field>
10329 
            <field>
10330 
              <name>DBA</name>
10331 
              <description>DMA base address</description>
10332 
              <bitOffset>0</bitOffset>
10333 
              <bitWidth>5</bitWidth>
10334 
            </field>
10335 
          </fields>
10336 
        </register>
10337 
        <register>
10338 
          <name>DMAR</name>
10339 
          <displayName>DMAR</displayName>
10340 
          <description>DMA address for full transfer</description>
10341 
          <addressOffset>0x4C</addressOffset>
10342 
          <size>0x20</size>
10343 
          <access>read-write</access>
10344 
          <resetValue>0x0000</resetValue>
10345 
          <fields>
10346 
            <field>
10347 
              <name>DMAB</name>
10348 
              <description>DMA register for burst
10349 
              accesses</description>
10350 
              <bitOffset>0</bitOffset>
10351 
              <bitWidth>16</bitWidth>
10352 
            </field>
10353 
          </fields>
10354 
        </register>
10355 
      </registers>
10356 
    </peripheral>
10357 
    <peripheral derivedFrom="TIM2">
10358 
      <name>TIM3</name>
10359 
      <baseAddress>0x40000400</baseAddress>
10360 
      <interrupt>
10361 
        <name>TIM3</name>
10362 
        <description>TIM3 global interrupt</description>
10363 
        <value>29</value>
10364 
      </interrupt>
10365 
    </peripheral>
10366 
    <peripheral derivedFrom="TIM2">
10367 
      <name>TIM4</name>
10368 
      <baseAddress>0x40000800</baseAddress>
10369 
      <interrupt>
10370 
        <name>TIM4</name>
10371 
        <description>TIM4 global interrupt</description>
10372 
        <value>30</value>
10373 
      </interrupt>
10374 
    </peripheral>
10375 
    <peripheral derivedFrom="TIM2">
10376 
      <name>TIM5</name>
10377 
      <baseAddress>0x40000C00</baseAddress>
10378 
      <interrupt>
10379 
        <name>TIM5</name>
10380 
        <description>TIM5 global interrupt</description>
10381 
        <value>50</value>
10382 
      </interrupt>
10383 
    </peripheral>
10384 
    <peripheral>
10385 
      <name>TIM9</name>
10386 
      <description>General purpose timer</description>
10387 
      <groupName>TIM</groupName>
10388 
      <baseAddress>0x40014C00</baseAddress>
10389 
      <addressBlock>
10390 
        <offset>0x0</offset>
10391 
        <size>0x400</size>
10392 
        <usage>registers</usage>
10393 
      </addressBlock>
10394 
      <registers>
10395 
        <register>
10396 
          <name>CR1</name>
10397 
          <displayName>CR1</displayName>
10398 
          <description>control register 1</description>
10399 
          <addressOffset>0x0</addressOffset>
10400 
          <size>0x20</size>
10401 
          <access>read-write</access>
10402 
          <resetValue>0x0000</resetValue>
10403 
          <fields>
10404 
            <field>
10405 
              <name>CKD</name>
10406 
              <description>Clock division</description>
10407 
              <bitOffset>8</bitOffset>
10408 
              <bitWidth>2</bitWidth>
10409 
            </field>
10410 
            <field>
10411 
              <name>ARPE</name>
10412 
              <description>Auto-reload preload enable</description>
10413 
              <bitOffset>7</bitOffset>
10414 
              <bitWidth>1</bitWidth>
10415 
            </field>
10416 
            <field>
10417 
              <name>OPM</name>
10418 
              <description>One-pulse mode</description>
10419 
              <bitOffset>3</bitOffset>
10420 
              <bitWidth>1</bitWidth>
10421 
            </field>
10422 
            <field>
10423 
              <name>URS</name>
10424 
              <description>Update request source</description>
10425 
              <bitOffset>2</bitOffset>
10426 
              <bitWidth>1</bitWidth>
10427 
            </field>
10428 
            <field>
10429 
              <name>UDIS</name>
10430 
              <description>Update disable</description>
10431 
              <bitOffset>1</bitOffset>
10432 
              <bitWidth>1</bitWidth>
10433 
            </field>
10434 
            <field>
10435 
              <name>CEN</name>
10436 
              <description>Counter enable</description>
10437 
              <bitOffset>0</bitOffset>
10438 
              <bitWidth>1</bitWidth>
10439 
            </field>
10440 
          </fields>
10441 
        </register>
10442 
        <register>
10443 
          <name>CR2</name>
10444 
          <displayName>CR2</displayName>
10445 
          <description>control register 2</description>
10446 
          <addressOffset>0x4</addressOffset>
10447 
          <size>0x20</size>
10448 
          <access>read-write</access>
10449 
          <resetValue>0x0000</resetValue>
10450 
          <fields>
10451 
            <field>
10452 
              <name>MMS</name>
10453 
              <description>Master mode selection</description>
10454 
              <bitOffset>4</bitOffset>
10455 
              <bitWidth>3</bitWidth>
10456 
            </field>
10457 
          </fields>
10458 
        </register>
10459 
        <register>
10460 
          <name>SMCR</name>
10461 
          <displayName>SMCR</displayName>
10462 
          <description>slave mode control register</description>
10463 
          <addressOffset>0x8</addressOffset>
10464 
          <size>0x20</size>
10465 
          <access>read-write</access>
10466 
          <resetValue>0x0000</resetValue>
10467 
          <fields>
10468 
            <field>
10469 
              <name>MSM</name>
10470 
              <description>Master/Slave mode</description>
10471 
              <bitOffset>7</bitOffset>
10472 
              <bitWidth>1</bitWidth>
10473 
            </field>
10474 
            <field>
10475 
              <name>TS</name>
10476 
              <description>Trigger selection</description>
10477 
              <bitOffset>4</bitOffset>
10478 
              <bitWidth>3</bitWidth>
10479 
            </field>
10480 
            <field>
10481 
              <name>SMS</name>
10482 
              <description>Slave mode selection</description>
10483 
              <bitOffset>0</bitOffset>
10484 
              <bitWidth>3</bitWidth>
10485 
            </field>
10486 
          </fields>
10487 
        </register>
10488 
        <register>
10489 
          <name>DIER</name>
10490 
          <displayName>DIER</displayName>
10491 
          <description>DMA/Interrupt enable register</description>
10492 
          <addressOffset>0xC</addressOffset>
10493 
          <size>0x20</size>
10494 
          <access>read-write</access>
10495 
          <resetValue>0x0000</resetValue>
10496 
          <fields>
10497 
            <field>
10498 
              <name>TIE</name>
10499 
              <description>Trigger interrupt enable</description>
10500 
              <bitOffset>6</bitOffset>
10501 
              <bitWidth>1</bitWidth>
10502 
            </field>
10503 
            <field>
10504 
              <name>CC2IE</name>
10505 
              <description>Capture/Compare 2 interrupt
10506 
              enable</description>
10507 
              <bitOffset>2</bitOffset>
10508 
              <bitWidth>1</bitWidth>
10509 
            </field>
10510 
            <field>
10511 
              <name>CC1IE</name>
10512 
              <description>Capture/Compare 1 interrupt
10513 
              enable</description>
10514 
              <bitOffset>1</bitOffset>
10515 
              <bitWidth>1</bitWidth>
10516 
            </field>
10517 
            <field>
10518 
              <name>UIE</name>
10519 
              <description>Update interrupt enable</description>
10520 
              <bitOffset>0</bitOffset>
10521 
              <bitWidth>1</bitWidth>
10522 
            </field>
10523 
          </fields>
10524 
        </register>
10525 
        <register>
10526 
          <name>SR</name>
10527 
          <displayName>SR</displayName>
10528 
          <description>status register</description>
10529 
          <addressOffset>0x10</addressOffset>
10530 
          <size>0x20</size>
10531 
          <access>read-write</access>
10532 
          <resetValue>0x0000</resetValue>
10533 
          <fields>
10534 
            <field>
10535 
              <name>CC2OF</name>
10536 
              <description>Capture/compare 2 overcapture
10537 
              flag</description>
10538 
              <bitOffset>10</bitOffset>
10539 
              <bitWidth>1</bitWidth>
10540 
            </field>
10541 
            <field>
10542 
              <name>CC1OF</name>
10543 
              <description>Capture/Compare 1 overcapture
10544 
              flag</description>
10545 
              <bitOffset>9</bitOffset>
10546 
              <bitWidth>1</bitWidth>
10547 
            </field>
10548 
            <field>
10549 
              <name>TIF</name>
10550 
              <description>Trigger interrupt flag</description>
10551 
              <bitOffset>6</bitOffset>
10552 
              <bitWidth>1</bitWidth>
10553 
            </field>
10554 
            <field>
10555 
              <name>CC2IF</name>
10556 
              <description>Capture/Compare 2 interrupt
10557 
              flag</description>
10558 
              <bitOffset>2</bitOffset>
10559 
              <bitWidth>1</bitWidth>
10560 
            </field>
10561 
            <field>
10562 
              <name>CC1IF</name>
10563 
              <description>Capture/compare 1 interrupt
10564 
              flag</description>
10565 
              <bitOffset>1</bitOffset>
10566 
              <bitWidth>1</bitWidth>
10567 
            </field>
10568 
            <field>
10569 
              <name>UIF</name>
10570 
              <description>Update interrupt flag</description>
10571 
              <bitOffset>0</bitOffset>
10572 
              <bitWidth>1</bitWidth>
10573 
            </field>
10574 
          </fields>
10575 
        </register>
10576 
        <register>
10577 
          <name>EGR</name>
10578 
          <displayName>EGR</displayName>
10579 
          <description>event generation register</description>
10580 
          <addressOffset>0x14</addressOffset>
10581 
          <size>0x20</size>
10582 
          <access>write-only</access>
10583 
          <resetValue>0x0000</resetValue>
10584 
          <fields>
10585 
            <field>
10586 
              <name>TG</name>
10587 
              <description>Trigger generation</description>
10588 
              <bitOffset>6</bitOffset>
10589 
              <bitWidth>1</bitWidth>
10590 
            </field>
10591 
            <field>
10592 
              <name>CC2G</name>
10593 
              <description>Capture/compare 2
10594 
              generation</description>
10595 
              <bitOffset>2</bitOffset>
10596 
              <bitWidth>1</bitWidth>
10597 
            </field>
10598 
            <field>
10599 
              <name>CC1G</name>
10600 
              <description>Capture/compare 1
10601 
              generation</description>
10602 
              <bitOffset>1</bitOffset>
10603 
              <bitWidth>1</bitWidth>
10604 
            </field>
10605 
            <field>
10606 
              <name>UG</name>
10607 
              <description>Update generation</description>
10608 
              <bitOffset>0</bitOffset>
10609 
              <bitWidth>1</bitWidth>
10610 
            </field>
10611 
          </fields>
10612 
        </register>
10613 
        <register>
10614 
          <name>CCMR1_Output</name>
10615 
          <displayName>CCMR1_Output</displayName>
10616 
          <description>capture/compare mode register 1 (output
10617 
          mode)</description>
10618 
          <addressOffset>0x18</addressOffset>
10619 
          <size>0x20</size>
10620 
          <access>read-write</access>
10621 
          <resetValue>0x00000000</resetValue>
10622 
          <fields>
10623 
            <field>
10624 
              <name>OC2M</name>
10625 
              <description>Output Compare 2 mode</description>
10626 
              <bitOffset>12</bitOffset>
10627 
              <bitWidth>3</bitWidth>
10628 
            </field>
10629 
            <field>
10630 
              <name>OC2PE</name>
10631 
              <description>Output Compare 2 preload
10632 
              enable</description>
10633 
              <bitOffset>11</bitOffset>
10634 
              <bitWidth>1</bitWidth>
10635 
            </field>
10636 
            <field>
10637 
              <name>OC2FE</name>
10638 
              <description>Output Compare 2 fast
10639 
              enable</description>
10640 
              <bitOffset>10</bitOffset>
10641 
              <bitWidth>1</bitWidth>
10642 
            </field>
10643 
            <field>
10644 
              <name>CC2S</name>
10645 
              <description>Capture/Compare 2
10646 
              selection</description>
10647 
              <bitOffset>8</bitOffset>
10648 
              <bitWidth>2</bitWidth>
10649 
            </field>
10650 
            <field>
10651 
              <name>OC1M</name>
10652 
              <description>Output Compare 1 mode</description>
10653 
              <bitOffset>4</bitOffset>
10654 
              <bitWidth>3</bitWidth>
10655 
            </field>
10656 
            <field>
10657 
              <name>OC1PE</name>
10658 
              <description>Output Compare 1 preload
10659 
              enable</description>
10660 
              <bitOffset>3</bitOffset>
10661 
              <bitWidth>1</bitWidth>
10662 
            </field>
10663 
            <field>
10664 
              <name>OC1FE</name>
10665 
              <description>Output Compare 1 fast
10666 
              enable</description>
10667 
              <bitOffset>2</bitOffset>
10668 
              <bitWidth>1</bitWidth>
10669 
            </field>
10670 
            <field>
10671 
              <name>CC1S</name>
10672 
              <description>Capture/Compare 1
10673 
              selection</description>
10674 
              <bitOffset>0</bitOffset>
10675 
              <bitWidth>2</bitWidth>
10676 
            </field>
10677 
          </fields>
10678 
        </register>
10679 
        <register>
10680 
          <name>CCMR1_Input</name>
10681 
          <displayName>CCMR1_Input</displayName>
10682 
          <description>capture/compare mode register 1 (input
10683 
          mode)</description>
10684 
          <alternateRegister>CCMR1_Output</alternateRegister>
10685 
          <addressOffset>0x18</addressOffset>
10686 
          <size>0x20</size>
10687 
          <access>read-write</access>
10688 
          <resetValue>0x00000000</resetValue>
10689 
          <fields>
10690 
            <field>
10691 
              <name>IC2F</name>
10692 
              <description>Input capture 2 filter</description>
10693 
              <bitOffset>12</bitOffset>
10694 
              <bitWidth>4</bitWidth>
10695 
            </field>
10696 
            <field>
10697 
              <name>IC2PSC</name>
10698 
              <description>Input capture 2 prescaler</description>
10699 
              <bitOffset>10</bitOffset>
10700 
              <bitWidth>2</bitWidth>
10701 
            </field>
10702 
            <field>
10703 
              <name>CC2S</name>
10704 
              <description>Capture/Compare 2
10705 
              selection</description>
10706 
              <bitOffset>8</bitOffset>
10707 
              <bitWidth>2</bitWidth>
10708 
            </field>
10709 
            <field>
10710 
              <name>IC1F</name>
10711 
              <description>Input capture 1 filter</description>
10712 
              <bitOffset>4</bitOffset>
10713 
              <bitWidth>4</bitWidth>
10714 
            </field>
10715 
            <field>
10716 
              <name>IC1PSC</name>
10717 
              <description>Input capture 1 prescaler</description>
10718 
              <bitOffset>2</bitOffset>
10719 
              <bitWidth>2</bitWidth>
10720 
            </field>
10721 
            <field>
10722 
              <name>CC1S</name>
10723 
              <description>Capture/Compare 1
10724 
              selection</description>
10725 
              <bitOffset>0</bitOffset>
10726 
              <bitWidth>2</bitWidth>
10727 
            </field>
10728 
          </fields>
10729 
        </register>
10730 
        <register>
10731 
          <name>CCER</name>
10732 
          <displayName>CCER</displayName>
10733 
          <description>capture/compare enable
10734 
          register</description>
10735 
          <addressOffset>0x20</addressOffset>
10736 
          <size>0x20</size>
10737 
          <access>read-write</access>
10738 
          <resetValue>0x0000</resetValue>
10739 
          <fields>
10740 
            <field>
10741 
              <name>CC2NP</name>
10742 
              <description>Capture/Compare 2 output
10743 
              Polarity</description>
10744 
              <bitOffset>7</bitOffset>
10745 
              <bitWidth>1</bitWidth>
10746 
            </field>
10747 
            <field>
10748 
              <name>CC2P</name>
10749 
              <description>Capture/Compare 2 output
10750 
              Polarity</description>
10751 
              <bitOffset>5</bitOffset>
10752 
              <bitWidth>1</bitWidth>
10753 
            </field>
10754 
            <field>
10755 
              <name>CC2E</name>
10756 
              <description>Capture/Compare 2 output
10757 
              enable</description>
10758 
              <bitOffset>4</bitOffset>
10759 
              <bitWidth>1</bitWidth>
10760 
            </field>
10761 
            <field>
10762 
              <name>CC1NP</name>
10763 
              <description>Capture/Compare 1 output
10764 
              Polarity</description>
10765 
              <bitOffset>3</bitOffset>
10766 
              <bitWidth>1</bitWidth>
10767 
            </field>
10768 
            <field>
10769 
              <name>CC1P</name>
10770 
              <description>Capture/Compare 1 output
10771 
              Polarity</description>
10772 
              <bitOffset>1</bitOffset>
10773 
              <bitWidth>1</bitWidth>
10774 
            </field>
10775 
            <field>
10776 
              <name>CC1E</name>
10777 
              <description>Capture/Compare 1 output
10778 
              enable</description>
10779 
              <bitOffset>0</bitOffset>
10780 
              <bitWidth>1</bitWidth>
10781 
            </field>
10782 
          </fields>
10783 
        </register>
10784 
        <register>
10785 
          <name>CNT</name>
10786 
          <displayName>CNT</displayName>
10787 
          <description>counter</description>
10788 
          <addressOffset>0x24</addressOffset>
10789 
          <size>0x20</size>
10790 
          <access>read-write</access>
10791 
          <resetValue>0x00000000</resetValue>
10792 
          <fields>
10793 
            <field>
10794 
              <name>CNT</name>
10795 
              <description>counter value</description>
10796 
              <bitOffset>0</bitOffset>
10797 
              <bitWidth>16</bitWidth>
10798 
            </field>
10799 
          </fields>
10800 
        </register>
10801 
        <register>
10802 
          <name>PSC</name>
10803 
          <displayName>PSC</displayName>
10804 
          <description>prescaler</description>
10805 
          <addressOffset>0x28</addressOffset>
10806 
          <size>0x20</size>
10807 
          <access>read-write</access>
10808 
          <resetValue>0x0000</resetValue>
10809 
          <fields>
10810 
            <field>
10811 
              <name>PSC</name>
10812 
              <description>Prescaler value</description>
10813 
              <bitOffset>0</bitOffset>
10814 
              <bitWidth>16</bitWidth>
10815 
            </field>
10816 
          </fields>
10817 
        </register>
10818 
        <register>
10819 
          <name>ARR</name>
10820 
          <displayName>ARR</displayName>
10821 
          <description>auto-reload register</description>
10822 
          <addressOffset>0x2C</addressOffset>
10823 
          <size>0x20</size>
10824 
          <access>read-write</access>
10825 
          <resetValue>0x00000000</resetValue>
10826 
          <fields>
10827 
            <field>
10828 
              <name>ARR</name>
10829 
              <description>Auto-reload value</description>
10830 
              <bitOffset>0</bitOffset>
10831 
              <bitWidth>16</bitWidth>
10832 
            </field>
10833 
          </fields>
10834 
        </register>
10835 
        <register>
10836 
          <name>CCR1</name>
10837 
          <displayName>CCR1</displayName>
10838 
          <description>capture/compare register 1</description>
10839 
          <addressOffset>0x34</addressOffset>
10840 
          <size>0x20</size>
10841 
          <access>read-write</access>
10842 
          <resetValue>0x00000000</resetValue>
10843 
          <fields>
10844 
            <field>
10845 
              <name>CCR1</name>
10846 
              <description>Capture/Compare 1 value</description>
10847 
              <bitOffset>0</bitOffset>
10848 
              <bitWidth>16</bitWidth>
10849 
            </field>
10850 
          </fields>
10851 
        </register>
10852 
        <register>
10853 
          <name>CCR2</name>
10854 
          <displayName>CCR2</displayName>
10855 
          <description>capture/compare register 2</description>
10856 
          <addressOffset>0x38</addressOffset>
10857 
          <size>0x20</size>
10858 
          <access>read-write</access>
10859 
          <resetValue>0x00000000</resetValue>
10860 
          <fields>
10861 
            <field>
10862 
              <name>CCR2</name>
10863 
              <description>Capture/Compare 2 value</description>
10864 
              <bitOffset>0</bitOffset>
10865 
              <bitWidth>16</bitWidth>
10866 
            </field>
10867 
          </fields>
10868 
        </register>
10869 
      </registers>
10870 
    </peripheral>
10871 
    <peripheral derivedFrom="TIM9">
10872 
      <name>TIM12</name>
10873 
      <baseAddress>0x40001800</baseAddress>
10874 
    </peripheral>
10875 
    <peripheral>
10876 
      <name>TIM10</name>
10877 
      <description>General purpose timer</description>
10878 
      <groupName>TIM</groupName>
10879 
      <baseAddress>0x40015000</baseAddress>
10880 
      <addressBlock>
10881 
        <offset>0x0</offset>
10882 
        <size>0x400</size>
10883 
        <usage>registers</usage>
10884 
      </addressBlock>
10885 
      <interrupt>
10886 
        <name>TIM1_UP</name>
10887 
        <description>TIM1 Update interrupt</description>
10888 
        <value>25</value>
10889 
      </interrupt>
10890 
      <registers>
10891 
        <register>
10892 
          <name>CR1</name>
10893 
          <displayName>CR1</displayName>
10894 
          <description>control register 1</description>
10895 
          <addressOffset>0x0</addressOffset>
10896 
          <size>0x20</size>
10897 
          <access>read-write</access>
10898 
          <resetValue>0x0000</resetValue>
10899 
          <fields>
10900 
            <field>
10901 
              <name>CKD</name>
10902 
              <description>Clock division</description>
10903 
              <bitOffset>8</bitOffset>
10904 
              <bitWidth>2</bitWidth>
10905 
            </field>
10906 
            <field>
10907 
              <name>ARPE</name>
10908 
              <description>Auto-reload preload enable</description>
10909 
              <bitOffset>7</bitOffset>
10910 
              <bitWidth>1</bitWidth>
10911 
            </field>
10912 
            <field>
10913 
              <name>URS</name>
10914 
              <description>Update request source</description>
10915 
              <bitOffset>2</bitOffset>
10916 
              <bitWidth>1</bitWidth>
10917 
            </field>
10918 
            <field>
10919 
              <name>UDIS</name>
10920 
              <description>Update disable</description>
10921 
              <bitOffset>1</bitOffset>
10922 
              <bitWidth>1</bitWidth>
10923 
            </field>
10924 
            <field>
10925 
              <name>CEN</name>
10926 
              <description>Counter enable</description>
10927 
              <bitOffset>0</bitOffset>
10928 
              <bitWidth>1</bitWidth>
10929 
            </field>
10930 
          </fields>
10931 
        </register>
10932 
        <register>
10933 
          <name>CR2</name>
10934 
          <displayName>CR2</displayName>
10935 
          <description>control register 2</description>
10936 
          <addressOffset>0x4</addressOffset>
10937 
          <size>0x20</size>
10938 
          <access>read-write</access>
10939 
          <resetValue>0x0000</resetValue>
10940 
          <fields>
10941 
            <field>
10942 
              <name>MMS</name>
10943 
              <description>Master mode selection</description>
10944 
              <bitOffset>4</bitOffset>
10945 
              <bitWidth>3</bitWidth>
10946 
            </field>
10947 
          </fields>
10948 
        </register>
10949 
        <register>
10950 
          <name>DIER</name>
10951 
          <displayName>DIER</displayName>
10952 
          <description>DMA/Interrupt enable register</description>
10953 
          <addressOffset>0xC</addressOffset>
10954 
          <size>0x20</size>
10955 
          <access>read-write</access>
10956 
          <resetValue>0x0000</resetValue>
10957 
          <fields>
10958 
            <field>
10959 
              <name>CC1IE</name>
10960 
              <description>Capture/Compare 1 interrupt
10961 
              enable</description>
10962 
              <bitOffset>1</bitOffset>
10963 
              <bitWidth>1</bitWidth>
10964 
            </field>
10965 
            <field>
10966 
              <name>UIE</name>
10967 
              <description>Update interrupt enable</description>
10968 
              <bitOffset>0</bitOffset>
10969 
              <bitWidth>1</bitWidth>
10970 
            </field>
10971 
          </fields>
10972 
        </register>
10973 
        <register>
10974 
          <name>SR</name>
10975 
          <displayName>SR</displayName>
10976 
          <description>status register</description>
10977 
          <addressOffset>0x10</addressOffset>
10978 
          <size>0x20</size>
10979 
          <access>read-write</access>
10980 
          <resetValue>0x0000</resetValue>
10981 
          <fields>
10982 
            <field>
10983 
              <name>CC1OF</name>
10984 
              <description>Capture/Compare 1 overcapture
10985 
              flag</description>
10986 
              <bitOffset>9</bitOffset>
10987 
              <bitWidth>1</bitWidth>
10988 
            </field>
10989 
            <field>
10990 
              <name>CC1IF</name>
10991 
              <description>Capture/compare 1 interrupt
10992 
              flag</description>
10993 
              <bitOffset>1</bitOffset>
10994 
              <bitWidth>1</bitWidth>
10995 
            </field>
10996 
            <field>
10997 
              <name>UIF</name>
10998 
              <description>Update interrupt flag</description>
10999 
              <bitOffset>0</bitOffset>
11000 
              <bitWidth>1</bitWidth>
11001 
            </field>
11002 
          </fields>
11003 
        </register>
11004 
        <register>
11005 
          <name>EGR</name>
11006 
          <displayName>EGR</displayName>
11007 
          <description>event generation register</description>
11008 
          <addressOffset>0x14</addressOffset>
11009 
          <size>0x20</size>
11010 
          <access>write-only</access>
11011 
          <resetValue>0x0000</resetValue>
11012 
          <fields>
11013 
            <field>
11014 
              <name>CC1G</name>
11015 
              <description>Capture/compare 1
11016 
              generation</description>
11017 
              <bitOffset>1</bitOffset>
11018 
              <bitWidth>1</bitWidth>
11019 
            </field>
11020 
            <field>
11021 
              <name>UG</name>
11022 
              <description>Update generation</description>
11023 
              <bitOffset>0</bitOffset>
11024 
              <bitWidth>1</bitWidth>
11025 
            </field>
11026 
          </fields>
11027 
        </register>
11028 
        <register>
11029 
          <name>CCMR1_Output</name>
11030 
          <displayName>CCMR1_Output</displayName>
11031 
          <description>capture/compare mode register (output
11032 
          mode)</description>
11033 
          <addressOffset>0x18</addressOffset>
11034 
          <size>0x20</size>
11035 
          <access>read-write</access>
11036 
          <resetValue>0x00000000</resetValue>
11037 
          <fields>
11038 
            <field>
11039 
              <name>OC1M</name>
11040 
              <description>Output Compare 1 mode</description>
11041 
              <bitOffset>4</bitOffset>
11042 
              <bitWidth>3</bitWidth>
11043 
            </field>
11044 
            <field>
11045 
              <name>OC1PE</name>
11046 
              <description>Output Compare 1 preload
11047 
              enable</description>
11048 
              <bitOffset>3</bitOffset>
11049 
              <bitWidth>1</bitWidth>
11050 
            </field>
11051 
            <field>
11052 
              <name>CC1S</name>
11053 
              <description>Capture/Compare 1
11054 
              selection</description>
11055 
              <bitOffset>0</bitOffset>
11056 
              <bitWidth>2</bitWidth>
11057 
            </field>
11058 
          </fields>
11059 
        </register>
11060 
        <register>
11061 
          <name>CCMR1_Input</name>
11062 
          <displayName>CCMR1_Input</displayName>
11063 
          <description>capture/compare mode register (input
11064 
          mode)</description>
11065 
          <alternateRegister>CCMR1_Output</alternateRegister>
11066 
          <addressOffset>0x18</addressOffset>
11067 
          <size>0x20</size>
11068 
          <access>read-write</access>
11069 
          <resetValue>0x00000000</resetValue>
11070 
          <fields>
11071 
            <field>
11072 
              <name>IC1F</name>
11073 
              <description>Input capture 1 filter</description>
11074 
              <bitOffset>4</bitOffset>
11075 
              <bitWidth>4</bitWidth>
11076 
            </field>
11077 
            <field>
11078 
              <name>IC1PSC</name>
11079 
              <description>Input capture 1 prescaler</description>
11080 
              <bitOffset>2</bitOffset>
11081 
              <bitWidth>2</bitWidth>
11082 
            </field>
11083 
            <field>
11084 
              <name>CC1S</name>
11085 
              <description>Capture/Compare 1
11086 
              selection</description>
11087 
              <bitOffset>0</bitOffset>
11088 
              <bitWidth>2</bitWidth>
11089 
            </field>
11090 
          </fields>
11091 
        </register>
11092 
        <register>
11093 
          <name>CCER</name>
11094 
          <displayName>CCER</displayName>
11095 
          <description>capture/compare enable
11096 
          register</description>
11097 
          <addressOffset>0x20</addressOffset>
11098 
          <size>0x20</size>
11099 
          <access>read-write</access>
11100 
          <resetValue>0x0000</resetValue>
11101 
          <fields>
11102 
            <field>
11103 
              <name>CC1NP</name>
11104 
              <description>Capture/Compare 1 output
11105 
              Polarity</description>
11106 
              <bitOffset>3</bitOffset>
11107 
              <bitWidth>1</bitWidth>
11108 
            </field>
11109 
            <field>
11110 
              <name>CC1P</name>
11111 
              <description>Capture/Compare 1 output
11112 
              Polarity</description>
11113 
              <bitOffset>1</bitOffset>
11114 
              <bitWidth>1</bitWidth>
11115 
            </field>
11116 
            <field>
11117 
              <name>CC1E</name>
11118 
              <description>Capture/Compare 1 output
11119 
              enable</description>
11120 
              <bitOffset>0</bitOffset>
11121 
              <bitWidth>1</bitWidth>
11122 
            </field>
11123 
          </fields>
11124 
        </register>
11125 
        <register>
11126 
          <name>CNT</name>
11127 
          <displayName>CNT</displayName>
11128 
          <description>counter</description>
11129 
          <addressOffset>0x24</addressOffset>
11130 
          <size>0x20</size>
11131 
          <access>read-write</access>
11132 
          <resetValue>0x00000000</resetValue>
11133 
          <fields>
11134 
            <field>
11135 
              <name>CNT</name>
11136 
              <description>counter value</description>
11137 
              <bitOffset>0</bitOffset>
11138 
              <bitWidth>16</bitWidth>
11139 
            </field>
11140 
          </fields>
11141 
        </register>
11142 
        <register>
11143 
          <name>PSC</name>
11144 
          <displayName>PSC</displayName>
11145 
          <description>prescaler</description>
11146 
          <addressOffset>0x28</addressOffset>
11147 
          <size>0x20</size>
11148 
          <access>read-write</access>
11149 
          <resetValue>0x0000</resetValue>
11150 
          <fields>
11151 
            <field>
11152 
              <name>PSC</name>
11153 
              <description>Prescaler value</description>
11154 
              <bitOffset>0</bitOffset>
11155 
              <bitWidth>16</bitWidth>
11156 
            </field>
11157 
          </fields>
11158 
        </register>
11159 
        <register>
11160 
          <name>ARR</name>
11161 
          <displayName>ARR</displayName>
11162 
          <description>auto-reload register</description>
11163 
          <addressOffset>0x2C</addressOffset>
11164 
          <size>0x20</size>
11165 
          <access>read-write</access>
11166 
          <resetValue>0x00000000</resetValue>
11167 
          <fields>
11168 
            <field>
11169 
              <name>ARR</name>
11170 
              <description>Auto-reload value</description>
11171 
              <bitOffset>0</bitOffset>
11172 
              <bitWidth>16</bitWidth>
11173 
            </field>
11174 
          </fields>
11175 
        </register>
11176 
        <register>
11177 
          <name>CCR1</name>
11178 
          <displayName>CCR1</displayName>
11179 
          <description>capture/compare register 1</description>
11180 
          <addressOffset>0x34</addressOffset>
11181 
          <size>0x20</size>
11182 
          <access>read-write</access>
11183 
          <resetValue>0x00000000</resetValue>
11184 
          <fields>
11185 
            <field>
11186 
              <name>CCR1</name>
11187 
              <description>Capture/Compare 1 value</description>
11188 
              <bitOffset>0</bitOffset>
11189 
              <bitWidth>16</bitWidth>
11190 
            </field>
11191 
          </fields>
11192 
        </register>
11193 
      </registers>
11194 
    </peripheral>
11195 
    <peripheral derivedFrom="TIM10">
11196 
      <name>TIM11</name>
11197 
      <baseAddress>0x40015400</baseAddress>
11198 
      <interrupt>
11199 
        <name>TIM1_TRG_COM</name>
11200 
        <description>TIM1 Trigger and Commutation
11201 
        interrupts</description>
11202 
        <value>26</value>
11203 
      </interrupt>
11204 
    </peripheral>
11205 
    <peripheral derivedFrom="TIM10">
11206 
      <name>TIM13</name>
11207 
      <baseAddress>0x40001C00</baseAddress>
11208 
    </peripheral>
11209 
    <peripheral derivedFrom="TIM10">
11210 
      <name>TIM14</name>
11211 
      <baseAddress>0x40002000</baseAddress>
11212 
    </peripheral>
11213 
    <peripheral>
11214 
      <name>TIM6</name>
11215 
      <description>Basic timer</description>
11216 
      <groupName>TIM</groupName>
11217 
      <baseAddress>0x40001000</baseAddress>
11218 
      <addressBlock>
11219 
        <offset>0x0</offset>
11220 
        <size>0x400</size>
11221 
        <usage>registers</usage>
11222 
      </addressBlock>
11223 
      <interrupt>
11224 
        <name>TIM6</name>
11225 
        <description>TIM6 global interrupt</description>
11226 
        <value>54</value>
11227 
      </interrupt>
11228 
      <registers>
11229 
        <register>
11230 
          <name>CR1</name>
11231 
          <displayName>CR1</displayName>
11232 
          <description>control register 1</description>
11233 
          <addressOffset>0x0</addressOffset>
11234 
          <size>0x20</size>
11235 
          <access>read-write</access>
11236 
          <resetValue>0x0000</resetValue>
11237 
          <fields>
11238 
            <field>
11239 
              <name>ARPE</name>
11240 
              <description>Auto-reload preload enable</description>
11241 
              <bitOffset>7</bitOffset>
11242 
              <bitWidth>1</bitWidth>
11243 
            </field>
11244 
            <field>
11245 
              <name>OPM</name>
11246 
              <description>One-pulse mode</description>
11247 
              <bitOffset>3</bitOffset>
11248 
              <bitWidth>1</bitWidth>
11249 
            </field>
11250 
            <field>
11251 
              <name>URS</name>
11252 
              <description>Update request source</description>
11253 
              <bitOffset>2</bitOffset>
11254 
              <bitWidth>1</bitWidth>
11255 
            </field>
11256 
            <field>
11257 
              <name>UDIS</name>
11258 
              <description>Update disable</description>
11259 
              <bitOffset>1</bitOffset>
11260 
              <bitWidth>1</bitWidth>
11261 
            </field>
11262 
            <field>
11263 
              <name>CEN</name>
11264 
              <description>Counter enable</description>
11265 
              <bitOffset>0</bitOffset>
11266 
              <bitWidth>1</bitWidth>
11267 
            </field>
11268 
          </fields>
11269 
        </register>
11270 
        <register>
11271 
          <name>CR2</name>
11272 
          <displayName>CR2</displayName>
11273 
          <description>control register 2</description>
11274 
          <addressOffset>0x4</addressOffset>
11275 
          <size>0x20</size>
11276 
          <access>read-write</access>
11277 
          <resetValue>0x0000</resetValue>
11278 
          <fields>
11279 
            <field>
11280 
              <name>MMS</name>
11281 
              <description>Master mode selection</description>
11282 
              <bitOffset>4</bitOffset>
11283 
              <bitWidth>3</bitWidth>
11284 
            </field>
11285 
          </fields>
11286 
        </register>
11287 
        <register>
11288 
          <name>DIER</name>
11289 
          <displayName>DIER</displayName>
11290 
          <description>DMA/Interrupt enable register</description>
11291 
          <addressOffset>0xC</addressOffset>
11292 
          <size>0x20</size>
11293 
          <access>read-write</access>
11294 
          <resetValue>0x0000</resetValue>
11295 
          <fields>
11296 
            <field>
11297 
              <name>UDE</name>
11298 
              <description>Update DMA request enable</description>
11299 
              <bitOffset>8</bitOffset>
11300 
              <bitWidth>1</bitWidth>
11301 
            </field>
11302 
            <field>
11303 
              <name>UIE</name>
11304 
              <description>Update interrupt enable</description>
11305 
              <bitOffset>0</bitOffset>
11306 
              <bitWidth>1</bitWidth>
11307 
            </field>
11308 
          </fields>
11309 
        </register>
11310 
        <register>
11311 
          <name>SR</name>
11312 
          <displayName>SR</displayName>
11313 
          <description>status register</description>
11314 
          <addressOffset>0x10</addressOffset>
11315 
          <size>0x20</size>
11316 
          <access>read-write</access>
11317 
          <resetValue>0x0000</resetValue>
11318 
          <fields>
11319 
            <field>
11320 
              <name>UIF</name>
11321 
              <description>Update interrupt flag</description>
11322 
              <bitOffset>0</bitOffset>
11323 
              <bitWidth>1</bitWidth>
11324 
            </field>
11325 
          </fields>
11326 
        </register>
11327 
        <register>
11328 
          <name>EGR</name>
11329 
          <displayName>EGR</displayName>
11330 
          <description>event generation register</description>
11331 
          <addressOffset>0x14</addressOffset>
11332 
          <size>0x20</size>
11333 
          <access>write-only</access>
11334 
          <resetValue>0x0000</resetValue>
11335 
          <fields>
11336 
            <field>
11337 
              <name>UG</name>
11338 
              <description>Update generation</description>
11339 
              <bitOffset>0</bitOffset>
11340 
              <bitWidth>1</bitWidth>
11341 
            </field>
11342 
          </fields>
11343 
        </register>
11344 
        <register>
11345 
          <name>CNT</name>
11346 
          <displayName>CNT</displayName>
11347 
          <description>counter</description>
11348 
          <addressOffset>0x24</addressOffset>
11349 
          <size>0x20</size>
11350 
          <access>read-write</access>
11351 
          <resetValue>0x00000000</resetValue>
11352 
          <fields>
11353 
            <field>
11354 
              <name>CNT</name>
11355 
              <description>Low counter value</description>
11356 
              <bitOffset>0</bitOffset>
11357 
              <bitWidth>16</bitWidth>
11358 
            </field>
11359 
          </fields>
11360 
        </register>
11361 
        <register>
11362 
          <name>PSC</name>
11363 
          <displayName>PSC</displayName>
11364 
          <description>prescaler</description>
11365 
          <addressOffset>0x28</addressOffset>
11366 
          <size>0x20</size>
11367 
          <access>read-write</access>
11368 
          <resetValue>0x0000</resetValue>
11369 
          <fields>
11370 
            <field>
11371 
              <name>PSC</name>
11372 
              <description>Prescaler value</description>
11373 
              <bitOffset>0</bitOffset>
11374 
              <bitWidth>16</bitWidth>
11375 
            </field>
11376 
          </fields>
11377 
        </register>
11378 
        <register>
11379 
          <name>ARR</name>
11380 
          <displayName>ARR</displayName>
11381 
          <description>auto-reload register</description>
11382 
          <addressOffset>0x2C</addressOffset>
11383 
          <size>0x20</size>
11384 
          <access>read-write</access>
11385 
          <resetValue>0x00000000</resetValue>
11386 
          <fields>
11387 
            <field>
11388 
              <name>ARR</name>
11389 
              <description>Low Auto-reload value</description>
11390 
              <bitOffset>0</bitOffset>
11391 
              <bitWidth>16</bitWidth>
11392 
            </field>
11393 
          </fields>
11394 
        </register>
11395 
      </registers>
11396 
    </peripheral>
11397 
    <peripheral derivedFrom="TIM6">
11398 
      <name>TIM7</name>
11399 
      <baseAddress>0x40001400</baseAddress>
11400 
      <interrupt>
11401 
        <name>TIM7</name>
11402 
        <description>TIM7 global interrupt</description>
11403 
        <value>55</value>
11404 
      </interrupt>
11405 
    </peripheral>
11406 
    <peripheral>
11407 
      <name>I2C1</name>
11408 
      <description>Inter integrated circuit</description>
11409 
      <groupName>I2C</groupName>
11410 
      <baseAddress>0x40005400</baseAddress>
11411 
      <addressBlock>
11412 
        <offset>0x0</offset>
11413 
        <size>0x400</size>
11414 
        <usage>registers</usage>
11415 
      </addressBlock>
11416 
      <interrupt>
11417 
        <name>I2C1_EV</name>
11418 
        <description>I2C1 event interrupt</description>
11419 
        <value>31</value>
11420 
      </interrupt>
11421 
      <interrupt>
11422 
        <name>I2C1_ER</name>
11423 
        <description>I2C1 error interrupt</description>
11424 
        <value>32</value>
11425 
      </interrupt>
11426 
      <registers>
11427 
        <register>
11428 
          <name>CR1</name>
11429 
          <displayName>CR1</displayName>
11430 
          <description>Control register 1</description>
11431 
          <addressOffset>0x0</addressOffset>
11432 
          <size>0x20</size>
11433 
          <access>read-write</access>
11434 
          <resetValue>0x0000</resetValue>
11435 
          <fields>
11436 
            <field>
11437 
              <name>SWRST</name>
11438 
              <description>Software reset</description>
11439 
              <bitOffset>15</bitOffset>
11440 
              <bitWidth>1</bitWidth>
11441 
            </field>
11442 
            <field>
11443 
              <name>ALERT</name>
11444 
              <description>SMBus alert</description>
11445 
              <bitOffset>13</bitOffset>
11446 
              <bitWidth>1</bitWidth>
11447 
            </field>
11448 
            <field>
11449 
              <name>PEC</name>
11450 
              <description>Packet error checking</description>
11451 
              <bitOffset>12</bitOffset>
11452 
              <bitWidth>1</bitWidth>
11453 
            </field>
11454 
            <field>
11455 
              <name>POS</name>
11456 
              <description>Acknowledge/PEC Position (for data
11457 
              reception)</description>
11458 
              <bitOffset>11</bitOffset>
11459 
              <bitWidth>1</bitWidth>
11460 
            </field>
11461 
            <field>
11462 
              <name>ACK</name>
11463 
              <description>Acknowledge enable</description>
11464 
              <bitOffset>10</bitOffset>
11465 
              <bitWidth>1</bitWidth>
11466 
            </field>
11467 
            <field>
11468 
              <name>STOP</name>
11469 
              <description>Stop generation</description>
11470 
              <bitOffset>9</bitOffset>
11471 
              <bitWidth>1</bitWidth>
11472 
            </field>
11473 
            <field>
11474 
              <name>START</name>
11475 
              <description>Start generation</description>
11476 
              <bitOffset>8</bitOffset>
11477 
              <bitWidth>1</bitWidth>
11478 
            </field>
11479 
            <field>
11480 
              <name>NOSTRETCH</name>
11481 
              <description>Clock stretching disable (Slave
11482 
              mode)</description>
11483 
              <bitOffset>7</bitOffset>
11484 
              <bitWidth>1</bitWidth>
11485 
            </field>
11486 
            <field>
11487 
              <name>ENGC</name>
11488 
              <description>General call enable</description>
11489 
              <bitOffset>6</bitOffset>
11490 
              <bitWidth>1</bitWidth>
11491 
            </field>
11492 
            <field>
11493 
              <name>ENPEC</name>
11494 
              <description>PEC enable</description>
11495 
              <bitOffset>5</bitOffset>
11496 
              <bitWidth>1</bitWidth>
11497 
            </field>
11498 
            <field>
11499 
              <name>ENARP</name>
11500 
              <description>ARP enable</description>
11501 
              <bitOffset>4</bitOffset>
11502 
              <bitWidth>1</bitWidth>
11503 
            </field>
11504 
            <field>
11505 
              <name>SMBTYPE</name>
11506 
              <description>SMBus type</description>
11507 
              <bitOffset>3</bitOffset>
11508 
              <bitWidth>1</bitWidth>
11509 
            </field>
11510 
            <field>
11511 
              <name>SMBUS</name>
11512 
              <description>SMBus mode</description>
11513 
              <bitOffset>1</bitOffset>
11514 
              <bitWidth>1</bitWidth>
11515 
            </field>
11516 
            <field>
11517 
              <name>PE</name>
11518 
              <description>Peripheral enable</description>
11519 
              <bitOffset>0</bitOffset>
11520 
              <bitWidth>1</bitWidth>
11521 
            </field>
11522 
          </fields>
11523 
        </register>
11524 
        <register>
11525 
          <name>CR2</name>
11526 
          <displayName>CR2</displayName>
11527 
          <description>Control register 2</description>
11528 
          <addressOffset>0x4</addressOffset>
11529 
          <size>0x20</size>
11530 
          <access>read-write</access>
11531 
          <resetValue>0x0000</resetValue>
11532 
          <fields>
11533 
            <field>
11534 
              <name>LAST</name>
11535 
              <description>DMA last transfer</description>
11536 
              <bitOffset>12</bitOffset>
11537 
              <bitWidth>1</bitWidth>
11538 
            </field>
11539 
            <field>
11540 
              <name>DMAEN</name>
11541 
              <description>DMA requests enable</description>
11542 
              <bitOffset>11</bitOffset>
11543 
              <bitWidth>1</bitWidth>
11544 
            </field>
11545 
            <field>
11546 
              <name>ITBUFEN</name>
11547 
              <description>Buffer interrupt enable</description>
11548 
              <bitOffset>10</bitOffset>
11549 
              <bitWidth>1</bitWidth>
11550 
            </field>
11551 
            <field>
11552 
              <name>ITEVTEN</name>
11553 
              <description>Event interrupt enable</description>
11554 
              <bitOffset>9</bitOffset>
11555 
              <bitWidth>1</bitWidth>
11556 
            </field>
11557 
            <field>
11558 
              <name>ITERREN</name>
11559 
              <description>Error interrupt enable</description>
11560 
              <bitOffset>8</bitOffset>
11561 
              <bitWidth>1</bitWidth>
11562 
            </field>
11563 
            <field>
11564 
              <name>FREQ</name>
11565 
              <description>Peripheral clock frequency</description>
11566 
              <bitOffset>0</bitOffset>
11567 
              <bitWidth>6</bitWidth>
11568 
            </field>
11569 
          </fields>
11570 
        </register>
11571 
        <register>
11572 
          <name>OAR1</name>
11573 
          <displayName>OAR1</displayName>
11574 
          <description>Own address register 1</description>
11575 
          <addressOffset>0x8</addressOffset>
11576 
          <size>0x20</size>
11577 
          <access>read-write</access>
11578 
          <resetValue>0x0000</resetValue>
11579 
          <fields>
11580 
            <field>
11581 
              <name>ADDMODE</name>
11582 
              <description>Addressing mode (slave
11583 
              mode)</description>
11584 
              <bitOffset>15</bitOffset>
11585 
              <bitWidth>1</bitWidth>
11586 
            </field>
11587 
            <field>
11588 
              <name>ADD10</name>
11589 
              <description>Interface address</description>
11590 
              <bitOffset>8</bitOffset>
11591 
              <bitWidth>2</bitWidth>
11592 
            </field>
11593 
            <field>
11594 
              <name>ADD7</name>
11595 
              <description>Interface address</description>
11596 
              <bitOffset>1</bitOffset>
11597 
              <bitWidth>7</bitWidth>
11598 
            </field>
11599 
            <field>
11600 
              <name>ADD0</name>
11601 
              <description>Interface address</description>
11602 
              <bitOffset>0</bitOffset>
11603 
              <bitWidth>1</bitWidth>
11604 
            </field>
11605 
          </fields>
11606 
        </register>
11607 
        <register>
11608 
          <name>OAR2</name>
11609 
          <displayName>OAR2</displayName>
11610 
          <description>Own address register 2</description>
11611 
          <addressOffset>0xC</addressOffset>
11612 
          <size>0x20</size>
11613 
          <access>read-write</access>
11614 
          <resetValue>0x0000</resetValue>
11615 
          <fields>
11616 
            <field>
11617 
              <name>ADD2</name>
11618 
              <description>Interface address</description>
11619 
              <bitOffset>1</bitOffset>
11620 
              <bitWidth>7</bitWidth>
11621 
            </field>
11622 
            <field>
11623 
              <name>ENDUAL</name>
11624 
              <description>Dual addressing mode
11625 
              enable</description>
11626 
              <bitOffset>0</bitOffset>
11627 
              <bitWidth>1</bitWidth>
11628 
            </field>
11629 
          </fields>
11630 
        </register>
11631 
        <register>
11632 
          <name>DR</name>
11633 
          <displayName>DR</displayName>
11634 
          <description>Data register</description>
11635 
          <addressOffset>0x10</addressOffset>
11636 
          <size>0x20</size>
11637 
          <access>read-write</access>
11638 
          <resetValue>0x0000</resetValue>
11639 
          <fields>
11640 
            <field>
11641 
              <name>DR</name>
11642 
              <description>8-bit data register</description>
11643 
              <bitOffset>0</bitOffset>
11644 
              <bitWidth>8</bitWidth>
11645 
            </field>
11646 
          </fields>
11647 
        </register>
11648 
        <register>
11649 
          <name>SR1</name>
11650 
          <displayName>SR1</displayName>
11651 
          <description>Status register 1</description>
11652 
          <addressOffset>0x14</addressOffset>
11653 
          <size>0x20</size>
11654 
          <resetValue>0x0000</resetValue>
11655 
          <fields>
11656 
            <field>
11657 
              <name>SMBALERT</name>
11658 
              <description>SMBus alert</description>
11659 
              <bitOffset>15</bitOffset>
11660 
              <bitWidth>1</bitWidth>
11661 
              <access>read-write</access>
11662 
            </field>
11663 
            <field>
11664 
              <name>TIMEOUT</name>
11665 
              <description>Timeout or Tlow error</description>
11666 
              <bitOffset>14</bitOffset>
11667 
              <bitWidth>1</bitWidth>
11668 
              <access>read-write</access>
11669 
            </field>
11670 
            <field>
11671 
              <name>PECERR</name>
11672 
              <description>PEC Error in reception</description>
11673 
              <bitOffset>12</bitOffset>
11674 
              <bitWidth>1</bitWidth>
11675 
              <access>read-write</access>
11676 
            </field>
11677 
            <field>
11678 
              <name>OVR</name>
11679 
              <description>Overrun/Underrun</description>
11680 
              <bitOffset>11</bitOffset>
11681 
              <bitWidth>1</bitWidth>
11682 
              <access>read-write</access>
11683 
            </field>
11684 
            <field>
11685 
              <name>AF</name>
11686 
              <description>Acknowledge failure</description>
11687 
              <bitOffset>10</bitOffset>
11688 
              <bitWidth>1</bitWidth>
11689 
              <access>read-write</access>
11690 
            </field>
11691 
            <field>
11692 
              <name>ARLO</name>
11693 
              <description>Arbitration lost (master
11694 
              mode)</description>
11695 
              <bitOffset>9</bitOffset>
11696 
              <bitWidth>1</bitWidth>
11697 
              <access>read-write</access>
11698 
            </field>
11699 
            <field>
11700 
              <name>BERR</name>
11701 
              <description>Bus error</description>
11702 
              <bitOffset>8</bitOffset>
11703 
              <bitWidth>1</bitWidth>
11704 
              <access>read-write</access>
11705 
            </field>
11706 
            <field>
11707 
              <name>TxE</name>
11708 
              <description>Data register empty
11709 
              (transmitters)</description>
11710 
              <bitOffset>7</bitOffset>
11711 
              <bitWidth>1</bitWidth>
11712 
              <access>read-only</access>
11713 
            </field>
11714 
            <field>
11715 
              <name>RxNE</name>
11716 
              <description>Data register not empty
11717 
              (receivers)</description>
11718 
              <bitOffset>6</bitOffset>
11719 
              <bitWidth>1</bitWidth>
11720 
              <access>read-only</access>
11721 
            </field>
11722 
            <field>
11723 
              <name>STOPF</name>
11724 
              <description>Stop detection (slave
11725 
              mode)</description>
11726 
              <bitOffset>4</bitOffset>
11727 
              <bitWidth>1</bitWidth>
11728 
              <access>read-only</access>
11729 
            </field>
11730 
            <field>
11731 
              <name>ADD10</name>
11732 
              <description>10-bit header sent (Master
11733 
              mode)</description>
11734 
              <bitOffset>3</bitOffset>
11735 
              <bitWidth>1</bitWidth>
11736 
              <access>read-only</access>
11737 
            </field>
11738 
            <field>
11739 
              <name>BTF</name>
11740 
              <description>Byte transfer finished</description>
11741 
              <bitOffset>2</bitOffset>
11742 
              <bitWidth>1</bitWidth>
11743 
              <access>read-only</access>
11744 
            </field>
11745 
            <field>
11746 
              <name>ADDR</name>
11747 
              <description>Address sent (master mode)/matched
11748 
              (slave mode)</description>
11749 
              <bitOffset>1</bitOffset>
11750 
              <bitWidth>1</bitWidth>
11751 
              <access>read-only</access>
11752 
            </field>
11753 
            <field>
11754 
              <name>SB</name>
11755 
              <description>Start bit (Master mode)</description>
11756 
              <bitOffset>0</bitOffset>
11757 
              <bitWidth>1</bitWidth>
11758 
              <access>read-only</access>
11759 
            </field>
11760 
          </fields>
11761 
        </register>
11762 
        <register>
11763 
          <name>SR2</name>
11764 
          <displayName>SR2</displayName>
11765 
          <description>Status register 2</description>
11766 
          <addressOffset>0x18</addressOffset>
11767 
          <size>0x20</size>
11768 
          <access>read-only</access>
11769 
          <resetValue>0x0000</resetValue>
11770 
          <fields>
11771 
            <field>
11772 
              <name>PEC</name>
11773 
              <description>acket error checking
11774 
              register</description>
11775 
              <bitOffset>8</bitOffset>
11776 
              <bitWidth>8</bitWidth>
11777 
            </field>
11778 
            <field>
11779 
              <name>DUALF</name>
11780 
              <description>Dual flag (Slave mode)</description>
11781 
              <bitOffset>7</bitOffset>
11782 
              <bitWidth>1</bitWidth>
11783 
            </field>
11784 
            <field>
11785 
              <name>SMBHOST</name>
11786 
              <description>SMBus host header (Slave
11787 
              mode)</description>
11788 
              <bitOffset>6</bitOffset>
11789 
              <bitWidth>1</bitWidth>
11790 
            </field>
11791 
            <field>
11792 
              <name>SMBDEFAULT</name>
11793 
              <description>SMBus device default address (Slave
11794 
              mode)</description>
11795 
              <bitOffset>5</bitOffset>
11796 
              <bitWidth>1</bitWidth>
11797 
            </field>
11798 
            <field>
11799 
              <name>GENCALL</name>
11800 
              <description>General call address (Slave
11801 
              mode)</description>
11802 
              <bitOffset>4</bitOffset>
11803 
              <bitWidth>1</bitWidth>
11804 
            </field>
11805 
            <field>
11806 
              <name>TRA</name>
11807 
              <description>Transmitter/receiver</description>
11808 
              <bitOffset>2</bitOffset>
11809 
              <bitWidth>1</bitWidth>
11810 
            </field>
11811 
            <field>
11812 
              <name>BUSY</name>
11813 
              <description>Bus busy</description>
11814 
              <bitOffset>1</bitOffset>
11815 
              <bitWidth>1</bitWidth>
11816 
            </field>
11817 
            <field>
11818 
              <name>MSL</name>
11819 
              <description>Master/slave</description>
11820 
              <bitOffset>0</bitOffset>
11821 
              <bitWidth>1</bitWidth>
11822 
            </field>
11823 
          </fields>
11824 
        </register>
11825 
        <register>
11826 
          <name>CCR</name>
11827 
          <displayName>CCR</displayName>
11828 
          <description>Clock control register</description>
11829 
          <addressOffset>0x1C</addressOffset>
11830 
          <size>0x20</size>
11831 
          <access>read-write</access>
11832 
          <resetValue>0x0000</resetValue>
11833 
          <fields>
11834 
            <field>
11835 
              <name>F_S</name>
11836 
              <description>I2C master mode selection</description>
11837 
              <bitOffset>15</bitOffset>
11838 
              <bitWidth>1</bitWidth>
11839 
            </field>
11840 
            <field>
11841 
              <name>DUTY</name>
11842 
              <description>Fast mode duty cycle</description>
11843 
              <bitOffset>14</bitOffset>
11844 
              <bitWidth>1</bitWidth>
11845 
            </field>
11846 
            <field>
11847 
              <name>CCR</name>
11848 
              <description>Clock control register in Fast/Standard
11849 
              mode (Master mode)</description>
11850 
              <bitOffset>0</bitOffset>
11851 
              <bitWidth>12</bitWidth>
11852 
            </field>
11853 
          </fields>
11854 
        </register>
11855 
        <register>
11856 
          <name>TRISE</name>
11857 
          <displayName>TRISE</displayName>
11858 
          <description>TRISE register</description>
11859 
          <addressOffset>0x20</addressOffset>
11860 
          <size>0x20</size>
11861 
          <access>read-write</access>
11862 
          <resetValue>0x0002</resetValue>
11863 
          <fields>
11864 
            <field>
11865 
              <name>TRISE</name>
11866 
              <description>Maximum rise time in Fast/Standard mode
11867 
              (Master mode)</description>
11868 
              <bitOffset>0</bitOffset>
11869 
              <bitWidth>6</bitWidth>
11870 
            </field>
11871 
          </fields>
11872 
        </register>
11873 
      </registers>
11874 
    </peripheral>
11875 
    <peripheral derivedFrom="I2C1">
11876 
      <name>I2C2</name>
11877 
      <baseAddress>0x40005800</baseAddress>
11878 
      <interrupt>
11879 
        <name>I2C2_EV</name>
11880 
        <description>I2C2 event interrupt</description>
11881 
        <value>33</value>
11882 
      </interrupt>
11883 
      <interrupt>
11884 
        <name>I2C2_ER</name>
11885 
        <description>I2C2 error interrupt</description>
11886 
        <value>34</value>
11887 
      </interrupt>
11888 
    </peripheral>
11889 
    <peripheral>
11890 
      <name>SPI1</name>
11891 
      <description>Serial peripheral interface</description>
11892 
      <groupName>SPI</groupName>
11893 
      <baseAddress>0x40013000</baseAddress>
11894 
      <addressBlock>
11895 
        <offset>0x0</offset>
11896 
        <size>0x400</size>
11897 
        <usage>registers</usage>
11898 
      </addressBlock>
11899 
      <interrupt>
11900 
        <name>SPI1</name>
11901 
        <description>SPI1 global interrupt</description>
11902 
        <value>35</value>
11903 
      </interrupt>
11904 
      <registers>
11905 
        <register>
11906 
          <name>CR1</name>
11907 
          <displayName>CR1</displayName>
11908 
          <description>control register 1</description>
11909 
          <addressOffset>0x0</addressOffset>
11910 
          <size>0x20</size>
11911 
          <access>read-write</access>
11912 
          <resetValue>0x0000</resetValue>
11913 
          <fields>
11914 
            <field>
11915 
              <name>BIDIMODE</name>
11916 
              <description>Bidirectional data mode
11917 
              enable</description>
11918 
              <bitOffset>15</bitOffset>
11919 
              <bitWidth>1</bitWidth>
11920 
            </field>
11921 
            <field>
11922 
              <name>BIDIOE</name>
11923 
              <description>Output enable in bidirectional
11924 
              mode</description>
11925 
              <bitOffset>14</bitOffset>
11926 
              <bitWidth>1</bitWidth>
11927 
            </field>
11928 
            <field>
11929 
              <name>CRCEN</name>
11930 
              <description>Hardware CRC calculation
11931 
              enable</description>
11932 
              <bitOffset>13</bitOffset>
11933 
              <bitWidth>1</bitWidth>
11934 
            </field>
11935 
            <field>
11936 
              <name>CRCNEXT</name>
11937 
              <description>CRC transfer next</description>
11938 
              <bitOffset>12</bitOffset>
11939 
              <bitWidth>1</bitWidth>
11940 
            </field>
11941 
            <field>
11942 
              <name>DFF</name>
11943 
              <description>Data frame format</description>
11944 
              <bitOffset>11</bitOffset>
11945 
              <bitWidth>1</bitWidth>
11946 
            </field>
11947 
            <field>
11948 
              <name>RXONLY</name>
11949 
              <description>Receive only</description>
11950 
              <bitOffset>10</bitOffset>
11951 
              <bitWidth>1</bitWidth>
11952 
            </field>
11953 
            <field>
11954 
              <name>SSM</name>
11955 
              <description>Software slave management</description>
11956 
              <bitOffset>9</bitOffset>
11957 
              <bitWidth>1</bitWidth>
11958 
            </field>
11959 
            <field>
11960 
              <name>SSI</name>
11961 
              <description>Internal slave select</description>
11962 
              <bitOffset>8</bitOffset>
11963 
              <bitWidth>1</bitWidth>
11964 
            </field>
11965 
            <field>
11966 
              <name>LSBFIRST</name>
11967 
              <description>Frame format</description>
11968 
              <bitOffset>7</bitOffset>
11969 
              <bitWidth>1</bitWidth>
11970 
            </field>
11971 
            <field>
11972 
              <name>SPE</name>
11973 
              <description>SPI enable</description>
11974 
              <bitOffset>6</bitOffset>
11975 
              <bitWidth>1</bitWidth>
11976 
            </field>
11977 
            <field>
11978 
              <name>BR</name>
11979 
              <description>Baud rate control</description>
11980 
              <bitOffset>3</bitOffset>
11981 
              <bitWidth>3</bitWidth>
11982 
            </field>
11983 
            <field>
11984 
              <name>MSTR</name>
11985 
              <description>Master selection</description>
11986 
              <bitOffset>2</bitOffset>
11987 
              <bitWidth>1</bitWidth>
11988 
            </field>
11989 
            <field>
11990 
              <name>CPOL</name>
11991 
              <description>Clock polarity</description>
11992 
              <bitOffset>1</bitOffset>
11993 
              <bitWidth>1</bitWidth>
11994 
            </field>
11995 
            <field>
11996 
              <name>CPHA</name>
11997 
              <description>Clock phase</description>
11998 
              <bitOffset>0</bitOffset>
11999 
              <bitWidth>1</bitWidth>
12000 
            </field>
12001 
          </fields>
12002 
        </register>
12003 
        <register>
12004 
          <name>CR2</name>
12005 
          <displayName>CR2</displayName>
12006 
          <description>control register 2</description>
12007 
          <addressOffset>0x4</addressOffset>
12008 
          <size>0x20</size>
12009 
          <access>read-write</access>
12010 
          <resetValue>0x0000</resetValue>
12011 
          <fields>
12012 
            <field>
12013 
              <name>TXEIE</name>
12014 
              <description>Tx buffer empty interrupt
12015 
              enable</description>
12016 
              <bitOffset>7</bitOffset>
12017 
              <bitWidth>1</bitWidth>
12018 
            </field>
12019 
            <field>
12020 
              <name>RXNEIE</name>
12021 
              <description>RX buffer not empty interrupt
12022 
              enable</description>
12023 
              <bitOffset>6</bitOffset>
12024 
              <bitWidth>1</bitWidth>
12025 
            </field>
12026 
            <field>
12027 
              <name>ERRIE</name>
12028 
              <description>Error interrupt enable</description>
12029 
              <bitOffset>5</bitOffset>
12030 
              <bitWidth>1</bitWidth>
12031 
            </field>
12032 
            <field>
12033 
              <name>SSOE</name>
12034 
              <description>SS output enable</description>
12035 
              <bitOffset>2</bitOffset>
12036 
              <bitWidth>1</bitWidth>
12037 
            </field>
12038 
            <field>
12039 
              <name>TXDMAEN</name>
12040 
              <description>Tx buffer DMA enable</description>
12041 
              <bitOffset>1</bitOffset>
12042 
              <bitWidth>1</bitWidth>
12043 
            </field>
12044 
            <field>
12045 
              <name>RXDMAEN</name>
12046 
              <description>Rx buffer DMA enable</description>
12047 
              <bitOffset>0</bitOffset>
12048 
              <bitWidth>1</bitWidth>
12049 
            </field>
12050 
          </fields>
12051 
        </register>
12052 
        <register>
12053 
          <name>SR</name>
12054 
          <displayName>SR</displayName>
12055 
          <description>status register</description>
12056 
          <addressOffset>0x8</addressOffset>
12057 
          <size>0x20</size>
12058 
          <resetValue>0x0002</resetValue>
12059 
          <fields>
12060 
            <field>
12061 
              <name>BSY</name>
12062 
              <description>Busy flag</description>
12063 
              <bitOffset>7</bitOffset>
12064 
              <bitWidth>1</bitWidth>
12065 
              <access>read-only</access>
12066 
            </field>
12067 
            <field>
12068 
              <name>OVR</name>
12069 
              <description>Overrun flag</description>
12070 
              <bitOffset>6</bitOffset>
12071 
              <bitWidth>1</bitWidth>
12072 
              <access>read-only</access>
12073 
            </field>
12074 
            <field>
12075 
              <name>MODF</name>
12076 
              <description>Mode fault</description>
12077 
              <bitOffset>5</bitOffset>
12078 
              <bitWidth>1</bitWidth>
12079 
              <access>read-only</access>
12080 
            </field>
12081 
            <field>
12082 
              <name>CRCERR</name>
12083 
              <description>CRC error flag</description>
12084 
              <bitOffset>4</bitOffset>
12085 
              <bitWidth>1</bitWidth>
12086 
              <access>read-write</access>
12087 
            </field>
12088 
            <field>
12089 
              <name>UDR</name>
12090 
              <description>Underrun flag</description>
12091 
              <bitOffset>3</bitOffset>
12092 
              <bitWidth>1</bitWidth>
12093 
              <access>read-only</access>
12094 
            </field>
12095 
            <field>
12096 
              <name>CHSIDE</name>
12097 
              <description>Channel side</description>
12098 
              <bitOffset>2</bitOffset>
12099 
              <bitWidth>1</bitWidth>
12100 
              <access>read-only</access>
12101 
            </field>
12102 
            <field>
12103 
              <name>TXE</name>
12104 
              <description>Transmit buffer empty</description>
12105 
              <bitOffset>1</bitOffset>
12106 
              <bitWidth>1</bitWidth>
12107 
              <access>read-only</access>
12108 
            </field>
12109 
            <field>
12110 
              <name>RXNE</name>
12111 
              <description>Receive buffer not empty</description>
12112 
              <bitOffset>0</bitOffset>
12113 
              <bitWidth>1</bitWidth>
12114 
              <access>read-only</access>
12115 
            </field>
12116 
          </fields>
12117 
        </register>
12118 
        <register>
12119 
          <name>DR</name>
12120 
          <displayName>DR</displayName>
12121 
          <description>data register</description>
12122 
          <addressOffset>0xC</addressOffset>
12123 
          <size>0x20</size>
12124 
          <access>read-write</access>
12125 
          <resetValue>0x0000</resetValue>
12126 
          <fields>
12127 
            <field>
12128 
              <name>DR</name>
12129 
              <description>Data register</description>
12130 
              <bitOffset>0</bitOffset>
12131 
              <bitWidth>16</bitWidth>
12132 
            </field>
12133 
          </fields>
12134 
        </register>
12135 
        <register>
12136 
          <name>CRCPR</name>
12137 
          <displayName>CRCPR</displayName>
12138 
          <description>CRC polynomial register</description>
12139 
          <addressOffset>0x10</addressOffset>
12140 
          <size>0x20</size>
12141 
          <access>read-write</access>
12142 
          <resetValue>0x0007</resetValue>
12143 
          <fields>
12144 
            <field>
12145 
              <name>CRCPOLY</name>
12146 
              <description>CRC polynomial register</description>
12147 
              <bitOffset>0</bitOffset>
12148 
              <bitWidth>16</bitWidth>
12149 
            </field>
12150 
          </fields>
12151 
        </register>
12152 
        <register>
12153 
          <name>RXCRCR</name>
12154 
          <displayName>RXCRCR</displayName>
12155 
          <description>RX CRC register</description>
12156 
          <addressOffset>0x14</addressOffset>
12157 
          <size>0x20</size>
12158 
          <access>read-only</access>
12159 
          <resetValue>0x0000</resetValue>
12160 
          <fields>
12161 
            <field>
12162 
              <name>RxCRC</name>
12163 
              <description>Rx CRC register</description>
12164 
              <bitOffset>0</bitOffset>
12165 
              <bitWidth>16</bitWidth>
12166 
            </field>
12167 
          </fields>
12168 
        </register>
12169 
        <register>
12170 
          <name>TXCRCR</name>
12171 
          <displayName>TXCRCR</displayName>
12172 
          <description>TX CRC register</description>
12173 
          <addressOffset>0x18</addressOffset>
12174 
          <size>0x20</size>
12175 
          <access>read-only</access>
12176 
          <resetValue>0x0000</resetValue>
12177 
          <fields>
12178 
            <field>
12179 
              <name>TxCRC</name>
12180 
              <description>Tx CRC register</description>
12181 
              <bitOffset>0</bitOffset>
12182 
              <bitWidth>16</bitWidth>
12183 
            </field>
12184 
          </fields>
12185 
        </register>
12186 
        <register>
12187 
          <name>I2SCFGR</name>
12188 
          <displayName>I2SCFGR</displayName>
12189 
          <description>I2S configuration register</description>
12190 
          <addressOffset>0x1C</addressOffset>
12191 
          <size>0x20</size>
12192 
          <access>read-write</access>
12193 
          <resetValue>0x0000</resetValue>
12194 
          <fields>
12195 
            <field>
12196 
              <name>I2SMOD</name>
12197 
              <description>I2S mode selection</description>
12198 
              <bitOffset>11</bitOffset>
12199 
              <bitWidth>1</bitWidth>
12200 
            </field>
12201 
            <field>
12202 
              <name>I2SE</name>
12203 
              <description>I2S Enable</description>
12204 
              <bitOffset>10</bitOffset>
12205 
              <bitWidth>1</bitWidth>
12206 
            </field>
12207 
            <field>
12208 
              <name>I2SCFG</name>
12209 
              <description>I2S configuration mode</description>
12210 
              <bitOffset>8</bitOffset>
12211 
              <bitWidth>2</bitWidth>
12212 
            </field>
12213 
            <field>
12214 
              <name>PCMSYNC</name>
12215 
              <description>PCM frame synchronization</description>
12216 
              <bitOffset>7</bitOffset>
12217 
              <bitWidth>1</bitWidth>
12218 
            </field>
12219 
            <field>
12220 
              <name>I2SSTD</name>
12221 
              <description>I2S standard selection</description>
12222 
              <bitOffset>4</bitOffset>
12223 
              <bitWidth>2</bitWidth>
12224 
            </field>
12225 
            <field>
12226 
              <name>CKPOL</name>
12227 
              <description>Steady state clock
12228 
              polarity</description>
12229 
              <bitOffset>3</bitOffset>
12230 
              <bitWidth>1</bitWidth>
12231 
            </field>
12232 
            <field>
12233 
              <name>DATLEN</name>
12234 
              <description>Data length to be
12235 
              transferred</description>
12236 
              <bitOffset>1</bitOffset>
12237 
              <bitWidth>2</bitWidth>
12238 
            </field>
12239 
            <field>
12240 
              <name>CHLEN</name>
12241 
              <description>Channel length (number of bits per audio
12242 
              channel)</description>
12243 
              <bitOffset>0</bitOffset>
12244 
              <bitWidth>1</bitWidth>
12245 
            </field>
12246 
          </fields>
12247 
        </register>
12248 
        <register>
12249 
          <name>I2SPR</name>
12250 
          <displayName>I2SPR</displayName>
12251 
          <description>I2S prescaler register</description>
12252 
          <addressOffset>0x20</addressOffset>
12253 
          <size>0x20</size>
12254 
          <access>read-write</access>
12255 
          <resetValue>00000010</resetValue>
12256 
          <fields>
12257 
            <field>
12258 
              <name>MCKOE</name>
12259 
              <description>Master clock output enable</description>
12260 
              <bitOffset>9</bitOffset>
12261 
              <bitWidth>1</bitWidth>
12262 
            </field>
12263 
            <field>
12264 
              <name>ODD</name>
12265 
              <description>Odd factor for the
12266 
              prescaler</description>
12267 
              <bitOffset>8</bitOffset>
12268 
              <bitWidth>1</bitWidth>
12269 
            </field>
12270 
            <field>
12271 
              <name>I2SDIV</name>
12272 
              <description>I2S Linear prescaler</description>
12273 
              <bitOffset>0</bitOffset>
12274 
              <bitWidth>8</bitWidth>
12275 
            </field>
12276 
          </fields>
12277 
        </register>
12278 
      </registers>
12279 
    </peripheral>
12280 
    <peripheral derivedFrom="SPI1">
12281 
      <name>SPI2</name>
12282 
      <baseAddress>0x40003800</baseAddress>
12283 
      <interrupt>
12284 
        <name>SPI2</name>
12285 
        <description>SPI2 global interrupt</description>
12286 
        <value>36</value>
12287 
      </interrupt>
12288 
    </peripheral>
12289 
    <peripheral derivedFrom="SPI1">
12290 
      <name>SPI3</name>
12291 
      <baseAddress>0x40003C00</baseAddress>
12292 
      <interrupt>
12293 
        <name>SPI3</name>
12294 
        <description>SPI3 global interrupt</description>
12295 
        <value>51</value>
12296 
      </interrupt>
12297 
    </peripheral>
12298 
    <peripheral>
12299 
      <name>USART1</name>
12300 
      <description>Universal synchronous asynchronous receiver
12301 
      transmitter</description>
12302 
      <groupName>USART</groupName>
12303 
      <baseAddress>0x40013800</baseAddress>
12304 
      <addressBlock>
12305 
        <offset>0x0</offset>
12306 
        <size>0x400</size>
12307 
        <usage>registers</usage>
12308 
      </addressBlock>
12309 
      <interrupt>
12310 
        <name>USART1</name>
12311 
        <description>USART1 global interrupt</description>
12312 
        <value>37</value>
12313 
      </interrupt>
12314 
      <registers>
12315 
        <register>
12316 
          <name>SR</name>
12317 
          <displayName>SR</displayName>
12318 
          <description>Status register</description>
12319 
          <addressOffset>0x0</addressOffset>
12320 
          <size>0x20</size>
12321 
          <resetValue>0x00C0</resetValue>
12322 
          <fields>
12323 
            <field>
12324 
              <name>CTS</name>
12325 
              <description>CTS flag</description>
12326 
              <bitOffset>9</bitOffset>
12327 
              <bitWidth>1</bitWidth>
12328 
              <access>read-write</access>
12329 
            </field>
12330 
            <field>
12331 
              <name>LBD</name>
12332 
              <description>LIN break detection flag</description>
12333 
              <bitOffset>8</bitOffset>
12334 
              <bitWidth>1</bitWidth>
12335 
              <access>read-write</access>
12336 
            </field>
12337 
            <field>
12338 
              <name>TXE</name>
12339 
              <description>Transmit data register
12340 
              empty</description>
12341 
              <bitOffset>7</bitOffset>
12342 
              <bitWidth>1</bitWidth>
12343 
              <access>read-only</access>
12344 
            </field>
12345 
            <field>
12346 
              <name>TC</name>
12347 
              <description>Transmission complete</description>
12348 
              <bitOffset>6</bitOffset>
12349 
              <bitWidth>1</bitWidth>
12350 
              <access>read-write</access>
12351 
            </field>
12352 
            <field>
12353 
              <name>RXNE</name>
12354 
              <description>Read data register not
12355 
              empty</description>
12356 
              <bitOffset>5</bitOffset>
12357 
              <bitWidth>1</bitWidth>
12358 
              <access>read-write</access>
12359 
            </field>
12360 
            <field>
12361 
              <name>IDLE</name>
12362 
              <description>IDLE line detected</description>
12363 
              <bitOffset>4</bitOffset>
12364 
              <bitWidth>1</bitWidth>
12365 
              <access>read-only</access>
12366 
            </field>
12367 
            <field>
12368 
              <name>ORE</name>
12369 
              <description>Overrun error</description>
12370 
              <bitOffset>3</bitOffset>
12371 
              <bitWidth>1</bitWidth>
12372 
              <access>read-only</access>
12373 
            </field>
12374 
            <field>
12375 
              <name>NE</name>
12376 
              <description>Noise error flag</description>
12377 
              <bitOffset>2</bitOffset>
12378 
              <bitWidth>1</bitWidth>
12379 
              <access>read-only</access>
12380 
            </field>
12381 
            <field>
12382 
              <name>FE</name>
12383 
              <description>Framing error</description>
12384 
              <bitOffset>1</bitOffset>
12385 
              <bitWidth>1</bitWidth>
12386 
              <access>read-only</access>
12387 
            </field>
12388 
            <field>
12389 
              <name>PE</name>
12390 
              <description>Parity error</description>
12391 
              <bitOffset>0</bitOffset>
12392 
              <bitWidth>1</bitWidth>
12393 
              <access>read-only</access>
12394 
            </field>
12395 
          </fields>
12396 
        </register>
12397 
        <register>
12398 
          <name>DR</name>
12399 
          <displayName>DR</displayName>
12400 
          <description>Data register</description>
12401 
          <addressOffset>0x4</addressOffset>
12402 
          <size>0x20</size>
12403 
          <access>read-write</access>
12404 
          <resetValue>0x00000000</resetValue>
12405 
          <fields>
12406 
            <field>
12407 
              <name>DR</name>
12408 
              <description>Data value</description>
12409 
              <bitOffset>0</bitOffset>
12410 
              <bitWidth>9</bitWidth>
12411 
            </field>
12412 
          </fields>
12413 
        </register>
12414 
        <register>
12415 
          <name>BRR</name>
12416 
          <displayName>BRR</displayName>
12417 
          <description>Baud rate register</description>
12418 
          <addressOffset>0x8</addressOffset>
12419 
          <size>0x20</size>
12420 
          <access>read-write</access>
12421 
          <resetValue>0x0000</resetValue>
12422 
          <fields>
12423 
            <field>
12424 
              <name>DIV_Mantissa</name>
12425 
              <description>mantissa of USARTDIV</description>
12426 
              <bitOffset>4</bitOffset>
12427 
              <bitWidth>12</bitWidth>
12428 
            </field>
12429 
            <field>
12430 
              <name>DIV_Fraction</name>
12431 
              <description>fraction of USARTDIV</description>
12432 
              <bitOffset>0</bitOffset>
12433 
              <bitWidth>4</bitWidth>
12434 
            </field>
12435 
          </fields>
12436 
        </register>
12437 
        <register>
12438 
          <name>CR1</name>
12439 
          <displayName>CR1</displayName>
12440 
          <description>Control register 1</description>
12441 
          <addressOffset>0xC</addressOffset>
12442 
          <size>0x20</size>
12443 
          <access>read-write</access>
12444 
          <resetValue>0x0000</resetValue>
12445 
          <fields>
12446 
            <field>
12447 
              <name>UE</name>
12448 
              <description>USART enable</description>
12449 
              <bitOffset>13</bitOffset>
12450 
              <bitWidth>1</bitWidth>
12451 
            </field>
12452 
            <field>
12453 
              <name>M</name>
12454 
              <description>Word length</description>
12455 
              <bitOffset>12</bitOffset>
12456 
              <bitWidth>1</bitWidth>
12457 
            </field>
12458 
            <field>
12459 
              <name>WAKE</name>
12460 
              <description>Wakeup method</description>
12461 
              <bitOffset>11</bitOffset>
12462 
              <bitWidth>1</bitWidth>
12463 
            </field>
12464 
            <field>
12465 
              <name>PCE</name>
12466 
              <description>Parity control enable</description>
12467 
              <bitOffset>10</bitOffset>
12468 
              <bitWidth>1</bitWidth>
12469 
            </field>
12470 
            <field>
12471 
              <name>PS</name>
12472 
              <description>Parity selection</description>
12473 
              <bitOffset>9</bitOffset>
12474 
              <bitWidth>1</bitWidth>
12475 
            </field>
12476 
            <field>
12477 
              <name>PEIE</name>
12478 
              <description>PE interrupt enable</description>
12479 
              <bitOffset>8</bitOffset>
12480 
              <bitWidth>1</bitWidth>
12481 
            </field>
12482 
            <field>
12483 
              <name>TXEIE</name>
12484 
              <description>TXE interrupt enable</description>
12485 
              <bitOffset>7</bitOffset>
12486 
              <bitWidth>1</bitWidth>
12487 
            </field>
12488 
            <field>
12489 
              <name>TCIE</name>
12490 
              <description>Transmission complete interrupt
12491 
              enable</description>
12492 
              <bitOffset>6</bitOffset>
12493 
              <bitWidth>1</bitWidth>
12494 
            </field>
12495 
            <field>
12496 
              <name>RXNEIE</name>
12497 
              <description>RXNE interrupt enable</description>
12498 
              <bitOffset>5</bitOffset>
12499 
              <bitWidth>1</bitWidth>
12500 
            </field>
12501 
            <field>
12502 
              <name>IDLEIE</name>
12503 
              <description>IDLE interrupt enable</description>
12504 
              <bitOffset>4</bitOffset>
12505 
              <bitWidth>1</bitWidth>
12506 
            </field>
12507 
            <field>
12508 
              <name>TE</name>
12509 
              <description>Transmitter enable</description>
12510 
              <bitOffset>3</bitOffset>
12511 
              <bitWidth>1</bitWidth>
12512 
            </field>
12513 
            <field>
12514 
              <name>RE</name>
12515 
              <description>Receiver enable</description>
12516 
              <bitOffset>2</bitOffset>
12517 
              <bitWidth>1</bitWidth>
12518 
            </field>
12519 
            <field>
12520 
              <name>RWU</name>
12521 
              <description>Receiver wakeup</description>
12522 
              <bitOffset>1</bitOffset>
12523 
              <bitWidth>1</bitWidth>
12524 
            </field>
12525 
            <field>
12526 
              <name>SBK</name>
12527 
              <description>Send break</description>
12528 
              <bitOffset>0</bitOffset>
12529 
              <bitWidth>1</bitWidth>
12530 
            </field>
12531 
          </fields>
12532 
        </register>
12533 
        <register>
12534 
          <name>CR2</name>
12535 
          <displayName>CR2</displayName>
12536 
          <description>Control register 2</description>
12537 
          <addressOffset>0x10</addressOffset>
12538 
          <size>0x20</size>
12539 
          <access>read-write</access>
12540 
          <resetValue>0x0000</resetValue>
12541 
          <fields>
12542 
            <field>
12543 
              <name>LINEN</name>
12544 
              <description>LIN mode enable</description>
12545 
              <bitOffset>14</bitOffset>
12546 
              <bitWidth>1</bitWidth>
12547 
            </field>
12548 
            <field>
12549 
              <name>STOP</name>
12550 
              <description>STOP bits</description>
12551 
              <bitOffset>12</bitOffset>
12552 
              <bitWidth>2</bitWidth>
12553 
            </field>
12554 
            <field>
12555 
              <name>CLKEN</name>
12556 
              <description>Clock enable</description>
12557 
              <bitOffset>11</bitOffset>
12558 
              <bitWidth>1</bitWidth>
12559 
            </field>
12560 
            <field>
12561 
              <name>CPOL</name>
12562 
              <description>Clock polarity</description>
12563 
              <bitOffset>10</bitOffset>
12564 
              <bitWidth>1</bitWidth>
12565 
            </field>
12566 
            <field>
12567 
              <name>CPHA</name>
12568 
              <description>Clock phase</description>
12569 
              <bitOffset>9</bitOffset>
12570 
              <bitWidth>1</bitWidth>
12571 
            </field>
12572 
            <field>
12573 
              <name>LBCL</name>
12574 
              <description>Last bit clock pulse</description>
12575 
              <bitOffset>8</bitOffset>
12576 
              <bitWidth>1</bitWidth>
12577 
            </field>
12578 
            <field>
12579 
              <name>LBDIE</name>
12580 
              <description>LIN break detection interrupt
12581 
              enable</description>
12582 
              <bitOffset>6</bitOffset>
12583 
              <bitWidth>1</bitWidth>
12584 
            </field>
12585 
            <field>
12586 
              <name>LBDL</name>
12587 
              <description>lin break detection length</description>
12588 
              <bitOffset>5</bitOffset>
12589 
              <bitWidth>1</bitWidth>
12590 
            </field>
12591 
            <field>
12592 
              <name>ADD</name>
12593 
              <description>Address of the USART node</description>
12594 
              <bitOffset>0</bitOffset>
12595 
              <bitWidth>4</bitWidth>
12596 
            </field>
12597 
          </fields>
12598 
        </register>
12599 
        <register>
12600 
          <name>CR3</name>
12601 
          <displayName>CR3</displayName>
12602 
          <description>Control register 3</description>
12603 
          <addressOffset>0x14</addressOffset>
12604 
          <size>0x20</size>
12605 
          <access>read-write</access>
12606 
          <resetValue>0x0000</resetValue>
12607 
          <fields>
12608 
            <field>
12609 
              <name>CTSIE</name>
12610 
              <description>CTS interrupt enable</description>
12611 
              <bitOffset>10</bitOffset>
12612 
              <bitWidth>1</bitWidth>
12613 
            </field>
12614 
            <field>
12615 
              <name>CTSE</name>
12616 
              <description>CTS enable</description>
12617 
              <bitOffset>9</bitOffset>
12618 
              <bitWidth>1</bitWidth>
12619 
            </field>
12620 
            <field>
12621 
              <name>RTSE</name>
12622 
              <description>RTS enable</description>
12623 
              <bitOffset>8</bitOffset>
12624 
              <bitWidth>1</bitWidth>
12625 
            </field>
12626 
            <field>
12627 
              <name>DMAT</name>
12628 
              <description>DMA enable transmitter</description>
12629 
              <bitOffset>7</bitOffset>
12630 
              <bitWidth>1</bitWidth>
12631 
            </field>
12632 
            <field>
12633 
              <name>DMAR</name>
12634 
              <description>DMA enable receiver</description>
12635 
              <bitOffset>6</bitOffset>
12636 
              <bitWidth>1</bitWidth>
12637 
            </field>
12638 
            <field>
12639 
              <name>SCEN</name>
12640 
              <description>Smartcard mode enable</description>
12641 
              <bitOffset>5</bitOffset>
12642 
              <bitWidth>1</bitWidth>
12643 
            </field>
12644 
            <field>
12645 
              <name>NACK</name>
12646 
              <description>Smartcard NACK enable</description>
12647 
              <bitOffset>4</bitOffset>
12648 
              <bitWidth>1</bitWidth>
12649 
            </field>
12650 
            <field>
12651 
              <name>HDSEL</name>
12652 
              <description>Half-duplex selection</description>
12653 
              <bitOffset>3</bitOffset>
12654 
              <bitWidth>1</bitWidth>
12655 
            </field>
12656 
            <field>
12657 
              <name>IRLP</name>
12658 
              <description>IrDA low-power</description>
12659 
              <bitOffset>2</bitOffset>
12660 
              <bitWidth>1</bitWidth>
12661 
            </field>
12662 
            <field>
12663 
              <name>IREN</name>
12664 
              <description>IrDA mode enable</description>
12665 
              <bitOffset>1</bitOffset>
12666 
              <bitWidth>1</bitWidth>
12667 
            </field>
12668 
            <field>
12669 
              <name>EIE</name>
12670 
              <description>Error interrupt enable</description>
12671 
              <bitOffset>0</bitOffset>
12672 
              <bitWidth>1</bitWidth>
12673 
            </field>
12674 
          </fields>
12675 
        </register>
12676 
        <register>
12677 
          <name>GTPR</name>
12678 
          <displayName>GTPR</displayName>
12679 
          <description>Guard time and prescaler
12680 
          register</description>
12681 
          <addressOffset>0x18</addressOffset>
12682 
          <size>0x20</size>
12683 
          <access>read-write</access>
12684 
          <resetValue>0x0000</resetValue>
12685 
          <fields>
12686 
            <field>
12687 
              <name>GT</name>
12688 
              <description>Guard time value</description>
12689 
              <bitOffset>8</bitOffset>
12690 
              <bitWidth>8</bitWidth>
12691 
            </field>
12692 
            <field>
12693 
              <name>PSC</name>
12694 
              <description>Prescaler value</description>
12695 
              <bitOffset>0</bitOffset>
12696 
              <bitWidth>8</bitWidth>
12697 
            </field>
12698 
          </fields>
12699 
        </register>
12700 
      </registers>
12701 
    </peripheral>
12702 
    <peripheral derivedFrom="USART1">
12703 
      <name>USART2</name>
12704 
      <baseAddress>0x40004400</baseAddress>
12705 
      <interrupt>
12706 
        <name>USART2</name>
12707 
        <description>USART2 global interrupt</description>
12708 
        <value>38</value>
12709 
      </interrupt>
12710 
    </peripheral>
12711 
    <peripheral derivedFrom="USART1">
12712 
      <name>USART3</name>
12713 
      <baseAddress>0x40004800</baseAddress>
12714 
      <interrupt>
12715 
        <name>USART3</name>
12716 
        <description>USART3 global interrupt</description>
12717 
        <value>39</value>
12718 
      </interrupt>
12719 
    </peripheral>
12720 
    <peripheral>
12721 
      <name>ADC1</name>
12722 
      <description>Analog to digital converter</description>
12723 
      <groupName>ADC</groupName>
12724 
      <baseAddress>0x40012400</baseAddress>
12725 
      <addressBlock>
12726 
        <offset>0x0</offset>
12727 
        <size>0x400</size>
12728 
        <usage>registers</usage>
12729 
      </addressBlock>
12730 
      <interrupt>
12731 
        <name>ADC1_2</name>
12732 
        <description>ADC1 and ADC2 global interrupt</description>
12733 
        <value>18</value>
12734 
      </interrupt>
12735 
      <registers>
12736 
        <register>
12737 
          <name>SR</name>
12738 
          <displayName>SR</displayName>
12739 
          <description>status register</description>
12740 
          <addressOffset>0x0</addressOffset>
12741 
          <size>0x20</size>
12742 
          <access>read-write</access>
12743 
          <resetValue>0x00000000</resetValue>
12744 
          <fields>
12745 
            <field>
12746 
              <name>STRT</name>
12747 
              <description>Regular channel start flag</description>
12748 
              <bitOffset>4</bitOffset>
12749 
              <bitWidth>1</bitWidth>
12750 
            </field>
12751 
            <field>
12752 
              <name>JSTRT</name>
12753 
              <description>Injected channel start
12754 
              flag</description>
12755 
              <bitOffset>3</bitOffset>
12756 
              <bitWidth>1</bitWidth>
12757 
            </field>
12758 
            <field>
12759 
              <name>JEOC</name>
12760 
              <description>Injected channel end of
12761 
              conversion</description>
12762 
              <bitOffset>2</bitOffset>
12763 
              <bitWidth>1</bitWidth>
12764 
            </field>
12765 
            <field>
12766 
              <name>EOC</name>
12767 
              <description>Regular channel end of
12768 
              conversion</description>
12769 
              <bitOffset>1</bitOffset>
12770 
              <bitWidth>1</bitWidth>
12771 
            </field>
12772 
            <field>
12773 
              <name>AWD</name>
12774 
              <description>Analog watchdog flag</description>
12775 
              <bitOffset>0</bitOffset>
12776 
              <bitWidth>1</bitWidth>
12777 
            </field>
12778 
          </fields>
12779 
        </register>
12780 
        <register>
12781 
          <name>CR1</name>
12782 
          <displayName>CR1</displayName>
12783 
          <description>control register 1</description>
12784 
          <addressOffset>0x4</addressOffset>
12785 
          <size>0x20</size>
12786 
          <access>read-write</access>
12787 
          <resetValue>0x00000000</resetValue>
12788 
          <fields>
12789 
            <field>
12790 
              <name>AWDEN</name>
12791 
              <description>Analog watchdog enable on regular
12792 
              channels</description>
12793 
              <bitOffset>23</bitOffset>
12794 
              <bitWidth>1</bitWidth>
12795 
            </field>
12796 
            <field>
12797 
              <name>JAWDEN</name>
12798 
              <description>Analog watchdog enable on injected
12799 
              channels</description>
12800 
              <bitOffset>22</bitOffset>
12801 
              <bitWidth>1</bitWidth>
12802 
            </field>
12803 
            <field>
12804 
              <name>DUALMOD</name>
12805 
              <description>Dual mode selection</description>
12806 
              <bitOffset>16</bitOffset>
12807 
              <bitWidth>4</bitWidth>
12808 
            </field>
12809 
            <field>
12810 
              <name>DISCNUM</name>
12811 
              <description>Discontinuous mode channel
12812 
              count</description>
12813 
              <bitOffset>13</bitOffset>
12814 
              <bitWidth>3</bitWidth>
12815 
            </field>
12816 
            <field>
12817 
              <name>JDISCEN</name>
12818 
              <description>Discontinuous mode on injected
12819 
              channels</description>
12820 
              <bitOffset>12</bitOffset>
12821 
              <bitWidth>1</bitWidth>
12822 
            </field>
12823 
            <field>
12824 
              <name>DISCEN</name>
12825 
              <description>Discontinuous mode on regular
12826 
              channels</description>
12827 
              <bitOffset>11</bitOffset>
12828 
              <bitWidth>1</bitWidth>
12829 
            </field>
12830 
            <field>
12831 
              <name>JAUTO</name>
12832 
              <description>Automatic injected group
12833 
              conversion</description>
12834 
              <bitOffset>10</bitOffset>
12835 
              <bitWidth>1</bitWidth>
12836 
            </field>
12837 
            <field>
12838 
              <name>AWDSGL</name>
12839 
              <description>Enable the watchdog on a single channel
12840 
              in scan mode</description>
12841 
              <bitOffset>9</bitOffset>
12842 
              <bitWidth>1</bitWidth>
12843 
            </field>
12844 
            <field>
12845 
              <name>SCAN</name>
12846 
              <description>Scan mode</description>
12847 
              <bitOffset>8</bitOffset>
12848 
              <bitWidth>1</bitWidth>
12849 
            </field>
12850 
            <field>
12851 
              <name>JEOCIE</name>
12852 
              <description>Interrupt enable for injected
12853 
              channels</description>
12854 
              <bitOffset>7</bitOffset>
12855 
              <bitWidth>1</bitWidth>
12856 
            </field>
12857 
            <field>
12858 
              <name>AWDIE</name>
12859 
              <description>Analog watchdog interrupt
12860 
              enable</description>
12861 
              <bitOffset>6</bitOffset>
12862 
              <bitWidth>1</bitWidth>
12863 
            </field>
12864 
            <field>
12865 
              <name>EOCIE</name>
12866 
              <description>Interrupt enable for EOC</description>
12867 
              <bitOffset>5</bitOffset>
12868 
              <bitWidth>1</bitWidth>
12869 
            </field>
12870 
            <field>
12871 
              <name>AWDCH</name>
12872 
              <description>Analog watchdog channel select
12873 
              bits</description>
12874 
              <bitOffset>0</bitOffset>
12875 
              <bitWidth>5</bitWidth>
12876 
            </field>
12877 
          </fields>
12878 
        </register>
12879 
        <register>
12880 
          <name>CR2</name>
12881 
          <displayName>CR2</displayName>
12882 
          <description>control register 2</description>
12883 
          <addressOffset>0x8</addressOffset>
12884 
          <size>0x20</size>
12885 
          <access>read-write</access>
12886 
          <resetValue>0x00000000</resetValue>
12887 
          <fields>
12888 
            <field>
12889 
              <name>TSVREFE</name>
12890 
              <description>Temperature sensor and VREFINT
12891 
              enable</description>
12892 
              <bitOffset>23</bitOffset>
12893 
              <bitWidth>1</bitWidth>
12894 
            </field>
12895 
            <field>
12896 
              <name>SWSTART</name>
12897 
              <description>Start conversion of regular
12898 
              channels</description>
12899 
              <bitOffset>22</bitOffset>
12900 
              <bitWidth>1</bitWidth>
12901 
            </field>
12902 
            <field>
12903 
              <name>JSWSTART</name>
12904 
              <description>Start conversion of injected
12905 
              channels</description>
12906 
              <bitOffset>21</bitOffset>
12907 
              <bitWidth>1</bitWidth>
12908 
            </field>
12909 
            <field>
12910 
              <name>EXTTRIG</name>
12911 
              <description>External trigger conversion mode for
12912 
              regular channels</description>
12913 
              <bitOffset>20</bitOffset>
12914 
              <bitWidth>1</bitWidth>
12915 
            </field>
12916 
            <field>
12917 
              <name>EXTSEL</name>
12918 
              <description>External event select for regular
12919 
              group</description>
12920 
              <bitOffset>17</bitOffset>
12921 
              <bitWidth>3</bitWidth>
12922 
            </field>
12923 
            <field>
12924 
              <name>JEXTTRIG</name>
12925 
              <description>External trigger conversion mode for
12926 
              injected channels</description>
12927 
              <bitOffset>15</bitOffset>
12928 
              <bitWidth>1</bitWidth>
12929 
            </field>
12930 
            <field>
12931 
              <name>JEXTSEL</name>
12932 
              <description>External event select for injected
12933 
              group</description>
12934 
              <bitOffset>12</bitOffset>
12935 
              <bitWidth>3</bitWidth>
12936 
            </field>
12937 
            <field>
12938 
              <name>ALIGN</name>
12939 
              <description>Data alignment</description>
12940 
              <bitOffset>11</bitOffset>
12941 
              <bitWidth>1</bitWidth>
12942 
            </field>
12943 
            <field>
12944 
              <name>DMA</name>
12945 
              <description>Direct memory access mode</description>
12946 
              <bitOffset>8</bitOffset>
12947 
              <bitWidth>1</bitWidth>
12948 
            </field>
12949 
            <field>
12950 
              <name>RSTCAL</name>
12951 
              <description>Reset calibration</description>
12952 
              <bitOffset>3</bitOffset>
12953 
              <bitWidth>1</bitWidth>
12954 
            </field>
12955 
            <field>
12956 
              <name>CAL</name>
12957 
              <description>A/D calibration</description>
12958 
              <bitOffset>2</bitOffset>
12959 
              <bitWidth>1</bitWidth>
12960 
            </field>
12961 
            <field>
12962 
              <name>CONT</name>
12963 
              <description>Continuous conversion</description>
12964 
              <bitOffset>1</bitOffset>
12965 
              <bitWidth>1</bitWidth>
12966 
            </field>
12967 
            <field>
12968 
              <name>ADON</name>
12969 
              <description>A/D converter ON / OFF</description>
12970 
              <bitOffset>0</bitOffset>
12971 
              <bitWidth>1</bitWidth>
12972 
            </field>
12973 
          </fields>
12974 
        </register>
12975 
        <register>
12976 
          <name>SMPR1</name>
12977 
          <displayName>SMPR1</displayName>
12978 
          <description>sample time register 1</description>
12979 
          <addressOffset>0xC</addressOffset>
12980 
          <size>0x20</size>
12981 
          <access>read-write</access>
12982 
          <resetValue>0x00000000</resetValue>
12983 
          <fields>
12984 
            <field>
12985 
              <name>SMP10</name>
12986 
              <description>Channel 10 sample time
12987 
              selection</description>
12988 
              <bitOffset>0</bitOffset>
12989 
              <bitWidth>3</bitWidth>
12990 
            </field>
12991 
            <field>
12992 
              <name>SMP11</name>
12993 
              <description>Channel 11 sample time
12994 
              selection</description>
12995 
              <bitOffset>3</bitOffset>
12996 
              <bitWidth>3</bitWidth>
12997 
            </field>
12998 
            <field>
12999 
              <name>SMP12</name>
13000 
              <description>Channel 12 sample time
13001 
              selection</description>
13002 
              <bitOffset>6</bitOffset>
13003 
              <bitWidth>3</bitWidth>
13004 
            </field>
13005 
            <field>
13006 
              <name>SMP13</name>
13007 
              <description>Channel 13 sample time
13008 
              selection</description>
13009 
              <bitOffset>9</bitOffset>
13010 
              <bitWidth>3</bitWidth>
13011 
            </field>
13012 
            <field>
13013 
              <name>SMP14</name>
13014 
              <description>Channel 14 sample time
13015 
              selection</description>
13016 
              <bitOffset>12</bitOffset>
13017 
              <bitWidth>3</bitWidth>
13018 
            </field>
13019 
            <field>
13020 
              <name>SMP15</name>
13021 
              <description>Channel 15 sample time
13022 
              selection</description>
13023 
              <bitOffset>15</bitOffset>
13024 
              <bitWidth>3</bitWidth>
13025 
            </field>
13026 
            <field>
13027 
              <name>SMP16</name>
13028 
              <description>Channel 16 sample time
13029 
              selection</description>
13030 
              <bitOffset>18</bitOffset>
13031 
              <bitWidth>3</bitWidth>
13032 
            </field>
13033 
            <field>
13034 
              <name>SMP17</name>
13035 
              <description>Channel 17 sample time
13036 
              selection</description>
13037 
              <bitOffset>21</bitOffset>
13038 
              <bitWidth>3</bitWidth>
13039 
            </field>
13040 
          </fields>
13041 
        </register>
13042 
        <register>
13043 
          <name>SMPR2</name>
13044 
          <displayName>SMPR2</displayName>
13045 
          <description>sample time register 2</description>
13046 
          <addressOffset>0x10</addressOffset>
13047 
          <size>0x20</size>
13048 
          <access>read-write</access>
13049 
          <resetValue>0x00000000</resetValue>
13050 
          <fields>
13051 
            <field>
13052 
              <name>SMP0</name>
13053 
              <description>Channel 0 sample time
13054 
              selection</description>
13055 
              <bitOffset>0</bitOffset>
13056 
              <bitWidth>3</bitWidth>
13057 
            </field>
13058 
            <field>
13059 
              <name>SMP1</name>
13060 
              <description>Channel 1 sample time
13061 
              selection</description>
13062 
              <bitOffset>3</bitOffset>
13063 
              <bitWidth>3</bitWidth>
13064 
            </field>
13065 
            <field>
13066 
              <name>SMP2</name>
13067 
              <description>Channel 2 sample time
13068 
              selection</description>
13069 
              <bitOffset>6</bitOffset>
13070 
              <bitWidth>3</bitWidth>
13071 
            </field>
13072 
            <field>
13073 
              <name>SMP3</name>
13074 
              <description>Channel 3 sample time
13075 
              selection</description>
13076 
              <bitOffset>9</bitOffset>
13077 
              <bitWidth>3</bitWidth>
13078 
            </field>
13079 
            <field>
13080 
              <name>SMP4</name>
13081 
              <description>Channel 4 sample time
13082 
              selection</description>
13083 
              <bitOffset>12</bitOffset>
13084 
              <bitWidth>3</bitWidth>
13085 
            </field>
13086 
            <field>
13087 
              <name>SMP5</name>
13088 
              <description>Channel 5 sample time
13089 
              selection</description>
13090 
              <bitOffset>15</bitOffset>
13091 
              <bitWidth>3</bitWidth>
13092 
            </field>
13093 
            <field>
13094 
              <name>SMP6</name>
13095 
              <description>Channel 6 sample time
13096 
              selection</description>
13097 
              <bitOffset>18</bitOffset>
13098 
              <bitWidth>3</bitWidth>
13099 
            </field>
13100 
            <field>
13101 
              <name>SMP7</name>
13102 
              <description>Channel 7 sample time
13103 
              selection</description>
13104 
              <bitOffset>21</bitOffset>
13105 
              <bitWidth>3</bitWidth>
13106 
            </field>
13107 
            <field>
13108 
              <name>SMP8</name>
13109 
              <description>Channel 8 sample time
13110 
              selection</description>
13111 
              <bitOffset>24</bitOffset>
13112 
              <bitWidth>3</bitWidth>
13113 
            </field>
13114 
            <field>
13115 
              <name>SMP9</name>
13116 
              <description>Channel 9 sample time
13117 
              selection</description>
13118 
              <bitOffset>27</bitOffset>
13119 
              <bitWidth>3</bitWidth>
13120 
            </field>
13121 
          </fields>
13122 
        </register>
13123 
        <register>
13124 
          <name>JOFR1</name>
13125 
          <displayName>JOFR1</displayName>
13126 
          <description>injected channel data offset register
13127 
          x</description>
13128 
          <addressOffset>0x14</addressOffset>
13129 
          <size>0x20</size>
13130 
          <access>read-write</access>
13131 
          <resetValue>0x00000000</resetValue>
13132 
          <fields>
13133 
            <field>
13134 
              <name>JOFFSET1</name>
13135 
              <description>Data offset for injected channel
13136 
              x</description>
13137 
              <bitOffset>0</bitOffset>
13138 
              <bitWidth>12</bitWidth>
13139 
            </field>
13140 
          </fields>
13141 
        </register>
13142 
        <register>
13143 
          <name>JOFR2</name>
13144 
          <displayName>JOFR2</displayName>
13145 
          <description>injected channel data offset register
13146 
          x</description>
13147 
          <addressOffset>0x18</addressOffset>
13148 
          <size>0x20</size>
13149 
          <access>read-write</access>
13150 
          <resetValue>0x00000000</resetValue>
13151 
          <fields>
13152 
            <field>
13153 
              <name>JOFFSET2</name>
13154 
              <description>Data offset for injected channel
13155 
              x</description>
13156 
              <bitOffset>0</bitOffset>
13157 
              <bitWidth>12</bitWidth>
13158 
            </field>
13159 
          </fields>
13160 
        </register>
13161 
        <register>
13162 
          <name>JOFR3</name>
13163 
          <displayName>JOFR3</displayName>
13164 
          <description>injected channel data offset register
13165 
          x</description>
13166 
          <addressOffset>0x1C</addressOffset>
13167 
          <size>0x20</size>
13168 
          <access>read-write</access>
13169 
          <resetValue>0x00000000</resetValue>
13170 
          <fields>
13171 
            <field>
13172 
              <name>JOFFSET3</name>
13173 
              <description>Data offset for injected channel
13174 
              x</description>
13175 
              <bitOffset>0</bitOffset>
13176 
              <bitWidth>12</bitWidth>
13177 
            </field>
13178 
          </fields>
13179 
        </register>
13180 
        <register>
13181 
          <name>JOFR4</name>
13182 
          <displayName>JOFR4</displayName>
13183 
          <description>injected channel data offset register
13184 
          x</description>
13185 
          <addressOffset>0x20</addressOffset>
13186 
          <size>0x20</size>
13187 
          <access>read-write</access>
13188 
          <resetValue>0x00000000</resetValue>
13189 
          <fields>
13190 
            <field>
13191 
              <name>JOFFSET4</name>
13192 
              <description>Data offset for injected channel
13193 
              x</description>
13194 
              <bitOffset>0</bitOffset>
13195 
              <bitWidth>12</bitWidth>
13196 
            </field>
13197 
          </fields>
13198 
        </register>
13199 
        <register>
13200 
          <name>HTR</name>
13201 
          <displayName>HTR</displayName>
13202 
          <description>watchdog higher threshold
13203 
          register</description>
13204 
          <addressOffset>0x24</addressOffset>
13205 
          <size>0x20</size>
13206 
          <access>read-write</access>
13207 
          <resetValue>0x00000FFF</resetValue>
13208 
          <fields>
13209 
            <field>
13210 
              <name>HT</name>
13211 
              <description>Analog watchdog higher
13212 
              threshold</description>
13213 
              <bitOffset>0</bitOffset>
13214 
              <bitWidth>12</bitWidth>
13215 
            </field>
13216 
          </fields>
13217 
        </register>
13218 
        <register>
13219 
          <name>LTR</name>
13220 
          <displayName>LTR</displayName>
13221 
          <description>watchdog lower threshold
13222 
          register</description>
13223 
          <addressOffset>0x28</addressOffset>
13224 
          <size>0x20</size>
13225 
          <access>read-write</access>
13226 
          <resetValue>0x00000000</resetValue>
13227 
          <fields>
13228 
            <field>
13229 
              <name>LT</name>
13230 
              <description>Analog watchdog lower
13231 
              threshold</description>
13232 
              <bitOffset>0</bitOffset>
13233 
              <bitWidth>12</bitWidth>
13234 
            </field>
13235 
          </fields>
13236 
        </register>
13237 
        <register>
13238 
          <name>SQR1</name>
13239 
          <displayName>SQR1</displayName>
13240 
          <description>regular sequence register 1</description>
13241 
          <addressOffset>0x2C</addressOffset>
13242 
          <size>0x20</size>
13243 
          <access>read-write</access>
13244 
          <resetValue>0x00000000</resetValue>
13245 
          <fields>
13246 
            <field>
13247 
              <name>L</name>
13248 
              <description>Regular channel sequence
13249 
              length</description>
13250 
              <bitOffset>20</bitOffset>
13251 
              <bitWidth>4</bitWidth>
13252 
            </field>
13253 
            <field>
13254 
              <name>SQ16</name>
13255 
              <description>16th conversion in regular
13256 
              sequence</description>
13257 
              <bitOffset>15</bitOffset>
13258 
              <bitWidth>5</bitWidth>
13259 
            </field>
13260 
            <field>
13261 
              <name>SQ15</name>
13262 
              <description>15th conversion in regular
13263 
              sequence</description>
13264 
              <bitOffset>10</bitOffset>
13265 
              <bitWidth>5</bitWidth>
13266 
            </field>
13267 
            <field>
13268 
              <name>SQ14</name>
13269 
              <description>14th conversion in regular
13270 
              sequence</description>
13271 
              <bitOffset>5</bitOffset>
13272 
              <bitWidth>5</bitWidth>
13273 
            </field>
13274 
            <field>
13275 
              <name>SQ13</name>
13276 
              <description>13th conversion in regular
13277 
              sequence</description>
13278 
              <bitOffset>0</bitOffset>
13279 
              <bitWidth>5</bitWidth>
13280 
            </field>
13281 
          </fields>
13282 
        </register>
13283 
        <register>
13284 
          <name>SQR2</name>
13285 
          <displayName>SQR2</displayName>
13286 
          <description>regular sequence register 2</description>
13287 
          <addressOffset>0x30</addressOffset>
13288 
          <size>0x20</size>
13289 
          <access>read-write</access>
13290 
          <resetValue>0x00000000</resetValue>
13291 
          <fields>
13292 
            <field>
13293 
              <name>SQ12</name>
13294 
              <description>12th conversion in regular
13295 
              sequence</description>
13296 
              <bitOffset>25</bitOffset>
13297 
              <bitWidth>5</bitWidth>
13298 
            </field>
13299 
            <field>
13300 
              <name>SQ11</name>
13301 
              <description>11th conversion in regular
13302 
              sequence</description>
13303 
              <bitOffset>20</bitOffset>
13304 
              <bitWidth>5</bitWidth>
13305 
            </field>
13306 
            <field>
13307 
              <name>SQ10</name>
13308 
              <description>10th conversion in regular
13309 
              sequence</description>
13310 
              <bitOffset>15</bitOffset>
13311 
              <bitWidth>5</bitWidth>
13312 
            </field>
13313 
            <field>
13314 
              <name>SQ9</name>
13315 
              <description>9th conversion in regular
13316 
              sequence</description>
13317 
              <bitOffset>10</bitOffset>
13318 
              <bitWidth>5</bitWidth>
13319 
            </field>
13320 
            <field>
13321 
              <name>SQ8</name>
13322 
              <description>8th conversion in regular
13323 
              sequence</description>
13324 
              <bitOffset>5</bitOffset>
13325 
              <bitWidth>5</bitWidth>
13326 
            </field>
13327 
            <field>
13328 
              <name>SQ7</name>
13329 
              <description>7th conversion in regular
13330 
              sequence</description>
13331 
              <bitOffset>0</bitOffset>
13332 
              <bitWidth>5</bitWidth>
13333 
            </field>
13334 
          </fields>
13335 
        </register>
13336 
        <register>
13337 
          <name>SQR3</name>
13338 
          <displayName>SQR3</displayName>
13339 
          <description>regular sequence register 3</description>
13340 
          <addressOffset>0x34</addressOffset>
13341 
          <size>0x20</size>
13342 
          <access>read-write</access>
13343 
          <resetValue>0x00000000</resetValue>
13344 
          <fields>
13345 
            <field>
13346 
              <name>SQ6</name>
13347 
              <description>6th conversion in regular
13348 
              sequence</description>
13349 
              <bitOffset>25</bitOffset>
13350 
              <bitWidth>5</bitWidth>
13351 
            </field>
13352 
            <field>
13353 
              <name>SQ5</name>
13354 
              <description>5th conversion in regular
13355 
              sequence</description>
13356 
              <bitOffset>20</bitOffset>
13357 
              <bitWidth>5</bitWidth>
13358 
            </field>
13359 
            <field>
13360 
              <name>SQ4</name>
13361 
              <description>4th conversion in regular
13362 
              sequence</description>
13363 
              <bitOffset>15</bitOffset>
13364 
              <bitWidth>5</bitWidth>
13365 
            </field>
13366 
            <field>
13367 
              <name>SQ3</name>
13368 
              <description>3rd conversion in regular
13369 
              sequence</description>
13370 
              <bitOffset>10</bitOffset>
13371 
              <bitWidth>5</bitWidth>
13372 
            </field>
13373 
            <field>
13374 
              <name>SQ2</name>
13375 
              <description>2nd conversion in regular
13376 
              sequence</description>
13377 
              <bitOffset>5</bitOffset>
13378 
              <bitWidth>5</bitWidth>
13379 
            </field>
13380 
            <field>
13381 
              <name>SQ1</name>
13382 
              <description>1st conversion in regular
13383 
              sequence</description>
13384 
              <bitOffset>0</bitOffset>
13385 
              <bitWidth>5</bitWidth>
13386 
            </field>
13387 
          </fields>
13388 
        </register>
13389 
        <register>
13390 
          <name>JSQR</name>
13391 
          <displayName>JSQR</displayName>
13392 
          <description>injected sequence register</description>
13393 
          <addressOffset>0x38</addressOffset>
13394 
          <size>0x20</size>
13395 
          <access>read-write</access>
13396 
          <resetValue>0x00000000</resetValue>
13397 
          <fields>
13398 
            <field>
13399 
              <name>JL</name>
13400 
              <description>Injected sequence length</description>
13401 
              <bitOffset>20</bitOffset>
13402 
              <bitWidth>2</bitWidth>
13403 
            </field>
13404 
            <field>
13405 
              <name>JSQ4</name>
13406 
              <description>4th conversion in injected
13407 
              sequence</description>
13408 
              <bitOffset>15</bitOffset>
13409 
              <bitWidth>5</bitWidth>
13410 
            </field>
13411 
            <field>
13412 
              <name>JSQ3</name>
13413 
              <description>3rd conversion in injected
13414 
              sequence</description>
13415 
              <bitOffset>10</bitOffset>
13416 
              <bitWidth>5</bitWidth>
13417 
            </field>
13418 
            <field>
13419 
              <name>JSQ2</name>
13420 
              <description>2nd conversion in injected
13421 
              sequence</description>
13422 
              <bitOffset>5</bitOffset>
13423 
              <bitWidth>5</bitWidth>
13424 
            </field>
13425 
            <field>
13426 
              <name>JSQ1</name>
13427 
              <description>1st conversion in injected
13428 
              sequence</description>
13429 
              <bitOffset>0</bitOffset>
13430 
              <bitWidth>5</bitWidth>
13431 
            </field>
13432 
          </fields>
13433 
        </register>
13434 
        <register>
13435 
          <name>JDR1</name>
13436 
          <displayName>JDR1</displayName>
13437 
          <description>injected data register x</description>
13438 
          <addressOffset>0x3C</addressOffset>
13439 
          <size>0x20</size>
13440 
          <access>read-only</access>
13441 
          <resetValue>0x00000000</resetValue>
13442 
          <fields>
13443 
            <field>
13444 
              <name>JDATA</name>
13445 
              <description>Injected data</description>
13446 
              <bitOffset>0</bitOffset>
13447 
              <bitWidth>16</bitWidth>
13448 
            </field>
13449 
          </fields>
13450 
        </register>
13451 
        <register>
13452 
          <name>JDR2</name>
13453 
          <displayName>JDR2</displayName>
13454 
          <description>injected data register x</description>
13455 
          <addressOffset>0x40</addressOffset>
13456 
          <size>0x20</size>
13457 
          <access>read-only</access>
13458 
          <resetValue>0x00000000</resetValue>
13459 
          <fields>
13460 
            <field>
13461 
              <name>JDATA</name>
13462 
              <description>Injected data</description>
13463 
              <bitOffset>0</bitOffset>
13464 
              <bitWidth>16</bitWidth>
13465 
            </field>
13466 
          </fields>
13467 
        </register>
13468 
        <register>
13469 
          <name>JDR3</name>
13470 
          <displayName>JDR3</displayName>
13471 
          <description>injected data register x</description>
13472 
          <addressOffset>0x44</addressOffset>
13473 
          <size>0x20</size>
13474 
          <access>read-only</access>
13475 
          <resetValue>0x00000000</resetValue>
13476 
          <fields>
13477 
            <field>
13478 
              <name>JDATA</name>
13479 
              <description>Injected data</description>
13480 
              <bitOffset>0</bitOffset>
13481 
              <bitWidth>16</bitWidth>
13482 
            </field>
13483 
          </fields>
13484 
        </register>
13485 
        <register>
13486 
          <name>JDR4</name>
13487 
          <displayName>JDR4</displayName>
13488 
          <description>injected data register x</description>
13489 
          <addressOffset>0x48</addressOffset>
13490 
          <size>0x20</size>
13491 
          <access>read-only</access>
13492 
          <resetValue>0x00000000</resetValue>
13493 
          <fields>
13494 
            <field>
13495 
              <name>JDATA</name>
13496 
              <description>Injected data</description>
13497 
              <bitOffset>0</bitOffset>
13498 
              <bitWidth>16</bitWidth>
13499 
            </field>
13500 
          </fields>
13501 
        </register>
13502 
        <register>
13503 
          <name>DR</name>
13504 
          <displayName>DR</displayName>
13505 
          <description>regular data register</description>
13506 
          <addressOffset>0x4C</addressOffset>
13507 
          <size>0x20</size>
13508 
          <access>read-only</access>
13509 
          <resetValue>0x00000000</resetValue>
13510 
          <fields>
13511 
            <field>
13512 
              <name>DATA</name>
13513 
              <description>Regular data</description>
13514 
              <bitOffset>0</bitOffset>
13515 
              <bitWidth>16</bitWidth>
13516 
            </field>
13517 
            <field>
13518 
              <name>ADC2DATA</name>
13519 
              <description>ADC2 data</description>
13520 
              <bitOffset>16</bitOffset>
13521 
              <bitWidth>16</bitWidth>
13522 
            </field>
13523 
          </fields>
13524 
        </register>
13525 
      </registers>
13526 
    </peripheral>
13527 
    <peripheral>
13528 
      <name>ADC2</name>
13529 
      <description>Analog to digital converter</description>
13530 
      <groupName>ADC</groupName>
13531 
      <baseAddress>0x40012800</baseAddress>
13532 
      <addressBlock>
13533 
        <offset>0x0</offset>
13534 
        <size>0x400</size>
13535 
        <usage>registers</usage>
13536 
      </addressBlock>
13537 
      <registers>
13538 
        <register>
13539 
          <name>SR</name>
13540 
          <displayName>SR</displayName>
13541 
          <description>status register</description>
13542 
          <addressOffset>0x0</addressOffset>
13543 
          <size>0x20</size>
13544 
          <access>read-write</access>
13545 
          <resetValue>0x00000000</resetValue>
13546 
          <fields>
13547 
            <field>
13548 
              <name>STRT</name>
13549 
              <description>Regular channel start flag</description>
13550 
              <bitOffset>4</bitOffset>
13551 
              <bitWidth>1</bitWidth>
13552 
            </field>
13553 
            <field>
13554 
              <name>JSTRT</name>
13555 
              <description>Injected channel start
13556 
              flag</description>
13557 
              <bitOffset>3</bitOffset>
13558 
              <bitWidth>1</bitWidth>
13559 
            </field>
13560 
            <field>
13561 
              <name>JEOC</name>
13562 
              <description>Injected channel end of
13563 
              conversion</description>
13564 
              <bitOffset>2</bitOffset>
13565 
              <bitWidth>1</bitWidth>
13566 
            </field>
13567 
            <field>
13568 
              <name>EOC</name>
13569 
              <description>Regular channel end of
13570 
              conversion</description>
13571 
              <bitOffset>1</bitOffset>
13572 
              <bitWidth>1</bitWidth>
13573 
            </field>
13574 
            <field>
13575 
              <name>AWD</name>
13576 
              <description>Analog watchdog flag</description>
13577 
              <bitOffset>0</bitOffset>
13578 
              <bitWidth>1</bitWidth>
13579 
            </field>
13580 
          </fields>
13581 
        </register>
13582 
        <register>
13583 
          <name>CR1</name>
13584 
          <displayName>CR1</displayName>
13585 
          <description>control register 1</description>
13586 
          <addressOffset>0x4</addressOffset>
13587 
          <size>0x20</size>
13588 
          <access>read-write</access>
13589 
          <resetValue>0x00000000</resetValue>
13590 
          <fields>
13591 
            <field>
13592 
              <name>AWDEN</name>
13593 
              <description>Analog watchdog enable on regular
13594 
              channels</description>
13595 
              <bitOffset>23</bitOffset>
13596 
              <bitWidth>1</bitWidth>
13597 
            </field>
13598 
            <field>
13599 
              <name>JAWDEN</name>
13600 
              <description>Analog watchdog enable on injected
13601 
              channels</description>
13602 
              <bitOffset>22</bitOffset>
13603 
              <bitWidth>1</bitWidth>
13604 
            </field>
13605 
            <field>
13606 
              <name>DISCNUM</name>
13607 
              <description>Discontinuous mode channel
13608 
              count</description>
13609 
              <bitOffset>13</bitOffset>
13610 
              <bitWidth>3</bitWidth>
13611 
            </field>
13612 
            <field>
13613 
              <name>JDISCEN</name>
13614 
              <description>Discontinuous mode on injected
13615 
              channels</description>
13616 
              <bitOffset>12</bitOffset>
13617 
              <bitWidth>1</bitWidth>
13618 
            </field>
13619 
            <field>
13620 
              <name>DISCEN</name>
13621 
              <description>Discontinuous mode on regular
13622 
              channels</description>
13623 
              <bitOffset>11</bitOffset>
13624 
              <bitWidth>1</bitWidth>
13625 
            </field>
13626 
            <field>
13627 
              <name>JAUTO</name>
13628 
              <description>Automatic injected group
13629 
              conversion</description>
13630 
              <bitOffset>10</bitOffset>
13631 
              <bitWidth>1</bitWidth>
13632 
            </field>
13633 
            <field>
13634 
              <name>AWDSGL</name>
13635 
              <description>Enable the watchdog on a single channel
13636 
              in scan mode</description>
13637 
              <bitOffset>9</bitOffset>
13638 
              <bitWidth>1</bitWidth>
13639 
            </field>
13640 
            <field>
13641 
              <name>SCAN</name>
13642 
              <description>Scan mode</description>
13643 
              <bitOffset>8</bitOffset>
13644 
              <bitWidth>1</bitWidth>
13645 
            </field>
13646 
            <field>
13647 
              <name>JEOCIE</name>
13648 
              <description>Interrupt enable for injected
13649 
              channels</description>
13650 
              <bitOffset>7</bitOffset>
13651 
              <bitWidth>1</bitWidth>
13652 
            </field>
13653 
            <field>
13654 
              <name>AWDIE</name>
13655 
              <description>Analog watchdog interrupt
13656 
              enable</description>
13657 
              <bitOffset>6</bitOffset>
13658 
              <bitWidth>1</bitWidth>
13659 
            </field>
13660 
            <field>
13661 
              <name>EOCIE</name>
13662 
              <description>Interrupt enable for EOC</description>
13663 
              <bitOffset>5</bitOffset>
13664 
              <bitWidth>1</bitWidth>
13665 
            </field>
13666 
            <field>
13667 
              <name>AWDCH</name>
13668 
              <description>Analog watchdog channel select
13669 
              bits</description>
13670 
              <bitOffset>0</bitOffset>
13671 
              <bitWidth>5</bitWidth>
13672 
            </field>
13673 
          </fields>
13674 
        </register>
13675 
        <register>
13676 
          <name>CR2</name>
13677 
          <displayName>CR2</displayName>
13678 
          <description>control register 2</description>
13679 
          <addressOffset>0x8</addressOffset>
13680 
          <size>0x20</size>
13681 
          <access>read-write</access>
13682 
          <resetValue>0x00000000</resetValue>
13683 
          <fields>
13684 
            <field>
13685 
              <name>TSVREFE</name>
13686 
              <description>Temperature sensor and VREFINT
13687 
              enable</description>
13688 
              <bitOffset>23</bitOffset>
13689 
              <bitWidth>1</bitWidth>
13690 
            </field>
13691 
            <field>
13692 
              <name>SWSTART</name>
13693 
              <description>Start conversion of regular
13694 
              channels</description>
13695 
              <bitOffset>22</bitOffset>
13696 
              <bitWidth>1</bitWidth>
13697 
            </field>
13698 
            <field>
13699 
              <name>JSWSTART</name>
13700 
              <description>Start conversion of injected
13701 
              channels</description>
13702 
              <bitOffset>21</bitOffset>
13703 
              <bitWidth>1</bitWidth>
13704 
            </field>
13705 
            <field>
13706 
              <name>EXTTRIG</name>
13707 
              <description>External trigger conversion mode for
13708 
              regular channels</description>
13709 
              <bitOffset>20</bitOffset>
13710 
              <bitWidth>1</bitWidth>
13711 
            </field>
13712 
            <field>
13713 
              <name>EXTSEL</name>
13714 
              <description>External event select for regular
13715 
              group</description>
13716 
              <bitOffset>17</bitOffset>
13717 
              <bitWidth>3</bitWidth>
13718 
            </field>
13719 
            <field>
13720 
              <name>JEXTTRIG</name>
13721 
              <description>External trigger conversion mode for
13722 
              injected channels</description>
13723 
              <bitOffset>15</bitOffset>
13724 
              <bitWidth>1</bitWidth>
13725 
            </field>
13726 
            <field>
13727 
              <name>JEXTSEL</name>
13728 
              <description>External event select for injected
13729 
              group</description>
13730 
              <bitOffset>12</bitOffset>
13731 
              <bitWidth>3</bitWidth>
13732 
            </field>
13733 
            <field>
13734 
              <name>ALIGN</name>
13735 
              <description>Data alignment</description>
13736 
              <bitOffset>11</bitOffset>
13737 
              <bitWidth>1</bitWidth>
13738 
            </field>
13739 
            <field>
13740 
              <name>DMA</name>
13741 
              <description>Direct memory access mode</description>
13742 
              <bitOffset>8</bitOffset>
13743 
              <bitWidth>1</bitWidth>
13744 
            </field>
13745 
            <field>
13746 
              <name>RSTCAL</name>
13747 
              <description>Reset calibration</description>
13748 
              <bitOffset>3</bitOffset>
13749 
              <bitWidth>1</bitWidth>
13750 
            </field>
13751 
            <field>
13752 
              <name>CAL</name>
13753 
              <description>A/D calibration</description>
13754 
              <bitOffset>2</bitOffset>
13755 
              <bitWidth>1</bitWidth>
13756 
            </field>
13757 
            <field>
13758 
              <name>CONT</name>
13759 
              <description>Continuous conversion</description>
13760 
              <bitOffset>1</bitOffset>
13761 
              <bitWidth>1</bitWidth>
13762 
            </field>
13763 
            <field>
13764 
              <name>ADON</name>
13765 
              <description>A/D converter ON / OFF</description>
13766 
              <bitOffset>0</bitOffset>
13767 
              <bitWidth>1</bitWidth>
13768 
            </field>
13769 
          </fields>
13770 
        </register>
13771 
        <register>
13772 
          <name>SMPR1</name>
13773 
          <displayName>SMPR1</displayName>
13774 
          <description>sample time register 1</description>
13775 
          <addressOffset>0xC</addressOffset>
13776 
          <size>0x20</size>
13777 
          <access>read-write</access>
13778 
          <resetValue>0x00000000</resetValue>
13779 
          <fields>
13780 
            <field>
13781 
              <name>SMP10</name>
13782 
              <description>Channel 10 sample time
13783 
              selection</description>
13784 
              <bitOffset>0</bitOffset>
13785 
              <bitWidth>3</bitWidth>
13786 
            </field>
13787 
            <field>
13788 
              <name>SMP11</name>
13789 
              <description>Channel 11 sample time
13790 
              selection</description>
13791 
              <bitOffset>3</bitOffset>
13792 
              <bitWidth>3</bitWidth>
13793 
            </field>
13794 
            <field>
13795 
              <name>SMP12</name>
13796 
              <description>Channel 12 sample time
13797 
              selection</description>
13798 
              <bitOffset>6</bitOffset>
13799 
              <bitWidth>3</bitWidth>
13800 
            </field>
13801 
            <field>
13802 
              <name>SMP13</name>
13803 
              <description>Channel 13 sample time
13804 
              selection</description>
13805 
              <bitOffset>9</bitOffset>
13806 
              <bitWidth>3</bitWidth>
13807 
            </field>
13808 
            <field>
13809 
              <name>SMP14</name>
13810 
              <description>Channel 14 sample time
13811 
              selection</description>
13812 
              <bitOffset>12</bitOffset>
13813 
              <bitWidth>3</bitWidth>
13814 
            </field>
13815 
            <field>
13816 
              <name>SMP15</name>
13817 
              <description>Channel 15 sample time
13818 
              selection</description>
13819 
              <bitOffset>15</bitOffset>
13820 
              <bitWidth>3</bitWidth>
13821 
            </field>
13822 
            <field>
13823 
              <name>SMP16</name>
13824 
              <description>Channel 16 sample time
13825 
              selection</description>
13826 
              <bitOffset>18</bitOffset>
13827 
              <bitWidth>3</bitWidth>
13828 
            </field>
13829 
            <field>
13830 
              <name>SMP17</name>
13831 
              <description>Channel 17 sample time
13832 
              selection</description>
13833 
              <bitOffset>21</bitOffset>
13834 
              <bitWidth>3</bitWidth>
13835 
            </field>
13836 
          </fields>
13837 
        </register>
13838 
        <register>
13839 
          <name>SMPR2</name>
13840 
          <displayName>SMPR2</displayName>
13841 
          <description>sample time register 2</description>
13842 
          <addressOffset>0x10</addressOffset>
13843 
          <size>0x20</size>
13844 
          <access>read-write</access>
13845 
          <resetValue>0x00000000</resetValue>
13846 
          <fields>
13847 
            <field>
13848 
              <name>SMP0</name>
13849 
              <description>Channel 0 sample time
13850 
              selection</description>
13851 
              <bitOffset>0</bitOffset>
13852 
              <bitWidth>3</bitWidth>
13853 
            </field>
13854 
            <field>
13855 
              <name>SMP1</name>
13856 
              <description>Channel 1 sample time
13857 
              selection</description>
13858 
              <bitOffset>3</bitOffset>
13859 
              <bitWidth>3</bitWidth>
13860 
            </field>
13861 
            <field>
13862 
              <name>SMP2</name>
13863 
              <description>Channel 2 sample time
13864 
              selection</description>
13865 
              <bitOffset>6</bitOffset>
13866 
              <bitWidth>3</bitWidth>
13867 
            </field>
13868 
            <field>
13869 
              <name>SMP3</name>
13870 
              <description>Channel 3 sample time
13871 
              selection</description>
13872 
              <bitOffset>9</bitOffset>
13873 
              <bitWidth>3</bitWidth>
13874 
            </field>
13875 
            <field>
13876 
              <name>SMP4</name>
13877 
              <description>Channel 4 sample time
13878 
              selection</description>
13879 
              <bitOffset>12</bitOffset>
13880 
              <bitWidth>3</bitWidth>
13881 
            </field>
13882 
            <field>
13883 
              <name>SMP5</name>
13884 
              <description>Channel 5 sample time
13885 
              selection</description>
13886 
              <bitOffset>15</bitOffset>
13887 
              <bitWidth>3</bitWidth>
13888 
            </field>
13889 
            <field>
13890 
              <name>SMP6</name>
13891 
              <description>Channel 6 sample time
13892 
              selection</description>
13893 
              <bitOffset>18</bitOffset>
13894 
              <bitWidth>3</bitWidth>
13895 
            </field>
13896 
            <field>
13897 
              <name>SMP7</name>
13898 
              <description>Channel 7 sample time
13899 
              selection</description>
13900 
              <bitOffset>21</bitOffset>
13901 
              <bitWidth>3</bitWidth>
13902 
            </field>
13903 
            <field>
13904 
              <name>SMP8</name>
13905 
              <description>Channel 8 sample time
13906 
              selection</description>
13907 
              <bitOffset>24</bitOffset>
13908 
              <bitWidth>3</bitWidth>
13909 
            </field>
13910 
            <field>
13911 
              <name>SMP9</name>
13912 
              <description>Channel 9 sample time
13913 
              selection</description>
13914 
              <bitOffset>27</bitOffset>
13915 
              <bitWidth>3</bitWidth>
13916 
            </field>
13917 
          </fields>
13918 
        </register>
13919 
        <register>
13920 
          <name>JOFR1</name>
13921 
          <displayName>JOFR1</displayName>
13922 
          <description>injected channel data offset register
13923 
          x</description>
13924 
          <addressOffset>0x14</addressOffset>
13925 
          <size>0x20</size>
13926 
          <access>read-write</access>
13927 
          <resetValue>0x00000000</resetValue>
13928 
          <fields>
13929 
            <field>
13930 
              <name>JOFFSET1</name>
13931 
              <description>Data offset for injected channel
13932 
              x</description>
13933 
              <bitOffset>0</bitOffset>
13934 
              <bitWidth>12</bitWidth>
13935 
            </field>
13936 
          </fields>
13937 
        </register>
13938 
        <register>
13939 
          <name>JOFR2</name>
13940 
          <displayName>JOFR2</displayName>
13941 
          <description>injected channel data offset register
13942 
          x</description>
13943 
          <addressOffset>0x18</addressOffset>
13944 
          <size>0x20</size>
13945 
          <access>read-write</access>
13946 
          <resetValue>0x00000000</resetValue>
13947 
          <fields>
13948 
            <field>
13949 
              <name>JOFFSET2</name>
13950 
              <description>Data offset for injected channel
13951 
              x</description>
13952 
              <bitOffset>0</bitOffset>
13953 
              <bitWidth>12</bitWidth>
13954 
            </field>
13955 
          </fields>
13956 
        </register>
13957 
        <register>
13958 
          <name>JOFR3</name>
13959 
          <displayName>JOFR3</displayName>
13960 
          <description>injected channel data offset register
13961 
          x</description>
13962 
          <addressOffset>0x1C</addressOffset>
13963 
          <size>0x20</size>
13964 
          <access>read-write</access>
13965 
          <resetValue>0x00000000</resetValue>
13966 
          <fields>
13967 
            <field>
13968 
              <name>JOFFSET3</name>
13969 
              <description>Data offset for injected channel
13970 
              x</description>
13971 
              <bitOffset>0</bitOffset>
13972 
              <bitWidth>12</bitWidth>
13973 
            </field>
13974 
          </fields>
13975 
        </register>
13976 
        <register>
13977 
          <name>JOFR4</name>
13978 
          <displayName>JOFR4</displayName>
13979 
          <description>injected channel data offset register
13980 
          x</description>
13981 
          <addressOffset>0x20</addressOffset>
13982 
          <size>0x20</size>
13983 
          <access>read-write</access>
13984 
          <resetValue>0x00000000</resetValue>
13985 
          <fields>
13986 
            <field>
13987 
              <name>JOFFSET4</name>
13988 
              <description>Data offset for injected channel
13989 
              x</description>
13990 
              <bitOffset>0</bitOffset>
13991 
              <bitWidth>12</bitWidth>
13992 
            </field>
13993 
          </fields>
13994 
        </register>
13995 
        <register>
13996 
          <name>HTR</name>
13997 
          <displayName>HTR</displayName>
13998 
          <description>watchdog higher threshold
13999 
          register</description>
14000 
          <addressOffset>0x24</addressOffset>
14001 
          <size>0x20</size>
14002 
          <access>read-write</access>
14003 
          <resetValue>0x00000FFF</resetValue>
14004 
          <fields>
14005 
            <field>
14006 
              <name>HT</name>
14007 
              <description>Analog watchdog higher
14008 
              threshold</description>
14009 
              <bitOffset>0</bitOffset>
14010 
              <bitWidth>12</bitWidth>
14011 
            </field>
14012 
          </fields>
14013 
        </register>
14014 
        <register>
14015 
          <name>LTR</name>
14016 
          <displayName>LTR</displayName>
14017 
          <description>watchdog lower threshold
14018 
          register</description>
14019 
          <addressOffset>0x28</addressOffset>
14020 
          <size>0x20</size>
14021 
          <access>read-write</access>
14022 
          <resetValue>0x00000000</resetValue>
14023 
          <fields>
14024 
            <field>
14025 
              <name>LT</name>
14026 
              <description>Analog watchdog lower
14027 
              threshold</description>
14028 
              <bitOffset>0</bitOffset>
14029 
              <bitWidth>12</bitWidth>
14030 
            </field>
14031 
          </fields>
14032 
        </register>
14033 
        <register>
14034 
          <name>SQR1</name>
14035 
          <displayName>SQR1</displayName>
14036 
          <description>regular sequence register 1</description>
14037 
          <addressOffset>0x2C</addressOffset>
14038 
          <size>0x20</size>
14039 
          <access>read-write</access>
14040 
          <resetValue>0x00000000</resetValue>
14041 
          <fields>
14042 
            <field>
14043 
              <name>L</name>
14044 
              <description>Regular channel sequence
14045 
              length</description>
14046 
              <bitOffset>20</bitOffset>
14047 
              <bitWidth>4</bitWidth>
14048 
            </field>
14049 
            <field>
14050 
              <name>SQ16</name>
14051 
              <description>16th conversion in regular
14052 
              sequence</description>
14053 
              <bitOffset>15</bitOffset>
14054 
              <bitWidth>5</bitWidth>
14055 
            </field>
14056 
            <field>
14057 
              <name>SQ15</name>
14058 
              <description>15th conversion in regular
14059 
              sequence</description>
14060 
              <bitOffset>10</bitOffset>
14061 
              <bitWidth>5</bitWidth>
14062 
            </field>
14063 
            <field>
14064 
              <name>SQ14</name>
14065 
              <description>14th conversion in regular
14066 
              sequence</description>
14067 
              <bitOffset>5</bitOffset>
14068 
              <bitWidth>5</bitWidth>
14069 
            </field>
14070 
            <field>
14071 
              <name>SQ13</name>
14072 
              <description>13th conversion in regular
14073 
              sequence</description>
14074 
              <bitOffset>0</bitOffset>
14075 
              <bitWidth>5</bitWidth>
14076 
            </field>
14077 
          </fields>
14078 
        </register>
14079 
        <register>
14080 
          <name>SQR2</name>
14081 
          <displayName>SQR2</displayName>
14082 
          <description>regular sequence register 2</description>
14083 
          <addressOffset>0x30</addressOffset>
14084 
          <size>0x20</size>
14085 
          <access>read-write</access>
14086 
          <resetValue>0x00000000</resetValue>
14087 
          <fields>
14088 
            <field>
14089 
              <name>SQ12</name>
14090 
              <description>12th conversion in regular
14091 
              sequence</description>
14092 
              <bitOffset>25</bitOffset>
14093 
              <bitWidth>5</bitWidth>
14094 
            </field>
14095 
            <field>
14096 
              <name>SQ11</name>
14097 
              <description>11th conversion in regular
14098 
              sequence</description>
14099 
              <bitOffset>20</bitOffset>
14100 
              <bitWidth>5</bitWidth>
14101 
            </field>
14102 
            <field>
14103 
              <name>SQ10</name>
14104 
              <description>10th conversion in regular
14105 
              sequence</description>
14106 
              <bitOffset>15</bitOffset>
14107 
              <bitWidth>5</bitWidth>
14108 
            </field>
14109 
            <field>
14110 
              <name>SQ9</name>
14111 
              <description>9th conversion in regular
14112 
              sequence</description>
14113 
              <bitOffset>10</bitOffset>
14114 
              <bitWidth>5</bitWidth>
14115 
            </field>
14116 
            <field>
14117 
              <name>SQ8</name>
14118 
              <description>8th conversion in regular
14119 
              sequence</description>
14120 
              <bitOffset>5</bitOffset>
14121 
              <bitWidth>5</bitWidth>
14122 
            </field>
14123 
            <field>
14124 
              <name>SQ7</name>
14125 
              <description>7th conversion in regular
14126 
              sequence</description>
14127 
              <bitOffset>0</bitOffset>
14128 
              <bitWidth>5</bitWidth>
14129 
            </field>
14130 
          </fields>
14131 
        </register>
14132 
        <register>
14133 
          <name>SQR3</name>
14134 
          <displayName>SQR3</displayName>
14135 
          <description>regular sequence register 3</description>
14136 
          <addressOffset>0x34</addressOffset>
14137 
          <size>0x20</size>
14138 
          <access>read-write</access>
14139 
          <resetValue>0x00000000</resetValue>
14140 
          <fields>
14141 
            <field>
14142 
              <name>SQ6</name>
14143 
              <description>6th conversion in regular
14144 
              sequence</description>
14145 
              <bitOffset>25</bitOffset>
14146 
              <bitWidth>5</bitWidth>
14147 
            </field>
14148 
            <field>
14149 
              <name>SQ5</name>
14150 
              <description>5th conversion in regular
14151 
              sequence</description>
14152 
              <bitOffset>20</bitOffset>
14153 
              <bitWidth>5</bitWidth>
14154 
            </field>
14155 
            <field>
14156 
              <name>SQ4</name>
14157 
              <description>4th conversion in regular
14158 
              sequence</description>
14159 
              <bitOffset>15</bitOffset>
14160 
              <bitWidth>5</bitWidth>
14161 
            </field>
14162 
            <field>
14163 
              <name>SQ3</name>
14164 
              <description>3rd conversion in regular
14165 
              sequence</description>
14166 
              <bitOffset>10</bitOffset>
14167 
              <bitWidth>5</bitWidth>
14168 
            </field>
14169 
            <field>
14170 
              <name>SQ2</name>
14171 
              <description>2nd conversion in regular
14172 
              sequence</description>
14173 
              <bitOffset>5</bitOffset>
14174 
              <bitWidth>5</bitWidth>
14175 
            </field>
14176 
            <field>
14177 
              <name>SQ1</name>
14178 
              <description>1st conversion in regular
14179 
              sequence</description>
14180 
              <bitOffset>0</bitOffset>
14181 
              <bitWidth>5</bitWidth>
14182 
            </field>
14183 
          </fields>
14184 
        </register>
14185 
        <register>
14186 
          <name>JSQR</name>
14187 
          <displayName>JSQR</displayName>
14188 
          <description>injected sequence register</description>
14189 
          <addressOffset>0x38</addressOffset>
14190 
          <size>0x20</size>
14191 
          <access>read-write</access>
14192 
          <resetValue>0x00000000</resetValue>
14193 
          <fields>
14194 
            <field>
14195 
              <name>JL</name>
14196 
              <description>Injected sequence length</description>
14197 
              <bitOffset>20</bitOffset>
14198 
              <bitWidth>2</bitWidth>
14199 
            </field>
14200 
            <field>
14201 
              <name>JSQ4</name>
14202 
              <description>4th conversion in injected
14203 
              sequence</description>
14204 
              <bitOffset>15</bitOffset>
14205 
              <bitWidth>5</bitWidth>
14206 
            </field>
14207 
            <field>
14208 
              <name>JSQ3</name>
14209 
              <description>3rd conversion in injected
14210 
              sequence</description>
14211 
              <bitOffset>10</bitOffset>
14212 
              <bitWidth>5</bitWidth>
14213 
            </field>
14214 
            <field>
14215 
              <name>JSQ2</name>
14216 
              <description>2nd conversion in injected
14217 
              sequence</description>
14218 
              <bitOffset>5</bitOffset>
14219 
              <bitWidth>5</bitWidth>
14220 
            </field>
14221 
            <field>
14222 
              <name>JSQ1</name>
14223 
              <description>1st conversion in injected
14224 
              sequence</description>
14225 
              <bitOffset>0</bitOffset>
14226 
              <bitWidth>5</bitWidth>
14227 
            </field>
14228 
          </fields>
14229 
        </register>
14230 
        <register>
14231 
          <name>JDR1</name>
14232 
          <displayName>JDR1</displayName>
14233 
          <description>injected data register x</description>
14234 
          <addressOffset>0x3C</addressOffset>
14235 
          <size>0x20</size>
14236 
          <access>read-only</access>
14237 
          <resetValue>0x00000000</resetValue>
14238 
          <fields>
14239 
            <field>
14240 
              <name>JDATA</name>
14241 
              <description>Injected data</description>
14242 
              <bitOffset>0</bitOffset>
14243 
              <bitWidth>16</bitWidth>
14244 
            </field>
14245 
          </fields>
14246 
        </register>
14247 
        <register>
14248 
          <name>JDR2</name>
14249 
          <displayName>JDR2</displayName>
14250 
          <description>injected data register x</description>
14251 
          <addressOffset>0x40</addressOffset>
14252 
          <size>0x20</size>
14253 
          <access>read-only</access>
14254 
          <resetValue>0x00000000</resetValue>
14255 
          <fields>
14256 
            <field>
14257 
              <name>JDATA</name>
14258 
              <description>Injected data</description>
14259 
              <bitOffset>0</bitOffset>
14260 
              <bitWidth>16</bitWidth>
14261 
            </field>
14262 
          </fields>
14263 
        </register>
14264 
        <register>
14265 
          <name>JDR3</name>
14266 
          <displayName>JDR3</displayName>
14267 
          <description>injected data register x</description>
14268 
          <addressOffset>0x44</addressOffset>
14269 
          <size>0x20</size>
14270 
          <access>read-only</access>
14271 
          <resetValue>0x00000000</resetValue>
14272 
          <fields>
14273 
            <field>
14274 
              <name>JDATA</name>
14275 
              <description>Injected data</description>
14276 
              <bitOffset>0</bitOffset>
14277 
              <bitWidth>16</bitWidth>
14278 
            </field>
14279 
          </fields>
14280 
        </register>
14281 
        <register>
14282 
          <name>JDR4</name>
14283 
          <displayName>JDR4</displayName>
14284 
          <description>injected data register x</description>
14285 
          <addressOffset>0x48</addressOffset>
14286 
          <size>0x20</size>
14287 
          <access>read-only</access>
14288 
          <resetValue>0x00000000</resetValue>
14289 
          <fields>
14290 
            <field>
14291 
              <name>JDATA</name>
14292 
              <description>Injected data</description>
14293 
              <bitOffset>0</bitOffset>
14294 
              <bitWidth>16</bitWidth>
14295 
            </field>
14296 
          </fields>
14297 
        </register>
14298 
        <register>
14299 
          <name>DR</name>
14300 
          <displayName>DR</displayName>
14301 
          <description>regular data register</description>
14302 
          <addressOffset>0x4C</addressOffset>
14303 
          <size>0x20</size>
14304 
          <access>read-only</access>
14305 
          <resetValue>0x00000000</resetValue>
14306 
          <fields>
14307 
            <field>
14308 
              <name>DATA</name>
14309 
              <description>Regular data</description>
14310 
              <bitOffset>0</bitOffset>
14311 
              <bitWidth>16</bitWidth>
14312 
            </field>
14313 
          </fields>
14314 
        </register>
14315 
      </registers>
14316 
    </peripheral>
14317 
    <peripheral derivedFrom="ADC2">
14318 
      <name>ADC3</name>
14319 
      <baseAddress>0x40013C00</baseAddress>
14320 
      <interrupt>
14321 
        <name>ADC3</name>
14322 
        <description>ADC3 global interrupt</description>
14323 
        <value>47</value>
14324 
      </interrupt>
14325 
    </peripheral>
14326 
    <peripheral>
14327 
      <name>CAN1</name>
14328 
      <description>Controller area network</description>
14329 
      <groupName>CAN</groupName>
14330 
      <baseAddress>0x40006400</baseAddress>
14331 
      <addressBlock>
14332 
        <offset>0x0</offset>
14333 
        <size>0x400</size>
14334 
        <usage>registers</usage>
14335 
      </addressBlock>
14336 
      <interrupt>
14337 
        <name>CAN_RX1</name>
14338 
        <description>CAN RX1 interrupt</description>
14339 
        <value>21</value>
14340 
      </interrupt>
14341 
      <interrupt>
14342 
        <name>CAN_SCE</name>
14343 
        <description>CAN SCE interrupt</description>
14344 
        <value>22</value>
14345 
      </interrupt>
14346 
      <interrupt>
14347 
        <name>CAN_SCE</name>
14348 
        <description>CAN SCE interrupt</description>
14349 
        <value>22</value>
14350 
      </interrupt>
14351 
      <registers>
14352 
        <register>
14353 
          <name>CAN_MCR</name>
14354 
          <displayName>CAN_MCR</displayName>
14355 
          <description>CAN_MCR</description>
14356 
          <addressOffset>0x0</addressOffset>
14357 
          <size>0x20</size>
14358 
          <access>read-write</access>
14359 
          <resetValue>0x00000000</resetValue>
14360 
          <fields>
14361 
            <field>
14362 
              <name>DBF</name>
14363 
              <description>DBF</description>
14364 
              <bitOffset>16</bitOffset>
14365 
              <bitWidth>1</bitWidth>
14366 
            </field>
14367 
            <field>
14368 
              <name>RESET</name>
14369 
              <description>RESET</description>
14370 
              <bitOffset>15</bitOffset>
14371 
              <bitWidth>1</bitWidth>
14372 
            </field>
14373 
            <field>
14374 
              <name>TTCM</name>
14375 
              <description>TTCM</description>
14376 
              <bitOffset>7</bitOffset>
14377 
              <bitWidth>1</bitWidth>
14378 
            </field>
14379 
            <field>
14380 
              <name>ABOM</name>
14381 
              <description>ABOM</description>
14382 
              <bitOffset>6</bitOffset>
14383 
              <bitWidth>1</bitWidth>
14384 
            </field>
14385 
            <field>
14386 
              <name>AWUM</name>
14387 
              <description>AWUM</description>
14388 
              <bitOffset>5</bitOffset>
14389 
              <bitWidth>1</bitWidth>
14390 
            </field>
14391 
            <field>
14392 
              <name>NART</name>
14393 
              <description>NART</description>
14394 
              <bitOffset>4</bitOffset>
14395 
              <bitWidth>1</bitWidth>
14396 
            </field>
14397 
            <field>
14398 
              <name>RFLM</name>
14399 
              <description>RFLM</description>
14400 
              <bitOffset>3</bitOffset>
14401 
              <bitWidth>1</bitWidth>
14402 
            </field>
14403 
            <field>
14404 
              <name>TXFP</name>
14405 
              <description>TXFP</description>
14406 
              <bitOffset>2</bitOffset>
14407 
              <bitWidth>1</bitWidth>
14408 
            </field>
14409 
            <field>
14410 
              <name>SLEEP</name>
14411 
              <description>SLEEP</description>
14412 
              <bitOffset>1</bitOffset>
14413 
              <bitWidth>1</bitWidth>
14414 
            </field>
14415 
            <field>
14416 
              <name>INRQ</name>
14417 
              <description>INRQ</description>
14418 
              <bitOffset>0</bitOffset>
14419 
              <bitWidth>1</bitWidth>
14420 
            </field>
14421 
          </fields>
14422 
        </register>
14423 
        <register>
14424 
          <name>CAN_MSR</name>
14425 
          <displayName>CAN_MSR</displayName>
14426 
          <description>CAN_MSR</description>
14427 
          <addressOffset>0x4</addressOffset>
14428 
          <size>0x20</size>
14429 
          <resetValue>0x00000000</resetValue>
14430 
          <fields>
14431 
            <field>
14432 
              <name>RX</name>
14433 
              <description>RX</description>
14434 
              <bitOffset>11</bitOffset>
14435 
              <bitWidth>1</bitWidth>
14436 
              <access>read-only</access>
14437 
            </field>
14438 
            <field>
14439 
              <name>SAMP</name>
14440 
              <description>SAMP</description>
14441 
              <bitOffset>10</bitOffset>
14442 
              <bitWidth>1</bitWidth>
14443 
              <access>read-only</access>
14444 
            </field>
14445 
            <field>
14446 
              <name>RXM</name>
14447 
              <description>RXM</description>
14448 
              <bitOffset>9</bitOffset>
14449 
              <bitWidth>1</bitWidth>
14450 
              <access>read-only</access>
14451 
            </field>
14452 
            <field>
14453 
              <name>TXM</name>
14454 
              <description>TXM</description>
14455 
              <bitOffset>8</bitOffset>
14456 
              <bitWidth>1</bitWidth>
14457 
              <access>read-only</access>
14458 
            </field>
14459 
            <field>
14460 
              <name>SLAKI</name>
14461 
              <description>SLAKI</description>
14462 
              <bitOffset>4</bitOffset>
14463 
              <bitWidth>1</bitWidth>
14464 
              <access>read-write</access>
14465 
            </field>
14466 
            <field>
14467 
              <name>WKUI</name>
14468 
              <description>WKUI</description>
14469 
              <bitOffset>3</bitOffset>
14470 
              <bitWidth>1</bitWidth>
14471 
              <access>read-write</access>
14472 
            </field>
14473 
            <field>
14474 
              <name>ERRI</name>
14475 
              <description>ERRI</description>
14476 
              <bitOffset>2</bitOffset>
14477 
              <bitWidth>1</bitWidth>
14478 
              <access>read-write</access>
14479 
            </field>
14480 
            <field>
14481 
              <name>SLAK</name>
14482 
              <description>SLAK</description>
14483 
              <bitOffset>1</bitOffset>
14484 
              <bitWidth>1</bitWidth>
14485 
              <access>read-only</access>
14486 
            </field>
14487 
            <field>
14488 
              <name>INAK</name>
14489 
              <description>INAK</description>
14490 
              <bitOffset>0</bitOffset>
14491 
              <bitWidth>1</bitWidth>
14492 
              <access>read-only</access>
14493 
            </field>
14494 
          </fields>
14495 
        </register>
14496 
        <register>
14497 
          <name>CAN_TSR</name>
14498 
          <displayName>CAN_TSR</displayName>
14499 
          <description>CAN_TSR</description>
14500 
          <addressOffset>0x8</addressOffset>
14501 
          <size>0x20</size>
14502 
          <resetValue>0x00000000</resetValue>
14503 
          <fields>
14504 
            <field>
14505 
              <name>LOW2</name>
14506 
              <description>Lowest priority flag for mailbox
14507 
              2</description>
14508 
              <bitOffset>31</bitOffset>
14509 
              <bitWidth>1</bitWidth>
14510 
              <access>read-only</access>
14511 
            </field>
14512 
            <field>
14513 
              <name>LOW1</name>
14514 
              <description>Lowest priority flag for mailbox
14515 
              1</description>
14516 
              <bitOffset>30</bitOffset>
14517 
              <bitWidth>1</bitWidth>
14518 
              <access>read-only</access>
14519 
            </field>
14520 
            <field>
14521 
              <name>LOW0</name>
14522 
              <description>Lowest priority flag for mailbox
14523 
              0</description>
14524 
              <bitOffset>29</bitOffset>
14525 
              <bitWidth>1</bitWidth>
14526 
              <access>read-only</access>
14527 
            </field>
14528 
            <field>
14529 
              <name>TME2</name>
14530 
              <description>Lowest priority flag for mailbox
14531 
              2</description>
14532 
              <bitOffset>28</bitOffset>
14533 
              <bitWidth>1</bitWidth>
14534 
              <access>read-only</access>
14535 
            </field>
14536 
            <field>
14537 
              <name>TME1</name>
14538 
              <description>Lowest priority flag for mailbox
14539 
              1</description>
14540 
              <bitOffset>27</bitOffset>
14541 
              <bitWidth>1</bitWidth>
14542 
              <access>read-only</access>
14543 
            </field>
14544 
            <field>
14545 
              <name>TME0</name>
14546 
              <description>Lowest priority flag for mailbox
14547 
              0</description>
14548 
              <bitOffset>26</bitOffset>
14549 
              <bitWidth>1</bitWidth>
14550 
              <access>read-only</access>
14551 
            </field>
14552 
            <field>
14553 
              <name>CODE</name>
14554 
              <description>CODE</description>
14555 
              <bitOffset>24</bitOffset>
14556 
              <bitWidth>2</bitWidth>
14557 
              <access>read-only</access>
14558 
            </field>
14559 
            <field>
14560 
              <name>ABRQ2</name>
14561 
              <description>ABRQ2</description>
14562 
              <bitOffset>23</bitOffset>
14563 
              <bitWidth>1</bitWidth>
14564 
              <access>read-write</access>
14565 
            </field>
14566 
            <field>
14567 
              <name>TERR2</name>
14568 
              <description>TERR2</description>
14569 
              <bitOffset>19</bitOffset>
14570 
              <bitWidth>1</bitWidth>
14571 
              <access>read-write</access>
14572 
            </field>
14573 
            <field>
14574 
              <name>ALST2</name>
14575 
              <description>ALST2</description>
14576 
              <bitOffset>18</bitOffset>
14577 
              <bitWidth>1</bitWidth>
14578 
              <access>read-write</access>
14579 
            </field>
14580 
            <field>
14581 
              <name>TXOK2</name>
14582 
              <description>TXOK2</description>
14583 
              <bitOffset>17</bitOffset>
14584 
              <bitWidth>1</bitWidth>
14585 
              <access>read-write</access>
14586 
            </field>
14587 
            <field>
14588 
              <name>RQCP2</name>
14589 
              <description>RQCP2</description>
14590 
              <bitOffset>16</bitOffset>
14591 
              <bitWidth>1</bitWidth>
14592 
              <access>read-write</access>
14593 
            </field>
14594 
            <field>
14595 
              <name>ABRQ1</name>
14596 
              <description>ABRQ1</description>
14597 
              <bitOffset>15</bitOffset>
14598 
              <bitWidth>1</bitWidth>
14599 
              <access>read-write</access>
14600 
            </field>
14601 
            <field>
14602 
              <name>TERR1</name>
14603 
              <description>TERR1</description>
14604 
              <bitOffset>11</bitOffset>
14605 
              <bitWidth>1</bitWidth>
14606 
              <access>read-write</access>
14607 
            </field>
14608 
            <field>
14609 
              <name>ALST1</name>
14610 
              <description>ALST1</description>
14611 
              <bitOffset>10</bitOffset>
14612 
              <bitWidth>1</bitWidth>
14613 
              <access>read-write</access>
14614 
            </field>
14615 
            <field>
14616 
              <name>TXOK1</name>
14617 
              <description>TXOK1</description>
14618 
              <bitOffset>9</bitOffset>
14619 
              <bitWidth>1</bitWidth>
14620 
              <access>read-write</access>
14621 
            </field>
14622 
            <field>
14623 
              <name>RQCP1</name>
14624 
              <description>RQCP1</description>
14625 
              <bitOffset>8</bitOffset>
14626 
              <bitWidth>1</bitWidth>
14627 
              <access>read-write</access>
14628 
            </field>
14629 
            <field>
14630 
              <name>ABRQ0</name>
14631 
              <description>ABRQ0</description>
14632 
              <bitOffset>7</bitOffset>
14633 
              <bitWidth>1</bitWidth>
14634 
              <access>read-write</access>
14635 
            </field>
14636 
            <field>
14637 
              <name>TERR0</name>
14638 
              <description>TERR0</description>
14639 
              <bitOffset>3</bitOffset>
14640 
              <bitWidth>1</bitWidth>
14641 
              <access>read-write</access>
14642 
            </field>
14643 
            <field>
14644 
              <name>ALST0</name>
14645 
              <description>ALST0</description>
14646 
              <bitOffset>2</bitOffset>
14647 
              <bitWidth>1</bitWidth>
14648 
              <access>read-write</access>
14649 
            </field>
14650 
            <field>
14651 
              <name>TXOK0</name>
14652 
              <description>TXOK0</description>
14653 
              <bitOffset>1</bitOffset>
14654 
              <bitWidth>1</bitWidth>
14655 
              <access>read-write</access>
14656 
            </field>
14657 
            <field>
14658 
              <name>RQCP0</name>
14659 
              <description>RQCP0</description>
14660 
              <bitOffset>0</bitOffset>
14661 
              <bitWidth>1</bitWidth>
14662 
              <access>read-write</access>
14663 
            </field>
14664 
          </fields>
14665 
        </register>
14666 
        <register>
14667 
          <name>CAN_RF0R</name>
14668 
          <displayName>CAN_RF0R</displayName>
14669 
          <description>CAN_RF0R</description>
14670 
          <addressOffset>0xC</addressOffset>
14671 
          <size>0x20</size>
14672 
          <resetValue>0x00000000</resetValue>
14673 
          <fields>
14674 
            <field>
14675 
              <name>RFOM0</name>
14676 
              <description>RFOM0</description>
14677 
              <bitOffset>5</bitOffset>
14678 
              <bitWidth>1</bitWidth>
14679 
              <access>read-write</access>
14680 
            </field>
14681 
            <field>
14682 
              <name>FOVR0</name>
14683 
              <description>FOVR0</description>
14684 
              <bitOffset>4</bitOffset>
14685 
              <bitWidth>1</bitWidth>
14686 
              <access>read-write</access>
14687 
            </field>
14688 
            <field>
14689 
              <name>FULL0</name>
14690 
              <description>FULL0</description>
14691 
              <bitOffset>3</bitOffset>
14692 
              <bitWidth>1</bitWidth>
14693 
              <access>read-write</access>
14694 
            </field>
14695 
            <field>
14696 
              <name>FMP0</name>
14697 
              <description>FMP0</description>
14698 
              <bitOffset>0</bitOffset>
14699 
              <bitWidth>2</bitWidth>
14700 
              <access>read-only</access>
14701 
            </field>
14702 
          </fields>
14703 
        </register>
14704 
        <register>
14705 
          <name>CAN_RF1R</name>
14706 
          <displayName>CAN_RF1R</displayName>
14707 
          <description>CAN_RF1R</description>
14708 
          <addressOffset>0x10</addressOffset>
14709 
          <size>0x20</size>
14710 
          <resetValue>0x00000000</resetValue>
14711 
          <fields>
14712 
            <field>
14713 
              <name>RFOM1</name>
14714 
              <description>RFOM1</description>
14715 
              <bitOffset>5</bitOffset>
14716 
              <bitWidth>1</bitWidth>
14717 
              <access>read-write</access>
14718 
            </field>
14719 
            <field>
14720 
              <name>FOVR1</name>
14721 
              <description>FOVR1</description>
14722 
              <bitOffset>4</bitOffset>
14723 
              <bitWidth>1</bitWidth>
14724 
              <access>read-write</access>
14725 
            </field>
14726 
            <field>
14727 
              <name>FULL1</name>
14728 
              <description>FULL1</description>
14729 
              <bitOffset>3</bitOffset>
14730 
              <bitWidth>1</bitWidth>
14731 
              <access>read-write</access>
14732 
            </field>
14733 
            <field>
14734 
              <name>FMP1</name>
14735 
              <description>FMP1</description>
14736 
              <bitOffset>0</bitOffset>
14737 
              <bitWidth>2</bitWidth>
14738 
              <access>read-only</access>
14739 
            </field>
14740 
          </fields>
14741 
        </register>
14742 
        <register>
14743 
          <name>CAN_IER</name>
14744 
          <displayName>CAN_IER</displayName>
14745 
          <description>CAN_IER</description>
14746 
          <addressOffset>0x14</addressOffset>
14747 
          <size>0x20</size>
14748 
          <access>read-write</access>
14749 
          <resetValue>0x00000000</resetValue>
14750 
          <fields>
14751 
            <field>
14752 
              <name>SLKIE</name>
14753 
              <description>SLKIE</description>
14754 
              <bitOffset>17</bitOffset>
14755 
              <bitWidth>1</bitWidth>
14756 
            </field>
14757 
            <field>
14758 
              <name>WKUIE</name>
14759 
              <description>WKUIE</description>
14760 
              <bitOffset>16</bitOffset>
14761 
              <bitWidth>1</bitWidth>
14762 
            </field>
14763 
            <field>
14764 
              <name>ERRIE</name>
14765 
              <description>ERRIE</description>
14766 
              <bitOffset>15</bitOffset>
14767 
              <bitWidth>1</bitWidth>
14768 
            </field>
14769 
            <field>
14770 
              <name>LECIE</name>
14771 
              <description>LECIE</description>
14772 
              <bitOffset>11</bitOffset>
14773 
              <bitWidth>1</bitWidth>
14774 
            </field>
14775 
            <field>
14776 
              <name>BOFIE</name>
14777 
              <description>BOFIE</description>
14778 
              <bitOffset>10</bitOffset>
14779 
              <bitWidth>1</bitWidth>
14780 
            </field>
14781 
            <field>
14782 
              <name>EPVIE</name>
14783 
              <description>EPVIE</description>
14784 
              <bitOffset>9</bitOffset>
14785 
              <bitWidth>1</bitWidth>
14786 
            </field>
14787 
            <field>
14788 
              <name>EWGIE</name>
14789 
              <description>EWGIE</description>
14790 
              <bitOffset>8</bitOffset>
14791 
              <bitWidth>1</bitWidth>
14792 
            </field>
14793 
            <field>
14794 
              <name>FOVIE1</name>
14795 
              <description>FOVIE1</description>
14796 
              <bitOffset>6</bitOffset>
14797 
              <bitWidth>1</bitWidth>
14798 
            </field>
14799 
            <field>
14800 
              <name>FFIE1</name>
14801 
              <description>FFIE1</description>
14802 
              <bitOffset>5</bitOffset>
14803 
              <bitWidth>1</bitWidth>
14804 
            </field>
14805 
            <field>
14806 
              <name>FMPIE1</name>
14807 
              <description>FMPIE1</description>
14808 
              <bitOffset>4</bitOffset>
14809 
              <bitWidth>1</bitWidth>
14810 
            </field>
14811 
            <field>
14812 
              <name>FOVIE0</name>
14813 
              <description>FOVIE0</description>
14814 
              <bitOffset>3</bitOffset>
14815 
              <bitWidth>1</bitWidth>
14816 
            </field>
14817 
            <field>
14818 
              <name>FFIE0</name>
14819 
              <description>FFIE0</description>
14820 
              <bitOffset>2</bitOffset>
14821 
              <bitWidth>1</bitWidth>
14822 
            </field>
14823 
            <field>
14824 
              <name>FMPIE0</name>
14825 
              <description>FMPIE0</description>
14826 
              <bitOffset>1</bitOffset>
14827 
              <bitWidth>1</bitWidth>
14828 
            </field>
14829 
            <field>
14830 
              <name>TMEIE</name>
14831 
              <description>TMEIE</description>
14832 
              <bitOffset>0</bitOffset>
14833 
              <bitWidth>1</bitWidth>
14834 
            </field>
14835 
          </fields>
14836 
        </register>
14837 
        <register>
14838 
          <name>CAN_ESR</name>
14839 
          <displayName>CAN_ESR</displayName>
14840 
          <description>CAN_ESR</description>
14841 
          <addressOffset>0x18</addressOffset>
14842 
          <size>0x20</size>
14843 
          <resetValue>0x00000000</resetValue>
14844 
          <fields>
14845 
            <field>
14846 
              <name>REC</name>
14847 
              <description>REC</description>
14848 
              <bitOffset>24</bitOffset>
14849 
              <bitWidth>8</bitWidth>
14850 
              <access>read-only</access>
14851 
            </field>
14852 
            <field>
14853 
              <name>TEC</name>
14854 
              <description>TEC</description>
14855 
              <bitOffset>16</bitOffset>
14856 
              <bitWidth>8</bitWidth>
14857 
              <access>read-only</access>
14858 
            </field>
14859 
            <field>
14860 
              <name>LEC</name>
14861 
              <description>LEC</description>
14862 
              <bitOffset>4</bitOffset>
14863 
              <bitWidth>3</bitWidth>
14864 
              <access>read-write</access>
14865 
            </field>
14866 
            <field>
14867 
              <name>BOFF</name>
14868 
              <description>BOFF</description>
14869 
              <bitOffset>2</bitOffset>
14870 
              <bitWidth>1</bitWidth>
14871 
              <access>read-only</access>
14872 
            </field>
14873 
            <field>
14874 
              <name>EPVF</name>
14875 
              <description>EPVF</description>
14876 
              <bitOffset>1</bitOffset>
14877 
              <bitWidth>1</bitWidth>
14878 
              <access>read-only</access>
14879 
            </field>
14880 
            <field>
14881 
              <name>EWGF</name>
14882 
              <description>EWGF</description>
14883 
              <bitOffset>0</bitOffset>
14884 
              <bitWidth>1</bitWidth>
14885 
              <access>read-only</access>
14886 
            </field>
14887 
          </fields>
14888 
        </register>
14889 
        <register>
14890 
          <name>CAN_BTR</name>
14891 
          <displayName>CAN_BTR</displayName>
14892 
          <description>CAN_BTR</description>
14893 
          <addressOffset>0x1C</addressOffset>
14894 
          <size>0x20</size>
14895 
          <access>read-write</access>
14896 
          <resetValue>0x00000000</resetValue>
14897 
          <fields>
14898 
            <field>
14899 
              <name>SILM</name>
14900 
              <description>SILM</description>
14901 
              <bitOffset>31</bitOffset>
14902 
              <bitWidth>1</bitWidth>
14903 
            </field>
14904 
            <field>
14905 
              <name>LBKM</name>
14906 
              <description>LBKM</description>
14907 
              <bitOffset>30</bitOffset>
14908 
              <bitWidth>1</bitWidth>
14909 
            </field>
14910 
            <field>
14911 
              <name>SJW</name>
14912 
              <description>SJW</description>
14913 
              <bitOffset>24</bitOffset>
14914 
              <bitWidth>2</bitWidth>
14915 
            </field>
14916 
            <field>
14917 
              <name>TS2</name>
14918 
              <description>TS2</description>
14919 
              <bitOffset>20</bitOffset>
14920 
              <bitWidth>3</bitWidth>
14921 
            </field>
14922 
            <field>
14923 
              <name>TS1</name>
14924 
              <description>TS1</description>
14925 
              <bitOffset>16</bitOffset>
14926 
              <bitWidth>4</bitWidth>
14927 
            </field>
14928 
            <field>
14929 
              <name>BRP</name>
14930 
              <description>BRP</description>
14931 
              <bitOffset>0</bitOffset>
14932 
              <bitWidth>10</bitWidth>
14933 
            </field>
14934 
          </fields>
14935 
        </register>
14936 
        <register>
14937 
          <name>CAN_TI0R</name>
14938 
          <displayName>CAN_TI0R</displayName>
14939 
          <description>CAN_TI0R</description>
14940 
          <addressOffset>0x180</addressOffset>
14941 
          <size>0x20</size>
14942 
          <access>read-write</access>
14943 
          <resetValue>0x00000000</resetValue>
14944 
          <fields>
14945 
            <field>
14946 
              <name>STID</name>
14947 
              <description>STID</description>
14948 
              <bitOffset>21</bitOffset>
14949 
              <bitWidth>11</bitWidth>
14950 
            </field>
14951 
            <field>
14952 
              <name>EXID</name>
14953 
              <description>EXID</description>
14954 
              <bitOffset>3</bitOffset>
14955 
              <bitWidth>18</bitWidth>
14956 
            </field>
14957 
            <field>
14958 
              <name>IDE</name>
14959 
              <description>IDE</description>
14960 
              <bitOffset>2</bitOffset>
14961 
              <bitWidth>1</bitWidth>
14962 
            </field>
14963 
            <field>
14964 
              <name>RTR</name>
14965 
              <description>RTR</description>
14966 
              <bitOffset>1</bitOffset>
14967 
              <bitWidth>1</bitWidth>
14968 
            </field>
14969 
            <field>
14970 
              <name>TXRQ</name>
14971 
              <description>TXRQ</description>
14972 
              <bitOffset>0</bitOffset>
14973 
              <bitWidth>1</bitWidth>
14974 
            </field>
14975 
          </fields>
14976 
        </register>
14977 
        <register>
14978 
          <name>CAN_TDT0R</name>
14979 
          <displayName>CAN_TDT0R</displayName>
14980 
          <description>CAN_TDT0R</description>
14981 
          <addressOffset>0x184</addressOffset>
14982 
          <size>0x20</size>
14983 
          <access>read-write</access>
14984 
          <resetValue>0x00000000</resetValue>
14985 
          <fields>
14986 
            <field>
14987 
              <name>TIME</name>
14988 
              <description>TIME</description>
14989 
              <bitOffset>16</bitOffset>
14990 
              <bitWidth>16</bitWidth>
14991 
            </field>
14992 
            <field>
14993 
              <name>TGT</name>
14994 
              <description>TGT</description>
14995 
              <bitOffset>8</bitOffset>
14996 
              <bitWidth>1</bitWidth>
14997 
            </field>
14998 
            <field>
14999 
              <name>DLC</name>
15000 
              <description>DLC</description>
15001 
              <bitOffset>0</bitOffset>
15002 
              <bitWidth>4</bitWidth>
15003 
            </field>
15004 
          </fields>
15005 
        </register>
15006 
        <register>
15007 
          <name>CAN_TDL0R</name>
15008 
          <displayName>CAN_TDL0R</displayName>
15009 
          <description>CAN_TDL0R</description>
15010 
          <addressOffset>0x188</addressOffset>
15011 
          <size>0x20</size>
15012 
          <access>read-write</access>
15013 
          <resetValue>0x00000000</resetValue>
15014 
          <fields>
15015 
            <field>
15016 
              <name>DATA3</name>
15017 
              <description>DATA3</description>
15018 
              <bitOffset>24</bitOffset>
15019 
              <bitWidth>8</bitWidth>
15020 
            </field>
15021 
            <field>
15022 
              <name>DATA2</name>
15023 
              <description>DATA2</description>
15024 
              <bitOffset>16</bitOffset>
15025 
              <bitWidth>8</bitWidth>
15026 
            </field>
15027 
            <field>
15028 
              <name>DATA1</name>
15029 
              <description>DATA1</description>
15030 
              <bitOffset>8</bitOffset>
15031 
              <bitWidth>8</bitWidth>
15032 
            </field>
15033 
            <field>
15034 
              <name>DATA0</name>
15035 
              <description>DATA0</description>
15036 
              <bitOffset>0</bitOffset>
15037 
              <bitWidth>8</bitWidth>
15038 
            </field>
15039 
          </fields>
15040 
        </register>
15041 
        <register>
15042 
          <name>CAN_TDH0R</name>
15043 
          <displayName>CAN_TDH0R</displayName>
15044 
          <description>CAN_TDH0R</description>
15045 
          <addressOffset>0x18C</addressOffset>
15046 
          <size>0x20</size>
15047 
          <access>read-write</access>
15048 
          <resetValue>0x00000000</resetValue>
15049 
          <fields>
15050 
            <field>
15051 
              <name>DATA7</name>
15052 
              <description>DATA7</description>
15053 
              <bitOffset>24</bitOffset>
15054 
              <bitWidth>8</bitWidth>
15055 
            </field>
15056 
            <field>
15057 
              <name>DATA6</name>
15058 
              <description>DATA6</description>
15059 
              <bitOffset>16</bitOffset>
15060 
              <bitWidth>8</bitWidth>
15061 
            </field>
15062 
            <field>
15063 
              <name>DATA5</name>
15064 
              <description>DATA5</description>
15065 
              <bitOffset>8</bitOffset>
15066 
              <bitWidth>8</bitWidth>
15067 
            </field>
15068 
            <field>
15069 
              <name>DATA4</name>
15070 
              <description>DATA4</description>
15071 
              <bitOffset>0</bitOffset>
15072 
              <bitWidth>8</bitWidth>
15073 
            </field>
15074 
          </fields>
15075 
        </register>
15076 
        <register>
15077 
          <name>CAN_TI1R</name>
15078 
          <displayName>CAN_TI1R</displayName>
15079 
          <description>CAN_TI1R</description>
15080 
          <addressOffset>0x190</addressOffset>
15081 
          <size>0x20</size>
15082 
          <access>read-write</access>
15083 
          <resetValue>0x00000000</resetValue>
15084 
          <fields>
15085 
            <field>
15086 
              <name>STID</name>
15087 
              <description>STID</description>
15088 
              <bitOffset>21</bitOffset>
15089 
              <bitWidth>11</bitWidth>
15090 
            </field>
15091 
            <field>
15092 
              <name>EXID</name>
15093 
              <description>EXID</description>
15094 
              <bitOffset>3</bitOffset>
15095 
              <bitWidth>18</bitWidth>
15096 
            </field>
15097 
            <field>
15098 
              <name>IDE</name>
15099 
              <description>IDE</description>
15100 
              <bitOffset>2</bitOffset>
15101 
              <bitWidth>1</bitWidth>
15102 
            </field>
15103 
            <field>
15104 
              <name>RTR</name>
15105 
              <description>RTR</description>
15106 
              <bitOffset>1</bitOffset>
15107 
              <bitWidth>1</bitWidth>
15108 
            </field>
15109 
            <field>
15110 
              <name>TXRQ</name>
15111 
              <description>TXRQ</description>
15112 
              <bitOffset>0</bitOffset>
15113 
              <bitWidth>1</bitWidth>
15114 
            </field>
15115 
          </fields>
15116 
        </register>
15117 
        <register>
15118 
          <name>CAN_TDT1R</name>
15119 
          <displayName>CAN_TDT1R</displayName>
15120 
          <description>CAN_TDT1R</description>
15121 
          <addressOffset>0x194</addressOffset>
15122 
          <size>0x20</size>
15123 
          <access>read-write</access>
15124 
          <resetValue>0x00000000</resetValue>
15125 
          <fields>
15126 
            <field>
15127 
              <name>TIME</name>
15128 
              <description>TIME</description>
15129 
              <bitOffset>16</bitOffset>
15130 
              <bitWidth>16</bitWidth>
15131 
            </field>
15132 
            <field>
15133 
              <name>TGT</name>
15134 
              <description>TGT</description>
15135 
              <bitOffset>8</bitOffset>
15136 
              <bitWidth>1</bitWidth>
15137 
            </field>
15138 
            <field>
15139 
              <name>DLC</name>
15140 
              <description>DLC</description>
15141 
              <bitOffset>0</bitOffset>
15142 
              <bitWidth>4</bitWidth>
15143 
            </field>
15144 
          </fields>
15145 
        </register>
15146 
        <register>
15147 
          <name>CAN_TDL1R</name>
15148 
          <displayName>CAN_TDL1R</displayName>
15149 
          <description>CAN_TDL1R</description>
15150 
          <addressOffset>0x198</addressOffset>
15151 
          <size>0x20</size>
15152 
          <access>read-write</access>
15153 
          <resetValue>0x00000000</resetValue>
15154 
          <fields>
15155 
            <field>
15156 
              <name>DATA3</name>
15157 
              <description>DATA3</description>
15158 
              <bitOffset>24</bitOffset>
15159 
              <bitWidth>8</bitWidth>
15160 
            </field>
15161 
            <field>
15162 
              <name>DATA2</name>
15163 
              <description>DATA2</description>
15164 
              <bitOffset>16</bitOffset>
15165 
              <bitWidth>8</bitWidth>
15166 
            </field>
15167 
            <field>
15168 
              <name>DATA1</name>
15169 
              <description>DATA1</description>
15170 
              <bitOffset>8</bitOffset>
15171 
              <bitWidth>8</bitWidth>
15172 
            </field>
15173 
            <field>
15174 
              <name>DATA0</name>
15175 
              <description>DATA0</description>
15176 
              <bitOffset>0</bitOffset>
15177 
              <bitWidth>8</bitWidth>
15178 
            </field>
15179 
          </fields>
15180 
        </register>
15181 
        <register>
15182 
          <name>CAN_TDH1R</name>
15183 
          <displayName>CAN_TDH1R</displayName>
15184 
          <description>CAN_TDH1R</description>
15185 
          <addressOffset>0x19C</addressOffset>
15186 
          <size>0x20</size>
15187 
          <access>read-write</access>
15188 
          <resetValue>0x00000000</resetValue>
15189 
          <fields>
15190 
            <field>
15191 
              <name>DATA7</name>
15192 
              <description>DATA7</description>
15193 
              <bitOffset>24</bitOffset>
15194 
              <bitWidth>8</bitWidth>
15195 
            </field>
15196 
            <field>
15197 
              <name>DATA6</name>
15198 
              <description>DATA6</description>
15199 
              <bitOffset>16</bitOffset>
15200 
              <bitWidth>8</bitWidth>
15201 
            </field>
15202 
            <field>
15203 
              <name>DATA5</name>
15204 
              <description>DATA5</description>
15205 
              <bitOffset>8</bitOffset>
15206 
              <bitWidth>8</bitWidth>
15207 
            </field>
15208 
            <field>
15209 
              <name>DATA4</name>
15210 
              <description>DATA4</description>
15211 
              <bitOffset>0</bitOffset>
15212 
              <bitWidth>8</bitWidth>
15213 
            </field>
15214 
          </fields>
15215 
        </register>
15216 
        <register>
15217 
          <name>CAN_TI2R</name>
15218 
          <displayName>CAN_TI2R</displayName>
15219 
          <description>CAN_TI2R</description>
15220 
          <addressOffset>0x1A0</addressOffset>
15221 
          <size>0x20</size>
15222 
          <access>read-write</access>
15223 
          <resetValue>0x00000000</resetValue>
15224 
          <fields>
15225 
            <field>
15226 
              <name>STID</name>
15227 
              <description>STID</description>
15228 
              <bitOffset>21</bitOffset>
15229 
              <bitWidth>11</bitWidth>
15230 
            </field>
15231 
            <field>
15232 
              <name>EXID</name>
15233 
              <description>EXID</description>
15234 
              <bitOffset>3</bitOffset>
15235 
              <bitWidth>18</bitWidth>
15236 
            </field>
15237 
            <field>
15238 
              <name>IDE</name>
15239 
              <description>IDE</description>
15240 
              <bitOffset>2</bitOffset>
15241 
              <bitWidth>1</bitWidth>
15242 
            </field>
15243 
            <field>
15244 
              <name>RTR</name>
15245 
              <description>RTR</description>
15246 
              <bitOffset>1</bitOffset>
15247 
              <bitWidth>1</bitWidth>
15248 
            </field>
15249 
            <field>
15250 
              <name>TXRQ</name>
15251 
              <description>TXRQ</description>
15252 
              <bitOffset>0</bitOffset>
15253 
              <bitWidth>1</bitWidth>
15254 
            </field>
15255 
          </fields>
15256 
        </register>
15257 
        <register>
15258 
          <name>CAN_TDT2R</name>
15259 
          <displayName>CAN_TDT2R</displayName>
15260 
          <description>CAN_TDT2R</description>
15261 
          <addressOffset>0x1A4</addressOffset>
15262 
          <size>0x20</size>
15263 
          <access>read-write</access>
15264 
          <resetValue>0x00000000</resetValue>
15265 
          <fields>
15266 
            <field>
15267 
              <name>TIME</name>
15268 
              <description>TIME</description>
15269 
              <bitOffset>16</bitOffset>
15270 
              <bitWidth>16</bitWidth>
15271 
            </field>
15272 
            <field>
15273 
              <name>TGT</name>
15274 
              <description>TGT</description>
15275 
              <bitOffset>8</bitOffset>
15276 
              <bitWidth>1</bitWidth>
15277 
            </field>
15278 
            <field>
15279 
              <name>DLC</name>
15280 
              <description>DLC</description>
15281 
              <bitOffset>0</bitOffset>
15282 
              <bitWidth>4</bitWidth>
15283 
            </field>
15284 
          </fields>
15285 
        </register>
15286 
        <register>
15287 
          <name>CAN_TDL2R</name>
15288 
          <displayName>CAN_TDL2R</displayName>
15289 
          <description>CAN_TDL2R</description>
15290 
          <addressOffset>0x1A8</addressOffset>
15291 
          <size>0x20</size>
15292 
          <access>read-write</access>
15293 
          <resetValue>0x00000000</resetValue>
15294 
          <fields>
15295 
            <field>
15296 
              <name>DATA3</name>
15297 
              <description>DATA3</description>
15298 
              <bitOffset>24</bitOffset>
15299 
              <bitWidth>8</bitWidth>
15300 
            </field>
15301 
            <field>
15302 
              <name>DATA2</name>
15303 
              <description>DATA2</description>
15304 
              <bitOffset>16</bitOffset>
15305 
              <bitWidth>8</bitWidth>
15306 
            </field>
15307 
            <field>
15308 
              <name>DATA1</name>
15309 
              <description>DATA1</description>
15310 
              <bitOffset>8</bitOffset>
15311 
              <bitWidth>8</bitWidth>
15312 
            </field>
15313 
            <field>
15314 
              <name>DATA0</name>
15315 
              <description>DATA0</description>
15316 
              <bitOffset>0</bitOffset>
15317 
              <bitWidth>8</bitWidth>
15318 
            </field>
15319 
          </fields>
15320 
        </register>
15321 
        <register>
15322 
          <name>CAN_TDH2R</name>
15323 
          <displayName>CAN_TDH2R</displayName>
15324 
          <description>CAN_TDH2R</description>
15325 
          <addressOffset>0x1AC</addressOffset>
15326 
          <size>0x20</size>
15327 
          <access>read-write</access>
15328 
          <resetValue>0x00000000</resetValue>
15329 
          <fields>
15330 
            <field>
15331 
              <name>DATA7</name>
15332 
              <description>DATA7</description>
15333 
              <bitOffset>24</bitOffset>
15334 
              <bitWidth>8</bitWidth>
15335 
            </field>
15336 
            <field>
15337 
              <name>DATA6</name>
15338 
              <description>DATA6</description>
15339 
              <bitOffset>16</bitOffset>
15340 
              <bitWidth>8</bitWidth>
15341 
            </field>
15342 
            <field>
15343 
              <name>DATA5</name>
15344 
              <description>DATA5</description>
15345 
              <bitOffset>8</bitOffset>
15346 
              <bitWidth>8</bitWidth>
15347 
            </field>
15348 
            <field>
15349 
              <name>DATA4</name>
15350 
              <description>DATA4</description>
15351 
              <bitOffset>0</bitOffset>
15352 
              <bitWidth>8</bitWidth>
15353 
            </field>
15354 
          </fields>
15355 
        </register>
15356 
        <register>
15357 
          <name>CAN_RI0R</name>
15358 
          <displayName>CAN_RI0R</displayName>
15359 
          <description>CAN_RI0R</description>
15360 
          <addressOffset>0x1B0</addressOffset>
15361 
          <size>0x20</size>
15362 
          <access>read-only</access>
15363 
          <resetValue>0x00000000</resetValue>
15364 
          <fields>
15365 
            <field>
15366 
              <name>STID</name>
15367 
              <description>STID</description>
15368 
              <bitOffset>21</bitOffset>
15369 
              <bitWidth>11</bitWidth>
15370 
            </field>
15371 
            <field>
15372 
              <name>EXID</name>
15373 
              <description>EXID</description>
15374 
              <bitOffset>3</bitOffset>
15375 
              <bitWidth>18</bitWidth>
15376 
            </field>
15377 
            <field>
15378 
              <name>IDE</name>
15379 
              <description>IDE</description>
15380 
              <bitOffset>2</bitOffset>
15381 
              <bitWidth>1</bitWidth>
15382 
            </field>
15383 
            <field>
15384 
              <name>RTR</name>
15385 
              <description>RTR</description>
15386 
              <bitOffset>1</bitOffset>
15387 
              <bitWidth>1</bitWidth>
15388 
            </field>
15389 
          </fields>
15390 
        </register>
15391 
        <register>
15392 
          <name>CAN_RDT0R</name>
15393 
          <displayName>CAN_RDT0R</displayName>
15394 
          <description>CAN_RDT0R</description>
15395 
          <addressOffset>0x1B4</addressOffset>
15396 
          <size>0x20</size>
15397 
          <access>read-only</access>
15398 
          <resetValue>0x00000000</resetValue>
15399 
          <fields>
15400 
            <field>
15401 
              <name>TIME</name>
15402 
              <description>TIME</description>
15403 
              <bitOffset>16</bitOffset>
15404 
              <bitWidth>16</bitWidth>
15405 
            </field>
15406 
            <field>
15407 
              <name>FMI</name>
15408 
              <description>FMI</description>
15409 
              <bitOffset>8</bitOffset>
15410 
              <bitWidth>8</bitWidth>
15411 
            </field>
15412 
            <field>
15413 
              <name>DLC</name>
15414 
              <description>DLC</description>
15415 
              <bitOffset>0</bitOffset>
15416 
              <bitWidth>4</bitWidth>
15417 
            </field>
15418 
          </fields>
15419 
        </register>
15420 
        <register>
15421 
          <name>CAN_RDL0R</name>
15422 
          <displayName>CAN_RDL0R</displayName>
15423 
          <description>CAN_RDL0R</description>
15424 
          <addressOffset>0x1B8</addressOffset>
15425 
          <size>0x20</size>
15426 
          <access>read-only</access>
15427 
          <resetValue>0x00000000</resetValue>
15428 
          <fields>
15429 
            <field>
15430 
              <name>DATA3</name>
15431 
              <description>DATA3</description>
15432 
              <bitOffset>24</bitOffset>
15433 
              <bitWidth>8</bitWidth>
15434 
            </field>
15435 
            <field>
15436 
              <name>DATA2</name>
15437 
              <description>DATA2</description>
15438 
              <bitOffset>16</bitOffset>
15439 
              <bitWidth>8</bitWidth>
15440 
            </field>
15441 
            <field>
15442 
              <name>DATA1</name>
15443 
              <description>DATA1</description>
15444 
              <bitOffset>8</bitOffset>
15445 
              <bitWidth>8</bitWidth>
15446 
            </field>
15447 
            <field>
15448 
              <name>DATA0</name>
15449 
              <description>DATA0</description>
15450 
              <bitOffset>0</bitOffset>
15451 
              <bitWidth>8</bitWidth>
15452 
            </field>
15453 
          </fields>
15454 
        </register>
15455 
        <register>
15456 
          <name>CAN_RDH0R</name>
15457 
          <displayName>CAN_RDH0R</displayName>
15458 
          <description>CAN_RDH0R</description>
15459 
          <addressOffset>0x1BC</addressOffset>
15460 
          <size>0x20</size>
15461 
          <access>read-only</access>
15462 
          <resetValue>0x00000000</resetValue>
15463 
          <fields>
15464 
            <field>
15465 
              <name>DATA7</name>
15466 
              <description>DATA7</description>
15467 
              <bitOffset>24</bitOffset>
15468 
              <bitWidth>8</bitWidth>
15469 
            </field>
15470 
            <field>
15471 
              <name>DATA6</name>
15472 
              <description>DATA6</description>
15473 
              <bitOffset>16</bitOffset>
15474 
              <bitWidth>8</bitWidth>
15475 
            </field>
15476 
            <field>
15477 
              <name>DATA5</name>
15478 
              <description>DATA5</description>
15479 
              <bitOffset>8</bitOffset>
15480 
              <bitWidth>8</bitWidth>
15481 
            </field>
15482 
            <field>
15483 
              <name>DATA4</name>
15484 
              <description>DATA4</description>
15485 
              <bitOffset>0</bitOffset>
15486 
              <bitWidth>8</bitWidth>
15487 
            </field>
15488 
          </fields>
15489 
        </register>
15490 
        <register>
15491 
          <name>CAN_RI1R</name>
15492 
          <displayName>CAN_RI1R</displayName>
15493 
          <description>CAN_RI1R</description>
15494 
          <addressOffset>0x1C0</addressOffset>
15495 
          <size>0x20</size>
15496 
          <access>read-only</access>
15497 
          <resetValue>0x00000000</resetValue>
15498 
          <fields>
15499 
            <field>
15500 
              <name>STID</name>
15501 
              <description>STID</description>
15502 
              <bitOffset>21</bitOffset>
15503 
              <bitWidth>11</bitWidth>
15504 
            </field>
15505 
            <field>
15506 
              <name>EXID</name>
15507 
              <description>EXID</description>
15508 
              <bitOffset>3</bitOffset>
15509 
              <bitWidth>18</bitWidth>
15510 
            </field>
15511 
            <field>
15512 
              <name>IDE</name>
15513 
              <description>IDE</description>
15514 
              <bitOffset>2</bitOffset>
15515 
              <bitWidth>1</bitWidth>
15516 
            </field>
15517 
            <field>
15518 
              <name>RTR</name>
15519 
              <description>RTR</description>
15520 
              <bitOffset>1</bitOffset>
15521 
              <bitWidth>1</bitWidth>
15522 
            </field>
15523 
          </fields>
15524 
        </register>
15525 
        <register>
15526 
          <name>CAN_RDT1R</name>
15527 
          <displayName>CAN_RDT1R</displayName>
15528 
          <description>CAN_RDT1R</description>
15529 
          <addressOffset>0x1C4</addressOffset>
15530 
          <size>0x20</size>
15531 
          <access>read-only</access>
15532 
          <resetValue>0x00000000</resetValue>
15533 
          <fields>
15534 
            <field>
15535 
              <name>TIME</name>
15536 
              <description>TIME</description>
15537 
              <bitOffset>16</bitOffset>
15538 
              <bitWidth>16</bitWidth>
15539 
            </field>
15540 
            <field>
15541 
              <name>FMI</name>
15542 
              <description>FMI</description>
15543 
              <bitOffset>8</bitOffset>
15544 
              <bitWidth>8</bitWidth>
15545 
            </field>
15546 
            <field>
15547 
              <name>DLC</name>
15548 
              <description>DLC</description>
15549 
              <bitOffset>0</bitOffset>
15550 
              <bitWidth>4</bitWidth>
15551 
            </field>
15552 
          </fields>
15553 
        </register>
15554 
        <register>
15555 
          <name>CAN_RDL1R</name>
15556 
          <displayName>CAN_RDL1R</displayName>
15557 
          <description>CAN_RDL1R</description>
15558 
          <addressOffset>0x1C8</addressOffset>
15559 
          <size>0x20</size>
15560 
          <access>read-only</access>
15561 
          <resetValue>0x00000000</resetValue>
15562 
          <fields>
15563 
            <field>
15564 
              <name>DATA3</name>
15565 
              <description>DATA3</description>
15566 
              <bitOffset>24</bitOffset>
15567 
              <bitWidth>8</bitWidth>
15568 
            </field>
15569 
            <field>
15570 
              <name>DATA2</name>
15571 
              <description>DATA2</description>
15572 
              <bitOffset>16</bitOffset>
15573 
              <bitWidth>8</bitWidth>
15574 
            </field>
15575 
            <field>
15576 
              <name>DATA1</name>
15577 
              <description>DATA1</description>
15578 
              <bitOffset>8</bitOffset>
15579 
              <bitWidth>8</bitWidth>
15580 
            </field>
15581 
            <field>
15582 
              <name>DATA0</name>
15583 
              <description>DATA0</description>
15584 
              <bitOffset>0</bitOffset>
15585 
              <bitWidth>8</bitWidth>
15586 
            </field>
15587 
          </fields>
15588 
        </register>
15589 
        <register>
15590 
          <name>CAN_RDH1R</name>
15591 
          <displayName>CAN_RDH1R</displayName>
15592 
          <description>CAN_RDH1R</description>
15593 
          <addressOffset>0x1CC</addressOffset>
15594 
          <size>0x20</size>
15595 
          <access>read-only</access>
15596 
          <resetValue>0x00000000</resetValue>
15597 
          <fields>
15598 
            <field>
15599 
              <name>DATA7</name>
15600 
              <description>DATA7</description>
15601 
              <bitOffset>24</bitOffset>
15602 
              <bitWidth>8</bitWidth>
15603 
            </field>
15604 
            <field>
15605 
              <name>DATA6</name>
15606 
              <description>DATA6</description>
15607 
              <bitOffset>16</bitOffset>
15608 
              <bitWidth>8</bitWidth>
15609 
            </field>
15610 
            <field>
15611 
              <name>DATA5</name>
15612 
              <description>DATA5</description>
15613 
              <bitOffset>8</bitOffset>
15614 
              <bitWidth>8</bitWidth>
15615 
            </field>
15616 
            <field>
15617 
              <name>DATA4</name>
15618 
              <description>DATA4</description>
15619 
              <bitOffset>0</bitOffset>
15620 
              <bitWidth>8</bitWidth>
15621 
            </field>
15622 
          </fields>
15623 
        </register>
15624 
        <register>
15625 
          <name>CAN_FMR</name>
15626 
          <displayName>CAN_FMR</displayName>
15627 
          <description>CAN_FMR</description>
15628 
          <addressOffset>0x200</addressOffset>
15629 
          <size>0x20</size>
15630 
          <access>read-write</access>
15631 
          <resetValue>0x00000000</resetValue>
15632 
          <fields>
15633 
            <field>
15634 
              <name>FINIT</name>
15635 
              <description>FINIT</description>
15636 
              <bitOffset>0</bitOffset>
15637 
              <bitWidth>1</bitWidth>
15638 
            </field>
15639 
          </fields>
15640 
        </register>
15641 
        <register>
15642 
          <name>CAN_FM1R</name>
15643 
          <displayName>CAN_FM1R</displayName>
15644 
          <description>CAN_FM1R</description>
15645 
          <addressOffset>0x204</addressOffset>
15646 
          <size>0x20</size>
15647 
          <access>read-write</access>
15648 
          <resetValue>0x00000000</resetValue>
15649 
          <fields>
15650 
            <field>
15651 
              <name>FBM0</name>
15652 
              <description>Filter mode</description>
15653 
              <bitOffset>0</bitOffset>
15654 
              <bitWidth>1</bitWidth>
15655 
            </field>
15656 
            <field>
15657 
              <name>FBM1</name>
15658 
              <description>Filter mode</description>
15659 
              <bitOffset>1</bitOffset>
15660 
              <bitWidth>1</bitWidth>
15661 
            </field>
15662 
            <field>
15663 
              <name>FBM2</name>
15664 
              <description>Filter mode</description>
15665 
              <bitOffset>2</bitOffset>
15666 
              <bitWidth>1</bitWidth>
15667 
            </field>
15668 
            <field>
15669 
              <name>FBM3</name>
15670 
              <description>Filter mode</description>
15671 
              <bitOffset>3</bitOffset>
15672 
              <bitWidth>1</bitWidth>
15673 
            </field>
15674 
            <field>
15675 
              <name>FBM4</name>
15676 
              <description>Filter mode</description>
15677 
              <bitOffset>4</bitOffset>
15678 
              <bitWidth>1</bitWidth>
15679 
            </field>
15680 
            <field>
15681 
              <name>FBM5</name>
15682 
              <description>Filter mode</description>
15683 
              <bitOffset>5</bitOffset>
15684 
              <bitWidth>1</bitWidth>
15685 
            </field>
15686 
            <field>
15687 
              <name>FBM6</name>
15688 
              <description>Filter mode</description>
15689 
              <bitOffset>6</bitOffset>
15690 
              <bitWidth>1</bitWidth>
15691 
            </field>
15692 
            <field>
15693 
              <name>FBM7</name>
15694 
              <description>Filter mode</description>
15695 
              <bitOffset>7</bitOffset>
15696 
              <bitWidth>1</bitWidth>
15697 
            </field>
15698 
            <field>
15699 
              <name>FBM8</name>
15700 
              <description>Filter mode</description>
15701 
              <bitOffset>8</bitOffset>
15702 
              <bitWidth>1</bitWidth>
15703 
            </field>
15704 
            <field>
15705 
              <name>FBM9</name>
15706 
              <description>Filter mode</description>
15707 
              <bitOffset>9</bitOffset>
15708 
              <bitWidth>1</bitWidth>
15709 
            </field>
15710 
            <field>
15711 
              <name>FBM10</name>
15712 
              <description>Filter mode</description>
15713 
              <bitOffset>10</bitOffset>
15714 
              <bitWidth>1</bitWidth>
15715 
            </field>
15716 
            <field>
15717 
              <name>FBM11</name>
15718 
              <description>Filter mode</description>
15719 
              <bitOffset>11</bitOffset>
15720 
              <bitWidth>1</bitWidth>
15721 
            </field>
15722 
            <field>
15723 
              <name>FBM12</name>
15724 
              <description>Filter mode</description>
15725 
              <bitOffset>12</bitOffset>
15726 
              <bitWidth>1</bitWidth>
15727 
            </field>
15728 
            <field>
15729 
              <name>FBM13</name>
15730 
              <description>Filter mode</description>
15731 
              <bitOffset>13</bitOffset>
15732 
              <bitWidth>1</bitWidth>
15733 
            </field>
15734 
          </fields>
15735 
        </register>
15736 
        <register>
15737 
          <name>CAN_FS1R</name>
15738 
          <displayName>CAN_FS1R</displayName>
15739 
          <description>CAN_FS1R</description>
15740 
          <addressOffset>0x20C</addressOffset>
15741 
          <size>0x20</size>
15742 
          <access>read-write</access>
15743 
          <resetValue>0x00000000</resetValue>
15744 
          <fields>
15745 
            <field>
15746 
              <name>FSC0</name>
15747 
              <description>Filter scale configuration</description>
15748 
              <bitOffset>0</bitOffset>
15749 
              <bitWidth>1</bitWidth>
15750 
            </field>
15751 
            <field>
15752 
              <name>FSC1</name>
15753 
              <description>Filter scale configuration</description>
15754 
              <bitOffset>1</bitOffset>
15755 
              <bitWidth>1</bitWidth>
15756 
            </field>
15757 
            <field>
15758 
              <name>FSC2</name>
15759 
              <description>Filter scale configuration</description>
15760 
              <bitOffset>2</bitOffset>
15761 
              <bitWidth>1</bitWidth>
15762 
            </field>
15763 
            <field>
15764 
              <name>FSC3</name>
15765 
              <description>Filter scale configuration</description>
15766 
              <bitOffset>3</bitOffset>
15767 
              <bitWidth>1</bitWidth>
15768 
            </field>
15769 
            <field>
15770 
              <name>FSC4</name>
15771 
              <description>Filter scale configuration</description>
15772 
              <bitOffset>4</bitOffset>
15773 
              <bitWidth>1</bitWidth>
15774 
            </field>
15775 
            <field>
15776 
              <name>FSC5</name>
15777 
              <description>Filter scale configuration</description>
15778 
              <bitOffset>5</bitOffset>
15779 
              <bitWidth>1</bitWidth>
15780 
            </field>
15781 
            <field>
15782 
              <name>FSC6</name>
15783 
              <description>Filter scale configuration</description>
15784 
              <bitOffset>6</bitOffset>
15785 
              <bitWidth>1</bitWidth>
15786 
            </field>
15787 
            <field>
15788 
              <name>FSC7</name>
15789 
              <description>Filter scale configuration</description>
15790 
              <bitOffset>7</bitOffset>
15791 
              <bitWidth>1</bitWidth>
15792 
            </field>
15793 
            <field>
15794 
              <name>FSC8</name>
15795 
              <description>Filter scale configuration</description>
15796 
              <bitOffset>8</bitOffset>
15797 
              <bitWidth>1</bitWidth>
15798 
            </field>
15799 
            <field>
15800 
              <name>FSC9</name>
15801 
              <description>Filter scale configuration</description>
15802 
              <bitOffset>9</bitOffset>
15803 
              <bitWidth>1</bitWidth>
15804 
            </field>
15805 
            <field>
15806 
              <name>FSC10</name>
15807 
              <description>Filter scale configuration</description>
15808 
              <bitOffset>10</bitOffset>
15809 
              <bitWidth>1</bitWidth>
15810 
            </field>
15811 
            <field>
15812 
              <name>FSC11</name>
15813 
              <description>Filter scale configuration</description>
15814 
              <bitOffset>11</bitOffset>
15815 
              <bitWidth>1</bitWidth>
15816 
            </field>
15817 
            <field>
15818 
              <name>FSC12</name>
15819 
              <description>Filter scale configuration</description>
15820 
              <bitOffset>12</bitOffset>
15821 
              <bitWidth>1</bitWidth>
15822 
            </field>
15823 
            <field>
15824 
              <name>FSC13</name>
15825 
              <description>Filter scale configuration</description>
15826 
              <bitOffset>13</bitOffset>
15827 
              <bitWidth>1</bitWidth>
15828 
            </field>
15829 
          </fields>
15830 
        </register>
15831 
        <register>
15832 
          <name>CAN_FFA1R</name>
15833 
          <displayName>CAN_FFA1R</displayName>
15834 
          <description>CAN_FFA1R</description>
15835 
          <addressOffset>0x214</addressOffset>
15836 
          <size>0x20</size>
15837 
          <access>read-write</access>
15838 
          <resetValue>0x00000000</resetValue>
15839 
          <fields>
15840 
            <field>
15841 
              <name>FFA0</name>
15842 
              <description>Filter FIFO assignment for filter
15843 
              0</description>
15844 
              <bitOffset>0</bitOffset>
15845 
              <bitWidth>1</bitWidth>
15846 
            </field>
15847 
            <field>
15848 
              <name>FFA1</name>
15849 
              <description>Filter FIFO assignment for filter
15850 
              1</description>
15851 
              <bitOffset>1</bitOffset>
15852 
              <bitWidth>1</bitWidth>
15853 
            </field>
15854 
            <field>
15855 
              <name>FFA2</name>
15856 
              <description>Filter FIFO assignment for filter
15857 
              2</description>
15858 
              <bitOffset>2</bitOffset>
15859 
              <bitWidth>1</bitWidth>
15860 
            </field>
15861 
            <field>
15862 
              <name>FFA3</name>
15863 
              <description>Filter FIFO assignment for filter
15864 
              3</description>
15865 
              <bitOffset>3</bitOffset>
15866 
              <bitWidth>1</bitWidth>
15867 
            </field>
15868 
            <field>
15869 
              <name>FFA4</name>
15870 
              <description>Filter FIFO assignment for filter
15871 
              4</description>
15872 
              <bitOffset>4</bitOffset>
15873 
              <bitWidth>1</bitWidth>
15874 
            </field>
15875 
            <field>
15876 
              <name>FFA5</name>
15877 
              <description>Filter FIFO assignment for filter
15878 
              5</description>
15879 
              <bitOffset>5</bitOffset>
15880 
              <bitWidth>1</bitWidth>
15881 
            </field>
15882 
            <field>
15883 
              <name>FFA6</name>
15884 
              <description>Filter FIFO assignment for filter
15885 
              6</description>
15886 
              <bitOffset>6</bitOffset>
15887 
              <bitWidth>1</bitWidth>
15888 
            </field>
15889 
            <field>
15890 
              <name>FFA7</name>
15891 
              <description>Filter FIFO assignment for filter
15892 
              7</description>
15893 
              <bitOffset>7</bitOffset>
15894 
              <bitWidth>1</bitWidth>
15895 
            </field>
15896 
            <field>
15897 
              <name>FFA8</name>
15898 
              <description>Filter FIFO assignment for filter
15899 
              8</description>
15900 
              <bitOffset>8</bitOffset>
15901 
              <bitWidth>1</bitWidth>
15902 
            </field>
15903 
            <field>
15904 
              <name>FFA9</name>
15905 
              <description>Filter FIFO assignment for filter
15906 
              9</description>
15907 
              <bitOffset>9</bitOffset>
15908 
              <bitWidth>1</bitWidth>
15909 
            </field>
15910 
            <field>
15911 
              <name>FFA10</name>
15912 
              <description>Filter FIFO assignment for filter
15913 
              10</description>
15914 
              <bitOffset>10</bitOffset>
15915 
              <bitWidth>1</bitWidth>
15916 
            </field>
15917 
            <field>
15918 
              <name>FFA11</name>
15919 
              <description>Filter FIFO assignment for filter
15920 
              11</description>
15921 
              <bitOffset>11</bitOffset>
15922 
              <bitWidth>1</bitWidth>
15923 
            </field>
15924 
            <field>
15925 
              <name>FFA12</name>
15926 
              <description>Filter FIFO assignment for filter
15927 
              12</description>
15928 
              <bitOffset>12</bitOffset>
15929 
              <bitWidth>1</bitWidth>
15930 
            </field>
15931 
            <field>
15932 
              <name>FFA13</name>
15933 
              <description>Filter FIFO assignment for filter
15934 
              13</description>
15935 
              <bitOffset>13</bitOffset>
15936 
              <bitWidth>1</bitWidth>
15937 
            </field>
15938 
          </fields>
15939 
        </register>
15940 
        <register>
15941 
          <name>CAN_FA1R</name>
15942 
          <displayName>CAN_FA1R</displayName>
15943 
          <description>CAN_FA1R</description>
15944 
          <addressOffset>0x21C</addressOffset>
15945 
          <size>0x20</size>
15946 
          <access>read-write</access>
15947 
          <resetValue>0x00000000</resetValue>
15948 
          <fields>
15949 
            <field>
15950 
              <name>FACT0</name>
15951 
              <description>Filter active</description>
15952 
              <bitOffset>0</bitOffset>
15953 
              <bitWidth>1</bitWidth>
15954 
            </field>
15955 
            <field>
15956 
              <name>FACT1</name>
15957 
              <description>Filter active</description>
15958 
              <bitOffset>1</bitOffset>
15959 
              <bitWidth>1</bitWidth>
15960 
            </field>
15961 
            <field>
15962 
              <name>FACT2</name>
15963 
              <description>Filter active</description>
15964 
              <bitOffset>2</bitOffset>
15965 
              <bitWidth>1</bitWidth>
15966 
            </field>
15967 
            <field>
15968 
              <name>FACT3</name>
15969 
              <description>Filter active</description>
15970 
              <bitOffset>3</bitOffset>
15971 
              <bitWidth>1</bitWidth>
15972 
            </field>
15973 
            <field>
15974 
              <name>FACT4</name>
15975 
              <description>Filter active</description>
15976 
              <bitOffset>4</bitOffset>
15977 
              <bitWidth>1</bitWidth>
15978 
            </field>
15979 
            <field>
15980 
              <name>FACT5</name>
15981 
              <description>Filter active</description>
15982 
              <bitOffset>5</bitOffset>
15983 
              <bitWidth>1</bitWidth>
15984 
            </field>
15985 
            <field>
15986 
              <name>FACT6</name>
15987 
              <description>Filter active</description>
15988 
              <bitOffset>6</bitOffset>
15989 
              <bitWidth>1</bitWidth>
15990 
            </field>
15991 
            <field>
15992 
              <name>FACT7</name>
15993 
              <description>Filter active</description>
15994 
              <bitOffset>7</bitOffset>
15995 
              <bitWidth>1</bitWidth>
15996 
            </field>
15997 
            <field>
15998 
              <name>FACT8</name>
15999 
              <description>Filter active</description>
16000 
              <bitOffset>8</bitOffset>
16001 
              <bitWidth>1</bitWidth>
16002 
            </field>
16003 
            <field>
16004 
              <name>FACT9</name>
16005 
              <description>Filter active</description>
16006 
              <bitOffset>9</bitOffset>
16007 
              <bitWidth>1</bitWidth>
16008 
            </field>
16009 
            <field>
16010 
              <name>FACT10</name>
16011 
              <description>Filter active</description>
16012 
              <bitOffset>10</bitOffset>
16013 
              <bitWidth>1</bitWidth>
16014 
            </field>
16015 
            <field>
16016 
              <name>FACT11</name>
16017 
              <description>Filter active</description>
16018 
              <bitOffset>11</bitOffset>
16019 
              <bitWidth>1</bitWidth>
16020 
            </field>
16021 
            <field>
16022 
              <name>FACT12</name>
16023 
              <description>Filter active</description>
16024 
              <bitOffset>12</bitOffset>
16025 
              <bitWidth>1</bitWidth>
16026 
            </field>
16027 
            <field>
16028 
              <name>FACT13</name>
16029 
              <description>Filter active</description>
16030 
              <bitOffset>13</bitOffset>
16031 
              <bitWidth>1</bitWidth>
16032 
            </field>
16033 
          </fields>
16034 
        </register>
16035 
        <register>
16036 
          <name>F0R1</name>
16037 
          <displayName>F0R1</displayName>
16038 
          <description>Filter bank 0 register 1</description>
16039 
          <addressOffset>0x240</addressOffset>
16040 
          <size>0x20</size>
16041 
          <access>read-write</access>
16042 
          <resetValue>0x00000000</resetValue>
16043 
          <fields>
16044 
            <field>
16045 
              <name>FB0</name>
16046 
              <description>Filter bits</description>
16047 
              <bitOffset>0</bitOffset>
16048 
              <bitWidth>1</bitWidth>
16049 
            </field>
16050 
            <field>
16051 
              <name>FB1</name>
16052 
              <description>Filter bits</description>
16053 
              <bitOffset>1</bitOffset>
16054 
              <bitWidth>1</bitWidth>
16055 
            </field>
16056 
            <field>
16057 
              <name>FB2</name>
16058 
              <description>Filter bits</description>
16059 
              <bitOffset>2</bitOffset>
16060 
              <bitWidth>1</bitWidth>
16061 
            </field>
16062 
            <field>
16063 
              <name>FB3</name>
16064 
              <description>Filter bits</description>
16065 
              <bitOffset>3</bitOffset>
16066 
              <bitWidth>1</bitWidth>
16067 
            </field>
16068 
            <field>
16069 
              <name>FB4</name>
16070 
              <description>Filter bits</description>
16071 
              <bitOffset>4</bitOffset>
16072 
              <bitWidth>1</bitWidth>
16073 
            </field>
16074 
            <field>
16075 
              <name>FB5</name>
16076 
              <description>Filter bits</description>
16077 
              <bitOffset>5</bitOffset>
16078 
              <bitWidth>1</bitWidth>
16079 
            </field>
16080 
            <field>
16081 
              <name>FB6</name>
16082 
              <description>Filter bits</description>
16083 
              <bitOffset>6</bitOffset>
16084 
              <bitWidth>1</bitWidth>
16085 
            </field>
16086 
            <field>
16087 
              <name>FB7</name>
16088 
              <description>Filter bits</description>
16089 
              <bitOffset>7</bitOffset>
16090 
              <bitWidth>1</bitWidth>
16091 
            </field>
16092 
            <field>
16093 
              <name>FB8</name>
16094 
              <description>Filter bits</description>
16095 
              <bitOffset>8</bitOffset>
16096 
              <bitWidth>1</bitWidth>
16097 
            </field>
16098 
            <field>
16099 
              <name>FB9</name>
16100 
              <description>Filter bits</description>
16101 
              <bitOffset>9</bitOffset>
16102 
              <bitWidth>1</bitWidth>
16103 
            </field>
16104 
            <field>
16105 
              <name>FB10</name>
16106 
              <description>Filter bits</description>
16107 
              <bitOffset>10</bitOffset>
16108 
              <bitWidth>1</bitWidth>
16109 
            </field>
16110 
            <field>
16111 
              <name>FB11</name>
16112 
              <description>Filter bits</description>
16113 
              <bitOffset>11</bitOffset>
16114 
              <bitWidth>1</bitWidth>
16115 
            </field>
16116 
            <field>
16117 
              <name>FB12</name>
16118 
              <description>Filter bits</description>
16119 
              <bitOffset>12</bitOffset>
16120 
              <bitWidth>1</bitWidth>
16121 
            </field>
16122 
            <field>
16123 
              <name>FB13</name>
16124 
              <description>Filter bits</description>
16125 
              <bitOffset>13</bitOffset>
16126 
              <bitWidth>1</bitWidth>
16127 
            </field>
16128 
            <field>
16129 
              <name>FB14</name>
16130 
              <description>Filter bits</description>
16131 
              <bitOffset>14</bitOffset>
16132 
              <bitWidth>1</bitWidth>
16133 
            </field>
16134 
            <field>
16135 
              <name>FB15</name>
16136 
              <description>Filter bits</description>
16137 
              <bitOffset>15</bitOffset>
16138 
              <bitWidth>1</bitWidth>
16139 
            </field>
16140 
            <field>
16141 
              <name>FB16</name>
16142 
              <description>Filter bits</description>
16143 
              <bitOffset>16</bitOffset>
16144 
              <bitWidth>1</bitWidth>
16145 
            </field>
16146 
            <field>
16147 
              <name>FB17</name>
16148 
              <description>Filter bits</description>
16149 
              <bitOffset>17</bitOffset>
16150 
              <bitWidth>1</bitWidth>
16151 
            </field>
16152 
            <field>
16153 
              <name>FB18</name>
16154 
              <description>Filter bits</description>
16155 
              <bitOffset>18</bitOffset>
16156 
              <bitWidth>1</bitWidth>
16157 
            </field>
16158 
            <field>
16159 
              <name>FB19</name>
16160 
              <description>Filter bits</description>
16161 
              <bitOffset>19</bitOffset>
16162 
              <bitWidth>1</bitWidth>
16163 
            </field>
16164 
            <field>
16165 
              <name>FB20</name>
16166 
              <description>Filter bits</description>
16167 
              <bitOffset>20</bitOffset>
16168 
              <bitWidth>1</bitWidth>
16169 
            </field>
16170 
            <field>
16171 
              <name>FB21</name>
16172 
              <description>Filter bits</description>
16173 
              <bitOffset>21</bitOffset>
16174 
              <bitWidth>1</bitWidth>
16175 
            </field>
16176 
            <field>
16177 
              <name>FB22</name>
16178 
              <description>Filter bits</description>
16179 
              <bitOffset>22</bitOffset>
16180 
              <bitWidth>1</bitWidth>
16181 
            </field>
16182 
            <field>
16183 
              <name>FB23</name>
16184 
              <description>Filter bits</description>
16185 
              <bitOffset>23</bitOffset>
16186 
              <bitWidth>1</bitWidth>
16187 
            </field>
16188 
            <field>
16189 
              <name>FB24</name>
16190 
              <description>Filter bits</description>
16191 
              <bitOffset>24</bitOffset>
16192 
              <bitWidth>1</bitWidth>
16193 
            </field>
16194 
            <field>
16195 
              <name>FB25</name>
16196 
              <description>Filter bits</description>
16197 
              <bitOffset>25</bitOffset>
16198 
              <bitWidth>1</bitWidth>
16199 
            </field>
16200 
            <field>
16201 
              <name>FB26</name>
16202 
              <description>Filter bits</description>
16203 
              <bitOffset>26</bitOffset>
16204 
              <bitWidth>1</bitWidth>
16205 
            </field>
16206 
            <field>
16207 
              <name>FB27</name>
16208 
              <description>Filter bits</description>
16209 
              <bitOffset>27</bitOffset>
16210 
              <bitWidth>1</bitWidth>
16211 
            </field>
16212 
            <field>
16213 
              <name>FB28</name>
16214 
              <description>Filter bits</description>
16215 
              <bitOffset>28</bitOffset>
16216 
              <bitWidth>1</bitWidth>
16217 
            </field>
16218 
            <field>
16219 
              <name>FB29</name>
16220 
              <description>Filter bits</description>
16221 
              <bitOffset>29</bitOffset>
16222 
              <bitWidth>1</bitWidth>
16223 
            </field>
16224 
            <field>
16225 
              <name>FB30</name>
16226 
              <description>Filter bits</description>
16227 
              <bitOffset>30</bitOffset>
16228 
              <bitWidth>1</bitWidth>
16229 
            </field>
16230 
            <field>
16231 
              <name>FB31</name>
16232 
              <description>Filter bits</description>
16233 
              <bitOffset>31</bitOffset>
16234 
              <bitWidth>1</bitWidth>
16235 
            </field>
16236 
          </fields>
16237 
        </register>
16238 
        <register>
16239 
          <name>F0R2</name>
16240 
          <displayName>F0R2</displayName>
16241 
          <description>Filter bank 0 register 2</description>
16242 
          <addressOffset>0x244</addressOffset>
16243 
          <size>0x20</size>
16244 
          <access>read-write</access>
16245 
          <resetValue>0x00000000</resetValue>
16246 
          <fields>
16247 
            <field>
16248 
              <name>FB0</name>
16249 
              <description>Filter bits</description>
16250 
              <bitOffset>0</bitOffset>
16251 
              <bitWidth>1</bitWidth>
16252 
            </field>
16253 
            <field>
16254 
              <name>FB1</name>
16255 
              <description>Filter bits</description>
16256 
              <bitOffset>1</bitOffset>
16257 
              <bitWidth>1</bitWidth>
16258 
            </field>
16259 
            <field>
16260 
              <name>FB2</name>
16261 
              <description>Filter bits</description>
16262 
              <bitOffset>2</bitOffset>
16263 
              <bitWidth>1</bitWidth>
16264 
            </field>
16265 
            <field>
16266 
              <name>FB3</name>
16267 
              <description>Filter bits</description>
16268 
              <bitOffset>3</bitOffset>
16269 
              <bitWidth>1</bitWidth>
16270 
            </field>
16271 
            <field>
16272 
              <name>FB4</name>
16273 
              <description>Filter bits</description>
16274 
              <bitOffset>4</bitOffset>
16275 
              <bitWidth>1</bitWidth>
16276 
            </field>
16277 
            <field>
16278 
              <name>FB5</name>
16279 
              <description>Filter bits</description>
16280 
              <bitOffset>5</bitOffset>
16281 
              <bitWidth>1</bitWidth>
16282 
            </field>
16283 
            <field>
16284 
              <name>FB6</name>
16285 
              <description>Filter bits</description>
16286 
              <bitOffset>6</bitOffset>
16287 
              <bitWidth>1</bitWidth>
16288 
            </field>
16289 
            <field>
16290 
              <name>FB7</name>
16291 
              <description>Filter bits</description>
16292 
              <bitOffset>7</bitOffset>
16293 
              <bitWidth>1</bitWidth>
16294 
            </field>
16295 
            <field>
16296 
              <name>FB8</name>
16297 
              <description>Filter bits</description>
16298 
              <bitOffset>8</bitOffset>
16299 
              <bitWidth>1</bitWidth>
16300 
            </field>
16301 
            <field>
16302 
              <name>FB9</name>
16303 
              <description>Filter bits</description>
16304 
              <bitOffset>9</bitOffset>
16305 
              <bitWidth>1</bitWidth>
16306 
            </field>
16307 
            <field>
16308 
              <name>FB10</name>
16309 
              <description>Filter bits</description>
16310 
              <bitOffset>10</bitOffset>
16311 
              <bitWidth>1</bitWidth>
16312 
            </field>
16313 
            <field>
16314 
              <name>FB11</name>
16315 
              <description>Filter bits</description>
16316 
              <bitOffset>11</bitOffset>
16317 
              <bitWidth>1</bitWidth>
16318 
            </field>
16319 
            <field>
16320 
              <name>FB12</name>
16321 
              <description>Filter bits</description>
16322 
              <bitOffset>12</bitOffset>
16323 
              <bitWidth>1</bitWidth>
16324 
            </field>
16325 
            <field>
16326 
              <name>FB13</name>
16327 
              <description>Filter bits</description>
16328 
              <bitOffset>13</bitOffset>
16329 
              <bitWidth>1</bitWidth>
16330 
            </field>
16331 
            <field>
16332 
              <name>FB14</name>
16333 
              <description>Filter bits</description>
16334 
              <bitOffset>14</bitOffset>
16335 
              <bitWidth>1</bitWidth>
16336 
            </field>
16337 
            <field>
16338 
              <name>FB15</name>
16339 
              <description>Filter bits</description>
16340 
              <bitOffset>15</bitOffset>
16341 
              <bitWidth>1</bitWidth>
16342 
            </field>
16343 
            <field>
16344 
              <name>FB16</name>
16345 
              <description>Filter bits</description>
16346 
              <bitOffset>16</bitOffset>
16347 
              <bitWidth>1</bitWidth>
16348 
            </field>
16349 
            <field>
16350 
              <name>FB17</name>
16351 
              <description>Filter bits</description>
16352 
              <bitOffset>17</bitOffset>
16353 
              <bitWidth>1</bitWidth>
16354 
            </field>
16355 
            <field>
16356 
              <name>FB18</name>
16357 
              <description>Filter bits</description>
16358 
              <bitOffset>18</bitOffset>
16359 
              <bitWidth>1</bitWidth>
16360 
            </field>
16361 
            <field>
16362 
              <name>FB19</name>
16363 
              <description>Filter bits</description>
16364 
              <bitOffset>19</bitOffset>
16365 
              <bitWidth>1</bitWidth>
16366 
            </field>
16367 
            <field>
16368 
              <name>FB20</name>
16369 
              <description>Filter bits</description>
16370 
              <bitOffset>20</bitOffset>
16371 
              <bitWidth>1</bitWidth>
16372 
            </field>
16373 
            <field>
16374 
              <name>FB21</name>
16375 
              <description>Filter bits</description>
16376 
              <bitOffset>21</bitOffset>
16377 
              <bitWidth>1</bitWidth>
16378 
            </field>
16379 
            <field>
16380 
              <name>FB22</name>
16381 
              <description>Filter bits</description>
16382 
              <bitOffset>22</bitOffset>
16383 
              <bitWidth>1</bitWidth>
16384 
            </field>
16385 
            <field>
16386 
              <name>FB23</name>
16387 
              <description>Filter bits</description>
16388 
              <bitOffset>23</bitOffset>
16389 
              <bitWidth>1</bitWidth>
16390 
            </field>
16391 
            <field>
16392 
              <name>FB24</name>
16393 
              <description>Filter bits</description>
16394 
              <bitOffset>24</bitOffset>
16395 
              <bitWidth>1</bitWidth>
16396 
            </field>
16397 
            <field>
16398 
              <name>FB25</name>
16399 
              <description>Filter bits</description>
16400 
              <bitOffset>25</bitOffset>
16401 
              <bitWidth>1</bitWidth>
16402 
            </field>
16403 
            <field>
16404 
              <name>FB26</name>
16405 
              <description>Filter bits</description>
16406 
              <bitOffset>26</bitOffset>
16407 
              <bitWidth>1</bitWidth>
16408 
            </field>
16409 
            <field>
16410 
              <name>FB27</name>
16411 
              <description>Filter bits</description>
16412 
              <bitOffset>27</bitOffset>
16413 
              <bitWidth>1</bitWidth>
16414 
            </field>
16415 
            <field>
16416 
              <name>FB28</name>
16417 
              <description>Filter bits</description>
16418 
              <bitOffset>28</bitOffset>
16419 
              <bitWidth>1</bitWidth>
16420 
            </field>
16421 
            <field>
16422 
              <name>FB29</name>
16423 
              <description>Filter bits</description>
16424 
              <bitOffset>29</bitOffset>
16425 
              <bitWidth>1</bitWidth>
16426 
            </field>
16427 
            <field>
16428 
              <name>FB30</name>
16429 
              <description>Filter bits</description>
16430 
              <bitOffset>30</bitOffset>
16431 
              <bitWidth>1</bitWidth>
16432 
            </field>
16433 
            <field>
16434 
              <name>FB31</name>
16435 
              <description>Filter bits</description>
16436 
              <bitOffset>31</bitOffset>
16437 
              <bitWidth>1</bitWidth>
16438 
            </field>
16439 
          </fields>
16440 
        </register>
16441 
        <register>
16442 
          <name>F1R1</name>
16443 
          <displayName>F1R1</displayName>
16444 
          <description>Filter bank 1 register 1</description>
16445 
          <addressOffset>0x248</addressOffset>
16446 
          <size>0x20</size>
16447 
          <access>read-write</access>
16448 
          <resetValue>0x00000000</resetValue>
16449 
          <fields>
16450 
            <field>
16451 
              <name>FB0</name>
16452 
              <description>Filter bits</description>
16453 
              <bitOffset>0</bitOffset>
16454 
              <bitWidth>1</bitWidth>
16455 
            </field>
16456 
            <field>
16457 
              <name>FB1</name>
16458 
              <description>Filter bits</description>
16459 
              <bitOffset>1</bitOffset>
16460 
              <bitWidth>1</bitWidth>
16461 
            </field>
16462 
            <field>
16463 
              <name>FB2</name>
16464 
              <description>Filter bits</description>
16465 
              <bitOffset>2</bitOffset>
16466 
              <bitWidth>1</bitWidth>
16467 
            </field>
16468 
            <field>
16469 
              <name>FB3</name>
16470 
              <description>Filter bits</description>
16471 
              <bitOffset>3</bitOffset>
16472 
              <bitWidth>1</bitWidth>
16473 
            </field>
16474 
            <field>
16475 
              <name>FB4</name>
16476 
              <description>Filter bits</description>
16477 
              <bitOffset>4</bitOffset>
16478 
              <bitWidth>1</bitWidth>
16479 
            </field>
16480 
            <field>
16481 
              <name>FB5</name>
16482 
              <description>Filter bits</description>
16483 
              <bitOffset>5</bitOffset>
16484 
              <bitWidth>1</bitWidth>
16485 
            </field>
16486 
            <field>
16487 
              <name>FB6</name>
16488 
              <description>Filter bits</description>
16489 
              <bitOffset>6</bitOffset>
16490 
              <bitWidth>1</bitWidth>
16491 
            </field>
16492 
            <field>
16493 
              <name>FB7</name>
16494 
              <description>Filter bits</description>
16495 
              <bitOffset>7</bitOffset>
16496 
              <bitWidth>1</bitWidth>
16497 
            </field>
16498 
            <field>
16499 
              <name>FB8</name>
16500 
              <description>Filter bits</description>
16501 
              <bitOffset>8</bitOffset>
16502 
              <bitWidth>1</bitWidth>
16503 
            </field>
16504 
            <field>
16505 
              <name>FB9</name>
16506 
              <description>Filter bits</description>
16507 
              <bitOffset>9</bitOffset>
16508 
              <bitWidth>1</bitWidth>
16509 
            </field>
16510 
            <field>
16511 
              <name>FB10</name>
16512 
              <description>Filter bits</description>
16513 
              <bitOffset>10</bitOffset>
16514 
              <bitWidth>1</bitWidth>
16515 
            </field>
16516 
            <field>
16517 
              <name>FB11</name>
16518 
              <description>Filter bits</description>
16519 
              <bitOffset>11</bitOffset>
16520 
              <bitWidth>1</bitWidth>
16521 
            </field>
16522 
            <field>
16523 
              <name>FB12</name>
16524 
              <description>Filter bits</description>
16525 
              <bitOffset>12</bitOffset>
16526 
              <bitWidth>1</bitWidth>
16527 
            </field>
16528 
            <field>
16529 
              <name>FB13</name>
16530 
              <description>Filter bits</description>
16531 
              <bitOffset>13</bitOffset>
16532 
              <bitWidth>1</bitWidth>
16533 
            </field>
16534 
            <field>
16535 
              <name>FB14</name>
16536 
              <description>Filter bits</description>
16537 
              <bitOffset>14</bitOffset>
16538 
              <bitWidth>1</bitWidth>
16539 
            </field>
16540 
            <field>
16541 
              <name>FB15</name>
16542 
              <description>Filter bits</description>
16543 
              <bitOffset>15</bitOffset>
16544 
              <bitWidth>1</bitWidth>
16545 
            </field>
16546 
            <field>
16547 
              <name>FB16</name>
16548 
              <description>Filter bits</description>
16549 
              <bitOffset>16</bitOffset>
16550 
              <bitWidth>1</bitWidth>
16551 
            </field>
16552 
            <field>
16553 
              <name>FB17</name>
16554 
              <description>Filter bits</description>
16555 
              <bitOffset>17</bitOffset>
16556 
              <bitWidth>1</bitWidth>
16557 
            </field>
16558 
            <field>
16559 
              <name>FB18</name>
16560 
              <description>Filter bits</description>
16561 
              <bitOffset>18</bitOffset>
16562 
              <bitWidth>1</bitWidth>
16563 
            </field>
16564 
            <field>
16565 
              <name>FB19</name>
16566 
              <description>Filter bits</description>
16567 
              <bitOffset>19</bitOffset>
16568 
              <bitWidth>1</bitWidth>
16569 
            </field>
16570 
            <field>
16571 
              <name>FB20</name>
16572 
              <description>Filter bits</description>
16573 
              <bitOffset>20</bitOffset>
16574 
              <bitWidth>1</bitWidth>
16575 
            </field>
16576 
            <field>
16577 
              <name>FB21</name>
16578 
              <description>Filter bits</description>
16579 
              <bitOffset>21</bitOffset>
16580 
              <bitWidth>1</bitWidth>
16581 
            </field>
16582 
            <field>
16583 
              <name>FB22</name>
16584 
              <description>Filter bits</description>
16585 
              <bitOffset>22</bitOffset>
16586 
              <bitWidth>1</bitWidth>
16587 
            </field>
16588 
            <field>
16589 
              <name>FB23</name>
16590 
              <description>Filter bits</description>
16591 
              <bitOffset>23</bitOffset>
16592 
              <bitWidth>1</bitWidth>
16593 
            </field>
16594 
            <field>
16595 
              <name>FB24</name>
16596 
              <description>Filter bits</description>
16597 
              <bitOffset>24</bitOffset>
16598 
              <bitWidth>1</bitWidth>
16599 
            </field>
16600 
            <field>
16601 
              <name>FB25</name>
16602 
              <description>Filter bits</description>
16603 
              <bitOffset>25</bitOffset>
16604 
              <bitWidth>1</bitWidth>
16605 
            </field>
16606 
            <field>
16607 
              <name>FB26</name>
16608 
              <description>Filter bits</description>
16609 
              <bitOffset>26</bitOffset>
16610 
              <bitWidth>1</bitWidth>
16611 
            </field>
16612 
            <field>
16613 
              <name>FB27</name>
16614 
              <description>Filter bits</description>
16615 
              <bitOffset>27</bitOffset>
16616 
              <bitWidth>1</bitWidth>
16617 
            </field>
16618 
            <field>
16619 
              <name>FB28</name>
16620 
              <description>Filter bits</description>
16621 
              <bitOffset>28</bitOffset>
16622 
              <bitWidth>1</bitWidth>
16623 
            </field>
16624 
            <field>
16625 
              <name>FB29</name>
16626 
              <description>Filter bits</description>
16627 
              <bitOffset>29</bitOffset>
16628 
              <bitWidth>1</bitWidth>
16629 
            </field>
16630 
            <field>
16631 
              <name>FB30</name>
16632 
              <description>Filter bits</description>
16633 
              <bitOffset>30</bitOffset>
16634 
              <bitWidth>1</bitWidth>
16635 
            </field>
16636 
            <field>
16637 
              <name>FB31</name>
16638 
              <description>Filter bits</description>
16639 
              <bitOffset>31</bitOffset>
16640 
              <bitWidth>1</bitWidth>
16641 
            </field>
16642 
          </fields>
16643 
        </register>
16644 
        <register>
16645 
          <name>F1R2</name>
16646 
          <displayName>F1R2</displayName>
16647 
          <description>Filter bank 1 register 2</description>
16648 
          <addressOffset>0x24C</addressOffset>
16649 
          <size>0x20</size>
16650 
          <access>read-write</access>
16651 
          <resetValue>0x00000000</resetValue>
16652 
          <fields>
16653 
            <field>
16654 
              <name>FB0</name>
16655 
              <description>Filter bits</description>
16656 
              <bitOffset>0</bitOffset>
16657 
              <bitWidth>1</bitWidth>
16658 
            </field>
16659 
            <field>
16660 
              <name>FB1</name>
16661 
              <description>Filter bits</description>
16662 
              <bitOffset>1</bitOffset>
16663 
              <bitWidth>1</bitWidth>
16664 
            </field>
16665 
            <field>
16666 
              <name>FB2</name>
16667 
              <description>Filter bits</description>
16668 
              <bitOffset>2</bitOffset>
16669 
              <bitWidth>1</bitWidth>
16670 
            </field>
16671 
            <field>
16672 
              <name>FB3</name>
16673 
              <description>Filter bits</description>
16674 
              <bitOffset>3</bitOffset>
16675 
              <bitWidth>1</bitWidth>
16676 
            </field>
16677 
            <field>
16678 
              <name>FB4</name>
16679 
              <description>Filter bits</description>
16680 
              <bitOffset>4</bitOffset>
16681 
              <bitWidth>1</bitWidth>
16682 
            </field>
16683 
            <field>
16684 
              <name>FB5</name>
16685 
              <description>Filter bits</description>
16686 
              <bitOffset>5</bitOffset>
16687 
              <bitWidth>1</bitWidth>
16688 
            </field>
16689 
            <field>
16690 
              <name>FB6</name>
16691 
              <description>Filter bits</description>
16692 
              <bitOffset>6</bitOffset>
16693 
              <bitWidth>1</bitWidth>
16694 
            </field>
16695 
            <field>
16696 
              <name>FB7</name>
16697 
              <description>Filter bits</description>
16698 
              <bitOffset>7</bitOffset>
16699 
              <bitWidth>1</bitWidth>
16700 
            </field>
16701 
            <field>
16702 
              <name>FB8</name>
16703 
              <description>Filter bits</description>
16704 
              <bitOffset>8</bitOffset>
16705 
              <bitWidth>1</bitWidth>
16706 
            </field>
16707 
            <field>
16708 
              <name>FB9</name>
16709 
              <description>Filter bits</description>
16710 
              <bitOffset>9</bitOffset>
16711 
              <bitWidth>1</bitWidth>
16712 
            </field>
16713 
            <field>
16714 
              <name>FB10</name>
16715 
              <description>Filter bits</description>
16716 
              <bitOffset>10</bitOffset>
16717 
              <bitWidth>1</bitWidth>
16718 
            </field>
16719 
            <field>
16720 
              <name>FB11</name>
16721 
              <description>Filter bits</description>
16722 
              <bitOffset>11</bitOffset>
16723 
              <bitWidth>1</bitWidth>
16724 
            </field>
16725 
            <field>
16726 
              <name>FB12</name>
16727 
              <description>Filter bits</description>
16728 
              <bitOffset>12</bitOffset>
16729 
              <bitWidth>1</bitWidth>
16730 
            </field>
16731 
            <field>
16732 
              <name>FB13</name>
16733 
              <description>Filter bits</description>
16734 
              <bitOffset>13</bitOffset>
16735 
              <bitWidth>1</bitWidth>
16736 
            </field>
16737 
            <field>
16738 
              <name>FB14</name>
16739 
              <description>Filter bits</description>
16740 
              <bitOffset>14</bitOffset>
16741 
              <bitWidth>1</bitWidth>
16742 
            </field>
16743 
            <field>
16744 
              <name>FB15</name>
16745 
              <description>Filter bits</description>
16746 
              <bitOffset>15</bitOffset>
16747 
              <bitWidth>1</bitWidth>
16748 
            </field>
16749 
            <field>
16750 
              <name>FB16</name>
16751 
              <description>Filter bits</description>
16752 
              <bitOffset>16</bitOffset>
16753 
              <bitWidth>1</bitWidth>
16754 
            </field>
16755 
            <field>
16756 
              <name>FB17</name>
16757 
              <description>Filter bits</description>
16758 
              <bitOffset>17</bitOffset>
16759 
              <bitWidth>1</bitWidth>
16760 
            </field>
16761 
            <field>
16762 
              <name>FB18</name>
16763 
              <description>Filter bits</description>
16764 
              <bitOffset>18</bitOffset>
16765 
              <bitWidth>1</bitWidth>
16766 
            </field>
16767 
            <field>
16768 
              <name>FB19</name>
16769 
              <description>Filter bits</description>
16770 
              <bitOffset>19</bitOffset>
16771 
              <bitWidth>1</bitWidth>
16772 
            </field>
16773 
            <field>
16774 
              <name>FB20</name>
16775 
              <description>Filter bits</description>
16776 
              <bitOffset>20</bitOffset>
16777 
              <bitWidth>1</bitWidth>
16778 
            </field>
16779 
            <field>
16780 
              <name>FB21</name>
16781 
              <description>Filter bits</description>
16782 
              <bitOffset>21</bitOffset>
16783 
              <bitWidth>1</bitWidth>
16784 
            </field>
16785 
            <field>
16786 
              <name>FB22</name>
16787 
              <description>Filter bits</description>
16788 
              <bitOffset>22</bitOffset>
16789 
              <bitWidth>1</bitWidth>
16790 
            </field>
16791 
            <field>
16792 
              <name>FB23</name>
16793 
              <description>Filter bits</description>
16794 
              <bitOffset>23</bitOffset>
16795 
              <bitWidth>1</bitWidth>
16796 
            </field>
16797 
            <field>
16798 
              <name>FB24</name>
16799 
              <description>Filter bits</description>
16800 
              <bitOffset>24</bitOffset>
16801 
              <bitWidth>1</bitWidth>
16802 
            </field>
16803 
            <field>
16804 
              <name>FB25</name>
16805 
              <description>Filter bits</description>
16806 
              <bitOffset>25</bitOffset>
16807 
              <bitWidth>1</bitWidth>
16808 
            </field>
16809 
            <field>
16810 
              <name>FB26</name>
16811 
              <description>Filter bits</description>
16812 
              <bitOffset>26</bitOffset>
16813 
              <bitWidth>1</bitWidth>
16814 
            </field>
16815 
            <field>
16816 
              <name>FB27</name>
16817 
              <description>Filter bits</description>
16818 
              <bitOffset>27</bitOffset>
16819 
              <bitWidth>1</bitWidth>
16820 
            </field>
16821 
            <field>
16822 
              <name>FB28</name>
16823 
              <description>Filter bits</description>
16824 
              <bitOffset>28</bitOffset>
16825 
              <bitWidth>1</bitWidth>
16826 
            </field>
16827 
            <field>
16828 
              <name>FB29</name>
16829 
              <description>Filter bits</description>
16830 
              <bitOffset>29</bitOffset>
16831 
              <bitWidth>1</bitWidth>
16832 
            </field>
16833 
            <field>
16834 
              <name>FB30</name>
16835 
              <description>Filter bits</description>
16836 
              <bitOffset>30</bitOffset>
16837 
              <bitWidth>1</bitWidth>
16838 
            </field>
16839 
            <field>
16840 
              <name>FB31</name>
16841 
              <description>Filter bits</description>
16842 
              <bitOffset>31</bitOffset>
16843 
              <bitWidth>1</bitWidth>
16844 
            </field>
16845 
          </fields>
16846 
        </register>
16847 
        <register>
16848 
          <name>F2R1</name>
16849 
          <displayName>F2R1</displayName>
16850 
          <description>Filter bank 2 register 1</description>
16851 
          <addressOffset>0x250</addressOffset>
16852 
          <size>0x20</size>
16853 
          <access>read-write</access>
16854 
          <resetValue>0x00000000</resetValue>
16855 
          <fields>
16856 
            <field>
16857 
              <name>FB0</name>
16858 
              <description>Filter bits</description>
16859 
              <bitOffset>0</bitOffset>
16860 
              <bitWidth>1</bitWidth>
16861 
            </field>
16862 
            <field>
16863 
              <name>FB1</name>
16864 
              <description>Filter bits</description>
16865 
              <bitOffset>1</bitOffset>
16866 
              <bitWidth>1</bitWidth>
16867 
            </field>
16868 
            <field>
16869 
              <name>FB2</name>
16870 
              <description>Filter bits</description>
16871 
              <bitOffset>2</bitOffset>
16872 
              <bitWidth>1</bitWidth>
16873 
            </field>
16874 
            <field>
16875 
              <name>FB3</name>
16876 
              <description>Filter bits</description>
16877 
              <bitOffset>3</bitOffset>
16878 
              <bitWidth>1</bitWidth>
16879 
            </field>
16880 
            <field>
16881 
              <name>FB4</name>
16882 
              <description>Filter bits</description>
16883 
              <bitOffset>4</bitOffset>
16884 
              <bitWidth>1</bitWidth>
16885 
            </field>
16886 
            <field>
16887 
              <name>FB5</name>
16888 
              <description>Filter bits</description>
16889 
              <bitOffset>5</bitOffset>
16890 
              <bitWidth>1</bitWidth>
16891 
            </field>
16892 
            <field>
16893 
              <name>FB6</name>
16894 
              <description>Filter bits</description>
16895 
              <bitOffset>6</bitOffset>
16896 
              <bitWidth>1</bitWidth>
16897 
            </field>
16898 
            <field>
16899 
              <name>FB7</name>
16900 
              <description>Filter bits</description>
16901 
              <bitOffset>7</bitOffset>
16902 
              <bitWidth>1</bitWidth>
16903 
            </field>
16904 
            <field>
16905 
              <name>FB8</name>
16906 
              <description>Filter bits</description>
16907 
              <bitOffset>8</bitOffset>
16908 
              <bitWidth>1</bitWidth>
16909 
            </field>
16910 
            <field>
16911 
              <name>FB9</name>
16912 
              <description>Filter bits</description>
16913 
              <bitOffset>9</bitOffset>
16914 
              <bitWidth>1</bitWidth>
16915 
            </field>
16916 
            <field>
16917 
              <name>FB10</name>
16918 
              <description>Filter bits</description>
16919 
              <bitOffset>10</bitOffset>
16920 
              <bitWidth>1</bitWidth>
16921 
            </field>
16922 
            <field>
16923 
              <name>FB11</name>
16924 
              <description>Filter bits</description>
16925 
              <bitOffset>11</bitOffset>
16926 
              <bitWidth>1</bitWidth>
16927 
            </field>
16928 
            <field>
16929 
              <name>FB12</name>
16930 
              <description>Filter bits</description>
16931 
              <bitOffset>12</bitOffset>
16932 
              <bitWidth>1</bitWidth>
16933 
            </field>
16934 
            <field>
16935 
              <name>FB13</name>
16936 
              <description>Filter bits</description>
16937 
              <bitOffset>13</bitOffset>
16938 
              <bitWidth>1</bitWidth>
16939 
            </field>
16940 
            <field>
16941 
              <name>FB14</name>
16942 
              <description>Filter bits</description>
16943 
              <bitOffset>14</bitOffset>
16944 
              <bitWidth>1</bitWidth>
16945 
            </field>
16946 
            <field>
16947 
              <name>FB15</name>
16948 
              <description>Filter bits</description>
16949 
              <bitOffset>15</bitOffset>
16950 
              <bitWidth>1</bitWidth>
16951 
            </field>
16952 
            <field>
16953 
              <name>FB16</name>
16954 
              <description>Filter bits</description>
16955 
              <bitOffset>16</bitOffset>
16956 
              <bitWidth>1</bitWidth>
16957 
            </field>
16958 
            <field>
16959 
              <name>FB17</name>
16960 
              <description>Filter bits</description>
16961 
              <bitOffset>17</bitOffset>
16962 
              <bitWidth>1</bitWidth>
16963 
            </field>
16964 
            <field>
16965 
              <name>FB18</name>
16966 
              <description>Filter bits</description>
16967 
              <bitOffset>18</bitOffset>
16968 
              <bitWidth>1</bitWidth>
16969 
            </field>
16970 
            <field>
16971 
              <name>FB19</name>
16972 
              <description>Filter bits</description>
16973 
              <bitOffset>19</bitOffset>
16974 
              <bitWidth>1</bitWidth>
16975 
            </field>
16976 
            <field>
16977 
              <name>FB20</name>
16978 
              <description>Filter bits</description>
16979 
              <bitOffset>20</bitOffset>
16980 
              <bitWidth>1</bitWidth>
16981 
            </field>
16982 
            <field>
16983 
              <name>FB21</name>
16984 
              <description>Filter bits</description>
16985 
              <bitOffset>21</bitOffset>
16986 
              <bitWidth>1</bitWidth>
16987 
            </field>
16988 
            <field>
16989 
              <name>FB22</name>
16990 
              <description>Filter bits</description>
16991 
              <bitOffset>22</bitOffset>
16992 
              <bitWidth>1</bitWidth>
16993 
            </field>
16994 
            <field>
16995 
              <name>FB23</name>
16996 
              <description>Filter bits</description>
16997 
              <bitOffset>23</bitOffset>
16998 
              <bitWidth>1</bitWidth>
16999 
            </field>
17000 
            <field>
17001 
              <name>FB24</name>
17002 
              <description>Filter bits</description>
17003 
              <bitOffset>24</bitOffset>
17004 
              <bitWidth>1</bitWidth>
17005 
            </field>
17006 
            <field>
17007 
              <name>FB25</name>
17008 
              <description>Filter bits</description>
17009 
              <bitOffset>25</bitOffset>
17010 
              <bitWidth>1</bitWidth>
17011 
            </field>
17012 
            <field>
17013 
              <name>FB26</name>
17014 
              <description>Filter bits</description>
17015 
              <bitOffset>26</bitOffset>
17016 
              <bitWidth>1</bitWidth>
17017 
            </field>
17018 
            <field>
17019 
              <name>FB27</name>
17020 
              <description>Filter bits</description>
17021 
              <bitOffset>27</bitOffset>
17022 
              <bitWidth>1</bitWidth>
17023 
            </field>
17024 
            <field>
17025 
              <name>FB28</name>
17026 
              <description>Filter bits</description>
17027 
              <bitOffset>28</bitOffset>
17028 
              <bitWidth>1</bitWidth>
17029 
            </field>
17030 
            <field>
17031 
              <name>FB29</name>
17032 
              <description>Filter bits</description>
17033 
              <bitOffset>29</bitOffset>
17034 
              <bitWidth>1</bitWidth>
17035 
            </field>
17036 
            <field>
17037 
              <name>FB30</name>
17038 
              <description>Filter bits</description>
17039 
              <bitOffset>30</bitOffset>
17040 
              <bitWidth>1</bitWidth>
17041 
            </field>
17042 
            <field>
17043 
              <name>FB31</name>
17044 
              <description>Filter bits</description>
17045 
              <bitOffset>31</bitOffset>
17046 
              <bitWidth>1</bitWidth>
17047 
            </field>
17048 
          </fields>
17049 
        </register>
17050 
        <register>
17051 
          <name>F2R2</name>
17052 
          <displayName>F2R2</displayName>
17053 
          <description>Filter bank 2 register 2</description>
17054 
          <addressOffset>0x254</addressOffset>
17055 
          <size>0x20</size>
17056 
          <access>read-write</access>
17057 
          <resetValue>0x00000000</resetValue>
17058 
          <fields>
17059 
            <field>
17060 
              <name>FB0</name>
17061 
              <description>Filter bits</description>
17062 
              <bitOffset>0</bitOffset>
17063 
              <bitWidth>1</bitWidth>
17064 
            </field>
17065 
            <field>
17066 
              <name>FB1</name>
17067 
              <description>Filter bits</description>
17068 
              <bitOffset>1</bitOffset>
17069 
              <bitWidth>1</bitWidth>
17070 
            </field>
17071 
            <field>
17072 
              <name>FB2</name>
17073 
              <description>Filter bits</description>
17074 
              <bitOffset>2</bitOffset>
17075 
              <bitWidth>1</bitWidth>
17076 
            </field>
17077 
            <field>
17078 
              <name>FB3</name>
17079 
              <description>Filter bits</description>
17080 
              <bitOffset>3</bitOffset>
17081 
              <bitWidth>1</bitWidth>
17082 
            </field>
17083 
            <field>
17084 
              <name>FB4</name>
17085 
              <description>Filter bits</description>
17086 
              <bitOffset>4</bitOffset>
17087 
              <bitWidth>1</bitWidth>
17088 
            </field>
17089 
            <field>
17090 
              <name>FB5</name>
17091 
              <description>Filter bits</description>
17092 
              <bitOffset>5</bitOffset>
17093 
              <bitWidth>1</bitWidth>
17094 
            </field>
17095 
            <field>
17096 
              <name>FB6</name>
17097 
              <description>Filter bits</description>
17098 
              <bitOffset>6</bitOffset>
17099 
              <bitWidth>1</bitWidth>
17100 
            </field>
17101 
            <field>
17102 
              <name>FB7</name>
17103 
              <description>Filter bits</description>
17104 
              <bitOffset>7</bitOffset>
17105 
              <bitWidth>1</bitWidth>
17106 
            </field>
17107 
            <field>
17108 
              <name>FB8</name>
17109 
              <description>Filter bits</description>
17110 
              <bitOffset>8</bitOffset>
17111 
              <bitWidth>1</bitWidth>
17112 
            </field>
17113 
            <field>
17114 
              <name>FB9</name>
17115 
              <description>Filter bits</description>
17116 
              <bitOffset>9</bitOffset>
17117 
              <bitWidth>1</bitWidth>
17118 
            </field>
17119 
            <field>
17120 
              <name>FB10</name>
17121 
              <description>Filter bits</description>
17122 
              <bitOffset>10</bitOffset>
17123 
              <bitWidth>1</bitWidth>
17124 
            </field>
17125 
            <field>
17126 
              <name>FB11</name>
17127 
              <description>Filter bits</description>
17128 
              <bitOffset>11</bitOffset>
17129 
              <bitWidth>1</bitWidth>
17130 
            </field>
17131 
            <field>
17132 
              <name>FB12</name>
17133 
              <description>Filter bits</description>
17134 
              <bitOffset>12</bitOffset>
17135 
              <bitWidth>1</bitWidth>
17136 
            </field>
17137 
            <field>
17138 
              <name>FB13</name>
17139 
              <description>Filter bits</description>
17140 
              <bitOffset>13</bitOffset>
17141 
              <bitWidth>1</bitWidth>
17142 
            </field>
17143 
            <field>
17144 
              <name>FB14</name>
17145 
              <description>Filter bits</description>
17146 
              <bitOffset>14</bitOffset>
17147 
              <bitWidth>1</bitWidth>
17148 
            </field>
17149 
            <field>
17150 
              <name>FB15</name>
17151 
              <description>Filter bits</description>
17152 
              <bitOffset>15</bitOffset>
17153 
              <bitWidth>1</bitWidth>
17154 
            </field>
17155 
            <field>
17156 
              <name>FB16</name>
17157 
              <description>Filter bits</description>
17158 
              <bitOffset>16</bitOffset>
17159 
              <bitWidth>1</bitWidth>
17160 
            </field>
17161 
            <field>
17162 
              <name>FB17</name>
17163 
              <description>Filter bits</description>
17164 
              <bitOffset>17</bitOffset>
17165 
              <bitWidth>1</bitWidth>
17166 
            </field>
17167 
            <field>
17168 
              <name>FB18</name>
17169 
              <description>Filter bits</description>
17170 
              <bitOffset>18</bitOffset>
17171 
              <bitWidth>1</bitWidth>
17172 
            </field>
17173 
            <field>
17174 
              <name>FB19</name>
17175 
              <description>Filter bits</description>
17176 
              <bitOffset>19</bitOffset>
17177 
              <bitWidth>1</bitWidth>
17178 
            </field>
17179 
            <field>
17180 
              <name>FB20</name>
17181 
              <description>Filter bits</description>
17182 
              <bitOffset>20</bitOffset>
17183 
              <bitWidth>1</bitWidth>
17184 
            </field>
17185 
            <field>
17186 
              <name>FB21</name>
17187 
              <description>Filter bits</description>
17188 
              <bitOffset>21</bitOffset>
17189 
              <bitWidth>1</bitWidth>
17190 
            </field>
17191 
            <field>
17192 
              <name>FB22</name>
17193 
              <description>Filter bits</description>
17194 
              <bitOffset>22</bitOffset>
17195 
              <bitWidth>1</bitWidth>
17196 
            </field>
17197 
            <field>
17198 
              <name>FB23</name>
17199 
              <description>Filter bits</description>
17200 
              <bitOffset>23</bitOffset>
17201 
              <bitWidth>1</bitWidth>
17202 
            </field>
17203 
            <field>
17204 
              <name>FB24</name>
17205 
              <description>Filter bits</description>
17206 
              <bitOffset>24</bitOffset>
17207 
              <bitWidth>1</bitWidth>
17208 
            </field>
17209 
            <field>
17210 
              <name>FB25</name>
17211 
              <description>Filter bits</description>
17212 
              <bitOffset>25</bitOffset>
17213 
              <bitWidth>1</bitWidth>
17214 
            </field>
17215 
            <field>
17216 
              <name>FB26</name>
17217 
              <description>Filter bits</description>
17218 
              <bitOffset>26</bitOffset>
17219 
              <bitWidth>1</bitWidth>
17220 
            </field>
17221 
            <field>
17222 
              <name>FB27</name>
17223 
              <description>Filter bits</description>
17224 
              <bitOffset>27</bitOffset>
17225 
              <bitWidth>1</bitWidth>
17226 
            </field>
17227 
            <field>
17228 
              <name>FB28</name>
17229 
              <description>Filter bits</description>
17230 
              <bitOffset>28</bitOffset>
17231 
              <bitWidth>1</bitWidth>
17232 
            </field>
17233 
            <field>
17234 
              <name>FB29</name>
17235 
              <description>Filter bits</description>
17236 
              <bitOffset>29</bitOffset>
17237 
              <bitWidth>1</bitWidth>
17238 
            </field>
17239 
            <field>
17240 
              <name>FB30</name>
17241 
              <description>Filter bits</description>
17242 
              <bitOffset>30</bitOffset>
17243 
              <bitWidth>1</bitWidth>
17244 
            </field>
17245 
            <field>
17246 
              <name>FB31</name>
17247 
              <description>Filter bits</description>
17248 
              <bitOffset>31</bitOffset>
17249 
              <bitWidth>1</bitWidth>
17250 
            </field>
17251 
          </fields>
17252 
        </register>
17253 
        <register>
17254 
          <name>F3R1</name>
17255 
          <displayName>F3R1</displayName>
17256 
          <description>Filter bank 3 register 1</description>
17257 
          <addressOffset>0x258</addressOffset>
17258 
          <size>0x20</size>
17259 
          <access>read-write</access>
17260 
          <resetValue>0x00000000</resetValue>
17261 
          <fields>
17262 
            <field>
17263 
              <name>FB0</name>
17264 
              <description>Filter bits</description>
17265 
              <bitOffset>0</bitOffset>
17266 
              <bitWidth>1</bitWidth>
17267 
            </field>
17268 
            <field>
17269 
              <name>FB1</name>
17270 
              <description>Filter bits</description>
17271 
              <bitOffset>1</bitOffset>
17272 
              <bitWidth>1</bitWidth>
17273 
            </field>
17274 
            <field>
17275 
              <name>FB2</name>
17276 
              <description>Filter bits</description>
17277 
              <bitOffset>2</bitOffset>
17278 
              <bitWidth>1</bitWidth>
17279 
            </field>
17280 
            <field>
17281 
              <name>FB3</name>
17282 
              <description>Filter bits</description>
17283 
              <bitOffset>3</bitOffset>
17284 
              <bitWidth>1</bitWidth>
17285 
            </field>
17286 
            <field>
17287 
              <name>FB4</name>
17288 
              <description>Filter bits</description>
17289 
              <bitOffset>4</bitOffset>
17290 
              <bitWidth>1</bitWidth>
17291 
            </field>
17292 
            <field>
17293 
              <name>FB5</name>
17294 
              <description>Filter bits</description>
17295 
              <bitOffset>5</bitOffset>
17296 
              <bitWidth>1</bitWidth>
17297 
            </field>
17298 
            <field>
17299 
              <name>FB6</name>
17300 
              <description>Filter bits</description>
17301 
              <bitOffset>6</bitOffset>
17302 
              <bitWidth>1</bitWidth>
17303 
            </field>
17304 
            <field>
17305 
              <name>FB7</name>
17306 
              <description>Filter bits</description>
17307 
              <bitOffset>7</bitOffset>
17308 
              <bitWidth>1</bitWidth>
17309 
            </field>
17310 
            <field>
17311 
              <name>FB8</name>
17312 
              <description>Filter bits</description>
17313 
              <bitOffset>8</bitOffset>
17314 
              <bitWidth>1</bitWidth>
17315 
            </field>
17316 
            <field>
17317 
              <name>FB9</name>
17318 
              <description>Filter bits</description>
17319 
              <bitOffset>9</bitOffset>
17320 
              <bitWidth>1</bitWidth>
17321 
            </field>
17322 
            <field>
17323 
              <name>FB10</name>
17324 
              <description>Filter bits</description>
17325 
              <bitOffset>10</bitOffset>
17326 
              <bitWidth>1</bitWidth>
17327 
            </field>
17328 
            <field>
17329 
              <name>FB11</name>
17330 
              <description>Filter bits</description>
17331 
              <bitOffset>11</bitOffset>
17332 
              <bitWidth>1</bitWidth>
17333 
            </field>
17334 
            <field>
17335 
              <name>FB12</name>
17336 
              <description>Filter bits</description>
17337 
              <bitOffset>12</bitOffset>
17338 
              <bitWidth>1</bitWidth>
17339 
            </field>
17340 
            <field>
17341 
              <name>FB13</name>
17342 
              <description>Filter bits</description>
17343 
              <bitOffset>13</bitOffset>
17344 
              <bitWidth>1</bitWidth>
17345 
            </field>
17346 
            <field>
17347 
              <name>FB14</name>
17348 
              <description>Filter bits</description>
17349 
              <bitOffset>14</bitOffset>
17350 
              <bitWidth>1</bitWidth>
17351 
            </field>
17352 
            <field>
17353 
              <name>FB15</name>
17354 
              <description>Filter bits</description>
17355 
              <bitOffset>15</bitOffset>
17356 
              <bitWidth>1</bitWidth>
17357 
            </field>
17358 
            <field>
17359 
              <name>FB16</name>
17360 
              <description>Filter bits</description>
17361 
              <bitOffset>16</bitOffset>
17362 
              <bitWidth>1</bitWidth>
17363 
            </field>
17364 
            <field>
17365 
              <name>FB17</name>
17366 
              <description>Filter bits</description>
17367 
              <bitOffset>17</bitOffset>
17368 
              <bitWidth>1</bitWidth>
17369 
            </field>
17370 
            <field>
17371 
              <name>FB18</name>
17372 
              <description>Filter bits</description>
17373 
              <bitOffset>18</bitOffset>
17374 
              <bitWidth>1</bitWidth>
17375 
            </field>
17376 
            <field>
17377 
              <name>FB19</name>
17378 
              <description>Filter bits</description>
17379 
              <bitOffset>19</bitOffset>
17380 
              <bitWidth>1</bitWidth>
17381 
            </field>
17382 
            <field>
17383 
              <name>FB20</name>
17384 
              <description>Filter bits</description>
17385 
              <bitOffset>20</bitOffset>
17386 
              <bitWidth>1</bitWidth>
17387 
            </field>
17388 
            <field>
17389 
              <name>FB21</name>
17390 
              <description>Filter bits</description>
17391 
              <bitOffset>21</bitOffset>
17392 
              <bitWidth>1</bitWidth>
17393 
            </field>
17394 
            <field>
17395 
              <name>FB22</name>
17396 
              <description>Filter bits</description>
17397 
              <bitOffset>22</bitOffset>
17398 
              <bitWidth>1</bitWidth>
17399 
            </field>
17400 
            <field>
17401 
              <name>FB23</name>
17402 
              <description>Filter bits</description>
17403 
              <bitOffset>23</bitOffset>
17404 
              <bitWidth>1</bitWidth>
17405 
            </field>
17406 
            <field>
17407 
              <name>FB24</name>
17408 
              <description>Filter bits</description>
17409 
              <bitOffset>24</bitOffset>
17410 
              <bitWidth>1</bitWidth>
17411 
            </field>
17412 
            <field>
17413 
              <name>FB25</name>
17414 
              <description>Filter bits</description>
17415 
              <bitOffset>25</bitOffset>
17416 
              <bitWidth>1</bitWidth>
17417 
            </field>
17418 
            <field>
17419 
              <name>FB26</name>
17420 
              <description>Filter bits</description>
17421 
              <bitOffset>26</bitOffset>
17422 
              <bitWidth>1</bitWidth>
17423 
            </field>
17424 
            <field>
17425 
              <name>FB27</name>
17426 
              <description>Filter bits</description>
17427 
              <bitOffset>27</bitOffset>
17428 
              <bitWidth>1</bitWidth>
17429 
            </field>
17430 
            <field>
17431 
              <name>FB28</name>
17432 
              <description>Filter bits</description>
17433 
              <bitOffset>28</bitOffset>
17434 
              <bitWidth>1</bitWidth>
17435 
            </field>
17436 
            <field>
17437 
              <name>FB29</name>
17438 
              <description>Filter bits</description>
17439 
              <bitOffset>29</bitOffset>
17440 
              <bitWidth>1</bitWidth>
17441 
            </field>
17442 
            <field>
17443 
              <name>FB30</name>
17444 
              <description>Filter bits</description>
17445 
              <bitOffset>30</bitOffset>
17446 
              <bitWidth>1</bitWidth>
17447 
            </field>
17448 
            <field>
17449 
              <name>FB31</name>
17450 
              <description>Filter bits</description>
17451 
              <bitOffset>31</bitOffset>
17452 
              <bitWidth>1</bitWidth>
17453 
            </field>
17454 
          </fields>
17455 
        </register>
17456 
        <register>
17457 
          <name>F3R2</name>
17458 
          <displayName>F3R2</displayName>
17459 
          <description>Filter bank 3 register 2</description>
17460 
          <addressOffset>0x25C</addressOffset>
17461 
          <size>0x20</size>
17462 
          <access>read-write</access>
17463 
          <resetValue>0x00000000</resetValue>
17464 
          <fields>
17465 
            <field>
17466 
              <name>FB0</name>
17467 
              <description>Filter bits</description>
17468 
              <bitOffset>0</bitOffset>
17469 
              <bitWidth>1</bitWidth>
17470 
            </field>
17471 
            <field>
17472 
              <name>FB1</name>
17473 
              <description>Filter bits</description>
17474 
              <bitOffset>1</bitOffset>
17475 
              <bitWidth>1</bitWidth>
17476 
            </field>
17477 
            <field>
17478 
              <name>FB2</name>
17479 
              <description>Filter bits</description>
17480 
              <bitOffset>2</bitOffset>
17481 
              <bitWidth>1</bitWidth>
17482 
            </field>
17483 
            <field>
17484 
              <name>FB3</name>
17485 
              <description>Filter bits</description>
17486 
              <bitOffset>3</bitOffset>
17487 
              <bitWidth>1</bitWidth>
17488 
            </field>
17489 
            <field>
17490 
              <name>FB4</name>
17491 
              <description>Filter bits</description>
17492 
              <bitOffset>4</bitOffset>
17493 
              <bitWidth>1</bitWidth>
17494 
            </field>
17495 
            <field>
17496 
              <name>FB5</name>
17497 
              <description>Filter bits</description>
17498 
              <bitOffset>5</bitOffset>
17499 
              <bitWidth>1</bitWidth>
17500 
            </field>
17501 
            <field>
17502 
              <name>FB6</name>
17503 
              <description>Filter bits</description>
17504 
              <bitOffset>6</bitOffset>
17505 
              <bitWidth>1</bitWidth>
17506 
            </field>
17507 
            <field>
17508 
              <name>FB7</name>
17509 
              <description>Filter bits</description>
17510 
              <bitOffset>7</bitOffset>
17511 
              <bitWidth>1</bitWidth>
17512 
            </field>
17513 
            <field>
17514 
              <name>FB8</name>
17515 
              <description>Filter bits</description>
17516 
              <bitOffset>8</bitOffset>
17517 
              <bitWidth>1</bitWidth>
17518 
            </field>
17519 
            <field>
17520 
              <name>FB9</name>
17521 
              <description>Filter bits</description>
17522 
              <bitOffset>9</bitOffset>
17523 
              <bitWidth>1</bitWidth>
17524 
            </field>
17525 
            <field>
17526 
              <name>FB10</name>
17527 
              <description>Filter bits</description>
17528 
              <bitOffset>10</bitOffset>
17529 
              <bitWidth>1</bitWidth>
17530 
            </field>
17531 
            <field>
17532 
              <name>FB11</name>
17533 
              <description>Filter bits</description>
17534 
              <bitOffset>11</bitOffset>
17535 
              <bitWidth>1</bitWidth>
17536 
            </field>
17537 
            <field>
17538 
              <name>FB12</name>
17539 
              <description>Filter bits</description>
17540 
              <bitOffset>12</bitOffset>
17541 
              <bitWidth>1</bitWidth>
17542 
            </field>
17543 
            <field>
17544 
              <name>FB13</name>
17545 
              <description>Filter bits</description>
17546 
              <bitOffset>13</bitOffset>
17547 
              <bitWidth>1</bitWidth>
17548 
            </field>
17549 
            <field>
17550 
              <name>FB14</name>
17551 
              <description>Filter bits</description>
17552 
              <bitOffset>14</bitOffset>
17553 
              <bitWidth>1</bitWidth>
17554 
            </field>
17555 
            <field>
17556 
              <name>FB15</name>
17557 
              <description>Filter bits</description>
17558 
              <bitOffset>15</bitOffset>
17559 
              <bitWidth>1</bitWidth>
17560 
            </field>
17561 
            <field>
17562 
              <name>FB16</name>
17563 
              <description>Filter bits</description>
17564 
              <bitOffset>16</bitOffset>
17565 
              <bitWidth>1</bitWidth>
17566 
            </field>
17567 
            <field>
17568 
              <name>FB17</name>
17569 
              <description>Filter bits</description>
17570 
              <bitOffset>17</bitOffset>
17571 
              <bitWidth>1</bitWidth>
17572 
            </field>
17573 
            <field>
17574 
              <name>FB18</name>
17575 
              <description>Filter bits</description>
17576 
              <bitOffset>18</bitOffset>
17577 
              <bitWidth>1</bitWidth>
17578 
            </field>
17579 
            <field>
17580 
              <name>FB19</name>
17581 
              <description>Filter bits</description>
17582 
              <bitOffset>19</bitOffset>
17583 
              <bitWidth>1</bitWidth>
17584 
            </field>
17585 
            <field>
17586 
              <name>FB20</name>
17587 
              <description>Filter bits</description>
17588 
              <bitOffset>20</bitOffset>
17589 
              <bitWidth>1</bitWidth>
17590 
            </field>
17591 
            <field>
17592 
              <name>FB21</name>
17593 
              <description>Filter bits</description>
17594 
              <bitOffset>21</bitOffset>
17595 
              <bitWidth>1</bitWidth>
17596 
            </field>
17597 
            <field>
17598 
              <name>FB22</name>
17599 
              <description>Filter bits</description>
17600 
              <bitOffset>22</bitOffset>
17601 
              <bitWidth>1</bitWidth>
17602 
            </field>
17603 
            <field>
17604 
              <name>FB23</name>
17605 
              <description>Filter bits</description>
17606 
              <bitOffset>23</bitOffset>
17607 
              <bitWidth>1</bitWidth>
17608 
            </field>
17609 
            <field>
17610 
              <name>FB24</name>
17611 
              <description>Filter bits</description>
17612 
              <bitOffset>24</bitOffset>
17613 
              <bitWidth>1</bitWidth>
17614 
            </field>
17615 
            <field>
17616 
              <name>FB25</name>
17617 
              <description>Filter bits</description>
17618 
              <bitOffset>25</bitOffset>
17619 
              <bitWidth>1</bitWidth>
17620 
            </field>
17621 
            <field>
17622 
              <name>FB26</name>
17623 
              <description>Filter bits</description>
17624 
              <bitOffset>26</bitOffset>
17625 
              <bitWidth>1</bitWidth>
17626 
            </field>
17627 
            <field>
17628 
              <name>FB27</name>
17629 
              <description>Filter bits</description>
17630 
              <bitOffset>27</bitOffset>
17631 
              <bitWidth>1</bitWidth>
17632 
            </field>
17633 
            <field>
17634 
              <name>FB28</name>
17635 
              <description>Filter bits</description>
17636 
              <bitOffset>28</bitOffset>
17637 
              <bitWidth>1</bitWidth>
17638 
            </field>
17639 
            <field>
17640 
              <name>FB29</name>
17641 
              <description>Filter bits</description>
17642 
              <bitOffset>29</bitOffset>
17643 
              <bitWidth>1</bitWidth>
17644 
            </field>
17645 
            <field>
17646 
              <name>FB30</name>
17647 
              <description>Filter bits</description>
17648 
              <bitOffset>30</bitOffset>
17649 
              <bitWidth>1</bitWidth>
17650 
            </field>
17651 
            <field>
17652 
              <name>FB31</name>
17653 
              <description>Filter bits</description>
17654 
              <bitOffset>31</bitOffset>
17655 
              <bitWidth>1</bitWidth>
17656 
            </field>
17657 
          </fields>
17658 
        </register>
17659 
        <register>
17660 
          <name>F4R1</name>
17661 
          <displayName>F4R1</displayName>
17662 
          <description>Filter bank 4 register 1</description>
17663 
          <addressOffset>0x260</addressOffset>
17664 
          <size>0x20</size>
17665 
          <access>read-write</access>
17666 
          <resetValue>0x00000000</resetValue>
17667 
          <fields>
17668 
            <field>
17669 
              <name>FB0</name>
17670 
              <description>Filter bits</description>
17671 
              <bitOffset>0</bitOffset>
17672 
              <bitWidth>1</bitWidth>
17673 
            </field>
17674 
            <field>
17675 
              <name>FB1</name>
17676 
              <description>Filter bits</description>
17677 
              <bitOffset>1</bitOffset>
17678 
              <bitWidth>1</bitWidth>
17679 
            </field>
17680 
            <field>
17681 
              <name>FB2</name>
17682 
              <description>Filter bits</description>
17683 
              <bitOffset>2</bitOffset>
17684 
              <bitWidth>1</bitWidth>
17685 
            </field>
17686 
            <field>
17687 
              <name>FB3</name>
17688 
              <description>Filter bits</description>
17689 
              <bitOffset>3</bitOffset>
17690 
              <bitWidth>1</bitWidth>
17691 
            </field>
17692 
            <field>
17693 
              <name>FB4</name>
17694 
              <description>Filter bits</description>
17695 
              <bitOffset>4</bitOffset>
17696 
              <bitWidth>1</bitWidth>
17697 
            </field>
17698 
            <field>
17699 
              <name>FB5</name>
17700 
              <description>Filter bits</description>
17701 
              <bitOffset>5</bitOffset>
17702 
              <bitWidth>1</bitWidth>
17703 
            </field>
17704 
            <field>
17705 
              <name>FB6</name>
17706 
              <description>Filter bits</description>
17707 
              <bitOffset>6</bitOffset>
17708 
              <bitWidth>1</bitWidth>
17709 
            </field>
17710 
            <field>
17711 
              <name>FB7</name>
17712 
              <description>Filter bits</description>
17713 
              <bitOffset>7</bitOffset>
17714 
              <bitWidth>1</bitWidth>
17715 
            </field>
17716 
            <field>
17717 
              <name>FB8</name>
17718 
              <description>Filter bits</description>
17719 
              <bitOffset>8</bitOffset>
17720 
              <bitWidth>1</bitWidth>
17721 
            </field>
17722 
            <field>
17723 
              <name>FB9</name>
17724 
              <description>Filter bits</description>
17725 
              <bitOffset>9</bitOffset>
17726 
              <bitWidth>1</bitWidth>
17727 
            </field>
17728 
            <field>
17729 
              <name>FB10</name>
17730 
              <description>Filter bits</description>
17731 
              <bitOffset>10</bitOffset>
17732 
              <bitWidth>1</bitWidth>
17733 
            </field>
17734 
            <field>
17735 
              <name>FB11</name>
17736 
              <description>Filter bits</description>
17737 
              <bitOffset>11</bitOffset>
17738 
              <bitWidth>1</bitWidth>
17739 
            </field>
17740 
            <field>
17741 
              <name>FB12</name>
17742 
              <description>Filter bits</description>
17743 
              <bitOffset>12</bitOffset>
17744 
              <bitWidth>1</bitWidth>
17745 
            </field>
17746 
            <field>
17747 
              <name>FB13</name>
17748 
              <description>Filter bits</description>
17749 
              <bitOffset>13</bitOffset>
17750 
              <bitWidth>1</bitWidth>
17751 
            </field>
17752 
            <field>
17753 
              <name>FB14</name>
17754 
              <description>Filter bits</description>
17755 
              <bitOffset>14</bitOffset>
17756 
              <bitWidth>1</bitWidth>
17757 
            </field>
17758 
            <field>
17759 
              <name>FB15</name>
17760 
              <description>Filter bits</description>
17761 
              <bitOffset>15</bitOffset>
17762 
              <bitWidth>1</bitWidth>
17763 
            </field>
17764 
            <field>
17765 
              <name>FB16</name>
17766 
              <description>Filter bits</description>
17767 
              <bitOffset>16</bitOffset>
17768 
              <bitWidth>1</bitWidth>
17769 
            </field>
17770 
            <field>
17771 
              <name>FB17</name>
17772 
              <description>Filter bits</description>
17773 
              <bitOffset>17</bitOffset>
17774 
              <bitWidth>1</bitWidth>
17775 
            </field>
17776 
            <field>
17777 
              <name>FB18</name>
17778 
              <description>Filter bits</description>
17779 
              <bitOffset>18</bitOffset>
17780 
              <bitWidth>1</bitWidth>
17781 
            </field>
17782 
            <field>
17783 
              <name>FB19</name>
17784 
              <description>Filter bits</description>
17785 
              <bitOffset>19</bitOffset>
17786 
              <bitWidth>1</bitWidth>
17787 
            </field>
17788 
            <field>
17789 
              <name>FB20</name>
17790 
              <description>Filter bits</description>
17791 
              <bitOffset>20</bitOffset>
17792 
              <bitWidth>1</bitWidth>
17793 
            </field>
17794 
            <field>
17795 
              <name>FB21</name>
17796 
              <description>Filter bits</description>
17797 
              <bitOffset>21</bitOffset>
17798 
              <bitWidth>1</bitWidth>
17799 
            </field>
17800 
            <field>
17801 
              <name>FB22</name>
17802 
              <description>Filter bits</description>
17803 
              <bitOffset>22</bitOffset>
17804 
              <bitWidth>1</bitWidth>
17805 
            </field>
17806 
            <field>
17807 
              <name>FB23</name>
17808 
              <description>Filter bits</description>
17809 
              <bitOffset>23</bitOffset>
17810 
              <bitWidth>1</bitWidth>
17811 
            </field>
17812 
            <field>
17813 
              <name>FB24</name>
17814 
              <description>Filter bits</description>
17815 
              <bitOffset>24</bitOffset>
17816 
              <bitWidth>1</bitWidth>
17817 
            </field>
17818 
            <field>
17819 
              <name>FB25</name>
17820 
              <description>Filter bits</description>
17821 
              <bitOffset>25</bitOffset>
17822 
              <bitWidth>1</bitWidth>
17823 
            </field>
17824 
            <field>
17825 
              <name>FB26</name>
17826 
              <description>Filter bits</description>
17827 
              <bitOffset>26</bitOffset>
17828 
              <bitWidth>1</bitWidth>
17829 
            </field>
17830 
            <field>
17831 
              <name>FB27</name>
17832 
              <description>Filter bits</description>
17833 
              <bitOffset>27</bitOffset>
17834 
              <bitWidth>1</bitWidth>
17835 
            </field>
17836 
            <field>
17837 
              <name>FB28</name>
17838 
              <description>Filter bits</description>
17839 
              <bitOffset>28</bitOffset>
17840 
              <bitWidth>1</bitWidth>
17841 
            </field>
17842 
            <field>
17843 
              <name>FB29</name>
17844 
              <description>Filter bits</description>
17845 
              <bitOffset>29</bitOffset>
17846 
              <bitWidth>1</bitWidth>
17847 
            </field>
17848 
            <field>
17849 
              <name>FB30</name>
17850 
              <description>Filter bits</description>
17851 
              <bitOffset>30</bitOffset>
17852 
              <bitWidth>1</bitWidth>
17853 
            </field>
17854 
            <field>
17855 
              <name>FB31</name>
17856 
              <description>Filter bits</description>
17857 
              <bitOffset>31</bitOffset>
17858 
              <bitWidth>1</bitWidth>
17859 
            </field>
17860 
          </fields>
17861 
        </register>
17862 
        <register>
17863 
          <name>F4R2</name>
17864 
          <displayName>F4R2</displayName>
17865 
          <description>Filter bank 4 register 2</description>
17866 
          <addressOffset>0x264</addressOffset>
17867 
          <size>0x20</size>
17868 
          <access>read-write</access>
17869 
          <resetValue>0x00000000</resetValue>
17870 
          <fields>
17871 
            <field>
17872 
              <name>FB0</name>
17873 
              <description>Filter bits</description>
17874 
              <bitOffset>0</bitOffset>
17875 
              <bitWidth>1</bitWidth>
17876 
            </field>
17877 
            <field>
17878 
              <name>FB1</name>
17879 
              <description>Filter bits</description>
17880 
              <bitOffset>1</bitOffset>
17881 
              <bitWidth>1</bitWidth>
17882 
            </field>
17883 
            <field>
17884 
              <name>FB2</name>
17885 
              <description>Filter bits</description>
17886 
              <bitOffset>2</bitOffset>
17887 
              <bitWidth>1</bitWidth>
17888 
            </field>
17889 
            <field>
17890 
              <name>FB3</name>
17891 
              <description>Filter bits</description>
17892 
              <bitOffset>3</bitOffset>
17893 
              <bitWidth>1</bitWidth>
17894 
            </field>
17895 
            <field>
17896 
              <name>FB4</name>
17897 
              <description>Filter bits</description>
17898 
              <bitOffset>4</bitOffset>
17899 
              <bitWidth>1</bitWidth>
17900 
            </field>
17901 
            <field>
17902 
              <name>FB5</name>
17903 
              <description>Filter bits</description>
17904 
              <bitOffset>5</bitOffset>
17905 
              <bitWidth>1</bitWidth>
17906 
            </field>
17907 
            <field>
17908 
              <name>FB6</name>
17909 
              <description>Filter bits</description>
17910 
              <bitOffset>6</bitOffset>
17911 
              <bitWidth>1</bitWidth>
17912 
            </field>
17913 
            <field>
17914 
              <name>FB7</name>
17915 
              <description>Filter bits</description>
17916 
              <bitOffset>7</bitOffset>
17917 
              <bitWidth>1</bitWidth>
17918 
            </field>
17919 
            <field>
17920 
              <name>FB8</name>
17921 
              <description>Filter bits</description>
17922 
              <bitOffset>8</bitOffset>
17923 
              <bitWidth>1</bitWidth>
17924 
            </field>
17925 
            <field>
17926 
              <name>FB9</name>
17927 
              <description>Filter bits</description>
17928 
              <bitOffset>9</bitOffset>
17929 
              <bitWidth>1</bitWidth>
17930 
            </field>
17931 
            <field>
17932 
              <name>FB10</name>
17933 
              <description>Filter bits</description>
17934 
              <bitOffset>10</bitOffset>
17935 
              <bitWidth>1</bitWidth>
17936 
            </field>
17937 
            <field>
17938 
              <name>FB11</name>
17939 
              <description>Filter bits</description>
17940 
              <bitOffset>11</bitOffset>
17941 
              <bitWidth>1</bitWidth>
17942 
            </field>
17943 
            <field>
17944 
              <name>FB12</name>
17945 
              <description>Filter bits</description>
17946 
              <bitOffset>12</bitOffset>
17947 
              <bitWidth>1</bitWidth>
17948 
            </field>
17949 
            <field>
17950 
              <name>FB13</name>
17951 
              <description>Filter bits</description>
17952 
              <bitOffset>13</bitOffset>
17953 
              <bitWidth>1</bitWidth>
17954 
            </field>
17955 
            <field>
17956 
              <name>FB14</name>
17957 
              <description>Filter bits</description>
17958 
              <bitOffset>14</bitOffset>
17959 
              <bitWidth>1</bitWidth>
17960 
            </field>
17961 
            <field>
17962 
              <name>FB15</name>
17963 
              <description>Filter bits</description>
17964 
              <bitOffset>15</bitOffset>
17965 
              <bitWidth>1</bitWidth>
17966 
            </field>
17967 
            <field>
17968 
              <name>FB16</name>
17969 
              <description>Filter bits</description>
17970 
              <bitOffset>16</bitOffset>
17971 
              <bitWidth>1</bitWidth>
17972 
            </field>
17973 
            <field>
17974 
              <name>FB17</name>
17975 
              <description>Filter bits</description>
17976 
              <bitOffset>17</bitOffset>
17977 
              <bitWidth>1</bitWidth>
17978 
            </field>
17979 
            <field>
17980 
              <name>FB18</name>
17981 
              <description>Filter bits</description>
17982 
              <bitOffset>18</bitOffset>
17983 
              <bitWidth>1</bitWidth>
17984 
            </field>
17985 
            <field>
17986 
              <name>FB19</name>
17987 
              <description>Filter bits</description>
17988 
              <bitOffset>19</bitOffset>
17989 
              <bitWidth>1</bitWidth>
17990 
            </field>
17991 
            <field>
17992 
              <name>FB20</name>
17993 
              <description>Filter bits</description>
17994 
              <bitOffset>20</bitOffset>
17995 
              <bitWidth>1</bitWidth>
17996 
            </field>
17997 
            <field>
17998 
              <name>FB21</name>
17999 
              <description>Filter bits</description>
18000 
              <bitOffset>21</bitOffset>
18001 
              <bitWidth>1</bitWidth>
18002 
            </field>
18003 
            <field>
18004 
              <name>FB22</name>
18005 
              <description>Filter bits</description>
18006 
              <bitOffset>22</bitOffset>
18007 
              <bitWidth>1</bitWidth>
18008 
            </field>
18009 
            <field>
18010 
              <name>FB23</name>
18011 
              <description>Filter bits</description>
18012 
              <bitOffset>23</bitOffset>
18013 
              <bitWidth>1</bitWidth>
18014 
            </field>
18015 
            <field>
18016 
              <name>FB24</name>
18017 
              <description>Filter bits</description>
18018 
              <bitOffset>24</bitOffset>
18019 
              <bitWidth>1</bitWidth>
18020 
            </field>
18021 
            <field>
18022 
              <name>FB25</name>
18023 
              <description>Filter bits</description>
18024 
              <bitOffset>25</bitOffset>
18025 
              <bitWidth>1</bitWidth>
18026 
            </field>
18027 
            <field>
18028 
              <name>FB26</name>
18029 
              <description>Filter bits</description>
18030 
              <bitOffset>26</bitOffset>
18031 
              <bitWidth>1</bitWidth>
18032 
            </field>
18033 
            <field>
18034 
              <name>FB27</name>
18035 
              <description>Filter bits</description>
18036 
              <bitOffset>27</bitOffset>
18037 
              <bitWidth>1</bitWidth>
18038 
            </field>
18039 
            <field>
18040 
              <name>FB28</name>
18041 
              <description>Filter bits</description>
18042 
              <bitOffset>28</bitOffset>
18043 
              <bitWidth>1</bitWidth>
18044 
            </field>
18045 
            <field>
18046 
              <name>FB29</name>
18047 
              <description>Filter bits</description>
18048 
              <bitOffset>29</bitOffset>
18049 
              <bitWidth>1</bitWidth>
18050 
            </field>
18051 
            <field>
18052 
              <name>FB30</name>
18053 
              <description>Filter bits</description>
18054 
              <bitOffset>30</bitOffset>
18055 
              <bitWidth>1</bitWidth>
18056 
            </field>
18057 
            <field>
18058 
              <name>FB31</name>
18059 
              <description>Filter bits</description>
18060 
              <bitOffset>31</bitOffset>
18061 
              <bitWidth>1</bitWidth>
18062 
            </field>
18063 
          </fields>
18064 
        </register>
18065 
        <register>
18066 
          <name>F5R1</name>
18067 
          <displayName>F5R1</displayName>
18068 
          <description>Filter bank 5 register 1</description>
18069 
          <addressOffset>0x268</addressOffset>
18070 
          <size>0x20</size>
18071 
          <access>read-write</access>
18072 
          <resetValue>0x00000000</resetValue>
18073 
          <fields>
18074 
            <field>
18075 
              <name>FB0</name>
18076 
              <description>Filter bits</description>
18077 
              <bitOffset>0</bitOffset>
18078 
              <bitWidth>1</bitWidth>
18079 
            </field>
18080 
            <field>
18081 
              <name>FB1</name>
18082 
              <description>Filter bits</description>
18083 
              <bitOffset>1</bitOffset>
18084 
              <bitWidth>1</bitWidth>
18085 
            </field>
18086 
            <field>
18087 
              <name>FB2</name>
18088 
              <description>Filter bits</description>
18089 
              <bitOffset>2</bitOffset>
18090 
              <bitWidth>1</bitWidth>
18091 
            </field>
18092 
            <field>
18093 
              <name>FB3</name>
18094 
              <description>Filter bits</description>
18095 
              <bitOffset>3</bitOffset>
18096 
              <bitWidth>1</bitWidth>
18097 
            </field>
18098 
            <field>
18099 
              <name>FB4</name>
18100 
              <description>Filter bits</description>
18101 
              <bitOffset>4</bitOffset>
18102 
              <bitWidth>1</bitWidth>
18103 
            </field>
18104 
            <field>
18105 
              <name>FB5</name>
18106 
              <description>Filter bits</description>
18107 
              <bitOffset>5</bitOffset>
18108 
              <bitWidth>1</bitWidth>
18109 
            </field>
18110 
            <field>
18111 
              <name>FB6</name>
18112 
              <description>Filter bits</description>
18113 
              <bitOffset>6</bitOffset>
18114 
              <bitWidth>1</bitWidth>
18115 
            </field>
18116 
            <field>
18117 
              <name>FB7</name>
18118 
              <description>Filter bits</description>
18119 
              <bitOffset>7</bitOffset>
18120 
              <bitWidth>1</bitWidth>
18121 
            </field>
18122 
            <field>
18123 
              <name>FB8</name>
18124 
              <description>Filter bits</description>
18125 
              <bitOffset>8</bitOffset>
18126 
              <bitWidth>1</bitWidth>
18127 
            </field>
18128 
            <field>
18129 
              <name>FB9</name>
18130 
              <description>Filter bits</description>
18131 
              <bitOffset>9</bitOffset>
18132 
              <bitWidth>1</bitWidth>
18133 
            </field>
18134 
            <field>
18135 
              <name>FB10</name>
18136 
              <description>Filter bits</description>
18137 
              <bitOffset>10</bitOffset>
18138 
              <bitWidth>1</bitWidth>
18139 
            </field>
18140 
            <field>
18141 
              <name>FB11</name>
18142 
              <description>Filter bits</description>
18143 
              <bitOffset>11</bitOffset>
18144 
              <bitWidth>1</bitWidth>
18145 
            </field>
18146 
            <field>
18147 
              <name>FB12</name>
18148 
              <description>Filter bits</description>
18149 
              <bitOffset>12</bitOffset>
18150 
              <bitWidth>1</bitWidth>
18151 
            </field>
18152 
            <field>
18153 
              <name>FB13</name>
18154 
              <description>Filter bits</description>
18155 
              <bitOffset>13</bitOffset>
18156 
              <bitWidth>1</bitWidth>
18157 
            </field>
18158 
            <field>
18159 
              <name>FB14</name>
18160 
              <description>Filter bits</description>
18161 
              <bitOffset>14</bitOffset>
18162 
              <bitWidth>1</bitWidth>
18163 
            </field>
18164 
            <field>
18165 
              <name>FB15</name>
18166 
              <description>Filter bits</description>
18167 
              <bitOffset>15</bitOffset>
18168 
              <bitWidth>1</bitWidth>
18169 
            </field>
18170 
            <field>
18171 
              <name>FB16</name>
18172 
              <description>Filter bits</description>
18173 
              <bitOffset>16</bitOffset>
18174 
              <bitWidth>1</bitWidth>
18175 
            </field>
18176 
            <field>
18177 
              <name>FB17</name>
18178 
              <description>Filter bits</description>
18179 
              <bitOffset>17</bitOffset>
18180 
              <bitWidth>1</bitWidth>
18181 
            </field>
18182 
            <field>
18183 
              <name>FB18</name>
18184 
              <description>Filter bits</description>
18185 
              <bitOffset>18</bitOffset>
18186 
              <bitWidth>1</bitWidth>
18187 
            </field>
18188 
            <field>
18189 
              <name>FB19</name>
18190 
              <description>Filter bits</description>
18191 
              <bitOffset>19</bitOffset>
18192 
              <bitWidth>1</bitWidth>
18193 
            </field>
18194 
            <field>
18195 
              <name>FB20</name>
18196 
              <description>Filter bits</description>
18197 
              <bitOffset>20</bitOffset>
18198 
              <bitWidth>1</bitWidth>
18199 
            </field>
18200 
            <field>
18201 
              <name>FB21</name>
18202 
              <description>Filter bits</description>
18203 
              <bitOffset>21</bitOffset>
18204 
              <bitWidth>1</bitWidth>
18205 
            </field>
18206 
            <field>
18207 
              <name>FB22</name>
18208 
              <description>Filter bits</description>
18209 
              <bitOffset>22</bitOffset>
18210 
              <bitWidth>1</bitWidth>
18211 
            </field>
18212 
            <field>
18213 
              <name>FB23</name>
18214 
              <description>Filter bits</description>
18215 
              <bitOffset>23</bitOffset>
18216 
              <bitWidth>1</bitWidth>
18217 
            </field>
18218 
            <field>
18219 
              <name>FB24</name>
18220 
              <description>Filter bits</description>
18221 
              <bitOffset>24</bitOffset>
18222 
              <bitWidth>1</bitWidth>
18223 
            </field>
18224 
            <field>
18225 
              <name>FB25</name>
18226 
              <description>Filter bits</description>
18227 
              <bitOffset>25</bitOffset>
18228 
              <bitWidth>1</bitWidth>
18229 
            </field>
18230 
            <field>
18231 
              <name>FB26</name>
18232 
              <description>Filter bits</description>
18233 
              <bitOffset>26</bitOffset>
18234 
              <bitWidth>1</bitWidth>
18235 
            </field>
18236 
            <field>
18237 
              <name>FB27</name>
18238 
              <description>Filter bits</description>
18239 
              <bitOffset>27</bitOffset>
18240 
              <bitWidth>1</bitWidth>
18241 
            </field>
18242 
            <field>
18243 
              <name>FB28</name>
18244 
              <description>Filter bits</description>
18245 
              <bitOffset>28</bitOffset>
18246 
              <bitWidth>1</bitWidth>
18247 
            </field>
18248 
            <field>
18249 
              <name>FB29</name>
18250 
              <description>Filter bits</description>
18251 
              <bitOffset>29</bitOffset>
18252 
              <bitWidth>1</bitWidth>
18253 
            </field>
18254 
            <field>
18255 
              <name>FB30</name>
18256 
              <description>Filter bits</description>
18257 
              <bitOffset>30</bitOffset>
18258 
              <bitWidth>1</bitWidth>
18259 
            </field>
18260 
            <field>
18261 
              <name>FB31</name>
18262 
              <description>Filter bits</description>
18263 
              <bitOffset>31</bitOffset>
18264 
              <bitWidth>1</bitWidth>
18265 
            </field>
18266 
          </fields>
18267 
        </register>
18268 
        <register>
18269 
          <name>F5R2</name>
18270 
          <displayName>F5R2</displayName>
18271 
          <description>Filter bank 5 register 2</description>
18272 
          <addressOffset>0x26C</addressOffset>
18273 
          <size>0x20</size>
18274 
          <access>read-write</access>
18275 
          <resetValue>0x00000000</resetValue>
18276 
          <fields>
18277 
            <field>
18278 
              <name>FB0</name>
18279 
              <description>Filter bits</description>
18280 
              <bitOffset>0</bitOffset>
18281 
              <bitWidth>1</bitWidth>
18282 
            </field>
18283 
            <field>
18284 
              <name>FB1</name>
18285 
              <description>Filter bits</description>
18286 
              <bitOffset>1</bitOffset>
18287 
              <bitWidth>1</bitWidth>
18288 
            </field>
18289 
            <field>
18290 
              <name>FB2</name>
18291 
              <description>Filter bits</description>
18292 
              <bitOffset>2</bitOffset>
18293 
              <bitWidth>1</bitWidth>
18294 
            </field>
18295 
            <field>
18296 
              <name>FB3</name>
18297 
              <description>Filter bits</description>
18298 
              <bitOffset>3</bitOffset>
18299 
              <bitWidth>1</bitWidth>
18300 
            </field>
18301 
            <field>
18302 
              <name>FB4</name>
18303 
              <description>Filter bits</description>
18304 
              <bitOffset>4</bitOffset>
18305 
              <bitWidth>1</bitWidth>
18306 
            </field>
18307 
            <field>
18308 
              <name>FB5</name>
18309 
              <description>Filter bits</description>
18310 
              <bitOffset>5</bitOffset>
18311 
              <bitWidth>1</bitWidth>
18312 
            </field>
18313 
            <field>
18314 
              <name>FB6</name>
18315 
              <description>Filter bits</description>
18316 
              <bitOffset>6</bitOffset>
18317 
              <bitWidth>1</bitWidth>
18318 
            </field>
18319 
            <field>
18320 
              <name>FB7</name>
18321 
              <description>Filter bits</description>
18322 
              <bitOffset>7</bitOffset>
18323 
              <bitWidth>1</bitWidth>
18324 
            </field>
18325 
            <field>
18326 
              <name>FB8</name>
18327 
              <description>Filter bits</description>
18328 
              <bitOffset>8</bitOffset>
18329 
              <bitWidth>1</bitWidth>
18330 
            </field>
18331 
            <field>
18332 
              <name>FB9</name>
18333 
              <description>Filter bits</description>
18334 
              <bitOffset>9</bitOffset>
18335 
              <bitWidth>1</bitWidth>
18336 
            </field>
18337 
            <field>
18338 
              <name>FB10</name>
18339 
              <description>Filter bits</description>
18340 
              <bitOffset>10</bitOffset>
18341 
              <bitWidth>1</bitWidth>
18342 
            </field>
18343 
            <field>
18344 
              <name>FB11</name>
18345 
              <description>Filter bits</description>
18346 
              <bitOffset>11</bitOffset>
18347 
              <bitWidth>1</bitWidth>
18348 
            </field>
18349 
            <field>
18350 
              <name>FB12</name>
18351 
              <description>Filter bits</description>
18352 
              <bitOffset>12</bitOffset>
18353 
              <bitWidth>1</bitWidth>
18354 
            </field>
18355 
            <field>
18356 
              <name>FB13</name>
18357 
              <description>Filter bits</description>
18358 
              <bitOffset>13</bitOffset>
18359 
              <bitWidth>1</bitWidth>
18360 
            </field>
18361 
            <field>
18362 
              <name>FB14</name>
18363 
              <description>Filter bits</description>
18364 
              <bitOffset>14</bitOffset>
18365 
              <bitWidth>1</bitWidth>
18366 
            </field>
18367 
            <field>
18368 
              <name>FB15</name>
18369 
              <description>Filter bits</description>
18370 
              <bitOffset>15</bitOffset>
18371 
              <bitWidth>1</bitWidth>
18372 
            </field>
18373 
            <field>
18374 
              <name>FB16</name>
18375 
              <description>Filter bits</description>
18376 
              <bitOffset>16</bitOffset>
18377 
              <bitWidth>1</bitWidth>
18378 
            </field>
18379 
            <field>
18380 
              <name>FB17</name>
18381 
              <description>Filter bits</description>
18382 
              <bitOffset>17</bitOffset>
18383 
              <bitWidth>1</bitWidth>
18384 
            </field>
18385 
            <field>
18386 
              <name>FB18</name>
18387 
              <description>Filter bits</description>
18388 
              <bitOffset>18</bitOffset>
18389 
              <bitWidth>1</bitWidth>
18390 
            </field>
18391 
            <field>
18392 
              <name>FB19</name>
18393 
              <description>Filter bits</description>
18394 
              <bitOffset>19</bitOffset>
18395 
              <bitWidth>1</bitWidth>
18396 
            </field>
18397 
            <field>
18398 
              <name>FB20</name>
18399 
              <description>Filter bits</description>
18400 
              <bitOffset>20</bitOffset>
18401 
              <bitWidth>1</bitWidth>
18402 
            </field>
18403 
            <field>
18404 
              <name>FB21</name>
18405 
              <description>Filter bits</description>
18406 
              <bitOffset>21</bitOffset>
18407 
              <bitWidth>1</bitWidth>
18408 
            </field>
18409 
            <field>
18410 
              <name>FB22</name>
18411 
              <description>Filter bits</description>
18412 
              <bitOffset>22</bitOffset>
18413 
              <bitWidth>1</bitWidth>
18414 
            </field>
18415 
            <field>
18416 
              <name>FB23</name>
18417 
              <description>Filter bits</description>
18418 
              <bitOffset>23</bitOffset>
18419 
              <bitWidth>1</bitWidth>
18420 
            </field>
18421 
            <field>
18422 
              <name>FB24</name>
18423 
              <description>Filter bits</description>
18424 
              <bitOffset>24</bitOffset>
18425 
              <bitWidth>1</bitWidth>
18426 
            </field>
18427 
            <field>
18428 
              <name>FB25</name>
18429 
              <description>Filter bits</description>
18430 
              <bitOffset>25</bitOffset>
18431 
              <bitWidth>1</bitWidth>
18432 
            </field>
18433 
            <field>
18434 
              <name>FB26</name>
18435 
              <description>Filter bits</description>
18436 
              <bitOffset>26</bitOffset>
18437 
              <bitWidth>1</bitWidth>
18438 
            </field>
18439 
            <field>
18440 
              <name>FB27</name>
18441 
              <description>Filter bits</description>
18442 
              <bitOffset>27</bitOffset>
18443 
              <bitWidth>1</bitWidth>
18444 
            </field>
18445 
            <field>
18446 
              <name>FB28</name>
18447 
              <description>Filter bits</description>
18448 
              <bitOffset>28</bitOffset>
18449 
              <bitWidth>1</bitWidth>
18450 
            </field>
18451 
            <field>
18452 
              <name>FB29</name>
18453 
              <description>Filter bits</description>
18454 
              <bitOffset>29</bitOffset>
18455 
              <bitWidth>1</bitWidth>
18456 
            </field>
18457 
            <field>
18458 
              <name>FB30</name>
18459 
              <description>Filter bits</description>
18460 
              <bitOffset>30</bitOffset>
18461 
              <bitWidth>1</bitWidth>
18462 
            </field>
18463 
            <field>
18464 
              <name>FB31</name>
18465 
              <description>Filter bits</description>
18466 
              <bitOffset>31</bitOffset>
18467 
              <bitWidth>1</bitWidth>
18468 
            </field>
18469 
          </fields>
18470 
        </register>
18471 
        <register>
18472 
          <name>F6R1</name>
18473 
          <displayName>F6R1</displayName>
18474 
          <description>Filter bank 6 register 1</description>
18475 
          <addressOffset>0x270</addressOffset>
18476 
          <size>0x20</size>
18477 
          <access>read-write</access>
18478 
          <resetValue>0x00000000</resetValue>
18479 
          <fields>
18480 
            <field>
18481 
              <name>FB0</name>
18482 
              <description>Filter bits</description>
18483 
              <bitOffset>0</bitOffset>
18484 
              <bitWidth>1</bitWidth>
18485 
            </field>
18486 
            <field>
18487 
              <name>FB1</name>
18488 
              <description>Filter bits</description>
18489 
              <bitOffset>1</bitOffset>
18490 
              <bitWidth>1</bitWidth>
18491 
            </field>
18492 
            <field>
18493 
              <name>FB2</name>
18494 
              <description>Filter bits</description>
18495 
              <bitOffset>2</bitOffset>
18496 
              <bitWidth>1</bitWidth>
18497 
            </field>
18498 
            <field>
18499 
              <name>FB3</name>
18500 
              <description>Filter bits</description>
18501 
              <bitOffset>3</bitOffset>
18502 
              <bitWidth>1</bitWidth>
18503 
            </field>
18504 
            <field>
18505 
              <name>FB4</name>
18506 
              <description>Filter bits</description>
18507 
              <bitOffset>4</bitOffset>
18508 
              <bitWidth>1</bitWidth>
18509 
            </field>
18510 
            <field>
18511 
              <name>FB5</name>
18512 
              <description>Filter bits</description>
18513 
              <bitOffset>5</bitOffset>
18514 
              <bitWidth>1</bitWidth>
18515 
            </field>
18516 
            <field>
18517 
              <name>FB6</name>
18518 
              <description>Filter bits</description>
18519 
              <bitOffset>6</bitOffset>
18520 
              <bitWidth>1</bitWidth>
18521 
            </field>
18522 
            <field>
18523 
              <name>FB7</name>
18524 
              <description>Filter bits</description>
18525 
              <bitOffset>7</bitOffset>
18526 
              <bitWidth>1</bitWidth>
18527 
            </field>
18528 
            <field>
18529 
              <name>FB8</name>
18530 
              <description>Filter bits</description>
18531 
              <bitOffset>8</bitOffset>
18532 
              <bitWidth>1</bitWidth>
18533 
            </field>
18534 
            <field>
18535 
              <name>FB9</name>
18536 
              <description>Filter bits</description>
18537 
              <bitOffset>9</bitOffset>
18538 
              <bitWidth>1</bitWidth>
18539 
            </field>
18540 
            <field>
18541 
              <name>FB10</name>
18542 
              <description>Filter bits</description>
18543 
              <bitOffset>10</bitOffset>
18544 
              <bitWidth>1</bitWidth>
18545 
            </field>
18546 
            <field>
18547 
              <name>FB11</name>
18548 
              <description>Filter bits</description>
18549 
              <bitOffset>11</bitOffset>
18550 
              <bitWidth>1</bitWidth>
18551 
            </field>
18552 
            <field>
18553 
              <name>FB12</name>
18554 
              <description>Filter bits</description>
18555 
              <bitOffset>12</bitOffset>
18556 
              <bitWidth>1</bitWidth>
18557 
            </field>
18558 
            <field>
18559 
              <name>FB13</name>
18560 
              <description>Filter bits</description>
18561 
              <bitOffset>13</bitOffset>
18562 
              <bitWidth>1</bitWidth>
18563 
            </field>
18564 
            <field>
18565 
              <name>FB14</name>
18566 
              <description>Filter bits</description>
18567 
              <bitOffset>14</bitOffset>
18568 
              <bitWidth>1</bitWidth>
18569 
            </field>
18570 
            <field>
18571 
              <name>FB15</name>
18572 
              <description>Filter bits</description>
18573 
              <bitOffset>15</bitOffset>
18574 
              <bitWidth>1</bitWidth>
18575 
            </field>
18576 
            <field>
18577 
              <name>FB16</name>
18578 
              <description>Filter bits</description>
18579 
              <bitOffset>16</bitOffset>
18580 
              <bitWidth>1</bitWidth>
18581 
            </field>
18582 
            <field>
18583 
              <name>FB17</name>
18584 
              <description>Filter bits</description>
18585 
              <bitOffset>17</bitOffset>
18586 
              <bitWidth>1</bitWidth>
18587 
            </field>
18588 
            <field>
18589 
              <name>FB18</name>
18590 
              <description>Filter bits</description>
18591 
              <bitOffset>18</bitOffset>
18592 
              <bitWidth>1</bitWidth>
18593 
            </field>
18594 
            <field>
18595 
              <name>FB19</name>
18596 
              <description>Filter bits</description>
18597 
              <bitOffset>19</bitOffset>
18598 
              <bitWidth>1</bitWidth>
18599 
            </field>
18600 
            <field>
18601 
              <name>FB20</name>
18602 
              <description>Filter bits</description>
18603 
              <bitOffset>20</bitOffset>
18604 
              <bitWidth>1</bitWidth>
18605 
            </field>
18606 
            <field>
18607 
              <name>FB21</name>
18608 
              <description>Filter bits</description>
18609 
              <bitOffset>21</bitOffset>
18610 
              <bitWidth>1</bitWidth>
18611 
            </field>
18612 
            <field>
18613 
              <name>FB22</name>
18614 
              <description>Filter bits</description>
18615 
              <bitOffset>22</bitOffset>
18616 
              <bitWidth>1</bitWidth>
18617 
            </field>
18618 
            <field>
18619 
              <name>FB23</name>
18620 
              <description>Filter bits</description>
18621 
              <bitOffset>23</bitOffset>
18622 
              <bitWidth>1</bitWidth>
18623 
            </field>
18624 
            <field>
18625 
              <name>FB24</name>
18626 
              <description>Filter bits</description>
18627 
              <bitOffset>24</bitOffset>
18628 
              <bitWidth>1</bitWidth>
18629 
            </field>
18630 
            <field>
18631 
              <name>FB25</name>
18632 
              <description>Filter bits</description>
18633 
              <bitOffset>25</bitOffset>
18634 
              <bitWidth>1</bitWidth>
18635 
            </field>
18636 
            <field>
18637 
              <name>FB26</name>
18638 
              <description>Filter bits</description>
18639 
              <bitOffset>26</bitOffset>
18640 
              <bitWidth>1</bitWidth>
18641 
            </field>
18642 
            <field>
18643 
              <name>FB27</name>
18644 
              <description>Filter bits</description>
18645 
              <bitOffset>27</bitOffset>
18646 
              <bitWidth>1</bitWidth>
18647 
            </field>
18648 
            <field>
18649 
              <name>FB28</name>
18650 
              <description>Filter bits</description>
18651 
              <bitOffset>28</bitOffset>
18652 
              <bitWidth>1</bitWidth>
18653 
            </field>
18654 
            <field>
18655 
              <name>FB29</name>
18656 
              <description>Filter bits</description>
18657 
              <bitOffset>29</bitOffset>
18658 
              <bitWidth>1</bitWidth>
18659 
            </field>
18660 
            <field>
18661 
              <name>FB30</name>
18662 
              <description>Filter bits</description>
18663 
              <bitOffset>30</bitOffset>
18664 
              <bitWidth>1</bitWidth>
18665 
            </field>
18666 
            <field>
18667 
              <name>FB31</name>
18668 
              <description>Filter bits</description>
18669 
              <bitOffset>31</bitOffset>
18670 
              <bitWidth>1</bitWidth>
18671 
            </field>
18672 
          </fields>
18673 
        </register>
18674 
        <register>
18675 
          <name>F6R2</name>
18676 
          <displayName>F6R2</displayName>
18677 
          <description>Filter bank 6 register 2</description>
18678 
          <addressOffset>0x274</addressOffset>
18679 
          <size>0x20</size>
18680 
          <access>read-write</access>
18681 
          <resetValue>0x00000000</resetValue>
18682 
          <fields>
18683 
            <field>
18684 
              <name>FB0</name>
18685 
              <description>Filter bits</description>
18686 
              <bitOffset>0</bitOffset>
18687 
              <bitWidth>1</bitWidth>
18688 
            </field>
18689 
            <field>
18690 
              <name>FB1</name>
18691 
              <description>Filter bits</description>
18692 
              <bitOffset>1</bitOffset>
18693 
              <bitWidth>1</bitWidth>
18694 
            </field>
18695 
            <field>
18696 
              <name>FB2</name>
18697 
              <description>Filter bits</description>
18698 
              <bitOffset>2</bitOffset>
18699 
              <bitWidth>1</bitWidth>
18700 
            </field>
18701 
            <field>
18702 
              <name>FB3</name>
18703 
              <description>Filter bits</description>
18704 
              <bitOffset>3</bitOffset>
18705 
              <bitWidth>1</bitWidth>
18706 
            </field>
18707 
            <field>
18708 
              <name>FB4</name>
18709 
              <description>Filter bits</description>
18710 
              <bitOffset>4</bitOffset>
18711 
              <bitWidth>1</bitWidth>
18712 
            </field>
18713 
            <field>
18714 
              <name>FB5</name>
18715 
              <description>Filter bits</description>
18716 
              <bitOffset>5</bitOffset>
18717 
              <bitWidth>1</bitWidth>
18718 
            </field>
18719 
            <field>
18720 
              <name>FB6</name>
18721 
              <description>Filter bits</description>
18722 
              <bitOffset>6</bitOffset>
18723 
              <bitWidth>1</bitWidth>
18724 
            </field>
18725 
            <field>
18726 
              <name>FB7</name>
18727 
              <description>Filter bits</description>
18728 
              <bitOffset>7</bitOffset>
18729 
              <bitWidth>1</bitWidth>
18730 
            </field>
18731 
            <field>
18732 
              <name>FB8</name>
18733 
              <description>Filter bits</description>
18734 
              <bitOffset>8</bitOffset>
18735 
              <bitWidth>1</bitWidth>
18736 
            </field>
18737 
            <field>
18738 
              <name>FB9</name>
18739 
              <description>Filter bits</description>
18740 
              <bitOffset>9</bitOffset>
18741 
              <bitWidth>1</bitWidth>
18742 
            </field>
18743 
            <field>
18744 
              <name>FB10</name>
18745 
              <description>Filter bits</description>
18746 
              <bitOffset>10</bitOffset>
18747 
              <bitWidth>1</bitWidth>
18748 
            </field>
18749 
            <field>
18750 
              <name>FB11</name>
18751 
              <description>Filter bits</description>
18752 
              <bitOffset>11</bitOffset>
18753 
              <bitWidth>1</bitWidth>
18754 
            </field>
18755 
            <field>
18756 
              <name>FB12</name>
18757 
              <description>Filter bits</description>
18758 
              <bitOffset>12</bitOffset>
18759 
              <bitWidth>1</bitWidth>
18760 
            </field>
18761 
            <field>
18762 
              <name>FB13</name>
18763 
              <description>Filter bits</description>
18764 
              <bitOffset>13</bitOffset>
18765 
              <bitWidth>1</bitWidth>
18766 
            </field>
18767 
            <field>
18768 
              <name>FB14</name>
18769 
              <description>Filter bits</description>
18770 
              <bitOffset>14</bitOffset>
18771 
              <bitWidth>1</bitWidth>
18772 
            </field>
18773 
            <field>
18774 
              <name>FB15</name>
18775 
              <description>Filter bits</description>
18776 
              <bitOffset>15</bitOffset>
18777 
              <bitWidth>1</bitWidth>
18778 
            </field>
18779 
            <field>
18780 
              <name>FB16</name>
18781 
              <description>Filter bits</description>
18782 
              <bitOffset>16</bitOffset>
18783 
              <bitWidth>1</bitWidth>
18784 
            </field>
18785 
            <field>
18786 
              <name>FB17</name>
18787 
              <description>Filter bits</description>
18788 
              <bitOffset>17</bitOffset>
18789 
              <bitWidth>1</bitWidth>
18790 
            </field>
18791 
            <field>
18792 
              <name>FB18</name>
18793 
              <description>Filter bits</description>
18794 
              <bitOffset>18</bitOffset>
18795 
              <bitWidth>1</bitWidth>
18796 
            </field>
18797 
            <field>
18798 
              <name>FB19</name>
18799 
              <description>Filter bits</description>
18800 
              <bitOffset>19</bitOffset>
18801 
              <bitWidth>1</bitWidth>
18802 
            </field>
18803 
            <field>
18804 
              <name>FB20</name>
18805 
              <description>Filter bits</description>
18806 
              <bitOffset>20</bitOffset>
18807 
              <bitWidth>1</bitWidth>
18808 
            </field>
18809 
            <field>
18810 
              <name>FB21</name>
18811 
              <description>Filter bits</description>
18812 
              <bitOffset>21</bitOffset>
18813 
              <bitWidth>1</bitWidth>
18814 
            </field>
18815 
            <field>
18816 
              <name>FB22</name>
18817 
              <description>Filter bits</description>
18818 
              <bitOffset>22</bitOffset>
18819 
              <bitWidth>1</bitWidth>
18820 
            </field>
18821 
            <field>
18822 
              <name>FB23</name>
18823 
              <description>Filter bits</description>
18824 
              <bitOffset>23</bitOffset>
18825 
              <bitWidth>1</bitWidth>
18826 
            </field>
18827 
            <field>
18828 
              <name>FB24</name>
18829 
              <description>Filter bits</description>
18830 
              <bitOffset>24</bitOffset>
18831 
              <bitWidth>1</bitWidth>
18832 
            </field>
18833 
            <field>
18834 
              <name>FB25</name>
18835 
              <description>Filter bits</description>
18836 
              <bitOffset>25</bitOffset>
18837 
              <bitWidth>1</bitWidth>
18838 
            </field>
18839 
            <field>
18840 
              <name>FB26</name>
18841 
              <description>Filter bits</description>
18842 
              <bitOffset>26</bitOffset>
18843 
              <bitWidth>1</bitWidth>
18844 
            </field>
18845 
            <field>
18846 
              <name>FB27</name>
18847 
              <description>Filter bits</description>
18848 
              <bitOffset>27</bitOffset>
18849 
              <bitWidth>1</bitWidth>
18850 
            </field>
18851 
            <field>
18852 
              <name>FB28</name>
18853 
              <description>Filter bits</description>
18854 
              <bitOffset>28</bitOffset>
18855 
              <bitWidth>1</bitWidth>
18856 
            </field>
18857 
            <field>
18858 
              <name>FB29</name>
18859 
              <description>Filter bits</description>
18860 
              <bitOffset>29</bitOffset>
18861 
              <bitWidth>1</bitWidth>
18862 
            </field>
18863 
            <field>
18864 
              <name>FB30</name>
18865 
              <description>Filter bits</description>
18866 
              <bitOffset>30</bitOffset>
18867 
              <bitWidth>1</bitWidth>
18868 
            </field>
18869 
            <field>
18870 
              <name>FB31</name>
18871 
              <description>Filter bits</description>
18872 
              <bitOffset>31</bitOffset>
18873 
              <bitWidth>1</bitWidth>
18874 
            </field>
18875 
          </fields>
18876 
        </register>
18877 
        <register>
18878 
          <name>F7R1</name>
18879 
          <displayName>F7R1</displayName>
18880 
          <description>Filter bank 7 register 1</description>
18881 
          <addressOffset>0x278</addressOffset>
18882 
          <size>0x20</size>
18883 
          <access>read-write</access>
18884 
          <resetValue>0x00000000</resetValue>
18885 
          <fields>
18886 
            <field>
18887 
              <name>FB0</name>
18888 
              <description>Filter bits</description>
18889 
              <bitOffset>0</bitOffset>
18890 
              <bitWidth>1</bitWidth>
18891 
            </field>
18892 
            <field>
18893 
              <name>FB1</name>
18894 
              <description>Filter bits</description>
18895 
              <bitOffset>1</bitOffset>
18896 
              <bitWidth>1</bitWidth>
18897 
            </field>
18898 
            <field>
18899 
              <name>FB2</name>
18900 
              <description>Filter bits</description>
18901 
              <bitOffset>2</bitOffset>
18902 
              <bitWidth>1</bitWidth>
18903 
            </field>
18904 
            <field>
18905 
              <name>FB3</name>
18906 
              <description>Filter bits</description>
18907 
              <bitOffset>3</bitOffset>
18908 
              <bitWidth>1</bitWidth>
18909 
            </field>
18910 
            <field>
18911 
              <name>FB4</name>
18912 
              <description>Filter bits</description>
18913 
              <bitOffset>4</bitOffset>
18914 
              <bitWidth>1</bitWidth>
18915 
            </field>
18916 
            <field>
18917 
              <name>FB5</name>
18918 
              <description>Filter bits</description>
18919 
              <bitOffset>5</bitOffset>
18920 
              <bitWidth>1</bitWidth>
18921 
            </field>
18922 
            <field>
18923 
              <name>FB6</name>
18924 
              <description>Filter bits</description>
18925 
              <bitOffset>6</bitOffset>
18926 
              <bitWidth>1</bitWidth>
18927 
            </field>
18928 
            <field>
18929 
              <name>FB7</name>
18930 
              <description>Filter bits</description>
18931 
              <bitOffset>7</bitOffset>
18932 
              <bitWidth>1</bitWidth>
18933 
            </field>
18934 
            <field>
18935 
              <name>FB8</name>
18936 
              <description>Filter bits</description>
18937 
              <bitOffset>8</bitOffset>
18938 
              <bitWidth>1</bitWidth>
18939 
            </field>
18940 
            <field>
18941 
              <name>FB9</name>
18942 
              <description>Filter bits</description>
18943 
              <bitOffset>9</bitOffset>
18944 
              <bitWidth>1</bitWidth>
18945 
            </field>
18946 
            <field>
18947 
              <name>FB10</name>
18948 
              <description>Filter bits</description>
18949 
              <bitOffset>10</bitOffset>
18950 
              <bitWidth>1</bitWidth>
18951 
            </field>
18952 
            <field>
18953 
              <name>FB11</name>
18954 
              <description>Filter bits</description>
18955 
              <bitOffset>11</bitOffset>
18956 
              <bitWidth>1</bitWidth>
18957 
            </field>
18958 
            <field>
18959 
              <name>FB12</name>
18960 
              <description>Filter bits</description>
18961 
              <bitOffset>12</bitOffset>
18962 
              <bitWidth>1</bitWidth>
18963 
            </field>
18964 
            <field>
18965 
              <name>FB13</name>
18966 
              <description>Filter bits</description>
18967 
              <bitOffset>13</bitOffset>
18968 
              <bitWidth>1</bitWidth>
18969 
            </field>
18970 
            <field>
18971 
              <name>FB14</name>
18972 
              <description>Filter bits</description>
18973 
              <bitOffset>14</bitOffset>
18974 
              <bitWidth>1</bitWidth>
18975 
            </field>
18976 
            <field>
18977 
              <name>FB15</name>
18978 
              <description>Filter bits</description>
18979 
              <bitOffset>15</bitOffset>
18980 
              <bitWidth>1</bitWidth>
18981 
            </field>
18982 
            <field>
18983 
              <name>FB16</name>
18984 
              <description>Filter bits</description>
18985 
              <bitOffset>16</bitOffset>
18986 
              <bitWidth>1</bitWidth>
18987 
            </field>
18988 
            <field>
18989 
              <name>FB17</name>
18990 
              <description>Filter bits</description>
18991 
              <bitOffset>17</bitOffset>
18992 
              <bitWidth>1</bitWidth>
18993 
            </field>
18994 
            <field>
18995 
              <name>FB18</name>
18996 
              <description>Filter bits</description>
18997 
              <bitOffset>18</bitOffset>
18998 
              <bitWidth>1</bitWidth>
18999 
            </field>
19000 
            <field>
19001 
              <name>FB19</name>
19002 
              <description>Filter bits</description>
19003 
              <bitOffset>19</bitOffset>
19004 
              <bitWidth>1</bitWidth>
19005 
            </field>
19006 
            <field>
19007 
              <name>FB20</name>
19008 
              <description>Filter bits</description>
19009 
              <bitOffset>20</bitOffset>
19010 
              <bitWidth>1</bitWidth>
19011 
            </field>
19012 
            <field>
19013 
              <name>FB21</name>
19014 
              <description>Filter bits</description>
19015 
              <bitOffset>21</bitOffset>
19016 
              <bitWidth>1</bitWidth>
19017 
            </field>
19018 
            <field>
19019 
              <name>FB22</name>
19020 
              <description>Filter bits</description>
19021 
              <bitOffset>22</bitOffset>
19022 
              <bitWidth>1</bitWidth>
19023 
            </field>
19024 
            <field>
19025 
              <name>FB23</name>
19026 
              <description>Filter bits</description>
19027 
              <bitOffset>23</bitOffset>
19028 
              <bitWidth>1</bitWidth>
19029 
            </field>
19030 
            <field>
19031 
              <name>FB24</name>
19032 
              <description>Filter bits</description>
19033 
              <bitOffset>24</bitOffset>
19034 
              <bitWidth>1</bitWidth>
19035 
            </field>
19036 
            <field>
19037 
              <name>FB25</name>
19038 
              <description>Filter bits</description>
19039 
              <bitOffset>25</bitOffset>
19040 
              <bitWidth>1</bitWidth>
19041 
            </field>
19042 
            <field>
19043 
              <name>FB26</name>
19044 
              <description>Filter bits</description>
19045 
              <bitOffset>26</bitOffset>
19046 
              <bitWidth>1</bitWidth>
19047 
            </field>
19048 
            <field>
19049 
              <name>FB27</name>
19050 
              <description>Filter bits</description>
19051 
              <bitOffset>27</bitOffset>
19052 
              <bitWidth>1</bitWidth>
19053 
            </field>
19054 
            <field>
19055 
              <name>FB28</name>
19056 
              <description>Filter bits</description>
19057 
              <bitOffset>28</bitOffset>
19058 
              <bitWidth>1</bitWidth>
19059 
            </field>
19060 
            <field>
19061 
              <name>FB29</name>
19062 
              <description>Filter bits</description>
19063 
              <bitOffset>29</bitOffset>
19064 
              <bitWidth>1</bitWidth>
19065 
            </field>
19066 
            <field>
19067 
              <name>FB30</name>
19068 
              <description>Filter bits</description>
19069 
              <bitOffset>30</bitOffset>
19070 
              <bitWidth>1</bitWidth>
19071 
            </field>
19072 
            <field>
19073 
              <name>FB31</name>
19074 
              <description>Filter bits</description>
19075 
              <bitOffset>31</bitOffset>
19076 
              <bitWidth>1</bitWidth>
19077 
            </field>
19078 
          </fields>
19079 
        </register>
19080 
        <register>
19081 
          <name>F7R2</name>
19082 
          <displayName>F7R2</displayName>
19083 
          <description>Filter bank 7 register 2</description>
19084 
          <addressOffset>0x27C</addressOffset>
19085 
          <size>0x20</size>
19086 
          <access>read-write</access>
19087 
          <resetValue>0x00000000</resetValue>
19088 
          <fields>
19089 
            <field>
19090 
              <name>FB0</name>
19091 
              <description>Filter bits</description>
19092 
              <bitOffset>0</bitOffset>
19093 
              <bitWidth>1</bitWidth>
19094 
            </field>
19095 
            <field>
19096 
              <name>FB1</name>
19097 
              <description>Filter bits</description>
19098 
              <bitOffset>1</bitOffset>
19099 
              <bitWidth>1</bitWidth>
19100 
            </field>
19101 
            <field>
19102 
              <name>FB2</name>
19103 
              <description>Filter bits</description>
19104 
              <bitOffset>2</bitOffset>
19105 
              <bitWidth>1</bitWidth>
19106 
            </field>
19107 
            <field>
19108 
              <name>FB3</name>
19109 
              <description>Filter bits</description>
19110 
              <bitOffset>3</bitOffset>
19111 
              <bitWidth>1</bitWidth>
19112 
            </field>
19113 
            <field>
19114 
              <name>FB4</name>
19115 
              <description>Filter bits</description>
19116 
              <bitOffset>4</bitOffset>
19117 
              <bitWidth>1</bitWidth>
19118 
            </field>
19119 
            <field>
19120 
              <name>FB5</name>
19121 
              <description>Filter bits</description>
19122 
              <bitOffset>5</bitOffset>
19123 
              <bitWidth>1</bitWidth>
19124 
            </field>
19125 
            <field>
19126 
              <name>FB6</name>
19127 
              <description>Filter bits</description>
19128 
              <bitOffset>6</bitOffset>
19129 
              <bitWidth>1</bitWidth>
19130 
            </field>
19131 
            <field>
19132 
              <name>FB7</name>
19133 
              <description>Filter bits</description>
19134 
              <bitOffset>7</bitOffset>
19135 
              <bitWidth>1</bitWidth>
19136 
            </field>
19137 
            <field>
19138 
              <name>FB8</name>
19139 
              <description>Filter bits</description>
19140 
              <bitOffset>8</bitOffset>
19141 
              <bitWidth>1</bitWidth>
19142 
            </field>
19143 
            <field>
19144 
              <name>FB9</name>
19145 
              <description>Filter bits</description>
19146 
              <bitOffset>9</bitOffset>
19147 
              <bitWidth>1</bitWidth>
19148 
            </field>
19149 
            <field>
19150 
              <name>FB10</name>
19151 
              <description>Filter bits</description>
19152 
              <bitOffset>10</bitOffset>
19153 
              <bitWidth>1</bitWidth>
19154 
            </field>
19155 
            <field>
19156 
              <name>FB11</name>
19157 
              <description>Filter bits</description>
19158 
              <bitOffset>11</bitOffset>
19159 
              <bitWidth>1</bitWidth>
19160 
            </field>
19161 
            <field>
19162 
              <name>FB12</name>
19163 
              <description>Filter bits</description>
19164 
              <bitOffset>12</bitOffset>
19165 
              <bitWidth>1</bitWidth>
19166 
            </field>
19167 
            <field>
19168 
              <name>FB13</name>
19169 
              <description>Filter bits</description>
19170 
              <bitOffset>13</bitOffset>
19171 
              <bitWidth>1</bitWidth>
19172 
            </field>
19173 
            <field>
19174 
              <name>FB14</name>
19175 
              <description>Filter bits</description>
19176 
              <bitOffset>14</bitOffset>
19177 
              <bitWidth>1</bitWidth>
19178 
            </field>
19179 
            <field>
19180 
              <name>FB15</name>
19181 
              <description>Filter bits</description>
19182 
              <bitOffset>15</bitOffset>
19183 
              <bitWidth>1</bitWidth>
19184 
            </field>
19185 
            <field>
19186 
              <name>FB16</name>
19187 
              <description>Filter bits</description>
19188 
              <bitOffset>16</bitOffset>
19189 
              <bitWidth>1</bitWidth>
19190 
            </field>
19191 
            <field>
19192 
              <name>FB17</name>
19193 
              <description>Filter bits</description>
19194 
              <bitOffset>17</bitOffset>
19195 
              <bitWidth>1</bitWidth>
19196 
            </field>
19197 
            <field>
19198 
              <name>FB18</name>
19199 
              <description>Filter bits</description>
19200 
              <bitOffset>18</bitOffset>
19201 
              <bitWidth>1</bitWidth>
19202 
            </field>
19203 
            <field>
19204 
              <name>FB19</name>
19205 
              <description>Filter bits</description>
19206 
              <bitOffset>19</bitOffset>
19207 
              <bitWidth>1</bitWidth>
19208 
            </field>
19209 
            <field>
19210 
              <name>FB20</name>
19211 
              <description>Filter bits</description>
19212 
              <bitOffset>20</bitOffset>
19213 
              <bitWidth>1</bitWidth>
19214 
            </field>
19215 
            <field>
19216 
              <name>FB21</name>
19217 
              <description>Filter bits</description>
19218 
              <bitOffset>21</bitOffset>
19219 
              <bitWidth>1</bitWidth>
19220 
            </field>
19221 
            <field>
19222 
              <name>FB22</name>
19223 
              <description>Filter bits</description>
19224 
              <bitOffset>22</bitOffset>
19225 
              <bitWidth>1</bitWidth>
19226 
            </field>
19227 
            <field>
19228 
              <name>FB23</name>
19229 
              <description>Filter bits</description>
19230 
              <bitOffset>23</bitOffset>
19231 
              <bitWidth>1</bitWidth>
19232 
            </field>
19233 
            <field>
19234 
              <name>FB24</name>
19235 
              <description>Filter bits</description>
19236 
              <bitOffset>24</bitOffset>
19237 
              <bitWidth>1</bitWidth>
19238 
            </field>
19239 
            <field>
19240 
              <name>FB25</name>
19241 
              <description>Filter bits</description>
19242 
              <bitOffset>25</bitOffset>
19243 
              <bitWidth>1</bitWidth>
19244 
            </field>
19245 
            <field>
19246 
              <name>FB26</name>
19247 
              <description>Filter bits</description>
19248 
              <bitOffset>26</bitOffset>
19249 
              <bitWidth>1</bitWidth>
19250 
            </field>
19251 
            <field>
19252 
              <name>FB27</name>
19253 
              <description>Filter bits</description>
19254 
              <bitOffset>27</bitOffset>
19255 
              <bitWidth>1</bitWidth>
19256 
            </field>
19257 
            <field>
19258 
              <name>FB28</name>
19259 
              <description>Filter bits</description>
19260 
              <bitOffset>28</bitOffset>
19261 
              <bitWidth>1</bitWidth>
19262 
            </field>
19263 
            <field>
19264 
              <name>FB29</name>
19265 
              <description>Filter bits</description>
19266 
              <bitOffset>29</bitOffset>
19267 
              <bitWidth>1</bitWidth>
19268 
            </field>
19269 
            <field>
19270 
              <name>FB30</name>
19271 
              <description>Filter bits</description>
19272 
              <bitOffset>30</bitOffset>
19273 
              <bitWidth>1</bitWidth>
19274 
            </field>
19275 
            <field>
19276 
              <name>FB31</name>
19277 
              <description>Filter bits</description>
19278 
              <bitOffset>31</bitOffset>
19279 
              <bitWidth>1</bitWidth>
19280 
            </field>
19281 
          </fields>
19282 
        </register>
19283 
        <register>
19284 
          <name>F8R1</name>
19285 
          <displayName>F8R1</displayName>
19286 
          <description>Filter bank 8 register 1</description>
19287 
          <addressOffset>0x280</addressOffset>
19288 
          <size>0x20</size>
19289 
          <access>read-write</access>
19290 
          <resetValue>0x00000000</resetValue>
19291 
          <fields>
19292 
            <field>
19293 
              <name>FB0</name>
19294 
              <description>Filter bits</description>
19295 
              <bitOffset>0</bitOffset>
19296 
              <bitWidth>1</bitWidth>
19297 
            </field>
19298 
            <field>
19299 
              <name>FB1</name>
19300 
              <description>Filter bits</description>
19301 
              <bitOffset>1</bitOffset>
19302 
              <bitWidth>1</bitWidth>
19303 
            </field>
19304 
            <field>
19305 
              <name>FB2</name>
19306 
              <description>Filter bits</description>
19307 
              <bitOffset>2</bitOffset>
19308 
              <bitWidth>1</bitWidth>
19309 
            </field>
19310 
            <field>
19311 
              <name>FB3</name>
19312 
              <description>Filter bits</description>
19313 
              <bitOffset>3</bitOffset>
19314 
              <bitWidth>1</bitWidth>
19315 
            </field>
19316 
            <field>
19317 
              <name>FB4</name>
19318 
              <description>Filter bits</description>
19319 
              <bitOffset>4</bitOffset>
19320 
              <bitWidth>1</bitWidth>
19321 
            </field>
19322 
            <field>
19323 
              <name>FB5</name>
19324 
              <description>Filter bits</description>
19325 
              <bitOffset>5</bitOffset>
19326 
              <bitWidth>1</bitWidth>
19327 
            </field>
19328 
            <field>
19329 
              <name>FB6</name>
19330 
              <description>Filter bits</description>
19331 
              <bitOffset>6</bitOffset>
19332 
              <bitWidth>1</bitWidth>
19333 
            </field>
19334 
            <field>
19335 
              <name>FB7</name>
19336 
              <description>Filter bits</description>
19337 
              <bitOffset>7</bitOffset>
19338 
              <bitWidth>1</bitWidth>
19339 
            </field>
19340 
            <field>
19341 
              <name>FB8</name>
19342 
              <description>Filter bits</description>
19343 
              <bitOffset>8</bitOffset>
19344 
              <bitWidth>1</bitWidth>
19345 
            </field>
19346 
            <field>
19347 
              <name>FB9</name>
19348 
              <description>Filter bits</description>
19349 
              <bitOffset>9</bitOffset>
19350 
              <bitWidth>1</bitWidth>
19351 
            </field>
19352 
            <field>
19353 
              <name>FB10</name>
19354 
              <description>Filter bits</description>
19355 
              <bitOffset>10</bitOffset>
19356 
              <bitWidth>1</bitWidth>
19357 
            </field>
19358 
            <field>
19359 
              <name>FB11</name>
19360 
              <description>Filter bits</description>
19361 
              <bitOffset>11</bitOffset>
19362 
              <bitWidth>1</bitWidth>
19363 
            </field>
19364 
            <field>
19365 
              <name>FB12</name>
19366 
              <description>Filter bits</description>
19367 
              <bitOffset>12</bitOffset>
19368 
              <bitWidth>1</bitWidth>
19369 
            </field>
19370 
            <field>
19371 
              <name>FB13</name>
19372 
              <description>Filter bits</description>
19373 
              <bitOffset>13</bitOffset>
19374 
              <bitWidth>1</bitWidth>
19375 
            </field>
19376 
            <field>
19377 
              <name>FB14</name>
19378 
              <description>Filter bits</description>
19379 
              <bitOffset>14</bitOffset>
19380 
              <bitWidth>1</bitWidth>
19381 
            </field>
19382 
            <field>
19383 
              <name>FB15</name>
19384 
              <description>Filter bits</description>
19385 
              <bitOffset>15</bitOffset>
19386 
              <bitWidth>1</bitWidth>
19387 
            </field>
19388 
            <field>
19389 
              <name>FB16</name>
19390 
              <description>Filter bits</description>
19391 
              <bitOffset>16</bitOffset>
19392 
              <bitWidth>1</bitWidth>
19393 
            </field>
19394 
            <field>
19395 
              <name>FB17</name>
19396 
              <description>Filter bits</description>
19397 
              <bitOffset>17</bitOffset>
19398 
              <bitWidth>1</bitWidth>
19399 
            </field>
19400 
            <field>
19401 
              <name>FB18</name>
19402 
              <description>Filter bits</description>
19403 
              <bitOffset>18</bitOffset>
19404 
              <bitWidth>1</bitWidth>
19405 
            </field>
19406 
            <field>
19407 
              <name>FB19</name>
19408 
              <description>Filter bits</description>
19409 
              <bitOffset>19</bitOffset>
19410 
              <bitWidth>1</bitWidth>
19411 
            </field>
19412 
            <field>
19413 
              <name>FB20</name>
19414 
              <description>Filter bits</description>
19415 
              <bitOffset>20</bitOffset>
19416 
              <bitWidth>1</bitWidth>
19417 
            </field>
19418 
            <field>
19419 
              <name>FB21</name>
19420 
              <description>Filter bits</description>
19421 
              <bitOffset>21</bitOffset>
19422 
              <bitWidth>1</bitWidth>
19423 
            </field>
19424 
            <field>
19425 
              <name>FB22</name>
19426 
              <description>Filter bits</description>
19427 
              <bitOffset>22</bitOffset>
19428 
              <bitWidth>1</bitWidth>
19429 
            </field>
19430 
            <field>
19431 
              <name>FB23</name>
19432 
              <description>Filter bits</description>
19433 
              <bitOffset>23</bitOffset>
19434 
              <bitWidth>1</bitWidth>
19435 
            </field>
19436 
            <field>
19437 
              <name>FB24</name>
19438 
              <description>Filter bits</description>
19439 
              <bitOffset>24</bitOffset>
19440 
              <bitWidth>1</bitWidth>
19441 
            </field>
19442 
            <field>
19443 
              <name>FB25</name>
19444 
              <description>Filter bits</description>
19445 
              <bitOffset>25</bitOffset>
19446 
              <bitWidth>1</bitWidth>
19447 
            </field>
19448 
            <field>
19449 
              <name>FB26</name>
19450 
              <description>Filter bits</description>
19451 
              <bitOffset>26</bitOffset>
19452 
              <bitWidth>1</bitWidth>
19453 
            </field>
19454 
            <field>
19455 
              <name>FB27</name>
19456 
              <description>Filter bits</description>
19457 
              <bitOffset>27</bitOffset>
19458 
              <bitWidth>1</bitWidth>
19459 
            </field>
19460 
            <field>
19461 
              <name>FB28</name>
19462 
              <description>Filter bits</description>
19463 
              <bitOffset>28</bitOffset>
19464 
              <bitWidth>1</bitWidth>
19465 
            </field>
19466 
            <field>
19467 
              <name>FB29</name>
19468 
              <description>Filter bits</description>
19469 
              <bitOffset>29</bitOffset>
19470 
              <bitWidth>1</bitWidth>
19471 
            </field>
19472 
            <field>
19473 
              <name>FB30</name>
19474 
              <description>Filter bits</description>
19475 
              <bitOffset>30</bitOffset>
19476 
              <bitWidth>1</bitWidth>
19477 
            </field>
19478 
            <field>
19479 
              <name>FB31</name>
19480 
              <description>Filter bits</description>
19481 
              <bitOffset>31</bitOffset>
19482 
              <bitWidth>1</bitWidth>
19483 
            </field>
19484 
          </fields>
19485 
        </register>
19486 
        <register>
19487 
          <name>F8R2</name>
19488 
          <displayName>F8R2</displayName>
19489 
          <description>Filter bank 8 register 2</description>
19490 
          <addressOffset>0x284</addressOffset>
19491 
          <size>0x20</size>
19492 
          <access>read-write</access>
19493 
          <resetValue>0x00000000</resetValue>
19494 
          <fields>
19495 
            <field>
19496 
              <name>FB0</name>
19497 
              <description>Filter bits</description>
19498 
              <bitOffset>0</bitOffset>
19499 
              <bitWidth>1</bitWidth>
19500 
            </field>
19501 
            <field>
19502 
              <name>FB1</name>
19503 
              <description>Filter bits</description>
19504 
              <bitOffset>1</bitOffset>
19505 
              <bitWidth>1</bitWidth>
19506 
            </field>
19507 
            <field>
19508 
              <name>FB2</name>
19509 
              <description>Filter bits</description>
19510 
              <bitOffset>2</bitOffset>
19511 
              <bitWidth>1</bitWidth>
19512 
            </field>
19513 
            <field>
19514 
              <name>FB3</name>
19515 
              <description>Filter bits</description>
19516 
              <bitOffset>3</bitOffset>
19517 
              <bitWidth>1</bitWidth>
19518 
            </field>
19519 
            <field>
19520 
              <name>FB4</name>
19521 
              <description>Filter bits</description>
19522 
              <bitOffset>4</bitOffset>
19523 
              <bitWidth>1</bitWidth>
19524 
            </field>
19525 
            <field>
19526 
              <name>FB5</name>
19527 
              <description>Filter bits</description>
19528 
              <bitOffset>5</bitOffset>
19529 
              <bitWidth>1</bitWidth>
19530 
            </field>
19531 
            <field>
19532 
              <name>FB6</name>
19533 
              <description>Filter bits</description>
19534 
              <bitOffset>6</bitOffset>
19535 
              <bitWidth>1</bitWidth>
19536 
            </field>
19537 
            <field>
19538 
              <name>FB7</name>
19539 
              <description>Filter bits</description>
19540 
              <bitOffset>7</bitOffset>
19541 
              <bitWidth>1</bitWidth>
19542 
            </field>
19543 
            <field>
19544 
              <name>FB8</name>
19545 
              <description>Filter bits</description>
19546 
              <bitOffset>8</bitOffset>
19547 
              <bitWidth>1</bitWidth>
19548 
            </field>
19549 
            <field>
19550 
              <name>FB9</name>
19551 
              <description>Filter bits</description>
19552 
              <bitOffset>9</bitOffset>
19553 
              <bitWidth>1</bitWidth>
19554 
            </field>
19555 
            <field>
19556 
              <name>FB10</name>
19557 
              <description>Filter bits</description>
19558 
              <bitOffset>10</bitOffset>
19559 
              <bitWidth>1</bitWidth>
19560 
            </field>
19561 
            <field>
19562 
              <name>FB11</name>
19563 
              <description>Filter bits</description>
19564 
              <bitOffset>11</bitOffset>
19565 
              <bitWidth>1</bitWidth>
19566 
            </field>
19567 
            <field>
19568 
              <name>FB12</name>
19569 
              <description>Filter bits</description>
19570 
              <bitOffset>12</bitOffset>
19571 
              <bitWidth>1</bitWidth>
19572 
            </field>
19573 
            <field>
19574 
              <name>FB13</name>
19575 
              <description>Filter bits</description>
19576 
              <bitOffset>13</bitOffset>
19577 
              <bitWidth>1</bitWidth>
19578 
            </field>
19579 
            <field>
19580 
              <name>FB14</name>
19581 
              <description>Filter bits</description>
19582 
              <bitOffset>14</bitOffset>
19583 
              <bitWidth>1</bitWidth>
19584 
            </field>
19585 
            <field>
19586 
              <name>FB15</name>
19587 
              <description>Filter bits</description>
19588 
              <bitOffset>15</bitOffset>
19589 
              <bitWidth>1</bitWidth>
19590 
            </field>
19591 
            <field>
19592 
              <name>FB16</name>
19593 
              <description>Filter bits</description>
19594 
              <bitOffset>16</bitOffset>
19595 
              <bitWidth>1</bitWidth>
19596 
            </field>
19597 
            <field>
19598 
              <name>FB17</name>
19599 
              <description>Filter bits</description>
19600 
              <bitOffset>17</bitOffset>
19601 
              <bitWidth>1</bitWidth>
19602 
            </field>
19603 
            <field>
19604 
              <name>FB18</name>
19605 
              <description>Filter bits</description>
19606 
              <bitOffset>18</bitOffset>
19607 
              <bitWidth>1</bitWidth>
19608 
            </field>
19609 
            <field>
19610 
              <name>FB19</name>
19611 
              <description>Filter bits</description>
19612 
              <bitOffset>19</bitOffset>
19613 
              <bitWidth>1</bitWidth>
19614 
            </field>
19615 
            <field>
19616 
              <name>FB20</name>
19617 
              <description>Filter bits</description>
19618 
              <bitOffset>20</bitOffset>
19619 
              <bitWidth>1</bitWidth>
19620 
            </field>
19621 
            <field>
19622 
              <name>FB21</name>
19623 
              <description>Filter bits</description>
19624 
              <bitOffset>21</bitOffset>
19625 
              <bitWidth>1</bitWidth>
19626 
            </field>
19627 
            <field>
19628 
              <name>FB22</name>
19629 
              <description>Filter bits</description>
19630 
              <bitOffset>22</bitOffset>
19631 
              <bitWidth>1</bitWidth>
19632 
            </field>
19633 
            <field>
19634 
              <name>FB23</name>
19635 
              <description>Filter bits</description>
19636 
              <bitOffset>23</bitOffset>
19637 
              <bitWidth>1</bitWidth>
19638 
            </field>
19639 
            <field>
19640 
              <name>FB24</name>
19641 
              <description>Filter bits</description>
19642 
              <bitOffset>24</bitOffset>
19643 
              <bitWidth>1</bitWidth>
19644 
            </field>
19645 
            <field>
19646 
              <name>FB25</name>
19647 
              <description>Filter bits</description>
19648 
              <bitOffset>25</bitOffset>
19649 
              <bitWidth>1</bitWidth>
19650 
            </field>
19651 
            <field>
19652 
              <name>FB26</name>
19653 
              <description>Filter bits</description>
19654 
              <bitOffset>26</bitOffset>
19655 
              <bitWidth>1</bitWidth>
19656 
            </field>
19657 
            <field>
19658 
              <name>FB27</name>
19659 
              <description>Filter bits</description>
19660 
              <bitOffset>27</bitOffset>
19661 
              <bitWidth>1</bitWidth>
19662 
            </field>
19663 
            <field>
19664 
              <name>FB28</name>
19665 
              <description>Filter bits</description>
19666 
              <bitOffset>28</bitOffset>
19667 
              <bitWidth>1</bitWidth>
19668 
            </field>
19669 
            <field>
19670 
              <name>FB29</name>
19671 
              <description>Filter bits</description>
19672 
              <bitOffset>29</bitOffset>
19673 
              <bitWidth>1</bitWidth>
19674 
            </field>
19675 
            <field>
19676 
              <name>FB30</name>
19677 
              <description>Filter bits</description>
19678 
              <bitOffset>30</bitOffset>
19679 
              <bitWidth>1</bitWidth>
19680 
            </field>
19681 
            <field>
19682 
              <name>FB31</name>
19683 
              <description>Filter bits</description>
19684 
              <bitOffset>31</bitOffset>
19685 
              <bitWidth>1</bitWidth>
19686 
            </field>
19687 
          </fields>
19688 
        </register>
19689 
        <register>
19690 
          <name>F9R1</name>
19691 
          <displayName>F9R1</displayName>
19692 
          <description>Filter bank 9 register 1</description>
19693 
          <addressOffset>0x288</addressOffset>
19694 
          <size>0x20</size>
19695 
          <access>read-write</access>
19696 
          <resetValue>0x00000000</resetValue>
19697 
          <fields>
19698 
            <field>
19699 
              <name>FB0</name>
19700 
              <description>Filter bits</description>
19701 
              <bitOffset>0</bitOffset>
19702 
              <bitWidth>1</bitWidth>
19703 
            </field>
19704 
            <field>
19705 
              <name>FB1</name>
19706 
              <description>Filter bits</description>
19707 
              <bitOffset>1</bitOffset>
19708 
              <bitWidth>1</bitWidth>
19709 
            </field>
19710 
            <field>
19711 
              <name>FB2</name>
19712 
              <description>Filter bits</description>
19713 
              <bitOffset>2</bitOffset>
19714 
              <bitWidth>1</bitWidth>
19715 
            </field>
19716 
            <field>
19717 
              <name>FB3</name>
19718 
              <description>Filter bits</description>
19719 
              <bitOffset>3</bitOffset>
19720 
              <bitWidth>1</bitWidth>
19721 
            </field>
19722 
            <field>
19723 
              <name>FB4</name>
19724 
              <description>Filter bits</description>
19725 
              <bitOffset>4</bitOffset>
19726 
              <bitWidth>1</bitWidth>
19727 
            </field>
19728 
            <field>
19729 
              <name>FB5</name>
19730 
              <description>Filter bits</description>
19731 
              <bitOffset>5</bitOffset>
19732 
              <bitWidth>1</bitWidth>
19733 
            </field>
19734 
            <field>
19735 
              <name>FB6</name>
19736 
              <description>Filter bits</description>
19737 
              <bitOffset>6</bitOffset>
19738 
              <bitWidth>1</bitWidth>
19739 
            </field>
19740 
            <field>
19741 
              <name>FB7</name>
19742 
              <description>Filter bits</description>
19743 
              <bitOffset>7</bitOffset>
19744 
              <bitWidth>1</bitWidth>
19745 
            </field>
19746 
            <field>
19747 
              <name>FB8</name>
19748 
              <description>Filter bits</description>
19749 
              <bitOffset>8</bitOffset>
19750 
              <bitWidth>1</bitWidth>
19751 
            </field>
19752 
            <field>
19753 
              <name>FB9</name>
19754 
              <description>Filter bits</description>
19755 
              <bitOffset>9</bitOffset>
19756 
              <bitWidth>1</bitWidth>
19757 
            </field>
19758 
            <field>
19759 
              <name>FB10</name>
19760 
              <description>Filter bits</description>
19761 
              <bitOffset>10</bitOffset>
19762 
              <bitWidth>1</bitWidth>
19763 
            </field>
19764 
            <field>
19765 
              <name>FB11</name>
19766 
              <description>Filter bits</description>
19767 
              <bitOffset>11</bitOffset>
19768 
              <bitWidth>1</bitWidth>
19769 
            </field>
19770 
            <field>
19771 
              <name>FB12</name>
19772 
              <description>Filter bits</description>
19773 
              <bitOffset>12</bitOffset>
19774 
              <bitWidth>1</bitWidth>
19775 
            </field>
19776 
            <field>
19777 
              <name>FB13</name>
19778 
              <description>Filter bits</description>
19779 
              <bitOffset>13</bitOffset>
19780 
              <bitWidth>1</bitWidth>
19781 
            </field>
19782 
            <field>
19783 
              <name>FB14</name>
19784 
              <description>Filter bits</description>
19785 
              <bitOffset>14</bitOffset>
19786 
              <bitWidth>1</bitWidth>
19787 
            </field>
19788 
            <field>
19789 
              <name>FB15</name>
19790 
              <description>Filter bits</description>
19791 
              <bitOffset>15</bitOffset>
19792 
              <bitWidth>1</bitWidth>
19793 
            </field>
19794 
            <field>
19795 
              <name>FB16</name>
19796 
              <description>Filter bits</description>
19797 
              <bitOffset>16</bitOffset>
19798 
              <bitWidth>1</bitWidth>
19799 
            </field>
19800 
            <field>
19801 
              <name>FB17</name>
19802 
              <description>Filter bits</description>
19803 
              <bitOffset>17</bitOffset>
19804 
              <bitWidth>1</bitWidth>
19805 
            </field>
19806 
            <field>
19807 
              <name>FB18</name>
19808 
              <description>Filter bits</description>
19809 
              <bitOffset>18</bitOffset>
19810 
              <bitWidth>1</bitWidth>
19811 
            </field>
19812 
            <field>
19813 
              <name>FB19</name>
19814 
              <description>Filter bits</description>
19815 
              <bitOffset>19</bitOffset>
19816 
              <bitWidth>1</bitWidth>
19817 
            </field>
19818 
            <field>
19819 
              <name>FB20</name>
19820 
              <description>Filter bits</description>
19821 
              <bitOffset>20</bitOffset>
19822 
              <bitWidth>1</bitWidth>
19823 
            </field>
19824 
            <field>
19825 
              <name>FB21</name>
19826 
              <description>Filter bits</description>
19827 
              <bitOffset>21</bitOffset>
19828 
              <bitWidth>1</bitWidth>
19829 
            </field>
19830 
            <field>
19831 
              <name>FB22</name>
19832 
              <description>Filter bits</description>
19833 
              <bitOffset>22</bitOffset>
19834 
              <bitWidth>1</bitWidth>
19835 
            </field>
19836 
            <field>
19837 
              <name>FB23</name>
19838 
              <description>Filter bits</description>
19839 
              <bitOffset>23</bitOffset>
19840 
              <bitWidth>1</bitWidth>
19841 
            </field>
19842 
            <field>
19843 
              <name>FB24</name>
19844 
              <description>Filter bits</description>
19845 
              <bitOffset>24</bitOffset>
19846 
              <bitWidth>1</bitWidth>
19847 
            </field>
19848 
            <field>
19849 
              <name>FB25</name>
19850 
              <description>Filter bits</description>
19851 
              <bitOffset>25</bitOffset>
19852 
              <bitWidth>1</bitWidth>
19853 
            </field>
19854 
            <field>
19855 
              <name>FB26</name>
19856 
              <description>Filter bits</description>
19857 
              <bitOffset>26</bitOffset>
19858 
              <bitWidth>1</bitWidth>
19859 
            </field>
19860 
            <field>
19861 
              <name>FB27</name>
19862 
              <description>Filter bits</description>
19863 
              <bitOffset>27</bitOffset>
19864 
              <bitWidth>1</bitWidth>
19865 
            </field>
19866 
            <field>
19867 
              <name>FB28</name>
19868 
              <description>Filter bits</description>
19869 
              <bitOffset>28</bitOffset>
19870 
              <bitWidth>1</bitWidth>
19871 
            </field>
19872 
            <field>
19873 
              <name>FB29</name>
19874 
              <description>Filter bits</description>
19875 
              <bitOffset>29</bitOffset>
19876 
              <bitWidth>1</bitWidth>
19877 
            </field>
19878 
            <field>
19879 
              <name>FB30</name>
19880 
              <description>Filter bits</description>
19881 
              <bitOffset>30</bitOffset>
19882 
              <bitWidth>1</bitWidth>
19883 
            </field>
19884 
            <field>
19885 
              <name>FB31</name>
19886 
              <description>Filter bits</description>
19887 
              <bitOffset>31</bitOffset>
19888 
              <bitWidth>1</bitWidth>
19889 
            </field>
19890 
          </fields>
19891 
        </register>
19892 
        <register>
19893 
          <name>F9R2</name>
19894 
          <displayName>F9R2</displayName>
19895 
          <description>Filter bank 9 register 2</description>
19896 
          <addressOffset>0x28C</addressOffset>
19897 
          <size>0x20</size>
19898 
          <access>read-write</access>
19899 
          <resetValue>0x00000000</resetValue>
19900 
          <fields>
19901 
            <field>
19902 
              <name>FB0</name>
19903 
              <description>Filter bits</description>
19904 
              <bitOffset>0</bitOffset>
19905 
              <bitWidth>1</bitWidth>
19906 
            </field>
19907 
            <field>
19908 
              <name>FB1</name>
19909 
              <description>Filter bits</description>
19910 
              <bitOffset>1</bitOffset>
19911 
              <bitWidth>1</bitWidth>
19912 
            </field>
19913 
            <field>
19914 
              <name>FB2</name>
19915 
              <description>Filter bits</description>
19916 
              <bitOffset>2</bitOffset>
19917 
              <bitWidth>1</bitWidth>
19918 
            </field>
19919 
            <field>
19920 
              <name>FB3</name>
19921 
              <description>Filter bits</description>
19922 
              <bitOffset>3</bitOffset>
19923 
              <bitWidth>1</bitWidth>
19924 
            </field>
19925 
            <field>
19926 
              <name>FB4</name>
19927 
              <description>Filter bits</description>
19928 
              <bitOffset>4</bitOffset>
19929 
              <bitWidth>1</bitWidth>
19930 
            </field>
19931 
            <field>
19932 
              <name>FB5</name>
19933 
              <description>Filter bits</description>
19934 
              <bitOffset>5</bitOffset>
19935 
              <bitWidth>1</bitWidth>
19936 
            </field>
19937 
            <field>
19938 
              <name>FB6</name>
19939 
              <description>Filter bits</description>
19940 
              <bitOffset>6</bitOffset>
19941 
              <bitWidth>1</bitWidth>
19942 
            </field>
19943 
            <field>
19944 
              <name>FB7</name>
19945 
              <description>Filter bits</description>
19946 
              <bitOffset>7</bitOffset>
19947 
              <bitWidth>1</bitWidth>
19948 
            </field>
19949 
            <field>
19950 
              <name>FB8</name>
19951 
              <description>Filter bits</description>
19952 
              <bitOffset>8</bitOffset>
19953 
              <bitWidth>1</bitWidth>
19954 
            </field>
19955 
            <field>
19956 
              <name>FB9</name>
19957 
              <description>Filter bits</description>
19958 
              <bitOffset>9</bitOffset>
19959 
              <bitWidth>1</bitWidth>
19960 
            </field>
19961 
            <field>
19962 
              <name>FB10</name>
19963 
              <description>Filter bits</description>
19964 
              <bitOffset>10</bitOffset>
19965 
              <bitWidth>1</bitWidth>
19966 
            </field>
19967 
            <field>
19968 
              <name>FB11</name>
19969 
              <description>Filter bits</description>
19970 
              <bitOffset>11</bitOffset>
19971 
              <bitWidth>1</bitWidth>
19972 
            </field>
19973 
            <field>
19974 
              <name>FB12</name>
19975 
              <description>Filter bits</description>
19976 
              <bitOffset>12</bitOffset>
19977 
              <bitWidth>1</bitWidth>
19978 
            </field>
19979 
            <field>
19980 
              <name>FB13</name>
19981 
              <description>Filter bits</description>
19982 
              <bitOffset>13</bitOffset>
19983 
              <bitWidth>1</bitWidth>
19984 
            </field>
19985 
            <field>
19986 
              <name>FB14</name>
19987 
              <description>Filter bits</description>
19988 
              <bitOffset>14</bitOffset>
19989 
              <bitWidth>1</bitWidth>
19990 
            </field>
19991 
            <field>
19992 
              <name>FB15</name>
19993 
              <description>Filter bits</description>
19994 
              <bitOffset>15</bitOffset>
19995 
              <bitWidth>1</bitWidth>
19996 
            </field>
19997 
            <field>
19998 
              <name>FB16</name>
19999 
              <description>Filter bits</description>
20000 
              <bitOffset>16</bitOffset>
20001 
              <bitWidth>1</bitWidth>
20002 
            </field>
20003 
            <field>
20004 
              <name>FB17</name>
20005 
              <description>Filter bits</description>
20006 
              <bitOffset>17</bitOffset>
20007 
              <bitWidth>1</bitWidth>
20008 
            </field>
20009 
            <field>
20010 
              <name>FB18</name>
20011 
              <description>Filter bits</description>
20012 
              <bitOffset>18</bitOffset>
20013 
              <bitWidth>1</bitWidth>
20014 
            </field>
20015 
            <field>
20016 
              <name>FB19</name>
20017 
              <description>Filter bits</description>
20018 
              <bitOffset>19</bitOffset>
20019 
              <bitWidth>1</bitWidth>
20020 
            </field>
20021 
            <field>
20022 
              <name>FB20</name>
20023 
              <description>Filter bits</description>
20024 
              <bitOffset>20</bitOffset>
20025 
              <bitWidth>1</bitWidth>
20026 
            </field>
20027 
            <field>
20028 
              <name>FB21</name>
20029 
              <description>Filter bits</description>
20030 
              <bitOffset>21</bitOffset>
20031 
              <bitWidth>1</bitWidth>
20032 
            </field>
20033 
            <field>
20034 
              <name>FB22</name>
20035 
              <description>Filter bits</description>
20036 
              <bitOffset>22</bitOffset>
20037 
              <bitWidth>1</bitWidth>
20038 
            </field>
20039 
            <field>
20040 
              <name>FB23</name>
20041 
              <description>Filter bits</description>
20042 
              <bitOffset>23</bitOffset>
20043 
              <bitWidth>1</bitWidth>
20044 
            </field>
20045 
            <field>
20046 
              <name>FB24</name>
20047 
              <description>Filter bits</description>
20048 
              <bitOffset>24</bitOffset>
20049 
              <bitWidth>1</bitWidth>
20050 
            </field>
20051 
            <field>
20052 
              <name>FB25</name>
20053 
              <description>Filter bits</description>
20054 
              <bitOffset>25</bitOffset>
20055 
              <bitWidth>1</bitWidth>
20056 
            </field>
20057 
            <field>
20058 
              <name>FB26</name>
20059 
              <description>Filter bits</description>
20060 
              <bitOffset>26</bitOffset>
20061 
              <bitWidth>1</bitWidth>
20062 
            </field>
20063 
            <field>
20064 
              <name>FB27</name>
20065 
              <description>Filter bits</description>
20066 
              <bitOffset>27</bitOffset>
20067 
              <bitWidth>1</bitWidth>
20068 
            </field>
20069 
            <field>
20070 
              <name>FB28</name>
20071 
              <description>Filter bits</description>
20072 
              <bitOffset>28</bitOffset>
20073 
              <bitWidth>1</bitWidth>
20074 
            </field>
20075 
            <field>
20076 
              <name>FB29</name>
20077 
              <description>Filter bits</description>
20078 
              <bitOffset>29</bitOffset>
20079 
              <bitWidth>1</bitWidth>
20080 
            </field>
20081 
            <field>
20082 
              <name>FB30</name>
20083 
              <description>Filter bits</description>
20084 
              <bitOffset>30</bitOffset>
20085 
              <bitWidth>1</bitWidth>
20086 
            </field>
20087 
            <field>
20088 
              <name>FB31</name>
20089 
              <description>Filter bits</description>
20090 
              <bitOffset>31</bitOffset>
20091 
              <bitWidth>1</bitWidth>
20092 
            </field>
20093 
          </fields>
20094 
        </register>
20095 
        <register>
20096 
          <name>F10R1</name>
20097 
          <displayName>F10R1</displayName>
20098 
          <description>Filter bank 10 register 1</description>
20099 
          <addressOffset>0x290</addressOffset>
20100 
          <size>0x20</size>
20101 
          <access>read-write</access>
20102 
          <resetValue>0x00000000</resetValue>
20103 
          <fields>
20104 
            <field>
20105 
              <name>FB0</name>
20106 
              <description>Filter bits</description>
20107 
              <bitOffset>0</bitOffset>
20108 
              <bitWidth>1</bitWidth>
20109 
            </field>
20110 
            <field>
20111 
              <name>FB1</name>
20112 
              <description>Filter bits</description>
20113 
              <bitOffset>1</bitOffset>
20114 
              <bitWidth>1</bitWidth>
20115 
            </field>
20116 
            <field>
20117 
              <name>FB2</name>
20118 
              <description>Filter bits</description>
20119 
              <bitOffset>2</bitOffset>
20120 
              <bitWidth>1</bitWidth>
20121 
            </field>
20122 
            <field>
20123 
              <name>FB3</name>
20124 
              <description>Filter bits</description>
20125 
              <bitOffset>3</bitOffset>
20126 
              <bitWidth>1</bitWidth>
20127 
            </field>
20128 
            <field>
20129 
              <name>FB4</name>
20130 
              <description>Filter bits</description>
20131 
              <bitOffset>4</bitOffset>
20132 
              <bitWidth>1</bitWidth>
20133 
            </field>
20134 
            <field>
20135 
              <name>FB5</name>
20136 
              <description>Filter bits</description>
20137 
              <bitOffset>5</bitOffset>
20138 
              <bitWidth>1</bitWidth>
20139 
            </field>
20140 
            <field>
20141 
              <name>FB6</name>
20142 
              <description>Filter bits</description>
20143 
              <bitOffset>6</bitOffset>
20144 
              <bitWidth>1</bitWidth>
20145 
            </field>
20146 
            <field>
20147 
              <name>FB7</name>
20148 
              <description>Filter bits</description>
20149 
              <bitOffset>7</bitOffset>
20150 
              <bitWidth>1</bitWidth>
20151 
            </field>
20152 
            <field>
20153 
              <name>FB8</name>
20154 
              <description>Filter bits</description>
20155 
              <bitOffset>8</bitOffset>
20156 
              <bitWidth>1</bitWidth>
20157 
            </field>
20158 
            <field>
20159 
              <name>FB9</name>
20160 
              <description>Filter bits</description>
20161 
              <bitOffset>9</bitOffset>
20162 
              <bitWidth>1</bitWidth>
20163 
            </field>
20164 
            <field>
20165 
              <name>FB10</name>
20166 
              <description>Filter bits</description>
20167 
              <bitOffset>10</bitOffset>
20168 
              <bitWidth>1</bitWidth>
20169 
            </field>
20170 
            <field>
20171 
              <name>FB11</name>
20172 
              <description>Filter bits</description>
20173 
              <bitOffset>11</bitOffset>
20174 
              <bitWidth>1</bitWidth>
20175 
            </field>
20176 
            <field>
20177 
              <name>FB12</name>
20178 
              <description>Filter bits</description>
20179 
              <bitOffset>12</bitOffset>
20180 
              <bitWidth>1</bitWidth>
20181 
            </field>
20182 
            <field>
20183 
              <name>FB13</name>
20184 
              <description>Filter bits</description>
20185 
              <bitOffset>13</bitOffset>
20186 
              <bitWidth>1</bitWidth>
20187 
            </field>
20188 
            <field>
20189 
              <name>FB14</name>
20190 
              <description>Filter bits</description>
20191 
              <bitOffset>14</bitOffset>
20192 
              <bitWidth>1</bitWidth>
20193 
            </field>
20194 
            <field>
20195 
              <name>FB15</name>
20196 
              <description>Filter bits</description>
20197 
              <bitOffset>15</bitOffset>
20198 
              <bitWidth>1</bitWidth>
20199 
            </field>
20200 
            <field>
20201 
              <name>FB16</name>
20202 
              <description>Filter bits</description>
20203 
              <bitOffset>16</bitOffset>
20204 
              <bitWidth>1</bitWidth>
20205 
            </field>
20206 
            <field>
20207 
              <name>FB17</name>
20208 
              <description>Filter bits</description>
20209 
              <bitOffset>17</bitOffset>
20210 
              <bitWidth>1</bitWidth>
20211 
            </field>
20212 
            <field>
20213 
              <name>FB18</name>
20214 
              <description>Filter bits</description>
20215 
              <bitOffset>18</bitOffset>
20216 
              <bitWidth>1</bitWidth>
20217 
            </field>
20218 
            <field>
20219 
              <name>FB19</name>
20220 
              <description>Filter bits</description>
20221 
              <bitOffset>19</bitOffset>
20222 
              <bitWidth>1</bitWidth>
20223 
            </field>
20224 
            <field>
20225 
              <name>FB20</name>
20226 
              <description>Filter bits</description>
20227 
              <bitOffset>20</bitOffset>
20228 
              <bitWidth>1</bitWidth>
20229 
            </field>
20230 
            <field>
20231 
              <name>FB21</name>
20232 
              <description>Filter bits</description>
20233 
              <bitOffset>21</bitOffset>
20234 
              <bitWidth>1</bitWidth>
20235 
            </field>
20236 
            <field>
20237 
              <name>FB22</name>
20238 
              <description>Filter bits</description>
20239 
              <bitOffset>22</bitOffset>
20240 
              <bitWidth>1</bitWidth>
20241 
            </field>
20242 
            <field>
20243 
              <name>FB23</name>
20244 
              <description>Filter bits</description>
20245 
              <bitOffset>23</bitOffset>
20246 
              <bitWidth>1</bitWidth>
20247 
            </field>
20248 
            <field>
20249 
              <name>FB24</name>
20250 
              <description>Filter bits</description>
20251 
              <bitOffset>24</bitOffset>
20252 
              <bitWidth>1</bitWidth>
20253 
            </field>
20254 
            <field>
20255 
              <name>FB25</name>
20256 
              <description>Filter bits</description>
20257 
              <bitOffset>25</bitOffset>
20258 
              <bitWidth>1</bitWidth>
20259 
            </field>
20260 
            <field>
20261 
              <name>FB26</name>
20262 
              <description>Filter bits</description>
20263 
              <bitOffset>26</bitOffset>
20264 
              <bitWidth>1</bitWidth>
20265 
            </field>
20266 
            <field>
20267 
              <name>FB27</name>
20268 
              <description>Filter bits</description>
20269 
              <bitOffset>27</bitOffset>
20270 
              <bitWidth>1</bitWidth>
20271 
            </field>
20272 
            <field>
20273 
              <name>FB28</name>
20274 
              <description>Filter bits</description>
20275 
              <bitOffset>28</bitOffset>
20276 
              <bitWidth>1</bitWidth>
20277 
            </field>
20278 
            <field>
20279 
              <name>FB29</name>
20280 
              <description>Filter bits</description>
20281 
              <bitOffset>29</bitOffset>
20282 
              <bitWidth>1</bitWidth>
20283 
            </field>
20284 
            <field>
20285 
              <name>FB30</name>
20286 
              <description>Filter bits</description>
20287 
              <bitOffset>30</bitOffset>
20288 
              <bitWidth>1</bitWidth>
20289 
            </field>
20290 
            <field>
20291 
              <name>FB31</name>
20292 
              <description>Filter bits</description>
20293 
              <bitOffset>31</bitOffset>
20294 
              <bitWidth>1</bitWidth>
20295 
            </field>
20296 
          </fields>
20297 
        </register>
20298 
        <register>
20299 
          <name>F10R2</name>
20300 
          <displayName>F10R2</displayName>
20301 
          <description>Filter bank 10 register 2</description>
20302 
          <addressOffset>0x294</addressOffset>
20303 
          <size>0x20</size>
20304 
          <access>read-write</access>
20305 
          <resetValue>0x00000000</resetValue>
20306 
          <fields>
20307 
            <field>
20308 
              <name>FB0</name>
20309 
              <description>Filter bits</description>
20310 
              <bitOffset>0</bitOffset>
20311 
              <bitWidth>1</bitWidth>
20312 
            </field>
20313 
            <field>
20314 
              <name>FB1</name>
20315 
              <description>Filter bits</description>
20316 
              <bitOffset>1</bitOffset>
20317 
              <bitWidth>1</bitWidth>
20318 
            </field>
20319 
            <field>
20320 
              <name>FB2</name>
20321 
              <description>Filter bits</description>
20322 
              <bitOffset>2</bitOffset>
20323 
              <bitWidth>1</bitWidth>
20324 
            </field>
20325 
            <field>
20326 
              <name>FB3</name>
20327 
              <description>Filter bits</description>
20328 
              <bitOffset>3</bitOffset>
20329 
              <bitWidth>1</bitWidth>
20330 
            </field>
20331 
            <field>
20332 
              <name>FB4</name>
20333 
              <description>Filter bits</description>
20334 
              <bitOffset>4</bitOffset>
20335 
              <bitWidth>1</bitWidth>
20336 
            </field>
20337 
            <field>
20338 
              <name>FB5</name>
20339 
              <description>Filter bits</description>
20340 
              <bitOffset>5</bitOffset>
20341 
              <bitWidth>1</bitWidth>
20342 
            </field>
20343 
            <field>
20344 
              <name>FB6</name>
20345 
              <description>Filter bits</description>
20346 
              <bitOffset>6</bitOffset>
20347 
              <bitWidth>1</bitWidth>
20348 
            </field>
20349 
            <field>
20350 
              <name>FB7</name>
20351 
              <description>Filter bits</description>
20352 
              <bitOffset>7</bitOffset>
20353 
              <bitWidth>1</bitWidth>
20354 
            </field>
20355 
            <field>
20356 
              <name>FB8</name>
20357 
              <description>Filter bits</description>
20358 
              <bitOffset>8</bitOffset>
20359 
              <bitWidth>1</bitWidth>
20360 
            </field>
20361 
            <field>
20362 
              <name>FB9</name>
20363 
              <description>Filter bits</description>
20364 
              <bitOffset>9</bitOffset>
20365 
              <bitWidth>1</bitWidth>
20366 
            </field>
20367 
            <field>
20368 
              <name>FB10</name>
20369 
              <description>Filter bits</description>
20370 
              <bitOffset>10</bitOffset>
20371 
              <bitWidth>1</bitWidth>
20372 
            </field>
20373 
            <field>
20374 
              <name>FB11</name>
20375 
              <description>Filter bits</description>
20376 
              <bitOffset>11</bitOffset>
20377 
              <bitWidth>1</bitWidth>
20378 
            </field>
20379 
            <field>
20380 
              <name>FB12</name>
20381 
              <description>Filter bits</description>
20382 
              <bitOffset>12</bitOffset>
20383 
              <bitWidth>1</bitWidth>
20384 
            </field>
20385 
            <field>
20386 
              <name>FB13</name>
20387 
              <description>Filter bits</description>
20388 
              <bitOffset>13</bitOffset>
20389 
              <bitWidth>1</bitWidth>
20390 
            </field>
20391 
            <field>
20392 
              <name>FB14</name>
20393 
              <description>Filter bits</description>
20394 
              <bitOffset>14</bitOffset>
20395 
              <bitWidth>1</bitWidth>
20396 
            </field>
20397 
            <field>
20398 
              <name>FB15</name>
20399 
              <description>Filter bits</description>
20400 
              <bitOffset>15</bitOffset>
20401 
              <bitWidth>1</bitWidth>
20402 
            </field>
20403 
            <field>
20404 
              <name>FB16</name>
20405 
              <description>Filter bits</description>
20406 
              <bitOffset>16</bitOffset>
20407 
              <bitWidth>1</bitWidth>
20408 
            </field>
20409 
            <field>
20410 
              <name>FB17</name>
20411 
              <description>Filter bits</description>
20412 
              <bitOffset>17</bitOffset>
20413 
              <bitWidth>1</bitWidth>
20414 
            </field>
20415 
            <field>
20416 
              <name>FB18</name>
20417 
              <description>Filter bits</description>
20418 
              <bitOffset>18</bitOffset>
20419 
              <bitWidth>1</bitWidth>
20420 
            </field>
20421 
            <field>
20422 
              <name>FB19</name>
20423 
              <description>Filter bits</description>
20424 
              <bitOffset>19</bitOffset>
20425 
              <bitWidth>1</bitWidth>
20426 
            </field>
20427 
            <field>
20428 
              <name>FB20</name>
20429 
              <description>Filter bits</description>
20430 
              <bitOffset>20</bitOffset>
20431 
              <bitWidth>1</bitWidth>
20432 
            </field>
20433 
            <field>
20434 
              <name>FB21</name>
20435 
              <description>Filter bits</description>
20436 
              <bitOffset>21</bitOffset>
20437 
              <bitWidth>1</bitWidth>
20438 
            </field>
20439 
            <field>
20440 
              <name>FB22</name>
20441 
              <description>Filter bits</description>
20442 
              <bitOffset>22</bitOffset>
20443 
              <bitWidth>1</bitWidth>
20444 
            </field>
20445 
            <field>
20446 
              <name>FB23</name>
20447 
              <description>Filter bits</description>
20448 
              <bitOffset>23</bitOffset>
20449 
              <bitWidth>1</bitWidth>
20450 
            </field>
20451 
            <field>
20452 
              <name>FB24</name>
20453 
              <description>Filter bits</description>
20454 
              <bitOffset>24</bitOffset>
20455 
              <bitWidth>1</bitWidth>
20456 
            </field>
20457 
            <field>
20458 
              <name>FB25</name>
20459 
              <description>Filter bits</description>
20460 
              <bitOffset>25</bitOffset>
20461 
              <bitWidth>1</bitWidth>
20462 
            </field>
20463 
            <field>
20464 
              <name>FB26</name>
20465 
              <description>Filter bits</description>
20466 
              <bitOffset>26</bitOffset>
20467 
              <bitWidth>1</bitWidth>
20468 
            </field>
20469 
            <field>
20470 
              <name>FB27</name>
20471 
              <description>Filter bits</description>
20472 
              <bitOffset>27</bitOffset>
20473 
              <bitWidth>1</bitWidth>
20474 
            </field>
20475 
            <field>
20476 
              <name>FB28</name>
20477 
              <description>Filter bits</description>
20478 
              <bitOffset>28</bitOffset>
20479 
              <bitWidth>1</bitWidth>
20480 
            </field>
20481 
            <field>
20482 
              <name>FB29</name>
20483 
              <description>Filter bits</description>
20484 
              <bitOffset>29</bitOffset>
20485 
              <bitWidth>1</bitWidth>
20486 
            </field>
20487 
            <field>
20488 
              <name>FB30</name>
20489 
              <description>Filter bits</description>
20490 
              <bitOffset>30</bitOffset>
20491 
              <bitWidth>1</bitWidth>
20492 
            </field>
20493 
            <field>
20494 
              <name>FB31</name>
20495 
              <description>Filter bits</description>
20496 
              <bitOffset>31</bitOffset>
20497 
              <bitWidth>1</bitWidth>
20498 
            </field>
20499 
          </fields>
20500 
        </register>
20501 
        <register>
20502 
          <name>F11R1</name>
20503 
          <displayName>F11R1</displayName>
20504 
          <description>Filter bank 11 register 1</description>
20505 
          <addressOffset>0x298</addressOffset>
20506 
          <size>0x20</size>
20507 
          <access>read-write</access>
20508 
          <resetValue>0x00000000</resetValue>
20509 
          <fields>
20510 
            <field>
20511 
              <name>FB0</name>
20512 
              <description>Filter bits</description>
20513 
              <bitOffset>0</bitOffset>
20514 
              <bitWidth>1</bitWidth>
20515 
            </field>
20516 
            <field>
20517 
              <name>FB1</name>
20518 
              <description>Filter bits</description>
20519 
              <bitOffset>1</bitOffset>
20520 
              <bitWidth>1</bitWidth>
20521 
            </field>
20522 
            <field>
20523 
              <name>FB2</name>
20524 
              <description>Filter bits</description>
20525 
              <bitOffset>2</bitOffset>
20526 
              <bitWidth>1</bitWidth>
20527 
            </field>
20528 
            <field>
20529 
              <name>FB3</name>
20530 
              <description>Filter bits</description>
20531 
              <bitOffset>3</bitOffset>
20532 
              <bitWidth>1</bitWidth>
20533 
            </field>
20534 
            <field>
20535 
              <name>FB4</name>
20536 
              <description>Filter bits</description>
20537 
              <bitOffset>4</bitOffset>
20538 
              <bitWidth>1</bitWidth>
20539 
            </field>
20540 
            <field>
20541 
              <name>FB5</name>
20542 
              <description>Filter bits</description>
20543 
              <bitOffset>5</bitOffset>
20544 
              <bitWidth>1</bitWidth>
20545 
            </field>
20546 
            <field>
20547 
              <name>FB6</name>
20548 
              <description>Filter bits</description>
20549 
              <bitOffset>6</bitOffset>
20550 
              <bitWidth>1</bitWidth>
20551 
            </field>
20552 
            <field>
20553 
              <name>FB7</name>
20554 
              <description>Filter bits</description>
20555 
              <bitOffset>7</bitOffset>
20556 
              <bitWidth>1</bitWidth>
20557 
            </field>
20558 
            <field>
20559 
              <name>FB8</name>
20560 
              <description>Filter bits</description>
20561 
              <bitOffset>8</bitOffset>
20562 
              <bitWidth>1</bitWidth>
20563 
            </field>
20564 
            <field>
20565 
              <name>FB9</name>
20566 
              <description>Filter bits</description>
20567 
              <bitOffset>9</bitOffset>
20568 
              <bitWidth>1</bitWidth>
20569 
            </field>
20570 
            <field>
20571 
              <name>FB10</name>
20572 
              <description>Filter bits</description>
20573 
              <bitOffset>10</bitOffset>
20574 
              <bitWidth>1</bitWidth>
20575 
            </field>
20576 
            <field>
20577 
              <name>FB11</name>
20578 
              <description>Filter bits</description>
20579 
              <bitOffset>11</bitOffset>
20580 
              <bitWidth>1</bitWidth>
20581 
            </field>
20582 
            <field>
20583 
              <name>FB12</name>
20584 
              <description>Filter bits</description>
20585 
              <bitOffset>12</bitOffset>
20586 
              <bitWidth>1</bitWidth>
20587 
            </field>
20588 
            <field>
20589 
              <name>FB13</name>
20590 
              <description>Filter bits</description>
20591 
              <bitOffset>13</bitOffset>
20592 
              <bitWidth>1</bitWidth>
20593 
            </field>
20594 
            <field>
20595 
              <name>FB14</name>
20596 
              <description>Filter bits</description>
20597 
              <bitOffset>14</bitOffset>
20598 
              <bitWidth>1</bitWidth>
20599 
            </field>
20600 
            <field>
20601 
              <name>FB15</name>
20602 
              <description>Filter bits</description>
20603 
              <bitOffset>15</bitOffset>
20604 
              <bitWidth>1</bitWidth>
20605 
            </field>
20606 
            <field>
20607 
              <name>FB16</name>
20608 
              <description>Filter bits</description>
20609 
              <bitOffset>16</bitOffset>
20610 
              <bitWidth>1</bitWidth>
20611 
            </field>
20612 
            <field>
20613 
              <name>FB17</name>
20614 
              <description>Filter bits</description>
20615 
              <bitOffset>17</bitOffset>
20616 
              <bitWidth>1</bitWidth>
20617 
            </field>
20618 
            <field>
20619 
              <name>FB18</name>
20620 
              <description>Filter bits</description>
20621 
              <bitOffset>18</bitOffset>
20622 
              <bitWidth>1</bitWidth>
20623 
            </field>
20624 
            <field>
20625 
              <name>FB19</name>
20626 
              <description>Filter bits</description>
20627 
              <bitOffset>19</bitOffset>
20628 
              <bitWidth>1</bitWidth>
20629 
            </field>
20630 
            <field>
20631 
              <name>FB20</name>
20632 
              <description>Filter bits</description>
20633 
              <bitOffset>20</bitOffset>
20634 
              <bitWidth>1</bitWidth>
20635 
            </field>
20636 
            <field>
20637 
              <name>FB21</name>
20638 
              <description>Filter bits</description>
20639 
              <bitOffset>21</bitOffset>
20640 
              <bitWidth>1</bitWidth>
20641 
            </field>
20642 
            <field>
20643 
              <name>FB22</name>
20644 
              <description>Filter bits</description>
20645 
              <bitOffset>22</bitOffset>
20646 
              <bitWidth>1</bitWidth>
20647 
            </field>
20648 
            <field>
20649 
              <name>FB23</name>
20650 
              <description>Filter bits</description>
20651 
              <bitOffset>23</bitOffset>
20652 
              <bitWidth>1</bitWidth>
20653 
            </field>
20654 
            <field>
20655 
              <name>FB24</name>
20656 
              <description>Filter bits</description>
20657 
              <bitOffset>24</bitOffset>
20658 
              <bitWidth>1</bitWidth>
20659 
            </field>
20660 
            <field>
20661 
              <name>FB25</name>
20662 
              <description>Filter bits</description>
20663 
              <bitOffset>25</bitOffset>
20664 
              <bitWidth>1</bitWidth>
20665 
            </field>
20666 
            <field>
20667 
              <name>FB26</name>
20668 
              <description>Filter bits</description>
20669 
              <bitOffset>26</bitOffset>
20670 
              <bitWidth>1</bitWidth>
20671 
            </field>
20672 
            <field>
20673 
              <name>FB27</name>
20674 
              <description>Filter bits</description>
20675 
              <bitOffset>27</bitOffset>
20676 
              <bitWidth>1</bitWidth>
20677 
            </field>
20678 
            <field>
20679 
              <name>FB28</name>
20680 
              <description>Filter bits</description>
20681 
              <bitOffset>28</bitOffset>
20682 
              <bitWidth>1</bitWidth>
20683 
            </field>
20684 
            <field>
20685 
              <name>FB29</name>
20686 
              <description>Filter bits</description>
20687 
              <bitOffset>29</bitOffset>
20688 
              <bitWidth>1</bitWidth>
20689 
            </field>
20690 
            <field>
20691 
              <name>FB30</name>
20692 
              <description>Filter bits</description>
20693 
              <bitOffset>30</bitOffset>
20694 
              <bitWidth>1</bitWidth>
20695 
            </field>
20696 
            <field>
20697 
              <name>FB31</name>
20698 
              <description>Filter bits</description>
20699 
              <bitOffset>31</bitOffset>
20700 
              <bitWidth>1</bitWidth>
20701 
            </field>
20702 
          </fields>
20703 
        </register>
20704 
        <register>
20705 
          <name>F11R2</name>
20706 
          <displayName>F11R2</displayName>
20707 
          <description>Filter bank 11 register 2</description>
20708 
          <addressOffset>0x29C</addressOffset>
20709 
          <size>0x20</size>
20710 
          <access>read-write</access>
20711 
          <resetValue>0x00000000</resetValue>
20712 
          <fields>
20713 
            <field>
20714 
              <name>FB0</name>
20715 
              <description>Filter bits</description>
20716 
              <bitOffset>0</bitOffset>
20717 
              <bitWidth>1</bitWidth>
20718 
            </field>
20719 
            <field>
20720 
              <name>FB1</name>
20721 
              <description>Filter bits</description>
20722 
              <bitOffset>1</bitOffset>
20723 
              <bitWidth>1</bitWidth>
20724 
            </field>
20725 
            <field>
20726 
              <name>FB2</name>
20727 
              <description>Filter bits</description>
20728 
              <bitOffset>2</bitOffset>
20729 
              <bitWidth>1</bitWidth>
20730 
            </field>
20731 
            <field>
20732 
              <name>FB3</name>
20733 
              <description>Filter bits</description>
20734 
              <bitOffset>3</bitOffset>
20735 
              <bitWidth>1</bitWidth>
20736 
            </field>
20737 
            <field>
20738 
              <name>FB4</name>
20739 
              <description>Filter bits</description>
20740 
              <bitOffset>4</bitOffset>
20741 
              <bitWidth>1</bitWidth>
20742 
            </field>
20743 
            <field>
20744 
              <name>FB5</name>
20745 
              <description>Filter bits</description>
20746 
              <bitOffset>5</bitOffset>
20747 
              <bitWidth>1</bitWidth>
20748 
            </field>
20749 
            <field>
20750 
              <name>FB6</name>
20751 
              <description>Filter bits</description>
20752 
              <bitOffset>6</bitOffset>
20753 
              <bitWidth>1</bitWidth>
20754 
            </field>
20755 
            <field>
20756 
              <name>FB7</name>
20757 
              <description>Filter bits</description>
20758 
              <bitOffset>7</bitOffset>
20759 
              <bitWidth>1</bitWidth>
20760 
            </field>
20761 
            <field>
20762 
              <name>FB8</name>
20763 
              <description>Filter bits</description>
20764 
              <bitOffset>8</bitOffset>
20765 
              <bitWidth>1</bitWidth>
20766 
            </field>
20767 
            <field>
20768 
              <name>FB9</name>
20769 
              <description>Filter bits</description>
20770 
              <bitOffset>9</bitOffset>
20771 
              <bitWidth>1</bitWidth>
20772 
            </field>
20773 
            <field>
20774 
              <name>FB10</name>
20775 
              <description>Filter bits</description>
20776 
              <bitOffset>10</bitOffset>
20777 
              <bitWidth>1</bitWidth>
20778 
            </field>
20779 
            <field>
20780 
              <name>FB11</name>
20781 
              <description>Filter bits</description>
20782 
              <bitOffset>11</bitOffset>
20783 
              <bitWidth>1</bitWidth>
20784 
            </field>
20785 
            <field>
20786 
              <name>FB12</name>
20787 
              <description>Filter bits</description>
20788 
              <bitOffset>12</bitOffset>
20789 
              <bitWidth>1</bitWidth>
20790 
            </field>
20791 
            <field>
20792 
              <name>FB13</name>
20793 
              <description>Filter bits</description>
20794 
              <bitOffset>13</bitOffset>
20795 
              <bitWidth>1</bitWidth>
20796 
            </field>
20797 
            <field>
20798 
              <name>FB14</name>
20799 
              <description>Filter bits</description>
20800 
              <bitOffset>14</bitOffset>
20801 
              <bitWidth>1</bitWidth>
20802 
            </field>
20803 
            <field>
20804 
              <name>FB15</name>
20805 
              <description>Filter bits</description>
20806 
              <bitOffset>15</bitOffset>
20807 
              <bitWidth>1</bitWidth>
20808 
            </field>
20809 
            <field>
20810 
              <name>FB16</name>
20811 
              <description>Filter bits</description>
20812 
              <bitOffset>16</bitOffset>
20813 
              <bitWidth>1</bitWidth>
20814 
            </field>
20815 
            <field>
20816 
              <name>FB17</name>
20817 
              <description>Filter bits</description>
20818 
              <bitOffset>17</bitOffset>
20819 
              <bitWidth>1</bitWidth>
20820 
            </field>
20821 
            <field>
20822 
              <name>FB18</name>
20823 
              <description>Filter bits</description>
20824 
              <bitOffset>18</bitOffset>
20825 
              <bitWidth>1</bitWidth>
20826 
            </field>
20827 
            <field>
20828 
              <name>FB19</name>
20829 
              <description>Filter bits</description>
20830 
              <bitOffset>19</bitOffset>
20831 
              <bitWidth>1</bitWidth>
20832 
            </field>
20833 
            <field>
20834 
              <name>FB20</name>
20835 
              <description>Filter bits</description>
20836 
              <bitOffset>20</bitOffset>
20837 
              <bitWidth>1</bitWidth>
20838 
            </field>
20839 
            <field>
20840 
              <name>FB21</name>
20841 
              <description>Filter bits</description>
20842 
              <bitOffset>21</bitOffset>
20843 
              <bitWidth>1</bitWidth>
20844 
            </field>
20845 
            <field>
20846 
              <name>FB22</name>
20847 
              <description>Filter bits</description>
20848 
              <bitOffset>22</bitOffset>
20849 
              <bitWidth>1</bitWidth>
20850 
            </field>
20851 
            <field>
20852 
              <name>FB23</name>
20853 
              <description>Filter bits</description>
20854 
              <bitOffset>23</bitOffset>
20855 
              <bitWidth>1</bitWidth>
20856 
            </field>
20857 
            <field>
20858 
              <name>FB24</name>
20859 
              <description>Filter bits</description>
20860 
              <bitOffset>24</bitOffset>
20861 
              <bitWidth>1</bitWidth>
20862 
            </field>
20863 
            <field>
20864 
              <name>FB25</name>
20865 
              <description>Filter bits</description>
20866 
              <bitOffset>25</bitOffset>
20867 
              <bitWidth>1</bitWidth>
20868 
            </field>
20869 
            <field>
20870 
              <name>FB26</name>
20871 
              <description>Filter bits</description>
20872 
              <bitOffset>26</bitOffset>
20873 
              <bitWidth>1</bitWidth>
20874 
            </field>
20875 
            <field>
20876 
              <name>FB27</name>
20877 
              <description>Filter bits</description>
20878 
              <bitOffset>27</bitOffset>
20879 
              <bitWidth>1</bitWidth>
20880 
            </field>
20881 
            <field>
20882 
              <name>FB28</name>
20883 
              <description>Filter bits</description>
20884 
              <bitOffset>28</bitOffset>
20885 
              <bitWidth>1</bitWidth>
20886 
            </field>
20887 
            <field>
20888 
              <name>FB29</name>
20889 
              <description>Filter bits</description>
20890 
              <bitOffset>29</bitOffset>
20891 
              <bitWidth>1</bitWidth>
20892 
            </field>
20893 
            <field>
20894 
              <name>FB30</name>
20895 
              <description>Filter bits</description>
20896 
              <bitOffset>30</bitOffset>
20897 
              <bitWidth>1</bitWidth>
20898 
            </field>
20899 
            <field>
20900 
              <name>FB31</name>
20901 
              <description>Filter bits</description>
20902 
              <bitOffset>31</bitOffset>
20903 
              <bitWidth>1</bitWidth>
20904 
            </field>
20905 
          </fields>
20906 
        </register>
20907 
        <register>
20908 
          <name>F12R1</name>
20909 
          <displayName>F12R1</displayName>
20910 
          <description>Filter bank 4 register 1</description>
20911 
          <addressOffset>0x2A0</addressOffset>
20912 
          <size>0x20</size>
20913 
          <access>read-write</access>
20914 
          <resetValue>0x00000000</resetValue>
20915 
          <fields>
20916 
            <field>
20917 
              <name>FB0</name>
20918 
              <description>Filter bits</description>
20919 
              <bitOffset>0</bitOffset>
20920 
              <bitWidth>1</bitWidth>
20921 
            </field>
20922 
            <field>
20923 
              <name>FB1</name>
20924 
              <description>Filter bits</description>
20925 
              <bitOffset>1</bitOffset>
20926 
              <bitWidth>1</bitWidth>
20927 
            </field>
20928 
            <field>
20929 
              <name>FB2</name>
20930 
              <description>Filter bits</description>
20931 
              <bitOffset>2</bitOffset>
20932 
              <bitWidth>1</bitWidth>
20933 
            </field>
20934 
            <field>
20935 
              <name>FB3</name>
20936 
              <description>Filter bits</description>
20937 
              <bitOffset>3</bitOffset>
20938 
              <bitWidth>1</bitWidth>
20939 
            </field>
20940 
            <field>
20941 
              <name>FB4</name>
20942 
              <description>Filter bits</description>
20943 
              <bitOffset>4</bitOffset>
20944 
              <bitWidth>1</bitWidth>
20945 
            </field>
20946 
            <field>
20947 
              <name>FB5</name>
20948 
              <description>Filter bits</description>
20949 
              <bitOffset>5</bitOffset>
20950 
              <bitWidth>1</bitWidth>
20951 
            </field>
20952 
            <field>
20953 
              <name>FB6</name>
20954 
              <description>Filter bits</description>
20955 
              <bitOffset>6</bitOffset>
20956 
              <bitWidth>1</bitWidth>
20957 
            </field>
20958 
            <field>
20959 
              <name>FB7</name>
20960 
              <description>Filter bits</description>
20961 
              <bitOffset>7</bitOffset>
20962 
              <bitWidth>1</bitWidth>
20963 
            </field>
20964 
            <field>
20965 
              <name>FB8</name>
20966 
              <description>Filter bits</description>
20967 
              <bitOffset>8</bitOffset>
20968 
              <bitWidth>1</bitWidth>
20969 
            </field>
20970 
            <field>
20971 
              <name>FB9</name>
20972 
              <description>Filter bits</description>
20973 
              <bitOffset>9</bitOffset>
20974 
              <bitWidth>1</bitWidth>
20975 
            </field>
20976 
            <field>
20977 
              <name>FB10</name>
20978 
              <description>Filter bits</description>
20979 
              <bitOffset>10</bitOffset>
20980 
              <bitWidth>1</bitWidth>
20981 
            </field>
20982 
            <field>
20983 
              <name>FB11</name>
20984 
              <description>Filter bits</description>
20985 
              <bitOffset>11</bitOffset>
20986 
              <bitWidth>1</bitWidth>
20987 
            </field>
20988 
            <field>
20989 
              <name>FB12</name>
20990 
              <description>Filter bits</description>
20991 
              <bitOffset>12</bitOffset>
20992 
              <bitWidth>1</bitWidth>
20993 
            </field>
20994 
            <field>
20995 
              <name>FB13</name>
20996 
              <description>Filter bits</description>
20997 
              <bitOffset>13</bitOffset>
20998 
              <bitWidth>1</bitWidth>
20999 
            </field>
21000 
            <field>
21001 
              <name>FB14</name>
21002 
              <description>Filter bits</description>
21003 
              <bitOffset>14</bitOffset>
21004 
              <bitWidth>1</bitWidth>
21005 
            </field>
21006 
            <field>
21007 
              <name>FB15</name>
21008 
              <description>Filter bits</description>
21009 
              <bitOffset>15</bitOffset>
21010 
              <bitWidth>1</bitWidth>
21011 
            </field>
21012 
            <field>
21013 
              <name>FB16</name>
21014 
              <description>Filter bits</description>
21015 
              <bitOffset>16</bitOffset>
21016 
              <bitWidth>1</bitWidth>
21017 
            </field>
21018 
            <field>
21019 
              <name>FB17</name>
21020 
              <description>Filter bits</description>
21021 
              <bitOffset>17</bitOffset>
21022 
              <bitWidth>1</bitWidth>
21023 
            </field>
21024 
            <field>
21025 
              <name>FB18</name>
21026 
              <description>Filter bits</description>
21027 
              <bitOffset>18</bitOffset>
21028 
              <bitWidth>1</bitWidth>
21029 
            </field>
21030 
            <field>
21031 
              <name>FB19</name>
21032 
              <description>Filter bits</description>
21033 
              <bitOffset>19</bitOffset>
21034 
              <bitWidth>1</bitWidth>
21035 
            </field>
21036 
            <field>
21037 
              <name>FB20</name>
21038 
              <description>Filter bits</description>
21039 
              <bitOffset>20</bitOffset>
21040 
              <bitWidth>1</bitWidth>
21041 
            </field>
21042 
            <field>
21043 
              <name>FB21</name>
21044 
              <description>Filter bits</description>
21045 
              <bitOffset>21</bitOffset>
21046 
              <bitWidth>1</bitWidth>
21047 
            </field>
21048 
            <field>
21049 
              <name>FB22</name>
21050 
              <description>Filter bits</description>
21051 
              <bitOffset>22</bitOffset>
21052 
              <bitWidth>1</bitWidth>
21053 
            </field>
21054 
            <field>
21055 
              <name>FB23</name>
21056 
              <description>Filter bits</description>
21057 
              <bitOffset>23</bitOffset>
21058 
              <bitWidth>1</bitWidth>
21059 
            </field>
21060 
            <field>
21061 
              <name>FB24</name>
21062 
              <description>Filter bits</description>
21063 
              <bitOffset>24</bitOffset>
21064 
              <bitWidth>1</bitWidth>
21065 
            </field>
21066 
            <field>
21067 
              <name>FB25</name>
21068 
              <description>Filter bits</description>
21069 
              <bitOffset>25</bitOffset>
21070 
              <bitWidth>1</bitWidth>
21071 
            </field>
21072 
            <field>
21073 
              <name>FB26</name>
21074 
              <description>Filter bits</description>
21075 
              <bitOffset>26</bitOffset>
21076 
              <bitWidth>1</bitWidth>
21077 
            </field>
21078 
            <field>
21079 
              <name>FB27</name>
21080 
              <description>Filter bits</description>
21081 
              <bitOffset>27</bitOffset>
21082 
              <bitWidth>1</bitWidth>
21083 
            </field>
21084 
            <field>
21085 
              <name>FB28</name>
21086 
              <description>Filter bits</description>
21087 
              <bitOffset>28</bitOffset>
21088 
              <bitWidth>1</bitWidth>
21089 
            </field>
21090 
            <field>
21091 
              <name>FB29</name>
21092 
              <description>Filter bits</description>
21093 
              <bitOffset>29</bitOffset>
21094 
              <bitWidth>1</bitWidth>
21095 
            </field>
21096 
            <field>
21097 
              <name>FB30</name>
21098 
              <description>Filter bits</description>
21099 
              <bitOffset>30</bitOffset>
21100 
              <bitWidth>1</bitWidth>
21101 
            </field>
21102 
            <field>
21103 
              <name>FB31</name>
21104 
              <description>Filter bits</description>
21105 
              <bitOffset>31</bitOffset>
21106 
              <bitWidth>1</bitWidth>
21107 
            </field>
21108 
          </fields>
21109 
        </register>
21110 
        <register>
21111 
          <name>F12R2</name>
21112 
          <displayName>F12R2</displayName>
21113 
          <description>Filter bank 12 register 2</description>
21114 
          <addressOffset>0x2A4</addressOffset>
21115 
          <size>0x20</size>
21116 
          <access>read-write</access>
21117 
          <resetValue>0x00000000</resetValue>
21118 
          <fields>
21119 
            <field>
21120 
              <name>FB0</name>
21121 
              <description>Filter bits</description>
21122 
              <bitOffset>0</bitOffset>
21123 
              <bitWidth>1</bitWidth>
21124 
            </field>
21125 
            <field>
21126 
              <name>FB1</name>
21127 
              <description>Filter bits</description>
21128 
              <bitOffset>1</bitOffset>
21129 
              <bitWidth>1</bitWidth>
21130 
            </field>
21131 
            <field>
21132 
              <name>FB2</name>
21133 
              <description>Filter bits</description>
21134 
              <bitOffset>2</bitOffset>
21135 
              <bitWidth>1</bitWidth>
21136 
            </field>
21137 
            <field>
21138 
              <name>FB3</name>
21139 
              <description>Filter bits</description>
21140 
              <bitOffset>3</bitOffset>
21141 
              <bitWidth>1</bitWidth>
21142 
            </field>
21143 
            <field>
21144 
              <name>FB4</name>
21145 
              <description>Filter bits</description>
21146 
              <bitOffset>4</bitOffset>
21147 
              <bitWidth>1</bitWidth>
21148 
            </field>
21149 
            <field>
21150 
              <name>FB5</name>
21151 
              <description>Filter bits</description>
21152 
              <bitOffset>5</bitOffset>
21153 
              <bitWidth>1</bitWidth>
21154 
            </field>
21155 
            <field>
21156 
              <name>FB6</name>
21157 
              <description>Filter bits</description>
21158 
              <bitOffset>6</bitOffset>
21159 
              <bitWidth>1</bitWidth>
21160 
            </field>
21161 
            <field>
21162 
              <name>FB7</name>
21163 
              <description>Filter bits</description>
21164 
              <bitOffset>7</bitOffset>
21165 
              <bitWidth>1</bitWidth>
21166 
            </field>
21167 
            <field>
21168 
              <name>FB8</name>
21169 
              <description>Filter bits</description>
21170 
              <bitOffset>8</bitOffset>
21171 
              <bitWidth>1</bitWidth>
21172 
            </field>
21173 
            <field>
21174 
              <name>FB9</name>
21175 
              <description>Filter bits</description>
21176 
              <bitOffset>9</bitOffset>
21177 
              <bitWidth>1</bitWidth>
21178 
            </field>
21179 
            <field>
21180 
              <name>FB10</name>
21181 
              <description>Filter bits</description>
21182 
              <bitOffset>10</bitOffset>
21183 
              <bitWidth>1</bitWidth>
21184 
            </field>
21185 
            <field>
21186 
              <name>FB11</name>
21187 
              <description>Filter bits</description>
21188 
              <bitOffset>11</bitOffset>
21189 
              <bitWidth>1</bitWidth>
21190 
            </field>
21191 
            <field>
21192 
              <name>FB12</name>
21193 
              <description>Filter bits</description>
21194 
              <bitOffset>12</bitOffset>
21195 
              <bitWidth>1</bitWidth>
21196 
            </field>
21197 
            <field>
21198 
              <name>FB13</name>
21199 
              <description>Filter bits</description>
21200 
              <bitOffset>13</bitOffset>
21201 
              <bitWidth>1</bitWidth>
21202 
            </field>
21203 
            <field>
21204 
              <name>FB14</name>
21205 
              <description>Filter bits</description>
21206 
              <bitOffset>14</bitOffset>
21207 
              <bitWidth>1</bitWidth>
21208 
            </field>
21209 
            <field>
21210 
              <name>FB15</name>
21211 
              <description>Filter bits</description>
21212 
              <bitOffset>15</bitOffset>
21213 
              <bitWidth>1</bitWidth>
21214 
            </field>
21215 
            <field>
21216 
              <name>FB16</name>
21217 
              <description>Filter bits</description>
21218 
              <bitOffset>16</bitOffset>
21219 
              <bitWidth>1</bitWidth>
21220 
            </field>
21221 
            <field>
21222 
              <name>FB17</name>
21223 
              <description>Filter bits</description>
21224 
              <bitOffset>17</bitOffset>
21225 
              <bitWidth>1</bitWidth>
21226 
            </field>
21227 
            <field>
21228 
              <name>FB18</name>
21229 
              <description>Filter bits</description>
21230 
              <bitOffset>18</bitOffset>
21231 
              <bitWidth>1</bitWidth>
21232 
            </field>
21233 
            <field>
21234 
              <name>FB19</name>
21235 
              <description>Filter bits</description>
21236 
              <bitOffset>19</bitOffset>
21237 
              <bitWidth>1</bitWidth>
21238 
            </field>
21239 
            <field>
21240 
              <name>FB20</name>
21241 
              <description>Filter bits</description>
21242 
              <bitOffset>20</bitOffset>
21243 
              <bitWidth>1</bitWidth>
21244 
            </field>
21245 
            <field>
21246 
              <name>FB21</name>
21247 
              <description>Filter bits</description>
21248 
              <bitOffset>21</bitOffset>
21249 
              <bitWidth>1</bitWidth>
21250 
            </field>
21251 
            <field>
21252 
              <name>FB22</name>
21253 
              <description>Filter bits</description>
21254 
              <bitOffset>22</bitOffset>
21255 
              <bitWidth>1</bitWidth>
21256 
            </field>
21257 
            <field>
21258 
              <name>FB23</name>
21259 
              <description>Filter bits</description>
21260 
              <bitOffset>23</bitOffset>
21261 
              <bitWidth>1</bitWidth>
21262 
            </field>
21263 
            <field>
21264 
              <name>FB24</name>
21265 
              <description>Filter bits</description>
21266 
              <bitOffset>24</bitOffset>
21267 
              <bitWidth>1</bitWidth>
21268 
            </field>
21269 
            <field>
21270 
              <name>FB25</name>
21271 
              <description>Filter bits</description>
21272 
              <bitOffset>25</bitOffset>
21273 
              <bitWidth>1</bitWidth>
21274 
            </field>
21275 
            <field>
21276 
              <name>FB26</name>
21277 
              <description>Filter bits</description>
21278 
              <bitOffset>26</bitOffset>
21279 
              <bitWidth>1</bitWidth>
21280 
            </field>
21281 
            <field>
21282 
              <name>FB27</name>
21283 
              <description>Filter bits</description>
21284 
              <bitOffset>27</bitOffset>
21285 
              <bitWidth>1</bitWidth>
21286 
            </field>
21287 
            <field>
21288 
              <name>FB28</name>
21289 
              <description>Filter bits</description>
21290 
              <bitOffset>28</bitOffset>
21291 
              <bitWidth>1</bitWidth>
21292 
            </field>
21293 
            <field>
21294 
              <name>FB29</name>
21295 
              <description>Filter bits</description>
21296 
              <bitOffset>29</bitOffset>
21297 
              <bitWidth>1</bitWidth>
21298 
            </field>
21299 
            <field>
21300 
              <name>FB30</name>
21301 
              <description>Filter bits</description>
21302 
              <bitOffset>30</bitOffset>
21303 
              <bitWidth>1</bitWidth>
21304 
            </field>
21305 
            <field>
21306 
              <name>FB31</name>
21307 
              <description>Filter bits</description>
21308 
              <bitOffset>31</bitOffset>
21309 
              <bitWidth>1</bitWidth>
21310 
            </field>
21311 
          </fields>
21312 
        </register>
21313 
        <register>
21314 
          <name>F13R1</name>
21315 
          <displayName>F13R1</displayName>
21316 
          <description>Filter bank 13 register 1</description>
21317 
          <addressOffset>0x2A8</addressOffset>
21318 
          <size>0x20</size>
21319 
          <access>read-write</access>
21320 
          <resetValue>0x00000000</resetValue>
21321 
          <fields>
21322 
            <field>
21323 
              <name>FB0</name>
21324 
              <description>Filter bits</description>
21325 
              <bitOffset>0</bitOffset>
21326 
              <bitWidth>1</bitWidth>
21327 
            </field>
21328 
            <field>
21329 
              <name>FB1</name>
21330 
              <description>Filter bits</description>
21331 
              <bitOffset>1</bitOffset>
21332 
              <bitWidth>1</bitWidth>
21333 
            </field>
21334 
            <field>
21335 
              <name>FB2</name>
21336 
              <description>Filter bits</description>
21337 
              <bitOffset>2</bitOffset>
21338 
              <bitWidth>1</bitWidth>
21339 
            </field>
21340 
            <field>
21341 
              <name>FB3</name>
21342 
              <description>Filter bits</description>
21343 
              <bitOffset>3</bitOffset>
21344 
              <bitWidth>1</bitWidth>
21345 
            </field>
21346 
            <field>
21347 
              <name>FB4</name>
21348 
              <description>Filter bits</description>
21349 
              <bitOffset>4</bitOffset>
21350 
              <bitWidth>1</bitWidth>
21351 
            </field>
21352 
            <field>
21353 
              <name>FB5</name>
21354 
              <description>Filter bits</description>
21355 
              <bitOffset>5</bitOffset>
21356 
              <bitWidth>1</bitWidth>
21357 
            </field>
21358 
            <field>
21359 
              <name>FB6</name>
21360 
              <description>Filter bits</description>
21361 
              <bitOffset>6</bitOffset>
21362 
              <bitWidth>1</bitWidth>
21363 
            </field>
21364 
            <field>
21365 
              <name>FB7</name>
21366 
              <description>Filter bits</description>
21367 
              <bitOffset>7</bitOffset>
21368 
              <bitWidth>1</bitWidth>
21369 
            </field>
21370 
            <field>
21371 
              <name>FB8</name>
21372 
              <description>Filter bits</description>
21373 
              <bitOffset>8</bitOffset>
21374 
              <bitWidth>1</bitWidth>
21375 
            </field>
21376 
            <field>
21377 
              <name>FB9</name>
21378 
              <description>Filter bits</description>
21379 
              <bitOffset>9</bitOffset>
21380 
              <bitWidth>1</bitWidth>
21381 
            </field>
21382 
            <field>
21383 
              <name>FB10</name>
21384 
              <description>Filter bits</description>
21385 
              <bitOffset>10</bitOffset>
21386 
              <bitWidth>1</bitWidth>
21387 
            </field>
21388 
            <field>
21389 
              <name>FB11</name>
21390 
              <description>Filter bits</description>
21391 
              <bitOffset>11</bitOffset>
21392 
              <bitWidth>1</bitWidth>
21393 
            </field>
21394 
            <field>
21395 
              <name>FB12</name>
21396 
              <description>Filter bits</description>
21397 
              <bitOffset>12</bitOffset>
21398 
              <bitWidth>1</bitWidth>
21399 
            </field>
21400 
            <field>
21401 
              <name>FB13</name>
21402 
              <description>Filter bits</description>
21403 
              <bitOffset>13</bitOffset>
21404 
              <bitWidth>1</bitWidth>
21405 
            </field>
21406 
            <field>
21407 
              <name>FB14</name>
21408 
              <description>Filter bits</description>
21409 
              <bitOffset>14</bitOffset>
21410 
              <bitWidth>1</bitWidth>
21411 
            </field>
21412 
            <field>
21413 
              <name>FB15</name>
21414 
              <description>Filter bits</description>
21415 
              <bitOffset>15</bitOffset>
21416 
              <bitWidth>1</bitWidth>
21417 
            </field>
21418 
            <field>
21419 
              <name>FB16</name>
21420 
              <description>Filter bits</description>
21421 
              <bitOffset>16</bitOffset>
21422 
              <bitWidth>1</bitWidth>
21423 
            </field>
21424 
            <field>
21425 
              <name>FB17</name>
21426 
              <description>Filter bits</description>
21427 
              <bitOffset>17</bitOffset>
21428 
              <bitWidth>1</bitWidth>
21429 
            </field>
21430 
            <field>
21431 
              <name>FB18</name>
21432 
              <description>Filter bits</description>
21433 
              <bitOffset>18</bitOffset>
21434 
              <bitWidth>1</bitWidth>
21435 
            </field>
21436 
            <field>
21437 
              <name>FB19</name>
21438 
              <description>Filter bits</description>
21439 
              <bitOffset>19</bitOffset>
21440 
              <bitWidth>1</bitWidth>
21441 
            </field>
21442 
            <field>
21443 
              <name>FB20</name>
21444 
              <description>Filter bits</description>
21445 
              <bitOffset>20</bitOffset>
21446 
              <bitWidth>1</bitWidth>
21447 
            </field>
21448 
            <field>
21449 
              <name>FB21</name>
21450 
              <description>Filter bits</description>
21451 
              <bitOffset>21</bitOffset>
21452 
              <bitWidth>1</bitWidth>
21453 
            </field>
21454 
            <field>
21455 
              <name>FB22</name>
21456 
              <description>Filter bits</description>
21457 
              <bitOffset>22</bitOffset>
21458 
              <bitWidth>1</bitWidth>
21459 
            </field>
21460 
            <field>
21461 
              <name>FB23</name>
21462 
              <description>Filter bits</description>
21463 
              <bitOffset>23</bitOffset>
21464 
              <bitWidth>1</bitWidth>
21465 
            </field>
21466 
            <field>
21467 
              <name>FB24</name>
21468 
              <description>Filter bits</description>
21469 
              <bitOffset>24</bitOffset>
21470 
              <bitWidth>1</bitWidth>
21471 
            </field>
21472 
            <field>
21473 
              <name>FB25</name>
21474 
              <description>Filter bits</description>
21475 
              <bitOffset>25</bitOffset>
21476 
              <bitWidth>1</bitWidth>
21477 
            </field>
21478 
            <field>
21479 
              <name>FB26</name>
21480 
              <description>Filter bits</description>
21481 
              <bitOffset>26</bitOffset>
21482 
              <bitWidth>1</bitWidth>
21483 
            </field>
21484 
            <field>
21485 
              <name>FB27</name>
21486 
              <description>Filter bits</description>
21487 
              <bitOffset>27</bitOffset>
21488 
              <bitWidth>1</bitWidth>
21489 
            </field>
21490 
            <field>
21491 
              <name>FB28</name>
21492 
              <description>Filter bits</description>
21493 
              <bitOffset>28</bitOffset>
21494 
              <bitWidth>1</bitWidth>
21495 
            </field>
21496 
            <field>
21497 
              <name>FB29</name>
21498 
              <description>Filter bits</description>
21499 
              <bitOffset>29</bitOffset>
21500 
              <bitWidth>1</bitWidth>
21501 
            </field>
21502 
            <field>
21503 
              <name>FB30</name>
21504 
              <description>Filter bits</description>
21505 
              <bitOffset>30</bitOffset>
21506 
              <bitWidth>1</bitWidth>
21507 
            </field>
21508 
            <field>
21509 
              <name>FB31</name>
21510 
              <description>Filter bits</description>
21511 
              <bitOffset>31</bitOffset>
21512 
              <bitWidth>1</bitWidth>
21513 
            </field>
21514 
          </fields>
21515 
        </register>
21516 
        <register>
21517 
          <name>F13R2</name>
21518 
          <displayName>F13R2</displayName>
21519 
          <description>Filter bank 13 register 2</description>
21520 
          <addressOffset>0x2AC</addressOffset>
21521 
          <size>0x20</size>
21522 
          <access>read-write</access>
21523 
          <resetValue>0x00000000</resetValue>
21524 
          <fields>
21525 
            <field>
21526 
              <name>FB0</name>
21527 
              <description>Filter bits</description>
21528 
              <bitOffset>0</bitOffset>
21529 
              <bitWidth>1</bitWidth>
21530 
            </field>
21531 
            <field>
21532 
              <name>FB1</name>
21533 
              <description>Filter bits</description>
21534 
              <bitOffset>1</bitOffset>
21535 
              <bitWidth>1</bitWidth>
21536 
            </field>
21537 
            <field>
21538 
              <name>FB2</name>
21539 
              <description>Filter bits</description>
21540 
              <bitOffset>2</bitOffset>
21541 
              <bitWidth>1</bitWidth>
21542 
            </field>
21543 
            <field>
21544 
              <name>FB3</name>
21545 
              <description>Filter bits</description>
21546 
              <bitOffset>3</bitOffset>
21547 
              <bitWidth>1</bitWidth>
21548 
            </field>
21549 
            <field>
21550 
              <name>FB4</name>
21551 
              <description>Filter bits</description>
21552 
              <bitOffset>4</bitOffset>
21553 
              <bitWidth>1</bitWidth>
21554 
            </field>
21555 
            <field>
21556 
              <name>FB5</name>
21557 
              <description>Filter bits</description>
21558 
              <bitOffset>5</bitOffset>
21559 
              <bitWidth>1</bitWidth>
21560 
            </field>
21561 
            <field>
21562 
              <name>FB6</name>
21563 
              <description>Filter bits</description>
21564 
              <bitOffset>6</bitOffset>
21565 
              <bitWidth>1</bitWidth>
21566 
            </field>
21567 
            <field>
21568 
              <name>FB7</name>
21569 
              <description>Filter bits</description>
21570 
              <bitOffset>7</bitOffset>
21571 
              <bitWidth>1</bitWidth>
21572 
            </field>
21573 
            <field>
21574 
              <name>FB8</name>
21575 
              <description>Filter bits</description>
21576 
              <bitOffset>8</bitOffset>
21577 
              <bitWidth>1</bitWidth>
21578 
            </field>
21579 
            <field>
21580 
              <name>FB9</name>
21581 
              <description>Filter bits</description>
21582 
              <bitOffset>9</bitOffset>
21583 
              <bitWidth>1</bitWidth>
21584 
            </field>
21585 
            <field>
21586 
              <name>FB10</name>
21587 
              <description>Filter bits</description>
21588 
              <bitOffset>10</bitOffset>
21589 
              <bitWidth>1</bitWidth>
21590 
            </field>
21591 
            <field>
21592 
              <name>FB11</name>
21593 
              <description>Filter bits</description>
21594 
              <bitOffset>11</bitOffset>
21595 
              <bitWidth>1</bitWidth>
21596 
            </field>
21597 
            <field>
21598 
              <name>FB12</name>
21599 
              <description>Filter bits</description>
21600 
              <bitOffset>12</bitOffset>
21601 
              <bitWidth>1</bitWidth>
21602 
            </field>
21603 
            <field>
21604 
              <name>FB13</name>
21605 
              <description>Filter bits</description>
21606 
              <bitOffset>13</bitOffset>
21607 
              <bitWidth>1</bitWidth>
21608 
            </field>
21609 
            <field>
21610 
              <name>FB14</name>
21611 
              <description>Filter bits</description>
21612 
              <bitOffset>14</bitOffset>
21613 
              <bitWidth>1</bitWidth>
21614 
            </field>
21615 
            <field>
21616 
              <name>FB15</name>
21617 
              <description>Filter bits</description>
21618 
              <bitOffset>15</bitOffset>
21619 
              <bitWidth>1</bitWidth>
21620 
            </field>
21621 
            <field>
21622 
              <name>FB16</name>
21623 
              <description>Filter bits</description>
21624 
              <bitOffset>16</bitOffset>
21625 
              <bitWidth>1</bitWidth>
21626 
            </field>
21627 
            <field>
21628 
              <name>FB17</name>
21629 
              <description>Filter bits</description>
21630 
              <bitOffset>17</bitOffset>
21631 
              <bitWidth>1</bitWidth>
21632 
            </field>
21633 
            <field>
21634 
              <name>FB18</name>
21635 
              <description>Filter bits</description>
21636 
              <bitOffset>18</bitOffset>
21637 
              <bitWidth>1</bitWidth>
21638 
            </field>
21639 
            <field>
21640 
              <name>FB19</name>
21641 
              <description>Filter bits</description>
21642 
              <bitOffset>19</bitOffset>
21643 
              <bitWidth>1</bitWidth>
21644 
            </field>
21645 
            <field>
21646 
              <name>FB20</name>
21647 
              <description>Filter bits</description>
21648 
              <bitOffset>20</bitOffset>
21649 
              <bitWidth>1</bitWidth>
21650 
            </field>
21651 
            <field>
21652 
              <name>FB21</name>
21653 
              <description>Filter bits</description>
21654 
              <bitOffset>21</bitOffset>
21655 
              <bitWidth>1</bitWidth>
21656 
            </field>
21657 
            <field>
21658 
              <name>FB22</name>
21659 
              <description>Filter bits</description>
21660 
              <bitOffset>22</bitOffset>
21661 
              <bitWidth>1</bitWidth>
21662 
            </field>
21663 
            <field>
21664 
              <name>FB23</name>
21665 
              <description>Filter bits</description>
21666 
              <bitOffset>23</bitOffset>
21667 
              <bitWidth>1</bitWidth>
21668 
            </field>
21669 
            <field>
21670 
              <name>FB24</name>
21671 
              <description>Filter bits</description>
21672 
              <bitOffset>24</bitOffset>
21673 
              <bitWidth>1</bitWidth>
21674 
            </field>
21675 
            <field>
21676 
              <name>FB25</name>
21677 
              <description>Filter bits</description>
21678 
              <bitOffset>25</bitOffset>
21679 
              <bitWidth>1</bitWidth>
21680 
            </field>
21681 
            <field>
21682 
              <name>FB26</name>
21683 
              <description>Filter bits</description>
21684 
              <bitOffset>26</bitOffset>
21685 
              <bitWidth>1</bitWidth>
21686 
            </field>
21687 
            <field>
21688 
              <name>FB27</name>
21689 
              <description>Filter bits</description>
21690 
              <bitOffset>27</bitOffset>
21691 
              <bitWidth>1</bitWidth>
21692 
            </field>
21693 
            <field>
21694 
              <name>FB28</name>
21695 
              <description>Filter bits</description>
21696 
              <bitOffset>28</bitOffset>
21697 
              <bitWidth>1</bitWidth>
21698 
            </field>
21699 
            <field>
21700 
              <name>FB29</name>
21701 
              <description>Filter bits</description>
21702 
              <bitOffset>29</bitOffset>
21703 
              <bitWidth>1</bitWidth>
21704 
            </field>
21705 
            <field>
21706 
              <name>FB30</name>
21707 
              <description>Filter bits</description>
21708 
              <bitOffset>30</bitOffset>
21709 
              <bitWidth>1</bitWidth>
21710 
            </field>
21711 
            <field>
21712 
              <name>FB31</name>
21713 
              <description>Filter bits</description>
21714 
              <bitOffset>31</bitOffset>
21715 
              <bitWidth>1</bitWidth>
21716 
            </field>
21717 
          </fields>
21718 
        </register>
21719 
      </registers>
21720 
    </peripheral>
21721 
    <peripheral derivedFrom="CAN1">
21722 
      <name>CAN2</name>
21723 
      <baseAddress>0x40006800</baseAddress>
21724 
    </peripheral>
21725 
    <peripheral>
21726 
      <name>DAC</name>
21727 
      <description>Digital to analog converter</description>
21728 
      <groupName>DAC</groupName>
21729 
      <baseAddress>0x40007400</baseAddress>
21730 
      <addressBlock>
21731 
        <offset>0x0</offset>
21732 
        <size>0x400</size>
21733 
        <usage>registers</usage>
21734 
      </addressBlock>
21735 
      <registers>
21736 
        <register>
21737 
          <name>CR</name>
21738 
          <displayName>CR</displayName>
21739 
          <description>Control register (DAC_CR)</description>
21740 
          <addressOffset>0x0</addressOffset>
21741 
          <size>0x20</size>
21742 
          <access>read-write</access>
21743 
          <resetValue>0x00000000</resetValue>
21744 
          <fields>
21745 
            <field>
21746 
              <name>EN1</name>
21747 
              <description>DAC channel1 enable</description>
21748 
              <bitOffset>0</bitOffset>
21749 
              <bitWidth>1</bitWidth>
21750 
            </field>
21751 
            <field>
21752 
              <name>BOFF1</name>
21753 
              <description>DAC channel1 output buffer
21754 
              disable</description>
21755 
              <bitOffset>1</bitOffset>
21756 
              <bitWidth>1</bitWidth>
21757 
            </field>
21758 
            <field>
21759 
              <name>TEN1</name>
21760 
              <description>DAC channel1 trigger
21761 
              enable</description>
21762 
              <bitOffset>2</bitOffset>
21763 
              <bitWidth>1</bitWidth>
21764 
            </field>
21765 
            <field>
21766 
              <name>TSEL1</name>
21767 
              <description>DAC channel1 trigger
21768 
              selection</description>
21769 
              <bitOffset>3</bitOffset>
21770 
              <bitWidth>3</bitWidth>
21771 
            </field>
21772 
            <field>
21773 
              <name>WAVE1</name>
21774 
              <description>DAC channel1 noise/triangle wave
21775 
              generation enable</description>
21776 
              <bitOffset>6</bitOffset>
21777 
              <bitWidth>2</bitWidth>
21778 
            </field>
21779 
            <field>
21780 
              <name>MAMP1</name>
21781 
              <description>DAC channel1 mask/amplitude
21782 
              selector</description>
21783 
              <bitOffset>8</bitOffset>
21784 
              <bitWidth>4</bitWidth>
21785 
            </field>
21786 
            <field>
21787 
              <name>DMAEN1</name>
21788 
              <description>DAC channel1 DMA enable</description>
21789 
              <bitOffset>12</bitOffset>
21790 
              <bitWidth>1</bitWidth>
21791 
            </field>
21792 
            <field>
21793 
              <name>EN2</name>
21794 
              <description>DAC channel2 enable</description>
21795 
              <bitOffset>16</bitOffset>
21796 
              <bitWidth>1</bitWidth>
21797 
            </field>
21798 
            <field>
21799 
              <name>BOFF2</name>
21800 
              <description>DAC channel2 output buffer
21801 
              disable</description>
21802 
              <bitOffset>17</bitOffset>
21803 
              <bitWidth>1</bitWidth>
21804 
            </field>
21805 
            <field>
21806 
              <name>TEN2</name>
21807 
              <description>DAC channel2 trigger
21808 
              enable</description>
21809 
              <bitOffset>18</bitOffset>
21810 
              <bitWidth>1</bitWidth>
21811 
            </field>
21812 
            <field>
21813 
              <name>TSEL2</name>
21814 
              <description>DAC channel2 trigger
21815 
              selection</description>
21816 
              <bitOffset>19</bitOffset>
21817 
              <bitWidth>3</bitWidth>
21818 
            </field>
21819 
            <field>
21820 
              <name>WAVE2</name>
21821 
              <description>DAC channel2 noise/triangle wave
21822 
              generation enable</description>
21823 
              <bitOffset>22</bitOffset>
21824 
              <bitWidth>2</bitWidth>
21825 
            </field>
21826 
            <field>
21827 
              <name>MAMP2</name>
21828 
              <description>DAC channel2 mask/amplitude
21829 
              selector</description>
21830 
              <bitOffset>24</bitOffset>
21831 
              <bitWidth>4</bitWidth>
21832 
            </field>
21833 
            <field>
21834 
              <name>DMAEN2</name>
21835 
              <description>DAC channel2 DMA enable</description>
21836 
              <bitOffset>28</bitOffset>
21837 
              <bitWidth>1</bitWidth>
21838 
            </field>
21839 
          </fields>
21840 
        </register>
21841 
        <register>
21842 
          <name>SWTRIGR</name>
21843 
          <displayName>SWTRIGR</displayName>
21844 
          <description>DAC software trigger register
21845 
          (DAC_SWTRIGR)</description>
21846 
          <addressOffset>0x4</addressOffset>
21847 
          <size>0x20</size>
21848 
          <access>write-only</access>
21849 
          <resetValue>0x00000000</resetValue>
21850 
          <fields>
21851 
            <field>
21852 
              <name>SWTRIG1</name>
21853 
              <description>DAC channel1 software
21854 
              trigger</description>
21855 
              <bitOffset>0</bitOffset>
21856 
              <bitWidth>1</bitWidth>
21857 
            </field>
21858 
            <field>
21859 
              <name>SWTRIG2</name>
21860 
              <description>DAC channel2 software
21861 
              trigger</description>
21862 
              <bitOffset>1</bitOffset>
21863 
              <bitWidth>1</bitWidth>
21864 
            </field>
21865 
          </fields>
21866 
        </register>
21867 
        <register>
21868 
          <name>DHR12R1</name>
21869 
          <displayName>DHR12R1</displayName>
21870 
          <description>DAC channel1 12-bit right-aligned data
21871 
          holding register(DAC_DHR12R1)</description>
21872 
          <addressOffset>0x8</addressOffset>
21873 
          <size>0x20</size>
21874 
          <access>read-write</access>
21875 
          <resetValue>0x00000000</resetValue>
21876 
          <fields>
21877 
            <field>
21878 
              <name>DACC1DHR</name>
21879 
              <description>DAC channel1 12-bit right-aligned
21880 
              data</description>
21881 
              <bitOffset>0</bitOffset>
21882 
              <bitWidth>12</bitWidth>
21883 
            </field>
21884 
          </fields>
21885 
        </register>
21886 
        <register>
21887 
          <name>DHR12L1</name>
21888 
          <displayName>DHR12L1</displayName>
21889 
          <description>DAC channel1 12-bit left aligned data
21890 
          holding register (DAC_DHR12L1)</description>
21891 
          <addressOffset>0xC</addressOffset>
21892 
          <size>0x20</size>
21893 
          <access>read-write</access>
21894 
          <resetValue>0x00000000</resetValue>
21895 
          <fields>
21896 
            <field>
21897 
              <name>DACC1DHR</name>
21898 
              <description>DAC channel1 12-bit left-aligned
21899 
              data</description>
21900 
              <bitOffset>4</bitOffset>
21901 
              <bitWidth>12</bitWidth>
21902 
            </field>
21903 
          </fields>
21904 
        </register>
21905 
        <register>
21906 
          <name>DHR8R1</name>
21907 
          <displayName>DHR8R1</displayName>
21908 
          <description>DAC channel1 8-bit right aligned data
21909 
          holding register (DAC_DHR8R1)</description>
21910 
          <addressOffset>0x10</addressOffset>
21911 
          <size>0x20</size>
21912 
          <access>read-write</access>
21913 
          <resetValue>0x00000000</resetValue>
21914 
          <fields>
21915 
            <field>
21916 
              <name>DACC1DHR</name>
21917 
              <description>DAC channel1 8-bit right-aligned
21918 
              data</description>
21919 
              <bitOffset>0</bitOffset>
21920 
              <bitWidth>8</bitWidth>
21921 
            </field>
21922 
          </fields>
21923 
        </register>
21924 
        <register>
21925 
          <name>DHR12R2</name>
21926 
          <displayName>DHR12R2</displayName>
21927 
          <description>DAC channel2 12-bit right aligned data
21928 
          holding register (DAC_DHR12R2)</description>
21929 
          <addressOffset>0x14</addressOffset>
21930 
          <size>0x20</size>
21931 
          <access>read-write</access>
21932 
          <resetValue>0x00000000</resetValue>
21933 
          <fields>
21934 
            <field>
21935 
              <name>DACC2DHR</name>
21936 
              <description>DAC channel2 12-bit right-aligned
21937 
              data</description>
21938 
              <bitOffset>0</bitOffset>
21939 
              <bitWidth>12</bitWidth>
21940 
            </field>
21941 
          </fields>
21942 
        </register>
21943 
        <register>
21944 
          <name>DHR12L2</name>
21945 
          <displayName>DHR12L2</displayName>
21946 
          <description>DAC channel2 12-bit left aligned data
21947 
          holding register (DAC_DHR12L2)</description>
21948 
          <addressOffset>0x18</addressOffset>
21949 
          <size>0x20</size>
21950 
          <access>read-write</access>
21951 
          <resetValue>0x00000000</resetValue>
21952 
          <fields>
21953 
            <field>
21954 
              <name>DACC2DHR</name>
21955 
              <description>DAC channel2 12-bit left-aligned
21956 
              data</description>
21957 
              <bitOffset>4</bitOffset>
21958 
              <bitWidth>12</bitWidth>
21959 
            </field>
21960 
          </fields>
21961 
        </register>
21962 
        <register>
21963 
          <name>DHR8R2</name>
21964 
          <displayName>DHR8R2</displayName>
21965 
          <description>DAC channel2 8-bit right-aligned data
21966 
          holding register (DAC_DHR8R2)</description>
21967 
          <addressOffset>0x1C</addressOffset>
21968 
          <size>0x20</size>
21969 
          <access>read-write</access>
21970 
          <resetValue>0x00000000</resetValue>
21971 
          <fields>
21972 
            <field>
21973 
              <name>DACC2DHR</name>
21974 
              <description>DAC channel2 8-bit right-aligned
21975 
              data</description>
21976 
              <bitOffset>0</bitOffset>
21977 
              <bitWidth>8</bitWidth>
21978 
            </field>
21979 
          </fields>
21980 
        </register>
21981 
        <register>
21982 
          <name>DHR12RD</name>
21983 
          <displayName>DHR12RD</displayName>
21984 
          <description>Dual DAC 12-bit right-aligned data holding
21985 
          register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12
21986 
          Reserved</description>
21987 
          <addressOffset>0x20</addressOffset>
21988 
          <size>0x20</size>
21989 
          <access>read-write</access>
21990 
          <resetValue>0x00000000</resetValue>
21991 
          <fields>
21992 
            <field>
21993 
              <name>DACC1DHR</name>
21994 
              <description>DAC channel1 12-bit right-aligned
21995 
              data</description>
21996 
              <bitOffset>0</bitOffset>
21997 
              <bitWidth>12</bitWidth>
21998 
            </field>
21999 
            <field>
22000 
              <name>DACC2DHR</name>
22001 
              <description>DAC channel2 12-bit right-aligned
22002 
              data</description>
22003 
              <bitOffset>16</bitOffset>
22004 
              <bitWidth>12</bitWidth>
22005 
            </field>
22006 
          </fields>
22007 
        </register>
22008 
        <register>
22009 
          <name>DHR12LD</name>
22010 
          <displayName>DHR12LD</displayName>
22011 
          <description>DUAL DAC 12-bit left aligned data holding
22012 
          register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0
22013 
          Reserved</description>
22014 
          <addressOffset>0x24</addressOffset>
22015 
          <size>0x20</size>
22016 
          <access>read-write</access>
22017 
          <resetValue>0x00000000</resetValue>
22018 
          <fields>
22019 
            <field>
22020 
              <name>DACC1DHR</name>
22021 
              <description>DAC channel1 12-bit left-aligned
22022 
              data</description>
22023 
              <bitOffset>4</bitOffset>
22024 
              <bitWidth>12</bitWidth>
22025 
            </field>
22026 
            <field>
22027 
              <name>DACC2DHR</name>
22028 
              <description>DAC channel2 12-bit right-aligned
22029 
              data</description>
22030 
              <bitOffset>20</bitOffset>
22031 
              <bitWidth>12</bitWidth>
22032 
            </field>
22033 
          </fields>
22034 
        </register>
22035 
        <register>
22036 
          <name>DHR8RD</name>
22037 
          <displayName>DHR8RD</displayName>
22038 
          <description>DUAL DAC 8-bit right aligned data holding
22039 
          register (DAC_DHR8RD), Bits 31:16 Reserved</description>
22040 
          <addressOffset>0x28</addressOffset>
22041 
          <size>0x20</size>
22042 
          <access>read-write</access>
22043 
          <resetValue>0x00000000</resetValue>
22044 
          <fields>
22045 
            <field>
22046 
              <name>DACC1DHR</name>
22047 
              <description>DAC channel1 8-bit right-aligned
22048 
              data</description>
22049 
              <bitOffset>0</bitOffset>
22050 
              <bitWidth>8</bitWidth>
22051 
            </field>
22052 
            <field>
22053 
              <name>DACC2DHR</name>
22054 
              <description>DAC channel2 8-bit right-aligned
22055 
              data</description>
22056 
              <bitOffset>8</bitOffset>
22057 
              <bitWidth>8</bitWidth>
22058 
            </field>
22059 
          </fields>
22060 
        </register>
22061 
        <register>
22062 
          <name>DOR1</name>
22063 
          <displayName>DOR1</displayName>
22064 
          <description>DAC channel1 data output register
22065 
          (DAC_DOR1)</description>
22066 
          <addressOffset>0x2C</addressOffset>
22067 
          <size>0x20</size>
22068 
          <access>read-only</access>
22069 
          <resetValue>0x00000000</resetValue>
22070 
          <fields>
22071 
            <field>
22072 
              <name>DACC1DOR</name>
22073 
              <description>DAC channel1 data output</description>
22074 
              <bitOffset>0</bitOffset>
22075 
              <bitWidth>12</bitWidth>
22076 
            </field>
22077 
          </fields>
22078 
        </register>
22079 
        <register>
22080 
          <name>DOR2</name>
22081 
          <displayName>DOR2</displayName>
22082 
          <description>DAC channel2 data output register
22083 
          (DAC_DOR2)</description>
22084 
          <addressOffset>0x30</addressOffset>
22085 
          <size>0x20</size>
22086 
          <access>read-only</access>
22087 
          <resetValue>0x00000000</resetValue>
22088 
          <fields>
22089 
            <field>
22090 
              <name>DACC2DOR</name>
22091 
              <description>DAC channel2 data output</description>
22092 
              <bitOffset>0</bitOffset>
22093 
              <bitWidth>12</bitWidth>
22094 
            </field>
22095 
          </fields>
22096 
        </register>
22097 
      </registers>
22098 
    </peripheral>
22099 
    <peripheral>
22100 
      <name>DBG</name>
22101 
      <description>Debug support</description>
22102 
      <groupName>DBG</groupName>
22103 
      <baseAddress>0xE0042000</baseAddress>
22104 
      <addressBlock>
22105 
        <offset>0x0</offset>
22106 
        <size>0x400</size>
22107 
        <usage>registers</usage>
22108 
      </addressBlock>
22109 
      <registers>
22110 
        <register>
22111 
          <name>IDCODE</name>
22112 
          <displayName>IDCODE</displayName>
22113 
          <description>DBGMCU_IDCODE</description>
22114 
          <addressOffset>0x0</addressOffset>
22115 
          <size>0x20</size>
22116 
          <access>read-only</access>
22117 
          <resetValue>0x0</resetValue>
22118 
          <fields>
22119 
            <field>
22120 
              <name>DEV_ID</name>
22121 
              <description>DEV_ID</description>
22122 
              <bitOffset>0</bitOffset>
22123 
              <bitWidth>12</bitWidth>
22124 
            </field>
22125 
            <field>
22126 
              <name>REV_ID</name>
22127 
              <description>REV_ID</description>
22128 
              <bitOffset>16</bitOffset>
22129 
              <bitWidth>16</bitWidth>
22130 
            </field>
22131 
          </fields>
22132 
        </register>
22133 
        <register>
22134 
          <name>CR</name>
22135 
          <displayName>CR</displayName>
22136 
          <description>DBGMCU_CR</description>
22137 
          <addressOffset>0x4</addressOffset>
22138 
          <size>0x20</size>
22139 
          <access>read-write</access>
22140 
          <resetValue>0x0</resetValue>
22141 
          <fields>
22142 
            <field>
22143 
              <name>DBG_SLEEP</name>
22144 
              <description>DBG_SLEEP</description>
22145 
              <bitOffset>0</bitOffset>
22146 
              <bitWidth>1</bitWidth>
22147 
            </field>
22148 
            <field>
22149 
              <name>DBG_STOP</name>
22150 
              <description>DBG_STOP</description>
22151 
              <bitOffset>1</bitOffset>
22152 
              <bitWidth>1</bitWidth>
22153 
            </field>
22154 
            <field>
22155 
              <name>DBG_STANDBY</name>
22156 
              <description>DBG_STANDBY</description>
22157 
              <bitOffset>2</bitOffset>
22158 
              <bitWidth>1</bitWidth>
22159 
            </field>
22160 
            <field>
22161 
              <name>TRACE_IOEN</name>
22162 
              <description>TRACE_IOEN</description>
22163 
              <bitOffset>5</bitOffset>
22164 
              <bitWidth>1</bitWidth>
22165 
            </field>
22166 
            <field>
22167 
              <name>TRACE_MODE</name>
22168 
              <description>TRACE_MODE</description>
22169 
              <bitOffset>6</bitOffset>
22170 
              <bitWidth>2</bitWidth>
22171 
            </field>
22172 
            <field>
22173 
              <name>DBG_IWDG_STOP</name>
22174 
              <description>DBG_IWDG_STOP</description>
22175 
              <bitOffset>8</bitOffset>
22176 
              <bitWidth>1</bitWidth>
22177 
            </field>
22178 
            <field>
22179 
              <name>DBG_WWDG_STOP</name>
22180 
              <description>DBG_WWDG_STOP</description>
22181 
              <bitOffset>9</bitOffset>
22182 
              <bitWidth>1</bitWidth>
22183 
            </field>
22184 
            <field>
22185 
              <name>DBG_TIM1_STOP</name>
22186 
              <description>DBG_TIM1_STOP</description>
22187 
              <bitOffset>10</bitOffset>
22188 
              <bitWidth>1</bitWidth>
22189 
            </field>
22190 
            <field>
22191 
              <name>DBG_TIM2_STOP</name>
22192 
              <description>DBG_TIM2_STOP</description>
22193 
              <bitOffset>11</bitOffset>
22194 
              <bitWidth>1</bitWidth>
22195 
            </field>
22196 
            <field>
22197 
              <name>DBG_TIM3_STOP</name>
22198 
              <description>DBG_TIM3_STOP</description>
22199 
              <bitOffset>12</bitOffset>
22200 
              <bitWidth>1</bitWidth>
22201 
            </field>
22202 
            <field>
22203 
              <name>DBG_TIM4_STOP</name>
22204 
              <description>DBG_TIM4_STOP</description>
22205 
              <bitOffset>13</bitOffset>
22206 
              <bitWidth>1</bitWidth>
22207 
            </field>
22208 
            <field>
22209 
              <name>DBG_CAN1_STOP</name>
22210 
              <description>DBG_CAN1_STOP</description>
22211 
              <bitOffset>14</bitOffset>
22212 
              <bitWidth>1</bitWidth>
22213 
            </field>
22214 
            <field>
22215 
              <name>DBG_I2C1_SMBUS_TIMEOUT</name>
22216 
              <description>DBG_I2C1_SMBUS_TIMEOUT</description>
22217 
              <bitOffset>15</bitOffset>
22218 
              <bitWidth>1</bitWidth>
22219 
            </field>
22220 
            <field>
22221 
              <name>DBG_I2C2_SMBUS_TIMEOUT</name>
22222 
              <description>DBG_I2C2_SMBUS_TIMEOUT</description>
22223 
              <bitOffset>16</bitOffset>
22224 
              <bitWidth>1</bitWidth>
22225 
            </field>
22226 
            <field>
22227 
              <name>DBG_TIM8_STOP</name>
22228 
              <description>DBG_TIM8_STOP</description>
22229 
              <bitOffset>17</bitOffset>
22230 
              <bitWidth>1</bitWidth>
22231 
            </field>
22232 
            <field>
22233 
              <name>DBG_TIM5_STOP</name>
22234 
              <description>DBG_TIM5_STOP</description>
22235 
              <bitOffset>18</bitOffset>
22236 
              <bitWidth>1</bitWidth>
22237 
            </field>
22238 
            <field>
22239 
              <name>DBG_TIM6_STOP</name>
22240 
              <description>DBG_TIM6_STOP</description>
22241 
              <bitOffset>19</bitOffset>
22242 
              <bitWidth>1</bitWidth>
22243 
            </field>
22244 
            <field>
22245 
              <name>DBG_TIM7_STOP</name>
22246 
              <description>DBG_TIM7_STOP</description>
22247 
              <bitOffset>20</bitOffset>
22248 
              <bitWidth>1</bitWidth>
22249 
            </field>
22250 
            <field>
22251 
              <name>DBG_CAN2_STOP</name>
22252 
              <description>DBG_CAN2_STOP</description>
22253 
              <bitOffset>21</bitOffset>
22254 
              <bitWidth>1</bitWidth>
22255 
            </field>
22256 
          </fields>
22257 
        </register>
22258 
      </registers>
22259 
    </peripheral>
22260 
    <peripheral>
22261 
      <name>UART4</name>
22262 
      <description>Universal asynchronous receiver
22263 
      transmitter</description>
22264 
      <groupName>USART</groupName>
22265 
      <baseAddress>0x40004C00</baseAddress>
22266 
      <addressBlock>
22267 
        <offset>0x0</offset>
22268 
        <size>0x400</size>
22269 
        <usage>registers</usage>
22270 
      </addressBlock>
22271 
      <interrupt>
22272 
        <name>UART4</name>
22273 
        <description>UART4 global interrupt</description>
22274 
        <value>52</value>
22275 
      </interrupt>
22276 
      <registers>
22277 
        <register>
22278 
          <name>SR</name>
22279 
          <displayName>SR</displayName>
22280 
          <description>UART4_SR</description>
22281 
          <addressOffset>0x0</addressOffset>
22282 
          <size>0x20</size>
22283 
          <resetValue>0x0</resetValue>
22284 
          <fields>
22285 
            <field>
22286 
              <name>PE</name>
22287 
              <description>Parity error</description>
22288 
              <bitOffset>0</bitOffset>
22289 
              <bitWidth>1</bitWidth>
22290 
              <access>read-only</access>
22291 
            </field>
22292 
            <field>
22293 
              <name>FE</name>
22294 
              <description>Framing error</description>
22295 
              <bitOffset>1</bitOffset>
22296 
              <bitWidth>1</bitWidth>
22297 
              <access>read-only</access>
22298 
            </field>
22299 
            <field>
22300 
              <name>NE</name>
22301 
              <description>Noise error flag</description>
22302 
              <bitOffset>2</bitOffset>
22303 
              <bitWidth>1</bitWidth>
22304 
              <access>read-only</access>
22305 
            </field>
22306 
            <field>
22307 
              <name>ORE</name>
22308 
              <description>Overrun error</description>
22309 
              <bitOffset>3</bitOffset>
22310 
              <bitWidth>1</bitWidth>
22311 
              <access>read-only</access>
22312 
            </field>
22313 
            <field>
22314 
              <name>IDLE</name>
22315 
              <description>IDLE line detected</description>
22316 
              <bitOffset>4</bitOffset>
22317 
              <bitWidth>1</bitWidth>
22318 
              <access>read-only</access>
22319 
            </field>
22320 
            <field>
22321 
              <name>RXNE</name>
22322 
              <description>Read data register not
22323 
              empty</description>
22324 
              <bitOffset>5</bitOffset>
22325 
              <bitWidth>1</bitWidth>
22326 
              <access>read-write</access>
22327 
            </field>
22328 
            <field>
22329 
              <name>TC</name>
22330 
              <description>Transmission complete</description>
22331 
              <bitOffset>6</bitOffset>
22332 
              <bitWidth>1</bitWidth>
22333 
              <access>read-write</access>
22334 
            </field>
22335 
            <field>
22336 
              <name>TXE</name>
22337 
              <description>Transmit data register
22338 
              empty</description>
22339 
              <bitOffset>7</bitOffset>
22340 
              <bitWidth>1</bitWidth>
22341 
              <access>read-only</access>
22342 
            </field>
22343 
            <field>
22344 
              <name>LBD</name>
22345 
              <description>LIN break detection flag</description>
22346 
              <bitOffset>8</bitOffset>
22347 
              <bitWidth>1</bitWidth>
22348 
              <access>read-write</access>
22349 
            </field>
22350 
          </fields>
22351 
        </register>
22352 
        <register>
22353 
          <name>DR</name>
22354 
          <displayName>DR</displayName>
22355 
          <description>UART4_DR</description>
22356 
          <addressOffset>0x4</addressOffset>
22357 
          <size>0x20</size>
22358 
          <access>read-write</access>
22359 
          <resetValue>0x0</resetValue>
22360 
          <fields>
22361 
            <field>
22362 
              <name>DR</name>
22363 
              <description>DR</description>
22364 
              <bitOffset>0</bitOffset>
22365 
              <bitWidth>9</bitWidth>
22366 
            </field>
22367 
          </fields>
22368 
        </register>
22369 
        <register>
22370 
          <name>BRR</name>
22371 
          <displayName>BRR</displayName>
22372 
          <description>UART4_BRR</description>
22373 
          <addressOffset>0x8</addressOffset>
22374 
          <size>0x20</size>
22375 
          <access>read-write</access>
22376 
          <resetValue>0x0</resetValue>
22377 
          <fields>
22378 
            <field>
22379 
              <name>DIV_Fraction</name>
22380 
              <description>DIV_Fraction</description>
22381 
              <bitOffset>0</bitOffset>
22382 
              <bitWidth>4</bitWidth>
22383 
            </field>
22384 
            <field>
22385 
              <name>DIV_Mantissa</name>
22386 
              <description>DIV_Mantissa</description>
22387 
              <bitOffset>4</bitOffset>
22388 
              <bitWidth>12</bitWidth>
22389 
            </field>
22390 
          </fields>
22391 
        </register>
22392 
        <register>
22393 
          <name>CR1</name>
22394 
          <displayName>CR1</displayName>
22395 
          <description>UART4_CR1</description>
22396 
          <addressOffset>0xC</addressOffset>
22397 
          <size>0x20</size>
22398 
          <access>read-write</access>
22399 
          <resetValue>0x0</resetValue>
22400 
          <fields>
22401 
            <field>
22402 
              <name>SBK</name>
22403 
              <description>Send break</description>
22404 
              <bitOffset>0</bitOffset>
22405 
              <bitWidth>1</bitWidth>
22406 
            </field>
22407 
            <field>
22408 
              <name>RWU</name>
22409 
              <description>Receiver wakeup</description>
22410 
              <bitOffset>1</bitOffset>
22411 
              <bitWidth>1</bitWidth>
22412 
            </field>
22413 
            <field>
22414 
              <name>RE</name>
22415 
              <description>Receiver enable</description>
22416 
              <bitOffset>2</bitOffset>
22417 
              <bitWidth>1</bitWidth>
22418 
            </field>
22419 
            <field>
22420 
              <name>TE</name>
22421 
              <description>Transmitter enable</description>
22422 
              <bitOffset>3</bitOffset>
22423 
              <bitWidth>1</bitWidth>
22424 
            </field>
22425 
            <field>
22426 
              <name>IDLEIE</name>
22427 
              <description>IDLE interrupt enable</description>
22428 
              <bitOffset>4</bitOffset>
22429 
              <bitWidth>1</bitWidth>
22430 
            </field>
22431 
            <field>
22432 
              <name>RXNEIE</name>
22433 
              <description>RXNE interrupt enable</description>
22434 
              <bitOffset>5</bitOffset>
22435 
              <bitWidth>1</bitWidth>
22436 
            </field>
22437 
            <field>
22438 
              <name>TCIE</name>
22439 
              <description>Transmission complete interrupt
22440 
              enable</description>
22441 
              <bitOffset>6</bitOffset>
22442 
              <bitWidth>1</bitWidth>
22443 
            </field>
22444 
            <field>
22445 
              <name>TXEIE</name>
22446 
              <description>TXE interrupt enable</description>
22447 
              <bitOffset>7</bitOffset>
22448 
              <bitWidth>1</bitWidth>
22449 
            </field>
22450 
            <field>
22451 
              <name>PEIE</name>
22452 
              <description>PE interrupt enable</description>
22453 
              <bitOffset>8</bitOffset>
22454 
              <bitWidth>1</bitWidth>
22455 
            </field>
22456 
            <field>
22457 
              <name>PS</name>
22458 
              <description>Parity selection</description>
22459 
              <bitOffset>9</bitOffset>
22460 
              <bitWidth>1</bitWidth>
22461 
            </field>
22462 
            <field>
22463 
              <name>PCE</name>
22464 
              <description>Parity control enable</description>
22465 
              <bitOffset>10</bitOffset>
22466 
              <bitWidth>1</bitWidth>
22467 
            </field>
22468 
            <field>
22469 
              <name>WAKE</name>
22470 
              <description>Wakeup method</description>
22471 
              <bitOffset>11</bitOffset>
22472 
              <bitWidth>1</bitWidth>
22473 
            </field>
22474 
            <field>
22475 
              <name>M</name>
22476 
              <description>Word length</description>
22477 
              <bitOffset>12</bitOffset>
22478 
              <bitWidth>1</bitWidth>
22479 
            </field>
22480 
            <field>
22481 
              <name>UE</name>
22482 
              <description>USART enable</description>
22483 
              <bitOffset>13</bitOffset>
22484 
              <bitWidth>1</bitWidth>
22485 
            </field>
22486 
          </fields>
22487 
        </register>
22488 
        <register>
22489 
          <name>CR2</name>
22490 
          <displayName>CR2</displayName>
22491 
          <description>UART4_CR2</description>
22492 
          <addressOffset>0x10</addressOffset>
22493 
          <size>0x20</size>
22494 
          <access>read-write</access>
22495 
          <resetValue>0x0</resetValue>
22496 
          <fields>
22497 
            <field>
22498 
              <name>ADD</name>
22499 
              <description>Address of the USART node</description>
22500 
              <bitOffset>0</bitOffset>
22501 
              <bitWidth>4</bitWidth>
22502 
            </field>
22503 
            <field>
22504 
              <name>LBDL</name>
22505 
              <description>lin break detection length</description>
22506 
              <bitOffset>5</bitOffset>
22507 
              <bitWidth>1</bitWidth>
22508 
            </field>
22509 
            <field>
22510 
              <name>LBDIE</name>
22511 
              <description>LIN break detection interrupt
22512 
              enable</description>
22513 
              <bitOffset>6</bitOffset>
22514 
              <bitWidth>1</bitWidth>
22515 
            </field>
22516 
            <field>
22517 
              <name>STOP</name>
22518 
              <description>STOP bits</description>
22519 
              <bitOffset>12</bitOffset>
22520 
              <bitWidth>2</bitWidth>
22521 
            </field>
22522 
            <field>
22523 
              <name>LINEN</name>
22524 
              <description>LIN mode enable</description>
22525 
              <bitOffset>14</bitOffset>
22526 
              <bitWidth>1</bitWidth>
22527 
            </field>
22528 
          </fields>
22529 
        </register>
22530 
        <register>
22531 
          <name>CR3</name>
22532 
          <displayName>CR3</displayName>
22533 
          <description>UART4_CR3</description>
22534 
          <addressOffset>0x14</addressOffset>
22535 
          <size>0x20</size>
22536 
          <access>read-write</access>
22537 
          <resetValue>0x0</resetValue>
22538 
          <fields>
22539 
            <field>
22540 
              <name>EIE</name>
22541 
              <description>Error interrupt enable</description>
22542 
              <bitOffset>0</bitOffset>
22543 
              <bitWidth>1</bitWidth>
22544 
            </field>
22545 
            <field>
22546 
              <name>IREN</name>
22547 
              <description>IrDA mode enable</description>
22548 
              <bitOffset>1</bitOffset>
22549 
              <bitWidth>1</bitWidth>
22550 
            </field>
22551 
            <field>
22552 
              <name>IRLP</name>
22553 
              <description>IrDA low-power</description>
22554 
              <bitOffset>2</bitOffset>
22555 
              <bitWidth>1</bitWidth>
22556 
            </field>
22557 
            <field>
22558 
              <name>HDSEL</name>
22559 
              <description>Half-duplex selection</description>
22560 
              <bitOffset>3</bitOffset>
22561 
              <bitWidth>1</bitWidth>
22562 
            </field>
22563 
            <field>
22564 
              <name>DMAR</name>
22565 
              <description>DMA enable receiver</description>
22566 
              <bitOffset>6</bitOffset>
22567 
              <bitWidth>1</bitWidth>
22568 
            </field>
22569 
            <field>
22570 
              <name>DMAT</name>
22571 
              <description>DMA enable transmitter</description>
22572 
              <bitOffset>7</bitOffset>
22573 
              <bitWidth>1</bitWidth>
22574 
            </field>
22575 
          </fields>
22576 
        </register>
22577 
      </registers>
22578 
    </peripheral>
22579 
    <peripheral>
22580 
      <name>UART5</name>
22581 
      <description>Universal asynchronous receiver
22582 
      transmitter</description>
22583 
      <groupName>USART</groupName>
22584 
      <baseAddress>0x40005000</baseAddress>
22585 
      <addressBlock>
22586 
        <offset>0x0</offset>
22587 
        <size>0x400</size>
22588 
        <usage>registers</usage>
22589 
      </addressBlock>
22590 
      <interrupt>
22591 
        <name>UART5</name>
22592 
        <description>UART5 global interrupt</description>
22593 
        <value>53</value>
22594 
      </interrupt>
22595 
      <registers>
22596 
        <register>
22597 
          <name>SR</name>
22598 
          <displayName>SR</displayName>
22599 
          <description>UART4_SR</description>
22600 
          <addressOffset>0x0</addressOffset>
22601 
          <size>0x20</size>
22602 
          <resetValue>0x0</resetValue>
22603 
          <fields>
22604 
            <field>
22605 
              <name>PE</name>
22606 
              <description>PE</description>
22607 
              <bitOffset>0</bitOffset>
22608 
              <bitWidth>1</bitWidth>
22609 
              <access>read-only</access>
22610 
            </field>
22611 
            <field>
22612 
              <name>FE</name>
22613 
              <description>FE</description>
22614 
              <bitOffset>1</bitOffset>
22615 
              <bitWidth>1</bitWidth>
22616 
              <access>read-only</access>
22617 
            </field>
22618 
            <field>
22619 
              <name>NE</name>
22620 
              <description>NE</description>
22621 
              <bitOffset>2</bitOffset>
22622 
              <bitWidth>1</bitWidth>
22623 
              <access>read-only</access>
22624 
            </field>
22625 
            <field>
22626 
              <name>ORE</name>
22627 
              <description>ORE</description>
22628 
              <bitOffset>3</bitOffset>
22629 
              <bitWidth>1</bitWidth>
22630 
              <access>read-only</access>
22631 
            </field>
22632 
            <field>
22633 
              <name>IDLE</name>
22634 
              <description>IDLE</description>
22635 
              <bitOffset>4</bitOffset>
22636 
              <bitWidth>1</bitWidth>
22637 
              <access>read-only</access>
22638 
            </field>
22639 
            <field>
22640 
              <name>RXNE</name>
22641 
              <description>RXNE</description>
22642 
              <bitOffset>5</bitOffset>
22643 
              <bitWidth>1</bitWidth>
22644 
              <access>read-write</access>
22645 
            </field>
22646 
            <field>
22647 
              <name>TC</name>
22648 
              <description>TC</description>
22649 
              <bitOffset>6</bitOffset>
22650 
              <bitWidth>1</bitWidth>
22651 
              <access>read-write</access>
22652 
            </field>
22653 
            <field>
22654 
              <name>TXE</name>
22655 
              <description>TXE</description>
22656 
              <bitOffset>7</bitOffset>
22657 
              <bitWidth>1</bitWidth>
22658 
              <access>read-only</access>
22659 
            </field>
22660 
            <field>
22661 
              <name>LBD</name>
22662 
              <description>LBD</description>
22663 
              <bitOffset>8</bitOffset>
22664 
              <bitWidth>1</bitWidth>
22665 
              <access>read-write</access>
22666 
            </field>
22667 
          </fields>
22668 
        </register>
22669 
        <register>
22670 
          <name>DR</name>
22671 
          <displayName>DR</displayName>
22672 
          <description>UART4_DR</description>
22673 
          <addressOffset>0x4</addressOffset>
22674 
          <size>0x20</size>
22675 
          <access>read-write</access>
22676 
          <resetValue>0x0</resetValue>
22677 
          <fields>
22678 
            <field>
22679 
              <name>DR</name>
22680 
              <description>DR</description>
22681 
              <bitOffset>0</bitOffset>
22682 
              <bitWidth>9</bitWidth>
22683 
            </field>
22684 
          </fields>
22685 
        </register>
22686 
        <register>
22687 
          <name>BRR</name>
22688 
          <displayName>BRR</displayName>
22689 
          <description>UART4_BRR</description>
22690 
          <addressOffset>0x8</addressOffset>
22691 
          <size>0x20</size>
22692 
          <access>read-write</access>
22693 
          <resetValue>0x0</resetValue>
22694 
          <fields>
22695 
            <field>
22696 
              <name>DIV_Fraction</name>
22697 
              <description>DIV_Fraction</description>
22698 
              <bitOffset>0</bitOffset>
22699 
              <bitWidth>4</bitWidth>
22700 
            </field>
22701 
            <field>
22702 
              <name>DIV_Mantissa</name>
22703 
              <description>DIV_Mantissa</description>
22704 
              <bitOffset>4</bitOffset>
22705 
              <bitWidth>12</bitWidth>
22706 
            </field>
22707 
          </fields>
22708 
        </register>
22709 
        <register>
22710 
          <name>CR1</name>
22711 
          <displayName>CR1</displayName>
22712 
          <description>UART4_CR1</description>
22713 
          <addressOffset>0xC</addressOffset>
22714 
          <size>0x20</size>
22715 
          <access>read-write</access>
22716 
          <resetValue>0x0</resetValue>
22717 
          <fields>
22718 
            <field>
22719 
              <name>SBK</name>
22720 
              <description>SBK</description>
22721 
              <bitOffset>0</bitOffset>
22722 
              <bitWidth>1</bitWidth>
22723 
            </field>
22724 
            <field>
22725 
              <name>RWU</name>
22726 
              <description>RWU</description>
22727 
              <bitOffset>1</bitOffset>
22728 
              <bitWidth>1</bitWidth>
22729 
            </field>
22730 
            <field>
22731 
              <name>RE</name>
22732 
              <description>RE</description>
22733 
              <bitOffset>2</bitOffset>
22734 
              <bitWidth>1</bitWidth>
22735 
            </field>
22736 
            <field>
22737 
              <name>TE</name>
22738 
              <description>TE</description>
22739 
              <bitOffset>3</bitOffset>
22740 
              <bitWidth>1</bitWidth>
22741 
            </field>
22742 
            <field>
22743 
              <name>IDLEIE</name>
22744 
              <description>IDLEIE</description>
22745 
              <bitOffset>4</bitOffset>
22746 
              <bitWidth>1</bitWidth>
22747 
            </field>
22748 
            <field>
22749 
              <name>RXNEIE</name>
22750 
              <description>RXNEIE</description>
22751 
              <bitOffset>5</bitOffset>
22752 
              <bitWidth>1</bitWidth>
22753 
            </field>
22754 
            <field>
22755 
              <name>TCIE</name>
22756 
              <description>TCIE</description>
22757 
              <bitOffset>6</bitOffset>
22758 
              <bitWidth>1</bitWidth>
22759 
            </field>
22760 
            <field>
22761 
              <name>TXEIE</name>
22762 
              <description>TXEIE</description>
22763 
              <bitOffset>7</bitOffset>
22764 
              <bitWidth>1</bitWidth>
22765 
            </field>
22766 
            <field>
22767 
              <name>PEIE</name>
22768 
              <description>PEIE</description>
22769 
              <bitOffset>8</bitOffset>
22770 
              <bitWidth>1</bitWidth>
22771 
            </field>
22772 
            <field>
22773 
              <name>PS</name>
22774 
              <description>PS</description>
22775 
              <bitOffset>9</bitOffset>
22776 
              <bitWidth>1</bitWidth>
22777 
            </field>
22778 
            <field>
22779 
              <name>PCE</name>
22780 
              <description>PCE</description>
22781 
              <bitOffset>10</bitOffset>
22782 
              <bitWidth>1</bitWidth>
22783 
            </field>
22784 
            <field>
22785 
              <name>WAKE</name>
22786 
              <description>WAKE</description>
22787 
              <bitOffset>11</bitOffset>
22788 
              <bitWidth>1</bitWidth>
22789 
            </field>
22790 
            <field>
22791 
              <name>M</name>
22792 
              <description>M</description>
22793 
              <bitOffset>12</bitOffset>
22794 
              <bitWidth>1</bitWidth>
22795 
            </field>
22796 
            <field>
22797 
              <name>UE</name>
22798 
              <description>UE</description>
22799 
              <bitOffset>13</bitOffset>
22800 
              <bitWidth>1</bitWidth>
22801 
            </field>
22802 
          </fields>
22803 
        </register>
22804 
        <register>
22805 
          <name>CR2</name>
22806 
          <displayName>CR2</displayName>
22807 
          <description>UART4_CR2</description>
22808 
          <addressOffset>0x10</addressOffset>
22809 
          <size>0x20</size>
22810 
          <access>read-write</access>
22811 
          <resetValue>0x0</resetValue>
22812 
          <fields>
22813 
            <field>
22814 
              <name>ADD</name>
22815 
              <description>ADD</description>
22816 
              <bitOffset>0</bitOffset>
22817 
              <bitWidth>4</bitWidth>
22818 
            </field>
22819 
            <field>
22820 
              <name>LBDL</name>
22821 
              <description>LBDL</description>
22822 
              <bitOffset>5</bitOffset>
22823 
              <bitWidth>1</bitWidth>
22824 
            </field>
22825 
            <field>
22826 
              <name>LBDIE</name>
22827 
              <description>LBDIE</description>
22828 
              <bitOffset>6</bitOffset>
22829 
              <bitWidth>1</bitWidth>
22830 
            </field>
22831 
            <field>
22832 
              <name>STOP</name>
22833 
              <description>STOP</description>
22834 
              <bitOffset>12</bitOffset>
22835 
              <bitWidth>2</bitWidth>
22836 
            </field>
22837 
            <field>
22838 
              <name>LINEN</name>
22839 
              <description>LINEN</description>
22840 
              <bitOffset>14</bitOffset>
22841 
              <bitWidth>1</bitWidth>
22842 
            </field>
22843 
          </fields>
22844 
        </register>
22845 
        <register>
22846 
          <name>CR3</name>
22847 
          <displayName>CR3</displayName>
22848 
          <description>UART4_CR3</description>
22849 
          <addressOffset>0x14</addressOffset>
22850 
          <size>0x20</size>
22851 
          <access>read-write</access>
22852 
          <resetValue>0x0</resetValue>
22853 
          <fields>
22854 
            <field>
22855 
              <name>EIE</name>
22856 
              <description>Error interrupt enable</description>
22857 
              <bitOffset>0</bitOffset>
22858 
              <bitWidth>1</bitWidth>
22859 
            </field>
22860 
            <field>
22861 
              <name>IREN</name>
22862 
              <description>IrDA mode enable</description>
22863 
              <bitOffset>1</bitOffset>
22864 
              <bitWidth>1</bitWidth>
22865 
            </field>
22866 
            <field>
22867 
              <name>IRLP</name>
22868 
              <description>IrDA low-power</description>
22869 
              <bitOffset>2</bitOffset>
22870 
              <bitWidth>1</bitWidth>
22871 
            </field>
22872 
            <field>
22873 
              <name>HDSEL</name>
22874 
              <description>Half-duplex selection</description>
22875 
              <bitOffset>3</bitOffset>
22876 
              <bitWidth>1</bitWidth>
22877 
            </field>
22878 
            <field>
22879 
              <name>DMAT</name>
22880 
              <description>DMA enable transmitter</description>
22881 
              <bitOffset>7</bitOffset>
22882 
              <bitWidth>1</bitWidth>
22883 
            </field>
22884 
          </fields>
22885 
        </register>
22886 
      </registers>
22887 
    </peripheral>
22888 
    <peripheral>
22889 
      <name>CRC</name>
22890 
      <description>CRC calculation unit</description>
22891 
      <groupName>CRC</groupName>
22892 
      <baseAddress>0x40023000</baseAddress>
22893 
      <addressBlock>
22894 
        <offset>0x0</offset>
22895 
        <size>0x400</size>
22896 
        <usage>registers</usage>
22897 
      </addressBlock>
22898 
      <registers>
22899 
        <register>
22900 
          <name>DR</name>
22901 
          <displayName>DR</displayName>
22902 
          <description>Data register</description>
22903 
          <addressOffset>0x0</addressOffset>
22904 
          <size>0x20</size>
22905 
          <access>read-write</access>
22906 
          <resetValue>0xFFFFFFFF</resetValue>
22907 
          <fields>
22908 
            <field>
22909 
              <name>DR</name>
22910 
              <description>Data Register</description>
22911 
              <bitOffset>0</bitOffset>
22912 
              <bitWidth>32</bitWidth>
22913 
            </field>
22914 
          </fields>
22915 
        </register>
22916 
        <register>
22917 
          <name>IDR</name>
22918 
          <displayName>IDR</displayName>
22919 
          <description>Independent Data register</description>
22920 
          <addressOffset>0x4</addressOffset>
22921 
          <size>0x20</size>
22922 
          <access>read-write</access>
22923 
          <resetValue>0x00000000</resetValue>
22924 
          <fields>
22925 
            <field>
22926 
              <name>IDR</name>
22927 
              <description>Independent Data register</description>
22928 
              <bitOffset>0</bitOffset>
22929 
              <bitWidth>8</bitWidth>
22930 
            </field>
22931 
          </fields>
22932 
        </register>
22933 
        <register>
22934 
          <name>CR</name>
22935 
          <displayName>CR</displayName>
22936 
          <description>Control register</description>
22937 
          <addressOffset>0x8</addressOffset>
22938 
          <size>0x20</size>
22939 
          <access>write-only</access>
22940 
          <resetValue>0x00000000</resetValue>
22941 
          <fields>
22942 
            <field>
22943 
              <name>RESET</name>
22944 
              <description>Reset bit</description>
22945 
              <bitOffset>0</bitOffset>
22946 
              <bitWidth>1</bitWidth>
22947 
            </field>
22948 
          </fields>
22949 
        </register>
22950 
      </registers>
22951 
    </peripheral>
22952 
    <peripheral>
22953 
      <name>FLASH</name>
22954 
      <description>FLASH</description>
22955 
      <groupName>FLASH</groupName>
22956 
      <baseAddress>0x40022000</baseAddress>
22957 
      <addressBlock>
22958 
        <offset>0x0</offset>
22959 
        <size>0x400</size>
22960 
        <usage>registers</usage>
22961 
      </addressBlock>
22962 
      <interrupt>
22963 
        <name>FLASH</name>
22964 
        <description>Flash global interrupt</description>
22965 
        <value>4</value>
22966 
      </interrupt>
22967 
      <registers>
22968 
        <register>
22969 
          <name>ACR</name>
22970 
          <displayName>ACR</displayName>
22971 
          <description>Flash access control register</description>
22972 
          <addressOffset>0x0</addressOffset>
22973 
          <size>0x20</size>
22974 
          <resetValue>0x00000030</resetValue>
22975 
          <fields>
22976 
            <field>
22977 
              <name>LATENCY</name>
22978 
              <description>Latency</description>
22979 
              <bitOffset>0</bitOffset>
22980 
              <bitWidth>3</bitWidth>
22981 
              <access>read-write</access>
22982 
            </field>
22983 
            <field>
22984 
              <name>HLFCYA</name>
22985 
              <description>Flash half cycle access
22986 
              enable</description>
22987 
              <bitOffset>3</bitOffset>
22988 
              <bitWidth>1</bitWidth>
22989 
              <access>read-write</access>
22990 
            </field>
22991 
            <field>
22992 
              <name>PRFTBE</name>
22993 
              <description>Prefetch buffer enable</description>
22994 
              <bitOffset>4</bitOffset>
22995 
              <bitWidth>1</bitWidth>
22996 
              <access>read-write</access>
22997 
            </field>
22998 
            <field>
22999 
              <name>PRFTBS</name>
23000 
              <description>Prefetch buffer status</description>
23001 
              <bitOffset>5</bitOffset>
23002 
              <bitWidth>1</bitWidth>
23003 
              <access>read-only</access>
23004 
            </field>
23005 
          </fields>
23006 
        </register>
23007 
        <register>
23008 
          <name>KEYR</name>
23009 
          <displayName>KEYR</displayName>
23010 
          <description>Flash key register</description>
23011 
          <addressOffset>0x4</addressOffset>
23012 
          <size>0x20</size>
23013 
          <access>write-only</access>
23014 
          <resetValue>0x00000000</resetValue>
23015 
          <fields>
23016 
            <field>
23017 
              <name>KEY</name>
23018 
              <description>FPEC key</description>
23019 
              <bitOffset>0</bitOffset>
23020 
              <bitWidth>32</bitWidth>
23021 
            </field>
23022 
          </fields>
23023 
        </register>
23024 
        <register>
23025 
          <name>OPTKEYR</name>
23026 
          <displayName>OPTKEYR</displayName>
23027 
          <description>Flash option key register</description>
23028 
          <addressOffset>0x8</addressOffset>
23029 
          <size>0x20</size>
23030 
          <access>write-only</access>
23031 
          <resetValue>0x00000000</resetValue>
23032 
          <fields>
23033 
            <field>
23034 
              <name>OPTKEY</name>
23035 
              <description>Option byte key</description>
23036 
              <bitOffset>0</bitOffset>
23037 
              <bitWidth>32</bitWidth>
23038 
            </field>
23039 
          </fields>
23040 
        </register>
23041 
        <register>
23042 
          <name>SR</name>
23043 
          <displayName>SR</displayName>
23044 
          <description>Status register</description>
23045 
          <addressOffset>0xC</addressOffset>
23046 
          <size>0x20</size>
23047 
          <resetValue>0x00000000</resetValue>
23048 
          <fields>
23049 
            <field>
23050 
              <name>EOP</name>
23051 
              <description>End of operation</description>
23052 
              <bitOffset>5</bitOffset>
23053 
              <bitWidth>1</bitWidth>
23054 
              <access>read-write</access>
23055 
            </field>
23056 
            <field>
23057 
              <name>WRPRTERR</name>
23058 
              <description>Write protection error</description>
23059 
              <bitOffset>4</bitOffset>
23060 
              <bitWidth>1</bitWidth>
23061 
              <access>read-write</access>
23062 
            </field>
23063 
            <field>
23064 
              <name>PGERR</name>
23065 
              <description>Programming error</description>
23066 
              <bitOffset>2</bitOffset>
23067 
              <bitWidth>1</bitWidth>
23068 
              <access>read-write</access>
23069 
            </field>
23070 
            <field>
23071 
              <name>BSY</name>
23072 
              <description>Busy</description>
23073 
              <bitOffset>0</bitOffset>
23074 
              <bitWidth>1</bitWidth>
23075 
              <access>read-only</access>
23076 
            </field>
23077 
          </fields>
23078 
        </register>
23079 
        <register>
23080 
          <name>CR</name>
23081 
          <displayName>CR</displayName>
23082 
          <description>Control register</description>
23083 
          <addressOffset>0x10</addressOffset>
23084 
          <size>0x20</size>
23085 
          <access>read-write</access>
23086 
          <resetValue>0x00000080</resetValue>
23087 
          <fields>
23088 
            <field>
23089 
              <name>PG</name>
23090 
              <description>Programming</description>
23091 
              <bitOffset>0</bitOffset>
23092 
              <bitWidth>1</bitWidth>
23093 
            </field>
23094 
            <field>
23095 
              <name>PER</name>
23096 
              <description>Page Erase</description>
23097 
              <bitOffset>1</bitOffset>
23098 
              <bitWidth>1</bitWidth>
23099 
            </field>
23100 
            <field>
23101 
              <name>MER</name>
23102 
              <description>Mass Erase</description>
23103 
              <bitOffset>2</bitOffset>
23104 
              <bitWidth>1</bitWidth>
23105 
            </field>
23106 
            <field>
23107 
              <name>OPTPG</name>
23108 
              <description>Option byte programming</description>
23109 
              <bitOffset>4</bitOffset>
23110 
              <bitWidth>1</bitWidth>
23111 
            </field>
23112 
            <field>
23113 
              <name>OPTER</name>
23114 
              <description>Option byte erase</description>
23115 
              <bitOffset>5</bitOffset>
23116 
              <bitWidth>1</bitWidth>
23117 
            </field>
23118 
            <field>
23119 
              <name>STRT</name>
23120 
              <description>Start</description>
23121 
              <bitOffset>6</bitOffset>
23122 
              <bitWidth>1</bitWidth>
23123 
            </field>
23124 
            <field>
23125 
              <name>LOCK</name>
23126 
              <description>Lock</description>
23127 
              <bitOffset>7</bitOffset>
23128 
              <bitWidth>1</bitWidth>
23129 
            </field>
23130 
            <field>
23131 
              <name>OPTWRE</name>
23132 
              <description>Option bytes write enable</description>
23133 
              <bitOffset>9</bitOffset>
23134 
              <bitWidth>1</bitWidth>
23135 
            </field>
23136 
            <field>
23137 
              <name>ERRIE</name>
23138 
              <description>Error interrupt enable</description>
23139 
              <bitOffset>10</bitOffset>
23140 
              <bitWidth>1</bitWidth>
23141 
            </field>
23142 
            <field>
23143 
              <name>EOPIE</name>
23144 
              <description>End of operation interrupt
23145 
              enable</description>
23146 
              <bitOffset>12</bitOffset>
23147 
              <bitWidth>1</bitWidth>
23148 
            </field>
23149 
          </fields>
23150 
        </register>
23151 
        <register>
23152 
          <name>AR</name>
23153 
          <displayName>AR</displayName>
23154 
          <description>Flash address register</description>
23155 
          <addressOffset>0x14</addressOffset>
23156 
          <size>0x20</size>
23157 
          <access>write-only</access>
23158 
          <resetValue>0x00000000</resetValue>
23159 
          <fields>
23160 
            <field>
23161 
              <name>FAR</name>
23162 
              <description>Flash Address</description>
23163 
              <bitOffset>0</bitOffset>
23164 
              <bitWidth>32</bitWidth>
23165 
            </field>
23166 
          </fields>
23167 
        </register>
23168 
        <register>
23169 
          <name>OBR</name>
23170 
          <displayName>OBR</displayName>
23171 
          <description>Option byte register</description>
23172 
          <addressOffset>0x1C</addressOffset>
23173 
          <size>0x20</size>
23174 
          <access>read-only</access>
23175 
          <resetValue>0x03FFFFFC</resetValue>
23176 
          <fields>
23177 
            <field>
23178 
              <name>OPTERR</name>
23179 
              <description>Option byte error</description>
23180 
              <bitOffset>0</bitOffset>
23181 
              <bitWidth>1</bitWidth>
23182 
            </field>
23183 
            <field>
23184 
              <name>RDPRT</name>
23185 
              <description>Read protection</description>
23186 
              <bitOffset>1</bitOffset>
23187 
              <bitWidth>1</bitWidth>
23188 
            </field>
23189 
            <field>
23190 
              <name>WDG_SW</name>
23191 
              <description>WDG_SW</description>
23192 
              <bitOffset>2</bitOffset>
23193 
              <bitWidth>1</bitWidth>
23194 
            </field>
23195 
            <field>
23196 
              <name>nRST_STOP</name>
23197 
              <description>nRST_STOP</description>
23198 
              <bitOffset>3</bitOffset>
23199 
              <bitWidth>1</bitWidth>
23200 
            </field>
23201 
            <field>
23202 
              <name>nRST_STDBY</name>
23203 
              <description>nRST_STDBY</description>
23204 
              <bitOffset>4</bitOffset>
23205 
              <bitWidth>1</bitWidth>
23206 
            </field>
23207 
            <field>
23208 
              <name>Data0</name>
23209 
              <description>Data0</description>
23210 
              <bitOffset>10</bitOffset>
23211 
              <bitWidth>8</bitWidth>
23212 
            </field>
23213 
            <field>
23214 
              <name>Data1</name>
23215 
              <description>Data1</description>
23216 
              <bitOffset>18</bitOffset>
23217 
              <bitWidth>8</bitWidth>
23218 
            </field>
23219 
          </fields>
23220 
        </register>
23221 
        <register>
23222 
          <name>WRPR</name>
23223 
          <displayName>WRPR</displayName>
23224 
          <description>Write protection register</description>
23225 
          <addressOffset>0x20</addressOffset>
23226 
          <size>0x20</size>
23227 
          <access>read-only</access>
23228 
          <resetValue>0xFFFFFFFF</resetValue>
23229 
          <fields>
23230 
            <field>
23231 
              <name>WRP</name>
23232 
              <description>Write protect</description>
23233 
              <bitOffset>0</bitOffset>
23234 
              <bitWidth>32</bitWidth>
23235 
            </field>
23236 
          </fields>
23237 
        </register>
23238 
      </registers>
23239 
    </peripheral>
23240 
    <peripheral>
23241 
      <name>NVIC</name>
23242 
      <description>Nested Vectored Interrupt
23243 
      Controller</description>
23244 
      <groupName>NVIC</groupName>
23245 
      <baseAddress>0xE000E000</baseAddress>
23246 
      <addressBlock>
23247 
        <offset>0x0</offset>
23248 
        <size>0x1001</size>
23249 
        <usage>registers</usage>
23250 
      </addressBlock>
23251 
      <registers>
23252 
        <register>
23253 
          <name>ICTR</name>
23254 
          <displayName>ICTR</displayName>
23255 
          <description>Interrupt Controller Type
23256 
          Register</description>
23257 
          <addressOffset>0x4</addressOffset>
23258 
          <size>0x20</size>
23259 
          <access>read-only</access>
23260 
          <resetValue>0x00000000</resetValue>
23261 
          <fields>
23262 
            <field>
23263 
              <name>INTLINESNUM</name>
23264 
              <description>Total number of interrupt lines in
23265 
              groups</description>
23266 
              <bitOffset>0</bitOffset>
23267 
              <bitWidth>4</bitWidth>
23268 
            </field>
23269 
          </fields>
23270 
        </register>
23271 
        <register>
23272 
          <name>STIR</name>
23273 
          <displayName>STIR</displayName>
23274 
          <description>Software Triggered Interrupt
23275 
          Register</description>
23276 
          <addressOffset>0xF00</addressOffset>
23277 
          <size>0x20</size>
23278 
          <access>write-only</access>
23279 
          <resetValue>0x00000000</resetValue>
23280 
          <fields>
23281 
            <field>
23282 
              <name>INTID</name>
23283 
              <description>interrupt to be triggered</description>
23284 
              <bitOffset>0</bitOffset>
23285 
              <bitWidth>9</bitWidth>
23286 
            </field>
23287 
          </fields>
23288 
        </register>
23289 
        <register>
23290 
          <name>ISER0</name>
23291 
          <displayName>ISER0</displayName>
23292 
          <description>Interrupt Set-Enable Register</description>
23293 
          <addressOffset>0x100</addressOffset>
23294 
          <size>0x20</size>
23295 
          <access>read-write</access>
23296 
          <resetValue>0x00000000</resetValue>
23297 
          <fields>
23298 
            <field>
23299 
              <name>SETENA</name>
23300 
              <description>SETENA</description>
23301 
              <bitOffset>0</bitOffset>
23302 
              <bitWidth>32</bitWidth>
23303 
            </field>
23304 
          </fields>
23305 
        </register>
23306 
        <register>
23307 
          <name>ISER1</name>
23308 
          <displayName>ISER1</displayName>
23309 
          <description>Interrupt Set-Enable Register</description>
23310 
          <addressOffset>0x104</addressOffset>
23311 
          <size>0x20</size>
23312 
          <access>read-write</access>
23313 
          <resetValue>0x00000000</resetValue>
23314 
          <fields>
23315 
            <field>
23316 
              <name>SETENA</name>
23317 
              <description>SETENA</description>
23318 
              <bitOffset>0</bitOffset>
23319 
              <bitWidth>32</bitWidth>
23320 
            </field>
23321 
          </fields>
23322 
        </register>
23323 
        <register>
23324 
          <name>ICER0</name>
23325 
          <displayName>ICER0</displayName>
23326 
          <description>Interrupt Clear-Enable
23327 
          Register</description>
23328 
          <addressOffset>0x180</addressOffset>
23329 
          <size>0x20</size>
23330 
          <access>read-write</access>
23331 
          <resetValue>0x00000000</resetValue>
23332 
          <fields>
23333 
            <field>
23334 
              <name>CLRENA</name>
23335 
              <description>CLRENA</description>
23336 
              <bitOffset>0</bitOffset>
23337 
              <bitWidth>32</bitWidth>
23338 
            </field>
23339 
          </fields>
23340 
        </register>
23341 
        <register>
23342 
          <name>ICER1</name>
23343 
          <displayName>ICER1</displayName>
23344 
          <description>Interrupt Clear-Enable
23345 
          Register</description>
23346 
          <addressOffset>0x184</addressOffset>
23347 
          <size>0x20</size>
23348 
          <access>read-write</access>
23349 
          <resetValue>0x00000000</resetValue>
23350 
          <fields>
23351 
            <field>
23352 
              <name>CLRENA</name>
23353 
              <description>CLRENA</description>
23354 
              <bitOffset>0</bitOffset>
23355 
              <bitWidth>32</bitWidth>
23356 
            </field>
23357 
          </fields>
23358 
        </register>
23359 
        <register>
23360 
          <name>ISPR0</name>
23361 
          <displayName>ISPR0</displayName>
23362 
          <description>Interrupt Set-Pending Register</description>
23363 
          <addressOffset>0x200</addressOffset>
23364 
          <size>0x20</size>
23365 
          <access>read-write</access>
23366 
          <resetValue>0x00000000</resetValue>
23367 
          <fields>
23368 
            <field>
23369 
              <name>SETPEND</name>
23370 
              <description>SETPEND</description>
23371 
              <bitOffset>0</bitOffset>
23372 
              <bitWidth>32</bitWidth>
23373 
            </field>
23374 
          </fields>
23375 
        </register>
23376 
        <register>
23377 
          <name>ISPR1</name>
23378 
          <displayName>ISPR1</displayName>
23379 
          <description>Interrupt Set-Pending Register</description>
23380 
          <addressOffset>0x204</addressOffset>
23381 
          <size>0x20</size>
23382 
          <access>read-write</access>
23383 
          <resetValue>0x00000000</resetValue>
23384 
          <fields>
23385 
            <field>
23386 
              <name>SETPEND</name>
23387 
              <description>SETPEND</description>
23388 
              <bitOffset>0</bitOffset>
23389 
              <bitWidth>32</bitWidth>
23390 
            </field>
23391 
          </fields>
23392 
        </register>
23393 
        <register>
23394 
          <name>ICPR0</name>
23395 
          <displayName>ICPR0</displayName>
23396 
          <description>Interrupt Clear-Pending
23397 
          Register</description>
23398 
          <addressOffset>0x280</addressOffset>
23399 
          <size>0x20</size>
23400 
          <access>read-write</access>
23401 
          <resetValue>0x00000000</resetValue>
23402 
          <fields>
23403 
            <field>
23404 
              <name>CLRPEND</name>
23405 
              <description>CLRPEND</description>
23406 
              <bitOffset>0</bitOffset>
23407 
              <bitWidth>32</bitWidth>
23408 
            </field>
23409 
          </fields>
23410 
        </register>
23411 
        <register>
23412 
          <name>ICPR1</name>
23413 
          <displayName>ICPR1</displayName>
23414 
          <description>Interrupt Clear-Pending
23415 
          Register</description>
23416 
          <addressOffset>0x284</addressOffset>
23417 
          <size>0x20</size>
23418 
          <access>read-write</access>
23419 
          <resetValue>0x00000000</resetValue>
23420 
          <fields>
23421 
            <field>
23422 
              <name>CLRPEND</name>
23423 
              <description>CLRPEND</description>
23424 
              <bitOffset>0</bitOffset>
23425 
              <bitWidth>32</bitWidth>
23426 
            </field>
23427 
          </fields>
23428 
        </register>
23429 
        <register>
23430 
          <name>IABR0</name>
23431 
          <displayName>IABR0</displayName>
23432 
          <description>Interrupt Active Bit Register</description>
23433 
          <addressOffset>0x300</addressOffset>
23434 
          <size>0x20</size>
23435 
          <access>read-only</access>
23436 
          <resetValue>0x00000000</resetValue>
23437 
          <fields>
23438 
            <field>
23439 
              <name>ACTIVE</name>
23440 
              <description>ACTIVE</description>
23441 
              <bitOffset>0</bitOffset>
23442 
              <bitWidth>32</bitWidth>
23443 
            </field>
23444 
          </fields>
23445 
        </register>
23446 
        <register>
23447 
          <name>IABR1</name>
23448 
          <displayName>IABR1</displayName>
23449 
          <description>Interrupt Active Bit Register</description>
23450 
          <addressOffset>0x304</addressOffset>
23451 
          <size>0x20</size>
23452 
          <access>read-only</access>
23453 
          <resetValue>0x00000000</resetValue>
23454 
          <fields>
23455 
            <field>
23456 
              <name>ACTIVE</name>
23457 
              <description>ACTIVE</description>
23458 
              <bitOffset>0</bitOffset>
23459 
              <bitWidth>32</bitWidth>
23460 
            </field>
23461 
          </fields>
23462 
        </register>
23463 
        <register>
23464 
          <name>IPR0</name>
23465 
          <displayName>IPR0</displayName>
23466 
          <description>Interrupt Priority Register</description>
23467 
          <addressOffset>0x400</addressOffset>
23468 
          <size>0x20</size>
23469 
          <access>read-write</access>
23470 
          <resetValue>0x00000000</resetValue>
23471 
          <fields>
23472 
            <field>
23473 
              <name>IPR_N0</name>
23474 
              <description>IPR_N0</description>
23475 
              <bitOffset>0</bitOffset>
23476 
              <bitWidth>8</bitWidth>
23477 
            </field>
23478 
            <field>
23479 
              <name>IPR_N1</name>
23480 
              <description>IPR_N1</description>
23481 
              <bitOffset>8</bitOffset>
23482 
              <bitWidth>8</bitWidth>
23483 
            </field>
23484 
            <field>
23485 
              <name>IPR_N2</name>
23486 
              <description>IPR_N2</description>
23487 
              <bitOffset>16</bitOffset>
23488 
              <bitWidth>8</bitWidth>
23489 
            </field>
23490 
            <field>
23491 
              <name>IPR_N3</name>
23492 
              <description>IPR_N3</description>
23493 
              <bitOffset>24</bitOffset>
23494 
              <bitWidth>8</bitWidth>
23495 
            </field>
23496 
          </fields>
23497 
        </register>
23498 
        <register>
23499 
          <name>IPR1</name>
23500 
          <displayName>IPR1</displayName>
23501 
          <description>Interrupt Priority Register</description>
23502 
          <addressOffset>0x404</addressOffset>
23503 
          <size>0x20</size>
23504 
          <access>read-write</access>
23505 
          <resetValue>0x00000000</resetValue>
23506 
          <fields>
23507 
            <field>
23508 
              <name>IPR_N0</name>
23509 
              <description>IPR_N0</description>
23510 
              <bitOffset>0</bitOffset>
23511 
              <bitWidth>8</bitWidth>
23512 
            </field>
23513 
            <field>
23514 
              <name>IPR_N1</name>
23515 
              <description>IPR_N1</description>
23516 
              <bitOffset>8</bitOffset>
23517 
              <bitWidth>8</bitWidth>
23518 
            </field>
23519 
            <field>
23520 
              <name>IPR_N2</name>
23521 
              <description>IPR_N2</description>
23522 
              <bitOffset>16</bitOffset>
23523 
              <bitWidth>8</bitWidth>
23524 
            </field>
23525 
            <field>
23526 
              <name>IPR_N3</name>
23527 
              <description>IPR_N3</description>
23528 
              <bitOffset>24</bitOffset>
23529 
              <bitWidth>8</bitWidth>
23530 
            </field>
23531 
          </fields>
23532 
        </register>
23533 
        <register>
23534 
          <name>IPR2</name>
23535 
          <displayName>IPR2</displayName>
23536 
          <description>Interrupt Priority Register</description>
23537 
          <addressOffset>0x408</addressOffset>
23538 
          <size>0x20</size>
23539 
          <access>read-write</access>
23540 
          <resetValue>0x00000000</resetValue>
23541 
          <fields>
23542 
            <field>
23543 
              <name>IPR_N0</name>
23544 
              <description>IPR_N0</description>
23545 
              <bitOffset>0</bitOffset>
23546 
              <bitWidth>8</bitWidth>
23547 
            </field>
23548 
            <field>
23549 
              <name>IPR_N1</name>
23550 
              <description>IPR_N1</description>
23551 
              <bitOffset>8</bitOffset>
23552 
              <bitWidth>8</bitWidth>
23553 
            </field>
23554 
            <field>
23555 
              <name>IPR_N2</name>
23556 
              <description>IPR_N2</description>
23557 
              <bitOffset>16</bitOffset>
23558 
              <bitWidth>8</bitWidth>
23559 
            </field>
23560 
            <field>
23561 
              <name>IPR_N3</name>
23562 
              <description>IPR_N3</description>
23563 
              <bitOffset>24</bitOffset>
23564 
              <bitWidth>8</bitWidth>
23565 
            </field>
23566 
          </fields>
23567 
        </register>
23568 
        <register>
23569 
          <name>IPR3</name>
23570 
          <displayName>IPR3</displayName>
23571 
          <description>Interrupt Priority Register</description>
23572 
          <addressOffset>0x40C</addressOffset>
23573 
          <size>0x20</size>
23574 
          <access>read-write</access>
23575 
          <resetValue>0x00000000</resetValue>
23576 
          <fields>
23577 
            <field>
23578 
              <name>IPR_N0</name>
23579 
              <description>IPR_N0</description>
23580 
              <bitOffset>0</bitOffset>
23581 
              <bitWidth>8</bitWidth>
23582 
            </field>
23583 
            <field>
23584 
              <name>IPR_N1</name>
23585 
              <description>IPR_N1</description>
23586 
              <bitOffset>8</bitOffset>
23587 
              <bitWidth>8</bitWidth>
23588 
            </field>
23589 
            <field>
23590 
              <name>IPR_N2</name>
23591 
              <description>IPR_N2</description>
23592 
              <bitOffset>16</bitOffset>
23593 
              <bitWidth>8</bitWidth>
23594 
            </field>
23595 
            <field>
23596 
              <name>IPR_N3</name>
23597 
              <description>IPR_N3</description>
23598 
              <bitOffset>24</bitOffset>
23599 
              <bitWidth>8</bitWidth>
23600 
            </field>
23601 
          </fields>
23602 
        </register>
23603 
        <register>
23604 
          <name>IPR4</name>
23605 
          <displayName>IPR4</displayName>
23606 
          <description>Interrupt Priority Register</description>
23607 
          <addressOffset>0x410</addressOffset>
23608 
          <size>0x20</size>
23609 
          <access>read-write</access>
23610 
          <resetValue>0x00000000</resetValue>
23611 
          <fields>
23612 
            <field>
23613 
              <name>IPR_N0</name>
23614 
              <description>IPR_N0</description>
23615 
              <bitOffset>0</bitOffset>
23616 
              <bitWidth>8</bitWidth>
23617 
            </field>
23618 
            <field>
23619 
              <name>IPR_N1</name>
23620 
              <description>IPR_N1</description>
23621 
              <bitOffset>8</bitOffset>
23622 
              <bitWidth>8</bitWidth>
23623 
            </field>
23624 
            <field>
23625 
              <name>IPR_N2</name>
23626 
              <description>IPR_N2</description>
23627 
              <bitOffset>16</bitOffset>
23628 
              <bitWidth>8</bitWidth>
23629 
            </field>
23630 
            <field>
23631 
              <name>IPR_N3</name>
23632 
              <description>IPR_N3</description>
23633 
              <bitOffset>24</bitOffset>
23634 
              <bitWidth>8</bitWidth>
23635 
            </field>
23636 
          </fields>
23637 
        </register>
23638 
        <register>
23639 
          <name>IPR5</name>
23640 
          <displayName>IPR5</displayName>
23641 
          <description>Interrupt Priority Register</description>
23642 
          <addressOffset>0x414</addressOffset>
23643 
          <size>0x20</size>
23644 
          <access>read-write</access>
23645 
          <resetValue>0x00000000</resetValue>
23646 
          <fields>
23647 
            <field>
23648 
              <name>IPR_N0</name>
23649 
              <description>IPR_N0</description>
23650 
              <bitOffset>0</bitOffset>
23651 
              <bitWidth>8</bitWidth>
23652 
            </field>
23653 
            <field>
23654 
              <name>IPR_N1</name>
23655 
              <description>IPR_N1</description>
23656 
              <bitOffset>8</bitOffset>
23657 
              <bitWidth>8</bitWidth>
23658 
            </field>
23659 
            <field>
23660 
              <name>IPR_N2</name>
23661 
              <description>IPR_N2</description>
23662 
              <bitOffset>16</bitOffset>
23663 
              <bitWidth>8</bitWidth>
23664 
            </field>
23665 
            <field>
23666 
              <name>IPR_N3</name>
23667 
              <description>IPR_N3</description>
23668 
              <bitOffset>24</bitOffset>
23669 
              <bitWidth>8</bitWidth>
23670 
            </field>
23671 
          </fields>
23672 
        </register>
23673 
        <register>
23674 
          <name>IPR6</name>
23675 
          <displayName>IPR6</displayName>
23676 
          <description>Interrupt Priority Register</description>
23677 
          <addressOffset>0x418</addressOffset>
23678 
          <size>0x20</size>
23679 
          <access>read-write</access>
23680 
          <resetValue>0x00000000</resetValue>
23681 
          <fields>
23682 
            <field>
23683 
              <name>IPR_N0</name>
23684 
              <description>IPR_N0</description>
23685 
              <bitOffset>0</bitOffset>
23686 
              <bitWidth>8</bitWidth>
23687 
            </field>
23688 
            <field>
23689 
              <name>IPR_N1</name>
23690 
              <description>IPR_N1</description>
23691 
              <bitOffset>8</bitOffset>
23692 
              <bitWidth>8</bitWidth>
23693 
            </field>
23694 
            <field>
23695 
              <name>IPR_N2</name>
23696 
              <description>IPR_N2</description>
23697 
              <bitOffset>16</bitOffset>
23698 
              <bitWidth>8</bitWidth>
23699 
            </field>
23700 
            <field>
23701 
              <name>IPR_N3</name>
23702 
              <description>IPR_N3</description>
23703 
              <bitOffset>24</bitOffset>
23704 
              <bitWidth>8</bitWidth>
23705 
            </field>
23706 
          </fields>
23707 
        </register>
23708 
        <register>
23709 
          <name>IPR7</name>
23710 
          <displayName>IPR7</displayName>
23711 
          <description>Interrupt Priority Register</description>
23712 
          <addressOffset>0x41C</addressOffset>
23713 
          <size>0x20</size>
23714 
          <access>read-write</access>
23715 
          <resetValue>0x00000000</resetValue>
23716 
          <fields>
23717 
            <field>
23718 
              <name>IPR_N0</name>
23719 
              <description>IPR_N0</description>
23720 
              <bitOffset>0</bitOffset>
23721 
              <bitWidth>8</bitWidth>
23722 
            </field>
23723 
            <field>
23724 
              <name>IPR_N1</name>
23725 
              <description>IPR_N1</description>
23726 
              <bitOffset>8</bitOffset>
23727 
              <bitWidth>8</bitWidth>
23728 
            </field>
23729 
            <field>
23730 
              <name>IPR_N2</name>
23731 
              <description>IPR_N2</description>
23732 
              <bitOffset>16</bitOffset>
23733 
              <bitWidth>8</bitWidth>
23734 
            </field>
23735 
            <field>
23736 
              <name>IPR_N3</name>
23737 
              <description>IPR_N3</description>
23738 
              <bitOffset>24</bitOffset>
23739 
              <bitWidth>8</bitWidth>
23740 
            </field>
23741 
          </fields>
23742 
        </register>
23743 
        <register>
23744 
          <name>IPR8</name>
23745 
          <displayName>IPR8</displayName>
23746 
          <description>Interrupt Priority Register</description>
23747 
          <addressOffset>0x420</addressOffset>
23748 
          <size>0x20</size>
23749 
          <access>read-write</access>
23750 
          <resetValue>0x00000000</resetValue>
23751 
          <fields>
23752 
            <field>
23753 
              <name>IPR_N0</name>
23754 
              <description>IPR_N0</description>
23755 
              <bitOffset>0</bitOffset>
23756 
              <bitWidth>8</bitWidth>
23757 
            </field>
23758 
            <field>
23759 
              <name>IPR_N1</name>
23760 
              <description>IPR_N1</description>
23761 
              <bitOffset>8</bitOffset>
23762 
              <bitWidth>8</bitWidth>
23763 
            </field>
23764 
            <field>
23765 
              <name>IPR_N2</name>
23766 
              <description>IPR_N2</description>
23767 
              <bitOffset>16</bitOffset>
23768 
              <bitWidth>8</bitWidth>
23769 
            </field>
23770 
            <field>
23771 
              <name>IPR_N3</name>
23772 
              <description>IPR_N3</description>
23773 
              <bitOffset>24</bitOffset>
23774 
              <bitWidth>8</bitWidth>
23775 
            </field>
23776 
          </fields>
23777 
        </register>
23778 
        <register>
23779 
          <name>IPR9</name>
23780 
          <displayName>IPR9</displayName>
23781 
          <description>Interrupt Priority Register</description>
23782 
          <addressOffset>0x424</addressOffset>
23783 
          <size>0x20</size>
23784 
          <access>read-write</access>
23785 
          <resetValue>0x00000000</resetValue>
23786 
          <fields>
23787 
            <field>
23788 
              <name>IPR_N0</name>
23789 
              <description>IPR_N0</description>
23790 
              <bitOffset>0</bitOffset>
23791 
              <bitWidth>8</bitWidth>
23792 
            </field>
23793 
            <field>
23794 
              <name>IPR_N1</name>
23795 
              <description>IPR_N1</description>
23796 
              <bitOffset>8</bitOffset>
23797 
              <bitWidth>8</bitWidth>
23798 
            </field>
23799 
            <field>
23800 
              <name>IPR_N2</name>
23801 
              <description>IPR_N2</description>
23802 
              <bitOffset>16</bitOffset>
23803 
              <bitWidth>8</bitWidth>
23804 
            </field>
23805 
            <field>
23806 
              <name>IPR_N3</name>
23807 
              <description>IPR_N3</description>
23808 
              <bitOffset>24</bitOffset>
23809 
              <bitWidth>8</bitWidth>
23810 
            </field>
23811 
          </fields>
23812 
        </register>
23813 
        <register>
23814 
          <name>IPR10</name>
23815 
          <displayName>IPR10</displayName>
23816 
          <description>Interrupt Priority Register</description>
23817 
          <addressOffset>0x428</addressOffset>
23818 
          <size>0x20</size>
23819 
          <access>read-write</access>
23820 
          <resetValue>0x00000000</resetValue>
23821 
          <fields>
23822 
            <field>
23823 
              <name>IPR_N0</name>
23824 
              <description>IPR_N0</description>
23825 
              <bitOffset>0</bitOffset>
23826 
              <bitWidth>8</bitWidth>
23827 
            </field>
23828 
            <field>
23829 
              <name>IPR_N1</name>
23830 
              <description>IPR_N1</description>
23831 
              <bitOffset>8</bitOffset>
23832 
              <bitWidth>8</bitWidth>
23833 
            </field>
23834 
            <field>
23835 
              <name>IPR_N2</name>
23836 
              <description>IPR_N2</description>
23837 
              <bitOffset>16</bitOffset>
23838 
              <bitWidth>8</bitWidth>
23839 
            </field>
23840 
            <field>
23841 
              <name>IPR_N3</name>
23842 
              <description>IPR_N3</description>
23843 
              <bitOffset>24</bitOffset>
23844 
              <bitWidth>8</bitWidth>
23845 
            </field>
23846 
          </fields>
23847 
        </register>
23848 
        <register>
23849 
          <name>IPR11</name>
23850 
          <displayName>IPR11</displayName>
23851 
          <description>Interrupt Priority Register</description>
23852 
          <addressOffset>0x42C</addressOffset>
23853 
          <size>0x20</size>
23854 
          <access>read-write</access>
23855 
          <resetValue>0x00000000</resetValue>
23856 
          <fields>
23857 
            <field>
23858 
              <name>IPR_N0</name>
23859 
              <description>IPR_N0</description>
23860 
              <bitOffset>0</bitOffset>
23861 
              <bitWidth>8</bitWidth>
23862 
            </field>
23863 
            <field>
23864 
              <name>IPR_N1</name>
23865 
              <description>IPR_N1</description>
23866 
              <bitOffset>8</bitOffset>
23867 
              <bitWidth>8</bitWidth>
23868 
            </field>
23869 
            <field>
23870 
              <name>IPR_N2</name>
23871 
              <description>IPR_N2</description>
23872 
              <bitOffset>16</bitOffset>
23873 
              <bitWidth>8</bitWidth>
23874 
            </field>
23875 
            <field>
23876 
              <name>IPR_N3</name>
23877 
              <description>IPR_N3</description>
23878 
              <bitOffset>24</bitOffset>
23879 
              <bitWidth>8</bitWidth>
23880 
            </field>
23881 
          </fields>
23882 
        </register>
23883 
        <register>
23884 
          <name>IPR12</name>
23885 
          <displayName>IPR12</displayName>
23886 
          <description>Interrupt Priority Register</description>
23887 
          <addressOffset>0x430</addressOffset>
23888 
          <size>0x20</size>
23889 
          <access>read-write</access>
23890 
          <resetValue>0x00000000</resetValue>
23891 
          <fields>
23892 
            <field>
23893 
              <name>IPR_N0</name>
23894 
              <description>IPR_N0</description>
23895 
              <bitOffset>0</bitOffset>
23896 
              <bitWidth>8</bitWidth>
23897 
            </field>
23898 
            <field>
23899 
              <name>IPR_N1</name>
23900 
              <description>IPR_N1</description>
23901 
              <bitOffset>8</bitOffset>
23902 
              <bitWidth>8</bitWidth>
23903 
            </field>
23904 
            <field>
23905 
              <name>IPR_N2</name>
23906 
              <description>IPR_N2</description>
23907 
              <bitOffset>16</bitOffset>
23908 
              <bitWidth>8</bitWidth>
23909 
            </field>
23910 
            <field>
23911 
              <name>IPR_N3</name>
23912 
              <description>IPR_N3</description>
23913 
              <bitOffset>24</bitOffset>
23914 
              <bitWidth>8</bitWidth>
23915 
            </field>
23916 
          </fields>
23917 
        </register>
23918 
        <register>
23919 
          <name>IPR13</name>
23920 
          <displayName>IPR13</displayName>
23921 
          <description>Interrupt Priority Register</description>
23922 
          <addressOffset>0x434</addressOffset>
23923 
          <size>0x20</size>
23924 
          <access>read-write</access>
23925 
          <resetValue>0x00000000</resetValue>
23926 
          <fields>
23927 
            <field>
23928 
              <name>IPR_N0</name>
23929 
              <description>IPR_N0</description>
23930 
              <bitOffset>0</bitOffset>
23931 
              <bitWidth>8</bitWidth>
23932 
            </field>
23933 
            <field>
23934 
              <name>IPR_N1</name>
23935 
              <description>IPR_N1</description>
23936 
              <bitOffset>8</bitOffset>
23937 
              <bitWidth>8</bitWidth>
23938 
            </field>
23939 
            <field>
23940 
              <name>IPR_N2</name>
23941 
              <description>IPR_N2</description>
23942 
              <bitOffset>16</bitOffset>
23943 
              <bitWidth>8</bitWidth>
23944 
            </field>
23945 
            <field>
23946 
              <name>IPR_N3</name>
23947 
              <description>IPR_N3</description>
23948 
              <bitOffset>24</bitOffset>
23949 
              <bitWidth>8</bitWidth>
23950 
            </field>
23951 
          </fields>
23952 
        </register>
23953 
        <register>
23954 
          <name>IPR14</name>
23955 
          <displayName>IPR14</displayName>
23956 
          <description>Interrupt Priority Register</description>
23957 
          <addressOffset>0x438</addressOffset>
23958 
          <size>0x20</size>
23959 
          <access>read-write</access>
23960 
          <resetValue>0x00000000</resetValue>
23961 
          <fields>
23962 
            <field>
23963 
              <name>IPR_N0</name>
23964 
              <description>IPR_N0</description>
23965 
              <bitOffset>0</bitOffset>
23966 
              <bitWidth>8</bitWidth>
23967 
            </field>
23968 
            <field>
23969 
              <name>IPR_N1</name>
23970 
              <description>IPR_N1</description>
23971 
              <bitOffset>8</bitOffset>
23972 
              <bitWidth>8</bitWidth>
23973 
            </field>
23974 
            <field>
23975 
              <name>IPR_N2</name>
23976 
              <description>IPR_N2</description>
23977 
              <bitOffset>16</bitOffset>
23978 
              <bitWidth>8</bitWidth>
23979 
            </field>
23980 
            <field>
23981 
              <name>IPR_N3</name>
23982 
              <description>IPR_N3</description>
23983 
              <bitOffset>24</bitOffset>
23984 
              <bitWidth>8</bitWidth>
23985 
            </field>
23986 
          </fields>
23987 
        </register>
23988 
      </registers>
23989 
    </peripheral>
23990 
    <peripheral>
23991 
      <name>USB</name>
23992 
      <description>Universal serial bus full-speed device
23993 
      interface</description>
23994 
      <groupName>USB</groupName>
23995 
      <baseAddress>0x40005C00</baseAddress>
23996 
      <addressBlock>
23997 
        <offset>0x0</offset>
23998 
        <size>0x400</size>
23999 
        <usage>registers</usage>
24000 
      </addressBlock>
24001 
      <interrupt>
24002 
        <name>USB_HP_CAN_TX</name>
24003 
        <description>USB High Priority or CAN TX
24004 
        interrupts</description>
24005 
        <value>19</value>
24006 
      </interrupt>
24007 
      <interrupt>
24008 
        <name>USB_LP_CAN_RX0</name>
24009 
        <description>USB Low Priority or CAN RX0
24010 
        interrupts</description>
24011 
        <value>20</value>
24012 
      </interrupt>
24013 
      <registers>
24014 
        <register>
24015 
          <name>EP0R</name>
24016 
          <displayName>EP0R</displayName>
24017 
          <description>endpoint 0 register</description>
24018 
          <addressOffset>0x0</addressOffset>
24019 
          <size>0x20</size>
24020 
          <access>read-write</access>
24021 
          <resetValue>0x00000000</resetValue>
24022 
          <fields>
24023 
            <field>
24024 
              <name>EA</name>
24025 
              <description>Endpoint address</description>
24026 
              <bitOffset>0</bitOffset>
24027 
              <bitWidth>4</bitWidth>
24028 
            </field>
24029 
            <field>
24030 
              <name>STAT_TX</name>
24031 
              <description>Status bits, for transmission
24032 
              transfers</description>
24033 
              <bitOffset>4</bitOffset>
24034 
              <bitWidth>2</bitWidth>
24035 
            </field>
24036 
            <field>
24037 
              <name>DTOG_TX</name>
24038 
              <description>Data Toggle, for transmission
24039 
              transfers</description>
24040 
              <bitOffset>6</bitOffset>
24041 
              <bitWidth>1</bitWidth>
24042 
            </field>
24043 
            <field>
24044 
              <name>CTR_TX</name>
24045 
              <description>Correct Transfer for
24046 
              transmission</description>
24047 
              <bitOffset>7</bitOffset>
24048 
              <bitWidth>1</bitWidth>
24049 
            </field>
24050 
            <field>
24051 
              <name>EP_KIND</name>
24052 
              <description>Endpoint kind</description>
24053 
              <bitOffset>8</bitOffset>
24054 
              <bitWidth>1</bitWidth>
24055 
            </field>
24056 
            <field>
24057 
              <name>EP_TYPE</name>
24058 
              <description>Endpoint type</description>
24059 
              <bitOffset>9</bitOffset>
24060 
              <bitWidth>2</bitWidth>
24061 
            </field>
24062 
            <field>
24063 
              <name>SETUP</name>
24064 
              <description>Setup transaction
24065 
              completed</description>
24066 
              <bitOffset>11</bitOffset>
24067 
              <bitWidth>1</bitWidth>
24068 
            </field>
24069 
            <field>
24070 
              <name>STAT_RX</name>
24071 
              <description>Status bits, for reception
24072 
              transfers</description>
24073 
              <bitOffset>12</bitOffset>
24074 
              <bitWidth>2</bitWidth>
24075 
            </field>
24076 
            <field>
24077 
              <name>DTOG_RX</name>
24078 
              <description>Data Toggle, for reception
24079 
              transfers</description>
24080 
              <bitOffset>14</bitOffset>
24081 
              <bitWidth>1</bitWidth>
24082 
            </field>
24083 
            <field>
24084 
              <name>CTR_RX</name>
24085 
              <description>Correct transfer for
24086 
              reception</description>
24087 
              <bitOffset>15</bitOffset>
24088 
              <bitWidth>1</bitWidth>
24089 
            </field>
24090 
          </fields>
24091 
        </register>
24092 
        <register>
24093 
          <name>EP1R</name>
24094 
          <displayName>EP1R</displayName>
24095 
          <description>endpoint 1 register</description>
24096 
          <addressOffset>0x4</addressOffset>
24097 
          <size>0x20</size>
24098 
          <access>read-write</access>
24099 
          <resetValue>0x00000000</resetValue>
24100 
          <fields>
24101 
            <field>
24102 
              <name>EA</name>
24103 
              <description>Endpoint address</description>
24104 
              <bitOffset>0</bitOffset>
24105 
              <bitWidth>4</bitWidth>
24106 
            </field>
24107 
            <field>
24108 
              <name>STAT_TX</name>
24109 
              <description>Status bits, for transmission
24110 
              transfers</description>
24111 
              <bitOffset>4</bitOffset>
24112 
              <bitWidth>2</bitWidth>
24113 
            </field>
24114 
            <field>
24115 
              <name>DTOG_TX</name>
24116 
              <description>Data Toggle, for transmission
24117 
              transfers</description>
24118 
              <bitOffset>6</bitOffset>
24119 
              <bitWidth>1</bitWidth>
24120 
            </field>
24121 
            <field>
24122 
              <name>CTR_TX</name>
24123 
              <description>Correct Transfer for
24124 
              transmission</description>
24125 
              <bitOffset>7</bitOffset>
24126 
              <bitWidth>1</bitWidth>
24127 
            </field>
24128 
            <field>
24129 
              <name>EP_KIND</name>
24130 
              <description>Endpoint kind</description>
24131 
              <bitOffset>8</bitOffset>
24132 
              <bitWidth>1</bitWidth>
24133 
            </field>
24134 
            <field>
24135 
              <name>EP_TYPE</name>
24136 
              <description>Endpoint type</description>
24137 
              <bitOffset>9</bitOffset>
24138 
              <bitWidth>2</bitWidth>
24139 
            </field>
24140 
            <field>
24141 
              <name>SETUP</name>
24142 
              <description>Setup transaction
24143 
              completed</description>
24144 
              <bitOffset>11</bitOffset>
24145 
              <bitWidth>1</bitWidth>
24146 
            </field>
24147 
            <field>
24148 
              <name>STAT_RX</name>
24149 
              <description>Status bits, for reception
24150 
              transfers</description>
24151 
              <bitOffset>12</bitOffset>
24152 
              <bitWidth>2</bitWidth>
24153 
            </field>
24154 
            <field>
24155 
              <name>DTOG_RX</name>
24156 
              <description>Data Toggle, for reception
24157 
              transfers</description>
24158 
              <bitOffset>14</bitOffset>
24159 
              <bitWidth>1</bitWidth>
24160 
            </field>
24161 
            <field>
24162 
              <name>CTR_RX</name>
24163 
              <description>Correct transfer for
24164 
              reception</description>
24165 
              <bitOffset>15</bitOffset>
24166 
              <bitWidth>1</bitWidth>
24167 
            </field>
24168 
          </fields>
24169 
        </register>
24170 
        <register>
24171 
          <name>EP2R</name>
24172 
          <displayName>EP2R</displayName>
24173 
          <description>endpoint 2 register</description>
24174 
          <addressOffset>0x8</addressOffset>
24175 
          <size>0x20</size>
24176 
          <access>read-write</access>
24177 
          <resetValue>0x00000000</resetValue>
24178 
          <fields>
24179 
            <field>
24180 
              <name>EA</name>
24181 
              <description>Endpoint address</description>
24182 
              <bitOffset>0</bitOffset>
24183 
              <bitWidth>4</bitWidth>
24184 
            </field>
24185 
            <field>
24186 
              <name>STAT_TX</name>
24187 
              <description>Status bits, for transmission
24188 
              transfers</description>
24189 
              <bitOffset>4</bitOffset>
24190 
              <bitWidth>2</bitWidth>
24191 
            </field>
24192 
            <field>
24193 
              <name>DTOG_TX</name>
24194 
              <description>Data Toggle, for transmission
24195 
              transfers</description>
24196 
              <bitOffset>6</bitOffset>
24197 
              <bitWidth>1</bitWidth>
24198 
            </field>
24199 
            <field>
24200 
              <name>CTR_TX</name>
24201 
              <description>Correct Transfer for
24202 
              transmission</description>
24203 
              <bitOffset>7</bitOffset>
24204 
              <bitWidth>1</bitWidth>
24205 
            </field>
24206 
            <field>
24207 
              <name>EP_KIND</name>
24208 
              <description>Endpoint kind</description>
24209 
              <bitOffset>8</bitOffset>
24210 
              <bitWidth>1</bitWidth>
24211 
            </field>
24212 
            <field>
24213 
              <name>EP_TYPE</name>
24214 
              <description>Endpoint type</description>
24215 
              <bitOffset>9</bitOffset>
24216 
              <bitWidth>2</bitWidth>
24217 
            </field>
24218 
            <field>
24219 
              <name>SETUP</name>
24220 
              <description>Setup transaction
24221 
              completed</description>
24222 
              <bitOffset>11</bitOffset>
24223 
              <bitWidth>1</bitWidth>
24224 
            </field>
24225 
            <field>
24226 
              <name>STAT_RX</name>
24227 
              <description>Status bits, for reception
24228 
              transfers</description>
24229 
              <bitOffset>12</bitOffset>
24230 
              <bitWidth>2</bitWidth>
24231 
            </field>
24232 
            <field>
24233 
              <name>DTOG_RX</name>
24234 
              <description>Data Toggle, for reception
24235 
              transfers</description>
24236 
              <bitOffset>14</bitOffset>
24237 
              <bitWidth>1</bitWidth>
24238 
            </field>
24239 
            <field>
24240 
              <name>CTR_RX</name>
24241 
              <description>Correct transfer for
24242 
              reception</description>
24243 
              <bitOffset>15</bitOffset>
24244 
              <bitWidth>1</bitWidth>
24245 
            </field>
24246 
          </fields>
24247 
        </register>
24248 
        <register>
24249 
          <name>EP3R</name>
24250 
          <displayName>EP3R</displayName>
24251 
          <description>endpoint 3 register</description>
24252 
          <addressOffset>0xC</addressOffset>
24253 
          <size>0x20</size>
24254 
          <access>read-write</access>
24255 
          <resetValue>0x00000000</resetValue>
24256 
          <fields>
24257 
            <field>
24258 
              <name>EA</name>
24259 
              <description>Endpoint address</description>
24260 
              <bitOffset>0</bitOffset>
24261 
              <bitWidth>4</bitWidth>
24262 
            </field>
24263 
            <field>
24264 
              <name>STAT_TX</name>
24265 
              <description>Status bits, for transmission
24266 
              transfers</description>
24267 
              <bitOffset>4</bitOffset>
24268 
              <bitWidth>2</bitWidth>
24269 
            </field>
24270 
            <field>
24271 
              <name>DTOG_TX</name>
24272 
              <description>Data Toggle, for transmission
24273 
              transfers</description>
24274 
              <bitOffset>6</bitOffset>
24275 
              <bitWidth>1</bitWidth>
24276 
            </field>
24277 
            <field>
24278 
              <name>CTR_TX</name>
24279 
              <description>Correct Transfer for
24280 
              transmission</description>
24281 
              <bitOffset>7</bitOffset>
24282 
              <bitWidth>1</bitWidth>
24283 
            </field>
24284 
            <field>
24285 
              <name>EP_KIND</name>
24286 
              <description>Endpoint kind</description>
24287 
              <bitOffset>8</bitOffset>
24288 
              <bitWidth>1</bitWidth>
24289 
            </field>
24290 
            <field>
24291 
              <name>EP_TYPE</name>
24292 
              <description>Endpoint type</description>
24293 
              <bitOffset>9</bitOffset>
24294 
              <bitWidth>2</bitWidth>
24295 
            </field>
24296 
            <field>
24297 
              <name>SETUP</name>
24298 
              <description>Setup transaction
24299 
              completed</description>
24300 
              <bitOffset>11</bitOffset>
24301 
              <bitWidth>1</bitWidth>
24302 
            </field>
24303 
            <field>
24304 
              <name>STAT_RX</name>
24305 
              <description>Status bits, for reception
24306 
              transfers</description>
24307 
              <bitOffset>12</bitOffset>
24308 
              <bitWidth>2</bitWidth>
24309 
            </field>
24310 
            <field>
24311 
              <name>DTOG_RX</name>
24312 
              <description>Data Toggle, for reception
24313 
              transfers</description>
24314 
              <bitOffset>14</bitOffset>
24315 
              <bitWidth>1</bitWidth>
24316 
            </field>
24317 
            <field>
24318 
              <name>CTR_RX</name>
24319 
              <description>Correct transfer for
24320 
              reception</description>
24321 
              <bitOffset>15</bitOffset>
24322 
              <bitWidth>1</bitWidth>
24323 
            </field>
24324 
          </fields>
24325 
        </register>
24326 
        <register>
24327 
          <name>EP4R</name>
24328 
          <displayName>EP4R</displayName>
24329 
          <description>endpoint 4 register</description>
24330 
          <addressOffset>0x10</addressOffset>
24331 
          <size>0x20</size>
24332 
          <access>read-write</access>
24333 
          <resetValue>0x00000000</resetValue>
24334 
          <fields>
24335 
            <field>
24336 
              <name>EA</name>
24337 
              <description>Endpoint address</description>
24338 
              <bitOffset>0</bitOffset>
24339 
              <bitWidth>4</bitWidth>
24340 
            </field>
24341 
            <field>
24342 
              <name>STAT_TX</name>
24343 
              <description>Status bits, for transmission
24344 
              transfers</description>
24345 
              <bitOffset>4</bitOffset>
24346 
              <bitWidth>2</bitWidth>
24347 
            </field>
24348 
            <field>
24349 
              <name>DTOG_TX</name>
24350 
              <description>Data Toggle, for transmission
24351 
              transfers</description>
24352 
              <bitOffset>6</bitOffset>
24353 
              <bitWidth>1</bitWidth>
24354 
            </field>
24355 
            <field>
24356 
              <name>CTR_TX</name>
24357 
              <description>Correct Transfer for
24358 
              transmission</description>
24359 
              <bitOffset>7</bitOffset>
24360 
              <bitWidth>1</bitWidth>
24361 
            </field>
24362 
            <field>
24363 
              <name>EP_KIND</name>
24364 
              <description>Endpoint kind</description>
24365 
              <bitOffset>8</bitOffset>
24366 
              <bitWidth>1</bitWidth>
24367 
            </field>
24368 
            <field>
24369 
              <name>EP_TYPE</name>
24370 
              <description>Endpoint type</description>
24371 
              <bitOffset>9</bitOffset>
24372 
              <bitWidth>2</bitWidth>
24373 
            </field>
24374 
            <field>
24375 
              <name>SETUP</name>
24376 
              <description>Setup transaction
24377 
              completed</description>
24378 
              <bitOffset>11</bitOffset>
24379 
              <bitWidth>1</bitWidth>
24380 
            </field>
24381 
            <field>
24382 
              <name>STAT_RX</name>
24383 
              <description>Status bits, for reception
24384 
              transfers</description>
24385 
              <bitOffset>12</bitOffset>
24386 
              <bitWidth>2</bitWidth>
24387 
            </field>
24388 
            <field>
24389 
              <name>DTOG_RX</name>
24390 
              <description>Data Toggle, for reception
24391 
              transfers</description>
24392 
              <bitOffset>14</bitOffset>
24393 
              <bitWidth>1</bitWidth>
24394 
            </field>
24395 
            <field>
24396 
              <name>CTR_RX</name>
24397 
              <description>Correct transfer for
24398 
              reception</description>
24399 
              <bitOffset>15</bitOffset>
24400 
              <bitWidth>1</bitWidth>
24401 
            </field>
24402 
          </fields>
24403 
        </register>
24404 
        <register>
24405 
          <name>EP5R</name>
24406 
          <displayName>EP5R</displayName>
24407 
          <description>endpoint 5 register</description>
24408 
          <addressOffset>0x14</addressOffset>
24409 
          <size>0x20</size>
24410 
          <access>read-write</access>
24411 
          <resetValue>0x00000000</resetValue>
24412 
          <fields>
24413 
            <field>
24414 
              <name>EA</name>
24415 
              <description>Endpoint address</description>
24416 
              <bitOffset>0</bitOffset>
24417 
              <bitWidth>4</bitWidth>
24418 
            </field>
24419 
            <field>
24420 
              <name>STAT_TX</name>
24421 
              <description>Status bits, for transmission
24422 
              transfers</description>
24423 
              <bitOffset>4</bitOffset>
24424 
              <bitWidth>2</bitWidth>
24425 
            </field>
24426 
            <field>
24427 
              <name>DTOG_TX</name>
24428 
              <description>Data Toggle, for transmission
24429 
              transfers</description>
24430 
              <bitOffset>6</bitOffset>
24431 
              <bitWidth>1</bitWidth>
24432 
            </field>
24433 
            <field>
24434 
              <name>CTR_TX</name>
24435 
              <description>Correct Transfer for
24436 
              transmission</description>
24437 
              <bitOffset>7</bitOffset>
24438 
              <bitWidth>1</bitWidth>
24439 
            </field>
24440 
            <field>
24441 
              <name>EP_KIND</name>
24442 
              <description>Endpoint kind</description>
24443 
              <bitOffset>8</bitOffset>
24444 
              <bitWidth>1</bitWidth>
24445 
            </field>
24446 
            <field>
24447 
              <name>EP_TYPE</name>
24448 
              <description>Endpoint type</description>
24449 
              <bitOffset>9</bitOffset>
24450 
              <bitWidth>2</bitWidth>
24451 
            </field>
24452 
            <field>
24453 
              <name>SETUP</name>
24454 
              <description>Setup transaction
24455 
              completed</description>
24456 
              <bitOffset>11</bitOffset>
24457 
              <bitWidth>1</bitWidth>
24458 
            </field>
24459 
            <field>
24460 
              <name>STAT_RX</name>
24461 
              <description>Status bits, for reception
24462 
              transfers</description>
24463 
              <bitOffset>12</bitOffset>
24464 
              <bitWidth>2</bitWidth>
24465 
            </field>
24466 
            <field>
24467 
              <name>DTOG_RX</name>
24468 
              <description>Data Toggle, for reception
24469 
              transfers</description>
24470 
              <bitOffset>14</bitOffset>
24471 
              <bitWidth>1</bitWidth>
24472 
            </field>
24473 
            <field>
24474 
              <name>CTR_RX</name>
24475 
              <description>Correct transfer for
24476 
              reception</description>
24477 
              <bitOffset>15</bitOffset>
24478 
              <bitWidth>1</bitWidth>
24479 
            </field>
24480 
          </fields>
24481 
        </register>
24482 
        <register>
24483 
          <name>EP6R</name>
24484 
          <displayName>EP6R</displayName>
24485 
          <description>endpoint 6 register</description>
24486 
          <addressOffset>0x18</addressOffset>
24487 
          <size>0x20</size>
24488 
          <access>read-write</access>
24489 
          <resetValue>0x00000000</resetValue>
24490 
          <fields>
24491 
            <field>
24492 
              <name>EA</name>
24493 
              <description>Endpoint address</description>
24494 
              <bitOffset>0</bitOffset>
24495 
              <bitWidth>4</bitWidth>
24496 
            </field>
24497 
            <field>
24498 
              <name>STAT_TX</name>
24499 
              <description>Status bits, for transmission
24500 
              transfers</description>
24501 
              <bitOffset>4</bitOffset>
24502 
              <bitWidth>2</bitWidth>
24503 
            </field>
24504 
            <field>
24505 
              <name>DTOG_TX</name>
24506 
              <description>Data Toggle, for transmission
24507 
              transfers</description>
24508 
              <bitOffset>6</bitOffset>
24509 
              <bitWidth>1</bitWidth>
24510 
            </field>
24511 
            <field>
24512 
              <name>CTR_TX</name>
24513 
              <description>Correct Transfer for
24514 
              transmission</description>
24515 
              <bitOffset>7</bitOffset>
24516 
              <bitWidth>1</bitWidth>
24517 
            </field>
24518 
            <field>
24519 
              <name>EP_KIND</name>
24520 
              <description>Endpoint kind</description>
24521 
              <bitOffset>8</bitOffset>
24522 
              <bitWidth>1</bitWidth>
24523 
            </field>
24524 
            <field>
24525 
              <name>EP_TYPE</name>
24526 
              <description>Endpoint type</description>
24527 
              <bitOffset>9</bitOffset>
24528 
              <bitWidth>2</bitWidth>
24529 
            </field>
24530 
            <field>
24531 
              <name>SETUP</name>
24532 
              <description>Setup transaction
24533 
              completed</description>
24534 
              <bitOffset>11</bitOffset>
24535 
              <bitWidth>1</bitWidth>
24536 
            </field>
24537 
            <field>
24538 
              <name>STAT_RX</name>
24539 
              <description>Status bits, for reception
24540 
              transfers</description>
24541 
              <bitOffset>12</bitOffset>
24542 
              <bitWidth>2</bitWidth>
24543 
            </field>
24544 
            <field>
24545 
              <name>DTOG_RX</name>
24546 
              <description>Data Toggle, for reception
24547 
              transfers</description>
24548 
              <bitOffset>14</bitOffset>
24549 
              <bitWidth>1</bitWidth>
24550 
            </field>
24551 
            <field>
24552 
              <name>CTR_RX</name>
24553 
              <description>Correct transfer for
24554 
              reception</description>
24555 
              <bitOffset>15</bitOffset>
24556 
              <bitWidth>1</bitWidth>
24557 
            </field>
24558 
          </fields>
24559 
        </register>
24560 
        <register>
24561 
          <name>EP7R</name>
24562 
          <displayName>EP7R</displayName>
24563 
          <description>endpoint 7 register</description>
24564 
          <addressOffset>0x1C</addressOffset>
24565 
          <size>0x20</size>
24566 
          <access>read-write</access>
24567 
          <resetValue>0x00000000</resetValue>
24568 
          <fields>
24569 
            <field>
24570 
              <name>EA</name>
24571 
              <description>Endpoint address</description>
24572 
              <bitOffset>0</bitOffset>
24573 
              <bitWidth>4</bitWidth>
24574 
            </field>
24575 
            <field>
24576 
              <name>STAT_TX</name>
24577 
              <description>Status bits, for transmission
24578 
              transfers</description>
24579 
              <bitOffset>4</bitOffset>
24580 
              <bitWidth>2</bitWidth>
24581 
            </field>
24582 
            <field>
24583 
              <name>DTOG_TX</name>
24584 
              <description>Data Toggle, for transmission
24585 
              transfers</description>
24586 
              <bitOffset>6</bitOffset>
24587 
              <bitWidth>1</bitWidth>
24588 
            </field>
24589 
            <field>
24590 
              <name>CTR_TX</name>
24591 
              <description>Correct Transfer for
24592 
              transmission</description>
24593 
              <bitOffset>7</bitOffset>
24594 
              <bitWidth>1</bitWidth>
24595 
            </field>
24596 
            <field>
24597 
              <name>EP_KIND</name>
24598 
              <description>Endpoint kind</description>
24599 
              <bitOffset>8</bitOffset>
24600 
              <bitWidth>1</bitWidth>
24601 
            </field>
24602 
            <field>
24603 
              <name>EP_TYPE</name>
24604 
              <description>Endpoint type</description>
24605 
              <bitOffset>9</bitOffset>
24606 
              <bitWidth>2</bitWidth>
24607 
            </field>
24608 
            <field>
24609 
              <name>SETUP</name>
24610 
              <description>Setup transaction
24611 
              completed</description>
24612 
              <bitOffset>11</bitOffset>
24613 
              <bitWidth>1</bitWidth>
24614 
            </field>
24615 
            <field>
24616 
              <name>STAT_RX</name>
24617 
              <description>Status bits, for reception
24618 
              transfers</description>
24619 
              <bitOffset>12</bitOffset>
24620 
              <bitWidth>2</bitWidth>
24621 
            </field>
24622 
            <field>
24623 
              <name>DTOG_RX</name>
24624 
              <description>Data Toggle, for reception
24625 
              transfers</description>
24626 
              <bitOffset>14</bitOffset>
24627 
              <bitWidth>1</bitWidth>
24628 
            </field>
24629 
            <field>
24630 
              <name>CTR_RX</name>
24631 
              <description>Correct transfer for
24632 
              reception</description>
24633 
              <bitOffset>15</bitOffset>
24634 
              <bitWidth>1</bitWidth>
24635 
            </field>
24636 
          </fields>
24637 
        </register>
24638 
        <register>
24639 
          <name>CNTR</name>
24640 
          <displayName>CNTR</displayName>
24641 
          <description>control register</description>
24642 
          <addressOffset>0x40</addressOffset>
24643 
          <size>0x20</size>
24644 
          <access>read-write</access>
24645 
          <resetValue>0x00000003</resetValue>
24646 
          <fields>
24647 
            <field>
24648 
              <name>FRES</name>
24649 
              <description>Force USB Reset</description>
24650 
              <bitOffset>0</bitOffset>
24651 
              <bitWidth>1</bitWidth>
24652 
            </field>
24653 
            <field>
24654 
              <name>PDWN</name>
24655 
              <description>Power down</description>
24656 
              <bitOffset>1</bitOffset>
24657 
              <bitWidth>1</bitWidth>
24658 
            </field>
24659 
            <field>
24660 
              <name>LPMODE</name>
24661 
              <description>Low-power mode</description>
24662 
              <bitOffset>2</bitOffset>
24663 
              <bitWidth>1</bitWidth>
24664 
            </field>
24665 
            <field>
24666 
              <name>FSUSP</name>
24667 
              <description>Force suspend</description>
24668 
              <bitOffset>3</bitOffset>
24669 
              <bitWidth>1</bitWidth>
24670 
            </field>
24671 
            <field>
24672 
              <name>RESUME</name>
24673 
              <description>Resume request</description>
24674 
              <bitOffset>4</bitOffset>
24675 
              <bitWidth>1</bitWidth>
24676 
            </field>
24677 
            <field>
24678 
              <name>ESOFM</name>
24679 
              <description>Expected start of frame interrupt
24680 
              mask</description>
24681 
              <bitOffset>8</bitOffset>
24682 
              <bitWidth>1</bitWidth>
24683 
            </field>
24684 
            <field>
24685 
              <name>SOFM</name>
24686 
              <description>Start of frame interrupt
24687 
              mask</description>
24688 
              <bitOffset>9</bitOffset>
24689 
              <bitWidth>1</bitWidth>
24690 
            </field>
24691 
            <field>
24692 
              <name>RESETM</name>
24693 
              <description>USB reset interrupt mask</description>
24694 
              <bitOffset>10</bitOffset>
24695 
              <bitWidth>1</bitWidth>
24696 
            </field>
24697 
            <field>
24698 
              <name>SUSPM</name>
24699 
              <description>Suspend mode interrupt
24700 
              mask</description>
24701 
              <bitOffset>11</bitOffset>
24702 
              <bitWidth>1</bitWidth>
24703 
            </field>
24704 
            <field>
24705 
              <name>WKUPM</name>
24706 
              <description>Wakeup interrupt mask</description>
24707 
              <bitOffset>12</bitOffset>
24708 
              <bitWidth>1</bitWidth>
24709 
            </field>
24710 
            <field>
24711 
              <name>ERRM</name>
24712 
              <description>Error interrupt mask</description>
24713 
              <bitOffset>13</bitOffset>
24714 
              <bitWidth>1</bitWidth>
24715 
            </field>
24716 
            <field>
24717 
              <name>PMAOVRM</name>
24718 
              <description>Packet memory area over / underrun
24719 
              interrupt mask</description>
24720 
              <bitOffset>14</bitOffset>
24721 
              <bitWidth>1</bitWidth>
24722 
            </field>
24723 
            <field>
24724 
              <name>CTRM</name>
24725 
              <description>Correct transfer interrupt
24726 
              mask</description>
24727 
              <bitOffset>15</bitOffset>
24728 
              <bitWidth>1</bitWidth>
24729 
            </field>
24730 
          </fields>
24731 
        </register>
24732 
        <register>
24733 
          <name>ISTR</name>
24734 
          <displayName>ISTR</displayName>
24735 
          <description>interrupt status register</description>
24736 
          <addressOffset>0x44</addressOffset>
24737 
          <size>0x20</size>
24738 
          <access>read-write</access>
24739 
          <resetValue>0x00000000</resetValue>
24740 
          <fields>
24741 
            <field>
24742 
              <name>EP_ID</name>
24743 
              <description>Endpoint Identifier</description>
24744 
              <bitOffset>0</bitOffset>
24745 
              <bitWidth>4</bitWidth>
24746 
            </field>
24747 
            <field>
24748 
              <name>DIR</name>
24749 
              <description>Direction of transaction</description>
24750 
              <bitOffset>4</bitOffset>
24751 
              <bitWidth>1</bitWidth>
24752 
            </field>
24753 
            <field>
24754 
              <name>ESOF</name>
24755 
              <description>Expected start frame</description>
24756 
              <bitOffset>8</bitOffset>
24757 
              <bitWidth>1</bitWidth>
24758 
            </field>
24759 
            <field>
24760 
              <name>SOF</name>
24761 
              <description>start of frame</description>
24762 
              <bitOffset>9</bitOffset>
24763 
              <bitWidth>1</bitWidth>
24764 
            </field>
24765 
            <field>
24766 
              <name>RESET</name>
24767 
              <description>reset request</description>
24768 
              <bitOffset>10</bitOffset>
24769 
              <bitWidth>1</bitWidth>
24770 
            </field>
24771 
            <field>
24772 
              <name>SUSP</name>
24773 
              <description>Suspend mode request</description>
24774 
              <bitOffset>11</bitOffset>
24775 
              <bitWidth>1</bitWidth>
24776 
            </field>
24777 
            <field>
24778 
              <name>WKUP</name>
24779 
              <description>Wakeup</description>
24780 
              <bitOffset>12</bitOffset>
24781 
              <bitWidth>1</bitWidth>
24782 
            </field>
24783 
            <field>
24784 
              <name>ERR</name>
24785 
              <description>Error</description>
24786 
              <bitOffset>13</bitOffset>
24787 
              <bitWidth>1</bitWidth>
24788 
            </field>
24789 
            <field>
24790 
              <name>PMAOVR</name>
24791 
              <description>Packet memory area over /
24792 
              underrun</description>
24793 
              <bitOffset>14</bitOffset>
24794 
              <bitWidth>1</bitWidth>
24795 
            </field>
24796 
            <field>
24797 
              <name>CTR</name>
24798 
              <description>Correct transfer</description>
24799 
              <bitOffset>15</bitOffset>
24800 
              <bitWidth>1</bitWidth>
24801 
            </field>
24802 
          </fields>
24803 
        </register>
24804 
        <register>
24805 
          <name>FNR</name>
24806 
          <displayName>FNR</displayName>
24807 
          <description>frame number register</description>
24808 
          <addressOffset>0x48</addressOffset>
24809 
          <size>0x20</size>
24810 
          <access>read-only</access>
24811 
          <resetValue>0x0000</resetValue>
24812 
          <fields>
24813 
            <field>
24814 
              <name>FN</name>
24815 
              <description>Frame number</description>
24816 
              <bitOffset>0</bitOffset>
24817 
              <bitWidth>11</bitWidth>
24818 
            </field>
24819 
            <field>
24820 
              <name>LSOF</name>
24821 
              <description>Lost SOF</description>
24822 
              <bitOffset>11</bitOffset>
24823 
              <bitWidth>2</bitWidth>
24824 
            </field>
24825 
            <field>
24826 
              <name>LCK</name>
24827 
              <description>Locked</description>
24828 
              <bitOffset>13</bitOffset>
24829 
              <bitWidth>1</bitWidth>
24830 
            </field>
24831 
            <field>
24832 
              <name>RXDM</name>
24833 
              <description>Receive data - line status</description>
24834 
              <bitOffset>14</bitOffset>
24835 
              <bitWidth>1</bitWidth>
24836 
            </field>
24837 
            <field>
24838 
              <name>RXDP</name>
24839 
              <description>Receive data + line status</description>
24840 
              <bitOffset>15</bitOffset>
24841 
              <bitWidth>1</bitWidth>
24842 
            </field>
24843 
          </fields>
24844 
        </register>
24845 
        <register>
24846 
          <name>DADDR</name>
24847 
          <displayName>DADDR</displayName>
24848 
          <description>device address</description>
24849 
          <addressOffset>0x4C</addressOffset>
24850 
          <size>0x20</size>
24851 
          <access>read-write</access>
24852 
          <resetValue>0x0000</resetValue>
24853 
          <fields>
24854 
            <field>
24855 
              <name>ADD</name>
24856 
              <description>Device address</description>
24857 
              <bitOffset>0</bitOffset>
24858 
              <bitWidth>7</bitWidth>
24859 
            </field>
24860 
            <field>
24861 
              <name>EF</name>
24862 
              <description>Enable function</description>
24863 
              <bitOffset>7</bitOffset>
24864 
              <bitWidth>1</bitWidth>
24865 
            </field>
24866 
          </fields>
24867 
        </register>
24868 
        <register>
24869 
          <name>BTABLE</name>
24870 
          <displayName>BTABLE</displayName>
24871 
          <description>Buffer table address</description>
24872 
          <addressOffset>0x50</addressOffset>
24873 
          <size>0x20</size>
24874 
          <access>read-write</access>
24875 
          <resetValue>0x0000</resetValue>
24876 
          <fields>
24877 
            <field>
24878 
              <name>BTABLE</name>
24879 
              <description>Buffer table</description>
24880 
              <bitOffset>3</bitOffset>
24881 
              <bitWidth>13</bitWidth>
24882 
            </field>
24883 
          </fields>
24884 
        </register>
24885 
      </registers>
24886 
    </peripheral>
24887 
    <peripheral>
24888 
      <name>OTG_FS_DEVICE</name>
24889 
      <description>USB on the go full speed</description>
24890 
      <groupName>USB_OTG_FS</groupName>
24891 
      <baseAddress>0x50000800</baseAddress>
24892 
      <addressBlock>
24893 
        <offset>0x0</offset>
24894 
        <size>0x400</size>
24895 
        <usage>registers</usage>
24896 
      </addressBlock>
24897 
      <registers>
24898 
        <register>
24899 
          <name>FS_DCFG</name>
24900 
          <displayName>FS_DCFG</displayName>
24901 
          <description>OTG_FS device configuration register
24902 
          (OTG_FS_DCFG)</description>
24903 
          <addressOffset>0x0</addressOffset>
24904 
          <size>0x20</size>
24905 
          <access>read-write</access>
24906 
          <resetValue>0x02200000</resetValue>
24907 
          <fields>
24908 
            <field>
24909 
              <name>DSPD</name>
24910 
              <description>Device speed</description>
24911 
              <bitOffset>0</bitOffset>
24912 
              <bitWidth>2</bitWidth>
24913 
            </field>
24914 
            <field>
24915 
              <name>NZLSOHSK</name>
24916 
              <description>Non-zero-length status OUT
24917 
              handshake</description>
24918 
              <bitOffset>2</bitOffset>
24919 
              <bitWidth>1</bitWidth>
24920 
            </field>
24921 
            <field>
24922 
              <name>DAD</name>
24923 
              <description>Device address</description>
24924 
              <bitOffset>4</bitOffset>
24925 
              <bitWidth>7</bitWidth>
24926 
            </field>
24927 
            <field>
24928 
              <name>PFIVL</name>
24929 
              <description>Periodic frame interval</description>
24930 
              <bitOffset>11</bitOffset>
24931 
              <bitWidth>2</bitWidth>
24932 
            </field>
24933 
          </fields>
24934 
        </register>
24935 
        <register>
24936 
          <name>FS_DCTL</name>
24937 
          <displayName>FS_DCTL</displayName>
24938 
          <description>OTG_FS device control register
24939 
          (OTG_FS_DCTL)</description>
24940 
          <addressOffset>0x4</addressOffset>
24941 
          <size>0x20</size>
24942 
          <resetValue>0x00000000</resetValue>
24943 
          <fields>
24944 
            <field>
24945 
              <name>RWUSIG</name>
24946 
              <description>Remote wakeup signaling</description>
24947 
              <bitOffset>0</bitOffset>
24948 
              <bitWidth>1</bitWidth>
24949 
              <access>read-write</access>
24950 
            </field>
24951 
            <field>
24952 
              <name>SDIS</name>
24953 
              <description>Soft disconnect</description>
24954 
              <bitOffset>1</bitOffset>
24955 
              <bitWidth>1</bitWidth>
24956 
              <access>read-write</access>
24957 
            </field>
24958 
            <field>
24959 
              <name>GINSTS</name>
24960 
              <description>Global IN NAK status</description>
24961 
              <bitOffset>2</bitOffset>
24962 
              <bitWidth>1</bitWidth>
24963 
              <access>read-only</access>
24964 
            </field>
24965 
            <field>
24966 
              <name>GONSTS</name>
24967 
              <description>Global OUT NAK status</description>
24968 
              <bitOffset>3</bitOffset>
24969 
              <bitWidth>1</bitWidth>
24970 
              <access>read-only</access>
24971 
            </field>
24972 
            <field>
24973 
              <name>TCTL</name>
24974 
              <description>Test control</description>
24975 
              <bitOffset>4</bitOffset>
24976 
              <bitWidth>3</bitWidth>
24977 
              <access>read-write</access>
24978 
            </field>
24979 
            <field>
24980 
              <name>SGINAK</name>
24981 
              <description>Set global IN NAK</description>
24982 
              <bitOffset>7</bitOffset>
24983 
              <bitWidth>1</bitWidth>
24984 
              <access>read-write</access>
24985 
            </field>
24986 
            <field>
24987 
              <name>CGINAK</name>
24988 
              <description>Clear global IN NAK</description>
24989 
              <bitOffset>8</bitOffset>
24990 
              <bitWidth>1</bitWidth>
24991 
              <access>read-write</access>
24992 
            </field>
24993 
            <field>
24994 
              <name>SGONAK</name>
24995 
              <description>Set global OUT NAK</description>
24996 
              <bitOffset>9</bitOffset>
24997 
              <bitWidth>1</bitWidth>
24998 
              <access>read-write</access>
24999 
            </field>
25000 
            <field>
25001 
              <name>CGONAK</name>
25002 
              <description>Clear global OUT NAK</description>
25003 
              <bitOffset>10</bitOffset>
25004 
              <bitWidth>1</bitWidth>
25005 
              <access>read-write</access>
25006 
            </field>
25007 
            <field>
25008 
              <name>POPRGDNE</name>
25009 
              <description>Power-on programming done</description>
25010 
              <bitOffset>11</bitOffset>
25011 
              <bitWidth>1</bitWidth>
25012 
              <access>read-write</access>
25013 
            </field>
25014 
          </fields>
25015 
        </register>
25016 
        <register>
25017 
          <name>FS_DSTS</name>
25018 
          <displayName>FS_DSTS</displayName>
25019 
          <description>OTG_FS device status register
25020 
          (OTG_FS_DSTS)</description>
25021 
          <addressOffset>0x8</addressOffset>
25022 
          <size>0x20</size>
25023 
          <access>read-only</access>
25024 
          <resetValue>0x00000010</resetValue>
25025 
          <fields>
25026 
            <field>
25027 
              <name>SUSPSTS</name>
25028 
              <description>Suspend status</description>
25029 
              <bitOffset>0</bitOffset>
25030 
              <bitWidth>1</bitWidth>
25031 
            </field>
25032 
            <field>
25033 
              <name>ENUMSPD</name>
25034 
              <description>Enumerated speed</description>
25035 
              <bitOffset>1</bitOffset>
25036 
              <bitWidth>2</bitWidth>
25037 
            </field>
25038 
            <field>
25039 
              <name>EERR</name>
25040 
              <description>Erratic error</description>
25041 
              <bitOffset>3</bitOffset>
25042 
              <bitWidth>1</bitWidth>
25043 
            </field>
25044 
            <field>
25045 
              <name>FNSOF</name>
25046 
              <description>Frame number of the received
25047 
              SOF</description>
25048 
              <bitOffset>8</bitOffset>
25049 
              <bitWidth>14</bitWidth>
25050 
            </field>
25051 
          </fields>
25052 
        </register>
25053 
        <register>
25054 
          <name>FS_DIEPMSK</name>
25055 
          <displayName>FS_DIEPMSK</displayName>
25056 
          <description>OTG_FS device IN endpoint common interrupt
25057 
          mask register (OTG_FS_DIEPMSK)</description>
25058 
          <addressOffset>0x10</addressOffset>
25059 
          <size>0x20</size>
25060 
          <access>read-write</access>
25061 
          <resetValue>0x00000000</resetValue>
25062 
          <fields>
25063 
            <field>
25064 
              <name>XFRCM</name>
25065 
              <description>Transfer completed interrupt
25066 
              mask</description>
25067 
              <bitOffset>0</bitOffset>
25068 
              <bitWidth>1</bitWidth>
25069 
            </field>
25070 
            <field>
25071 
              <name>EPDM</name>
25072 
              <description>Endpoint disabled interrupt
25073 
              mask</description>
25074 
              <bitOffset>1</bitOffset>
25075 
              <bitWidth>1</bitWidth>
25076 
            </field>
25077 
            <field>
25078 
              <name>TOM</name>
25079 
              <description>Timeout condition mask (Non-isochronous
25080 
              endpoints)</description>
25081 
              <bitOffset>3</bitOffset>
25082 
              <bitWidth>1</bitWidth>
25083 
            </field>
25084 
            <field>
25085 
              <name>ITTXFEMSK</name>
25086 
              <description>IN token received when TxFIFO empty
25087 
              mask</description>
25088 
              <bitOffset>4</bitOffset>
25089 
              <bitWidth>1</bitWidth>
25090 
            </field>
25091 
            <field>
25092 
              <name>INEPNMM</name>
25093 
              <description>IN token received with EP mismatch
25094 
              mask</description>
25095 
              <bitOffset>5</bitOffset>
25096 
              <bitWidth>1</bitWidth>
25097 
            </field>
25098 
            <field>
25099 
              <name>INEPNEM</name>
25100 
              <description>IN endpoint NAK effective
25101 
              mask</description>
25102 
              <bitOffset>6</bitOffset>
25103 
              <bitWidth>1</bitWidth>
25104 
            </field>
25105 
          </fields>
25106 
        </register>
25107 
        <register>
25108 
          <name>FS_DOEPMSK</name>
25109 
          <displayName>FS_DOEPMSK</displayName>
25110 
          <description>OTG_FS device OUT endpoint common interrupt
25111 
          mask register (OTG_FS_DOEPMSK)</description>
25112 
          <addressOffset>0x14</addressOffset>
25113 
          <size>0x20</size>
25114 
          <access>read-write</access>
25115 
          <resetValue>0x00000000</resetValue>
25116 
          <fields>
25117 
            <field>
25118 
              <name>XFRCM</name>
25119 
              <description>Transfer completed interrupt
25120 
              mask</description>
25121 
              <bitOffset>0</bitOffset>
25122 
              <bitWidth>1</bitWidth>
25123 
            </field>
25124 
            <field>
25125 
              <name>EPDM</name>
25126 
              <description>Endpoint disabled interrupt
25127 
              mask</description>
25128 
              <bitOffset>1</bitOffset>
25129 
              <bitWidth>1</bitWidth>
25130 
            </field>
25131 
            <field>
25132 
              <name>STUPM</name>
25133 
              <description>SETUP phase done mask</description>
25134 
              <bitOffset>3</bitOffset>
25135 
              <bitWidth>1</bitWidth>
25136 
            </field>
25137 
            <field>
25138 
              <name>OTEPDM</name>
25139 
              <description>OUT token received when endpoint
25140 
              disabled mask</description>
25141 
              <bitOffset>4</bitOffset>
25142 
              <bitWidth>1</bitWidth>
25143 
            </field>
25144 
          </fields>
25145 
        </register>
25146 
        <register>
25147 
          <name>FS_DAINT</name>
25148 
          <displayName>FS_DAINT</displayName>
25149 
          <description>OTG_FS device all endpoints interrupt
25150 
          register (OTG_FS_DAINT)</description>
25151 
          <addressOffset>0x18</addressOffset>
25152 
          <size>0x20</size>
25153 
          <access>read-only</access>
25154 
          <resetValue>0x00000000</resetValue>
25155 
          <fields>
25156 
            <field>
25157 
              <name>IEPINT</name>
25158 
              <description>IN endpoint interrupt bits</description>
25159 
              <bitOffset>0</bitOffset>
25160 
              <bitWidth>16</bitWidth>
25161 
            </field>
25162 
            <field>
25163 
              <name>OEPINT</name>
25164 
              <description>OUT endpoint interrupt
25165 
              bits</description>
25166 
              <bitOffset>16</bitOffset>
25167 
              <bitWidth>16</bitWidth>
25168 
            </field>
25169 
          </fields>
25170 
        </register>
25171 
        <register>
25172 
          <name>FS_DAINTMSK</name>
25173 
          <displayName>FS_DAINTMSK</displayName>
25174 
          <description>OTG_FS all endpoints interrupt mask register
25175 
          (OTG_FS_DAINTMSK)</description>
25176 
          <addressOffset>0x1C</addressOffset>
25177 
          <size>0x20</size>
25178 
          <access>read-write</access>
25179 
          <resetValue>0x00000000</resetValue>
25180 
          <fields>
25181 
            <field>
25182 
              <name>IEPM</name>
25183 
              <description>IN EP interrupt mask bits</description>
25184 
              <bitOffset>0</bitOffset>
25185 
              <bitWidth>16</bitWidth>
25186 
            </field>
25187 
            <field>
25188 
              <name>OEPINT</name>
25189 
              <description>OUT endpoint interrupt
25190 
              bits</description>
25191 
              <bitOffset>16</bitOffset>
25192 
              <bitWidth>16</bitWidth>
25193 
            </field>
25194 
          </fields>
25195 
        </register>
25196 
        <register>
25197 
          <name>DVBUSDIS</name>
25198 
          <displayName>DVBUSDIS</displayName>
25199 
          <description>OTG_FS device VBUS discharge time
25200 
          register</description>
25201 
          <addressOffset>0x28</addressOffset>
25202 
          <size>0x20</size>
25203 
          <access>read-write</access>
25204 
          <resetValue>0x000017D7</resetValue>
25205 
          <fields>
25206 
            <field>
25207 
              <name>VBUSDT</name>
25208 
              <description>Device VBUS discharge time</description>
25209 
              <bitOffset>0</bitOffset>
25210 
              <bitWidth>16</bitWidth>
25211 
            </field>
25212 
          </fields>
25213 
        </register>
25214 
        <register>
25215 
          <name>DVBUSPULSE</name>
25216 
          <displayName>DVBUSPULSE</displayName>
25217 
          <description>OTG_FS device VBUS pulsing time
25218 
          register</description>
25219 
          <addressOffset>0x2C</addressOffset>
25220 
          <size>0x20</size>
25221 
          <access>read-write</access>
25222 
          <resetValue>0x000005B8</resetValue>
25223 
          <fields>
25224 
            <field>
25225 
              <name>DVBUSP</name>
25226 
              <description>Device VBUS pulsing time</description>
25227 
              <bitOffset>0</bitOffset>
25228 
              <bitWidth>12</bitWidth>
25229 
            </field>
25230 
          </fields>
25231 
        </register>
25232 
        <register>
25233 
          <name>DIEPEMPMSK</name>
25234 
          <displayName>DIEPEMPMSK</displayName>
25235 
          <description>OTG_FS device IN endpoint FIFO empty
25236 
          interrupt mask register</description>
25237 
          <addressOffset>0x34</addressOffset>
25238 
          <size>0x20</size>
25239 
          <access>read-write</access>
25240 
          <resetValue>0x00000000</resetValue>
25241 
          <fields>
25242 
            <field>
25243 
              <name>INEPTXFEM</name>
25244 
              <description>IN EP Tx FIFO empty interrupt mask
25245 
              bits</description>
25246 
              <bitOffset>0</bitOffset>
25247 
              <bitWidth>16</bitWidth>
25248 
            </field>
25249 
          </fields>
25250 
        </register>
25251 
        <register>
25252 
          <name>FS_DIEPCTL0</name>
25253 
          <displayName>FS_DIEPCTL0</displayName>
25254 
          <description>OTG_FS device control IN endpoint 0 control
25255 
          register (OTG_FS_DIEPCTL0)</description>
25256 
          <addressOffset>0x100</addressOffset>
25257 
          <size>0x20</size>
25258 
          <resetValue>0x00000000</resetValue>
25259 
          <fields>
25260 
            <field>
25261 
              <name>MPSIZ</name>
25262 
              <description>Maximum packet size</description>
25263 
              <bitOffset>0</bitOffset>
25264 
              <bitWidth>2</bitWidth>
25265 
              <access>read-write</access>
25266 
            </field>
25267 
            <field>
25268 
              <name>USBAEP</name>
25269 
              <description>USB active endpoint</description>
25270 
              <bitOffset>15</bitOffset>
25271 
              <bitWidth>1</bitWidth>
25272 
              <access>read-only</access>
25273 
            </field>
25274 
            <field>
25275 
              <name>NAKSTS</name>
25276 
              <description>NAK status</description>
25277 
              <bitOffset>17</bitOffset>
25278 
              <bitWidth>1</bitWidth>
25279 
              <access>read-only</access>
25280 
            </field>
25281 
            <field>
25282 
              <name>EPTYP</name>
25283 
              <description>Endpoint type</description>
25284 
              <bitOffset>18</bitOffset>
25285 
              <bitWidth>2</bitWidth>
25286 
              <access>read-only</access>
25287 
            </field>
25288 
            <field>
25289 
              <name>STALL</name>
25290 
              <description>STALL handshake</description>
25291 
              <bitOffset>21</bitOffset>
25292 
              <bitWidth>1</bitWidth>
25293 
              <access>read-write</access>
25294 
            </field>
25295 
            <field>
25296 
              <name>TXFNUM</name>
25297 
              <description>TxFIFO number</description>
25298 
              <bitOffset>22</bitOffset>
25299 
              <bitWidth>4</bitWidth>
25300 
              <access>read-write</access>
25301 
            </field>
25302 
            <field>
25303 
              <name>CNAK</name>
25304 
              <description>Clear NAK</description>
25305 
              <bitOffset>26</bitOffset>
25306 
              <bitWidth>1</bitWidth>
25307 
              <access>write-only</access>
25308 
            </field>
25309 
            <field>
25310 
              <name>SNAK</name>
25311 
              <description>Set NAK</description>
25312 
              <bitOffset>27</bitOffset>
25313 
              <bitWidth>1</bitWidth>
25314 
              <access>write-only</access>
25315 
            </field>
25316 
            <field>
25317 
              <name>EPDIS</name>
25318 
              <description>Endpoint disable</description>
25319 
              <bitOffset>30</bitOffset>
25320 
              <bitWidth>1</bitWidth>
25321 
              <access>read-only</access>
25322 
            </field>
25323 
            <field>
25324 
              <name>EPENA</name>
25325 
              <description>Endpoint enable</description>
25326 
              <bitOffset>31</bitOffset>
25327 
              <bitWidth>1</bitWidth>
25328 
              <access>read-only</access>
25329 
            </field>
25330 
          </fields>
25331 
        </register>
25332 
        <register>
25333 
          <name>DIEPCTL1</name>
25334 
          <displayName>DIEPCTL1</displayName>
25335 
          <description>OTG device endpoint-1 control
25336 
          register</description>
25337 
          <addressOffset>0x120</addressOffset>
25338 
          <size>0x20</size>
25339 
          <resetValue>0x00000000</resetValue>
25340 
          <fields>
25341 
            <field>
25342 
              <name>EPENA</name>
25343 
              <description>EPENA</description>
25344 
              <bitOffset>31</bitOffset>
25345 
              <bitWidth>1</bitWidth>
25346 
              <access>read-write</access>
25347 
            </field>
25348 
            <field>
25349 
              <name>EPDIS</name>
25350 
              <description>EPDIS</description>
25351 
              <bitOffset>30</bitOffset>
25352 
              <bitWidth>1</bitWidth>
25353 
              <access>read-write</access>
25354 
            </field>
25355 
            <field>
25356 
              <name>SODDFRM_SD1PID</name>
25357 
              <description>SODDFRM/SD1PID</description>
25358 
              <bitOffset>29</bitOffset>
25359 
              <bitWidth>1</bitWidth>
25360 
              <access>write-only</access>
25361 
            </field>
25362 
            <field>
25363 
              <name>SD0PID_SEVNFRM</name>
25364 
              <description>SD0PID/SEVNFRM</description>
25365 
              <bitOffset>28</bitOffset>
25366 
              <bitWidth>1</bitWidth>
25367 
              <access>write-only</access>
25368 
            </field>
25369 
            <field>
25370 
              <name>SNAK</name>
25371 
              <description>SNAK</description>
25372 
              <bitOffset>27</bitOffset>
25373 
              <bitWidth>1</bitWidth>
25374 
              <access>write-only</access>
25375 
            </field>
25376 
            <field>
25377 
              <name>CNAK</name>
25378 
              <description>CNAK</description>
25379 
              <bitOffset>26</bitOffset>
25380 
              <bitWidth>1</bitWidth>
25381 
              <access>write-only</access>
25382 
            </field>
25383 
            <field>
25384 
              <name>TXFNUM</name>
25385 
              <description>TXFNUM</description>
25386 
              <bitOffset>22</bitOffset>
25387 
              <bitWidth>4</bitWidth>
25388 
              <access>read-write</access>
25389 
            </field>
25390 
            <field>
25391 
              <name>Stall</name>
25392 
              <description>Stall</description>
25393 
              <bitOffset>21</bitOffset>
25394 
              <bitWidth>1</bitWidth>
25395 
              <access>read-write</access>
25396 
            </field>
25397 
            <field>
25398 
              <name>EPTYP</name>
25399 
              <description>EPTYP</description>
25400 
              <bitOffset>18</bitOffset>
25401 
              <bitWidth>2</bitWidth>
25402 
              <access>read-write</access>
25403 
            </field>
25404 
            <field>
25405 
              <name>NAKSTS</name>
25406 
              <description>NAKSTS</description>
25407 
              <bitOffset>17</bitOffset>
25408 
              <bitWidth>1</bitWidth>
25409 
              <access>read-only</access>
25410 
            </field>
25411 
            <field>
25412 
              <name>EONUM_DPID</name>
25413 
              <description>EONUM/DPID</description>
25414 
              <bitOffset>16</bitOffset>
25415 
              <bitWidth>1</bitWidth>
25416 
              <access>read-only</access>
25417 
            </field>
25418 
            <field>
25419 
              <name>USBAEP</name>
25420 
              <description>USBAEP</description>
25421 
              <bitOffset>15</bitOffset>
25422 
              <bitWidth>1</bitWidth>
25423 
              <access>read-write</access>
25424 
            </field>
25425 
            <field>
25426 
              <name>MPSIZ</name>
25427 
              <description>MPSIZ</description>
25428 
              <bitOffset>0</bitOffset>
25429 
              <bitWidth>11</bitWidth>
25430 
              <access>read-write</access>
25431 
            </field>
25432 
          </fields>
25433 
        </register>
25434 
        <register>
25435 
          <name>DIEPCTL2</name>
25436 
          <displayName>DIEPCTL2</displayName>
25437 
          <description>OTG device endpoint-2 control
25438 
          register</description>
25439 
          <addressOffset>0x140</addressOffset>
25440 
          <size>0x20</size>
25441 
          <resetValue>0x00000000</resetValue>
25442 
          <fields>
25443 
            <field>
25444 
              <name>EPENA</name>
25445 
              <description>EPENA</description>
25446 
              <bitOffset>31</bitOffset>
25447 
              <bitWidth>1</bitWidth>
25448 
              <access>read-write</access>
25449 
            </field>
25450 
            <field>
25451 
              <name>EPDIS</name>
25452 
              <description>EPDIS</description>
25453 
              <bitOffset>30</bitOffset>
25454 
              <bitWidth>1</bitWidth>
25455 
              <access>read-write</access>
25456 
            </field>
25457 
            <field>
25458 
              <name>SODDFRM</name>
25459 
              <description>SODDFRM</description>
25460 
              <bitOffset>29</bitOffset>
25461 
              <bitWidth>1</bitWidth>
25462 
              <access>write-only</access>
25463 
            </field>
25464 
            <field>
25465 
              <name>SD0PID_SEVNFRM</name>
25466 
              <description>SD0PID/SEVNFRM</description>
25467 
              <bitOffset>28</bitOffset>
25468 
              <bitWidth>1</bitWidth>
25469 
              <access>write-only</access>
25470 
            </field>
25471 
            <field>
25472 
              <name>SNAK</name>
25473 
              <description>SNAK</description>
25474 
              <bitOffset>27</bitOffset>
25475 
              <bitWidth>1</bitWidth>
25476 
              <access>write-only</access>
25477 
            </field>
25478 
            <field>
25479 
              <name>CNAK</name>
25480 
              <description>CNAK</description>
25481 
              <bitOffset>26</bitOffset>
25482 
              <bitWidth>1</bitWidth>
25483 
              <access>write-only</access>
25484 
            </field>
25485 
            <field>
25486 
              <name>TXFNUM</name>
25487 
              <description>TXFNUM</description>
25488 
              <bitOffset>22</bitOffset>
25489 
              <bitWidth>4</bitWidth>
25490 
              <access>read-write</access>
25491 
            </field>
25492 
            <field>
25493 
              <name>Stall</name>
25494 
              <description>Stall</description>
25495 
              <bitOffset>21</bitOffset>
25496 
              <bitWidth>1</bitWidth>
25497 
              <access>read-write</access>
25498 
            </field>
25499 
            <field>
25500 
              <name>EPTYP</name>
25501 
              <description>EPTYP</description>
25502 
              <bitOffset>18</bitOffset>
25503 
              <bitWidth>2</bitWidth>
25504 
              <access>read-write</access>
25505 
            </field>
25506 
            <field>
25507 
              <name>NAKSTS</name>
25508 
              <description>NAKSTS</description>
25509 
              <bitOffset>17</bitOffset>
25510 
              <bitWidth>1</bitWidth>
25511 
              <access>read-only</access>
25512 
            </field>
25513 
            <field>
25514 
              <name>EONUM_DPID</name>
25515 
              <description>EONUM/DPID</description>
25516 
              <bitOffset>16</bitOffset>
25517 
              <bitWidth>1</bitWidth>
25518 
              <access>read-only</access>
25519 
            </field>
25520 
            <field>
25521 
              <name>USBAEP</name>
25522 
              <description>USBAEP</description>
25523 
              <bitOffset>15</bitOffset>
25524 
              <bitWidth>1</bitWidth>
25525 
              <access>read-write</access>
25526 
            </field>
25527 
            <field>
25528 
              <name>MPSIZ</name>
25529 
              <description>MPSIZ</description>
25530 
              <bitOffset>0</bitOffset>
25531 
              <bitWidth>11</bitWidth>
25532 
              <access>read-write</access>
25533 
            </field>
25534 
          </fields>
25535 
        </register>
25536 
        <register>
25537 
          <name>DIEPCTL3</name>
25538 
          <displayName>DIEPCTL3</displayName>
25539 
          <description>OTG device endpoint-3 control
25540 
          register</description>
25541 
          <addressOffset>0x160</addressOffset>
25542 
          <size>0x20</size>
25543 
          <resetValue>0x00000000</resetValue>
25544 
          <fields>
25545 
            <field>
25546 
              <name>EPENA</name>
25547 
              <description>EPENA</description>
25548 
              <bitOffset>31</bitOffset>
25549 
              <bitWidth>1</bitWidth>
25550 
              <access>read-write</access>
25551 
            </field>
25552 
            <field>
25553 
              <name>EPDIS</name>
25554 
              <description>EPDIS</description>
25555 
              <bitOffset>30</bitOffset>
25556 
              <bitWidth>1</bitWidth>
25557 
              <access>read-write</access>
25558 
            </field>
25559 
            <field>
25560 
              <name>SODDFRM</name>
25561 
              <description>SODDFRM</description>
25562 
              <bitOffset>29</bitOffset>
25563 
              <bitWidth>1</bitWidth>
25564 
              <access>write-only</access>
25565 
            </field>
25566 
            <field>
25567 
              <name>SD0PID_SEVNFRM</name>
25568 
              <description>SD0PID/SEVNFRM</description>
25569 
              <bitOffset>28</bitOffset>
25570 
              <bitWidth>1</bitWidth>
25571 
              <access>write-only</access>
25572 
            </field>
25573 
            <field>
25574 
              <name>SNAK</name>
25575 
              <description>SNAK</description>
25576 
              <bitOffset>27</bitOffset>
25577 
              <bitWidth>1</bitWidth>
25578 
              <access>write-only</access>
25579 
            </field>
25580 
            <field>
25581 
              <name>CNAK</name>
25582 
              <description>CNAK</description>
25583 
              <bitOffset>26</bitOffset>
25584 
              <bitWidth>1</bitWidth>
25585 
              <access>write-only</access>
25586 
            </field>
25587 
            <field>
25588 
              <name>TXFNUM</name>
25589 
              <description>TXFNUM</description>
25590 
              <bitOffset>22</bitOffset>
25591 
              <bitWidth>4</bitWidth>
25592 
              <access>read-write</access>
25593 
            </field>
25594 
            <field>
25595 
              <name>Stall</name>
25596 
              <description>Stall</description>
25597 
              <bitOffset>21</bitOffset>
25598 
              <bitWidth>1</bitWidth>
25599 
              <access>read-write</access>
25600 
            </field>
25601 
            <field>
25602 
              <name>EPTYP</name>
25603 
              <description>EPTYP</description>
25604 
              <bitOffset>18</bitOffset>
25605 
              <bitWidth>2</bitWidth>
25606 
              <access>read-write</access>
25607 
            </field>
25608 
            <field>
25609 
              <name>NAKSTS</name>
25610 
              <description>NAKSTS</description>
25611 
              <bitOffset>17</bitOffset>
25612 
              <bitWidth>1</bitWidth>
25613 
              <access>read-only</access>
25614 
            </field>
25615 
            <field>
25616 
              <name>EONUM_DPID</name>
25617 
              <description>EONUM/DPID</description>
25618 
              <bitOffset>16</bitOffset>
25619 
              <bitWidth>1</bitWidth>
25620 
              <access>read-only</access>
25621 
            </field>
25622 
            <field>
25623 
              <name>USBAEP</name>
25624 
              <description>USBAEP</description>
25625 
              <bitOffset>15</bitOffset>
25626 
              <bitWidth>1</bitWidth>
25627 
              <access>read-write</access>
25628 
            </field>
25629 
            <field>
25630 
              <name>MPSIZ</name>
25631 
              <description>MPSIZ</description>
25632 
              <bitOffset>0</bitOffset>
25633 
              <bitWidth>11</bitWidth>
25634 
              <access>read-write</access>
25635 
            </field>
25636 
          </fields>
25637 
        </register>
25638 
        <register>
25639 
          <name>DOEPCTL0</name>
25640 
          <displayName>DOEPCTL0</displayName>
25641 
          <description>device endpoint-0 control
25642 
          register</description>
25643 
          <addressOffset>0x300</addressOffset>
25644 
          <size>0x20</size>
25645 
          <resetValue>0x00008000</resetValue>
25646 
          <fields>
25647 
            <field>
25648 
              <name>EPENA</name>
25649 
              <description>EPENA</description>
25650 
              <bitOffset>31</bitOffset>
25651 
              <bitWidth>1</bitWidth>
25652 
              <access>write-only</access>
25653 
            </field>
25654 
            <field>
25655 
              <name>EPDIS</name>
25656 
              <description>EPDIS</description>
25657 
              <bitOffset>30</bitOffset>
25658 
              <bitWidth>1</bitWidth>
25659 
              <access>read-only</access>
25660 
            </field>
25661 
            <field>
25662 
              <name>SNAK</name>
25663 
              <description>SNAK</description>
25664 
              <bitOffset>27</bitOffset>
25665 
              <bitWidth>1</bitWidth>
25666 
              <access>write-only</access>
25667 
            </field>
25668 
            <field>
25669 
              <name>CNAK</name>
25670 
              <description>CNAK</description>
25671 
              <bitOffset>26</bitOffset>
25672 
              <bitWidth>1</bitWidth>
25673 
              <access>write-only</access>
25674 
            </field>
25675 
            <field>
25676 
              <name>Stall</name>
25677 
              <description>Stall</description>
25678 
              <bitOffset>21</bitOffset>
25679 
              <bitWidth>1</bitWidth>
25680 
              <access>read-write</access>
25681 
            </field>
25682 
            <field>
25683 
              <name>SNPM</name>
25684 
              <description>SNPM</description>
25685 
              <bitOffset>20</bitOffset>
25686 
              <bitWidth>1</bitWidth>
25687 
              <access>read-write</access>
25688 
            </field>
25689 
            <field>
25690 
              <name>EPTYP</name>
25691 
              <description>EPTYP</description>
25692 
              <bitOffset>18</bitOffset>
25693 
              <bitWidth>2</bitWidth>
25694 
              <access>read-only</access>
25695 
            </field>
25696 
            <field>
25697 
              <name>NAKSTS</name>
25698 
              <description>NAKSTS</description>
25699 
              <bitOffset>17</bitOffset>
25700 
              <bitWidth>1</bitWidth>
25701 
              <access>read-only</access>
25702 
            </field>
25703 
            <field>
25704 
              <name>USBAEP</name>
25705 
              <description>USBAEP</description>
25706 
              <bitOffset>15</bitOffset>
25707 
              <bitWidth>1</bitWidth>
25708 
              <access>read-only</access>
25709 
            </field>
25710 
            <field>
25711 
              <name>MPSIZ</name>
25712 
              <description>MPSIZ</description>
25713 
              <bitOffset>0</bitOffset>
25714 
              <bitWidth>2</bitWidth>
25715 
              <access>read-only</access>
25716 
            </field>
25717 
          </fields>
25718 
        </register>
25719 
        <register>
25720 
          <name>DOEPCTL1</name>
25721 
          <displayName>DOEPCTL1</displayName>
25722 
          <description>device endpoint-1 control
25723 
          register</description>
25724 
          <addressOffset>0x320</addressOffset>
25725 
          <size>0x20</size>
25726 
          <resetValue>0x00000000</resetValue>
25727 
          <fields>
25728 
            <field>
25729 
              <name>EPENA</name>
25730 
              <description>EPENA</description>
25731 
              <bitOffset>31</bitOffset>
25732 
              <bitWidth>1</bitWidth>
25733 
              <access>read-write</access>
25734 
            </field>
25735 
            <field>
25736 
              <name>EPDIS</name>
25737 
              <description>EPDIS</description>
25738 
              <bitOffset>30</bitOffset>
25739 
              <bitWidth>1</bitWidth>
25740 
              <access>read-write</access>
25741 
            </field>
25742 
            <field>
25743 
              <name>SODDFRM</name>
25744 
              <description>SODDFRM</description>
25745 
              <bitOffset>29</bitOffset>
25746 
              <bitWidth>1</bitWidth>
25747 
              <access>write-only</access>
25748 
            </field>
25749 
            <field>
25750 
              <name>SD0PID_SEVNFRM</name>
25751 
              <description>SD0PID/SEVNFRM</description>
25752 
              <bitOffset>28</bitOffset>
25753 
              <bitWidth>1</bitWidth>
25754 
              <access>write-only</access>
25755 
            </field>
25756 
            <field>
25757 
              <name>SNAK</name>
25758 
              <description>SNAK</description>
25759 
              <bitOffset>27</bitOffset>
25760 
              <bitWidth>1</bitWidth>
25761 
              <access>write-only</access>
25762 
            </field>
25763 
            <field>
25764 
              <name>CNAK</name>
25765 
              <description>CNAK</description>
25766 
              <bitOffset>26</bitOffset>
25767 
              <bitWidth>1</bitWidth>
25768 
              <access>write-only</access>
25769 
            </field>
25770 
            <field>
25771 
              <name>Stall</name>
25772 
              <description>Stall</description>
25773 
              <bitOffset>21</bitOffset>
25774 
              <bitWidth>1</bitWidth>
25775 
              <access>read-write</access>
25776 
            </field>
25777 
            <field>
25778 
              <name>SNPM</name>
25779 
              <description>SNPM</description>
25780 
              <bitOffset>20</bitOffset>
25781 
              <bitWidth>1</bitWidth>
25782 
              <access>read-write</access>
25783 
            </field>
25784 
            <field>
25785 
              <name>EPTYP</name>
25786 
              <description>EPTYP</description>
25787 
              <bitOffset>18</bitOffset>
25788 
              <bitWidth>2</bitWidth>
25789 
              <access>read-write</access>
25790 
            </field>
25791 
            <field>
25792 
              <name>NAKSTS</name>
25793 
              <description>NAKSTS</description>
25794 
              <bitOffset>17</bitOffset>
25795 
              <bitWidth>1</bitWidth>
25796 
              <access>read-only</access>
25797 
            </field>
25798 
            <field>
25799 
              <name>EONUM_DPID</name>
25800 
              <description>EONUM/DPID</description>
25801 
              <bitOffset>16</bitOffset>
25802 
              <bitWidth>1</bitWidth>
25803 
              <access>read-only</access>
25804 
            </field>
25805 
            <field>
25806 
              <name>USBAEP</name>
25807 
              <description>USBAEP</description>
25808 
              <bitOffset>15</bitOffset>
25809 
              <bitWidth>1</bitWidth>
25810 
              <access>read-write</access>
25811 
            </field>
25812 
            <field>
25813 
              <name>MPSIZ</name>
25814 
              <description>MPSIZ</description>
25815 
              <bitOffset>0</bitOffset>
25816 
              <bitWidth>11</bitWidth>
25817 
              <access>read-write</access>
25818 
            </field>
25819 
          </fields>
25820 
        </register>
25821 
        <register>
25822 
          <name>DOEPCTL2</name>
25823 
          <displayName>DOEPCTL2</displayName>
25824 
          <description>device endpoint-2 control
25825 
          register</description>
25826 
          <addressOffset>0x340</addressOffset>
25827 
          <size>0x20</size>
25828 
          <resetValue>0x00000000</resetValue>
25829 
          <fields>
25830 
            <field>
25831 
              <name>EPENA</name>
25832 
              <description>EPENA</description>
25833 
              <bitOffset>31</bitOffset>
25834 
              <bitWidth>1</bitWidth>
25835 
              <access>read-write</access>
25836 
            </field>
25837 
            <field>
25838 
              <name>EPDIS</name>
25839 
              <description>EPDIS</description>
25840 
              <bitOffset>30</bitOffset>
25841 
              <bitWidth>1</bitWidth>
25842 
              <access>read-write</access>
25843 
            </field>
25844 
            <field>
25845 
              <name>SODDFRM</name>
25846 
              <description>SODDFRM</description>
25847 
              <bitOffset>29</bitOffset>
25848 
              <bitWidth>1</bitWidth>
25849 
              <access>write-only</access>
25850 
            </field>
25851 
            <field>
25852 
              <name>SD0PID_SEVNFRM</name>
25853 
              <description>SD0PID/SEVNFRM</description>
25854 
              <bitOffset>28</bitOffset>
25855 
              <bitWidth>1</bitWidth>
25856 
              <access>write-only</access>
25857 
            </field>
25858 
            <field>
25859 
              <name>SNAK</name>
25860 
              <description>SNAK</description>
25861 
              <bitOffset>27</bitOffset>
25862 
              <bitWidth>1</bitWidth>
25863 
              <access>write-only</access>
25864 
            </field>
25865 
            <field>
25866 
              <name>CNAK</name>
25867 
              <description>CNAK</description>
25868 
              <bitOffset>26</bitOffset>
25869 
              <bitWidth>1</bitWidth>
25870 
              <access>write-only</access>
25871 
            </field>
25872 
            <field>
25873 
              <name>Stall</name>
25874 
              <description>Stall</description>
25875 
              <bitOffset>21</bitOffset>
25876 
              <bitWidth>1</bitWidth>
25877 
              <access>read-write</access>
25878 
            </field>
25879 
            <field>
25880 
              <name>SNPM</name>
25881 
              <description>SNPM</description>
25882 
              <bitOffset>20</bitOffset>
25883 
              <bitWidth>1</bitWidth>
25884 
              <access>read-write</access>
25885 
            </field>
25886 
            <field>
25887 
              <name>EPTYP</name>
25888 
              <description>EPTYP</description>
25889 
              <bitOffset>18</bitOffset>
25890 
              <bitWidth>2</bitWidth>
25891 
              <access>read-write</access>
25892 
            </field>
25893 
            <field>
25894 
              <name>NAKSTS</name>
25895 
              <description>NAKSTS</description>
25896 
              <bitOffset>17</bitOffset>
25897 
              <bitWidth>1</bitWidth>
25898 
              <access>read-only</access>
25899 
            </field>
25900 
            <field>
25901 
              <name>EONUM_DPID</name>
25902 
              <description>EONUM/DPID</description>
25903 
              <bitOffset>16</bitOffset>
25904 
              <bitWidth>1</bitWidth>
25905 
              <access>read-only</access>
25906 
            </field>
25907 
            <field>
25908 
              <name>USBAEP</name>
25909 
              <description>USBAEP</description>
25910 
              <bitOffset>15</bitOffset>
25911 
              <bitWidth>1</bitWidth>
25912 
              <access>read-write</access>
25913 
            </field>
25914 
            <field>
25915 
              <name>MPSIZ</name>
25916 
              <description>MPSIZ</description>
25917 
              <bitOffset>0</bitOffset>
25918 
              <bitWidth>11</bitWidth>
25919 
              <access>read-write</access>
25920 
            </field>
25921 
          </fields>
25922 
        </register>
25923 
        <register>
25924 
          <name>DOEPCTL3</name>
25925 
          <displayName>DOEPCTL3</displayName>
25926 
          <description>device endpoint-3 control
25927 
          register</description>
25928 
          <addressOffset>0x360</addressOffset>
25929 
          <size>0x20</size>
25930 
          <resetValue>0x00000000</resetValue>
25931 
          <fields>
25932 
            <field>
25933 
              <name>EPENA</name>
25934 
              <description>EPENA</description>
25935 
              <bitOffset>31</bitOffset>
25936 
              <bitWidth>1</bitWidth>
25937 
              <access>read-write</access>
25938 
            </field>
25939 
            <field>
25940 
              <name>EPDIS</name>
25941 
              <description>EPDIS</description>
25942 
              <bitOffset>30</bitOffset>
25943 
              <bitWidth>1</bitWidth>
25944 
              <access>read-write</access>
25945 
            </field>
25946 
            <field>
25947 
              <name>SODDFRM</name>
25948 
              <description>SODDFRM</description>
25949 
              <bitOffset>29</bitOffset>
25950 
              <bitWidth>1</bitWidth>
25951 
              <access>write-only</access>
25952 
            </field>
25953 
            <field>
25954 
              <name>SD0PID_SEVNFRM</name>
25955 
              <description>SD0PID/SEVNFRM</description>
25956 
              <bitOffset>28</bitOffset>
25957 
              <bitWidth>1</bitWidth>
25958 
              <access>write-only</access>
25959 
            </field>
25960 
            <field>
25961 
              <name>SNAK</name>
25962 
              <description>SNAK</description>
25963 
              <bitOffset>27</bitOffset>
25964 
              <bitWidth>1</bitWidth>
25965 
              <access>write-only</access>
25966 
            </field>
25967 
            <field>
25968 
              <name>CNAK</name>
25969 
              <description>CNAK</description>
25970 
              <bitOffset>26</bitOffset>
25971 
              <bitWidth>1</bitWidth>
25972 
              <access>write-only</access>
25973 
            </field>
25974 
            <field>
25975 
              <name>Stall</name>
25976 
              <description>Stall</description>
25977 
              <bitOffset>21</bitOffset>
25978 
              <bitWidth>1</bitWidth>
25979 
              <access>read-write</access>
25980 
            </field>
25981 
            <field>
25982 
              <name>SNPM</name>
25983 
              <description>SNPM</description>
25984 
              <bitOffset>20</bitOffset>
25985 
              <bitWidth>1</bitWidth>
25986 
              <access>read-write</access>
25987 
            </field>
25988 
            <field>
25989 
              <name>EPTYP</name>
25990 
              <description>EPTYP</description>
25991 
              <bitOffset>18</bitOffset>
25992 
              <bitWidth>2</bitWidth>
25993 
              <access>read-write</access>
25994 
            </field>
25995 
            <field>
25996 
              <name>NAKSTS</name>
25997 
              <description>NAKSTS</description>
25998 
              <bitOffset>17</bitOffset>
25999 
              <bitWidth>1</bitWidth>
26000 
              <access>read-only</access>
26001 
            </field>
26002 
            <field>
26003 
              <name>EONUM_DPID</name>
26004 
              <description>EONUM/DPID</description>
26005 
              <bitOffset>16</bitOffset>
26006 
              <bitWidth>1</bitWidth>
26007 
              <access>read-only</access>
26008 
            </field>
26009 
            <field>
26010 
              <name>USBAEP</name>
26011 
              <description>USBAEP</description>
26012 
              <bitOffset>15</bitOffset>
26013 
              <bitWidth>1</bitWidth>
26014 
              <access>read-write</access>
26015 
            </field>
26016 
            <field>
26017 
              <name>MPSIZ</name>
26018 
              <description>MPSIZ</description>
26019 
              <bitOffset>0</bitOffset>
26020 
              <bitWidth>11</bitWidth>
26021 
              <access>read-write</access>
26022 
            </field>
26023 
          </fields>
26024 
        </register>
26025 
        <register>
26026 
          <name>DIEPINT0</name>
26027 
          <displayName>DIEPINT0</displayName>
26028 
          <description>device endpoint-x interrupt
26029 
          register</description>
26030 
          <addressOffset>0x108</addressOffset>
26031 
          <size>0x20</size>
26032 
          <resetValue>0x00000080</resetValue>
26033 
          <fields>
26034 
            <field>
26035 
              <name>TXFE</name>
26036 
              <description>TXFE</description>
26037 
              <bitOffset>7</bitOffset>
26038 
              <bitWidth>1</bitWidth>
26039 
              <access>read-only</access>
26040 
            </field>
26041 
            <field>
26042 
              <name>INEPNE</name>
26043 
              <description>INEPNE</description>
26044 
              <bitOffset>6</bitOffset>
26045 
              <bitWidth>1</bitWidth>
26046 
              <access>read-write</access>
26047 
            </field>
26048 
            <field>
26049 
              <name>ITTXFE</name>
26050 
              <description>ITTXFE</description>
26051 
              <bitOffset>4</bitOffset>
26052 
              <bitWidth>1</bitWidth>
26053 
              <access>read-write</access>
26054 
            </field>
26055 
            <field>
26056 
              <name>TOC</name>
26057 
              <description>TOC</description>
26058 
              <bitOffset>3</bitOffset>
26059 
              <bitWidth>1</bitWidth>
26060 
              <access>read-write</access>
26061 
            </field>
26062 
            <field>
26063 
              <name>EPDISD</name>
26064 
              <description>EPDISD</description>
26065 
              <bitOffset>1</bitOffset>
26066 
              <bitWidth>1</bitWidth>
26067 
              <access>read-write</access>
26068 
            </field>
26069 
            <field>
26070 
              <name>XFRC</name>
26071 
              <description>XFRC</description>
26072 
              <bitOffset>0</bitOffset>
26073 
              <bitWidth>1</bitWidth>
26074 
              <access>read-write</access>
26075 
            </field>
26076 
          </fields>
26077 
        </register>
26078 
        <register>
26079 
          <name>DIEPINT1</name>
26080 
          <displayName>DIEPINT1</displayName>
26081 
          <description>device endpoint-1 interrupt
26082 
          register</description>
26083 
          <addressOffset>0x128</addressOffset>
26084 
          <size>0x20</size>
26085 
          <resetValue>0x00000080</resetValue>
26086 
          <fields>
26087 
            <field>
26088 
              <name>TXFE</name>
26089 
              <description>TXFE</description>
26090 
              <bitOffset>7</bitOffset>
26091 
              <bitWidth>1</bitWidth>
26092 
              <access>read-only</access>
26093 
            </field>
26094 
            <field>
26095 
              <name>INEPNE</name>
26096 
              <description>INEPNE</description>
26097 
              <bitOffset>6</bitOffset>
26098 
              <bitWidth>1</bitWidth>
26099 
              <access>read-write</access>
26100 
            </field>
26101 
            <field>
26102 
              <name>ITTXFE</name>
26103 
              <description>ITTXFE</description>
26104 
              <bitOffset>4</bitOffset>
26105 
              <bitWidth>1</bitWidth>
26106 
              <access>read-write</access>
26107 
            </field>
26108 
            <field>
26109 
              <name>TOC</name>
26110 
              <description>TOC</description>
26111 
              <bitOffset>3</bitOffset>
26112 
              <bitWidth>1</bitWidth>
26113 
              <access>read-write</access>
26114 
            </field>
26115 
            <field>
26116 
              <name>EPDISD</name>
26117 
              <description>EPDISD</description>
26118 
              <bitOffset>1</bitOffset>
26119 
              <bitWidth>1</bitWidth>
26120 
              <access>read-write</access>
26121 
            </field>
26122 
            <field>
26123 
              <name>XFRC</name>
26124 
              <description>XFRC</description>
26125 
              <bitOffset>0</bitOffset>
26126 
              <bitWidth>1</bitWidth>
26127 
              <access>read-write</access>
26128 
            </field>
26129 
          </fields>
26130 
        </register>
26131 
        <register>
26132 
          <name>DIEPINT2</name>
26133 
          <displayName>DIEPINT2</displayName>
26134 
          <description>device endpoint-2 interrupt
26135 
          register</description>
26136 
          <addressOffset>0x148</addressOffset>
26137 
          <size>0x20</size>
26138 
          <resetValue>0x00000080</resetValue>
26139 
          <fields>
26140 
            <field>
26141 
              <name>TXFE</name>
26142 
              <description>TXFE</description>
26143 
              <bitOffset>7</bitOffset>
26144 
              <bitWidth>1</bitWidth>
26145 
              <access>read-only</access>
26146 
            </field>
26147 
            <field>
26148 
              <name>INEPNE</name>
26149 
              <description>INEPNE</description>
26150 
              <bitOffset>6</bitOffset>
26151 
              <bitWidth>1</bitWidth>
26152 
              <access>read-write</access>
26153 
            </field>
26154 
            <field>
26155 
              <name>ITTXFE</name>
26156 
              <description>ITTXFE</description>
26157 
              <bitOffset>4</bitOffset>
26158 
              <bitWidth>1</bitWidth>
26159 
              <access>read-write</access>
26160 
            </field>
26161 
            <field>
26162 
              <name>TOC</name>
26163 
              <description>TOC</description>
26164 
              <bitOffset>3</bitOffset>
26165 
              <bitWidth>1</bitWidth>
26166 
              <access>read-write</access>
26167 
            </field>
26168 
            <field>
26169 
              <name>EPDISD</name>
26170 
              <description>EPDISD</description>
26171 
              <bitOffset>1</bitOffset>
26172 
              <bitWidth>1</bitWidth>
26173 
              <access>read-write</access>
26174 
            </field>
26175 
            <field>
26176 
              <name>XFRC</name>
26177 
              <description>XFRC</description>
26178 
              <bitOffset>0</bitOffset>
26179 
              <bitWidth>1</bitWidth>
26180 
              <access>read-write</access>
26181 
            </field>
26182 
          </fields>
26183 
        </register>
26184 
        <register>
26185 
          <name>DIEPINT3</name>
26186 
          <displayName>DIEPINT3</displayName>
26187 
          <description>device endpoint-3 interrupt
26188 
          register</description>
26189 
          <addressOffset>0x168</addressOffset>
26190 
          <size>0x20</size>
26191 
          <resetValue>0x00000080</resetValue>
26192 
          <fields>
26193 
            <field>
26194 
              <name>TXFE</name>
26195 
              <description>TXFE</description>
26196 
              <bitOffset>7</bitOffset>
26197 
              <bitWidth>1</bitWidth>
26198 
              <access>read-only</access>
26199 
            </field>
26200 
            <field>
26201 
              <name>INEPNE</name>
26202 
              <description>INEPNE</description>
26203 
              <bitOffset>6</bitOffset>
26204 
              <bitWidth>1</bitWidth>
26205 
              <access>read-write</access>
26206 
            </field>
26207 
            <field>
26208 
              <name>ITTXFE</name>
26209 
              <description>ITTXFE</description>
26210 
              <bitOffset>4</bitOffset>
26211 
              <bitWidth>1</bitWidth>
26212 
              <access>read-write</access>
26213 
            </field>
26214 
            <field>
26215 
              <name>TOC</name>
26216 
              <description>TOC</description>
26217 
              <bitOffset>3</bitOffset>
26218 
              <bitWidth>1</bitWidth>
26219 
              <access>read-write</access>
26220 
            </field>
26221 
            <field>
26222 
              <name>EPDISD</name>
26223 
              <description>EPDISD</description>
26224 
              <bitOffset>1</bitOffset>
26225 
              <bitWidth>1</bitWidth>
26226 
              <access>read-write</access>
26227 
            </field>
26228 
            <field>
26229 
              <name>XFRC</name>
26230 
              <description>XFRC</description>
26231 
              <bitOffset>0</bitOffset>
26232 
              <bitWidth>1</bitWidth>
26233 
              <access>read-write</access>
26234 
            </field>
26235 
          </fields>
26236 
        </register>
26237 
        <register>
26238 
          <name>DOEPINT0</name>
26239 
          <displayName>DOEPINT0</displayName>
26240 
          <description>device endpoint-0 interrupt
26241 
          register</description>
26242 
          <addressOffset>0x308</addressOffset>
26243 
          <size>0x20</size>
26244 
          <access>read-write</access>
26245 
          <resetValue>0x00000080</resetValue>
26246 
          <fields>
26247 
            <field>
26248 
              <name>B2BSTUP</name>
26249 
              <description>B2BSTUP</description>
26250 
              <bitOffset>6</bitOffset>
26251 
              <bitWidth>1</bitWidth>
26252 
            </field>
26253 
            <field>
26254 
              <name>OTEPDIS</name>
26255 
              <description>OTEPDIS</description>
26256 
              <bitOffset>4</bitOffset>
26257 
              <bitWidth>1</bitWidth>
26258 
            </field>
26259 
            <field>
26260 
              <name>STUP</name>
26261 
              <description>STUP</description>
26262 
              <bitOffset>3</bitOffset>
26263 
              <bitWidth>1</bitWidth>
26264 
            </field>
26265 
            <field>
26266 
              <name>EPDISD</name>
26267 
              <description>EPDISD</description>
26268 
              <bitOffset>1</bitOffset>
26269 
              <bitWidth>1</bitWidth>
26270 
            </field>
26271 
            <field>
26272 
              <name>XFRC</name>
26273 
              <description>XFRC</description>
26274 
              <bitOffset>0</bitOffset>
26275 
              <bitWidth>1</bitWidth>
26276 
            </field>
26277 
          </fields>
26278 
        </register>
26279 
        <register>
26280 
          <name>DOEPINT1</name>
26281 
          <displayName>DOEPINT1</displayName>
26282 
          <description>device endpoint-1 interrupt
26283 
          register</description>
26284 
          <addressOffset>0x328</addressOffset>
26285 
          <size>0x20</size>
26286 
          <access>read-write</access>
26287 
          <resetValue>0x00000080</resetValue>
26288 
          <fields>
26289 
            <field>
26290 
              <name>B2BSTUP</name>
26291 
              <description>B2BSTUP</description>
26292 
              <bitOffset>6</bitOffset>
26293 
              <bitWidth>1</bitWidth>
26294 
            </field>
26295 
            <field>
26296 
              <name>OTEPDIS</name>
26297 
              <description>OTEPDIS</description>
26298 
              <bitOffset>4</bitOffset>
26299 
              <bitWidth>1</bitWidth>
26300 
            </field>
26301 
            <field>
26302 
              <name>STUP</name>
26303 
              <description>STUP</description>
26304 
              <bitOffset>3</bitOffset>
26305 
              <bitWidth>1</bitWidth>
26306 
            </field>
26307 
            <field>
26308 
              <name>EPDISD</name>
26309 
              <description>EPDISD</description>
26310 
              <bitOffset>1</bitOffset>
26311 
              <bitWidth>1</bitWidth>
26312 
            </field>
26313 
            <field>
26314 
              <name>XFRC</name>
26315 
              <description>XFRC</description>
26316 
              <bitOffset>0</bitOffset>
26317 
              <bitWidth>1</bitWidth>
26318 
            </field>
26319 
          </fields>
26320 
        </register>
26321 
        <register>
26322 
          <name>DOEPINT2</name>
26323 
          <displayName>DOEPINT2</displayName>
26324 
          <description>device endpoint-2 interrupt
26325 
          register</description>
26326 
          <addressOffset>0x348</addressOffset>
26327 
          <size>0x20</size>
26328 
          <access>read-write</access>
26329 
          <resetValue>0x00000080</resetValue>
26330 
          <fields>
26331 
            <field>
26332 
              <name>B2BSTUP</name>
26333 
              <description>B2BSTUP</description>
26334 
              <bitOffset>6</bitOffset>
26335 
              <bitWidth>1</bitWidth>
26336 
            </field>
26337 
            <field>
26338 
              <name>OTEPDIS</name>
26339 
              <description>OTEPDIS</description>
26340 
              <bitOffset>4</bitOffset>
26341 
              <bitWidth>1</bitWidth>
26342 
            </field>
26343 
            <field>
26344 
              <name>STUP</name>
26345 
              <description>STUP</description>
26346 
              <bitOffset>3</bitOffset>
26347 
              <bitWidth>1</bitWidth>
26348 
            </field>
26349 
            <field>
26350 
              <name>EPDISD</name>
26351 
              <description>EPDISD</description>
26352 
              <bitOffset>1</bitOffset>
26353 
              <bitWidth>1</bitWidth>
26354 
            </field>
26355 
            <field>
26356 
              <name>XFRC</name>
26357 
              <description>XFRC</description>
26358 
              <bitOffset>0</bitOffset>
26359 
              <bitWidth>1</bitWidth>
26360 
            </field>
26361 
          </fields>
26362 
        </register>
26363 
        <register>
26364 
          <name>DOEPINT3</name>
26365 
          <displayName>DOEPINT3</displayName>
26366 
          <description>device endpoint-3 interrupt
26367 
          register</description>
26368 
          <addressOffset>0x368</addressOffset>
26369 
          <size>0x20</size>
26370 
          <access>read-write</access>
26371 
          <resetValue>0x00000080</resetValue>
26372 
          <fields>
26373 
            <field>
26374 
              <name>B2BSTUP</name>
26375 
              <description>B2BSTUP</description>
26376 
              <bitOffset>6</bitOffset>
26377 
              <bitWidth>1</bitWidth>
26378 
            </field>
26379 
            <field>
26380 
              <name>OTEPDIS</name>
26381 
              <description>OTEPDIS</description>
26382 
              <bitOffset>4</bitOffset>
26383 
              <bitWidth>1</bitWidth>
26384 
            </field>
26385 
            <field>
26386 
              <name>STUP</name>
26387 
              <description>STUP</description>
26388 
              <bitOffset>3</bitOffset>
26389 
              <bitWidth>1</bitWidth>
26390 
            </field>
26391 
            <field>
26392 
              <name>EPDISD</name>
26393 
              <description>EPDISD</description>
26394 
              <bitOffset>1</bitOffset>
26395 
              <bitWidth>1</bitWidth>
26396 
            </field>
26397 
            <field>
26398 
              <name>XFRC</name>
26399 
              <description>XFRC</description>
26400 
              <bitOffset>0</bitOffset>
26401 
              <bitWidth>1</bitWidth>
26402 
            </field>
26403 
          </fields>
26404 
        </register>
26405 
        <register>
26406 
          <name>DIEPTSIZ0</name>
26407 
          <displayName>DIEPTSIZ0</displayName>
26408 
          <description>device endpoint-0 transfer size
26409 
          register</description>
26410 
          <addressOffset>0x110</addressOffset>
26411 
          <size>0x20</size>
26412 
          <access>read-write</access>
26413 
          <resetValue>0x00000000</resetValue>
26414 
          <fields>
26415 
            <field>
26416 
              <name>PKTCNT</name>
26417 
              <description>Packet count</description>
26418 
              <bitOffset>19</bitOffset>
26419 
              <bitWidth>2</bitWidth>
26420 
            </field>
26421 
            <field>
26422 
              <name>XFRSIZ</name>
26423 
              <description>Transfer size</description>
26424 
              <bitOffset>0</bitOffset>
26425 
              <bitWidth>7</bitWidth>
26426 
            </field>
26427 
          </fields>
26428 
        </register>
26429 
        <register>
26430 
          <name>DOEPTSIZ0</name>
26431 
          <displayName>DOEPTSIZ0</displayName>
26432 
          <description>device OUT endpoint-0 transfer size
26433 
          register</description>
26434 
          <addressOffset>0x310</addressOffset>
26435 
          <size>0x20</size>
26436 
          <access>read-write</access>
26437 
          <resetValue>0x00000000</resetValue>
26438 
          <fields>
26439 
            <field>
26440 
              <name>STUPCNT</name>
26441 
              <description>SETUP packet count</description>
26442 
              <bitOffset>29</bitOffset>
26443 
              <bitWidth>2</bitWidth>
26444 
            </field>
26445 
            <field>
26446 
              <name>PKTCNT</name>
26447 
              <description>Packet count</description>
26448 
              <bitOffset>19</bitOffset>
26449 
              <bitWidth>1</bitWidth>
26450 
            </field>
26451 
            <field>
26452 
              <name>XFRSIZ</name>
26453 
              <description>Transfer size</description>
26454 
              <bitOffset>0</bitOffset>
26455 
              <bitWidth>7</bitWidth>
26456 
            </field>
26457 
          </fields>
26458 
        </register>
26459 
        <register>
26460 
          <name>DIEPTSIZ1</name>
26461 
          <displayName>DIEPTSIZ1</displayName>
26462 
          <description>device endpoint-1 transfer size
26463 
          register</description>
26464 
          <addressOffset>0x130</addressOffset>
26465 
          <size>0x20</size>
26466 
          <access>read-write</access>
26467 
          <resetValue>0x00000000</resetValue>
26468 
          <fields>
26469 
            <field>
26470 
              <name>MCNT</name>
26471 
              <description>Multi count</description>
26472 
              <bitOffset>29</bitOffset>
26473 
              <bitWidth>2</bitWidth>
26474 
            </field>
26475 
            <field>
26476 
              <name>PKTCNT</name>
26477 
              <description>Packet count</description>
26478 
              <bitOffset>19</bitOffset>
26479 
              <bitWidth>10</bitWidth>
26480 
            </field>
26481 
            <field>
26482 
              <name>XFRSIZ</name>
26483 
              <description>Transfer size</description>
26484 
              <bitOffset>0</bitOffset>
26485 
              <bitWidth>19</bitWidth>
26486 
            </field>
26487 
          </fields>
26488 
        </register>
26489 
        <register>
26490 
          <name>DIEPTSIZ2</name>
26491 
          <displayName>DIEPTSIZ2</displayName>
26492 
          <description>device endpoint-2 transfer size
26493 
          register</description>
26494 
          <addressOffset>0x150</addressOffset>
26495 
          <size>0x20</size>
26496 
          <access>read-write</access>
26497 
          <resetValue>0x00000000</resetValue>
26498 
          <fields>
26499 
            <field>
26500 
              <name>MCNT</name>
26501 
              <description>Multi count</description>
26502 
              <bitOffset>29</bitOffset>
26503 
              <bitWidth>2</bitWidth>
26504 
            </field>
26505 
            <field>
26506 
              <name>PKTCNT</name>
26507 
              <description>Packet count</description>
26508 
              <bitOffset>19</bitOffset>
26509 
              <bitWidth>10</bitWidth>
26510 
            </field>
26511 
            <field>
26512 
              <name>XFRSIZ</name>
26513 
              <description>Transfer size</description>
26514 
              <bitOffset>0</bitOffset>
26515 
              <bitWidth>19</bitWidth>
26516 
            </field>
26517 
          </fields>
26518 
        </register>
26519 
        <register>
26520 
          <name>DIEPTSIZ3</name>
26521 
          <displayName>DIEPTSIZ3</displayName>
26522 
          <description>device endpoint-3 transfer size
26523 
          register</description>
26524 
          <addressOffset>0x170</addressOffset>
26525 
          <size>0x20</size>
26526 
          <access>read-write</access>
26527 
          <resetValue>0x00000000</resetValue>
26528 
          <fields>
26529 
            <field>
26530 
              <name>MCNT</name>
26531 
              <description>Multi count</description>
26532 
              <bitOffset>29</bitOffset>
26533 
              <bitWidth>2</bitWidth>
26534 
            </field>
26535 
            <field>
26536 
              <name>PKTCNT</name>
26537 
              <description>Packet count</description>
26538 
              <bitOffset>19</bitOffset>
26539 
              <bitWidth>10</bitWidth>
26540 
            </field>
26541 
            <field>
26542 
              <name>XFRSIZ</name>
26543 
              <description>Transfer size</description>
26544 
              <bitOffset>0</bitOffset>
26545 
              <bitWidth>19</bitWidth>
26546 
            </field>
26547 
          </fields>
26548 
        </register>
26549 
        <register>
26550 
          <name>DTXFSTS0</name>
26551 
          <displayName>DTXFSTS0</displayName>
26552 
          <description>OTG_FS device IN endpoint transmit FIFO
26553 
          status register</description>
26554 
          <addressOffset>0x118</addressOffset>
26555 
          <size>0x20</size>
26556 
          <access>read-only</access>
26557 
          <resetValue>0x00000000</resetValue>
26558 
          <fields>
26559 
            <field>
26560 
              <name>INEPTFSAV</name>
26561 
              <description>IN endpoint TxFIFO space
26562 
              available</description>
26563 
              <bitOffset>0</bitOffset>
26564 
              <bitWidth>16</bitWidth>
26565 
            </field>
26566 
          </fields>
26567 
        </register>
26568 
        <register>
26569 
          <name>DTXFSTS1</name>
26570 
          <displayName>DTXFSTS1</displayName>
26571 
          <description>OTG_FS device IN endpoint transmit FIFO
26572 
          status register</description>
26573 
          <addressOffset>0x138</addressOffset>
26574 
          <size>0x20</size>
26575 
          <access>read-only</access>
26576 
          <resetValue>0x00000000</resetValue>
26577 
          <fields>
26578 
            <field>
26579 
              <name>INEPTFSAV</name>
26580 
              <description>IN endpoint TxFIFO space
26581 
              available</description>
26582 
              <bitOffset>0</bitOffset>
26583 
              <bitWidth>16</bitWidth>
26584 
            </field>
26585 
          </fields>
26586 
        </register>
26587 
        <register>
26588 
          <name>DTXFSTS2</name>
26589 
          <displayName>DTXFSTS2</displayName>
26590 
          <description>OTG_FS device IN endpoint transmit FIFO
26591 
          status register</description>
26592 
          <addressOffset>0x158</addressOffset>
26593 
          <size>0x20</size>
26594 
          <access>read-only</access>
26595 
          <resetValue>0x00000000</resetValue>
26596 
          <fields>
26597 
            <field>
26598 
              <name>INEPTFSAV</name>
26599 
              <description>IN endpoint TxFIFO space
26600 
              available</description>
26601 
              <bitOffset>0</bitOffset>
26602 
              <bitWidth>16</bitWidth>
26603 
            </field>
26604 
          </fields>
26605 
        </register>
26606 
        <register>
26607 
          <name>DTXFSTS3</name>
26608 
          <displayName>DTXFSTS3</displayName>
26609 
          <description>OTG_FS device IN endpoint transmit FIFO
26610 
          status register</description>
26611 
          <addressOffset>0x178</addressOffset>
26612 
          <size>0x20</size>
26613 
          <access>read-only</access>
26614 
          <resetValue>0x00000000</resetValue>
26615 
          <fields>
26616 
            <field>
26617 
              <name>INEPTFSAV</name>
26618 
              <description>IN endpoint TxFIFO space
26619 
              available</description>
26620 
              <bitOffset>0</bitOffset>
26621 
              <bitWidth>16</bitWidth>
26622 
            </field>
26623 
          </fields>
26624 
        </register>
26625 
        <register>
26626 
          <name>DOEPTSIZ1</name>
26627 
          <displayName>DOEPTSIZ1</displayName>
26628 
          <description>device OUT endpoint-1 transfer size
26629 
          register</description>
26630 
          <addressOffset>0x330</addressOffset>
26631 
          <size>0x20</size>
26632 
          <access>read-write</access>
26633 
          <resetValue>0x00000000</resetValue>
26634 
          <fields>
26635 
            <field>
26636 
              <name>RXDPID_STUPCNT</name>
26637 
              <description>Received data PID/SETUP packet
26638 
              count</description>
26639 
              <bitOffset>29</bitOffset>
26640 
              <bitWidth>2</bitWidth>
26641 
            </field>
26642 
            <field>
26643 
              <name>PKTCNT</name>
26644 
              <description>Packet count</description>
26645 
              <bitOffset>19</bitOffset>
26646 
              <bitWidth>10</bitWidth>
26647 
            </field>
26648 
            <field>
26649 
              <name>XFRSIZ</name>
26650 
              <description>Transfer size</description>
26651 
              <bitOffset>0</bitOffset>
26652 
              <bitWidth>19</bitWidth>
26653 
            </field>
26654 
          </fields>
26655 
        </register>
26656 
        <register>
26657 
          <name>DOEPTSIZ2</name>
26658 
          <displayName>DOEPTSIZ2</displayName>
26659 
          <description>device OUT endpoint-2 transfer size
26660 
          register</description>
26661 
          <addressOffset>0x350</addressOffset>
26662 
          <size>0x20</size>
26663 
          <access>read-write</access>
26664 
          <resetValue>0x00000000</resetValue>
26665 
          <fields>
26666 
            <field>
26667 
              <name>RXDPID_STUPCNT</name>
26668 
              <description>Received data PID/SETUP packet
26669 
              count</description>
26670 
              <bitOffset>29</bitOffset>
26671 
              <bitWidth>2</bitWidth>
26672 
            </field>
26673 
            <field>
26674 
              <name>PKTCNT</name>
26675 
              <description>Packet count</description>
26676 
              <bitOffset>19</bitOffset>
26677 
              <bitWidth>10</bitWidth>
26678 
            </field>
26679 
            <field>
26680 
              <name>XFRSIZ</name>
26681 
              <description>Transfer size</description>
26682 
              <bitOffset>0</bitOffset>
26683 
              <bitWidth>19</bitWidth>
26684 
            </field>
26685 
          </fields>
26686 
        </register>
26687 
        <register>
26688 
          <name>DOEPTSIZ3</name>
26689 
          <displayName>DOEPTSIZ3</displayName>
26690 
          <description>device OUT endpoint-3 transfer size
26691 
          register</description>
26692 
          <addressOffset>0x370</addressOffset>
26693 
          <size>0x20</size>
26694 
          <access>read-write</access>
26695 
          <resetValue>0x00000000</resetValue>
26696 
          <fields>
26697 
            <field>
26698 
              <name>RXDPID_STUPCNT</name>
26699 
              <description>Received data PID/SETUP packet
26700 
              count</description>
26701 
              <bitOffset>29</bitOffset>
26702 
              <bitWidth>2</bitWidth>
26703 
            </field>
26704 
            <field>
26705 
              <name>PKTCNT</name>
26706 
              <description>Packet count</description>
26707 
              <bitOffset>19</bitOffset>
26708 
              <bitWidth>10</bitWidth>
26709 
            </field>
26710 
            <field>
26711 
              <name>XFRSIZ</name>
26712 
              <description>Transfer size</description>
26713 
              <bitOffset>0</bitOffset>
26714 
              <bitWidth>19</bitWidth>
26715 
            </field>
26716 
          </fields>
26717 
        </register>
26718 
      </registers>
26719 
    </peripheral>
26720 
    <peripheral>
26721 
      <name>OTG_FS_GLOBAL</name>
26722 
      <description>USB on the go full speed</description>
26723 
      <groupName>USB_OTG_FS</groupName>
26724 
      <baseAddress>0x50000000</baseAddress>
26725 
      <addressBlock>
26726 
        <offset>0x0</offset>
26727 
        <size>0x400</size>
26728 
        <usage>registers</usage>
26729 
      </addressBlock>
26730 
      <registers>
26731 
        <register>
26732 
          <name>FS_GOTGCTL</name>
26733 
          <displayName>FS_GOTGCTL</displayName>
26734 
          <description>OTG_FS control and status register
26735 
          (OTG_FS_GOTGCTL)</description>
26736 
          <addressOffset>0x0</addressOffset>
26737 
          <size>0x20</size>
26738 
          <resetValue>0x00000800</resetValue>
26739 
          <fields>
26740 
            <field>
26741 
              <name>SRQSCS</name>
26742 
              <description>Session request success</description>
26743 
              <bitOffset>0</bitOffset>
26744 
              <bitWidth>1</bitWidth>
26745 
              <access>read-only</access>
26746 
            </field>
26747 
            <field>
26748 
              <name>SRQ</name>
26749 
              <description>Session request</description>
26750 
              <bitOffset>1</bitOffset>
26751 
              <bitWidth>1</bitWidth>
26752 
              <access>read-write</access>
26753 
            </field>
26754 
            <field>
26755 
              <name>HNGSCS</name>
26756 
              <description>Host negotiation success</description>
26757 
              <bitOffset>8</bitOffset>
26758 
              <bitWidth>1</bitWidth>
26759 
              <access>read-only</access>
26760 
            </field>
26761 
            <field>
26762 
              <name>HNPRQ</name>
26763 
              <description>HNP request</description>
26764 
              <bitOffset>9</bitOffset>
26765 
              <bitWidth>1</bitWidth>
26766 
              <access>read-write</access>
26767 
            </field>
26768 
            <field>
26769 
              <name>HSHNPEN</name>
26770 
              <description>Host set HNP enable</description>
26771 
              <bitOffset>10</bitOffset>
26772 
              <bitWidth>1</bitWidth>
26773 
              <access>read-write</access>
26774 
            </field>
26775 
            <field>
26776 
              <name>DHNPEN</name>
26777 
              <description>Device HNP enabled</description>
26778 
              <bitOffset>11</bitOffset>
26779 
              <bitWidth>1</bitWidth>
26780 
              <access>read-write</access>
26781 
            </field>
26782 
            <field>
26783 
              <name>CIDSTS</name>
26784 
              <description>Connector ID status</description>
26785 
              <bitOffset>16</bitOffset>
26786 
              <bitWidth>1</bitWidth>
26787 
              <access>read-only</access>
26788 
            </field>
26789 
            <field>
26790 
              <name>DBCT</name>
26791 
              <description>Long/short debounce time</description>
26792 
              <bitOffset>17</bitOffset>
26793 
              <bitWidth>1</bitWidth>
26794 
              <access>read-only</access>
26795 
            </field>
26796 
            <field>
26797 
              <name>ASVLD</name>
26798 
              <description>A-session valid</description>
26799 
              <bitOffset>18</bitOffset>
26800 
              <bitWidth>1</bitWidth>
26801 
              <access>read-only</access>
26802 
            </field>
26803 
            <field>
26804 
              <name>BSVLD</name>
26805 
              <description>B-session valid</description>
26806 
              <bitOffset>19</bitOffset>
26807 
              <bitWidth>1</bitWidth>
26808 
              <access>read-only</access>
26809 
            </field>
26810 
          </fields>
26811 
        </register>
26812 
        <register>
26813 
          <name>FS_GOTGINT</name>
26814 
          <displayName>FS_GOTGINT</displayName>
26815 
          <description>OTG_FS interrupt register
26816 
          (OTG_FS_GOTGINT)</description>
26817 
          <addressOffset>0x4</addressOffset>
26818 
          <size>0x20</size>
26819 
          <access>read-write</access>
26820 
          <resetValue>0x00000000</resetValue>
26821 
          <fields>
26822 
            <field>
26823 
              <name>SEDET</name>
26824 
              <description>Session end detected</description>
26825 
              <bitOffset>2</bitOffset>
26826 
              <bitWidth>1</bitWidth>
26827 
            </field>
26828 
            <field>
26829 
              <name>SRSSCHG</name>
26830 
              <description>Session request success status
26831 
              change</description>
26832 
              <bitOffset>8</bitOffset>
26833 
              <bitWidth>1</bitWidth>
26834 
            </field>
26835 
            <field>
26836 
              <name>HNSSCHG</name>
26837 
              <description>Host negotiation success status
26838 
              change</description>
26839 
              <bitOffset>9</bitOffset>
26840 
              <bitWidth>1</bitWidth>
26841 
            </field>
26842 
            <field>
26843 
              <name>HNGDET</name>
26844 
              <description>Host negotiation detected</description>
26845 
              <bitOffset>17</bitOffset>
26846 
              <bitWidth>1</bitWidth>
26847 
            </field>
26848 
            <field>
26849 
              <name>ADTOCHG</name>
26850 
              <description>A-device timeout change</description>
26851 
              <bitOffset>18</bitOffset>
26852 
              <bitWidth>1</bitWidth>
26853 
            </field>
26854 
            <field>
26855 
              <name>DBCDNE</name>
26856 
              <description>Debounce done</description>
26857 
              <bitOffset>19</bitOffset>
26858 
              <bitWidth>1</bitWidth>
26859 
            </field>
26860 
          </fields>
26861 
        </register>
26862 
        <register>
26863 
          <name>FS_GAHBCFG</name>
26864 
          <displayName>FS_GAHBCFG</displayName>
26865 
          <description>OTG_FS AHB configuration register
26866 
          (OTG_FS_GAHBCFG)</description>
26867 
          <addressOffset>0x8</addressOffset>
26868 
          <size>0x20</size>
26869 
          <access>read-write</access>
26870 
          <resetValue>0x00000000</resetValue>
26871 
          <fields>
26872 
            <field>
26873 
              <name>GINT</name>
26874 
              <description>Global interrupt mask</description>
26875 
              <bitOffset>0</bitOffset>
26876 
              <bitWidth>1</bitWidth>
26877 
            </field>
26878 
            <field>
26879 
              <name>TXFELVL</name>
26880 
              <description>TxFIFO empty level</description>
26881 
              <bitOffset>7</bitOffset>
26882 
              <bitWidth>1</bitWidth>
26883 
            </field>
26884 
            <field>
26885 
              <name>PTXFELVL</name>
26886 
              <description>Periodic TxFIFO empty
26887 
              level</description>
26888 
              <bitOffset>8</bitOffset>
26889 
              <bitWidth>1</bitWidth>
26890 
            </field>
26891 
          </fields>
26892 
        </register>
26893 
        <register>
26894 
          <name>FS_GUSBCFG</name>
26895 
          <displayName>FS_GUSBCFG</displayName>
26896 
          <description>OTG_FS USB configuration register
26897 
          (OTG_FS_GUSBCFG)</description>
26898 
          <addressOffset>0xC</addressOffset>
26899 
          <size>0x20</size>
26900 
          <resetValue>0x00000A00</resetValue>
26901 
          <fields>
26902 
            <field>
26903 
              <name>TOCAL</name>
26904 
              <description>FS timeout calibration</description>
26905 
              <bitOffset>0</bitOffset>
26906 
              <bitWidth>3</bitWidth>
26907 
              <access>read-write</access>
26908 
            </field>
26909 
            <field>
26910 
              <name>PHYSEL</name>
26911 
              <description>Full Speed serial transceiver
26912 
              select</description>
26913 
              <bitOffset>6</bitOffset>
26914 
              <bitWidth>1</bitWidth>
26915 
              <access>write-only</access>
26916 
            </field>
26917 
            <field>
26918 
              <name>SRPCAP</name>
26919 
              <description>SRP-capable</description>
26920 
              <bitOffset>8</bitOffset>
26921 
              <bitWidth>1</bitWidth>
26922 
              <access>read-write</access>
26923 
            </field>
26924 
            <field>
26925 
              <name>HNPCAP</name>
26926 
              <description>HNP-capable</description>
26927 
              <bitOffset>9</bitOffset>
26928 
              <bitWidth>1</bitWidth>
26929 
              <access>read-write</access>
26930 
            </field>
26931 
            <field>
26932 
              <name>TRDT</name>
26933 
              <description>USB turnaround time</description>
26934 
              <bitOffset>10</bitOffset>
26935 
              <bitWidth>4</bitWidth>
26936 
              <access>read-write</access>
26937 
            </field>
26938 
            <field>
26939 
              <name>FHMOD</name>
26940 
              <description>Force host mode</description>
26941 
              <bitOffset>29</bitOffset>
26942 
              <bitWidth>1</bitWidth>
26943 
              <access>read-write</access>
26944 
            </field>
26945 
            <field>
26946 
              <name>FDMOD</name>
26947 
              <description>Force device mode</description>
26948 
              <bitOffset>30</bitOffset>
26949 
              <bitWidth>1</bitWidth>
26950 
              <access>read-write</access>
26951 
            </field>
26952 
            <field>
26953 
              <name>CTXPKT</name>
26954 
              <description>Corrupt Tx packet</description>
26955 
              <bitOffset>31</bitOffset>
26956 
              <bitWidth>1</bitWidth>
26957 
              <access>read-write</access>
26958 
            </field>
26959 
          </fields>
26960 
        </register>
26961 
        <register>
26962 
          <name>FS_GRSTCTL</name>
26963 
          <displayName>FS_GRSTCTL</displayName>
26964 
          <description>OTG_FS reset register
26965 
          (OTG_FS_GRSTCTL)</description>
26966 
          <addressOffset>0x10</addressOffset>
26967 
          <size>0x20</size>
26968 
          <resetValue>0x20000000</resetValue>
26969 
          <fields>
26970 
            <field>
26971 
              <name>CSRST</name>
26972 
              <description>Core soft reset</description>
26973 
              <bitOffset>0</bitOffset>
26974 
              <bitWidth>1</bitWidth>
26975 
              <access>read-write</access>
26976 
            </field>
26977 
            <field>
26978 
              <name>HSRST</name>
26979 
              <description>HCLK soft reset</description>
26980 
              <bitOffset>1</bitOffset>
26981 
              <bitWidth>1</bitWidth>
26982 
              <access>read-write</access>
26983 
            </field>
26984 
            <field>
26985 
              <name>FCRST</name>
26986 
              <description>Host frame counter reset</description>
26987 
              <bitOffset>2</bitOffset>
26988 
              <bitWidth>1</bitWidth>
26989 
              <access>read-write</access>
26990 
            </field>
26991 
            <field>
26992 
              <name>RXFFLSH</name>
26993 
              <description>RxFIFO flush</description>
26994 
              <bitOffset>4</bitOffset>
26995 
              <bitWidth>1</bitWidth>
26996 
              <access>read-write</access>
26997 
            </field>
26998 
            <field>
26999 
              <name>TXFFLSH</name>
27000 
              <description>TxFIFO flush</description>
27001 
              <bitOffset>5</bitOffset>
27002 
              <bitWidth>1</bitWidth>
27003 
              <access>read-write</access>
27004 
            </field>
27005 
            <field>
27006 
              <name>TXFNUM</name>
27007 
              <description>TxFIFO number</description>
27008 
              <bitOffset>6</bitOffset>
27009 
              <bitWidth>5</bitWidth>
27010 
              <access>read-write</access>
27011 
            </field>
27012 
            <field>
27013 
              <name>AHBIDL</name>
27014 
              <description>AHB master idle</description>
27015 
              <bitOffset>31</bitOffset>
27016 
              <bitWidth>1</bitWidth>
27017 
              <access>read-only</access>
27018 
            </field>
27019 
          </fields>
27020 
        </register>
27021 
        <register>
27022 
          <name>FS_GINTSTS</name>
27023 
          <displayName>FS_GINTSTS</displayName>
27024 
          <description>OTG_FS core interrupt register
27025 
          (OTG_FS_GINTSTS)</description>
27026 
          <addressOffset>0x14</addressOffset>
27027 
          <size>0x20</size>
27028 
          <resetValue>0x04000020</resetValue>
27029 
          <fields>
27030 
            <field>
27031 
              <name>CMOD</name>
27032 
              <description>Current mode of operation</description>
27033 
              <bitOffset>0</bitOffset>
27034 
              <bitWidth>1</bitWidth>
27035 
              <access>read-only</access>
27036 
            </field>
27037 
            <field>
27038 
              <name>MMIS</name>
27039 
              <description>Mode mismatch interrupt</description>
27040 
              <bitOffset>1</bitOffset>
27041 
              <bitWidth>1</bitWidth>
27042 
              <access>read-write</access>
27043 
            </field>
27044 
            <field>
27045 
              <name>OTGINT</name>
27046 
              <description>OTG interrupt</description>
27047 
              <bitOffset>2</bitOffset>
27048 
              <bitWidth>1</bitWidth>
27049 
              <access>read-only</access>
27050 
            </field>
27051 
            <field>
27052 
              <name>SOF</name>
27053 
              <description>Start of frame</description>
27054 
              <bitOffset>3</bitOffset>
27055 
              <bitWidth>1</bitWidth>
27056 
              <access>read-write</access>
27057 
            </field>
27058 
            <field>
27059 
              <name>RXFLVL</name>
27060 
              <description>RxFIFO non-empty</description>
27061 
              <bitOffset>4</bitOffset>
27062 
              <bitWidth>1</bitWidth>
27063 
              <access>read-only</access>
27064 
            </field>
27065 
            <field>
27066 
              <name>NPTXFE</name>
27067 
              <description>Non-periodic TxFIFO empty</description>
27068 
              <bitOffset>5</bitOffset>
27069 
              <bitWidth>1</bitWidth>
27070 
              <access>read-only</access>
27071 
            </field>
27072 
            <field>
27073 
              <name>GINAKEFF</name>
27074 
              <description>Global IN non-periodic NAK
27075 
              effective</description>
27076 
              <bitOffset>6</bitOffset>
27077 
              <bitWidth>1</bitWidth>
27078 
              <access>read-only</access>
27079 
            </field>
27080 
            <field>
27081 
              <name>GOUTNAKEFF</name>
27082 
              <description>Global OUT NAK effective</description>
27083 
              <bitOffset>7</bitOffset>
27084 
              <bitWidth>1</bitWidth>
27085 
              <access>read-only</access>
27086 
            </field>
27087 
            <field>
27088 
              <name>ESUSP</name>
27089 
              <description>Early suspend</description>
27090 
              <bitOffset>10</bitOffset>
27091 
              <bitWidth>1</bitWidth>
27092 
              <access>read-write</access>
27093 
            </field>
27094 
            <field>
27095 
              <name>USBSUSP</name>
27096 
              <description>USB suspend</description>
27097 
              <bitOffset>11</bitOffset>
27098 
              <bitWidth>1</bitWidth>
27099 
              <access>read-write</access>
27100 
            </field>
27101 
            <field>
27102 
              <name>USBRST</name>
27103 
              <description>USB reset</description>
27104 
              <bitOffset>12</bitOffset>
27105 
              <bitWidth>1</bitWidth>
27106 
              <access>read-write</access>
27107 
            </field>
27108 
            <field>
27109 
              <name>ENUMDNE</name>
27110 
              <description>Enumeration done</description>
27111 
              <bitOffset>13</bitOffset>
27112 
              <bitWidth>1</bitWidth>
27113 
              <access>read-write</access>
27114 
            </field>
27115 
            <field>
27116 
              <name>ISOODRP</name>
27117 
              <description>Isochronous OUT packet dropped
27118 
              interrupt</description>
27119 
              <bitOffset>14</bitOffset>
27120 
              <bitWidth>1</bitWidth>
27121 
              <access>read-write</access>
27122 
            </field>
27123 
            <field>
27124 
              <name>EOPF</name>
27125 
              <description>End of periodic frame
27126 
              interrupt</description>
27127 
              <bitOffset>15</bitOffset>
27128 
              <bitWidth>1</bitWidth>
27129 
              <access>read-write</access>
27130 
            </field>
27131 
            <field>
27132 
              <name>IEPINT</name>
27133 
              <description>IN endpoint interrupt</description>
27134 
              <bitOffset>18</bitOffset>
27135 
              <bitWidth>1</bitWidth>
27136 
              <access>read-only</access>
27137 
            </field>
27138 
            <field>
27139 
              <name>OEPINT</name>
27140 
              <description>OUT endpoint interrupt</description>
27141 
              <bitOffset>19</bitOffset>
27142 
              <bitWidth>1</bitWidth>
27143 
              <access>read-only</access>
27144 
            </field>
27145 
            <field>
27146 
              <name>IISOIXFR</name>
27147 
              <description>Incomplete isochronous IN
27148 
              transfer</description>
27149 
              <bitOffset>20</bitOffset>
27150 
              <bitWidth>1</bitWidth>
27151 
              <access>read-write</access>
27152 
            </field>
27153 
            <field>
27154 
              <name>IPXFR_INCOMPISOOUT</name>
27155 
              <description>Incomplete periodic transfer(Host
27156 
              mode)/Incomplete isochronous OUT transfer(Device
27157 
              mode)</description>
27158 
              <bitOffset>21</bitOffset>
27159 
              <bitWidth>1</bitWidth>
27160 
              <access>read-write</access>
27161 
            </field>
27162 
            <field>
27163 
              <name>HPRTINT</name>
27164 
              <description>Host port interrupt</description>
27165 
              <bitOffset>24</bitOffset>
27166 
              <bitWidth>1</bitWidth>
27167 
              <access>read-only</access>
27168 
            </field>
27169 
            <field>
27170 
              <name>HCINT</name>
27171 
              <description>Host channels interrupt</description>
27172 
              <bitOffset>25</bitOffset>
27173 
              <bitWidth>1</bitWidth>
27174 
              <access>read-only</access>
27175 
            </field>
27176 
            <field>
27177 
              <name>PTXFE</name>
27178 
              <description>Periodic TxFIFO empty</description>
27179 
              <bitOffset>26</bitOffset>
27180 
              <bitWidth>1</bitWidth>
27181 
              <access>read-only</access>
27182 
            </field>
27183 
            <field>
27184 
              <name>CIDSCHG</name>
27185 
              <description>Connector ID status change</description>
27186 
              <bitOffset>28</bitOffset>
27187 
              <bitWidth>1</bitWidth>
27188 
              <access>read-write</access>
27189 
            </field>
27190 
            <field>
27191 
              <name>DISCINT</name>
27192 
              <description>Disconnect detected
27193 
              interrupt</description>
27194 
              <bitOffset>29</bitOffset>
27195 
              <bitWidth>1</bitWidth>
27196 
              <access>read-write</access>
27197 
            </field>
27198 
            <field>
27199 
              <name>SRQINT</name>
27200 
              <description>Session request/new session detected
27201 
              interrupt</description>
27202 
              <bitOffset>30</bitOffset>
27203 
              <bitWidth>1</bitWidth>
27204 
              <access>read-write</access>
27205 
            </field>
27206 
            <field>
27207 
              <name>WKUPINT</name>
27208 
              <description>Resume/remote wakeup detected
27209 
              interrupt</description>
27210 
              <bitOffset>31</bitOffset>
27211 
              <bitWidth>1</bitWidth>
27212 
              <access>read-write</access>
27213 
            </field>
27214 
          </fields>
27215 
        </register>
27216 
        <register>
27217 
          <name>FS_GINTMSK</name>
27218 
          <displayName>FS_GINTMSK</displayName>
27219 
          <description>OTG_FS interrupt mask register
27220 
          (OTG_FS_GINTMSK)</description>
27221 
          <addressOffset>0x18</addressOffset>
27222 
          <size>0x20</size>
27223 
          <resetValue>0x00000000</resetValue>
27224 
          <fields>
27225 
            <field>
27226 
              <name>MMISM</name>
27227 
              <description>Mode mismatch interrupt
27228 
              mask</description>
27229 
              <bitOffset>1</bitOffset>
27230 
              <bitWidth>1</bitWidth>
27231 
              <access>read-write</access>
27232 
            </field>
27233 
            <field>
27234 
              <name>OTGINT</name>
27235 
              <description>OTG interrupt mask</description>
27236 
              <bitOffset>2</bitOffset>
27237 
              <bitWidth>1</bitWidth>
27238 
              <access>read-write</access>
27239 
            </field>
27240 
            <field>
27241 
              <name>SOFM</name>
27242 
              <description>Start of frame mask</description>
27243 
              <bitOffset>3</bitOffset>
27244 
              <bitWidth>1</bitWidth>
27245 
              <access>read-write</access>
27246 
            </field>
27247 
            <field>
27248 
              <name>RXFLVLM</name>
27249 
              <description>Receive FIFO non-empty
27250 
              mask</description>
27251 
              <bitOffset>4</bitOffset>
27252 
              <bitWidth>1</bitWidth>
27253 
              <access>read-write</access>
27254 
            </field>
27255 
            <field>
27256 
              <name>NPTXFEM</name>
27257 
              <description>Non-periodic TxFIFO empty
27258 
              mask</description>
27259 
              <bitOffset>5</bitOffset>
27260 
              <bitWidth>1</bitWidth>
27261 
              <access>read-write</access>
27262 
            </field>
27263 
            <field>
27264 
              <name>GINAKEFFM</name>
27265 
              <description>Global non-periodic IN NAK effective
27266 
              mask</description>
27267 
              <bitOffset>6</bitOffset>
27268 
              <bitWidth>1</bitWidth>
27269 
              <access>read-write</access>
27270 
            </field>
27271 
            <field>
27272 
              <name>GONAKEFFM</name>
27273 
              <description>Global OUT NAK effective
27274 
              mask</description>
27275 
              <bitOffset>7</bitOffset>
27276 
              <bitWidth>1</bitWidth>
27277 
              <access>read-write</access>
27278 
            </field>
27279 
            <field>
27280 
              <name>ESUSPM</name>
27281 
              <description>Early suspend mask</description>
27282 
              <bitOffset>10</bitOffset>
27283 
              <bitWidth>1</bitWidth>
27284 
              <access>read-write</access>
27285 
            </field>
27286 
            <field>
27287 
              <name>USBSUSPM</name>
27288 
              <description>USB suspend mask</description>
27289 
              <bitOffset>11</bitOffset>
27290 
              <bitWidth>1</bitWidth>
27291 
              <access>read-write</access>
27292 
            </field>
27293 
            <field>
27294 
              <name>USBRST</name>
27295 
              <description>USB reset mask</description>
27296 
              <bitOffset>12</bitOffset>
27297 
              <bitWidth>1</bitWidth>
27298 
              <access>read-write</access>
27299 
            </field>
27300 
            <field>
27301 
              <name>ENUMDNEM</name>
27302 
              <description>Enumeration done mask</description>
27303 
              <bitOffset>13</bitOffset>
27304 
              <bitWidth>1</bitWidth>
27305 
              <access>read-write</access>
27306 
            </field>
27307 
            <field>
27308 
              <name>ISOODRPM</name>
27309 
              <description>Isochronous OUT packet dropped interrupt
27310 
              mask</description>
27311 
              <bitOffset>14</bitOffset>
27312 
              <bitWidth>1</bitWidth>
27313 
              <access>read-write</access>
27314 
            </field>
27315 
            <field>
27316 
              <name>EOPFM</name>
27317 
              <description>End of periodic frame interrupt
27318 
              mask</description>
27319 
              <bitOffset>15</bitOffset>
27320 
              <bitWidth>1</bitWidth>
27321 
              <access>read-write</access>
27322 
            </field>
27323 
            <field>
27324 
              <name>EPMISM</name>
27325 
              <description>Endpoint mismatch interrupt
27326 
              mask</description>
27327 
              <bitOffset>17</bitOffset>
27328 
              <bitWidth>1</bitWidth>
27329 
              <access>read-write</access>
27330 
            </field>
27331 
            <field>
27332 
              <name>IEPINT</name>
27333 
              <description>IN endpoints interrupt
27334 
              mask</description>
27335 
              <bitOffset>18</bitOffset>
27336 
              <bitWidth>1</bitWidth>
27337 
              <access>read-write</access>
27338 
            </field>
27339 
            <field>
27340 
              <name>OEPINT</name>
27341 
              <description>OUT endpoints interrupt
27342 
              mask</description>
27343 
              <bitOffset>19</bitOffset>
27344 
              <bitWidth>1</bitWidth>
27345 
              <access>read-write</access>
27346 
            </field>
27347 
            <field>
27348 
              <name>IISOIXFRM</name>
27349 
              <description>Incomplete isochronous IN transfer
27350 
              mask</description>
27351 
              <bitOffset>20</bitOffset>
27352 
              <bitWidth>1</bitWidth>
27353 
              <access>read-write</access>
27354 
            </field>
27355 
            <field>
27356 
              <name>IPXFRM_IISOOXFRM</name>
27357 
              <description>Incomplete periodic transfer mask(Host
27358 
              mode)/Incomplete isochronous OUT transfer mask(Device
27359 
              mode)</description>
27360 
              <bitOffset>21</bitOffset>
27361 
              <bitWidth>1</bitWidth>
27362 
              <access>read-write</access>
27363 
            </field>
27364 
            <field>
27365 
              <name>PRTIM</name>
27366 
              <description>Host port interrupt mask</description>
27367 
              <bitOffset>24</bitOffset>
27368 
              <bitWidth>1</bitWidth>
27369 
              <access>read-only</access>
27370 
            </field>
27371 
            <field>
27372 
              <name>HCIM</name>
27373 
              <description>Host channels interrupt
27374 
              mask</description>
27375 
              <bitOffset>25</bitOffset>
27376 
              <bitWidth>1</bitWidth>
27377 
              <access>read-write</access>
27378 
            </field>
27379 
            <field>
27380 
              <name>PTXFEM</name>
27381 
              <description>Periodic TxFIFO empty mask</description>
27382 
              <bitOffset>26</bitOffset>
27383 
              <bitWidth>1</bitWidth>
27384 
              <access>read-write</access>
27385 
            </field>
27386 
            <field>
27387 
              <name>CIDSCHGM</name>
27388 
              <description>Connector ID status change
27389 
              mask</description>
27390 
              <bitOffset>28</bitOffset>
27391 
              <bitWidth>1</bitWidth>
27392 
              <access>read-write</access>
27393 
            </field>
27394 
            <field>
27395 
              <name>DISCINT</name>
27396 
              <description>Disconnect detected interrupt
27397 
              mask</description>
27398 
              <bitOffset>29</bitOffset>
27399 
              <bitWidth>1</bitWidth>
27400 
              <access>read-write</access>
27401 
            </field>
27402 
            <field>
27403 
              <name>SRQIM</name>
27404 
              <description>Session request/new session detected
27405 
              interrupt mask</description>
27406 
              <bitOffset>30</bitOffset>
27407 
              <bitWidth>1</bitWidth>
27408 
              <access>read-write</access>
27409 
            </field>
27410 
            <field>
27411 
              <name>WUIM</name>
27412 
              <description>Resume/remote wakeup detected interrupt
27413 
              mask</description>
27414 
              <bitOffset>31</bitOffset>
27415 
              <bitWidth>1</bitWidth>
27416 
              <access>read-write</access>
27417 
            </field>
27418 
          </fields>
27419 
        </register>
27420 
        <register>
27421 
          <name>FS_GRXSTSR_Device</name>
27422 
          <displayName>FS_GRXSTSR_Device</displayName>
27423 
          <description>OTG_FS Receive status debug read(Device
27424 
          mode)</description>
27425 
          <addressOffset>0x1C</addressOffset>
27426 
          <size>0x20</size>
27427 
          <access>read-only</access>
27428 
          <resetValue>0x00000000</resetValue>
27429 
          <fields>
27430 
            <field>
27431 
              <name>EPNUM</name>
27432 
              <description>Endpoint number</description>
27433 
              <bitOffset>0</bitOffset>
27434 
              <bitWidth>4</bitWidth>
27435 
            </field>
27436 
            <field>
27437 
              <name>BCNT</name>
27438 
              <description>Byte count</description>
27439 
              <bitOffset>4</bitOffset>
27440 
              <bitWidth>11</bitWidth>
27441 
            </field>
27442 
            <field>
27443 
              <name>DPID</name>
27444 
              <description>Data PID</description>
27445 
              <bitOffset>15</bitOffset>
27446 
              <bitWidth>2</bitWidth>
27447 
            </field>
27448 
            <field>
27449 
              <name>PKTSTS</name>
27450 
              <description>Packet status</description>
27451 
              <bitOffset>17</bitOffset>
27452 
              <bitWidth>4</bitWidth>
27453 
            </field>
27454 
            <field>
27455 
              <name>FRMNUM</name>
27456 
              <description>Frame number</description>
27457 
              <bitOffset>21</bitOffset>
27458 
              <bitWidth>4</bitWidth>
27459 
            </field>
27460 
          </fields>
27461 
        </register>
27462 
        <register>
27463 
          <name>FS_GRXSTSR_Host</name>
27464 
          <displayName>FS_GRXSTSR_Host</displayName>
27465 
          <description>OTG_FS Receive status debug read(Host
27466 
          mode)</description>
27467 
          <alternateRegister>FS_GRXSTSR_Device</alternateRegister>
27468 
          <addressOffset>0x1C</addressOffset>
27469 
          <size>0x20</size>
27470 
          <access>read-only</access>
27471 
          <resetValue>0x00000000</resetValue>
27472 
          <fields>
27473 
            <field>
27474 
              <name>EPNUM</name>
27475 
              <description>Endpoint number</description>
27476 
              <bitOffset>0</bitOffset>
27477 
              <bitWidth>4</bitWidth>
27478 
            </field>
27479 
            <field>
27480 
              <name>BCNT</name>
27481 
              <description>Byte count</description>
27482 
              <bitOffset>4</bitOffset>
27483 
              <bitWidth>11</bitWidth>
27484 
            </field>
27485 
            <field>
27486 
              <name>DPID</name>
27487 
              <description>Data PID</description>
27488 
              <bitOffset>15</bitOffset>
27489 
              <bitWidth>2</bitWidth>
27490 
            </field>
27491 
            <field>
27492 
              <name>PKTSTS</name>
27493 
              <description>Packet status</description>
27494 
              <bitOffset>17</bitOffset>
27495 
              <bitWidth>4</bitWidth>
27496 
            </field>
27497 
            <field>
27498 
              <name>FRMNUM</name>
27499 
              <description>Frame number</description>
27500 
              <bitOffset>21</bitOffset>
27501 
              <bitWidth>4</bitWidth>
27502 
            </field>
27503 
          </fields>
27504 
        </register>
27505 
        <register>
27506 
          <name>FS_GRXFSIZ</name>
27507 
          <displayName>FS_GRXFSIZ</displayName>
27508 
          <description>OTG_FS Receive FIFO size register
27509 
          (OTG_FS_GRXFSIZ)</description>
27510 
          <addressOffset>0x24</addressOffset>
27511 
          <size>0x20</size>
27512 
          <access>read-write</access>
27513 
          <resetValue>0x00000200</resetValue>
27514 
          <fields>
27515 
            <field>
27516 
              <name>RXFD</name>
27517 
              <description>RxFIFO depth</description>
27518 
              <bitOffset>0</bitOffset>
27519 
              <bitWidth>16</bitWidth>
27520 
            </field>
27521 
          </fields>
27522 
        </register>
27523 
        <register>
27524 
          <name>FS_GNPTXFSIZ_Device</name>
27525 
          <displayName>FS_GNPTXFSIZ_Device</displayName>
27526 
          <description>OTG_FS non-periodic transmit FIFO size
27527 
          register (Device mode)</description>
27528 
          <addressOffset>0x28</addressOffset>
27529 
          <size>0x20</size>
27530 
          <access>read-write</access>
27531 
          <resetValue>0x00000200</resetValue>
27532 
          <fields>
27533 
            <field>
27534 
              <name>TX0FSA</name>
27535 
              <description>Endpoint 0 transmit RAM start
27536 
              address</description>
27537 
              <bitOffset>0</bitOffset>
27538 
              <bitWidth>16</bitWidth>
27539 
            </field>
27540 
            <field>
27541 
              <name>TX0FD</name>
27542 
              <description>Endpoint 0 TxFIFO depth</description>
27543 
              <bitOffset>16</bitOffset>
27544 
              <bitWidth>16</bitWidth>
27545 
            </field>
27546 
          </fields>
27547 
        </register>
27548 
        <register>
27549 
          <name>FS_GNPTXFSIZ_Host</name>
27550 
          <displayName>FS_GNPTXFSIZ_Host</displayName>
27551 
          <description>OTG_FS non-periodic transmit FIFO size
27552 
          register (Host mode)</description>
27553 
          <alternateRegister>
27554 
          FS_GNPTXFSIZ_Device</alternateRegister>
27555 
          <addressOffset>0x28</addressOffset>
27556 
          <size>0x20</size>
27557 
          <access>read-write</access>
27558 
          <resetValue>0x00000200</resetValue>
27559 
          <fields>
27560 
            <field>
27561 
              <name>NPTXFSA</name>
27562 
              <description>Non-periodic transmit RAM start
27563 
              address</description>
27564 
              <bitOffset>0</bitOffset>
27565 
              <bitWidth>16</bitWidth>
27566 
            </field>
27567 
            <field>
27568 
              <name>NPTXFD</name>
27569 
              <description>Non-periodic TxFIFO depth</description>
27570 
              <bitOffset>16</bitOffset>
27571 
              <bitWidth>16</bitWidth>
27572 
            </field>
27573 
          </fields>
27574 
        </register>
27575 
        <register>
27576 
          <name>FS_GNPTXSTS</name>
27577 
          <displayName>FS_GNPTXSTS</displayName>
27578 
          <description>OTG_FS non-periodic transmit FIFO/queue
27579 
          status register (OTG_FS_GNPTXSTS)</description>
27580 
          <addressOffset>0x2C</addressOffset>
27581 
          <size>0x20</size>
27582 
          <access>read-only</access>
27583 
          <resetValue>0x00080200</resetValue>
27584 
          <fields>
27585 
            <field>
27586 
              <name>NPTXFSAV</name>
27587 
              <description>Non-periodic TxFIFO space
27588 
              available</description>
27589 
              <bitOffset>0</bitOffset>
27590 
              <bitWidth>16</bitWidth>
27591 
            </field>
27592 
            <field>
27593 
              <name>NPTQXSAV</name>
27594 
              <description>Non-periodic transmit request queue
27595 
              space available</description>
27596 
              <bitOffset>16</bitOffset>
27597 
              <bitWidth>8</bitWidth>
27598 
            </field>
27599 
            <field>
27600 
              <name>NPTXQTOP</name>
27601 
              <description>Top of the non-periodic transmit request
27602 
              queue</description>
27603 
              <bitOffset>24</bitOffset>
27604 
              <bitWidth>7</bitWidth>
27605 
            </field>
27606 
          </fields>
27607 
        </register>
27608 
        <register>
27609 
          <name>FS_GCCFG</name>
27610 
          <displayName>FS_GCCFG</displayName>
27611 
          <description>OTG_FS general core configuration register
27612 
          (OTG_FS_GCCFG)</description>
27613 
          <addressOffset>0x38</addressOffset>
27614 
          <size>0x20</size>
27615 
          <access>read-write</access>
27616 
          <resetValue>0x00000000</resetValue>
27617 
          <fields>
27618 
            <field>
27619 
              <name>PWRDWN</name>
27620 
              <description>Power down</description>
27621 
              <bitOffset>16</bitOffset>
27622 
              <bitWidth>1</bitWidth>
27623 
            </field>
27624 
            <field>
27625 
              <name>VBUSASEN</name>
27626 
              <description>Enable the VBUS sensing
27627 
              device</description>
27628 
              <bitOffset>18</bitOffset>
27629 
              <bitWidth>1</bitWidth>
27630 
            </field>
27631 
            <field>
27632 
              <name>VBUSBSEN</name>
27633 
              <description>Enable the VBUS sensing
27634 
              device</description>
27635 
              <bitOffset>19</bitOffset>
27636 
              <bitWidth>1</bitWidth>
27637 
            </field>
27638 
            <field>
27639 
              <name>SOFOUTEN</name>
27640 
              <description>SOF output enable</description>
27641 
              <bitOffset>20</bitOffset>
27642 
              <bitWidth>1</bitWidth>
27643 
            </field>
27644 
          </fields>
27645 
        </register>
27646 
        <register>
27647 
          <name>FS_CID</name>
27648 
          <displayName>FS_CID</displayName>
27649 
          <description>core ID register</description>
27650 
          <addressOffset>0x3C</addressOffset>
27651 
          <size>0x20</size>
27652 
          <access>read-write</access>
27653 
          <resetValue>0x00001000</resetValue>
27654 
          <fields>
27655 
            <field>
27656 
              <name>PRODUCT_ID</name>
27657 
              <description>Product ID field</description>
27658 
              <bitOffset>0</bitOffset>
27659 
              <bitWidth>32</bitWidth>
27660 
            </field>
27661 
          </fields>
27662 
        </register>
27663 
        <register>
27664 
          <name>FS_HPTXFSIZ</name>
27665 
          <displayName>FS_HPTXFSIZ</displayName>
27666 
          <description>OTG_FS Host periodic transmit FIFO size
27667 
          register (OTG_FS_HPTXFSIZ)</description>
27668 
          <addressOffset>0x100</addressOffset>
27669 
          <size>0x20</size>
27670 
          <access>read-write</access>
27671 
          <resetValue>0x02000600</resetValue>
27672 
          <fields>
27673 
            <field>
27674 
              <name>PTXSA</name>
27675 
              <description>Host periodic TxFIFO start
27676 
              address</description>
27677 
              <bitOffset>0</bitOffset>
27678 
              <bitWidth>16</bitWidth>
27679 
            </field>
27680 
            <field>
27681 
              <name>PTXFSIZ</name>
27682 
              <description>Host periodic TxFIFO depth</description>
27683 
              <bitOffset>16</bitOffset>
27684 
              <bitWidth>16</bitWidth>
27685 
            </field>
27686 
          </fields>
27687 
        </register>
27688 
        <register>
27689 
          <name>FS_DIEPTXF1</name>
27690 
          <displayName>FS_DIEPTXF1</displayName>
27691 
          <description>OTG_FS device IN endpoint transmit FIFO size
27692 
          register (OTG_FS_DIEPTXF2)</description>
27693 
          <addressOffset>0x104</addressOffset>
27694 
          <size>0x20</size>
27695 
          <access>read-write</access>
27696 
          <resetValue>0x02000400</resetValue>
27697 
          <fields>
27698 
            <field>
27699 
              <name>INEPTXSA</name>
27700 
              <description>IN endpoint FIFO2 transmit RAM start
27701 
              address</description>
27702 
              <bitOffset>0</bitOffset>
27703 
              <bitWidth>16</bitWidth>
27704 
            </field>
27705 
            <field>
27706 
              <name>INEPTXFD</name>
27707 
              <description>IN endpoint TxFIFO depth</description>
27708 
              <bitOffset>16</bitOffset>
27709 
              <bitWidth>16</bitWidth>
27710 
            </field>
27711 
          </fields>
27712 
        </register>
27713 
        <register>
27714 
          <name>FS_DIEPTXF2</name>
27715 
          <displayName>FS_DIEPTXF2</displayName>
27716 
          <description>OTG_FS device IN endpoint transmit FIFO size
27717 
          register (OTG_FS_DIEPTXF3)</description>
27718 
          <addressOffset>0x108</addressOffset>
27719 
          <size>0x20</size>
27720 
          <access>read-write</access>
27721 
          <resetValue>0x02000400</resetValue>
27722 
          <fields>
27723 
            <field>
27724 
              <name>INEPTXSA</name>
27725 
              <description>IN endpoint FIFO3 transmit RAM start
27726 
              address</description>
27727 
              <bitOffset>0</bitOffset>
27728 
              <bitWidth>16</bitWidth>
27729 
            </field>
27730 
            <field>
27731 
              <name>INEPTXFD</name>
27732 
              <description>IN endpoint TxFIFO depth</description>
27733 
              <bitOffset>16</bitOffset>
27734 
              <bitWidth>16</bitWidth>
27735 
            </field>
27736 
          </fields>
27737 
        </register>
27738 
        <register>
27739 
          <name>FS_DIEPTXF3</name>
27740 
          <displayName>FS_DIEPTXF3</displayName>
27741 
          <description>OTG_FS device IN endpoint transmit FIFO size
27742 
          register (OTG_FS_DIEPTXF4)</description>
27743 
          <addressOffset>0x10C</addressOffset>
27744 
          <size>0x20</size>
27745 
          <access>read-write</access>
27746 
          <resetValue>0x02000400</resetValue>
27747 
          <fields>
27748 
            <field>
27749 
              <name>INEPTXSA</name>
27750 
              <description>IN endpoint FIFO4 transmit RAM start
27751 
              address</description>
27752 
              <bitOffset>0</bitOffset>
27753 
              <bitWidth>16</bitWidth>
27754 
            </field>
27755 
            <field>
27756 
              <name>INEPTXFD</name>
27757 
              <description>IN endpoint TxFIFO depth</description>
27758 
              <bitOffset>16</bitOffset>
27759 
              <bitWidth>16</bitWidth>
27760 
            </field>
27761 
          </fields>
27762 
        </register>
27763 
      </registers>
27764 
    </peripheral>
27765 
    <peripheral>
27766 
      <name>OTG_FS_HOST</name>
27767 
      <description>USB on the go full speed</description>
27768 
      <groupName>USB_OTG_FS</groupName>
27769 
      <baseAddress>0x50000400</baseAddress>
27770 
      <addressBlock>
27771 
        <offset>0x0</offset>
27772 
        <size>0x400</size>
27773 
        <usage>registers</usage>
27774 
      </addressBlock>
27775 
      <registers>
27776 
        <register>
27777 
          <name>FS_HCFG</name>
27778 
          <displayName>FS_HCFG</displayName>
27779 
          <description>OTG_FS host configuration register
27780 
          (OTG_FS_HCFG)</description>
27781 
          <addressOffset>0x0</addressOffset>
27782 
          <size>0x20</size>
27783 
          <resetValue>0x00000000</resetValue>
27784 
          <fields>
27785 
            <field>
27786 
              <name>FSLSPCS</name>
27787 
              <description>FS/LS PHY clock select</description>
27788 
              <bitOffset>0</bitOffset>
27789 
              <bitWidth>2</bitWidth>
27790 
              <access>read-write</access>
27791 
            </field>
27792 
            <field>
27793 
              <name>FSLSS</name>
27794 
              <description>FS- and LS-only support</description>
27795 
              <bitOffset>2</bitOffset>
27796 
              <bitWidth>1</bitWidth>
27797 
              <access>read-only</access>
27798 
            </field>
27799 
          </fields>
27800 
        </register>
27801 
        <register>
27802 
          <name>HFIR</name>
27803 
          <displayName>HFIR</displayName>
27804 
          <description>OTG_FS Host frame interval
27805 
          register</description>
27806 
          <addressOffset>0x4</addressOffset>
27807 
          <size>0x20</size>
27808 
          <access>read-write</access>
27809 
          <resetValue>0x0000EA60</resetValue>
27810 
          <fields>
27811 
            <field>
27812 
              <name>FRIVL</name>
27813 
              <description>Frame interval</description>
27814 
              <bitOffset>0</bitOffset>
27815 
              <bitWidth>16</bitWidth>
27816 
            </field>
27817 
          </fields>
27818 
        </register>
27819 
        <register>
27820 
          <name>FS_HFNUM</name>
27821 
          <displayName>FS_HFNUM</displayName>
27822 
          <description>OTG_FS host frame number/frame time
27823 
          remaining register (OTG_FS_HFNUM)</description>
27824 
          <addressOffset>0x8</addressOffset>
27825 
          <size>0x20</size>
27826 
          <access>read-only</access>
27827 
          <resetValue>0x00003FFF</resetValue>
27828 
          <fields>
27829 
            <field>
27830 
              <name>FRNUM</name>
27831 
              <description>Frame number</description>
27832 
              <bitOffset>0</bitOffset>
27833 
              <bitWidth>16</bitWidth>
27834 
            </field>
27835 
            <field>
27836 
              <name>FTREM</name>
27837 
              <description>Frame time remaining</description>
27838 
              <bitOffset>16</bitOffset>
27839 
              <bitWidth>16</bitWidth>
27840 
            </field>
27841 
          </fields>
27842 
        </register>
27843 
        <register>
27844 
          <name>FS_HPTXSTS</name>
27845 
          <displayName>FS_HPTXSTS</displayName>
27846 
          <description>OTG_FS_Host periodic transmit FIFO/queue
27847 
          status register (OTG_FS_HPTXSTS)</description>
27848 
          <addressOffset>0x10</addressOffset>
27849 
          <size>0x20</size>
27850 
          <resetValue>0x00080100</resetValue>
27851 
          <fields>
27852 
            <field>
27853 
              <name>PTXFSAVL</name>
27854 
              <description>Periodic transmit data FIFO space
27855 
              available</description>
27856 
              <bitOffset>0</bitOffset>
27857 
              <bitWidth>16</bitWidth>
27858 
              <access>read-write</access>
27859 
            </field>
27860 
            <field>
27861 
              <name>PTXQSAV</name>
27862 
              <description>Periodic transmit request queue space
27863 
              available</description>
27864 
              <bitOffset>16</bitOffset>
27865 
              <bitWidth>8</bitWidth>
27866 
              <access>read-only</access>
27867 
            </field>
27868 
            <field>
27869 
              <name>PTXQTOP</name>
27870 
              <description>Top of the periodic transmit request
27871 
              queue</description>
27872 
              <bitOffset>24</bitOffset>
27873 
              <bitWidth>8</bitWidth>
27874 
              <access>read-only</access>
27875 
            </field>
27876 
          </fields>
27877 
        </register>
27878 
        <register>
27879 
          <name>HAINT</name>
27880 
          <displayName>HAINT</displayName>
27881 
          <description>OTG_FS Host all channels interrupt
27882 
          register</description>
27883 
          <addressOffset>0x14</addressOffset>
27884 
          <size>0x20</size>
27885 
          <access>read-only</access>
27886 
          <resetValue>0x00000000</resetValue>
27887 
          <fields>
27888 
            <field>
27889 
              <name>HAINT</name>
27890 
              <description>Channel interrupts</description>
27891 
              <bitOffset>0</bitOffset>
27892 
              <bitWidth>16</bitWidth>
27893 
            </field>
27894 
          </fields>
27895 
        </register>
27896 
        <register>
27897 
          <name>HAINTMSK</name>
27898 
          <displayName>HAINTMSK</displayName>
27899 
          <description>OTG_FS host all channels interrupt mask
27900 
          register</description>
27901 
          <addressOffset>0x18</addressOffset>
27902 
          <size>0x20</size>
27903 
          <access>read-write</access>
27904 
          <resetValue>0x00000000</resetValue>
27905 
          <fields>
27906 
            <field>
27907 
              <name>HAINTM</name>
27908 
              <description>Channel interrupt mask</description>
27909 
              <bitOffset>0</bitOffset>
27910 
              <bitWidth>16</bitWidth>
27911 
            </field>
27912 
          </fields>
27913 
        </register>
27914 
        <register>
27915 
          <name>FS_HPRT</name>
27916 
          <displayName>FS_HPRT</displayName>
27917 
          <description>OTG_FS host port control and status register
27918 
          (OTG_FS_HPRT)</description>
27919 
          <addressOffset>0x40</addressOffset>
27920 
          <size>0x20</size>
27921 
          <resetValue>0x00000000</resetValue>
27922 
          <fields>
27923 
            <field>
27924 
              <name>PCSTS</name>
27925 
              <description>Port connect status</description>
27926 
              <bitOffset>0</bitOffset>
27927 
              <bitWidth>1</bitWidth>
27928 
              <access>read-only</access>
27929 
            </field>
27930 
            <field>
27931 
              <name>PCDET</name>
27932 
              <description>Port connect detected</description>
27933 
              <bitOffset>1</bitOffset>
27934 
              <bitWidth>1</bitWidth>
27935 
              <access>read-write</access>
27936 
            </field>
27937 
            <field>
27938 
              <name>PENA</name>
27939 
              <description>Port enable</description>
27940 
              <bitOffset>2</bitOffset>
27941 
              <bitWidth>1</bitWidth>
27942 
              <access>read-write</access>
27943 
            </field>
27944 
            <field>
27945 
              <name>PENCHNG</name>
27946 
              <description>Port enable/disable change</description>
27947 
              <bitOffset>3</bitOffset>
27948 
              <bitWidth>1</bitWidth>
27949 
              <access>read-write</access>
27950 
            </field>
27951 
            <field>
27952 
              <name>POCA</name>
27953 
              <description>Port overcurrent active</description>
27954 
              <bitOffset>4</bitOffset>
27955 
              <bitWidth>1</bitWidth>
27956 
              <access>read-only</access>
27957 
            </field>
27958 
            <field>
27959 
              <name>POCCHNG</name>
27960 
              <description>Port overcurrent change</description>
27961 
              <bitOffset>5</bitOffset>
27962 
              <bitWidth>1</bitWidth>
27963 
              <access>read-write</access>
27964 
            </field>
27965 
            <field>
27966 
              <name>PRES</name>
27967 
              <description>Port resume</description>
27968 
              <bitOffset>6</bitOffset>
27969 
              <bitWidth>1</bitWidth>
27970 
              <access>read-write</access>
27971 
            </field>
27972 
            <field>
27973 
              <name>PSUSP</name>
27974 
              <description>Port suspend</description>
27975 
              <bitOffset>7</bitOffset>
27976 
              <bitWidth>1</bitWidth>
27977 
              <access>read-write</access>
27978 
            </field>
27979 
            <field>
27980 
              <name>PRST</name>
27981 
              <description>Port reset</description>
27982 
              <bitOffset>8</bitOffset>
27983 
              <bitWidth>1</bitWidth>
27984 
              <access>read-write</access>
27985 
            </field>
27986 
            <field>
27987 
              <name>PLSTS</name>
27988 
              <description>Port line status</description>
27989 
              <bitOffset>10</bitOffset>
27990 
              <bitWidth>2</bitWidth>
27991 
              <access>read-only</access>
27992 
            </field>
27993 
            <field>
27994 
              <name>PPWR</name>
27995 
              <description>Port power</description>
27996 
              <bitOffset>12</bitOffset>
27997 
              <bitWidth>1</bitWidth>
27998 
              <access>read-write</access>
27999 
            </field>
28000 
            <field>
28001 
              <name>PTCTL</name>
28002 
              <description>Port test control</description>
28003 
              <bitOffset>13</bitOffset>
28004 
              <bitWidth>4</bitWidth>
28005 
              <access>read-write</access>
28006 
            </field>
28007 
            <field>
28008 
              <name>PSPD</name>
28009 
              <description>Port speed</description>
28010 
              <bitOffset>17</bitOffset>
28011 
              <bitWidth>2</bitWidth>
28012 
              <access>read-only</access>
28013 
            </field>
28014 
          </fields>
28015 
        </register>
28016 
        <register>
28017 
          <name>FS_HCCHAR0</name>
28018 
          <displayName>FS_HCCHAR0</displayName>
28019 
          <description>OTG_FS host channel-0 characteristics
28020 
          register (OTG_FS_HCCHAR0)</description>
28021 
          <addressOffset>0x100</addressOffset>
28022 
          <size>0x20</size>
28023 
          <access>read-write</access>
28024 
          <resetValue>0x00000000</resetValue>
28025 
          <fields>
28026 
            <field>
28027 
              <name>MPSIZ</name>
28028 
              <description>Maximum packet size</description>
28029 
              <bitOffset>0</bitOffset>
28030 
              <bitWidth>11</bitWidth>
28031 
            </field>
28032 
            <field>
28033 
              <name>EPNUM</name>
28034 
              <description>Endpoint number</description>
28035 
              <bitOffset>11</bitOffset>
28036 
              <bitWidth>4</bitWidth>
28037 
            </field>
28038 
            <field>
28039 
              <name>EPDIR</name>
28040 
              <description>Endpoint direction</description>
28041 
              <bitOffset>15</bitOffset>
28042 
              <bitWidth>1</bitWidth>
28043 
            </field>
28044 
            <field>
28045 
              <name>LSDEV</name>
28046 
              <description>Low-speed device</description>
28047 
              <bitOffset>17</bitOffset>
28048 
              <bitWidth>1</bitWidth>
28049 
            </field>
28050 
            <field>
28051 
              <name>EPTYP</name>
28052 
              <description>Endpoint type</description>
28053 
              <bitOffset>18</bitOffset>
28054 
              <bitWidth>2</bitWidth>
28055 
            </field>
28056 
            <field>
28057 
              <name>MCNT</name>
28058 
              <description>Multicount</description>
28059 
              <bitOffset>20</bitOffset>
28060 
              <bitWidth>2</bitWidth>
28061 
            </field>
28062 
            <field>
28063 
              <name>DAD</name>
28064 
              <description>Device address</description>
28065 
              <bitOffset>22</bitOffset>
28066 
              <bitWidth>7</bitWidth>
28067 
            </field>
28068 
            <field>
28069 
              <name>ODDFRM</name>
28070 
              <description>Odd frame</description>
28071 
              <bitOffset>29</bitOffset>
28072 
              <bitWidth>1</bitWidth>
28073 
            </field>
28074 
            <field>
28075 
              <name>CHDIS</name>
28076 
              <description>Channel disable</description>
28077 
              <bitOffset>30</bitOffset>
28078 
              <bitWidth>1</bitWidth>
28079 
            </field>
28080 
            <field>
28081 
              <name>CHENA</name>
28082 
              <description>Channel enable</description>
28083 
              <bitOffset>31</bitOffset>
28084 
              <bitWidth>1</bitWidth>
28085 
            </field>
28086 
          </fields>
28087 
        </register>
28088 
        <register>
28089 
          <name>FS_HCCHAR1</name>
28090 
          <displayName>FS_HCCHAR1</displayName>
28091 
          <description>OTG_FS host channel-1 characteristics
28092 
          register (OTG_FS_HCCHAR1)</description>
28093 
          <addressOffset>0x120</addressOffset>
28094 
          <size>0x20</size>
28095 
          <access>read-write</access>
28096 
          <resetValue>0x00000000</resetValue>
28097 
          <fields>
28098 
            <field>
28099 
              <name>MPSIZ</name>
28100 
              <description>Maximum packet size</description>
28101 
              <bitOffset>0</bitOffset>
28102 
              <bitWidth>11</bitWidth>
28103 
            </field>
28104 
            <field>
28105 
              <name>EPNUM</name>
28106 
              <description>Endpoint number</description>
28107 
              <bitOffset>11</bitOffset>
28108 
              <bitWidth>4</bitWidth>
28109 
            </field>
28110 
            <field>
28111 
              <name>EPDIR</name>
28112 
              <description>Endpoint direction</description>
28113 
              <bitOffset>15</bitOffset>
28114 
              <bitWidth>1</bitWidth>
28115 
            </field>
28116 
            <field>
28117 
              <name>LSDEV</name>
28118 
              <description>Low-speed device</description>
28119 
              <bitOffset>17</bitOffset>
28120 
              <bitWidth>1</bitWidth>
28121 
            </field>
28122 
            <field>
28123 
              <name>EPTYP</name>
28124 
              <description>Endpoint type</description>
28125 
              <bitOffset>18</bitOffset>
28126 
              <bitWidth>2</bitWidth>
28127 
            </field>
28128 
            <field>
28129 
              <name>MCNT</name>
28130 
              <description>Multicount</description>
28131 
              <bitOffset>20</bitOffset>
28132 
              <bitWidth>2</bitWidth>
28133 
            </field>
28134 
            <field>
28135 
              <name>DAD</name>
28136 
              <description>Device address</description>
28137 
              <bitOffset>22</bitOffset>
28138 
              <bitWidth>7</bitWidth>
28139 
            </field>
28140 
            <field>
28141 
              <name>ODDFRM</name>
28142 
              <description>Odd frame</description>
28143 
              <bitOffset>29</bitOffset>
28144 
              <bitWidth>1</bitWidth>
28145 
            </field>
28146 
            <field>
28147 
              <name>CHDIS</name>
28148 
              <description>Channel disable</description>
28149 
              <bitOffset>30</bitOffset>
28150 
              <bitWidth>1</bitWidth>
28151 
            </field>
28152 
            <field>
28153 
              <name>CHENA</name>
28154 
              <description>Channel enable</description>
28155 
              <bitOffset>31</bitOffset>
28156 
              <bitWidth>1</bitWidth>
28157 
            </field>
28158 
          </fields>
28159 
        </register>
28160 
        <register>
28161 
          <name>FS_HCCHAR2</name>
28162 
          <displayName>FS_HCCHAR2</displayName>
28163 
          <description>OTG_FS host channel-2 characteristics
28164 
          register (OTG_FS_HCCHAR2)</description>
28165 
          <addressOffset>0x140</addressOffset>
28166 
          <size>0x20</size>
28167 
          <access>read-write</access>
28168 
          <resetValue>0x00000000</resetValue>
28169 
          <fields>
28170 
            <field>
28171 
              <name>MPSIZ</name>
28172 
              <description>Maximum packet size</description>
28173 
              <bitOffset>0</bitOffset>
28174 
              <bitWidth>11</bitWidth>
28175 
            </field>
28176 
            <field>
28177 
              <name>EPNUM</name>
28178 
              <description>Endpoint number</description>
28179 
              <bitOffset>11</bitOffset>
28180 
              <bitWidth>4</bitWidth>
28181 
            </field>
28182 
            <field>
28183 
              <name>EPDIR</name>
28184 
              <description>Endpoint direction</description>
28185 
              <bitOffset>15</bitOffset>
28186 
              <bitWidth>1</bitWidth>
28187 
            </field>
28188 
            <field>
28189 
              <name>LSDEV</name>
28190 
              <description>Low-speed device</description>
28191 
              <bitOffset>17</bitOffset>
28192 
              <bitWidth>1</bitWidth>
28193 
            </field>
28194 
            <field>
28195 
              <name>EPTYP</name>
28196 
              <description>Endpoint type</description>
28197 
              <bitOffset>18</bitOffset>
28198 
              <bitWidth>2</bitWidth>
28199 
            </field>
28200 
            <field>
28201 
              <name>MCNT</name>
28202 
              <description>Multicount</description>
28203 
              <bitOffset>20</bitOffset>
28204 
              <bitWidth>2</bitWidth>
28205 
            </field>
28206 
            <field>
28207 
              <name>DAD</name>
28208 
              <description>Device address</description>
28209 
              <bitOffset>22</bitOffset>
28210 
              <bitWidth>7</bitWidth>
28211 
            </field>
28212 
            <field>
28213 
              <name>ODDFRM</name>
28214 
              <description>Odd frame</description>
28215 
              <bitOffset>29</bitOffset>
28216 
              <bitWidth>1</bitWidth>
28217 
            </field>
28218 
            <field>
28219 
              <name>CHDIS</name>
28220 
              <description>Channel disable</description>
28221 
              <bitOffset>30</bitOffset>
28222 
              <bitWidth>1</bitWidth>
28223 
            </field>
28224 
            <field>
28225 
              <name>CHENA</name>
28226 
              <description>Channel enable</description>
28227 
              <bitOffset>31</bitOffset>
28228 
              <bitWidth>1</bitWidth>
28229 
            </field>
28230 
          </fields>
28231 
        </register>
28232 
        <register>
28233 
          <name>FS_HCCHAR3</name>
28234 
          <displayName>FS_HCCHAR3</displayName>
28235 
          <description>OTG_FS host channel-3 characteristics
28236 
          register (OTG_FS_HCCHAR3)</description>
28237 
          <addressOffset>0x160</addressOffset>
28238 
          <size>0x20</size>
28239 
          <access>read-write</access>
28240 
          <resetValue>0x00000000</resetValue>
28241 
          <fields>
28242 
            <field>
28243 
              <name>MPSIZ</name>
28244 
              <description>Maximum packet size</description>
28245 
              <bitOffset>0</bitOffset>
28246 
              <bitWidth>11</bitWidth>
28247 
            </field>
28248 
            <field>
28249 
              <name>EPNUM</name>
28250 
              <description>Endpoint number</description>
28251 
              <bitOffset>11</bitOffset>
28252 
              <bitWidth>4</bitWidth>
28253 
            </field>
28254 
            <field>
28255 
              <name>EPDIR</name>
28256 
              <description>Endpoint direction</description>
28257 
              <bitOffset>15</bitOffset>
28258 
              <bitWidth>1</bitWidth>
28259 
            </field>
28260 
            <field>
28261 
              <name>LSDEV</name>
28262 
              <description>Low-speed device</description>
28263 
              <bitOffset>17</bitOffset>
28264 
              <bitWidth>1</bitWidth>
28265 
            </field>
28266 
            <field>
28267 
              <name>EPTYP</name>
28268 
              <description>Endpoint type</description>
28269 
              <bitOffset>18</bitOffset>
28270 
              <bitWidth>2</bitWidth>
28271 
            </field>
28272 
            <field>
28273 
              <name>MCNT</name>
28274 
              <description>Multicount</description>
28275 
              <bitOffset>20</bitOffset>
28276 
              <bitWidth>2</bitWidth>
28277 
            </field>
28278 
            <field>
28279 
              <name>DAD</name>
28280 
              <description>Device address</description>
28281 
              <bitOffset>22</bitOffset>
28282 
              <bitWidth>7</bitWidth>
28283 
            </field>
28284 
            <field>
28285 
              <name>ODDFRM</name>
28286 
              <description>Odd frame</description>
28287 
              <bitOffset>29</bitOffset>
28288 
              <bitWidth>1</bitWidth>
28289 
            </field>
28290 
            <field>
28291 
              <name>CHDIS</name>
28292 
              <description>Channel disable</description>
28293 
              <bitOffset>30</bitOffset>
28294 
              <bitWidth>1</bitWidth>
28295 
            </field>
28296 
            <field>
28297 
              <name>CHENA</name>
28298 
              <description>Channel enable</description>
28299 
              <bitOffset>31</bitOffset>
28300 
              <bitWidth>1</bitWidth>
28301 
            </field>
28302 
          </fields>
28303 
        </register>
28304 
        <register>
28305 
          <name>FS_HCCHAR4</name>
28306 
          <displayName>FS_HCCHAR4</displayName>
28307 
          <description>OTG_FS host channel-4 characteristics
28308 
          register (OTG_FS_HCCHAR4)</description>
28309 
          <addressOffset>0x180</addressOffset>
28310 
          <size>0x20</size>
28311 
          <access>read-write</access>
28312 
          <resetValue>0x00000000</resetValue>
28313 
          <fields>
28314 
            <field>
28315 
              <name>MPSIZ</name>
28316 
              <description>Maximum packet size</description>
28317 
              <bitOffset>0</bitOffset>
28318 
              <bitWidth>11</bitWidth>
28319 
            </field>
28320 
            <field>
28321 
              <name>EPNUM</name>
28322 
              <description>Endpoint number</description>
28323 
              <bitOffset>11</bitOffset>
28324 
              <bitWidth>4</bitWidth>
28325 
            </field>
28326 
            <field>
28327 
              <name>EPDIR</name>
28328 
              <description>Endpoint direction</description>
28329 
              <bitOffset>15</bitOffset>
28330 
              <bitWidth>1</bitWidth>
28331 
            </field>
28332 
            <field>
28333 
              <name>LSDEV</name>
28334 
              <description>Low-speed device</description>
28335 
              <bitOffset>17</bitOffset>
28336 
              <bitWidth>1</bitWidth>
28337 
            </field>
28338 
            <field>
28339 
              <name>EPTYP</name>
28340 
              <description>Endpoint type</description>
28341 
              <bitOffset>18</bitOffset>
28342 
              <bitWidth>2</bitWidth>
28343 
            </field>
28344 
            <field>
28345 
              <name>MCNT</name>
28346 
              <description>Multicount</description>
28347 
              <bitOffset>20</bitOffset>
28348 
              <bitWidth>2</bitWidth>
28349 
            </field>
28350 
            <field>
28351 
              <name>DAD</name>
28352 
              <description>Device address</description>
28353 
              <bitOffset>22</bitOffset>
28354 
              <bitWidth>7</bitWidth>
28355 
            </field>
28356 
            <field>
28357 
              <name>ODDFRM</name>
28358 
              <description>Odd frame</description>
28359 
              <bitOffset>29</bitOffset>
28360 
              <bitWidth>1</bitWidth>
28361 
            </field>
28362 
            <field>
28363 
              <name>CHDIS</name>
28364 
              <description>Channel disable</description>
28365 
              <bitOffset>30</bitOffset>
28366 
              <bitWidth>1</bitWidth>
28367 
            </field>
28368 
            <field>
28369 
              <name>CHENA</name>
28370 
              <description>Channel enable</description>
28371 
              <bitOffset>31</bitOffset>
28372 
              <bitWidth>1</bitWidth>
28373 
            </field>
28374 
          </fields>
28375 
        </register>
28376 
        <register>
28377 
          <name>FS_HCCHAR5</name>
28378 
          <displayName>FS_HCCHAR5</displayName>
28379 
          <description>OTG_FS host channel-5 characteristics
28380 
          register (OTG_FS_HCCHAR5)</description>
28381 
          <addressOffset>0x1A0</addressOffset>
28382 
          <size>0x20</size>
28383 
          <access>read-write</access>
28384 
          <resetValue>0x00000000</resetValue>
28385 
          <fields>
28386 
            <field>
28387 
              <name>MPSIZ</name>
28388 
              <description>Maximum packet size</description>
28389 
              <bitOffset>0</bitOffset>
28390 
              <bitWidth>11</bitWidth>
28391 
            </field>
28392 
            <field>
28393 
              <name>EPNUM</name>
28394 
              <description>Endpoint number</description>
28395 
              <bitOffset>11</bitOffset>
28396 
              <bitWidth>4</bitWidth>
28397 
            </field>
28398 
            <field>
28399 
              <name>EPDIR</name>
28400 
              <description>Endpoint direction</description>
28401 
              <bitOffset>15</bitOffset>
28402 
              <bitWidth>1</bitWidth>
28403 
            </field>
28404 
            <field>
28405 
              <name>LSDEV</name>
28406 
              <description>Low-speed device</description>
28407 
              <bitOffset>17</bitOffset>
28408 
              <bitWidth>1</bitWidth>
28409 
            </field>
28410 
            <field>
28411 
              <name>EPTYP</name>
28412 
              <description>Endpoint type</description>
28413 
              <bitOffset>18</bitOffset>
28414 
              <bitWidth>2</bitWidth>
28415 
            </field>
28416 
            <field>
28417 
              <name>MCNT</name>
28418 
              <description>Multicount</description>
28419 
              <bitOffset>20</bitOffset>
28420 
              <bitWidth>2</bitWidth>
28421 
            </field>
28422 
            <field>
28423 
              <name>DAD</name>
28424 
              <description>Device address</description>
28425 
              <bitOffset>22</bitOffset>
28426 
              <bitWidth>7</bitWidth>
28427 
            </field>
28428 
            <field>
28429 
              <name>ODDFRM</name>
28430 
              <description>Odd frame</description>
28431 
              <bitOffset>29</bitOffset>
28432 
              <bitWidth>1</bitWidth>
28433 
            </field>
28434 
            <field>
28435 
              <name>CHDIS</name>
28436 
              <description>Channel disable</description>
28437 
              <bitOffset>30</bitOffset>
28438 
              <bitWidth>1</bitWidth>
28439 
            </field>
28440 
            <field>
28441 
              <name>CHENA</name>
28442 
              <description>Channel enable</description>
28443 
              <bitOffset>31</bitOffset>
28444 
              <bitWidth>1</bitWidth>
28445 
            </field>
28446 
          </fields>
28447 
        </register>
28448 
        <register>
28449 
          <name>FS_HCCHAR6</name>
28450 
          <displayName>FS_HCCHAR6</displayName>
28451 
          <description>OTG_FS host channel-6 characteristics
28452 
          register (OTG_FS_HCCHAR6)</description>
28453 
          <addressOffset>0x1C0</addressOffset>
28454 
          <size>0x20</size>
28455 
          <access>read-write</access>
28456 
          <resetValue>0x00000000</resetValue>
28457 
          <fields>
28458 
            <field>
28459 
              <name>MPSIZ</name>
28460 
              <description>Maximum packet size</description>
28461 
              <bitOffset>0</bitOffset>
28462 
              <bitWidth>11</bitWidth>
28463 
            </field>
28464 
            <field>
28465 
              <name>EPNUM</name>
28466 
              <description>Endpoint number</description>
28467 
              <bitOffset>11</bitOffset>
28468 
              <bitWidth>4</bitWidth>
28469 
            </field>
28470 
            <field>
28471 
              <name>EPDIR</name>
28472 
              <description>Endpoint direction</description>
28473 
              <bitOffset>15</bitOffset>
28474 
              <bitWidth>1</bitWidth>
28475 
            </field>
28476 
            <field>
28477 
              <name>LSDEV</name>
28478 
              <description>Low-speed device</description>
28479 
              <bitOffset>17</bitOffset>
28480 
              <bitWidth>1</bitWidth>
28481 
            </field>
28482 
            <field>
28483 
              <name>EPTYP</name>
28484 
              <description>Endpoint type</description>
28485 
              <bitOffset>18</bitOffset>
28486 
              <bitWidth>2</bitWidth>
28487 
            </field>
28488 
            <field>
28489 
              <name>MCNT</name>
28490 
              <description>Multicount</description>
28491 
              <bitOffset>20</bitOffset>
28492 
              <bitWidth>2</bitWidth>
28493 
            </field>
28494 
            <field>
28495 
              <name>DAD</name>
28496 
              <description>Device address</description>
28497 
              <bitOffset>22</bitOffset>
28498 
              <bitWidth>7</bitWidth>
28499 
            </field>
28500 
            <field>
28501 
              <name>ODDFRM</name>
28502 
              <description>Odd frame</description>
28503 
              <bitOffset>29</bitOffset>
28504 
              <bitWidth>1</bitWidth>
28505 
            </field>
28506 
            <field>
28507 
              <name>CHDIS</name>
28508 
              <description>Channel disable</description>
28509 
              <bitOffset>30</bitOffset>
28510 
              <bitWidth>1</bitWidth>
28511 
            </field>
28512 
            <field>
28513 
              <name>CHENA</name>
28514 
              <description>Channel enable</description>
28515 
              <bitOffset>31</bitOffset>
28516 
              <bitWidth>1</bitWidth>
28517 
            </field>
28518 
          </fields>
28519 
        </register>
28520 
        <register>
28521 
          <name>FS_HCCHAR7</name>
28522 
          <displayName>FS_HCCHAR7</displayName>
28523 
          <description>OTG_FS host channel-7 characteristics
28524 
          register (OTG_FS_HCCHAR7)</description>
28525 
          <addressOffset>0x1E0</addressOffset>
28526 
          <size>0x20</size>
28527 
          <access>read-write</access>
28528 
          <resetValue>0x00000000</resetValue>
28529 
          <fields>
28530 
            <field>
28531 
              <name>MPSIZ</name>
28532 
              <description>Maximum packet size</description>
28533 
              <bitOffset>0</bitOffset>
28534 
              <bitWidth>11</bitWidth>
28535 
            </field>
28536 
            <field>
28537 
              <name>EPNUM</name>
28538 
              <description>Endpoint number</description>
28539 
              <bitOffset>11</bitOffset>
28540 
              <bitWidth>4</bitWidth>
28541 
            </field>
28542 
            <field>
28543 
              <name>EPDIR</name>
28544 
              <description>Endpoint direction</description>
28545 
              <bitOffset>15</bitOffset>
28546 
              <bitWidth>1</bitWidth>
28547 
            </field>
28548 
            <field>
28549 
              <name>LSDEV</name>
28550 
              <description>Low-speed device</description>
28551 
              <bitOffset>17</bitOffset>
28552 
              <bitWidth>1</bitWidth>
28553 
            </field>
28554 
            <field>
28555 
              <name>EPTYP</name>
28556 
              <description>Endpoint type</description>
28557 
              <bitOffset>18</bitOffset>
28558 
              <bitWidth>2</bitWidth>
28559 
            </field>
28560 
            <field>
28561 
              <name>MCNT</name>
28562 
              <description>Multicount</description>
28563 
              <bitOffset>20</bitOffset>
28564 
              <bitWidth>2</bitWidth>
28565 
            </field>
28566 
            <field>
28567 
              <name>DAD</name>
28568 
              <description>Device address</description>
28569 
              <bitOffset>22</bitOffset>
28570 
              <bitWidth>7</bitWidth>
28571 
            </field>
28572 
            <field>
28573 
              <name>ODDFRM</name>
28574 
              <description>Odd frame</description>
28575 
              <bitOffset>29</bitOffset>
28576 
              <bitWidth>1</bitWidth>
28577 
            </field>
28578 
            <field>
28579 
              <name>CHDIS</name>
28580 
              <description>Channel disable</description>
28581 
              <bitOffset>30</bitOffset>
28582 
              <bitWidth>1</bitWidth>
28583 
            </field>
28584 
            <field>
28585 
              <name>CHENA</name>
28586 
              <description>Channel enable</description>
28587 
              <bitOffset>31</bitOffset>
28588 
              <bitWidth>1</bitWidth>
28589 
            </field>
28590 
          </fields>
28591 
        </register>
28592 
        <register>
28593 
          <name>FS_HCINT0</name>
28594 
          <displayName>FS_HCINT0</displayName>
28595 
          <description>OTG_FS host channel-0 interrupt register
28596 
          (OTG_FS_HCINT0)</description>
28597 
          <addressOffset>0x108</addressOffset>
28598 
          <size>0x20</size>
28599 
          <access>read-write</access>
28600 
          <resetValue>0x00000000</resetValue>
28601 
          <fields>
28602 
            <field>
28603 
              <name>XFRC</name>
28604 
              <description>Transfer completed</description>
28605 
              <bitOffset>0</bitOffset>
28606 
              <bitWidth>1</bitWidth>
28607 
            </field>
28608 
            <field>
28609 
              <name>CHH</name>
28610 
              <description>Channel halted</description>
28611 
              <bitOffset>1</bitOffset>
28612 
              <bitWidth>1</bitWidth>
28613 
            </field>
28614 
            <field>
28615 
              <name>STALL</name>
28616 
              <description>STALL response received
28617 
              interrupt</description>
28618 
              <bitOffset>3</bitOffset>
28619 
              <bitWidth>1</bitWidth>
28620 
            </field>
28621 
            <field>
28622 
              <name>NAK</name>
28623 
              <description>NAK response received
28624 
              interrupt</description>
28625 
              <bitOffset>4</bitOffset>
28626 
              <bitWidth>1</bitWidth>
28627 
            </field>
28628 
            <field>
28629 
              <name>ACK</name>
28630 
              <description>ACK response received/transmitted
28631 
              interrupt</description>
28632 
              <bitOffset>5</bitOffset>
28633 
              <bitWidth>1</bitWidth>
28634 
            </field>
28635 
            <field>
28636 
              <name>TXERR</name>
28637 
              <description>Transaction error</description>
28638 
              <bitOffset>7</bitOffset>
28639 
              <bitWidth>1</bitWidth>
28640 
            </field>
28641 
            <field>
28642 
              <name>BBERR</name>
28643 
              <description>Babble error</description>
28644 
              <bitOffset>8</bitOffset>
28645 
              <bitWidth>1</bitWidth>
28646 
            </field>
28647 
            <field>
28648 
              <name>FRMOR</name>
28649 
              <description>Frame overrun</description>
28650 
              <bitOffset>9</bitOffset>
28651 
              <bitWidth>1</bitWidth>
28652 
            </field>
28653 
            <field>
28654 
              <name>DTERR</name>
28655 
              <description>Data toggle error</description>
28656 
              <bitOffset>10</bitOffset>
28657 
              <bitWidth>1</bitWidth>
28658 
            </field>
28659 
          </fields>
28660 
        </register>
28661 
        <register>
28662 
          <name>FS_HCINT1</name>
28663 
          <displayName>FS_HCINT1</displayName>
28664 
          <description>OTG_FS host channel-1 interrupt register
28665 
          (OTG_FS_HCINT1)</description>
28666 
          <addressOffset>0x128</addressOffset>
28667 
          <size>0x20</size>
28668 
          <access>read-write</access>
28669 
          <resetValue>0x00000000</resetValue>
28670 
          <fields>
28671 
            <field>
28672 
              <name>XFRC</name>
28673 
              <description>Transfer completed</description>
28674 
              <bitOffset>0</bitOffset>
28675 
              <bitWidth>1</bitWidth>
28676 
            </field>
28677 
            <field>
28678 
              <name>CHH</name>
28679 
              <description>Channel halted</description>
28680 
              <bitOffset>1</bitOffset>
28681 
              <bitWidth>1</bitWidth>
28682 
            </field>
28683 
            <field>
28684 
              <name>STALL</name>
28685 
              <description>STALL response received
28686 
              interrupt</description>
28687 
              <bitOffset>3</bitOffset>
28688 
              <bitWidth>1</bitWidth>
28689 
            </field>
28690 
            <field>
28691 
              <name>NAK</name>
28692 
              <description>NAK response received
28693 
              interrupt</description>
28694 
              <bitOffset>4</bitOffset>
28695 
              <bitWidth>1</bitWidth>
28696 
            </field>
28697 
            <field>
28698 
              <name>ACK</name>
28699 
              <description>ACK response received/transmitted
28700 
              interrupt</description>
28701 
              <bitOffset>5</bitOffset>
28702 
              <bitWidth>1</bitWidth>
28703 
            </field>
28704 
            <field>
28705 
              <name>TXERR</name>
28706 
              <description>Transaction error</description>
28707 
              <bitOffset>7</bitOffset>
28708 
              <bitWidth>1</bitWidth>
28709 
            </field>
28710 
            <field>
28711 
              <name>BBERR</name>
28712 
              <description>Babble error</description>
28713 
              <bitOffset>8</bitOffset>
28714 
              <bitWidth>1</bitWidth>
28715 
            </field>
28716 
            <field>
28717 
              <name>FRMOR</name>
28718 
              <description>Frame overrun</description>
28719 
              <bitOffset>9</bitOffset>
28720 
              <bitWidth>1</bitWidth>
28721 
            </field>
28722 
            <field>
28723 
              <name>DTERR</name>
28724 
              <description>Data toggle error</description>
28725 
              <bitOffset>10</bitOffset>
28726 
              <bitWidth>1</bitWidth>
28727 
            </field>
28728 
          </fields>
28729 
        </register>
28730 
        <register>
28731 
          <name>FS_HCINT2</name>
28732 
          <displayName>FS_HCINT2</displayName>
28733 
          <description>OTG_FS host channel-2 interrupt register
28734 
          (OTG_FS_HCINT2)</description>
28735 
          <addressOffset>0x148</addressOffset>
28736 
          <size>0x20</size>
28737 
          <access>read-write</access>
28738 
          <resetValue>0x00000000</resetValue>
28739 
          <fields>
28740 
            <field>
28741 
              <name>XFRC</name>
28742 
              <description>Transfer completed</description>
28743 
              <bitOffset>0</bitOffset>
28744 
              <bitWidth>1</bitWidth>
28745 
            </field>
28746 
            <field>
28747 
              <name>CHH</name>
28748 
              <description>Channel halted</description>
28749 
              <bitOffset>1</bitOffset>
28750 
              <bitWidth>1</bitWidth>
28751 
            </field>
28752 
            <field>
28753 
              <name>STALL</name>
28754 
              <description>STALL response received
28755 
              interrupt</description>
28756 
              <bitOffset>3</bitOffset>
28757 
              <bitWidth>1</bitWidth>
28758 
            </field>
28759 
            <field>
28760 
              <name>NAK</name>
28761 
              <description>NAK response received
28762 
              interrupt</description>
28763 
              <bitOffset>4</bitOffset>
28764 
              <bitWidth>1</bitWidth>
28765 
            </field>
28766 
            <field>
28767 
              <name>ACK</name>
28768 
              <description>ACK response received/transmitted
28769 
              interrupt</description>
28770 
              <bitOffset>5</bitOffset>
28771 
              <bitWidth>1</bitWidth>
28772 
            </field>
28773 
            <field>
28774 
              <name>TXERR</name>
28775 
              <description>Transaction error</description>
28776 
              <bitOffset>7</bitOffset>
28777 
              <bitWidth>1</bitWidth>
28778 
            </field>
28779 
            <field>
28780 
              <name>BBERR</name>
28781 
              <description>Babble error</description>
28782 
              <bitOffset>8</bitOffset>
28783 
              <bitWidth>1</bitWidth>
28784 
            </field>
28785 
            <field>
28786 
              <name>FRMOR</name>
28787 
              <description>Frame overrun</description>
28788 
              <bitOffset>9</bitOffset>
28789 
              <bitWidth>1</bitWidth>
28790 
            </field>
28791 
            <field>
28792 
              <name>DTERR</name>
28793 
              <description>Data toggle error</description>
28794 
              <bitOffset>10</bitOffset>
28795 
              <bitWidth>1</bitWidth>
28796 
            </field>
28797 
          </fields>
28798 
        </register>
28799 
        <register>
28800 
          <name>FS_HCINT3</name>
28801 
          <displayName>FS_HCINT3</displayName>
28802 
          <description>OTG_FS host channel-3 interrupt register
28803 
          (OTG_FS_HCINT3)</description>
28804 
          <addressOffset>0x168</addressOffset>
28805 
          <size>0x20</size>
28806 
          <access>read-write</access>
28807 
          <resetValue>0x00000000</resetValue>
28808 
          <fields>
28809 
            <field>
28810 
              <name>XFRC</name>
28811 
              <description>Transfer completed</description>
28812 
              <bitOffset>0</bitOffset>
28813 
              <bitWidth>1</bitWidth>
28814 
            </field>
28815 
            <field>
28816 
              <name>CHH</name>
28817 
              <description>Channel halted</description>
28818 
              <bitOffset>1</bitOffset>
28819 
              <bitWidth>1</bitWidth>
28820 
            </field>
28821 
            <field>
28822 
              <name>STALL</name>
28823 
              <description>STALL response received
28824 
              interrupt</description>
28825 
              <bitOffset>3</bitOffset>
28826 
              <bitWidth>1</bitWidth>
28827 
            </field>
28828 
            <field>
28829 
              <name>NAK</name>
28830 
              <description>NAK response received
28831 
              interrupt</description>
28832 
              <bitOffset>4</bitOffset>
28833 
              <bitWidth>1</bitWidth>
28834 
            </field>
28835 
            <field>
28836 
              <name>ACK</name>
28837 
              <description>ACK response received/transmitted
28838 
              interrupt</description>
28839 
              <bitOffset>5</bitOffset>
28840 
              <bitWidth>1</bitWidth>
28841 
            </field>
28842 
            <field>
28843 
              <name>TXERR</name>
28844 
              <description>Transaction error</description>
28845 
              <bitOffset>7</bitOffset>
28846 
              <bitWidth>1</bitWidth>
28847 
            </field>
28848 
            <field>
28849 
              <name>BBERR</name>
28850 
              <description>Babble error</description>
28851 
              <bitOffset>8</bitOffset>
28852 
              <bitWidth>1</bitWidth>
28853 
            </field>
28854 
            <field>
28855 
              <name>FRMOR</name>
28856 
              <description>Frame overrun</description>
28857 
              <bitOffset>9</bitOffset>
28858 
              <bitWidth>1</bitWidth>
28859 
            </field>
28860 
            <field>
28861 
              <name>DTERR</name>
28862 
              <description>Data toggle error</description>
28863 
              <bitOffset>10</bitOffset>
28864 
              <bitWidth>1</bitWidth>
28865 
            </field>
28866 
          </fields>
28867 
        </register>
28868 
        <register>
28869 
          <name>FS_HCINT4</name>
28870 
          <displayName>FS_HCINT4</displayName>
28871 
          <description>OTG_FS host channel-4 interrupt register
28872 
          (OTG_FS_HCINT4)</description>
28873 
          <addressOffset>0x188</addressOffset>
28874 
          <size>0x20</size>
28875 
          <access>read-write</access>
28876 
          <resetValue>0x00000000</resetValue>
28877 
          <fields>
28878 
            <field>
28879 
              <name>XFRC</name>
28880 
              <description>Transfer completed</description>
28881 
              <bitOffset>0</bitOffset>
28882 
              <bitWidth>1</bitWidth>
28883 
            </field>
28884 
            <field>
28885 
              <name>CHH</name>
28886 
              <description>Channel halted</description>
28887 
              <bitOffset>1</bitOffset>
28888 
              <bitWidth>1</bitWidth>
28889 
            </field>
28890 
            <field>
28891 
              <name>STALL</name>
28892 
              <description>STALL response received
28893 
              interrupt</description>
28894 
              <bitOffset>3</bitOffset>
28895 
              <bitWidth>1</bitWidth>
28896 
            </field>
28897 
            <field>
28898 
              <name>NAK</name>
28899 
              <description>NAK response received
28900 
              interrupt</description>
28901 
              <bitOffset>4</bitOffset>
28902 
              <bitWidth>1</bitWidth>
28903 
            </field>
28904 
            <field>
28905 
              <name>ACK</name>
28906 
              <description>ACK response received/transmitted
28907 
              interrupt</description>
28908 
              <bitOffset>5</bitOffset>
28909 
              <bitWidth>1</bitWidth>
28910 
            </field>
28911 
            <field>
28912 
              <name>TXERR</name>
28913 
              <description>Transaction error</description>
28914 
              <bitOffset>7</bitOffset>
28915 
              <bitWidth>1</bitWidth>
28916 
            </field>
28917 
            <field>
28918 
              <name>BBERR</name>
28919 
              <description>Babble error</description>
28920 
              <bitOffset>8</bitOffset>
28921 
              <bitWidth>1</bitWidth>
28922 
            </field>
28923 
            <field>
28924 
              <name>FRMOR</name>
28925 
              <description>Frame overrun</description>
28926 
              <bitOffset>9</bitOffset>
28927 
              <bitWidth>1</bitWidth>
28928 
            </field>
28929 
            <field>
28930 
              <name>DTERR</name>
28931 
              <description>Data toggle error</description>
28932 
              <bitOffset>10</bitOffset>
28933 
              <bitWidth>1</bitWidth>
28934 
            </field>
28935 
          </fields>
28936 
        </register>
28937 
        <register>
28938 
          <name>FS_HCINT5</name>
28939 
          <displayName>FS_HCINT5</displayName>
28940 
          <description>OTG_FS host channel-5 interrupt register
28941 
          (OTG_FS_HCINT5)</description>
28942 
          <addressOffset>0x1A8</addressOffset>
28943 
          <size>0x20</size>
28944 
          <access>read-write</access>
28945 
          <resetValue>0x00000000</resetValue>
28946 
          <fields>
28947 
            <field>
28948 
              <name>XFRC</name>
28949 
              <description>Transfer completed</description>
28950 
              <bitOffset>0</bitOffset>
28951 
              <bitWidth>1</bitWidth>
28952 
            </field>
28953 
            <field>
28954 
              <name>CHH</name>
28955 
              <description>Channel halted</description>
28956 
              <bitOffset>1</bitOffset>
28957 
              <bitWidth>1</bitWidth>
28958 
            </field>
28959 
            <field>
28960 
              <name>STALL</name>
28961 
              <description>STALL response received
28962 
              interrupt</description>
28963 
              <bitOffset>3</bitOffset>
28964 
              <bitWidth>1</bitWidth>
28965 
            </field>
28966 
            <field>
28967 
              <name>NAK</name>
28968 
              <description>NAK response received
28969 
              interrupt</description>
28970 
              <bitOffset>4</bitOffset>
28971 
              <bitWidth>1</bitWidth>
28972 
            </field>
28973 
            <field>
28974 
              <name>ACK</name>
28975 
              <description>ACK response received/transmitted
28976 
              interrupt</description>
28977 
              <bitOffset>5</bitOffset>
28978 
              <bitWidth>1</bitWidth>
28979 
            </field>
28980 
            <field>
28981 
              <name>TXERR</name>
28982 
              <description>Transaction error</description>
28983 
              <bitOffset>7</bitOffset>
28984 
              <bitWidth>1</bitWidth>
28985 
            </field>
28986 
            <field>
28987 
              <name>BBERR</name>
28988 
              <description>Babble error</description>
28989 
              <bitOffset>8</bitOffset>
28990 
              <bitWidth>1</bitWidth>
28991 
            </field>
28992 
            <field>
28993 
              <name>FRMOR</name>
28994 
              <description>Frame overrun</description>
28995 
              <bitOffset>9</bitOffset>
28996 
              <bitWidth>1</bitWidth>
28997 
            </field>
28998 
            <field>
28999 
              <name>DTERR</name>
29000 
              <description>Data toggle error</description>
29001 
              <bitOffset>10</bitOffset>
29002 
              <bitWidth>1</bitWidth>
29003 
            </field>
29004 
          </fields>
29005 
        </register>
29006 
        <register>
29007 
          <name>FS_HCINT6</name>
29008 
          <displayName>FS_HCINT6</displayName>
29009 
          <description>OTG_FS host channel-6 interrupt register
29010 
          (OTG_FS_HCINT6)</description>
29011 
          <addressOffset>0x1C8</addressOffset>
29012 
          <size>0x20</size>
29013 
          <access>read-write</access>
29014 
          <resetValue>0x00000000</resetValue>
29015 
          <fields>
29016 
            <field>
29017 
              <name>XFRC</name>
29018 
              <description>Transfer completed</description>
29019 
              <bitOffset>0</bitOffset>
29020 
              <bitWidth>1</bitWidth>
29021 
            </field>
29022 
            <field>
29023 
              <name>CHH</name>
29024 
              <description>Channel halted</description>
29025 
              <bitOffset>1</bitOffset>
29026 
              <bitWidth>1</bitWidth>
29027 
            </field>
29028 
            <field>
29029 
              <name>STALL</name>
29030 
              <description>STALL response received
29031 
              interrupt</description>
29032 
              <bitOffset>3</bitOffset>
29033 
              <bitWidth>1</bitWidth>
29034 
            </field>
29035 
            <field>
29036 
              <name>NAK</name>
29037 
              <description>NAK response received
29038 
              interrupt</description>
29039 
              <bitOffset>4</bitOffset>
29040 
              <bitWidth>1</bitWidth>
29041 
            </field>
29042 
            <field>
29043 
              <name>ACK</name>
29044 
              <description>ACK response received/transmitted
29045 
              interrupt</description>
29046 
              <bitOffset>5</bitOffset>
29047 
              <bitWidth>1</bitWidth>
29048 
            </field>
29049 
            <field>
29050 
              <name>TXERR</name>
29051 
              <description>Transaction error</description>
29052 
              <bitOffset>7</bitOffset>
29053 
              <bitWidth>1</bitWidth>
29054 
            </field>
29055 
            <field>
29056 
              <name>BBERR</name>
29057 
              <description>Babble error</description>
29058 
              <bitOffset>8</bitOffset>
29059 
              <bitWidth>1</bitWidth>
29060 
            </field>
29061 
            <field>
29062 
              <name>FRMOR</name>
29063 
              <description>Frame overrun</description>
29064 
              <bitOffset>9</bitOffset>
29065 
              <bitWidth>1</bitWidth>
29066 
            </field>
29067 
            <field>
29068 
              <name>DTERR</name>
29069 
              <description>Data toggle error</description>
29070 
              <bitOffset>10</bitOffset>
29071 
              <bitWidth>1</bitWidth>
29072 
            </field>
29073 
          </fields>
29074 
        </register>
29075 
        <register>
29076 
          <name>FS_HCINT7</name>
29077 
          <displayName>FS_HCINT7</displayName>
29078 
          <description>OTG_FS host channel-7 interrupt register
29079 
          (OTG_FS_HCINT7)</description>
29080 
          <addressOffset>0x1E8</addressOffset>
29081 
          <size>0x20</size>
29082 
          <access>read-write</access>
29083 
          <resetValue>0x00000000</resetValue>
29084 
          <fields>
29085 
            <field>
29086 
              <name>XFRC</name>
29087 
              <description>Transfer completed</description>
29088 
              <bitOffset>0</bitOffset>
29089 
              <bitWidth>1</bitWidth>
29090 
            </field>
29091 
            <field>
29092 
              <name>CHH</name>
29093 
              <description>Channel halted</description>
29094 
              <bitOffset>1</bitOffset>
29095 
              <bitWidth>1</bitWidth>
29096 
            </field>
29097 
            <field>
29098 
              <name>STALL</name>
29099 
              <description>STALL response received
29100 
              interrupt</description>
29101 
              <bitOffset>3</bitOffset>
29102 
              <bitWidth>1</bitWidth>
29103 
            </field>
29104 
            <field>
29105 
              <name>NAK</name>
29106 
              <description>NAK response received
29107 
              interrupt</description>
29108 
              <bitOffset>4</bitOffset>
29109 
              <bitWidth>1</bitWidth>
29110 
            </field>
29111 
            <field>
29112 
              <name>ACK</name>
29113 
              <description>ACK response received/transmitted
29114 
              interrupt</description>
29115 
              <bitOffset>5</bitOffset>
29116 
              <bitWidth>1</bitWidth>
29117 
            </field>
29118 
            <field>
29119 
              <name>TXERR</name>
29120 
              <description>Transaction error</description>
29121 
              <bitOffset>7</bitOffset>
29122 
              <bitWidth>1</bitWidth>
29123 
            </field>
29124 
            <field>
29125 
              <name>BBERR</name>
29126 
              <description>Babble error</description>
29127 
              <bitOffset>8</bitOffset>
29128 
              <bitWidth>1</bitWidth>
29129 
            </field>
29130 
            <field>
29131 
              <name>FRMOR</name>
29132 
              <description>Frame overrun</description>
29133 
              <bitOffset>9</bitOffset>
29134 
              <bitWidth>1</bitWidth>
29135 
            </field>
29136 
            <field>
29137 
              <name>DTERR</name>
29138 
              <description>Data toggle error</description>
29139 
              <bitOffset>10</bitOffset>
29140 
              <bitWidth>1</bitWidth>
29141 
            </field>
29142 
          </fields>
29143 
        </register>
29144 
        <register>
29145 
          <name>FS_HCINTMSK0</name>
29146 
          <displayName>FS_HCINTMSK0</displayName>
29147 
          <description>OTG_FS host channel-0 mask register
29148 
          (OTG_FS_HCINTMSK0)</description>
29149 
          <addressOffset>0x10C</addressOffset>
29150 
          <size>0x20</size>
29151 
          <access>read-write</access>
29152 
          <resetValue>0x00000000</resetValue>
29153 
          <fields>
29154 
            <field>
29155 
              <name>XFRCM</name>
29156 
              <description>Transfer completed mask</description>
29157 
              <bitOffset>0</bitOffset>
29158 
              <bitWidth>1</bitWidth>
29159 
            </field>
29160 
            <field>
29161 
              <name>CHHM</name>
29162 
              <description>Channel halted mask</description>
29163 
              <bitOffset>1</bitOffset>
29164 
              <bitWidth>1</bitWidth>
29165 
            </field>
29166 
            <field>
29167 
              <name>STALLM</name>
29168 
              <description>STALL response received interrupt
29169 
              mask</description>
29170 
              <bitOffset>3</bitOffset>
29171 
              <bitWidth>1</bitWidth>
29172 
            </field>
29173 
            <field>
29174 
              <name>NAKM</name>
29175 
              <description>NAK response received interrupt
29176 
              mask</description>
29177 
              <bitOffset>4</bitOffset>
29178 
              <bitWidth>1</bitWidth>
29179 
            </field>
29180 
            <field>
29181 
              <name>ACKM</name>
29182 
              <description>ACK response received/transmitted
29183 
              interrupt mask</description>
29184 
              <bitOffset>5</bitOffset>
29185 
              <bitWidth>1</bitWidth>
29186 
            </field>
29187 
            <field>
29188 
              <name>NYET</name>
29189 
              <description>response received interrupt
29190 
              mask</description>
29191 
              <bitOffset>6</bitOffset>
29192 
              <bitWidth>1</bitWidth>
29193 
            </field>
29194 
            <field>
29195 
              <name>TXERRM</name>
29196 
              <description>Transaction error mask</description>
29197 
              <bitOffset>7</bitOffset>
29198 
              <bitWidth>1</bitWidth>
29199 
            </field>
29200 
            <field>
29201 
              <name>BBERRM</name>
29202 
              <description>Babble error mask</description>
29203 
              <bitOffset>8</bitOffset>
29204 
              <bitWidth>1</bitWidth>
29205 
            </field>
29206 
            <field>
29207 
              <name>FRMORM</name>
29208 
              <description>Frame overrun mask</description>
29209 
              <bitOffset>9</bitOffset>
29210 
              <bitWidth>1</bitWidth>
29211 
            </field>
29212 
            <field>
29213 
              <name>DTERRM</name>
29214 
              <description>Data toggle error mask</description>
29215 
              <bitOffset>10</bitOffset>
29216 
              <bitWidth>1</bitWidth>
29217 
            </field>
29218 
          </fields>
29219 
        </register>
29220 
        <register>
29221 
          <name>FS_HCINTMSK1</name>
29222 
          <displayName>FS_HCINTMSK1</displayName>
29223 
          <description>OTG_FS host channel-1 mask register
29224 
          (OTG_FS_HCINTMSK1)</description>
29225 
          <addressOffset>0x12C</addressOffset>
29226 
          <size>0x20</size>
29227 
          <access>read-write</access>
29228 
          <resetValue>0x00000000</resetValue>
29229 
          <fields>
29230 
            <field>
29231 
              <name>XFRCM</name>
29232 
              <description>Transfer completed mask</description>
29233 
              <bitOffset>0</bitOffset>
29234 
              <bitWidth>1</bitWidth>
29235 
            </field>
29236 
            <field>
29237 
              <name>CHHM</name>
29238 
              <description>Channel halted mask</description>
29239 
              <bitOffset>1</bitOffset>
29240 
              <bitWidth>1</bitWidth>
29241 
            </field>
29242 
            <field>
29243 
              <name>STALLM</name>
29244 
              <description>STALL response received interrupt
29245 
              mask</description>
29246 
              <bitOffset>3</bitOffset>
29247 
              <bitWidth>1</bitWidth>
29248 
            </field>
29249 
            <field>
29250 
              <name>NAKM</name>
29251 
              <description>NAK response received interrupt
29252 
              mask</description>
29253 
              <bitOffset>4</bitOffset>
29254 
              <bitWidth>1</bitWidth>
29255 
            </field>
29256 
            <field>
29257 
              <name>ACKM</name>
29258 
              <description>ACK response received/transmitted
29259 
              interrupt mask</description>
29260 
              <bitOffset>5</bitOffset>
29261 
              <bitWidth>1</bitWidth>
29262 
            </field>
29263 
            <field>
29264 
              <name>NYET</name>
29265 
              <description>response received interrupt
29266 
              mask</description>
29267 
              <bitOffset>6</bitOffset>
29268 
              <bitWidth>1</bitWidth>
29269 
            </field>
29270 
            <field>
29271 
              <name>TXERRM</name>
29272 
              <description>Transaction error mask</description>
29273 
              <bitOffset>7</bitOffset>
29274 
              <bitWidth>1</bitWidth>
29275 
            </field>
29276 
            <field>
29277 
              <name>BBERRM</name>
29278 
              <description>Babble error mask</description>
29279 
              <bitOffset>8</bitOffset>
29280 
              <bitWidth>1</bitWidth>
29281 
            </field>
29282 
            <field>
29283 
              <name>FRMORM</name>
29284 
              <description>Frame overrun mask</description>
29285 
              <bitOffset>9</bitOffset>
29286 
              <bitWidth>1</bitWidth>
29287 
            </field>
29288 
            <field>
29289 
              <name>DTERRM</name>
29290 
              <description>Data toggle error mask</description>
29291 
              <bitOffset>10</bitOffset>
29292 
              <bitWidth>1</bitWidth>
29293 
            </field>
29294 
          </fields>
29295 
        </register>
29296 
        <register>
29297 
          <name>FS_HCINTMSK2</name>
29298 
          <displayName>FS_HCINTMSK2</displayName>
29299 
          <description>OTG_FS host channel-2 mask register
29300 
          (OTG_FS_HCINTMSK2)</description>
29301 
          <addressOffset>0x14C</addressOffset>
29302 
          <size>0x20</size>
29303 
          <access>read-write</access>
29304 
          <resetValue>0x00000000</resetValue>
29305 
          <fields>
29306 
            <field>
29307 
              <name>XFRCM</name>
29308 
              <description>Transfer completed mask</description>
29309 
              <bitOffset>0</bitOffset>
29310 
              <bitWidth>1</bitWidth>
29311 
            </field>
29312 
            <field>
29313 
              <name>CHHM</name>
29314 
              <description>Channel halted mask</description>
29315 
              <bitOffset>1</bitOffset>
29316 
              <bitWidth>1</bitWidth>
29317 
            </field>
29318 
            <field>
29319 
              <name>STALLM</name>
29320 
              <description>STALL response received interrupt
29321 
              mask</description>
29322 
              <bitOffset>3</bitOffset>
29323 
              <bitWidth>1</bitWidth>
29324 
            </field>
29325 
            <field>
29326 
              <name>NAKM</name>
29327 
              <description>NAK response received interrupt
29328 
              mask</description>
29329 
              <bitOffset>4</bitOffset>
29330 
              <bitWidth>1</bitWidth>
29331 
            </field>
29332 
            <field>
29333 
              <name>ACKM</name>
29334 
              <description>ACK response received/transmitted
29335 
              interrupt mask</description>
29336 
              <bitOffset>5</bitOffset>
29337 
              <bitWidth>1</bitWidth>
29338 
            </field>
29339 
            <field>
29340 
              <name>NYET</name>
29341 
              <description>response received interrupt
29342 
              mask</description>
29343 
              <bitOffset>6</bitOffset>
29344 
              <bitWidth>1</bitWidth>
29345 
            </field>
29346 
            <field>
29347 
              <name>TXERRM</name>
29348 
              <description>Transaction error mask</description>
29349 
              <bitOffset>7</bitOffset>
29350 
              <bitWidth>1</bitWidth>
29351 
            </field>
29352 
            <field>
29353 
              <name>BBERRM</name>
29354 
              <description>Babble error mask</description>
29355 
              <bitOffset>8</bitOffset>
29356 
              <bitWidth>1</bitWidth>
29357 
            </field>
29358 
            <field>
29359 
              <name>FRMORM</name>
29360 
              <description>Frame overrun mask</description>
29361 
              <bitOffset>9</bitOffset>
29362 
              <bitWidth>1</bitWidth>
29363 
            </field>
29364 
            <field>
29365 
              <name>DTERRM</name>
29366 
              <description>Data toggle error mask</description>
29367 
              <bitOffset>10</bitOffset>
29368 
              <bitWidth>1</bitWidth>
29369 
            </field>
29370 
          </fields>
29371 
        </register>
29372 
        <register>
29373 
          <name>FS_HCINTMSK3</name>
29374 
          <displayName>FS_HCINTMSK3</displayName>
29375 
          <description>OTG_FS host channel-3 mask register
29376 
          (OTG_FS_HCINTMSK3)</description>
29377 
          <addressOffset>0x16C</addressOffset>
29378 
          <size>0x20</size>
29379 
          <access>read-write</access>
29380 
          <resetValue>0x00000000</resetValue>
29381 
          <fields>
29382 
            <field>
29383 
              <name>XFRCM</name>
29384 
              <description>Transfer completed mask</description>
29385 
              <bitOffset>0</bitOffset>
29386 
              <bitWidth>1</bitWidth>
29387 
            </field>
29388 
            <field>
29389 
              <name>CHHM</name>
29390 
              <description>Channel halted mask</description>
29391 
              <bitOffset>1</bitOffset>
29392 
              <bitWidth>1</bitWidth>
29393 
            </field>
29394 
            <field>
29395 
              <name>STALLM</name>
29396 
              <description>STALL response received interrupt
29397 
              mask</description>
29398 
              <bitOffset>3</bitOffset>
29399 
              <bitWidth>1</bitWidth>
29400 
            </field>
29401 
            <field>
29402 
              <name>NAKM</name>
29403 
              <description>NAK response received interrupt
29404 
              mask</description>
29405 
              <bitOffset>4</bitOffset>
29406 
              <bitWidth>1</bitWidth>
29407 
            </field>
29408 
            <field>
29409 
              <name>ACKM</name>
29410 
              <description>ACK response received/transmitted
29411 
              interrupt mask</description>
29412 
              <bitOffset>5</bitOffset>
29413 
              <bitWidth>1</bitWidth>
29414 
            </field>
29415 
            <field>
29416 
              <name>NYET</name>
29417 
              <description>response received interrupt
29418 
              mask</description>
29419 
              <bitOffset>6</bitOffset>
29420 
              <bitWidth>1</bitWidth>
29421 
            </field>
29422 
            <field>
29423 
              <name>TXERRM</name>
29424 
              <description>Transaction error mask</description>
29425 
              <bitOffset>7</bitOffset>
29426 
              <bitWidth>1</bitWidth>
29427 
            </field>
29428 
            <field>
29429 
              <name>BBERRM</name>
29430 
              <description>Babble error mask</description>
29431 
              <bitOffset>8</bitOffset>
29432 
              <bitWidth>1</bitWidth>
29433 
            </field>
29434 
            <field>
29435 
              <name>FRMORM</name>
29436 
              <description>Frame overrun mask</description>
29437 
              <bitOffset>9</bitOffset>
29438 
              <bitWidth>1</bitWidth>
29439 
            </field>
29440 
            <field>
29441 
              <name>DTERRM</name>
29442 
              <description>Data toggle error mask</description>
29443 
              <bitOffset>10</bitOffset>
29444 
              <bitWidth>1</bitWidth>
29445 
            </field>
29446 
          </fields>
29447 
        </register>
29448 
        <register>
29449 
          <name>FS_HCINTMSK4</name>
29450 
          <displayName>FS_HCINTMSK4</displayName>
29451 
          <description>OTG_FS host channel-4 mask register
29452 
          (OTG_FS_HCINTMSK4)</description>
29453 
          <addressOffset>0x18C</addressOffset>
29454 
          <size>0x20</size>
29455 
          <access>read-write</access>
29456 
          <resetValue>0x00000000</resetValue>
29457 
          <fields>
29458 
            <field>
29459 
              <name>XFRCM</name>
29460 
              <description>Transfer completed mask</description>
29461 
              <bitOffset>0</bitOffset>
29462 
              <bitWidth>1</bitWidth>
29463 
            </field>
29464 
            <field>
29465 
              <name>CHHM</name>
29466 
              <description>Channel halted mask</description>
29467 
              <bitOffset>1</bitOffset>
29468 
              <bitWidth>1</bitWidth>
29469 
            </field>
29470 
            <field>
29471 
              <name>STALLM</name>
29472 
              <description>STALL response received interrupt
29473 
              mask</description>
29474 
              <bitOffset>3</bitOffset>
29475 
              <bitWidth>1</bitWidth>
29476 
            </field>
29477 
            <field>
29478 
              <name>NAKM</name>
29479 
              <description>NAK response received interrupt
29480 
              mask</description>
29481 
              <bitOffset>4</bitOffset>
29482 
              <bitWidth>1</bitWidth>
29483 
            </field>
29484 
            <field>
29485 
              <name>ACKM</name>
29486 
              <description>ACK response received/transmitted
29487 
              interrupt mask</description>
29488 
              <bitOffset>5</bitOffset>
29489 
              <bitWidth>1</bitWidth>
29490 
            </field>
29491 
            <field>
29492 
              <name>NYET</name>
29493 
              <description>response received interrupt
29494 
              mask</description>
29495 
              <bitOffset>6</bitOffset>
29496 
              <bitWidth>1</bitWidth>
29497 
            </field>
29498 
            <field>
29499 
              <name>TXERRM</name>
29500 
              <description>Transaction error mask</description>
29501 
              <bitOffset>7</bitOffset>
29502 
              <bitWidth>1</bitWidth>
29503 
            </field>
29504 
            <field>
29505 
              <name>BBERRM</name>
29506 
              <description>Babble error mask</description>
29507 
              <bitOffset>8</bitOffset>
29508 
              <bitWidth>1</bitWidth>
29509 
            </field>
29510 
            <field>
29511 
              <name>FRMORM</name>
29512 
              <description>Frame overrun mask</description>
29513 
              <bitOffset>9</bitOffset>
29514 
              <bitWidth>1</bitWidth>
29515 
            </field>
29516 
            <field>
29517 
              <name>DTERRM</name>
29518 
              <description>Data toggle error mask</description>
29519 
              <bitOffset>10</bitOffset>
29520 
              <bitWidth>1</bitWidth>
29521 
            </field>
29522 
          </fields>
29523 
        </register>
29524 
        <register>
29525 
          <name>FS_HCINTMSK5</name>
29526 
          <displayName>FS_HCINTMSK5</displayName>
29527 
          <description>OTG_FS host channel-5 mask register
29528 
          (OTG_FS_HCINTMSK5)</description>
29529 
          <addressOffset>0x1AC</addressOffset>
29530 
          <size>0x20</size>
29531 
          <access>read-write</access>
29532 
          <resetValue>0x00000000</resetValue>
29533 
          <fields>
29534 
            <field>
29535 
              <name>XFRCM</name>
29536 
              <description>Transfer completed mask</description>
29537 
              <bitOffset>0</bitOffset>
29538 
              <bitWidth>1</bitWidth>
29539 
            </field>
29540 
            <field>
29541 
              <name>CHHM</name>
29542 
              <description>Channel halted mask</description>
29543 
              <bitOffset>1</bitOffset>
29544 
              <bitWidth>1</bitWidth>
29545 
            </field>
29546 
            <field>
29547 
              <name>STALLM</name>
29548 
              <description>STALL response received interrupt
29549 
              mask</description>
29550 
              <bitOffset>3</bitOffset>
29551 
              <bitWidth>1</bitWidth>
29552 
            </field>
29553 
            <field>
29554 
              <name>NAKM</name>
29555 
              <description>NAK response received interrupt
29556 
              mask</description>
29557 
              <bitOffset>4</bitOffset>
29558 
              <bitWidth>1</bitWidth>
29559 
            </field>
29560 
            <field>
29561 
              <name>ACKM</name>
29562 
              <description>ACK response received/transmitted
29563 
              interrupt mask</description>
29564 
              <bitOffset>5</bitOffset>
29565 
              <bitWidth>1</bitWidth>
29566 
            </field>
29567 
            <field>
29568 
              <name>NYET</name>
29569 
              <description>response received interrupt
29570 
              mask</description>
29571 
              <bitOffset>6</bitOffset>
29572 
              <bitWidth>1</bitWidth>
29573 
            </field>
29574 
            <field>
29575 
              <name>TXERRM</name>
29576 
              <description>Transaction error mask</description>
29577 
              <bitOffset>7</bitOffset>
29578 
              <bitWidth>1</bitWidth>
29579 
            </field>
29580 
            <field>
29581 
              <name>BBERRM</name>
29582 
              <description>Babble error mask</description>
29583 
              <bitOffset>8</bitOffset>
29584 
              <bitWidth>1</bitWidth>
29585 
            </field>
29586 
            <field>
29587 
              <name>FRMORM</name>
29588 
              <description>Frame overrun mask</description>
29589 
              <bitOffset>9</bitOffset>
29590 
              <bitWidth>1</bitWidth>
29591 
            </field>
29592 
            <field>
29593 
              <name>DTERRM</name>
29594 
              <description>Data toggle error mask</description>
29595 
              <bitOffset>10</bitOffset>
29596 
              <bitWidth>1</bitWidth>
29597 
            </field>
29598 
          </fields>
29599 
        </register>
29600 
        <register>
29601 
          <name>FS_HCINTMSK6</name>
29602 
          <displayName>FS_HCINTMSK6</displayName>
29603 
          <description>OTG_FS host channel-6 mask register
29604 
          (OTG_FS_HCINTMSK6)</description>
29605 
          <addressOffset>0x1CC</addressOffset>
29606 
          <size>0x20</size>
29607 
          <access>read-write</access>
29608 
          <resetValue>0x00000000</resetValue>
29609 
          <fields>
29610 
            <field>
29611 
              <name>XFRCM</name>
29612 
              <description>Transfer completed mask</description>
29613 
              <bitOffset>0</bitOffset>
29614 
              <bitWidth>1</bitWidth>
29615 
            </field>
29616 
            <field>
29617 
              <name>CHHM</name>
29618 
              <description>Channel halted mask</description>
29619 
              <bitOffset>1</bitOffset>
29620 
              <bitWidth>1</bitWidth>
29621 
            </field>
29622 
            <field>
29623 
              <name>STALLM</name>
29624 
              <description>STALL response received interrupt
29625 
              mask</description>
29626 
              <bitOffset>3</bitOffset>
29627 
              <bitWidth>1</bitWidth>
29628 
            </field>
29629 
            <field>
29630 
              <name>NAKM</name>
29631 
              <description>NAK response received interrupt
29632 
              mask</description>
29633 
              <bitOffset>4</bitOffset>
29634 
              <bitWidth>1</bitWidth>
29635 
            </field>
29636 
            <field>
29637 
              <name>ACKM</name>
29638 
              <description>ACK response received/transmitted
29639 
              interrupt mask</description>
29640 
              <bitOffset>5</bitOffset>
29641 
              <bitWidth>1</bitWidth>
29642 
            </field>
29643 
            <field>
29644 
              <name>NYET</name>
29645 
              <description>response received interrupt
29646 
              mask</description>
29647 
              <bitOffset>6</bitOffset>
29648 
              <bitWidth>1</bitWidth>
29649 
            </field>
29650 
            <field>
29651 
              <name>TXERRM</name>
29652 
              <description>Transaction error mask</description>
29653 
              <bitOffset>7</bitOffset>
29654 
              <bitWidth>1</bitWidth>
29655 
            </field>
29656 
            <field>
29657 
              <name>BBERRM</name>
29658 
              <description>Babble error mask</description>
29659 
              <bitOffset>8</bitOffset>
29660 
              <bitWidth>1</bitWidth>
29661 
            </field>
29662 
            <field>
29663 
              <name>FRMORM</name>
29664 
              <description>Frame overrun mask</description>
29665 
              <bitOffset>9</bitOffset>
29666 
              <bitWidth>1</bitWidth>
29667 
            </field>
29668 
            <field>
29669 
              <name>DTERRM</name>
29670 
              <description>Data toggle error mask</description>
29671 
              <bitOffset>10</bitOffset>
29672 
              <bitWidth>1</bitWidth>
29673 
            </field>
29674 
          </fields>
29675 
        </register>
29676 
        <register>
29677 
          <name>FS_HCINTMSK7</name>
29678 
          <displayName>FS_HCINTMSK7</displayName>
29679 
          <description>OTG_FS host channel-7 mask register
29680 
          (OTG_FS_HCINTMSK7)</description>
29681 
          <addressOffset>0x1EC</addressOffset>
29682 
          <size>0x20</size>
29683 
          <access>read-write</access>
29684 
          <resetValue>0x00000000</resetValue>
29685 
          <fields>
29686 
            <field>
29687 
              <name>XFRCM</name>
29688 
              <description>Transfer completed mask</description>
29689 
              <bitOffset>0</bitOffset>
29690 
              <bitWidth>1</bitWidth>
29691 
            </field>
29692 
            <field>
29693 
              <name>CHHM</name>
29694 
              <description>Channel halted mask</description>
29695 
              <bitOffset>1</bitOffset>
29696 
              <bitWidth>1</bitWidth>
29697 
            </field>
29698 
            <field>
29699 
              <name>STALLM</name>
29700 
              <description>STALL response received interrupt
29701 
              mask</description>
29702 
              <bitOffset>3</bitOffset>
29703 
              <bitWidth>1</bitWidth>
29704 
            </field>
29705 
            <field>
29706 
              <name>NAKM</name>
29707 
              <description>NAK response received interrupt
29708 
              mask</description>
29709 
              <bitOffset>4</bitOffset>
29710 
              <bitWidth>1</bitWidth>
29711 
            </field>
29712 
            <field>
29713 
              <name>ACKM</name>
29714 
              <description>ACK response received/transmitted
29715 
              interrupt mask</description>
29716 
              <bitOffset>5</bitOffset>
29717 
              <bitWidth>1</bitWidth>
29718 
            </field>
29719 
            <field>
29720 
              <name>NYET</name>
29721 
              <description>response received interrupt
29722 
              mask</description>
29723 
              <bitOffset>6</bitOffset>
29724 
              <bitWidth>1</bitWidth>
29725 
            </field>
29726 
            <field>
29727 
              <name>TXERRM</name>
29728 
              <description>Transaction error mask</description>
29729 
              <bitOffset>7</bitOffset>
29730 
              <bitWidth>1</bitWidth>
29731 
            </field>
29732 
            <field>
29733 
              <name>BBERRM</name>
29734 
              <description>Babble error mask</description>
29735 
              <bitOffset>8</bitOffset>
29736 
              <bitWidth>1</bitWidth>
29737 
            </field>
29738 
            <field>
29739 
              <name>FRMORM</name>
29740 
              <description>Frame overrun mask</description>
29741 
              <bitOffset>9</bitOffset>
29742 
              <bitWidth>1</bitWidth>
29743 
            </field>
29744 
            <field>
29745 
              <name>DTERRM</name>
29746 
              <description>Data toggle error mask</description>
29747 
              <bitOffset>10</bitOffset>
29748 
              <bitWidth>1</bitWidth>
29749 
            </field>
29750 
          </fields>
29751 
        </register>
29752 
        <register>
29753 
          <name>FS_HCTSIZ0</name>
29754 
          <displayName>FS_HCTSIZ0</displayName>
29755 
          <description>OTG_FS host channel-0 transfer size
29756 
          register</description>
29757 
          <addressOffset>0x110</addressOffset>
29758 
          <size>0x20</size>
29759 
          <access>read-write</access>
29760 
          <resetValue>0x00000000</resetValue>
29761 
          <fields>
29762 
            <field>
29763 
              <name>XFRSIZ</name>
29764 
              <description>Transfer size</description>
29765 
              <bitOffset>0</bitOffset>
29766 
              <bitWidth>19</bitWidth>
29767 
            </field>
29768 
            <field>
29769 
              <name>PKTCNT</name>
29770 
              <description>Packet count</description>
29771 
              <bitOffset>19</bitOffset>
29772 
              <bitWidth>10</bitWidth>
29773 
            </field>
29774 
            <field>
29775 
              <name>DPID</name>
29776 
              <description>Data PID</description>
29777 
              <bitOffset>29</bitOffset>
29778 
              <bitWidth>2</bitWidth>
29779 
            </field>
29780 
          </fields>
29781 
        </register>
29782 
        <register>
29783 
          <name>FS_HCTSIZ1</name>
29784 
          <displayName>FS_HCTSIZ1</displayName>
29785 
          <description>OTG_FS host channel-1 transfer size
29786 
          register</description>
29787 
          <addressOffset>0x130</addressOffset>
29788 
          <size>0x20</size>
29789 
          <access>read-write</access>
29790 
          <resetValue>0x00000000</resetValue>
29791 
          <fields>
29792 
            <field>
29793 
              <name>XFRSIZ</name>
29794 
              <description>Transfer size</description>
29795 
              <bitOffset>0</bitOffset>
29796 
              <bitWidth>19</bitWidth>
29797 
            </field>
29798 
            <field>
29799 
              <name>PKTCNT</name>
29800 
              <description>Packet count</description>
29801 
              <bitOffset>19</bitOffset>
29802 
              <bitWidth>10</bitWidth>
29803 
            </field>
29804 
            <field>
29805 
              <name>DPID</name>
29806 
              <description>Data PID</description>
29807 
              <bitOffset>29</bitOffset>
29808 
              <bitWidth>2</bitWidth>
29809 
            </field>
29810 
          </fields>
29811 
        </register>
29812 
        <register>
29813 
          <name>FS_HCTSIZ2</name>
29814 
          <displayName>FS_HCTSIZ2</displayName>
29815 
          <description>OTG_FS host channel-2 transfer size
29816 
          register</description>
29817 
          <addressOffset>0x150</addressOffset>
29818 
          <size>0x20</size>
29819 
          <access>read-write</access>
29820 
          <resetValue>0x00000000</resetValue>
29821 
          <fields>
29822 
            <field>
29823 
              <name>XFRSIZ</name>
29824 
              <description>Transfer size</description>
29825 
              <bitOffset>0</bitOffset>
29826 
              <bitWidth>19</bitWidth>
29827 
            </field>
29828 
            <field>
29829 
              <name>PKTCNT</name>
29830 
              <description>Packet count</description>
29831 
              <bitOffset>19</bitOffset>
29832 
              <bitWidth>10</bitWidth>
29833 
            </field>
29834 
            <field>
29835 
              <name>DPID</name>
29836 
              <description>Data PID</description>
29837 
              <bitOffset>29</bitOffset>
29838 
              <bitWidth>2</bitWidth>
29839 
            </field>
29840 
          </fields>
29841 
        </register>
29842 
        <register>
29843 
          <name>FS_HCTSIZ3</name>
29844 
          <displayName>FS_HCTSIZ3</displayName>
29845 
          <description>OTG_FS host channel-3 transfer size
29846 
          register</description>
29847 
          <addressOffset>0x170</addressOffset>
29848 
          <size>0x20</size>
29849 
          <access>read-write</access>
29850 
          <resetValue>0x00000000</resetValue>
29851 
          <fields>
29852 
            <field>
29853 
              <name>XFRSIZ</name>
29854 
              <description>Transfer size</description>
29855 
              <bitOffset>0</bitOffset>
29856 
              <bitWidth>19</bitWidth>
29857 
            </field>
29858 
            <field>
29859 
              <name>PKTCNT</name>
29860 
              <description>Packet count</description>
29861 
              <bitOffset>19</bitOffset>
29862 
              <bitWidth>10</bitWidth>
29863 
            </field>
29864 
            <field>
29865 
              <name>DPID</name>
29866 
              <description>Data PID</description>
29867 
              <bitOffset>29</bitOffset>
29868 
              <bitWidth>2</bitWidth>
29869 
            </field>
29870 
          </fields>
29871 
        </register>
29872 
        <register>
29873 
          <name>FS_HCTSIZ4</name>
29874 
          <displayName>FS_HCTSIZ4</displayName>
29875 
          <description>OTG_FS host channel-x transfer size
29876 
          register</description>
29877 
          <addressOffset>0x190</addressOffset>
29878 
          <size>0x20</size>
29879 
          <access>read-write</access>
29880 
          <resetValue>0x00000000</resetValue>
29881 
          <fields>
29882 
            <field>
29883 
              <name>XFRSIZ</name>
29884 
              <description>Transfer size</description>
29885 
              <bitOffset>0</bitOffset>
29886 
              <bitWidth>19</bitWidth>
29887 
            </field>
29888 
            <field>
29889 
              <name>PKTCNT</name>
29890 
              <description>Packet count</description>
29891 
              <bitOffset>19</bitOffset>
29892 
              <bitWidth>10</bitWidth>
29893 
            </field>
29894 
            <field>
29895 
              <name>DPID</name>
29896 
              <description>Data PID</description>
29897 
              <bitOffset>29</bitOffset>
29898 
              <bitWidth>2</bitWidth>
29899 
            </field>
29900 
          </fields>
29901 
        </register>
29902 
        <register>
29903 
          <name>FS_HCTSIZ5</name>
29904 
          <displayName>FS_HCTSIZ5</displayName>
29905 
          <description>OTG_FS host channel-5 transfer size
29906 
          register</description>
29907 
          <addressOffset>0x1B0</addressOffset>
29908 
          <size>0x20</size>
29909 
          <access>read-write</access>
29910 
          <resetValue>0x00000000</resetValue>
29911 
          <fields>
29912 
            <field>
29913 
              <name>XFRSIZ</name>
29914 
              <description>Transfer size</description>
29915 
              <bitOffset>0</bitOffset>
29916 
              <bitWidth>19</bitWidth>
29917 
            </field>
29918 
            <field>
29919 
              <name>PKTCNT</name>
29920 
              <description>Packet count</description>
29921 
              <bitOffset>19</bitOffset>
29922 
              <bitWidth>10</bitWidth>
29923 
            </field>
29924 
            <field>
29925 
              <name>DPID</name>
29926 
              <description>Data PID</description>
29927 
              <bitOffset>29</bitOffset>
29928 
              <bitWidth>2</bitWidth>
29929 
            </field>
29930 
          </fields>
29931 
        </register>
29932 
        <register>
29933 
          <name>FS_HCTSIZ6</name>
29934 
          <displayName>FS_HCTSIZ6</displayName>
29935 
          <description>OTG_FS host channel-6 transfer size
29936 
          register</description>
29937 
          <addressOffset>0x1D0</addressOffset>
29938 
          <size>0x20</size>
29939 
          <access>read-write</access>
29940 
          <resetValue>0x00000000</resetValue>
29941 
          <fields>
29942 
            <field>
29943 
              <name>XFRSIZ</name>
29944 
              <description>Transfer size</description>
29945 
              <bitOffset>0</bitOffset>
29946 
              <bitWidth>19</bitWidth>
29947 
            </field>
29948 
            <field>
29949 
              <name>PKTCNT</name>
29950 
              <description>Packet count</description>
29951 
              <bitOffset>19</bitOffset>
29952 
              <bitWidth>10</bitWidth>
29953 
            </field>
29954 
            <field>
29955 
              <name>DPID</name>
29956 
              <description>Data PID</description>
29957 
              <bitOffset>29</bitOffset>
29958 
              <bitWidth>2</bitWidth>
29959 
            </field>
29960 
          </fields>
29961 
        </register>
29962 
        <register>
29963 
          <name>FS_HCTSIZ7</name>
29964 
          <displayName>FS_HCTSIZ7</displayName>
29965 
          <description>OTG_FS host channel-7 transfer size
29966 
          register</description>
29967 
          <addressOffset>0x1F0</addressOffset>
29968 
          <size>0x20</size>
29969 
          <access>read-write</access>
29970 
          <resetValue>0x00000000</resetValue>
29971 
          <fields>
29972 
            <field>
29973 
              <name>XFRSIZ</name>
29974 
              <description>Transfer size</description>
29975 
              <bitOffset>0</bitOffset>
29976 
              <bitWidth>19</bitWidth>
29977 
            </field>
29978 
            <field>
29979 
              <name>PKTCNT</name>
29980 
              <description>Packet count</description>
29981 
              <bitOffset>19</bitOffset>
29982 
              <bitWidth>10</bitWidth>
29983 
            </field>
29984 
            <field>
29985 
              <name>DPID</name>
29986 
              <description>Data PID</description>
29987 
              <bitOffset>29</bitOffset>
29988 
              <bitWidth>2</bitWidth>
29989 
            </field>
29990 
          </fields>
29991 
        </register>
29992 
      </registers>
29993 
    </peripheral>
29994 
    <peripheral>
29995 
      <name>OTG_FS_PWRCLK</name>
29996 
      <description>USB on the go full speed</description>
29997 
      <groupName>USB_OTG_FS</groupName>
29998 
      <baseAddress>0x50000E00</baseAddress>
29999 
      <addressBlock>
30000 
        <offset>0x0</offset>
30001 
        <size>0x400</size>
30002 
        <usage>registers</usage>
30003 
      </addressBlock>
30004 
      <registers>
30005 
        <register>
30006 
          <name>FS_PCGCCTL</name>
30007 
          <displayName>FS_PCGCCTL</displayName>
30008 
          <description>OTG_FS power and clock gating control
30009 
          register</description>
30010 
          <addressOffset>0x0</addressOffset>
30011 
          <size>0x20</size>
30012 
          <access>read-write</access>
30013 
          <resetValue>0x00000000</resetValue>
30014 
          <fields>
30015 
            <field>
30016 
              <name>STPPCLK</name>
30017 
              <description>Stop PHY clock</description>
30018 
              <bitOffset>0</bitOffset>
30019 
              <bitWidth>1</bitWidth>
30020 
            </field>
30021 
            <field>
30022 
              <name>GATEHCLK</name>
30023 
              <description>Gate HCLK</description>
30024 
              <bitOffset>1</bitOffset>
30025 
              <bitWidth>1</bitWidth>
30026 
            </field>
30027 
            <field>
30028 
              <name>PHYSUSP</name>
30029 
              <description>PHY Suspended</description>
30030 
              <bitOffset>4</bitOffset>
30031 
              <bitWidth>1</bitWidth>
30032 
            </field>
30033 
          </fields>
30034 
        </register>
30035 
      </registers>
30036 
    </peripheral>
30037 
    <peripheral>
30038 
      <name>ETHERNET_MMC</name>
30039 
      <description>Ethernet: MAC management counters</description>
30040 
      <groupName>ETHERNET</groupName>
30041 
      <baseAddress>0x40028100</baseAddress>
30042 
      <addressBlock>
30043 
        <offset>0x0</offset>
30044 
        <size>0x400</size>
30045 
        <usage>registers</usage>
30046 
      </addressBlock>
30047 
      <registers>
30048 
        <register>
30049 
          <name>MMCCR</name>
30050 
          <displayName>MMCCR</displayName>
30051 
          <description>Ethernet MMC control register
30052 
          (ETH_MMCCR)</description>
30053 
          <addressOffset>0x0</addressOffset>
30054 
          <size>0x20</size>
30055 
          <access>read-write</access>
30056 
          <resetValue>0x00000000</resetValue>
30057 
          <fields>
30058 
            <field>
30059 
              <name>CR</name>
30060 
              <description>Counter reset</description>
30061 
              <bitOffset>0</bitOffset>
30062 
              <bitWidth>1</bitWidth>
30063 
            </field>
30064 
            <field>
30065 
              <name>CSR</name>
30066 
              <description>Counter stop rollover</description>
30067 
              <bitOffset>1</bitOffset>
30068 
              <bitWidth>1</bitWidth>
30069 
            </field>
30070 
            <field>
30071 
              <name>ROR</name>
30072 
              <description>Reset on read</description>
30073 
              <bitOffset>2</bitOffset>
30074 
              <bitWidth>1</bitWidth>
30075 
            </field>
30076 
            <field>
30077 
              <name>MCF</name>
30078 
              <description>MMC counter freeze</description>
30079 
              <bitOffset>31</bitOffset>
30080 
              <bitWidth>1</bitWidth>
30081 
            </field>
30082 
          </fields>
30083 
        </register>
30084 
        <register>
30085 
          <name>MMCRIR</name>
30086 
          <displayName>MMCRIR</displayName>
30087 
          <description>Ethernet MMC receive interrupt register
30088 
          (ETH_MMCRIR)</description>
30089 
          <addressOffset>0x4</addressOffset>
30090 
          <size>0x20</size>
30091 
          <access>read-write</access>
30092 
          <resetValue>0x00000000</resetValue>
30093 
          <fields>
30094 
            <field>
30095 
              <name>RFCES</name>
30096 
              <description>Received frames CRC error
30097 
              status</description>
30098 
              <bitOffset>5</bitOffset>
30099 
              <bitWidth>1</bitWidth>
30100 
            </field>
30101 
            <field>
30102 
              <name>RFAES</name>
30103 
              <description>Received frames alignment error
30104 
              status</description>
30105 
              <bitOffset>6</bitOffset>
30106 
              <bitWidth>1</bitWidth>
30107 
            </field>
30108 
            <field>
30109 
              <name>RGUFS</name>
30110 
              <description>Received Good Unicast Frames
30111 
              Status</description>
30112 
              <bitOffset>17</bitOffset>
30113 
              <bitWidth>1</bitWidth>
30114 
            </field>
30115 
          </fields>
30116 
        </register>
30117 
        <register>
30118 
          <name>MMCTIR</name>
30119 
          <displayName>MMCTIR</displayName>
30120 
          <description>Ethernet MMC transmit interrupt register
30121 
          (ETH_MMCTIR)</description>
30122 
          <addressOffset>0x8</addressOffset>
30123 
          <size>0x20</size>
30124 
          <access>read-write</access>
30125 
          <resetValue>0x00000000</resetValue>
30126 
          <fields>
30127 
            <field>
30128 
              <name>TGFSCS</name>
30129 
              <description>Transmitted good frames single collision
30130 
              status</description>
30131 
              <bitOffset>14</bitOffset>
30132 
              <bitWidth>1</bitWidth>
30133 
            </field>
30134 
            <field>
30135 
              <name>TGFMSCS</name>
30136 
              <description>Transmitted good frames more single
30137 
              collision status</description>
30138 
              <bitOffset>15</bitOffset>
30139 
              <bitWidth>1</bitWidth>
30140 
            </field>
30141 
            <field>
30142 
              <name>TGFS</name>
30143 
              <description>Transmitted good frames
30144 
              status</description>
30145 
              <bitOffset>21</bitOffset>
30146 
              <bitWidth>1</bitWidth>
30147 
            </field>
30148 
          </fields>
30149 
        </register>
30150 
        <register>
30151 
          <name>MMCRIMR</name>
30152 
          <displayName>MMCRIMR</displayName>
30153 
          <description>Ethernet MMC receive interrupt mask register
30154 
          (ETH_MMCRIMR)</description>
30155 
          <addressOffset>0xC</addressOffset>
30156 
          <size>0x20</size>
30157 
          <access>read-write</access>
30158 
          <resetValue>0x00000000</resetValue>
30159 
          <fields>
30160 
            <field>
30161 
              <name>RFCEM</name>
30162 
              <description>Received frame CRC error
30163 
              mask</description>
30164 
              <bitOffset>5</bitOffset>
30165 
              <bitWidth>1</bitWidth>
30166 
            </field>
30167 
            <field>
30168 
              <name>RFAEM</name>
30169 
              <description>Received frames alignment error
30170 
              mask</description>
30171 
              <bitOffset>6</bitOffset>
30172 
              <bitWidth>1</bitWidth>
30173 
            </field>
30174 
            <field>
30175 
              <name>RGUFM</name>
30176 
              <description>Received good unicast frames
30177 
              mask</description>
30178 
              <bitOffset>17</bitOffset>
30179 
              <bitWidth>1</bitWidth>
30180 
            </field>
30181 
          </fields>
30182 
        </register>
30183 
        <register>
30184 
          <name>MMCTIMR</name>
30185 
          <displayName>MMCTIMR</displayName>
30186 
          <description>Ethernet MMC transmit interrupt mask
30187 
          register (ETH_MMCTIMR)</description>
30188 
          <addressOffset>0x10</addressOffset>
30189 
          <size>0x20</size>
30190 
          <access>read-write</access>
30191 
          <resetValue>0x00000000</resetValue>
30192 
          <fields>
30193 
            <field>
30194 
              <name>TGFSCM</name>
30195 
              <description>Transmitted good frames single collision
30196 
              mask</description>
30197 
              <bitOffset>14</bitOffset>
30198 
              <bitWidth>1</bitWidth>
30199 
            </field>
30200 
            <field>
30201 
              <name>TGFMSCM</name>
30202 
              <description>Transmitted good frames more single
30203 
              collision mask</description>
30204 
              <bitOffset>15</bitOffset>
30205 
              <bitWidth>1</bitWidth>
30206 
            </field>
30207 
            <field>
30208 
              <name>TGFM</name>
30209 
              <description>Transmitted good frames
30210 
              mask</description>
30211 
              <bitOffset>21</bitOffset>
30212 
              <bitWidth>1</bitWidth>
30213 
            </field>
30214 
          </fields>
30215 
        </register>
30216 
        <register>
30217 
          <name>MMCTGFSCCR</name>
30218 
          <displayName>MMCTGFSCCR</displayName>
30219 
          <description>Ethernet MMC transmitted good frames after a
30220 
          single collision counter</description>
30221 
          <addressOffset>0x4C</addressOffset>
30222 
          <size>0x20</size>
30223 
          <access>read-only</access>
30224 
          <resetValue>0x00000000</resetValue>
30225 
          <fields>
30226 
            <field>
30227 
              <name>TGFSCC</name>
30228 
              <description>Transmitted good frames after a single
30229 
              collision counter</description>
30230 
              <bitOffset>0</bitOffset>
30231 
              <bitWidth>32</bitWidth>
30232 
            </field>
30233 
          </fields>
30234 
        </register>
30235 
        <register>
30236 
          <name>MMCTGFMSCCR</name>
30237 
          <displayName>MMCTGFMSCCR</displayName>
30238 
          <description>Ethernet MMC transmitted good frames after
30239 
          more than a single collision</description>
30240 
          <addressOffset>0x50</addressOffset>
30241 
          <size>0x20</size>
30242 
          <access>read-only</access>
30243 
          <resetValue>0x00000000</resetValue>
30244 
          <fields>
30245 
            <field>
30246 
              <name>TGFMSCC</name>
30247 
              <description>Transmitted good frames after more than
30248 
              a single collision counter</description>
30249 
              <bitOffset>0</bitOffset>
30250 
              <bitWidth>32</bitWidth>
30251 
            </field>
30252 
          </fields>
30253 
        </register>
30254 
        <register>
30255 
          <name>MMCTGFCR</name>
30256 
          <displayName>MMCTGFCR</displayName>
30257 
          <description>Ethernet MMC transmitted good frames counter
30258 
          register</description>
30259 
          <addressOffset>0x68</addressOffset>
30260 
          <size>0x20</size>
30261 
          <access>read-only</access>
30262 
          <resetValue>0x00000000</resetValue>
30263 
          <fields>
30264 
            <field>
30265 
              <name>TGFC</name>
30266 
              <description>Transmitted good frames
30267 
              counter</description>
30268 
              <bitOffset>0</bitOffset>
30269 
              <bitWidth>32</bitWidth>
30270 
            </field>
30271 
          </fields>
30272 
        </register>
30273 
        <register>
30274 
          <name>MMCRFCECR</name>
30275 
          <displayName>MMCRFCECR</displayName>
30276 
          <description>Ethernet MMC received frames with CRC error
30277 
          counter register</description>
30278 
          <addressOffset>0x94</addressOffset>
30279 
          <size>0x20</size>
30280 
          <access>read-only</access>
30281 
          <resetValue>0x00000000</resetValue>
30282 
          <fields>
30283 
            <field>
30284 
              <name>RFCFC</name>
30285 
              <description>Received frames with CRC error
30286 
              counter</description>
30287 
              <bitOffset>0</bitOffset>
30288 
              <bitWidth>32</bitWidth>
30289 
            </field>
30290 
          </fields>
30291 
        </register>
30292 
        <register>
30293 
          <name>MMCRFAECR</name>
30294 
          <displayName>MMCRFAECR</displayName>
30295 
          <description>Ethernet MMC received frames with alignment
30296 
          error counter register</description>
30297 
          <addressOffset>0x98</addressOffset>
30298 
          <size>0x20</size>
30299 
          <access>read-only</access>
30300 
          <resetValue>0x00000000</resetValue>
30301 
          <fields>
30302 
            <field>
30303 
              <name>RFAEC</name>
30304 
              <description>Received frames with alignment error
30305 
              counter</description>
30306 
              <bitOffset>0</bitOffset>
30307 
              <bitWidth>32</bitWidth>
30308 
            </field>
30309 
          </fields>
30310 
        </register>
30311 
        <register>
30312 
          <name>MMCRGUFCR</name>
30313 
          <displayName>MMCRGUFCR</displayName>
30314 
          <description>MMC received good unicast frames counter
30315 
          register</description>
30316 
          <addressOffset>0xC4</addressOffset>
30317 
          <size>0x20</size>
30318 
          <access>read-only</access>
30319 
          <resetValue>0x00000000</resetValue>
30320 
          <fields>
30321 
            <field>
30322 
              <name>RGUFC</name>
30323 
              <description>Received good unicast frames
30324 
              counter</description>
30325 
              <bitOffset>0</bitOffset>
30326 
              <bitWidth>32</bitWidth>
30327 
            </field>
30328 
          </fields>
30329 
        </register>
30330 
      </registers>
30331 
    </peripheral>
30332 
    <peripheral>
30333 
      <name>ETHERNET_MAC</name>
30334 
      <description>Ethernet: media access control</description>
30335 
      <groupName>ETHERNET</groupName>
30336 
      <baseAddress>0x40028000</baseAddress>
30337 
      <addressBlock>
30338 
        <offset>0x0</offset>
30339 
        <size>0x61</size>
30340 
        <usage>registers</usage>
30341 
      </addressBlock>
30342 
      <registers>
30343 
        <register>
30344 
          <name>MACCR</name>
30345 
          <displayName>MACCR</displayName>
30346 
          <description>Ethernet MAC configuration register
30347 
          (ETH_MACCR)</description>
30348 
          <addressOffset>0x0</addressOffset>
30349 
          <size>0x20</size>
30350 
          <access>read-write</access>
30351 
          <resetValue>0x00008000</resetValue>
30352 
          <fields>
30353 
            <field>
30354 
              <name>RE</name>
30355 
              <description>Receiver enable</description>
30356 
              <bitOffset>2</bitOffset>
30357 
              <bitWidth>1</bitWidth>
30358 
            </field>
30359 
            <field>
30360 
              <name>TE</name>
30361 
              <description>Transmitter enable</description>
30362 
              <bitOffset>3</bitOffset>
30363 
              <bitWidth>1</bitWidth>
30364 
            </field>
30365 
            <field>
30366 
              <name>DC</name>
30367 
              <description>Deferral check</description>
30368 
              <bitOffset>4</bitOffset>
30369 
              <bitWidth>1</bitWidth>
30370 
            </field>
30371 
            <field>
30372 
              <name>BL</name>
30373 
              <description>Back-off limit</description>
30374 
              <bitOffset>5</bitOffset>
30375 
              <bitWidth>2</bitWidth>
30376 
            </field>
30377 
            <field>
30378 
              <name>APCS</name>
30379 
              <description>Automatic pad/CRC
30380 
              stripping</description>
30381 
              <bitOffset>7</bitOffset>
30382 
              <bitWidth>1</bitWidth>
30383 
            </field>
30384 
            <field>
30385 
              <name>RD</name>
30386 
              <description>Retry disable</description>
30387 
              <bitOffset>9</bitOffset>
30388 
              <bitWidth>1</bitWidth>
30389 
            </field>
30390 
            <field>
30391 
              <name>IPCO</name>
30392 
              <description>IPv4 checksum offload</description>
30393 
              <bitOffset>10</bitOffset>
30394 
              <bitWidth>1</bitWidth>
30395 
            </field>
30396 
            <field>
30397 
              <name>DM</name>
30398 
              <description>Duplex mode</description>
30399 
              <bitOffset>11</bitOffset>
30400 
              <bitWidth>1</bitWidth>
30401 
            </field>
30402 
            <field>
30403 
              <name>LM</name>
30404 
              <description>Loopback mode</description>
30405 
              <bitOffset>12</bitOffset>
30406 
              <bitWidth>1</bitWidth>
30407 
            </field>
30408 
            <field>
30409 
              <name>ROD</name>
30410 
              <description>Receive own disable</description>
30411 
              <bitOffset>13</bitOffset>
30412 
              <bitWidth>1</bitWidth>
30413 
            </field>
30414 
            <field>
30415 
              <name>FES</name>
30416 
              <description>Fast Ethernet speed</description>
30417 
              <bitOffset>14</bitOffset>
30418 
              <bitWidth>1</bitWidth>
30419 
            </field>
30420 
            <field>
30421 
              <name>CSD</name>
30422 
              <description>Carrier sense disable</description>
30423 
              <bitOffset>16</bitOffset>
30424 
              <bitWidth>1</bitWidth>
30425 
            </field>
30426 
            <field>
30427 
              <name>IFG</name>
30428 
              <description>Interframe gap</description>
30429 
              <bitOffset>17</bitOffset>
30430 
              <bitWidth>3</bitWidth>
30431 
            </field>
30432 
            <field>
30433 
              <name>JD</name>
30434 
              <description>Jabber disable</description>
30435 
              <bitOffset>22</bitOffset>
30436 
              <bitWidth>1</bitWidth>
30437 
            </field>
30438 
            <field>
30439 
              <name>WD</name>
30440 
              <description>Watchdog disable</description>
30441 
              <bitOffset>23</bitOffset>
30442 
              <bitWidth>1</bitWidth>
30443 
            </field>
30444 
          </fields>
30445 
        </register>
30446 
        <register>
30447 
          <name>MACFFR</name>
30448 
          <displayName>MACFFR</displayName>
30449 
          <description>Ethernet MAC frame filter register
30450 
          (ETH_MACCFFR)</description>
30451 
          <addressOffset>0x4</addressOffset>
30452 
          <size>0x20</size>
30453 
          <access>read-write</access>
30454 
          <resetValue>0x00000000</resetValue>
30455 
          <fields>
30456 
            <field>
30457 
              <name>PM</name>
30458 
              <description>Promiscuous mode</description>
30459 
              <bitOffset>0</bitOffset>
30460 
              <bitWidth>1</bitWidth>
30461 
            </field>
30462 
            <field>
30463 
              <name>HU</name>
30464 
              <description>Hash unicast</description>
30465 
              <bitOffset>1</bitOffset>
30466 
              <bitWidth>1</bitWidth>
30467 
            </field>
30468 
            <field>
30469 
              <name>HM</name>
30470 
              <description>Hash multicast</description>
30471 
              <bitOffset>2</bitOffset>
30472 
              <bitWidth>1</bitWidth>
30473 
            </field>
30474 
            <field>
30475 
              <name>DAIF</name>
30476 
              <description>Destination address inverse
30477 
              filtering</description>
30478 
              <bitOffset>3</bitOffset>
30479 
              <bitWidth>1</bitWidth>
30480 
            </field>
30481 
            <field>
30482 
              <name>PAM</name>
30483 
              <description>Pass all multicast</description>
30484 
              <bitOffset>4</bitOffset>
30485 
              <bitWidth>1</bitWidth>
30486 
            </field>
30487 
            <field>
30488 
              <name>BFD</name>
30489 
              <description>Broadcast frames disable</description>
30490 
              <bitOffset>5</bitOffset>
30491 
              <bitWidth>1</bitWidth>
30492 
            </field>
30493 
            <field>
30494 
              <name>PCF</name>
30495 
              <description>Pass control frames</description>
30496 
              <bitOffset>6</bitOffset>
30497 
              <bitWidth>2</bitWidth>
30498 
            </field>
30499 
            <field>
30500 
              <name>SAIF</name>
30501 
              <description>Source address inverse
30502 
              filtering</description>
30503 
              <bitOffset>8</bitOffset>
30504 
              <bitWidth>1</bitWidth>
30505 
            </field>
30506 
            <field>
30507 
              <name>SAF</name>
30508 
              <description>Source address filter</description>
30509 
              <bitOffset>9</bitOffset>
30510 
              <bitWidth>1</bitWidth>
30511 
            </field>
30512 
            <field>
30513 
              <name>HPF</name>
30514 
              <description>Hash or perfect filter</description>
30515 
              <bitOffset>10</bitOffset>
30516 
              <bitWidth>1</bitWidth>
30517 
            </field>
30518 
            <field>
30519 
              <name>RA</name>
30520 
              <description>Receive all</description>
30521 
              <bitOffset>31</bitOffset>
30522 
              <bitWidth>1</bitWidth>
30523 
            </field>
30524 
          </fields>
30525 
        </register>
30526 
        <register>
30527 
          <name>MACHTHR</name>
30528 
          <displayName>MACHTHR</displayName>
30529 
          <description>Ethernet MAC hash table high
30530 
          register</description>
30531 
          <addressOffset>0x8</addressOffset>
30532 
          <size>0x20</size>
30533 
          <access>read-write</access>
30534 
          <resetValue>0x00000000</resetValue>
30535 
          <fields>
30536 
            <field>
30537 
              <name>HTH</name>
30538 
              <description>Hash table high</description>
30539 
              <bitOffset>0</bitOffset>
30540 
              <bitWidth>32</bitWidth>
30541 
            </field>
30542 
          </fields>
30543 
        </register>
30544 
        <register>
30545 
          <name>MACHTLR</name>
30546 
          <displayName>MACHTLR</displayName>
30547 
          <description>Ethernet MAC hash table low
30548 
          register</description>
30549 
          <addressOffset>0xC</addressOffset>
30550 
          <size>0x20</size>
30551 
          <access>read-write</access>
30552 
          <resetValue>0x00000000</resetValue>
30553 
          <fields>
30554 
            <field>
30555 
              <name>HTL</name>
30556 
              <description>Hash table low</description>
30557 
              <bitOffset>0</bitOffset>
30558 
              <bitWidth>32</bitWidth>
30559 
            </field>
30560 
          </fields>
30561 
        </register>
30562 
        <register>
30563 
          <name>MACMIIAR</name>
30564 
          <displayName>MACMIIAR</displayName>
30565 
          <description>Ethernet MAC MII address register
30566 
          (ETH_MACMIIAR)</description>
30567 
          <addressOffset>0x10</addressOffset>
30568 
          <size>0x20</size>
30569 
          <access>read-write</access>
30570 
          <resetValue>0x00000000</resetValue>
30571 
          <fields>
30572 
            <field>
30573 
              <name>MB</name>
30574 
              <description>MII busy</description>
30575 
              <bitOffset>0</bitOffset>
30576 
              <bitWidth>1</bitWidth>
30577 
            </field>
30578 
            <field>
30579 
              <name>MW</name>
30580 
              <description>MII write</description>
30581 
              <bitOffset>1</bitOffset>
30582 
              <bitWidth>1</bitWidth>
30583 
            </field>
30584 
            <field>
30585 
              <name>CR</name>
30586 
              <description>Clock range</description>
30587 
              <bitOffset>2</bitOffset>
30588 
              <bitWidth>3</bitWidth>
30589 
            </field>
30590 
            <field>
30591 
              <name>MR</name>
30592 
              <description>MII register</description>
30593 
              <bitOffset>6</bitOffset>
30594 
              <bitWidth>5</bitWidth>
30595 
            </field>
30596 
            <field>
30597 
              <name>PA</name>
30598 
              <description>PHY address</description>
30599 
              <bitOffset>11</bitOffset>
30600 
              <bitWidth>5</bitWidth>
30601 
            </field>
30602 
          </fields>
30603 
        </register>
30604 
        <register>
30605 
          <name>MACMIIDR</name>
30606 
          <displayName>MACMIIDR</displayName>
30607 
          <description>Ethernet MAC MII data register
30608 
          (ETH_MACMIIDR)</description>
30609 
          <addressOffset>0x14</addressOffset>
30610 
          <size>0x20</size>
30611 
          <access>read-write</access>
30612 
          <resetValue>0x00000000</resetValue>
30613 
          <fields>
30614 
            <field>
30615 
              <name>MD</name>
30616 
              <description>MII data</description>
30617 
              <bitOffset>0</bitOffset>
30618 
              <bitWidth>16</bitWidth>
30619 
            </field>
30620 
          </fields>
30621 
        </register>
30622 
        <register>
30623 
          <name>MACFCR</name>
30624 
          <displayName>MACFCR</displayName>
30625 
          <description>Ethernet MAC flow control register
30626 
          (ETH_MACFCR)</description>
30627 
          <addressOffset>0x18</addressOffset>
30628 
          <size>0x20</size>
30629 
          <access>read-write</access>
30630 
          <resetValue>0x00000000</resetValue>
30631 
          <fields>
30632 
            <field>
30633 
              <name>FCB_BPA</name>
30634 
              <description>Flow control busy/back pressure
30635 
              activate</description>
30636 
              <bitOffset>0</bitOffset>
30637 
              <bitWidth>1</bitWidth>
30638 
            </field>
30639 
            <field>
30640 
              <name>TFCE</name>
30641 
              <description>Transmit flow control
30642 
              enable</description>
30643 
              <bitOffset>1</bitOffset>
30644 
              <bitWidth>1</bitWidth>
30645 
            </field>
30646 
            <field>
30647 
              <name>RFCE</name>
30648 
              <description>Receive flow control
30649 
              enable</description>
30650 
              <bitOffset>2</bitOffset>
30651 
              <bitWidth>1</bitWidth>
30652 
            </field>
30653 
            <field>
30654 
              <name>UPFD</name>
30655 
              <description>Unicast pause frame detect</description>
30656 
              <bitOffset>3</bitOffset>
30657 
              <bitWidth>1</bitWidth>
30658 
            </field>
30659 
            <field>
30660 
              <name>PLT</name>
30661 
              <description>Pause low threshold</description>
30662 
              <bitOffset>4</bitOffset>
30663 
              <bitWidth>2</bitWidth>
30664 
            </field>
30665 
            <field>
30666 
              <name>ZQPD</name>
30667 
              <description>Zero-quanta pause disable</description>
30668 
              <bitOffset>7</bitOffset>
30669 
              <bitWidth>1</bitWidth>
30670 
            </field>
30671 
            <field>
30672 
              <name>PT</name>
30673 
              <description>Pass control frames</description>
30674 
              <bitOffset>16</bitOffset>
30675 
              <bitWidth>16</bitWidth>
30676 
            </field>
30677 
          </fields>
30678 
        </register>
30679 
        <register>
30680 
          <name>MACVLANTR</name>
30681 
          <displayName>MACVLANTR</displayName>
30682 
          <description>Ethernet MAC VLAN tag register
30683 
          (ETH_MACVLANTR)</description>
30684 
          <addressOffset>0x1C</addressOffset>
30685 
          <size>0x20</size>
30686 
          <access>read-write</access>
30687 
          <resetValue>0x00000000</resetValue>
30688 
          <fields>
30689 
            <field>
30690 
              <name>VLANTI</name>
30691 
              <description>VLAN tag identifier (for receive
30692 
              frames)</description>
30693 
              <bitOffset>0</bitOffset>
30694 
              <bitWidth>16</bitWidth>
30695 
            </field>
30696 
            <field>
30697 
              <name>VLANTC</name>
30698 
              <description>12-bit VLAN tag comparison</description>
30699 
              <bitOffset>16</bitOffset>
30700 
              <bitWidth>1</bitWidth>
30701 
            </field>
30702 
          </fields>
30703 
        </register>
30704 
        <register>
30705 
          <name>MACRWUFFR</name>
30706 
          <displayName>MACRWUFFR</displayName>
30707 
          <description>Ethernet MAC remote wakeup frame filter
30708 
          register (ETH_MACRWUFFR)</description>
30709 
          <addressOffset>0x28</addressOffset>
30710 
          <size>0x20</size>
30711 
          <access>read-write</access>
30712 
          <resetValue>0x00000000</resetValue>
30713 
        </register>
30714 
        <register>
30715 
          <name>MACPMTCSR</name>
30716 
          <displayName>MACPMTCSR</displayName>
30717 
          <description>Ethernet MAC PMT control and status register
30718 
          (ETH_MACPMTCSR)</description>
30719 
          <addressOffset>0x2C</addressOffset>
30720 
          <size>0x20</size>
30721 
          <access>read-write</access>
30722 
          <resetValue>0x00000000</resetValue>
30723 
          <fields>
30724 
            <field>
30725 
              <name>PD</name>
30726 
              <description>Power down</description>
30727 
              <bitOffset>0</bitOffset>
30728 
              <bitWidth>1</bitWidth>
30729 
            </field>
30730 
            <field>
30731 
              <name>MPE</name>
30732 
              <description>Magic Packet enable</description>
30733 
              <bitOffset>1</bitOffset>
30734 
              <bitWidth>1</bitWidth>
30735 
            </field>
30736 
            <field>
30737 
              <name>WFE</name>
30738 
              <description>Wakeup frame enable</description>
30739 
              <bitOffset>2</bitOffset>
30740 
              <bitWidth>1</bitWidth>
30741 
            </field>
30742 
            <field>
30743 
              <name>MPR</name>
30744 
              <description>Magic packet received</description>
30745 
              <bitOffset>5</bitOffset>
30746 
              <bitWidth>1</bitWidth>
30747 
            </field>
30748 
            <field>
30749 
              <name>WFR</name>
30750 
              <description>Wakeup frame received</description>
30751 
              <bitOffset>6</bitOffset>
30752 
              <bitWidth>1</bitWidth>
30753 
            </field>
30754 
            <field>
30755 
              <name>GU</name>
30756 
              <description>Global unicast</description>
30757 
              <bitOffset>9</bitOffset>
30758 
              <bitWidth>1</bitWidth>
30759 
            </field>
30760 
            <field>
30761 
              <name>WFFRPR</name>
30762 
              <description>Wakeup frame filter register pointer
30763 
              reset</description>
30764 
              <bitOffset>31</bitOffset>
30765 
              <bitWidth>1</bitWidth>
30766 
            </field>
30767 
          </fields>
30768 
        </register>
30769 
        <register>
30770 
          <name>MACSR</name>
30771 
          <displayName>MACSR</displayName>
30772 
          <description>Ethernet MAC interrupt status register
30773 
          (ETH_MACSR)</description>
30774 
          <addressOffset>0x38</addressOffset>
30775 
          <size>0x20</size>
30776 
          <access>read-write</access>
30777 
          <resetValue>0x00000000</resetValue>
30778 
          <fields>
30779 
            <field>
30780 
              <name>PMTS</name>
30781 
              <description>PMT status</description>
30782 
              <bitOffset>3</bitOffset>
30783 
              <bitWidth>1</bitWidth>
30784 
            </field>
30785 
            <field>
30786 
              <name>MMCS</name>
30787 
              <description>MMC status</description>
30788 
              <bitOffset>4</bitOffset>
30789 
              <bitWidth>1</bitWidth>
30790 
            </field>
30791 
            <field>
30792 
              <name>MMCRS</name>
30793 
              <description>MMC receive status</description>
30794 
              <bitOffset>5</bitOffset>
30795 
              <bitWidth>1</bitWidth>
30796 
            </field>
30797 
            <field>
30798 
              <name>MMCTS</name>
30799 
              <description>MMC transmit status</description>
30800 
              <bitOffset>6</bitOffset>
30801 
              <bitWidth>1</bitWidth>
30802 
            </field>
30803 
            <field>
30804 
              <name>TSTS</name>
30805 
              <description>Time stamp trigger status</description>
30806 
              <bitOffset>9</bitOffset>
30807 
              <bitWidth>1</bitWidth>
30808 
            </field>
30809 
          </fields>
30810 
        </register>
30811 
        <register>
30812 
          <name>MACIMR</name>
30813 
          <displayName>MACIMR</displayName>
30814 
          <description>Ethernet MAC interrupt mask register
30815 
          (ETH_MACIMR)</description>
30816 
          <addressOffset>0x3C</addressOffset>
30817 
          <size>0x20</size>
30818 
          <access>read-write</access>
30819 
          <resetValue>0x00000000</resetValue>
30820 
          <fields>
30821 
            <field>
30822 
              <name>PMTIM</name>
30823 
              <description>PMT interrupt mask</description>
30824 
              <bitOffset>3</bitOffset>
30825 
              <bitWidth>1</bitWidth>
30826 
            </field>
30827 
            <field>
30828 
              <name>TSTIM</name>
30829 
              <description>Time stamp trigger interrupt
30830 
              mask</description>
30831 
              <bitOffset>9</bitOffset>
30832 
              <bitWidth>1</bitWidth>
30833 
            </field>
30834 
          </fields>
30835 
        </register>
30836 
        <register>
30837 
          <name>MACA0HR</name>
30838 
          <displayName>MACA0HR</displayName>
30839 
          <description>Ethernet MAC address 0 high register
30840 
          (ETH_MACA0HR)</description>
30841 
          <addressOffset>0x40</addressOffset>
30842 
          <size>0x20</size>
30843 
          <resetValue>0x0010FFFF</resetValue>
30844 
          <fields>
30845 
            <field>
30846 
              <name>MACA0H</name>
30847 
              <description>MAC address0 high</description>
30848 
              <bitOffset>0</bitOffset>
30849 
              <bitWidth>16</bitWidth>
30850 
              <access>read-write</access>
30851 
            </field>
30852 
            <field>
30853 
              <name>MO</name>
30854 
              <description>Always 1</description>
30855 
              <bitOffset>31</bitOffset>
30856 
              <bitWidth>1</bitWidth>
30857 
              <access>read-only</access>
30858 
            </field>
30859 
          </fields>
30860 
        </register>
30861 
        <register>
30862 
          <name>MACA0LR</name>
30863 
          <displayName>MACA0LR</displayName>
30864 
          <description>Ethernet MAC address 0 low
30865 
          register</description>
30866 
          <addressOffset>0x44</addressOffset>
30867 
          <size>0x20</size>
30868 
          <access>read-write</access>
30869 
          <resetValue>0xFFFFFFFF</resetValue>
30870 
          <fields>
30871 
            <field>
30872 
              <name>MACA0L</name>
30873 
              <description>MAC address0 low</description>
30874 
              <bitOffset>0</bitOffset>
30875 
              <bitWidth>32</bitWidth>
30876 
            </field>
30877 
          </fields>
30878 
        </register>
30879 
        <register>
30880 
          <name>MACA1HR</name>
30881 
          <displayName>MACA1HR</displayName>
30882 
          <description>Ethernet MAC address 1 high register
30883 
          (ETH_MACA1HR)</description>
30884 
          <addressOffset>0x48</addressOffset>
30885 
          <size>0x20</size>
30886 
          <access>read-write</access>
30887 
          <resetValue>0x0000FFFF</resetValue>
30888 
          <fields>
30889 
            <field>
30890 
              <name>MACA1H</name>
30891 
              <description>MAC address1 high</description>
30892 
              <bitOffset>0</bitOffset>
30893 
              <bitWidth>16</bitWidth>
30894 
            </field>
30895 
            <field>
30896 
              <name>MBC</name>
30897 
              <description>Mask byte control</description>
30898 
              <bitOffset>24</bitOffset>
30899 
              <bitWidth>6</bitWidth>
30900 
            </field>
30901 
            <field>
30902 
              <name>SA</name>
30903 
              <description>Source address</description>
30904 
              <bitOffset>30</bitOffset>
30905 
              <bitWidth>1</bitWidth>
30906 
            </field>
30907 
            <field>
30908 
              <name>AE</name>
30909 
              <description>Address enable</description>
30910 
              <bitOffset>31</bitOffset>
30911 
              <bitWidth>1</bitWidth>
30912 
            </field>
30913 
          </fields>
30914 
        </register>
30915 
        <register>
30916 
          <name>MACA1LR</name>
30917 
          <displayName>MACA1LR</displayName>
30918 
          <description>Ethernet MAC address1 low
30919 
          register</description>
30920 
          <addressOffset>0x4C</addressOffset>
30921 
          <size>0x20</size>
30922 
          <access>read-write</access>
30923 
          <resetValue>0xFFFFFFFF</resetValue>
30924 
          <fields>
30925 
            <field>
30926 
              <name>MACA1L</name>
30927 
              <description>MAC address1 low</description>
30928 
              <bitOffset>0</bitOffset>
30929 
              <bitWidth>32</bitWidth>
30930 
            </field>
30931 
          </fields>
30932 
        </register>
30933 
        <register>
30934 
          <name>MACA2HR</name>
30935 
          <displayName>MACA2HR</displayName>
30936 
          <description>Ethernet MAC address 2 high register
30937 
          (ETH_MACA2HR)</description>
30938 
          <addressOffset>0x50</addressOffset>
30939 
          <size>0x20</size>
30940 
          <access>read-write</access>
30941 
          <resetValue>0x0050</resetValue>
30942 
          <fields>
30943 
            <field>
30944 
              <name>ETH_MACA2HR</name>
30945 
              <description>Ethernet MAC address 2 high
30946 
              register</description>
30947 
              <bitOffset>0</bitOffset>
30948 
              <bitWidth>16</bitWidth>
30949 
            </field>
30950 
            <field>
30951 
              <name>MBC</name>
30952 
              <description>Mask byte control</description>
30953 
              <bitOffset>24</bitOffset>
30954 
              <bitWidth>6</bitWidth>
30955 
            </field>
30956 
            <field>
30957 
              <name>SA</name>
30958 
              <description>Source address</description>
30959 
              <bitOffset>30</bitOffset>
30960 
              <bitWidth>1</bitWidth>
30961 
            </field>
30962 
            <field>
30963 
              <name>AE</name>
30964 
              <description>Address enable</description>
30965 
              <bitOffset>31</bitOffset>
30966 
              <bitWidth>1</bitWidth>
30967 
            </field>
30968 
          </fields>
30969 
        </register>
30970 
        <register>
30971 
          <name>MACA2LR</name>
30972 
          <displayName>MACA2LR</displayName>
30973 
          <description>Ethernet MAC address 2 low
30974 
          register</description>
30975 
          <addressOffset>0x54</addressOffset>
30976 
          <size>0x20</size>
30977 
          <access>read-write</access>
30978 
          <resetValue>0xFFFFFFFF</resetValue>
30979 
          <fields>
30980 
            <field>
30981 
              <name>MACA2L</name>
30982 
              <description>MAC address2 low</description>
30983 
              <bitOffset>0</bitOffset>
30984 
              <bitWidth>31</bitWidth>
30985 
            </field>
30986 
          </fields>
30987 
        </register>
30988 
        <register>
30989 
          <name>MACA3HR</name>
30990 
          <displayName>MACA3HR</displayName>
30991 
          <description>Ethernet MAC address 3 high register
30992 
          (ETH_MACA3HR)</description>
30993 
          <addressOffset>0x58</addressOffset>
30994 
          <size>0x20</size>
30995 
          <access>read-write</access>
30996 
          <resetValue>0x0000FFFF</resetValue>
30997 
          <fields>
30998 
            <field>
30999 
              <name>MACA3H</name>
31000 
              <description>MAC address3 high</description>
31001 
              <bitOffset>0</bitOffset>
31002 
              <bitWidth>16</bitWidth>
31003 
            </field>
31004 
            <field>
31005 
              <name>MBC</name>
31006 
              <description>Mask byte control</description>
31007 
              <bitOffset>24</bitOffset>
31008 
              <bitWidth>6</bitWidth>
31009 
            </field>
31010 
            <field>
31011 
              <name>SA</name>
31012 
              <description>Source address</description>
31013 
              <bitOffset>30</bitOffset>
31014 
              <bitWidth>1</bitWidth>
31015 
            </field>
31016 
            <field>
31017 
              <name>AE</name>
31018 
              <description>Address enable</description>
31019 
              <bitOffset>31</bitOffset>
31020 
              <bitWidth>1</bitWidth>
31021 
            </field>
31022 
          </fields>
31023 
        </register>
31024 
        <register>
31025 
          <name>MACA3LR</name>
31026 
          <displayName>MACA3LR</displayName>
31027 
          <description>Ethernet MAC address 3 low
31028 
          register</description>
31029 
          <addressOffset>0x5C</addressOffset>
31030 
          <size>0x20</size>
31031 
          <access>read-write</access>
31032 
          <resetValue>0xFFFFFFFF</resetValue>
31033 
          <fields>
31034 
            <field>
31035 
              <name>MBCA3L</name>
31036 
              <description>MAC address3 low</description>
31037 
              <bitOffset>0</bitOffset>
31038 
              <bitWidth>32</bitWidth>
31039 
            </field>
31040 
          </fields>
31041 
        </register>
31042 
      </registers>
31043 
    </peripheral>
31044 
    <peripheral>
31045 
      <name>ETHERNET_PTP</name>
31046 
      <description>Ethernet: Precision time protocol</description>
31047 
      <groupName>ETHERNET</groupName>
31048 
      <baseAddress>0x40028700</baseAddress>
31049 
      <addressBlock>
31050 
        <offset>0x0</offset>
31051 
        <size>0x400</size>
31052 
        <usage>registers</usage>
31053 
      </addressBlock>
31054 
      <registers>
31055 
        <register>
31056 
          <name>PTPTSCR</name>
31057 
          <displayName>PTPTSCR</displayName>
31058 
          <description>Ethernet PTP time stamp control register
31059 
          (ETH_PTPTSCR)</description>
31060 
          <addressOffset>0x0</addressOffset>
31061 
          <size>0x20</size>
31062 
          <access>read-write</access>
31063 
          <resetValue>0x00000000</resetValue>
31064 
          <fields>
31065 
            <field>
31066 
              <name>TSE</name>
31067 
              <description>Time stamp enable</description>
31068 
              <bitOffset>0</bitOffset>
31069 
              <bitWidth>1</bitWidth>
31070 
            </field>
31071 
            <field>
31072 
              <name>TSFCU</name>
31073 
              <description>Time stamp fine or coarse
31074 
              update</description>
31075 
              <bitOffset>1</bitOffset>
31076 
              <bitWidth>1</bitWidth>
31077 
            </field>
31078 
            <field>
31079 
              <name>TSSTI</name>
31080 
              <description>Time stamp system time
31081 
              initialize</description>
31082 
              <bitOffset>2</bitOffset>
31083 
              <bitWidth>1</bitWidth>
31084 
            </field>
31085 
            <field>
31086 
              <name>TSSTU</name>
31087 
              <description>Time stamp system time
31088 
              update</description>
31089 
              <bitOffset>3</bitOffset>
31090 
              <bitWidth>1</bitWidth>
31091 
            </field>
31092 
            <field>
31093 
              <name>TSITE</name>
31094 
              <description>Time stamp interrupt trigger
31095 
              enable</description>
31096 
              <bitOffset>4</bitOffset>
31097 
              <bitWidth>1</bitWidth>
31098 
            </field>
31099 
            <field>
31100 
              <name>TSARU</name>
31101 
              <description>Time stamp addend register
31102 
              update</description>
31103 
              <bitOffset>5</bitOffset>
31104 
              <bitWidth>1</bitWidth>
31105 
            </field>
31106 
          </fields>
31107 
        </register>
31108 
        <register>
31109 
          <name>PTPSSIR</name>
31110 
          <displayName>PTPSSIR</displayName>
31111 
          <description>Ethernet PTP subsecond increment
31112 
          register</description>
31113 
          <addressOffset>0x4</addressOffset>
31114 
          <size>0x20</size>
31115 
          <access>read-write</access>
31116 
          <resetValue>0x00000000</resetValue>
31117 
          <fields>
31118 
            <field>
31119 
              <name>STSSI</name>
31120 
              <description>System time subsecond
31121 
              increment</description>
31122 
              <bitOffset>0</bitOffset>
31123 
              <bitWidth>8</bitWidth>
31124 
            </field>
31125 
          </fields>
31126 
        </register>
31127 
        <register>
31128 
          <name>PTPTSHR</name>
31129 
          <displayName>PTPTSHR</displayName>
31130 
          <description>Ethernet PTP time stamp high
31131 
          register</description>
31132 
          <addressOffset>0x8</addressOffset>
31133 
          <size>0x20</size>
31134 
          <access>read-only</access>
31135 
          <resetValue>0x00000000</resetValue>
31136 
          <fields>
31137 
            <field>
31138 
              <name>STS</name>
31139 
              <description>System time second</description>
31140 
              <bitOffset>0</bitOffset>
31141 
              <bitWidth>32</bitWidth>
31142 
            </field>
31143 
          </fields>
31144 
        </register>
31145 
        <register>
31146 
          <name>PTPTSLR</name>
31147 
          <displayName>PTPTSLR</displayName>
31148 
          <description>Ethernet PTP time stamp low register
31149 
          (ETH_PTPTSLR)</description>
31150 
          <addressOffset>0xC</addressOffset>
31151 
          <size>0x20</size>
31152 
          <access>read-only</access>
31153 
          <resetValue>0x00000000</resetValue>
31154 
          <fields>
31155 
            <field>
31156 
              <name>STSS</name>
31157 
              <description>System time subseconds</description>
31158 
              <bitOffset>0</bitOffset>
31159 
              <bitWidth>31</bitWidth>
31160 
            </field>
31161 
            <field>
31162 
              <name>STPNS</name>
31163 
              <description>System time positive or negative
31164 
              sign</description>
31165 
              <bitOffset>31</bitOffset>
31166 
              <bitWidth>1</bitWidth>
31167 
            </field>
31168 
          </fields>
31169 
        </register>
31170 
        <register>
31171 
          <name>PTPTSHUR</name>
31172 
          <displayName>PTPTSHUR</displayName>
31173 
          <description>Ethernet PTP time stamp high update
31174 
          register</description>
31175 
          <addressOffset>0x10</addressOffset>
31176 
          <size>0x20</size>
31177 
          <access>read-write</access>
31178 
          <resetValue>0x00000000</resetValue>
31179 
          <fields>
31180 
            <field>
31181 
              <name>TSUS</name>
31182 
              <description>Time stamp update second</description>
31183 
              <bitOffset>0</bitOffset>
31184 
              <bitWidth>32</bitWidth>
31185 
            </field>
31186 
          </fields>
31187 
        </register>
31188 
        <register>
31189 
          <name>PTPTSLUR</name>
31190 
          <displayName>PTPTSLUR</displayName>
31191 
          <description>Ethernet PTP time stamp low update register
31192 
          (ETH_PTPTSLUR)</description>
31193 
          <addressOffset>0x14</addressOffset>
31194 
          <size>0x20</size>
31195 
          <access>read-write</access>
31196 
          <resetValue>0x00000000</resetValue>
31197 
          <fields>
31198 
            <field>
31199 
              <name>TSUSS</name>
31200 
              <description>Time stamp update
31201 
              subseconds</description>
31202 
              <bitOffset>0</bitOffset>
31203 
              <bitWidth>31</bitWidth>
31204 
            </field>
31205 
            <field>
31206 
              <name>TSUPNS</name>
31207 
              <description>Time stamp update positive or negative
31208 
              sign</description>
31209 
              <bitOffset>31</bitOffset>
31210 
              <bitWidth>1</bitWidth>
31211 
            </field>
31212 
          </fields>
31213 
        </register>
31214 
        <register>
31215 
          <name>PTPTSAR</name>
31216 
          <displayName>PTPTSAR</displayName>
31217 
          <description>Ethernet PTP time stamp addend
31218 
          register</description>
31219 
          <addressOffset>0x18</addressOffset>
31220 
          <size>0x20</size>
31221 
          <access>read-write</access>
31222 
          <resetValue>0x00000000</resetValue>
31223 
          <fields>
31224 
            <field>
31225 
              <name>TSA</name>
31226 
              <description>Time stamp addend</description>
31227 
              <bitOffset>0</bitOffset>
31228 
              <bitWidth>32</bitWidth>
31229 
            </field>
31230 
          </fields>
31231 
        </register>
31232 
        <register>
31233 
          <name>PTPTTHR</name>
31234 
          <displayName>PTPTTHR</displayName>
31235 
          <description>Ethernet PTP target time high
31236 
          register</description>
31237 
          <addressOffset>0x1C</addressOffset>
31238 
          <size>0x20</size>
31239 
          <access>read-write</access>
31240 
          <resetValue>0x00000000</resetValue>
31241 
          <fields>
31242 
            <field>
31243 
              <name>TTSH</name>
31244 
              <description>Target time stamp high</description>
31245 
              <bitOffset>0</bitOffset>
31246 
              <bitWidth>32</bitWidth>
31247 
            </field>
31248 
          </fields>
31249 
        </register>
31250 
        <register>
31251 
          <name>PTPTTLR</name>
31252 
          <displayName>PTPTTLR</displayName>
31253 
          <description>Ethernet PTP target time low
31254 
          register</description>
31255 
          <addressOffset>0x20</addressOffset>
31256 
          <size>0x20</size>
31257 
          <access>read-write</access>
31258 
          <resetValue>0x00000000</resetValue>
31259 
          <fields>
31260 
            <field>
31261 
              <name>TTSL</name>
31262 
              <description>Target time stamp low</description>
31263 
              <bitOffset>0</bitOffset>
31264 
              <bitWidth>32</bitWidth>
31265 
            </field>
31266 
          </fields>
31267 
        </register>
31268 
      </registers>
31269 
    </peripheral>
31270 
    <peripheral>
31271 
      <name>ETHERNET_DMA</name>
31272 
      <description>Ethernet: DMA controller operation</description>
31273 
      <groupName>ETHERNET</groupName>
31274 
      <baseAddress>0x40029000</baseAddress>
31275 
      <addressBlock>
31276 
        <offset>0x0</offset>
31277 
        <size>0x400</size>
31278 
        <usage>registers</usage>
31279 
      </addressBlock>
31280 
      <registers>
31281 
        <register>
31282 
          <name>DMABMR</name>
31283 
          <displayName>DMABMR</displayName>
31284 
          <description>Ethernet DMA bus mode register</description>
31285 
          <addressOffset>0x0</addressOffset>
31286 
          <size>0x20</size>
31287 
          <access>read-write</access>
31288 
          <resetValue>0x20101</resetValue>
31289 
          <fields>
31290 
            <field>
31291 
              <name>SR</name>
31292 
              <description>Software reset</description>
31293 
              <bitOffset>0</bitOffset>
31294 
              <bitWidth>1</bitWidth>
31295 
            </field>
31296 
            <field>
31297 
              <name>DA</name>
31298 
              <description>DMA Arbitration</description>
31299 
              <bitOffset>1</bitOffset>
31300 
              <bitWidth>1</bitWidth>
31301 
            </field>
31302 
            <field>
31303 
              <name>DSL</name>
31304 
              <description>Descriptor skip length</description>
31305 
              <bitOffset>2</bitOffset>
31306 
              <bitWidth>5</bitWidth>
31307 
            </field>
31308 
            <field>
31309 
              <name>PBL</name>
31310 
              <description>Programmable burst length</description>
31311 
              <bitOffset>8</bitOffset>
31312 
              <bitWidth>6</bitWidth>
31313 
            </field>
31314 
            <field>
31315 
              <name>RTPR</name>
31316 
              <description>Rx Tx priority ratio</description>
31317 
              <bitOffset>14</bitOffset>
31318 
              <bitWidth>2</bitWidth>
31319 
            </field>
31320 
            <field>
31321 
              <name>FB</name>
31322 
              <description>Fixed burst</description>
31323 
              <bitOffset>16</bitOffset>
31324 
              <bitWidth>1</bitWidth>
31325 
            </field>
31326 
            <field>
31327 
              <name>RDP</name>
31328 
              <description>Rx DMA PBL</description>
31329 
              <bitOffset>17</bitOffset>
31330 
              <bitWidth>6</bitWidth>
31331 
            </field>
31332 
            <field>
31333 
              <name>USP</name>
31334 
              <description>Use separate PBL</description>
31335 
              <bitOffset>23</bitOffset>
31336 
              <bitWidth>1</bitWidth>
31337 
            </field>
31338 
            <field>
31339 
              <name>FPM</name>
31340 
              <description>4xPBL mode</description>
31341 
              <bitOffset>24</bitOffset>
31342 
              <bitWidth>1</bitWidth>
31343 
            </field>
31344 
            <field>
31345 
              <name>AAB</name>
31346 
              <description>Address-aligned beats</description>
31347 
              <bitOffset>25</bitOffset>
31348 
              <bitWidth>1</bitWidth>
31349 
            </field>
31350 
          </fields>
31351 
        </register>
31352 
        <register>
31353 
          <name>DMATPDR</name>
31354 
          <displayName>DMATPDR</displayName>
31355 
          <description>Ethernet DMA transmit poll demand
31356 
          register</description>
31357 
          <addressOffset>0x4</addressOffset>
31358 
          <size>0x20</size>
31359 
          <access>read-write</access>
31360 
          <resetValue>0x00000000</resetValue>
31361 
          <fields>
31362 
            <field>
31363 
              <name>TPD</name>
31364 
              <description>Transmit poll demand</description>
31365 
              <bitOffset>0</bitOffset>
31366 
              <bitWidth>32</bitWidth>
31367 
            </field>
31368 
          </fields>
31369 
        </register>
31370 
        <register>
31371 
          <name>DMARPDR</name>
31372 
          <displayName>DMARPDR</displayName>
31373 
          <description>EHERNET DMA receive poll demand
31374 
          register</description>
31375 
          <addressOffset>0x8</addressOffset>
31376 
          <size>0x20</size>
31377 
          <access>read-write</access>
31378 
          <resetValue>0x00000000</resetValue>
31379 
          <fields>
31380 
            <field>
31381 
              <name>RPD</name>
31382 
              <description>Receive poll demand</description>
31383 
              <bitOffset>0</bitOffset>
31384 
              <bitWidth>32</bitWidth>
31385 
            </field>
31386 
          </fields>
31387 
        </register>
31388 
        <register>
31389 
          <name>DMARDLAR</name>
31390 
          <displayName>DMARDLAR</displayName>
31391 
          <description>Ethernet DMA receive descriptor list address
31392 
          register</description>
31393 
          <addressOffset>0xC</addressOffset>
31394 
          <size>0x20</size>
31395 
          <access>read-write</access>
31396 
          <resetValue>0x00000000</resetValue>
31397 
          <fields>
31398 
            <field>
31399 
              <name>SRL</name>
31400 
              <description>Start of receive list</description>
31401 
              <bitOffset>0</bitOffset>
31402 
              <bitWidth>32</bitWidth>
31403 
            </field>
31404 
          </fields>
31405 
        </register>
31406 
        <register>
31407 
          <name>DMATDLAR</name>
31408 
          <displayName>DMATDLAR</displayName>
31409 
          <description>Ethernet DMA transmit descriptor list
31410 
          address register</description>
31411 
          <addressOffset>0x10</addressOffset>
31412 
          <size>0x20</size>
31413 
          <access>read-write</access>
31414 
          <resetValue>0x00000000</resetValue>
31415 
          <fields>
31416 
            <field>
31417 
              <name>STL</name>
31418 
              <description>Start of transmit list</description>
31419 
              <bitOffset>0</bitOffset>
31420 
              <bitWidth>32</bitWidth>
31421 
            </field>
31422 
          </fields>
31423 
        </register>
31424 
        <register>
31425 
          <name>DMASR</name>
31426 
          <displayName>DMASR</displayName>
31427 
          <description>Ethernet DMA status register</description>
31428 
          <addressOffset>0x14</addressOffset>
31429 
          <size>0x20</size>
31430 
          <resetValue>0x00000000</resetValue>
31431 
          <fields>
31432 
            <field>
31433 
              <name>TS</name>
31434 
              <description>Transmit status</description>
31435 
              <bitOffset>0</bitOffset>
31436 
              <bitWidth>1</bitWidth>
31437 
              <access>read-write</access>
31438 
            </field>
31439 
            <field>
31440 
              <name>TPSS</name>
31441 
              <description>Transmit process stopped
31442 
              status</description>
31443 
              <bitOffset>1</bitOffset>
31444 
              <bitWidth>1</bitWidth>
31445 
              <access>read-write</access>
31446 
            </field>
31447 
            <field>
31448 
              <name>TBUS</name>
31449 
              <description>Transmit buffer unavailable
31450 
              status</description>
31451 
              <bitOffset>2</bitOffset>
31452 
              <bitWidth>1</bitWidth>
31453 
              <access>read-write</access>
31454 
            </field>
31455 
            <field>
31456 
              <name>TJTS</name>
31457 
              <description>Transmit jabber timeout
31458 
              status</description>
31459 
              <bitOffset>3</bitOffset>
31460 
              <bitWidth>1</bitWidth>
31461 
              <access>read-write</access>
31462 
            </field>
31463 
            <field>
31464 
              <name>ROS</name>
31465 
              <description>Receive overflow status</description>
31466 
              <bitOffset>4</bitOffset>
31467 
              <bitWidth>1</bitWidth>
31468 
              <access>read-write</access>
31469 
            </field>
31470 
            <field>
31471 
              <name>TUS</name>
31472 
              <description>Transmit underflow status</description>
31473 
              <bitOffset>5</bitOffset>
31474 
              <bitWidth>1</bitWidth>
31475 
              <access>read-write</access>
31476 
            </field>
31477 
            <field>
31478 
              <name>RS</name>
31479 
              <description>Receive status</description>
31480 
              <bitOffset>6</bitOffset>
31481 
              <bitWidth>1</bitWidth>
31482 
              <access>read-write</access>
31483 
            </field>
31484 
            <field>
31485 
              <name>RBUS</name>
31486 
              <description>Receive buffer unavailable
31487 
              status</description>
31488 
              <bitOffset>7</bitOffset>
31489 
              <bitWidth>1</bitWidth>
31490 
              <access>read-write</access>
31491 
            </field>
31492 
            <field>
31493 
              <name>RPSS</name>
31494 
              <description>Receive process stopped
31495 
              status</description>
31496 
              <bitOffset>8</bitOffset>
31497 
              <bitWidth>1</bitWidth>
31498 
              <access>read-write</access>
31499 
            </field>
31500 
            <field>
31501 
              <name>PWTS</name>
31502 
              <description>Receive watchdog timeout
31503 
              status</description>
31504 
              <bitOffset>9</bitOffset>
31505 
              <bitWidth>1</bitWidth>
31506 
              <access>read-write</access>
31507 
            </field>
31508 
            <field>
31509 
              <name>ETS</name>
31510 
              <description>Early transmit status</description>
31511 
              <bitOffset>10</bitOffset>
31512 
              <bitWidth>1</bitWidth>
31513 
              <access>read-write</access>
31514 
            </field>
31515 
            <field>
31516 
              <name>FBES</name>
31517 
              <description>Fatal bus error status</description>
31518 
              <bitOffset>13</bitOffset>
31519 
              <bitWidth>1</bitWidth>
31520 
              <access>read-write</access>
31521 
            </field>
31522 
            <field>
31523 
              <name>ERS</name>
31524 
              <description>Early receive status</description>
31525 
              <bitOffset>14</bitOffset>
31526 
              <bitWidth>1</bitWidth>
31527 
              <access>read-write</access>
31528 
            </field>
31529 
            <field>
31530 
              <name>AIS</name>
31531 
              <description>Abnormal interrupt summary</description>
31532 
              <bitOffset>15</bitOffset>
31533 
              <bitWidth>1</bitWidth>
31534 
              <access>read-write</access>
31535 
            </field>
31536 
            <field>
31537 
              <name>NIS</name>
31538 
              <description>Normal interrupt summary</description>
31539 
              <bitOffset>16</bitOffset>
31540 
              <bitWidth>1</bitWidth>
31541 
              <access>read-write</access>
31542 
            </field>
31543 
            <field>
31544 
              <name>RPS</name>
31545 
              <description>Receive process state</description>
31546 
              <bitOffset>17</bitOffset>
31547 
              <bitWidth>3</bitWidth>
31548 
              <access>read-only</access>
31549 
            </field>
31550 
            <field>
31551 
              <name>TPS</name>
31552 
              <description>Transmit process state</description>
31553 
              <bitOffset>20</bitOffset>
31554 
              <bitWidth>3</bitWidth>
31555 
              <access>read-only</access>
31556 
            </field>
31557 
            <field>
31558 
              <name>EBS</name>
31559 
              <description>Error bits status</description>
31560 
              <bitOffset>23</bitOffset>
31561 
              <bitWidth>3</bitWidth>
31562 
              <access>read-only</access>
31563 
            </field>
31564 
            <field>
31565 
              <name>MMCS</name>
31566 
              <description>MMC status</description>
31567 
              <bitOffset>27</bitOffset>
31568 
              <bitWidth>1</bitWidth>
31569 
              <access>read-only</access>
31570 
            </field>
31571 
            <field>
31572 
              <name>PMTS</name>
31573 
              <description>PMT status</description>
31574 
              <bitOffset>28</bitOffset>
31575 
              <bitWidth>1</bitWidth>
31576 
              <access>read-only</access>
31577 
            </field>
31578 
            <field>
31579 
              <name>TSTS</name>
31580 
              <description>Time stamp trigger status</description>
31581 
              <bitOffset>29</bitOffset>
31582 
              <bitWidth>1</bitWidth>
31583 
              <access>read-only</access>
31584 
            </field>
31585 
          </fields>
31586 
        </register>
31587 
        <register>
31588 
          <name>DMAOMR</name>
31589 
          <displayName>DMAOMR</displayName>
31590 
          <description>Ethernet DMA operation mode
31591 
          register</description>
31592 
          <addressOffset>0x18</addressOffset>
31593 
          <size>0x20</size>
31594 
          <access>read-write</access>
31595 
          <resetValue>0x00000000</resetValue>
31596 
          <fields>
31597 
            <field>
31598 
              <name>SR</name>
31599 
              <description>SR</description>
31600 
              <bitOffset>1</bitOffset>
31601 
              <bitWidth>1</bitWidth>
31602 
            </field>
31603 
            <field>
31604 
              <name>OSF</name>
31605 
              <description>OSF</description>
31606 
              <bitOffset>2</bitOffset>
31607 
              <bitWidth>1</bitWidth>
31608 
            </field>
31609 
            <field>
31610 
              <name>RTC</name>
31611 
              <description>RTC</description>
31612 
              <bitOffset>3</bitOffset>
31613 
              <bitWidth>2</bitWidth>
31614 
            </field>
31615 
            <field>
31616 
              <name>FUGF</name>
31617 
              <description>FUGF</description>
31618 
              <bitOffset>6</bitOffset>
31619 
              <bitWidth>1</bitWidth>
31620 
            </field>
31621 
            <field>
31622 
              <name>FEF</name>
31623 
              <description>FEF</description>
31624 
              <bitOffset>7</bitOffset>
31625 
              <bitWidth>1</bitWidth>
31626 
            </field>
31627 
            <field>
31628 
              <name>ST</name>
31629 
              <description>ST</description>
31630 
              <bitOffset>13</bitOffset>
31631 
              <bitWidth>1</bitWidth>
31632 
            </field>
31633 
            <field>
31634 
              <name>TTC</name>
31635 
              <description>TTC</description>
31636 
              <bitOffset>14</bitOffset>
31637 
              <bitWidth>3</bitWidth>
31638 
            </field>
31639 
            <field>
31640 
              <name>FTF</name>
31641 
              <description>FTF</description>
31642 
              <bitOffset>20</bitOffset>
31643 
              <bitWidth>1</bitWidth>
31644 
            </field>
31645 
            <field>
31646 
              <name>TSF</name>
31647 
              <description>TSF</description>
31648 
              <bitOffset>21</bitOffset>
31649 
              <bitWidth>1</bitWidth>
31650 
            </field>
31651 
            <field>
31652 
              <name>DFRF</name>
31653 
              <description>DFRF</description>
31654 
              <bitOffset>24</bitOffset>
31655 
              <bitWidth>1</bitWidth>
31656 
            </field>
31657 
            <field>
31658 
              <name>RSF</name>
31659 
              <description>RSF</description>
31660 
              <bitOffset>25</bitOffset>
31661 
              <bitWidth>1</bitWidth>
31662 
            </field>
31663 
            <field>
31664 
              <name>DTCEFD</name>
31665 
              <description>DTCEFD</description>
31666 
              <bitOffset>26</bitOffset>
31667 
              <bitWidth>1</bitWidth>
31668 
            </field>
31669 
          </fields>
31670 
        </register>
31671 
        <register>
31672 
          <name>DMAIER</name>
31673 
          <displayName>DMAIER</displayName>
31674 
          <description>Ethernet DMA interrupt enable
31675 
          register</description>
31676 
          <addressOffset>0x1C</addressOffset>
31677 
          <size>0x20</size>
31678 
          <access>read-write</access>
31679 
          <resetValue>0x00000000</resetValue>
31680 
          <fields>
31681 
            <field>
31682 
              <name>TIE</name>
31683 
              <description>Transmit interrupt enable</description>
31684 
              <bitOffset>0</bitOffset>
31685 
              <bitWidth>1</bitWidth>
31686 
            </field>
31687 
            <field>
31688 
              <name>TPSIE</name>
31689 
              <description>Transmit process stopped interrupt
31690 
              enable</description>
31691 
              <bitOffset>1</bitOffset>
31692 
              <bitWidth>1</bitWidth>
31693 
            </field>
31694 
            <field>
31695 
              <name>TBUIE</name>
31696 
              <description>Transmit buffer unavailable interrupt
31697 
              enable</description>
31698 
              <bitOffset>2</bitOffset>
31699 
              <bitWidth>1</bitWidth>
31700 
            </field>
31701 
            <field>
31702 
              <name>TJTIE</name>
31703 
              <description>Transmit jabber timeout interrupt
31704 
              enable</description>
31705 
              <bitOffset>3</bitOffset>
31706 
              <bitWidth>1</bitWidth>
31707 
            </field>
31708 
            <field>
31709 
              <name>ROIE</name>
31710 
              <description>Overflow interrupt enable</description>
31711 
              <bitOffset>4</bitOffset>
31712 
              <bitWidth>1</bitWidth>
31713 
            </field>
31714 
            <field>
31715 
              <name>TUIE</name>
31716 
              <description>Underflow interrupt enable</description>
31717 
              <bitOffset>5</bitOffset>
31718 
              <bitWidth>1</bitWidth>
31719 
            </field>
31720 
            <field>
31721 
              <name>RIE</name>
31722 
              <description>Receive interrupt enable</description>
31723 
              <bitOffset>6</bitOffset>
31724 
              <bitWidth>1</bitWidth>
31725 
            </field>
31726 
            <field>
31727 
              <name>RBUIE</name>
31728 
              <description>Receive buffer unavailable interrupt
31729 
              enable</description>
31730 
              <bitOffset>7</bitOffset>
31731 
              <bitWidth>1</bitWidth>
31732 
            </field>
31733 
            <field>
31734 
              <name>RPSIE</name>
31735 
              <description>Receive process stopped interrupt
31736 
              enable</description>
31737 
              <bitOffset>8</bitOffset>
31738 
              <bitWidth>1</bitWidth>
31739 
            </field>
31740 
            <field>
31741 
              <name>RWTIE</name>
31742 
              <description>receive watchdog timeout interrupt
31743 
              enable</description>
31744 
              <bitOffset>9</bitOffset>
31745 
              <bitWidth>1</bitWidth>
31746 
            </field>
31747 
            <field>
31748 
              <name>ETIE</name>
31749 
              <description>Early transmit interrupt
31750 
              enable</description>
31751 
              <bitOffset>10</bitOffset>
31752 
              <bitWidth>1</bitWidth>
31753 
            </field>
31754 
            <field>
31755 
              <name>FBEIE</name>
31756 
              <description>Fatal bus error interrupt
31757 
              enable</description>
31758 
              <bitOffset>13</bitOffset>
31759 
              <bitWidth>1</bitWidth>
31760 
            </field>
31761 
            <field>
31762 
              <name>ERIE</name>
31763 
              <description>Early receive interrupt
31764 
              enable</description>
31765 
              <bitOffset>14</bitOffset>
31766 
              <bitWidth>1</bitWidth>
31767 
            </field>
31768 
            <field>
31769 
              <name>AISE</name>
31770 
              <description>Abnormal interrupt summary
31771 
              enable</description>
31772 
              <bitOffset>15</bitOffset>
31773 
              <bitWidth>1</bitWidth>
31774 
            </field>
31775 
            <field>
31776 
              <name>NISE</name>
31777 
              <description>Normal interrupt summary
31778 
              enable</description>
31779 
              <bitOffset>16</bitOffset>
31780 
              <bitWidth>1</bitWidth>
31781 
            </field>
31782 
          </fields>
31783 
        </register>
31784 
        <register>
31785 
          <name>DMAMFBOCR</name>
31786 
          <displayName>DMAMFBOCR</displayName>
31787 
          <description>Ethernet DMA missed frame and buffer
31788 
          overflow counter register</description>
31789 
          <addressOffset>0x20</addressOffset>
31790 
          <size>0x20</size>
31791 
          <access>read-only</access>
31792 
          <resetValue>0x00000000</resetValue>
31793 
          <fields>
31794 
            <field>
31795 
              <name>MFC</name>
31796 
              <description>Missed frames by the
31797 
              controller</description>
31798 
              <bitOffset>0</bitOffset>
31799 
              <bitWidth>16</bitWidth>
31800 
            </field>
31801 
            <field>
31802 
              <name>OMFC</name>
31803 
              <description>Overflow bit for missed frame
31804 
              counter</description>
31805 
              <bitOffset>16</bitOffset>
31806 
              <bitWidth>1</bitWidth>
31807 
            </field>
31808 
            <field>
31809 
              <name>MFA</name>
31810 
              <description>Missed frames by the
31811 
              application</description>
31812 
              <bitOffset>17</bitOffset>
31813 
              <bitWidth>11</bitWidth>
31814 
            </field>
31815 
            <field>
31816 
              <name>OFOC</name>
31817 
              <description>Overflow bit for FIFO overflow
31818 
              counter</description>
31819 
              <bitOffset>28</bitOffset>
31820 
              <bitWidth>1</bitWidth>
31821 
            </field>
31822 
          </fields>
31823 
        </register>
31824 
        <register>
31825 
          <name>DMACHTDR</name>
31826 
          <displayName>DMACHTDR</displayName>
31827 
          <description>Ethernet DMA current host transmit
31828 
          descriptor register</description>
31829 
          <addressOffset>0x48</addressOffset>
31830 
          <size>0x20</size>
31831 
          <access>read-only</access>
31832 
          <resetValue>0x00000000</resetValue>
31833 
          <fields>
31834 
            <field>
31835 
              <name>HTDAP</name>
31836 
              <description>Host transmit descriptor address
31837 
              pointer</description>
31838 
              <bitOffset>0</bitOffset>
31839 
              <bitWidth>32</bitWidth>
31840 
            </field>
31841 
          </fields>
31842 
        </register>
31843 
        <register>
31844 
          <name>DMACHRDR</name>
31845 
          <displayName>DMACHRDR</displayName>
31846 
          <description>Ethernet DMA current host receive descriptor
31847 
          register</description>
31848 
          <addressOffset>0x4C</addressOffset>
31849 
          <size>0x20</size>
31850 
          <access>read-only</access>
31851 
          <resetValue>0x00000000</resetValue>
31852 
          <fields>
31853 
            <field>
31854 
              <name>HRDAP</name>
31855 
              <description>Host receive descriptor address
31856 
              pointer</description>
31857 
              <bitOffset>0</bitOffset>
31858 
              <bitWidth>32</bitWidth>
31859 
            </field>
31860 
          </fields>
31861 
        </register>
31862 
        <register>
31863 
          <name>DMACHTBAR</name>
31864 
          <displayName>DMACHTBAR</displayName>
31865 
          <description>Ethernet DMA current host transmit buffer
31866 
          address register</description>
31867 
          <addressOffset>0x50</addressOffset>
31868 
          <size>0x20</size>
31869 
          <access>read-only</access>
31870 
          <resetValue>0x00000000</resetValue>
31871 
          <fields>
31872 
            <field>
31873 
              <name>HTBAP</name>
31874 
              <description>Host transmit buffer address
31875 
              pointer</description>
31876 
              <bitOffset>0</bitOffset>
31877 
              <bitWidth>32</bitWidth>
31878 
            </field>
31879 
          </fields>
31880 
        </register>
31881 
        <register>
31882 
          <name>DMACHRBAR</name>
31883 
          <displayName>DMACHRBAR</displayName>
31884 
          <description>Ethernet DMA current host receive buffer
31885 
          address register</description>
31886 
          <addressOffset>0x54</addressOffset>
31887 
          <size>0x20</size>
31888 
          <access>read-only</access>
31889 
          <resetValue>0x00000000</resetValue>
31890 
          <fields>
31891 
            <field>
31892 
              <name>HRBAP</name>
31893 
              <description>Host receive buffer address
31894 
              pointer</description>
31895 
              <bitOffset>0</bitOffset>
31896 
              <bitWidth>32</bitWidth>
31897 
            </field>
31898 
          </fields>
31899 
        </register>
31900 
      </registers>
31901 
    </peripheral>
31902 
  </peripherals>
31903 
</device>