Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | <?xml version="1.0" encoding="utf-8" standalone="no"?> |
| 2 | <device schemaVersion="1.1" |
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| 3 | xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" |
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| 4 | xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> |
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| 5 | <name>STM32F030</name> |
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| 6 | <version>1.0</version> |
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| 7 | <description>STM32F030</description> |
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| 8 | <!--Bus Interface Properties--> |
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| 9 | <!--Cortex-M0 is byte addressable--> |
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| 10 | <addressUnitBits>8</addressUnitBits> |
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| 11 | <!--the maximum data bit width accessible within a single transfer--> |
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| 12 | <width>32</width> |
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| 13 | <!--Register Default Properties--> |
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| 14 | <size>0x20</size> |
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| 15 | <resetValue>0x0</resetValue> |
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| 16 | <resetMask>0xFFFFFFFF</resetMask> |
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| 17 | <peripherals> |
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| 18 | <peripheral> |
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| 19 | <name>CRC</name> |
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| 20 | <description>cyclic redundancy check calculation |
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| 21 | unit</description> |
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| 22 | <groupName>CRC</groupName> |
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| 23 | <baseAddress>0x40023000</baseAddress> |
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| 24 | <addressBlock> |
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| 25 | <offset>0x0</offset> |
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| 26 | <size>0x400</size> |
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| 27 | <usage>registers</usage> |
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| 28 | </addressBlock> |
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| 29 | <registers> |
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| 30 | <register> |
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| 31 | <name>DR</name> |
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| 32 | <displayName>DR</displayName> |
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| 33 | <description>Data register</description> |
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| 34 | <addressOffset>0x0</addressOffset> |
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| 35 | <size>0x20</size> |
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| 36 | <access>read-write</access> |
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| 37 | <resetValue>0xFFFFFFFF</resetValue> |
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| 38 | <fields> |
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| 39 | <field> |
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| 40 | <name>DR</name> |
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| 41 | <description>Data register bits</description> |
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| 42 | <bitOffset>0</bitOffset> |
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| 43 | <bitWidth>32</bitWidth> |
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| 44 | </field> |
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| 45 | </fields> |
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| 46 | </register> |
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| 47 | <register> |
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| 48 | <name>IDR</name> |
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| 49 | <displayName>IDR</displayName> |
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| 50 | <description>Independent data register</description> |
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| 51 | <addressOffset>0x4</addressOffset> |
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| 52 | <size>0x20</size> |
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| 53 | <access>read-write</access> |
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| 54 | <resetValue>0x00000000</resetValue> |
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| 55 | <fields> |
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| 56 | <field> |
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| 57 | <name>IDR</name> |
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| 58 | <description>General-purpose 8-bit data register |
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| 59 | bits</description> |
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| 60 | <bitOffset>0</bitOffset> |
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| 61 | <bitWidth>8</bitWidth> |
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| 62 | </field> |
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| 63 | </fields> |
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| 64 | </register> |
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| 65 | <register> |
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| 66 | <name>CR</name> |
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| 67 | <displayName>CR</displayName> |
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| 68 | <description>Control register</description> |
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| 69 | <addressOffset>0x8</addressOffset> |
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| 70 | <size>0x20</size> |
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| 71 | <access>read-write</access> |
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| 72 | <resetValue>0x00000000</resetValue> |
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| 73 | <fields> |
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| 74 | <field> |
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| 75 | <name>RESET</name> |
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| 76 | <description>reset bit</description> |
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| 77 | <bitOffset>0</bitOffset> |
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| 78 | <bitWidth>1</bitWidth> |
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| 79 | </field> |
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| 80 | <field> |
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| 81 | <name>REV_IN</name> |
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| 82 | <description>Reverse input data</description> |
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| 83 | <bitOffset>5</bitOffset> |
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| 84 | <bitWidth>2</bitWidth> |
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| 85 | </field> |
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| 86 | <field> |
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| 87 | <name>REV_OUT</name> |
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| 88 | <description>Reverse output data</description> |
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| 89 | <bitOffset>7</bitOffset> |
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| 90 | <bitWidth>1</bitWidth> |
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| 91 | </field> |
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| 92 | </fields> |
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| 93 | </register> |
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| 94 | <register> |
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| 95 | <name>INIT</name> |
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| 96 | <displayName>INIT</displayName> |
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| 97 | <description>Initial CRC value</description> |
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| 98 | <addressOffset>0xC</addressOffset> |
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| 99 | <size>0x20</size> |
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| 100 | <access>read-write</access> |
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| 101 | <resetValue>0xFFFFFFFF</resetValue> |
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| 102 | <fields> |
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| 103 | <field> |
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| 104 | <name>INIT</name> |
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| 105 | <description>Programmable initial CRC |
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| 106 | value</description> |
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| 107 | <bitOffset>0</bitOffset> |
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| 108 | <bitWidth>32</bitWidth> |
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| 109 | </field> |
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| 110 | </fields> |
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| 111 | </register> |
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| 112 | </registers> |
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| 113 | </peripheral> |
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| 114 | <peripheral> |
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| 115 | <name>GPIOF</name> |
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| 116 | <description>General-purpose I/Os</description> |
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| 117 | <groupName>GPIO</groupName> |
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| 118 | <baseAddress>0x48001400</baseAddress> |
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| 119 | <addressBlock> |
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| 120 | <offset>0x0</offset> |
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| 121 | <size>0x400</size> |
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| 122 | <usage>registers</usage> |
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| 123 | </addressBlock> |
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| 124 | <registers> |
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| 125 | <register> |
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| 126 | <name>MODER</name> |
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| 127 | <displayName>MODER</displayName> |
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| 128 | <description>GPIO port mode register</description> |
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| 129 | <addressOffset>0x0</addressOffset> |
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| 130 | <size>0x20</size> |
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| 131 | <access>read-write</access> |
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| 132 | <resetValue>0x00000000</resetValue> |
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| 133 | <fields> |
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| 134 | <field> |
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| 135 | <name>MODER15</name> |
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| 136 | <description>Port x configuration bits (y = |
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| 137 | 0..15)</description> |
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| 138 | <bitOffset>30</bitOffset> |
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| 139 | <bitWidth>2</bitWidth> |
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| 140 | </field> |
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| 141 | <field> |
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| 142 | <name>MODER14</name> |
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| 143 | <description>Port x configuration bits (y = |
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| 144 | 0..15)</description> |
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| 145 | <bitOffset>28</bitOffset> |
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| 146 | <bitWidth>2</bitWidth> |
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| 147 | </field> |
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| 148 | <field> |
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| 149 | <name>MODER13</name> |
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| 150 | <description>Port x configuration bits (y = |
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| 151 | 0..15)</description> |
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| 152 | <bitOffset>26</bitOffset> |
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| 153 | <bitWidth>2</bitWidth> |
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| 154 | </field> |
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| 155 | <field> |
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| 156 | <name>MODER12</name> |
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| 157 | <description>Port x configuration bits (y = |
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| 158 | 0..15)</description> |
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| 159 | <bitOffset>24</bitOffset> |
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| 160 | <bitWidth>2</bitWidth> |
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| 161 | </field> |
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| 162 | <field> |
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| 163 | <name>MODER11</name> |
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| 164 | <description>Port x configuration bits (y = |
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| 165 | 0..15)</description> |
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| 166 | <bitOffset>22</bitOffset> |
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| 167 | <bitWidth>2</bitWidth> |
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| 168 | </field> |
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| 169 | <field> |
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| 170 | <name>MODER10</name> |
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| 171 | <description>Port x configuration bits (y = |
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| 172 | 0..15)</description> |
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| 173 | <bitOffset>20</bitOffset> |
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| 174 | <bitWidth>2</bitWidth> |
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| 175 | </field> |
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| 176 | <field> |
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| 177 | <name>MODER9</name> |
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| 178 | <description>Port x configuration bits (y = |
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| 179 | 0..15)</description> |
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| 180 | <bitOffset>18</bitOffset> |
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| 181 | <bitWidth>2</bitWidth> |
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| 182 | </field> |
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| 183 | <field> |
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| 184 | <name>MODER8</name> |
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| 185 | <description>Port x configuration bits (y = |
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| 186 | 0..15)</description> |
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| 187 | <bitOffset>16</bitOffset> |
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| 188 | <bitWidth>2</bitWidth> |
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| 189 | </field> |
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| 190 | <field> |
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| 191 | <name>MODER7</name> |
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| 192 | <description>Port x configuration bits (y = |
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| 193 | 0..15)</description> |
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| 194 | <bitOffset>14</bitOffset> |
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| 195 | <bitWidth>2</bitWidth> |
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| 196 | </field> |
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| 197 | <field> |
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| 198 | <name>MODER6</name> |
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| 199 | <description>Port x configuration bits (y = |
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| 200 | 0..15)</description> |
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| 201 | <bitOffset>12</bitOffset> |
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| 202 | <bitWidth>2</bitWidth> |
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| 203 | </field> |
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| 204 | <field> |
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| 205 | <name>MODER5</name> |
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| 206 | <description>Port x configuration bits (y = |
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| 207 | 0..15)</description> |
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| 208 | <bitOffset>10</bitOffset> |
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| 209 | <bitWidth>2</bitWidth> |
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| 210 | </field> |
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| 211 | <field> |
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| 212 | <name>MODER4</name> |
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| 213 | <description>Port x configuration bits (y = |
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| 214 | 0..15)</description> |
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| 215 | <bitOffset>8</bitOffset> |
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| 216 | <bitWidth>2</bitWidth> |
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| 217 | </field> |
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| 218 | <field> |
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| 219 | <name>MODER3</name> |
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| 220 | <description>Port x configuration bits (y = |
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| 221 | 0..15)</description> |
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| 222 | <bitOffset>6</bitOffset> |
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| 223 | <bitWidth>2</bitWidth> |
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| 224 | </field> |
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| 225 | <field> |
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| 226 | <name>MODER2</name> |
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| 227 | <description>Port x configuration bits (y = |
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| 228 | 0..15)</description> |
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| 229 | <bitOffset>4</bitOffset> |
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| 230 | <bitWidth>2</bitWidth> |
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| 231 | </field> |
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| 232 | <field> |
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| 233 | <name>MODER1</name> |
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| 234 | <description>Port x configuration bits (y = |
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| 235 | 0..15)</description> |
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| 236 | <bitOffset>2</bitOffset> |
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| 237 | <bitWidth>2</bitWidth> |
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| 238 | </field> |
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| 239 | <field> |
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| 240 | <name>MODER0</name> |
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| 241 | <description>Port x configuration bits (y = |
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| 242 | 0..15)</description> |
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| 243 | <bitOffset>0</bitOffset> |
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| 244 | <bitWidth>2</bitWidth> |
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| 245 | </field> |
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| 246 | </fields> |
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| 247 | </register> |
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| 248 | <register> |
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| 249 | <name>OTYPER</name> |
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| 250 | <displayName>OTYPER</displayName> |
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| 251 | <description>GPIO port output type register</description> |
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| 252 | <addressOffset>0x4</addressOffset> |
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| 253 | <size>0x20</size> |
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| 254 | <access>read-write</access> |
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| 255 | <resetValue>0x00000000</resetValue> |
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| 256 | <fields> |
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| 257 | <field> |
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| 258 | <name>OT15</name> |
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| 259 | <description>Port x configuration bit |
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| 260 | 15</description> |
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| 261 | <bitOffset>15</bitOffset> |
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| 262 | <bitWidth>1</bitWidth> |
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| 263 | </field> |
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| 264 | <field> |
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| 265 | <name>OT14</name> |
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| 266 | <description>Port x configuration bit |
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| 267 | 14</description> |
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| 268 | <bitOffset>14</bitOffset> |
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| 269 | <bitWidth>1</bitWidth> |
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| 270 | </field> |
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| 271 | <field> |
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| 272 | <name>OT13</name> |
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| 273 | <description>Port x configuration bit |
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| 274 | 13</description> |
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| 275 | <bitOffset>13</bitOffset> |
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| 276 | <bitWidth>1</bitWidth> |
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| 277 | </field> |
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| 278 | <field> |
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| 279 | <name>OT12</name> |
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| 280 | <description>Port x configuration bit |
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| 281 | 12</description> |
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| 282 | <bitOffset>12</bitOffset> |
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| 283 | <bitWidth>1</bitWidth> |
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| 284 | </field> |
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| 285 | <field> |
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| 286 | <name>OT11</name> |
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| 287 | <description>Port x configuration bit |
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| 288 | 11</description> |
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| 289 | <bitOffset>11</bitOffset> |
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| 290 | <bitWidth>1</bitWidth> |
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| 291 | </field> |
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| 292 | <field> |
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| 293 | <name>OT10</name> |
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| 294 | <description>Port x configuration bit |
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| 295 | 10</description> |
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| 296 | <bitOffset>10</bitOffset> |
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| 297 | <bitWidth>1</bitWidth> |
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| 298 | </field> |
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| 299 | <field> |
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| 300 | <name>OT9</name> |
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| 301 | <description>Port x configuration bit 9</description> |
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| 302 | <bitOffset>9</bitOffset> |
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| 303 | <bitWidth>1</bitWidth> |
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| 304 | </field> |
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| 305 | <field> |
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| 306 | <name>OT8</name> |
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| 307 | <description>Port x configuration bit 8</description> |
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| 308 | <bitOffset>8</bitOffset> |
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| 309 | <bitWidth>1</bitWidth> |
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| 310 | </field> |
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| 311 | <field> |
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| 312 | <name>OT7</name> |
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| 313 | <description>Port x configuration bit 7</description> |
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| 314 | <bitOffset>7</bitOffset> |
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| 315 | <bitWidth>1</bitWidth> |
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| 316 | </field> |
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| 317 | <field> |
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| 318 | <name>OT6</name> |
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| 319 | <description>Port x configuration bit 6</description> |
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| 320 | <bitOffset>6</bitOffset> |
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| 321 | <bitWidth>1</bitWidth> |
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| 322 | </field> |
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| 323 | <field> |
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| 324 | <name>OT5</name> |
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| 325 | <description>Port x configuration bit 5</description> |
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| 326 | <bitOffset>5</bitOffset> |
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| 327 | <bitWidth>1</bitWidth> |
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| 328 | </field> |
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| 329 | <field> |
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| 330 | <name>OT4</name> |
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| 331 | <description>Port x configuration bit 4</description> |
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| 332 | <bitOffset>4</bitOffset> |
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| 333 | <bitWidth>1</bitWidth> |
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| 334 | </field> |
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| 335 | <field> |
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| 336 | <name>OT3</name> |
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| 337 | <description>Port x configuration bit 3</description> |
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| 338 | <bitOffset>3</bitOffset> |
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| 339 | <bitWidth>1</bitWidth> |
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| 340 | </field> |
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| 341 | <field> |
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| 342 | <name>OT2</name> |
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| 343 | <description>Port x configuration bit 2</description> |
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| 344 | <bitOffset>2</bitOffset> |
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| 345 | <bitWidth>1</bitWidth> |
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| 346 | </field> |
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| 347 | <field> |
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| 348 | <name>OT1</name> |
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| 349 | <description>Port x configuration bit 1</description> |
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| 350 | <bitOffset>1</bitOffset> |
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| 351 | <bitWidth>1</bitWidth> |
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| 352 | </field> |
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| 353 | <field> |
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| 354 | <name>OT0</name> |
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| 355 | <description>Port x configuration bit 0</description> |
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| 356 | <bitOffset>0</bitOffset> |
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| 357 | <bitWidth>1</bitWidth> |
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| 358 | </field> |
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| 359 | </fields> |
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| 360 | </register> |
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| 361 | <register> |
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| 362 | <name>OSPEEDR</name> |
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| 363 | <displayName>OSPEEDR</displayName> |
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| 364 | <description>GPIO port output speed |
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| 365 | register</description> |
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| 366 | <addressOffset>0x8</addressOffset> |
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| 367 | <size>0x20</size> |
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| 368 | <access>read-write</access> |
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| 369 | <resetValue>0x00000000</resetValue> |
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| 370 | <fields> |
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| 371 | <field> |
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| 372 | <name>OSPEEDR15</name> |
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| 373 | <description>Port x configuration bits (y = |
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| 374 | 0..15)</description> |
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| 375 | <bitOffset>30</bitOffset> |
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| 376 | <bitWidth>2</bitWidth> |
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| 377 | </field> |
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| 378 | <field> |
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| 379 | <name>OSPEEDR14</name> |
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| 380 | <description>Port x configuration bits (y = |
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| 381 | 0..15)</description> |
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| 382 | <bitOffset>28</bitOffset> |
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| 383 | <bitWidth>2</bitWidth> |
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| 384 | </field> |
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| 385 | <field> |
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| 386 | <name>OSPEEDR13</name> |
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| 387 | <description>Port x configuration bits (y = |
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| 388 | 0..15)</description> |
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| 389 | <bitOffset>26</bitOffset> |
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| 390 | <bitWidth>2</bitWidth> |
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| 391 | </field> |
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| 392 | <field> |
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| 393 | <name>OSPEEDR12</name> |
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| 394 | <description>Port x configuration bits (y = |
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| 395 | 0..15)</description> |
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| 396 | <bitOffset>24</bitOffset> |
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| 397 | <bitWidth>2</bitWidth> |
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| 398 | </field> |
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| 399 | <field> |
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| 400 | <name>OSPEEDR11</name> |
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| 401 | <description>Port x configuration bits (y = |
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| 402 | 0..15)</description> |
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| 403 | <bitOffset>22</bitOffset> |
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| 404 | <bitWidth>2</bitWidth> |
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| 405 | </field> |
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| 406 | <field> |
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| 407 | <name>OSPEEDR10</name> |
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| 408 | <description>Port x configuration bits (y = |
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| 409 | 0..15)</description> |
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| 410 | <bitOffset>20</bitOffset> |
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| 411 | <bitWidth>2</bitWidth> |
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| 412 | </field> |
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| 413 | <field> |
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| 414 | <name>OSPEEDR9</name> |
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| 415 | <description>Port x configuration bits (y = |
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| 416 | 0..15)</description> |
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| 417 | <bitOffset>18</bitOffset> |
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| 418 | <bitWidth>2</bitWidth> |
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| 419 | </field> |
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| 420 | <field> |
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| 421 | <name>OSPEEDR8</name> |
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| 422 | <description>Port x configuration bits (y = |
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| 423 | 0..15)</description> |
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| 424 | <bitOffset>16</bitOffset> |
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| 425 | <bitWidth>2</bitWidth> |
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| 426 | </field> |
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| 427 | <field> |
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| 428 | <name>OSPEEDR7</name> |
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| 429 | <description>Port x configuration bits (y = |
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| 430 | 0..15)</description> |
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| 431 | <bitOffset>14</bitOffset> |
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| 432 | <bitWidth>2</bitWidth> |
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| 433 | </field> |
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| 434 | <field> |
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| 435 | <name>OSPEEDR6</name> |
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| 436 | <description>Port x configuration bits (y = |
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| 437 | 0..15)</description> |
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| 438 | <bitOffset>12</bitOffset> |
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| 439 | <bitWidth>2</bitWidth> |
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| 440 | </field> |
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| 441 | <field> |
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| 442 | <name>OSPEEDR5</name> |
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| 443 | <description>Port x configuration bits (y = |
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| 444 | 0..15)</description> |
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| 445 | <bitOffset>10</bitOffset> |
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| 446 | <bitWidth>2</bitWidth> |
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| 447 | </field> |
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| 448 | <field> |
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| 449 | <name>OSPEEDR4</name> |
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| 450 | <description>Port x configuration bits (y = |
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| 451 | 0..15)</description> |
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| 452 | <bitOffset>8</bitOffset> |
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| 453 | <bitWidth>2</bitWidth> |
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| 454 | </field> |
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| 455 | <field> |
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| 456 | <name>OSPEEDR3</name> |
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| 457 | <description>Port x configuration bits (y = |
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| 458 | 0..15)</description> |
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| 459 | <bitOffset>6</bitOffset> |
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| 460 | <bitWidth>2</bitWidth> |
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| 461 | </field> |
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| 462 | <field> |
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| 463 | <name>OSPEEDR2</name> |
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| 464 | <description>Port x configuration bits (y = |
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| 465 | 0..15)</description> |
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| 466 | <bitOffset>4</bitOffset> |
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| 467 | <bitWidth>2</bitWidth> |
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| 468 | </field> |
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| 469 | <field> |
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| 470 | <name>OSPEEDR1</name> |
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| 471 | <description>Port x configuration bits (y = |
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| 472 | 0..15)</description> |
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| 473 | <bitOffset>2</bitOffset> |
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| 474 | <bitWidth>2</bitWidth> |
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| 475 | </field> |
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| 476 | <field> |
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| 477 | <name>OSPEEDR0</name> |
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| 478 | <description>Port x configuration bits (y = |
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| 479 | 0..15)</description> |
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| 480 | <bitOffset>0</bitOffset> |
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| 481 | <bitWidth>2</bitWidth> |
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| 482 | </field> |
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| 483 | </fields> |
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| 484 | </register> |
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| 485 | <register> |
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| 486 | <name>PUPDR</name> |
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| 487 | <displayName>PUPDR</displayName> |
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| 488 | <description>GPIO port pull-up/pull-down |
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| 489 | register</description> |
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| 490 | <addressOffset>0xC</addressOffset> |
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| 491 | <size>0x20</size> |
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| 492 | <access>read-write</access> |
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| 493 | <resetValue>0x00000000</resetValue> |
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| 494 | <fields> |
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| 495 | <field> |
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| 496 | <name>PUPDR15</name> |
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| 497 | <description>Port x configuration bits (y = |
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| 498 | 0..15)</description> |
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| 499 | <bitOffset>30</bitOffset> |
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| 500 | <bitWidth>2</bitWidth> |
||
| 501 | </field> |
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| 502 | <field> |
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| 503 | <name>PUPDR14</name> |
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| 504 | <description>Port x configuration bits (y = |
||
| 505 | 0..15)</description> |
||
| 506 | <bitOffset>28</bitOffset> |
||
| 507 | <bitWidth>2</bitWidth> |
||
| 508 | </field> |
||
| 509 | <field> |
||
| 510 | <name>PUPDR13</name> |
||
| 511 | <description>Port x configuration bits (y = |
||
| 512 | 0..15)</description> |
||
| 513 | <bitOffset>26</bitOffset> |
||
| 514 | <bitWidth>2</bitWidth> |
||
| 515 | </field> |
||
| 516 | <field> |
||
| 517 | <name>PUPDR12</name> |
||
| 518 | <description>Port x configuration bits (y = |
||
| 519 | 0..15)</description> |
||
| 520 | <bitOffset>24</bitOffset> |
||
| 521 | <bitWidth>2</bitWidth> |
||
| 522 | </field> |
||
| 523 | <field> |
||
| 524 | <name>PUPDR11</name> |
||
| 525 | <description>Port x configuration bits (y = |
||
| 526 | 0..15)</description> |
||
| 527 | <bitOffset>22</bitOffset> |
||
| 528 | <bitWidth>2</bitWidth> |
||
| 529 | </field> |
||
| 530 | <field> |
||
| 531 | <name>PUPDR10</name> |
||
| 532 | <description>Port x configuration bits (y = |
||
| 533 | 0..15)</description> |
||
| 534 | <bitOffset>20</bitOffset> |
||
| 535 | <bitWidth>2</bitWidth> |
||
| 536 | </field> |
||
| 537 | <field> |
||
| 538 | <name>PUPDR9</name> |
||
| 539 | <description>Port x configuration bits (y = |
||
| 540 | 0..15)</description> |
||
| 541 | <bitOffset>18</bitOffset> |
||
| 542 | <bitWidth>2</bitWidth> |
||
| 543 | </field> |
||
| 544 | <field> |
||
| 545 | <name>PUPDR8</name> |
||
| 546 | <description>Port x configuration bits (y = |
||
| 547 | 0..15)</description> |
||
| 548 | <bitOffset>16</bitOffset> |
||
| 549 | <bitWidth>2</bitWidth> |
||
| 550 | </field> |
||
| 551 | <field> |
||
| 552 | <name>PUPDR7</name> |
||
| 553 | <description>Port x configuration bits (y = |
||
| 554 | 0..15)</description> |
||
| 555 | <bitOffset>14</bitOffset> |
||
| 556 | <bitWidth>2</bitWidth> |
||
| 557 | </field> |
||
| 558 | <field> |
||
| 559 | <name>PUPDR6</name> |
||
| 560 | <description>Port x configuration bits (y = |
||
| 561 | 0..15)</description> |
||
| 562 | <bitOffset>12</bitOffset> |
||
| 563 | <bitWidth>2</bitWidth> |
||
| 564 | </field> |
||
| 565 | <field> |
||
| 566 | <name>PUPDR5</name> |
||
| 567 | <description>Port x configuration bits (y = |
||
| 568 | 0..15)</description> |
||
| 569 | <bitOffset>10</bitOffset> |
||
| 570 | <bitWidth>2</bitWidth> |
||
| 571 | </field> |
||
| 572 | <field> |
||
| 573 | <name>PUPDR4</name> |
||
| 574 | <description>Port x configuration bits (y = |
||
| 575 | 0..15)</description> |
||
| 576 | <bitOffset>8</bitOffset> |
||
| 577 | <bitWidth>2</bitWidth> |
||
| 578 | </field> |
||
| 579 | <field> |
||
| 580 | <name>PUPDR3</name> |
||
| 581 | <description>Port x configuration bits (y = |
||
| 582 | 0..15)</description> |
||
| 583 | <bitOffset>6</bitOffset> |
||
| 584 | <bitWidth>2</bitWidth> |
||
| 585 | </field> |
||
| 586 | <field> |
||
| 587 | <name>PUPDR2</name> |
||
| 588 | <description>Port x configuration bits (y = |
||
| 589 | 0..15)</description> |
||
| 590 | <bitOffset>4</bitOffset> |
||
| 591 | <bitWidth>2</bitWidth> |
||
| 592 | </field> |
||
| 593 | <field> |
||
| 594 | <name>PUPDR1</name> |
||
| 595 | <description>Port x configuration bits (y = |
||
| 596 | 0..15)</description> |
||
| 597 | <bitOffset>2</bitOffset> |
||
| 598 | <bitWidth>2</bitWidth> |
||
| 599 | </field> |
||
| 600 | <field> |
||
| 601 | <name>PUPDR0</name> |
||
| 602 | <description>Port x configuration bits (y = |
||
| 603 | 0..15)</description> |
||
| 604 | <bitOffset>0</bitOffset> |
||
| 605 | <bitWidth>2</bitWidth> |
||
| 606 | </field> |
||
| 607 | </fields> |
||
| 608 | </register> |
||
| 609 | <register> |
||
| 610 | <name>IDR</name> |
||
| 611 | <displayName>IDR</displayName> |
||
| 612 | <description>GPIO port input data register</description> |
||
| 613 | <addressOffset>0x10</addressOffset> |
||
| 614 | <size>0x20</size> |
||
| 615 | <access>read-only</access> |
||
| 616 | <resetValue>0x00000000</resetValue> |
||
| 617 | <fields> |
||
| 618 | <field> |
||
| 619 | <name>IDR15</name> |
||
| 620 | <description>Port input data (y = |
||
| 621 | 0..15)</description> |
||
| 622 | <bitOffset>15</bitOffset> |
||
| 623 | <bitWidth>1</bitWidth> |
||
| 624 | </field> |
||
| 625 | <field> |
||
| 626 | <name>IDR14</name> |
||
| 627 | <description>Port input data (y = |
||
| 628 | 0..15)</description> |
||
| 629 | <bitOffset>14</bitOffset> |
||
| 630 | <bitWidth>1</bitWidth> |
||
| 631 | </field> |
||
| 632 | <field> |
||
| 633 | <name>IDR13</name> |
||
| 634 | <description>Port input data (y = |
||
| 635 | 0..15)</description> |
||
| 636 | <bitOffset>13</bitOffset> |
||
| 637 | <bitWidth>1</bitWidth> |
||
| 638 | </field> |
||
| 639 | <field> |
||
| 640 | <name>IDR12</name> |
||
| 641 | <description>Port input data (y = |
||
| 642 | 0..15)</description> |
||
| 643 | <bitOffset>12</bitOffset> |
||
| 644 | <bitWidth>1</bitWidth> |
||
| 645 | </field> |
||
| 646 | <field> |
||
| 647 | <name>IDR11</name> |
||
| 648 | <description>Port input data (y = |
||
| 649 | 0..15)</description> |
||
| 650 | <bitOffset>11</bitOffset> |
||
| 651 | <bitWidth>1</bitWidth> |
||
| 652 | </field> |
||
| 653 | <field> |
||
| 654 | <name>IDR10</name> |
||
| 655 | <description>Port input data (y = |
||
| 656 | 0..15)</description> |
||
| 657 | <bitOffset>10</bitOffset> |
||
| 658 | <bitWidth>1</bitWidth> |
||
| 659 | </field> |
||
| 660 | <field> |
||
| 661 | <name>IDR9</name> |
||
| 662 | <description>Port input data (y = |
||
| 663 | 0..15)</description> |
||
| 664 | <bitOffset>9</bitOffset> |
||
| 665 | <bitWidth>1</bitWidth> |
||
| 666 | </field> |
||
| 667 | <field> |
||
| 668 | <name>IDR8</name> |
||
| 669 | <description>Port input data (y = |
||
| 670 | 0..15)</description> |
||
| 671 | <bitOffset>8</bitOffset> |
||
| 672 | <bitWidth>1</bitWidth> |
||
| 673 | </field> |
||
| 674 | <field> |
||
| 675 | <name>IDR7</name> |
||
| 676 | <description>Port input data (y = |
||
| 677 | 0..15)</description> |
||
| 678 | <bitOffset>7</bitOffset> |
||
| 679 | <bitWidth>1</bitWidth> |
||
| 680 | </field> |
||
| 681 | <field> |
||
| 682 | <name>IDR6</name> |
||
| 683 | <description>Port input data (y = |
||
| 684 | 0..15)</description> |
||
| 685 | <bitOffset>6</bitOffset> |
||
| 686 | <bitWidth>1</bitWidth> |
||
| 687 | </field> |
||
| 688 | <field> |
||
| 689 | <name>IDR5</name> |
||
| 690 | <description>Port input data (y = |
||
| 691 | 0..15)</description> |
||
| 692 | <bitOffset>5</bitOffset> |
||
| 693 | <bitWidth>1</bitWidth> |
||
| 694 | </field> |
||
| 695 | <field> |
||
| 696 | <name>IDR4</name> |
||
| 697 | <description>Port input data (y = |
||
| 698 | 0..15)</description> |
||
| 699 | <bitOffset>4</bitOffset> |
||
| 700 | <bitWidth>1</bitWidth> |
||
| 701 | </field> |
||
| 702 | <field> |
||
| 703 | <name>IDR3</name> |
||
| 704 | <description>Port input data (y = |
||
| 705 | 0..15)</description> |
||
| 706 | <bitOffset>3</bitOffset> |
||
| 707 | <bitWidth>1</bitWidth> |
||
| 708 | </field> |
||
| 709 | <field> |
||
| 710 | <name>IDR2</name> |
||
| 711 | <description>Port input data (y = |
||
| 712 | 0..15)</description> |
||
| 713 | <bitOffset>2</bitOffset> |
||
| 714 | <bitWidth>1</bitWidth> |
||
| 715 | </field> |
||
| 716 | <field> |
||
| 717 | <name>IDR1</name> |
||
| 718 | <description>Port input data (y = |
||
| 719 | 0..15)</description> |
||
| 720 | <bitOffset>1</bitOffset> |
||
| 721 | <bitWidth>1</bitWidth> |
||
| 722 | </field> |
||
| 723 | <field> |
||
| 724 | <name>IDR0</name> |
||
| 725 | <description>Port input data (y = |
||
| 726 | 0..15)</description> |
||
| 727 | <bitOffset>0</bitOffset> |
||
| 728 | <bitWidth>1</bitWidth> |
||
| 729 | </field> |
||
| 730 | </fields> |
||
| 731 | </register> |
||
| 732 | <register> |
||
| 733 | <name>ODR</name> |
||
| 734 | <displayName>ODR</displayName> |
||
| 735 | <description>GPIO port output data register</description> |
||
| 736 | <addressOffset>0x14</addressOffset> |
||
| 737 | <size>0x20</size> |
||
| 738 | <access>read-write</access> |
||
| 739 | <resetValue>0x00000000</resetValue> |
||
| 740 | <fields> |
||
| 741 | <field> |
||
| 742 | <name>ODR15</name> |
||
| 743 | <description>Port output data (y = |
||
| 744 | 0..15)</description> |
||
| 745 | <bitOffset>15</bitOffset> |
||
| 746 | <bitWidth>1</bitWidth> |
||
| 747 | </field> |
||
| 748 | <field> |
||
| 749 | <name>ODR14</name> |
||
| 750 | <description>Port output data (y = |
||
| 751 | 0..15)</description> |
||
| 752 | <bitOffset>14</bitOffset> |
||
| 753 | <bitWidth>1</bitWidth> |
||
| 754 | </field> |
||
| 755 | <field> |
||
| 756 | <name>ODR13</name> |
||
| 757 | <description>Port output data (y = |
||
| 758 | 0..15)</description> |
||
| 759 | <bitOffset>13</bitOffset> |
||
| 760 | <bitWidth>1</bitWidth> |
||
| 761 | </field> |
||
| 762 | <field> |
||
| 763 | <name>ODR12</name> |
||
| 764 | <description>Port output data (y = |
||
| 765 | 0..15)</description> |
||
| 766 | <bitOffset>12</bitOffset> |
||
| 767 | <bitWidth>1</bitWidth> |
||
| 768 | </field> |
||
| 769 | <field> |
||
| 770 | <name>ODR11</name> |
||
| 771 | <description>Port output data (y = |
||
| 772 | 0..15)</description> |
||
| 773 | <bitOffset>11</bitOffset> |
||
| 774 | <bitWidth>1</bitWidth> |
||
| 775 | </field> |
||
| 776 | <field> |
||
| 777 | <name>ODR10</name> |
||
| 778 | <description>Port output data (y = |
||
| 779 | 0..15)</description> |
||
| 780 | <bitOffset>10</bitOffset> |
||
| 781 | <bitWidth>1</bitWidth> |
||
| 782 | </field> |
||
| 783 | <field> |
||
| 784 | <name>ODR9</name> |
||
| 785 | <description>Port output data (y = |
||
| 786 | 0..15)</description> |
||
| 787 | <bitOffset>9</bitOffset> |
||
| 788 | <bitWidth>1</bitWidth> |
||
| 789 | </field> |
||
| 790 | <field> |
||
| 791 | <name>ODR8</name> |
||
| 792 | <description>Port output data (y = |
||
| 793 | 0..15)</description> |
||
| 794 | <bitOffset>8</bitOffset> |
||
| 795 | <bitWidth>1</bitWidth> |
||
| 796 | </field> |
||
| 797 | <field> |
||
| 798 | <name>ODR7</name> |
||
| 799 | <description>Port output data (y = |
||
| 800 | 0..15)</description> |
||
| 801 | <bitOffset>7</bitOffset> |
||
| 802 | <bitWidth>1</bitWidth> |
||
| 803 | </field> |
||
| 804 | <field> |
||
| 805 | <name>ODR6</name> |
||
| 806 | <description>Port output data (y = |
||
| 807 | 0..15)</description> |
||
| 808 | <bitOffset>6</bitOffset> |
||
| 809 | <bitWidth>1</bitWidth> |
||
| 810 | </field> |
||
| 811 | <field> |
||
| 812 | <name>ODR5</name> |
||
| 813 | <description>Port output data (y = |
||
| 814 | 0..15)</description> |
||
| 815 | <bitOffset>5</bitOffset> |
||
| 816 | <bitWidth>1</bitWidth> |
||
| 817 | </field> |
||
| 818 | <field> |
||
| 819 | <name>ODR4</name> |
||
| 820 | <description>Port output data (y = |
||
| 821 | 0..15)</description> |
||
| 822 | <bitOffset>4</bitOffset> |
||
| 823 | <bitWidth>1</bitWidth> |
||
| 824 | </field> |
||
| 825 | <field> |
||
| 826 | <name>ODR3</name> |
||
| 827 | <description>Port output data (y = |
||
| 828 | 0..15)</description> |
||
| 829 | <bitOffset>3</bitOffset> |
||
| 830 | <bitWidth>1</bitWidth> |
||
| 831 | </field> |
||
| 832 | <field> |
||
| 833 | <name>ODR2</name> |
||
| 834 | <description>Port output data (y = |
||
| 835 | 0..15)</description> |
||
| 836 | <bitOffset>2</bitOffset> |
||
| 837 | <bitWidth>1</bitWidth> |
||
| 838 | </field> |
||
| 839 | <field> |
||
| 840 | <name>ODR1</name> |
||
| 841 | <description>Port output data (y = |
||
| 842 | 0..15)</description> |
||
| 843 | <bitOffset>1</bitOffset> |
||
| 844 | <bitWidth>1</bitWidth> |
||
| 845 | </field> |
||
| 846 | <field> |
||
| 847 | <name>ODR0</name> |
||
| 848 | <description>Port output data (y = |
||
| 849 | 0..15)</description> |
||
| 850 | <bitOffset>0</bitOffset> |
||
| 851 | <bitWidth>1</bitWidth> |
||
| 852 | </field> |
||
| 853 | </fields> |
||
| 854 | </register> |
||
| 855 | <register> |
||
| 856 | <name>BSRR</name> |
||
| 857 | <displayName>BSRR</displayName> |
||
| 858 | <description>GPIO port bit set/reset |
||
| 859 | register</description> |
||
| 860 | <addressOffset>0x18</addressOffset> |
||
| 861 | <size>0x20</size> |
||
| 862 | <access>write-only</access> |
||
| 863 | <resetValue>0x00000000</resetValue> |
||
| 864 | <fields> |
||
| 865 | <field> |
||
| 866 | <name>BR15</name> |
||
| 867 | <description>Port x reset bit y (y = |
||
| 868 | 0..15)</description> |
||
| 869 | <bitOffset>31</bitOffset> |
||
| 870 | <bitWidth>1</bitWidth> |
||
| 871 | </field> |
||
| 872 | <field> |
||
| 873 | <name>BR14</name> |
||
| 874 | <description>Port x reset bit y (y = |
||
| 875 | 0..15)</description> |
||
| 876 | <bitOffset>30</bitOffset> |
||
| 877 | <bitWidth>1</bitWidth> |
||
| 878 | </field> |
||
| 879 | <field> |
||
| 880 | <name>BR13</name> |
||
| 881 | <description>Port x reset bit y (y = |
||
| 882 | 0..15)</description> |
||
| 883 | <bitOffset>29</bitOffset> |
||
| 884 | <bitWidth>1</bitWidth> |
||
| 885 | </field> |
||
| 886 | <field> |
||
| 887 | <name>BR12</name> |
||
| 888 | <description>Port x reset bit y (y = |
||
| 889 | 0..15)</description> |
||
| 890 | <bitOffset>28</bitOffset> |
||
| 891 | <bitWidth>1</bitWidth> |
||
| 892 | </field> |
||
| 893 | <field> |
||
| 894 | <name>BR11</name> |
||
| 895 | <description>Port x reset bit y (y = |
||
| 896 | 0..15)</description> |
||
| 897 | <bitOffset>27</bitOffset> |
||
| 898 | <bitWidth>1</bitWidth> |
||
| 899 | </field> |
||
| 900 | <field> |
||
| 901 | <name>BR10</name> |
||
| 902 | <description>Port x reset bit y (y = |
||
| 903 | 0..15)</description> |
||
| 904 | <bitOffset>26</bitOffset> |
||
| 905 | <bitWidth>1</bitWidth> |
||
| 906 | </field> |
||
| 907 | <field> |
||
| 908 | <name>BR9</name> |
||
| 909 | <description>Port x reset bit y (y = |
||
| 910 | 0..15)</description> |
||
| 911 | <bitOffset>25</bitOffset> |
||
| 912 | <bitWidth>1</bitWidth> |
||
| 913 | </field> |
||
| 914 | <field> |
||
| 915 | <name>BR8</name> |
||
| 916 | <description>Port x reset bit y (y = |
||
| 917 | 0..15)</description> |
||
| 918 | <bitOffset>24</bitOffset> |
||
| 919 | <bitWidth>1</bitWidth> |
||
| 920 | </field> |
||
| 921 | <field> |
||
| 922 | <name>BR7</name> |
||
| 923 | <description>Port x reset bit y (y = |
||
| 924 | 0..15)</description> |
||
| 925 | <bitOffset>23</bitOffset> |
||
| 926 | <bitWidth>1</bitWidth> |
||
| 927 | </field> |
||
| 928 | <field> |
||
| 929 | <name>BR6</name> |
||
| 930 | <description>Port x reset bit y (y = |
||
| 931 | 0..15)</description> |
||
| 932 | <bitOffset>22</bitOffset> |
||
| 933 | <bitWidth>1</bitWidth> |
||
| 934 | </field> |
||
| 935 | <field> |
||
| 936 | <name>BR5</name> |
||
| 937 | <description>Port x reset bit y (y = |
||
| 938 | 0..15)</description> |
||
| 939 | <bitOffset>21</bitOffset> |
||
| 940 | <bitWidth>1</bitWidth> |
||
| 941 | </field> |
||
| 942 | <field> |
||
| 943 | <name>BR4</name> |
||
| 944 | <description>Port x reset bit y (y = |
||
| 945 | 0..15)</description> |
||
| 946 | <bitOffset>20</bitOffset> |
||
| 947 | <bitWidth>1</bitWidth> |
||
| 948 | </field> |
||
| 949 | <field> |
||
| 950 | <name>BR3</name> |
||
| 951 | <description>Port x reset bit y (y = |
||
| 952 | 0..15)</description> |
||
| 953 | <bitOffset>19</bitOffset> |
||
| 954 | <bitWidth>1</bitWidth> |
||
| 955 | </field> |
||
| 956 | <field> |
||
| 957 | <name>BR2</name> |
||
| 958 | <description>Port x reset bit y (y = |
||
| 959 | 0..15)</description> |
||
| 960 | <bitOffset>18</bitOffset> |
||
| 961 | <bitWidth>1</bitWidth> |
||
| 962 | </field> |
||
| 963 | <field> |
||
| 964 | <name>BR1</name> |
||
| 965 | <description>Port x reset bit y (y = |
||
| 966 | 0..15)</description> |
||
| 967 | <bitOffset>17</bitOffset> |
||
| 968 | <bitWidth>1</bitWidth> |
||
| 969 | </field> |
||
| 970 | <field> |
||
| 971 | <name>BR0</name> |
||
| 972 | <description>Port x set bit y (y= |
||
| 973 | 0..15)</description> |
||
| 974 | <bitOffset>16</bitOffset> |
||
| 975 | <bitWidth>1</bitWidth> |
||
| 976 | </field> |
||
| 977 | <field> |
||
| 978 | <name>BS15</name> |
||
| 979 | <description>Port x set bit y (y= |
||
| 980 | 0..15)</description> |
||
| 981 | <bitOffset>15</bitOffset> |
||
| 982 | <bitWidth>1</bitWidth> |
||
| 983 | </field> |
||
| 984 | <field> |
||
| 985 | <name>BS14</name> |
||
| 986 | <description>Port x set bit y (y= |
||
| 987 | 0..15)</description> |
||
| 988 | <bitOffset>14</bitOffset> |
||
| 989 | <bitWidth>1</bitWidth> |
||
| 990 | </field> |
||
| 991 | <field> |
||
| 992 | <name>BS13</name> |
||
| 993 | <description>Port x set bit y (y= |
||
| 994 | 0..15)</description> |
||
| 995 | <bitOffset>13</bitOffset> |
||
| 996 | <bitWidth>1</bitWidth> |
||
| 997 | </field> |
||
| 998 | <field> |
||
| 999 | <name>BS12</name> |
||
| 1000 | <description>Port x set bit y (y= |
||
| 1001 | 0..15)</description> |
||
| 1002 | <bitOffset>12</bitOffset> |
||
| 1003 | <bitWidth>1</bitWidth> |
||
| 1004 | </field> |
||
| 1005 | <field> |
||
| 1006 | <name>BS11</name> |
||
| 1007 | <description>Port x set bit y (y= |
||
| 1008 | 0..15)</description> |
||
| 1009 | <bitOffset>11</bitOffset> |
||
| 1010 | <bitWidth>1</bitWidth> |
||
| 1011 | </field> |
||
| 1012 | <field> |
||
| 1013 | <name>BS10</name> |
||
| 1014 | <description>Port x set bit y (y= |
||
| 1015 | 0..15)</description> |
||
| 1016 | <bitOffset>10</bitOffset> |
||
| 1017 | <bitWidth>1</bitWidth> |
||
| 1018 | </field> |
||
| 1019 | <field> |
||
| 1020 | <name>BS9</name> |
||
| 1021 | <description>Port x set bit y (y= |
||
| 1022 | 0..15)</description> |
||
| 1023 | <bitOffset>9</bitOffset> |
||
| 1024 | <bitWidth>1</bitWidth> |
||
| 1025 | </field> |
||
| 1026 | <field> |
||
| 1027 | <name>BS8</name> |
||
| 1028 | <description>Port x set bit y (y= |
||
| 1029 | 0..15)</description> |
||
| 1030 | <bitOffset>8</bitOffset> |
||
| 1031 | <bitWidth>1</bitWidth> |
||
| 1032 | </field> |
||
| 1033 | <field> |
||
| 1034 | <name>BS7</name> |
||
| 1035 | <description>Port x set bit y (y= |
||
| 1036 | 0..15)</description> |
||
| 1037 | <bitOffset>7</bitOffset> |
||
| 1038 | <bitWidth>1</bitWidth> |
||
| 1039 | </field> |
||
| 1040 | <field> |
||
| 1041 | <name>BS6</name> |
||
| 1042 | <description>Port x set bit y (y= |
||
| 1043 | 0..15)</description> |
||
| 1044 | <bitOffset>6</bitOffset> |
||
| 1045 | <bitWidth>1</bitWidth> |
||
| 1046 | </field> |
||
| 1047 | <field> |
||
| 1048 | <name>BS5</name> |
||
| 1049 | <description>Port x set bit y (y= |
||
| 1050 | 0..15)</description> |
||
| 1051 | <bitOffset>5</bitOffset> |
||
| 1052 | <bitWidth>1</bitWidth> |
||
| 1053 | </field> |
||
| 1054 | <field> |
||
| 1055 | <name>BS4</name> |
||
| 1056 | <description>Port x set bit y (y= |
||
| 1057 | 0..15)</description> |
||
| 1058 | <bitOffset>4</bitOffset> |
||
| 1059 | <bitWidth>1</bitWidth> |
||
| 1060 | </field> |
||
| 1061 | <field> |
||
| 1062 | <name>BS3</name> |
||
| 1063 | <description>Port x set bit y (y= |
||
| 1064 | 0..15)</description> |
||
| 1065 | <bitOffset>3</bitOffset> |
||
| 1066 | <bitWidth>1</bitWidth> |
||
| 1067 | </field> |
||
| 1068 | <field> |
||
| 1069 | <name>BS2</name> |
||
| 1070 | <description>Port x set bit y (y= |
||
| 1071 | 0..15)</description> |
||
| 1072 | <bitOffset>2</bitOffset> |
||
| 1073 | <bitWidth>1</bitWidth> |
||
| 1074 | </field> |
||
| 1075 | <field> |
||
| 1076 | <name>BS1</name> |
||
| 1077 | <description>Port x set bit y (y= |
||
| 1078 | 0..15)</description> |
||
| 1079 | <bitOffset>1</bitOffset> |
||
| 1080 | <bitWidth>1</bitWidth> |
||
| 1081 | </field> |
||
| 1082 | <field> |
||
| 1083 | <name>BS0</name> |
||
| 1084 | <description>Port x set bit y (y= |
||
| 1085 | 0..15)</description> |
||
| 1086 | <bitOffset>0</bitOffset> |
||
| 1087 | <bitWidth>1</bitWidth> |
||
| 1088 | </field> |
||
| 1089 | </fields> |
||
| 1090 | </register> |
||
| 1091 | <register> |
||
| 1092 | <name>LCKR</name> |
||
| 1093 | <displayName>LCKR</displayName> |
||
| 1094 | <description>GPIO port configuration lock |
||
| 1095 | register</description> |
||
| 1096 | <addressOffset>0x1C</addressOffset> |
||
| 1097 | <size>0x20</size> |
||
| 1098 | <access>read-write</access> |
||
| 1099 | <resetValue>0x00000000</resetValue> |
||
| 1100 | <fields> |
||
| 1101 | <field> |
||
| 1102 | <name>LCKK</name> |
||
| 1103 | <description>Port x lock bit y</description> |
||
| 1104 | <bitOffset>16</bitOffset> |
||
| 1105 | <bitWidth>1</bitWidth> |
||
| 1106 | </field> |
||
| 1107 | <field> |
||
| 1108 | <name>LCK15</name> |
||
| 1109 | <description>Port x lock bit y (y= |
||
| 1110 | 0..15)</description> |
||
| 1111 | <bitOffset>15</bitOffset> |
||
| 1112 | <bitWidth>1</bitWidth> |
||
| 1113 | </field> |
||
| 1114 | <field> |
||
| 1115 | <name>LCK14</name> |
||
| 1116 | <description>Port x lock bit y (y= |
||
| 1117 | 0..15)</description> |
||
| 1118 | <bitOffset>14</bitOffset> |
||
| 1119 | <bitWidth>1</bitWidth> |
||
| 1120 | </field> |
||
| 1121 | <field> |
||
| 1122 | <name>LCK13</name> |
||
| 1123 | <description>Port x lock bit y (y= |
||
| 1124 | 0..15)</description> |
||
| 1125 | <bitOffset>13</bitOffset> |
||
| 1126 | <bitWidth>1</bitWidth> |
||
| 1127 | </field> |
||
| 1128 | <field> |
||
| 1129 | <name>LCK12</name> |
||
| 1130 | <description>Port x lock bit y (y= |
||
| 1131 | 0..15)</description> |
||
| 1132 | <bitOffset>12</bitOffset> |
||
| 1133 | <bitWidth>1</bitWidth> |
||
| 1134 | </field> |
||
| 1135 | <field> |
||
| 1136 | <name>LCK11</name> |
||
| 1137 | <description>Port x lock bit y (y= |
||
| 1138 | 0..15)</description> |
||
| 1139 | <bitOffset>11</bitOffset> |
||
| 1140 | <bitWidth>1</bitWidth> |
||
| 1141 | </field> |
||
| 1142 | <field> |
||
| 1143 | <name>LCK10</name> |
||
| 1144 | <description>Port x lock bit y (y= |
||
| 1145 | 0..15)</description> |
||
| 1146 | <bitOffset>10</bitOffset> |
||
| 1147 | <bitWidth>1</bitWidth> |
||
| 1148 | </field> |
||
| 1149 | <field> |
||
| 1150 | <name>LCK9</name> |
||
| 1151 | <description>Port x lock bit y (y= |
||
| 1152 | 0..15)</description> |
||
| 1153 | <bitOffset>9</bitOffset> |
||
| 1154 | <bitWidth>1</bitWidth> |
||
| 1155 | </field> |
||
| 1156 | <field> |
||
| 1157 | <name>LCK8</name> |
||
| 1158 | <description>Port x lock bit y (y= |
||
| 1159 | 0..15)</description> |
||
| 1160 | <bitOffset>8</bitOffset> |
||
| 1161 | <bitWidth>1</bitWidth> |
||
| 1162 | </field> |
||
| 1163 | <field> |
||
| 1164 | <name>LCK7</name> |
||
| 1165 | <description>Port x lock bit y (y= |
||
| 1166 | 0..15)</description> |
||
| 1167 | <bitOffset>7</bitOffset> |
||
| 1168 | <bitWidth>1</bitWidth> |
||
| 1169 | </field> |
||
| 1170 | <field> |
||
| 1171 | <name>LCK6</name> |
||
| 1172 | <description>Port x lock bit y (y= |
||
| 1173 | 0..15)</description> |
||
| 1174 | <bitOffset>6</bitOffset> |
||
| 1175 | <bitWidth>1</bitWidth> |
||
| 1176 | </field> |
||
| 1177 | <field> |
||
| 1178 | <name>LCK5</name> |
||
| 1179 | <description>Port x lock bit y (y= |
||
| 1180 | 0..15)</description> |
||
| 1181 | <bitOffset>5</bitOffset> |
||
| 1182 | <bitWidth>1</bitWidth> |
||
| 1183 | </field> |
||
| 1184 | <field> |
||
| 1185 | <name>LCK4</name> |
||
| 1186 | <description>Port x lock bit y (y= |
||
| 1187 | 0..15)</description> |
||
| 1188 | <bitOffset>4</bitOffset> |
||
| 1189 | <bitWidth>1</bitWidth> |
||
| 1190 | </field> |
||
| 1191 | <field> |
||
| 1192 | <name>LCK3</name> |
||
| 1193 | <description>Port x lock bit y (y= |
||
| 1194 | 0..15)</description> |
||
| 1195 | <bitOffset>3</bitOffset> |
||
| 1196 | <bitWidth>1</bitWidth> |
||
| 1197 | </field> |
||
| 1198 | <field> |
||
| 1199 | <name>LCK2</name> |
||
| 1200 | <description>Port x lock bit y (y= |
||
| 1201 | 0..15)</description> |
||
| 1202 | <bitOffset>2</bitOffset> |
||
| 1203 | <bitWidth>1</bitWidth> |
||
| 1204 | </field> |
||
| 1205 | <field> |
||
| 1206 | <name>LCK1</name> |
||
| 1207 | <description>Port x lock bit y (y= |
||
| 1208 | 0..15)</description> |
||
| 1209 | <bitOffset>1</bitOffset> |
||
| 1210 | <bitWidth>1</bitWidth> |
||
| 1211 | </field> |
||
| 1212 | <field> |
||
| 1213 | <name>LCK0</name> |
||
| 1214 | <description>Port x lock bit y (y= |
||
| 1215 | 0..15)</description> |
||
| 1216 | <bitOffset>0</bitOffset> |
||
| 1217 | <bitWidth>1</bitWidth> |
||
| 1218 | </field> |
||
| 1219 | </fields> |
||
| 1220 | </register> |
||
| 1221 | <register> |
||
| 1222 | <name>AFRL</name> |
||
| 1223 | <displayName>AFRL</displayName> |
||
| 1224 | <description>GPIO alternate function low |
||
| 1225 | register</description> |
||
| 1226 | <addressOffset>0x20</addressOffset> |
||
| 1227 | <size>0x20</size> |
||
| 1228 | <access>read-write</access> |
||
| 1229 | <resetValue>0x00000000</resetValue> |
||
| 1230 | <fields> |
||
| 1231 | <field> |
||
| 1232 | <name>AFRL7</name> |
||
| 1233 | <description>Alternate function selection for port x |
||
| 1234 | bit y (y = 0..7)</description> |
||
| 1235 | <bitOffset>28</bitOffset> |
||
| 1236 | <bitWidth>4</bitWidth> |
||
| 1237 | </field> |
||
| 1238 | <field> |
||
| 1239 | <name>AFRL6</name> |
||
| 1240 | <description>Alternate function selection for port x |
||
| 1241 | bit y (y = 0..7)</description> |
||
| 1242 | <bitOffset>24</bitOffset> |
||
| 1243 | <bitWidth>4</bitWidth> |
||
| 1244 | </field> |
||
| 1245 | <field> |
||
| 1246 | <name>AFRL5</name> |
||
| 1247 | <description>Alternate function selection for port x |
||
| 1248 | bit y (y = 0..7)</description> |
||
| 1249 | <bitOffset>20</bitOffset> |
||
| 1250 | <bitWidth>4</bitWidth> |
||
| 1251 | </field> |
||
| 1252 | <field> |
||
| 1253 | <name>AFRL4</name> |
||
| 1254 | <description>Alternate function selection for port x |
||
| 1255 | bit y (y = 0..7)</description> |
||
| 1256 | <bitOffset>16</bitOffset> |
||
| 1257 | <bitWidth>4</bitWidth> |
||
| 1258 | </field> |
||
| 1259 | <field> |
||
| 1260 | <name>AFRL3</name> |
||
| 1261 | <description>Alternate function selection for port x |
||
| 1262 | bit y (y = 0..7)</description> |
||
| 1263 | <bitOffset>12</bitOffset> |
||
| 1264 | <bitWidth>4</bitWidth> |
||
| 1265 | </field> |
||
| 1266 | <field> |
||
| 1267 | <name>AFRL2</name> |
||
| 1268 | <description>Alternate function selection for port x |
||
| 1269 | bit y (y = 0..7)</description> |
||
| 1270 | <bitOffset>8</bitOffset> |
||
| 1271 | <bitWidth>4</bitWidth> |
||
| 1272 | </field> |
||
| 1273 | <field> |
||
| 1274 | <name>AFRL1</name> |
||
| 1275 | <description>Alternate function selection for port x |
||
| 1276 | bit y (y = 0..7)</description> |
||
| 1277 | <bitOffset>4</bitOffset> |
||
| 1278 | <bitWidth>4</bitWidth> |
||
| 1279 | </field> |
||
| 1280 | <field> |
||
| 1281 | <name>AFRL0</name> |
||
| 1282 | <description>Alternate function selection for port x |
||
| 1283 | bit y (y = 0..7)</description> |
||
| 1284 | <bitOffset>0</bitOffset> |
||
| 1285 | <bitWidth>4</bitWidth> |
||
| 1286 | </field> |
||
| 1287 | </fields> |
||
| 1288 | </register> |
||
| 1289 | <register> |
||
| 1290 | <name>AFRH</name> |
||
| 1291 | <displayName>AFRH</displayName> |
||
| 1292 | <description>GPIO alternate function high |
||
| 1293 | register</description> |
||
| 1294 | <addressOffset>0x24</addressOffset> |
||
| 1295 | <size>0x20</size> |
||
| 1296 | <access>read-write</access> |
||
| 1297 | <resetValue>0x00000000</resetValue> |
||
| 1298 | <fields> |
||
| 1299 | <field> |
||
| 1300 | <name>AFRH15</name> |
||
| 1301 | <description>Alternate function selection for port x |
||
| 1302 | bit y (y = 8..15)</description> |
||
| 1303 | <bitOffset>28</bitOffset> |
||
| 1304 | <bitWidth>4</bitWidth> |
||
| 1305 | </field> |
||
| 1306 | <field> |
||
| 1307 | <name>AFRH14</name> |
||
| 1308 | <description>Alternate function selection for port x |
||
| 1309 | bit y (y = 8..15)</description> |
||
| 1310 | <bitOffset>24</bitOffset> |
||
| 1311 | <bitWidth>4</bitWidth> |
||
| 1312 | </field> |
||
| 1313 | <field> |
||
| 1314 | <name>AFRH13</name> |
||
| 1315 | <description>Alternate function selection for port x |
||
| 1316 | bit y (y = 8..15)</description> |
||
| 1317 | <bitOffset>20</bitOffset> |
||
| 1318 | <bitWidth>4</bitWidth> |
||
| 1319 | </field> |
||
| 1320 | <field> |
||
| 1321 | <name>AFRH12</name> |
||
| 1322 | <description>Alternate function selection for port x |
||
| 1323 | bit y (y = 8..15)</description> |
||
| 1324 | <bitOffset>16</bitOffset> |
||
| 1325 | <bitWidth>4</bitWidth> |
||
| 1326 | </field> |
||
| 1327 | <field> |
||
| 1328 | <name>AFRH11</name> |
||
| 1329 | <description>Alternate function selection for port x |
||
| 1330 | bit y (y = 8..15)</description> |
||
| 1331 | <bitOffset>12</bitOffset> |
||
| 1332 | <bitWidth>4</bitWidth> |
||
| 1333 | </field> |
||
| 1334 | <field> |
||
| 1335 | <name>AFRH10</name> |
||
| 1336 | <description>Alternate function selection for port x |
||
| 1337 | bit y (y = 8..15)</description> |
||
| 1338 | <bitOffset>8</bitOffset> |
||
| 1339 | <bitWidth>4</bitWidth> |
||
| 1340 | </field> |
||
| 1341 | <field> |
||
| 1342 | <name>AFRH9</name> |
||
| 1343 | <description>Alternate function selection for port x |
||
| 1344 | bit y (y = 8..15)</description> |
||
| 1345 | <bitOffset>4</bitOffset> |
||
| 1346 | <bitWidth>4</bitWidth> |
||
| 1347 | </field> |
||
| 1348 | <field> |
||
| 1349 | <name>AFRH8</name> |
||
| 1350 | <description>Alternate function selection for port x |
||
| 1351 | bit y (y = 8..15)</description> |
||
| 1352 | <bitOffset>0</bitOffset> |
||
| 1353 | <bitWidth>4</bitWidth> |
||
| 1354 | </field> |
||
| 1355 | </fields> |
||
| 1356 | </register> |
||
| 1357 | <register> |
||
| 1358 | <name>BRR</name> |
||
| 1359 | <displayName>BRR</displayName> |
||
| 1360 | <description>Port bit reset register</description> |
||
| 1361 | <addressOffset>0x28</addressOffset> |
||
| 1362 | <size>0x20</size> |
||
| 1363 | <access>write-only</access> |
||
| 1364 | <resetValue>0x00000000</resetValue> |
||
| 1365 | <fields> |
||
| 1366 | <field> |
||
| 1367 | <name>BR0</name> |
||
| 1368 | <description>Port x Reset bit y</description> |
||
| 1369 | <bitOffset>0</bitOffset> |
||
| 1370 | <bitWidth>1</bitWidth> |
||
| 1371 | </field> |
||
| 1372 | <field> |
||
| 1373 | <name>BR1</name> |
||
| 1374 | <description>Port x Reset bit y</description> |
||
| 1375 | <bitOffset>1</bitOffset> |
||
| 1376 | <bitWidth>1</bitWidth> |
||
| 1377 | </field> |
||
| 1378 | <field> |
||
| 1379 | <name>BR2</name> |
||
| 1380 | <description>Port x Reset bit y</description> |
||
| 1381 | <bitOffset>2</bitOffset> |
||
| 1382 | <bitWidth>1</bitWidth> |
||
| 1383 | </field> |
||
| 1384 | <field> |
||
| 1385 | <name>BR3</name> |
||
| 1386 | <description>Port x Reset bit y</description> |
||
| 1387 | <bitOffset>3</bitOffset> |
||
| 1388 | <bitWidth>1</bitWidth> |
||
| 1389 | </field> |
||
| 1390 | <field> |
||
| 1391 | <name>BR4</name> |
||
| 1392 | <description>Port x Reset bit y</description> |
||
| 1393 | <bitOffset>4</bitOffset> |
||
| 1394 | <bitWidth>1</bitWidth> |
||
| 1395 | </field> |
||
| 1396 | <field> |
||
| 1397 | <name>BR5</name> |
||
| 1398 | <description>Port x Reset bit y</description> |
||
| 1399 | <bitOffset>5</bitOffset> |
||
| 1400 | <bitWidth>1</bitWidth> |
||
| 1401 | </field> |
||
| 1402 | <field> |
||
| 1403 | <name>BR6</name> |
||
| 1404 | <description>Port x Reset bit y</description> |
||
| 1405 | <bitOffset>6</bitOffset> |
||
| 1406 | <bitWidth>1</bitWidth> |
||
| 1407 | </field> |
||
| 1408 | <field> |
||
| 1409 | <name>BR7</name> |
||
| 1410 | <description>Port x Reset bit y</description> |
||
| 1411 | <bitOffset>7</bitOffset> |
||
| 1412 | <bitWidth>1</bitWidth> |
||
| 1413 | </field> |
||
| 1414 | <field> |
||
| 1415 | <name>BR8</name> |
||
| 1416 | <description>Port x Reset bit y</description> |
||
| 1417 | <bitOffset>8</bitOffset> |
||
| 1418 | <bitWidth>1</bitWidth> |
||
| 1419 | </field> |
||
| 1420 | <field> |
||
| 1421 | <name>BR9</name> |
||
| 1422 | <description>Port x Reset bit y</description> |
||
| 1423 | <bitOffset>9</bitOffset> |
||
| 1424 | <bitWidth>1</bitWidth> |
||
| 1425 | </field> |
||
| 1426 | <field> |
||
| 1427 | <name>BR10</name> |
||
| 1428 | <description>Port x Reset bit y</description> |
||
| 1429 | <bitOffset>10</bitOffset> |
||
| 1430 | <bitWidth>1</bitWidth> |
||
| 1431 | </field> |
||
| 1432 | <field> |
||
| 1433 | <name>BR11</name> |
||
| 1434 | <description>Port x Reset bit y</description> |
||
| 1435 | <bitOffset>11</bitOffset> |
||
| 1436 | <bitWidth>1</bitWidth> |
||
| 1437 | </field> |
||
| 1438 | <field> |
||
| 1439 | <name>BR12</name> |
||
| 1440 | <description>Port x Reset bit y</description> |
||
| 1441 | <bitOffset>12</bitOffset> |
||
| 1442 | <bitWidth>1</bitWidth> |
||
| 1443 | </field> |
||
| 1444 | <field> |
||
| 1445 | <name>BR13</name> |
||
| 1446 | <description>Port x Reset bit y</description> |
||
| 1447 | <bitOffset>13</bitOffset> |
||
| 1448 | <bitWidth>1</bitWidth> |
||
| 1449 | </field> |
||
| 1450 | <field> |
||
| 1451 | <name>BR14</name> |
||
| 1452 | <description>Port x Reset bit y</description> |
||
| 1453 | <bitOffset>14</bitOffset> |
||
| 1454 | <bitWidth>1</bitWidth> |
||
| 1455 | </field> |
||
| 1456 | <field> |
||
| 1457 | <name>BR15</name> |
||
| 1458 | <description>Port x Reset bit y</description> |
||
| 1459 | <bitOffset>15</bitOffset> |
||
| 1460 | <bitWidth>1</bitWidth> |
||
| 1461 | </field> |
||
| 1462 | </fields> |
||
| 1463 | </register> |
||
| 1464 | </registers> |
||
| 1465 | </peripheral> |
||
| 1466 | <peripheral derivedFrom="GPIOF"> |
||
| 1467 | <name>GPIOD</name> |
||
| 1468 | <baseAddress>0x48000C00</baseAddress> |
||
| 1469 | </peripheral> |
||
| 1470 | <peripheral derivedFrom="GPIOF"> |
||
| 1471 | <name>GPIOC</name> |
||
| 1472 | <baseAddress>0x48000800</baseAddress> |
||
| 1473 | </peripheral> |
||
| 1474 | <peripheral derivedFrom="GPIOF"> |
||
| 1475 | <name>GPIOB</name> |
||
| 1476 | <baseAddress>0x48000400</baseAddress> |
||
| 1477 | </peripheral> |
||
| 1478 | <peripheral> |
||
| 1479 | <name>GPIOA</name> |
||
| 1480 | <description>General-purpose I/Os</description> |
||
| 1481 | <groupName>GPIO</groupName> |
||
| 1482 | <baseAddress>0x48000000</baseAddress> |
||
| 1483 | <addressBlock> |
||
| 1484 | <offset>0x0</offset> |
||
| 1485 | <size>0x400</size> |
||
| 1486 | <usage>registers</usage> |
||
| 1487 | </addressBlock> |
||
| 1488 | <registers> |
||
| 1489 | <register> |
||
| 1490 | <name>MODER</name> |
||
| 1491 | <displayName>MODER</displayName> |
||
| 1492 | <description>GPIO port mode register</description> |
||
| 1493 | <addressOffset>0x0</addressOffset> |
||
| 1494 | <size>0x20</size> |
||
| 1495 | <access>read-write</access> |
||
| 1496 | <resetValue>0x28000000</resetValue> |
||
| 1497 | <fields> |
||
| 1498 | <field> |
||
| 1499 | <name>MODER15</name> |
||
| 1500 | <description>Port x configuration bits (y = |
||
| 1501 | 0..15)</description> |
||
| 1502 | <bitOffset>30</bitOffset> |
||
| 1503 | <bitWidth>2</bitWidth> |
||
| 1504 | </field> |
||
| 1505 | <field> |
||
| 1506 | <name>MODER14</name> |
||
| 1507 | <description>Port x configuration bits (y = |
||
| 1508 | 0..15)</description> |
||
| 1509 | <bitOffset>28</bitOffset> |
||
| 1510 | <bitWidth>2</bitWidth> |
||
| 1511 | </field> |
||
| 1512 | <field> |
||
| 1513 | <name>MODER13</name> |
||
| 1514 | <description>Port x configuration bits (y = |
||
| 1515 | 0..15)</description> |
||
| 1516 | <bitOffset>26</bitOffset> |
||
| 1517 | <bitWidth>2</bitWidth> |
||
| 1518 | </field> |
||
| 1519 | <field> |
||
| 1520 | <name>MODER12</name> |
||
| 1521 | <description>Port x configuration bits (y = |
||
| 1522 | 0..15)</description> |
||
| 1523 | <bitOffset>24</bitOffset> |
||
| 1524 | <bitWidth>2</bitWidth> |
||
| 1525 | </field> |
||
| 1526 | <field> |
||
| 1527 | <name>MODER11</name> |
||
| 1528 | <description>Port x configuration bits (y = |
||
| 1529 | 0..15)</description> |
||
| 1530 | <bitOffset>22</bitOffset> |
||
| 1531 | <bitWidth>2</bitWidth> |
||
| 1532 | </field> |
||
| 1533 | <field> |
||
| 1534 | <name>MODER10</name> |
||
| 1535 | <description>Port x configuration bits (y = |
||
| 1536 | 0..15)</description> |
||
| 1537 | <bitOffset>20</bitOffset> |
||
| 1538 | <bitWidth>2</bitWidth> |
||
| 1539 | </field> |
||
| 1540 | <field> |
||
| 1541 | <name>MODER9</name> |
||
| 1542 | <description>Port x configuration bits (y = |
||
| 1543 | 0..15)</description> |
||
| 1544 | <bitOffset>18</bitOffset> |
||
| 1545 | <bitWidth>2</bitWidth> |
||
| 1546 | </field> |
||
| 1547 | <field> |
||
| 1548 | <name>MODER8</name> |
||
| 1549 | <description>Port x configuration bits (y = |
||
| 1550 | 0..15)</description> |
||
| 1551 | <bitOffset>16</bitOffset> |
||
| 1552 | <bitWidth>2</bitWidth> |
||
| 1553 | </field> |
||
| 1554 | <field> |
||
| 1555 | <name>MODER7</name> |
||
| 1556 | <description>Port x configuration bits (y = |
||
| 1557 | 0..15)</description> |
||
| 1558 | <bitOffset>14</bitOffset> |
||
| 1559 | <bitWidth>2</bitWidth> |
||
| 1560 | </field> |
||
| 1561 | <field> |
||
| 1562 | <name>MODER6</name> |
||
| 1563 | <description>Port x configuration bits (y = |
||
| 1564 | 0..15)</description> |
||
| 1565 | <bitOffset>12</bitOffset> |
||
| 1566 | <bitWidth>2</bitWidth> |
||
| 1567 | </field> |
||
| 1568 | <field> |
||
| 1569 | <name>MODER5</name> |
||
| 1570 | <description>Port x configuration bits (y = |
||
| 1571 | 0..15)</description> |
||
| 1572 | <bitOffset>10</bitOffset> |
||
| 1573 | <bitWidth>2</bitWidth> |
||
| 1574 | </field> |
||
| 1575 | <field> |
||
| 1576 | <name>MODER4</name> |
||
| 1577 | <description>Port x configuration bits (y = |
||
| 1578 | 0..15)</description> |
||
| 1579 | <bitOffset>8</bitOffset> |
||
| 1580 | <bitWidth>2</bitWidth> |
||
| 1581 | </field> |
||
| 1582 | <field> |
||
| 1583 | <name>MODER3</name> |
||
| 1584 | <description>Port x configuration bits (y = |
||
| 1585 | 0..15)</description> |
||
| 1586 | <bitOffset>6</bitOffset> |
||
| 1587 | <bitWidth>2</bitWidth> |
||
| 1588 | </field> |
||
| 1589 | <field> |
||
| 1590 | <name>MODER2</name> |
||
| 1591 | <description>Port x configuration bits (y = |
||
| 1592 | 0..15)</description> |
||
| 1593 | <bitOffset>4</bitOffset> |
||
| 1594 | <bitWidth>2</bitWidth> |
||
| 1595 | </field> |
||
| 1596 | <field> |
||
| 1597 | <name>MODER1</name> |
||
| 1598 | <description>Port x configuration bits (y = |
||
| 1599 | 0..15)</description> |
||
| 1600 | <bitOffset>2</bitOffset> |
||
| 1601 | <bitWidth>2</bitWidth> |
||
| 1602 | </field> |
||
| 1603 | <field> |
||
| 1604 | <name>MODER0</name> |
||
| 1605 | <description>Port x configuration bits (y = |
||
| 1606 | 0..15)</description> |
||
| 1607 | <bitOffset>0</bitOffset> |
||
| 1608 | <bitWidth>2</bitWidth> |
||
| 1609 | </field> |
||
| 1610 | </fields> |
||
| 1611 | </register> |
||
| 1612 | <register> |
||
| 1613 | <name>OTYPER</name> |
||
| 1614 | <displayName>OTYPER</displayName> |
||
| 1615 | <description>GPIO port output type register</description> |
||
| 1616 | <addressOffset>0x4</addressOffset> |
||
| 1617 | <size>0x20</size> |
||
| 1618 | <access>read-write</access> |
||
| 1619 | <resetValue>0x00000000</resetValue> |
||
| 1620 | <fields> |
||
| 1621 | <field> |
||
| 1622 | <name>OT15</name> |
||
| 1623 | <description>Port x configuration bits (y = |
||
| 1624 | 0..15)</description> |
||
| 1625 | <bitOffset>15</bitOffset> |
||
| 1626 | <bitWidth>1</bitWidth> |
||
| 1627 | </field> |
||
| 1628 | <field> |
||
| 1629 | <name>OT14</name> |
||
| 1630 | <description>Port x configuration bits (y = |
||
| 1631 | 0..15)</description> |
||
| 1632 | <bitOffset>14</bitOffset> |
||
| 1633 | <bitWidth>1</bitWidth> |
||
| 1634 | </field> |
||
| 1635 | <field> |
||
| 1636 | <name>OT13</name> |
||
| 1637 | <description>Port x configuration bits (y = |
||
| 1638 | 0..15)</description> |
||
| 1639 | <bitOffset>13</bitOffset> |
||
| 1640 | <bitWidth>1</bitWidth> |
||
| 1641 | </field> |
||
| 1642 | <field> |
||
| 1643 | <name>OT12</name> |
||
| 1644 | <description>Port x configuration bits (y = |
||
| 1645 | 0..15)</description> |
||
| 1646 | <bitOffset>12</bitOffset> |
||
| 1647 | <bitWidth>1</bitWidth> |
||
| 1648 | </field> |
||
| 1649 | <field> |
||
| 1650 | <name>OT11</name> |
||
| 1651 | <description>Port x configuration bits (y = |
||
| 1652 | 0..15)</description> |
||
| 1653 | <bitOffset>11</bitOffset> |
||
| 1654 | <bitWidth>1</bitWidth> |
||
| 1655 | </field> |
||
| 1656 | <field> |
||
| 1657 | <name>OT10</name> |
||
| 1658 | <description>Port x configuration bits (y = |
||
| 1659 | 0..15)</description> |
||
| 1660 | <bitOffset>10</bitOffset> |
||
| 1661 | <bitWidth>1</bitWidth> |
||
| 1662 | </field> |
||
| 1663 | <field> |
||
| 1664 | <name>OT9</name> |
||
| 1665 | <description>Port x configuration bits (y = |
||
| 1666 | 0..15)</description> |
||
| 1667 | <bitOffset>9</bitOffset> |
||
| 1668 | <bitWidth>1</bitWidth> |
||
| 1669 | </field> |
||
| 1670 | <field> |
||
| 1671 | <name>OT8</name> |
||
| 1672 | <description>Port x configuration bits (y = |
||
| 1673 | 0..15)</description> |
||
| 1674 | <bitOffset>8</bitOffset> |
||
| 1675 | <bitWidth>1</bitWidth> |
||
| 1676 | </field> |
||
| 1677 | <field> |
||
| 1678 | <name>OT7</name> |
||
| 1679 | <description>Port x configuration bits (y = |
||
| 1680 | 0..15)</description> |
||
| 1681 | <bitOffset>7</bitOffset> |
||
| 1682 | <bitWidth>1</bitWidth> |
||
| 1683 | </field> |
||
| 1684 | <field> |
||
| 1685 | <name>OT6</name> |
||
| 1686 | <description>Port x configuration bits (y = |
||
| 1687 | 0..15)</description> |
||
| 1688 | <bitOffset>6</bitOffset> |
||
| 1689 | <bitWidth>1</bitWidth> |
||
| 1690 | </field> |
||
| 1691 | <field> |
||
| 1692 | <name>OT5</name> |
||
| 1693 | <description>Port x configuration bits (y = |
||
| 1694 | 0..15)</description> |
||
| 1695 | <bitOffset>5</bitOffset> |
||
| 1696 | <bitWidth>1</bitWidth> |
||
| 1697 | </field> |
||
| 1698 | <field> |
||
| 1699 | <name>OT4</name> |
||
| 1700 | <description>Port x configuration bits (y = |
||
| 1701 | 0..15)</description> |
||
| 1702 | <bitOffset>4</bitOffset> |
||
| 1703 | <bitWidth>1</bitWidth> |
||
| 1704 | </field> |
||
| 1705 | <field> |
||
| 1706 | <name>OT3</name> |
||
| 1707 | <description>Port x configuration bits (y = |
||
| 1708 | 0..15)</description> |
||
| 1709 | <bitOffset>3</bitOffset> |
||
| 1710 | <bitWidth>1</bitWidth> |
||
| 1711 | </field> |
||
| 1712 | <field> |
||
| 1713 | <name>OT2</name> |
||
| 1714 | <description>Port x configuration bits (y = |
||
| 1715 | 0..15)</description> |
||
| 1716 | <bitOffset>2</bitOffset> |
||
| 1717 | <bitWidth>1</bitWidth> |
||
| 1718 | </field> |
||
| 1719 | <field> |
||
| 1720 | <name>OT1</name> |
||
| 1721 | <description>Port x configuration bits (y = |
||
| 1722 | 0..15)</description> |
||
| 1723 | <bitOffset>1</bitOffset> |
||
| 1724 | <bitWidth>1</bitWidth> |
||
| 1725 | </field> |
||
| 1726 | <field> |
||
| 1727 | <name>OT0</name> |
||
| 1728 | <description>Port x configuration bits (y = |
||
| 1729 | 0..15)</description> |
||
| 1730 | <bitOffset>0</bitOffset> |
||
| 1731 | <bitWidth>1</bitWidth> |
||
| 1732 | </field> |
||
| 1733 | </fields> |
||
| 1734 | </register> |
||
| 1735 | <register> |
||
| 1736 | <name>OSPEEDR</name> |
||
| 1737 | <displayName>OSPEEDR</displayName> |
||
| 1738 | <description>GPIO port output speed |
||
| 1739 | register</description> |
||
| 1740 | <addressOffset>0x8</addressOffset> |
||
| 1741 | <size>0x20</size> |
||
| 1742 | <access>read-write</access> |
||
| 1743 | <resetValue>0x00000000</resetValue> |
||
| 1744 | <fields> |
||
| 1745 | <field> |
||
| 1746 | <name>OSPEEDR15</name> |
||
| 1747 | <description>Port x configuration bits (y = |
||
| 1748 | 0..15)</description> |
||
| 1749 | <bitOffset>30</bitOffset> |
||
| 1750 | <bitWidth>2</bitWidth> |
||
| 1751 | </field> |
||
| 1752 | <field> |
||
| 1753 | <name>OSPEEDR14</name> |
||
| 1754 | <description>Port x configuration bits (y = |
||
| 1755 | 0..15)</description> |
||
| 1756 | <bitOffset>28</bitOffset> |
||
| 1757 | <bitWidth>2</bitWidth> |
||
| 1758 | </field> |
||
| 1759 | <field> |
||
| 1760 | <name>OSPEEDR13</name> |
||
| 1761 | <description>Port x configuration bits (y = |
||
| 1762 | 0..15)</description> |
||
| 1763 | <bitOffset>26</bitOffset> |
||
| 1764 | <bitWidth>2</bitWidth> |
||
| 1765 | </field> |
||
| 1766 | <field> |
||
| 1767 | <name>OSPEEDR12</name> |
||
| 1768 | <description>Port x configuration bits (y = |
||
| 1769 | 0..15)</description> |
||
| 1770 | <bitOffset>24</bitOffset> |
||
| 1771 | <bitWidth>2</bitWidth> |
||
| 1772 | </field> |
||
| 1773 | <field> |
||
| 1774 | <name>OSPEEDR11</name> |
||
| 1775 | <description>Port x configuration bits (y = |
||
| 1776 | 0..15)</description> |
||
| 1777 | <bitOffset>22</bitOffset> |
||
| 1778 | <bitWidth>2</bitWidth> |
||
| 1779 | </field> |
||
| 1780 | <field> |
||
| 1781 | <name>OSPEEDR10</name> |
||
| 1782 | <description>Port x configuration bits (y = |
||
| 1783 | 0..15)</description> |
||
| 1784 | <bitOffset>20</bitOffset> |
||
| 1785 | <bitWidth>2</bitWidth> |
||
| 1786 | </field> |
||
| 1787 | <field> |
||
| 1788 | <name>OSPEEDR9</name> |
||
| 1789 | <description>Port x configuration bits (y = |
||
| 1790 | 0..15)</description> |
||
| 1791 | <bitOffset>18</bitOffset> |
||
| 1792 | <bitWidth>2</bitWidth> |
||
| 1793 | </field> |
||
| 1794 | <field> |
||
| 1795 | <name>OSPEEDR8</name> |
||
| 1796 | <description>Port x configuration bits (y = |
||
| 1797 | 0..15)</description> |
||
| 1798 | <bitOffset>16</bitOffset> |
||
| 1799 | <bitWidth>2</bitWidth> |
||
| 1800 | </field> |
||
| 1801 | <field> |
||
| 1802 | <name>OSPEEDR7</name> |
||
| 1803 | <description>Port x configuration bits (y = |
||
| 1804 | 0..15)</description> |
||
| 1805 | <bitOffset>14</bitOffset> |
||
| 1806 | <bitWidth>2</bitWidth> |
||
| 1807 | </field> |
||
| 1808 | <field> |
||
| 1809 | <name>OSPEEDR6</name> |
||
| 1810 | <description>Port x configuration bits (y = |
||
| 1811 | 0..15)</description> |
||
| 1812 | <bitOffset>12</bitOffset> |
||
| 1813 | <bitWidth>2</bitWidth> |
||
| 1814 | </field> |
||
| 1815 | <field> |
||
| 1816 | <name>OSPEEDR5</name> |
||
| 1817 | <description>Port x configuration bits (y = |
||
| 1818 | 0..15)</description> |
||
| 1819 | <bitOffset>10</bitOffset> |
||
| 1820 | <bitWidth>2</bitWidth> |
||
| 1821 | </field> |
||
| 1822 | <field> |
||
| 1823 | <name>OSPEEDR4</name> |
||
| 1824 | <description>Port x configuration bits (y = |
||
| 1825 | 0..15)</description> |
||
| 1826 | <bitOffset>8</bitOffset> |
||
| 1827 | <bitWidth>2</bitWidth> |
||
| 1828 | </field> |
||
| 1829 | <field> |
||
| 1830 | <name>OSPEEDR3</name> |
||
| 1831 | <description>Port x configuration bits (y = |
||
| 1832 | 0..15)</description> |
||
| 1833 | <bitOffset>6</bitOffset> |
||
| 1834 | <bitWidth>2</bitWidth> |
||
| 1835 | </field> |
||
| 1836 | <field> |
||
| 1837 | <name>OSPEEDR2</name> |
||
| 1838 | <description>Port x configuration bits (y = |
||
| 1839 | 0..15)</description> |
||
| 1840 | <bitOffset>4</bitOffset> |
||
| 1841 | <bitWidth>2</bitWidth> |
||
| 1842 | </field> |
||
| 1843 | <field> |
||
| 1844 | <name>OSPEEDR1</name> |
||
| 1845 | <description>Port x configuration bits (y = |
||
| 1846 | 0..15)</description> |
||
| 1847 | <bitOffset>2</bitOffset> |
||
| 1848 | <bitWidth>2</bitWidth> |
||
| 1849 | </field> |
||
| 1850 | <field> |
||
| 1851 | <name>OSPEEDR0</name> |
||
| 1852 | <description>Port x configuration bits (y = |
||
| 1853 | 0..15)</description> |
||
| 1854 | <bitOffset>0</bitOffset> |
||
| 1855 | <bitWidth>2</bitWidth> |
||
| 1856 | </field> |
||
| 1857 | </fields> |
||
| 1858 | </register> |
||
| 1859 | <register> |
||
| 1860 | <name>PUPDR</name> |
||
| 1861 | <displayName>PUPDR</displayName> |
||
| 1862 | <description>GPIO port pull-up/pull-down |
||
| 1863 | register</description> |
||
| 1864 | <addressOffset>0xC</addressOffset> |
||
| 1865 | <size>0x20</size> |
||
| 1866 | <access>read-write</access> |
||
| 1867 | <resetValue>0x24000000</resetValue> |
||
| 1868 | <fields> |
||
| 1869 | <field> |
||
| 1870 | <name>PUPDR15</name> |
||
| 1871 | <description>Port x configuration bits (y = |
||
| 1872 | 0..15)</description> |
||
| 1873 | <bitOffset>30</bitOffset> |
||
| 1874 | <bitWidth>2</bitWidth> |
||
| 1875 | </field> |
||
| 1876 | <field> |
||
| 1877 | <name>PUPDR14</name> |
||
| 1878 | <description>Port x configuration bits (y = |
||
| 1879 | 0..15)</description> |
||
| 1880 | <bitOffset>28</bitOffset> |
||
| 1881 | <bitWidth>2</bitWidth> |
||
| 1882 | </field> |
||
| 1883 | <field> |
||
| 1884 | <name>PUPDR13</name> |
||
| 1885 | <description>Port x configuration bits (y = |
||
| 1886 | 0..15)</description> |
||
| 1887 | <bitOffset>26</bitOffset> |
||
| 1888 | <bitWidth>2</bitWidth> |
||
| 1889 | </field> |
||
| 1890 | <field> |
||
| 1891 | <name>PUPDR12</name> |
||
| 1892 | <description>Port x configuration bits (y = |
||
| 1893 | 0..15)</description> |
||
| 1894 | <bitOffset>24</bitOffset> |
||
| 1895 | <bitWidth>2</bitWidth> |
||
| 1896 | </field> |
||
| 1897 | <field> |
||
| 1898 | <name>PUPDR11</name> |
||
| 1899 | <description>Port x configuration bits (y = |
||
| 1900 | 0..15)</description> |
||
| 1901 | <bitOffset>22</bitOffset> |
||
| 1902 | <bitWidth>2</bitWidth> |
||
| 1903 | </field> |
||
| 1904 | <field> |
||
| 1905 | <name>PUPDR10</name> |
||
| 1906 | <description>Port x configuration bits (y = |
||
| 1907 | 0..15)</description> |
||
| 1908 | <bitOffset>20</bitOffset> |
||
| 1909 | <bitWidth>2</bitWidth> |
||
| 1910 | </field> |
||
| 1911 | <field> |
||
| 1912 | <name>PUPDR9</name> |
||
| 1913 | <description>Port x configuration bits (y = |
||
| 1914 | 0..15)</description> |
||
| 1915 | <bitOffset>18</bitOffset> |
||
| 1916 | <bitWidth>2</bitWidth> |
||
| 1917 | </field> |
||
| 1918 | <field> |
||
| 1919 | <name>PUPDR8</name> |
||
| 1920 | <description>Port x configuration bits (y = |
||
| 1921 | 0..15)</description> |
||
| 1922 | <bitOffset>16</bitOffset> |
||
| 1923 | <bitWidth>2</bitWidth> |
||
| 1924 | </field> |
||
| 1925 | <field> |
||
| 1926 | <name>PUPDR7</name> |
||
| 1927 | <description>Port x configuration bits (y = |
||
| 1928 | 0..15)</description> |
||
| 1929 | <bitOffset>14</bitOffset> |
||
| 1930 | <bitWidth>2</bitWidth> |
||
| 1931 | </field> |
||
| 1932 | <field> |
||
| 1933 | <name>PUPDR6</name> |
||
| 1934 | <description>Port x configuration bits (y = |
||
| 1935 | 0..15)</description> |
||
| 1936 | <bitOffset>12</bitOffset> |
||
| 1937 | <bitWidth>2</bitWidth> |
||
| 1938 | </field> |
||
| 1939 | <field> |
||
| 1940 | <name>PUPDR5</name> |
||
| 1941 | <description>Port x configuration bits (y = |
||
| 1942 | 0..15)</description> |
||
| 1943 | <bitOffset>10</bitOffset> |
||
| 1944 | <bitWidth>2</bitWidth> |
||
| 1945 | </field> |
||
| 1946 | <field> |
||
| 1947 | <name>PUPDR4</name> |
||
| 1948 | <description>Port x configuration bits (y = |
||
| 1949 | 0..15)</description> |
||
| 1950 | <bitOffset>8</bitOffset> |
||
| 1951 | <bitWidth>2</bitWidth> |
||
| 1952 | </field> |
||
| 1953 | <field> |
||
| 1954 | <name>PUPDR3</name> |
||
| 1955 | <description>Port x configuration bits (y = |
||
| 1956 | 0..15)</description> |
||
| 1957 | <bitOffset>6</bitOffset> |
||
| 1958 | <bitWidth>2</bitWidth> |
||
| 1959 | </field> |
||
| 1960 | <field> |
||
| 1961 | <name>PUPDR2</name> |
||
| 1962 | <description>Port x configuration bits (y = |
||
| 1963 | 0..15)</description> |
||
| 1964 | <bitOffset>4</bitOffset> |
||
| 1965 | <bitWidth>2</bitWidth> |
||
| 1966 | </field> |
||
| 1967 | <field> |
||
| 1968 | <name>PUPDR1</name> |
||
| 1969 | <description>Port x configuration bits (y = |
||
| 1970 | 0..15)</description> |
||
| 1971 | <bitOffset>2</bitOffset> |
||
| 1972 | <bitWidth>2</bitWidth> |
||
| 1973 | </field> |
||
| 1974 | <field> |
||
| 1975 | <name>PUPDR0</name> |
||
| 1976 | <description>Port x configuration bits (y = |
||
| 1977 | 0..15)</description> |
||
| 1978 | <bitOffset>0</bitOffset> |
||
| 1979 | <bitWidth>2</bitWidth> |
||
| 1980 | </field> |
||
| 1981 | </fields> |
||
| 1982 | </register> |
||
| 1983 | <register> |
||
| 1984 | <name>IDR</name> |
||
| 1985 | <displayName>IDR</displayName> |
||
| 1986 | <description>GPIO port input data register</description> |
||
| 1987 | <addressOffset>0x10</addressOffset> |
||
| 1988 | <size>0x20</size> |
||
| 1989 | <access>read-only</access> |
||
| 1990 | <resetValue>0x00000000</resetValue> |
||
| 1991 | <fields> |
||
| 1992 | <field> |
||
| 1993 | <name>IDR15</name> |
||
| 1994 | <description>Port input data (y = |
||
| 1995 | 0..15)</description> |
||
| 1996 | <bitOffset>15</bitOffset> |
||
| 1997 | <bitWidth>1</bitWidth> |
||
| 1998 | </field> |
||
| 1999 | <field> |
||
| 2000 | <name>IDR14</name> |
||
| 2001 | <description>Port input data (y = |
||
| 2002 | 0..15)</description> |
||
| 2003 | <bitOffset>14</bitOffset> |
||
| 2004 | <bitWidth>1</bitWidth> |
||
| 2005 | </field> |
||
| 2006 | <field> |
||
| 2007 | <name>IDR13</name> |
||
| 2008 | <description>Port input data (y = |
||
| 2009 | 0..15)</description> |
||
| 2010 | <bitOffset>13</bitOffset> |
||
| 2011 | <bitWidth>1</bitWidth> |
||
| 2012 | </field> |
||
| 2013 | <field> |
||
| 2014 | <name>IDR12</name> |
||
| 2015 | <description>Port input data (y = |
||
| 2016 | 0..15)</description> |
||
| 2017 | <bitOffset>12</bitOffset> |
||
| 2018 | <bitWidth>1</bitWidth> |
||
| 2019 | </field> |
||
| 2020 | <field> |
||
| 2021 | <name>IDR11</name> |
||
| 2022 | <description>Port input data (y = |
||
| 2023 | 0..15)</description> |
||
| 2024 | <bitOffset>11</bitOffset> |
||
| 2025 | <bitWidth>1</bitWidth> |
||
| 2026 | </field> |
||
| 2027 | <field> |
||
| 2028 | <name>IDR10</name> |
||
| 2029 | <description>Port input data (y = |
||
| 2030 | 0..15)</description> |
||
| 2031 | <bitOffset>10</bitOffset> |
||
| 2032 | <bitWidth>1</bitWidth> |
||
| 2033 | </field> |
||
| 2034 | <field> |
||
| 2035 | <name>IDR9</name> |
||
| 2036 | <description>Port input data (y = |
||
| 2037 | 0..15)</description> |
||
| 2038 | <bitOffset>9</bitOffset> |
||
| 2039 | <bitWidth>1</bitWidth> |
||
| 2040 | </field> |
||
| 2041 | <field> |
||
| 2042 | <name>IDR8</name> |
||
| 2043 | <description>Port input data (y = |
||
| 2044 | 0..15)</description> |
||
| 2045 | <bitOffset>8</bitOffset> |
||
| 2046 | <bitWidth>1</bitWidth> |
||
| 2047 | </field> |
||
| 2048 | <field> |
||
| 2049 | <name>IDR7</name> |
||
| 2050 | <description>Port input data (y = |
||
| 2051 | 0..15)</description> |
||
| 2052 | <bitOffset>7</bitOffset> |
||
| 2053 | <bitWidth>1</bitWidth> |
||
| 2054 | </field> |
||
| 2055 | <field> |
||
| 2056 | <name>IDR6</name> |
||
| 2057 | <description>Port input data (y = |
||
| 2058 | 0..15)</description> |
||
| 2059 | <bitOffset>6</bitOffset> |
||
| 2060 | <bitWidth>1</bitWidth> |
||
| 2061 | </field> |
||
| 2062 | <field> |
||
| 2063 | <name>IDR5</name> |
||
| 2064 | <description>Port input data (y = |
||
| 2065 | 0..15)</description> |
||
| 2066 | <bitOffset>5</bitOffset> |
||
| 2067 | <bitWidth>1</bitWidth> |
||
| 2068 | </field> |
||
| 2069 | <field> |
||
| 2070 | <name>IDR4</name> |
||
| 2071 | <description>Port input data (y = |
||
| 2072 | 0..15)</description> |
||
| 2073 | <bitOffset>4</bitOffset> |
||
| 2074 | <bitWidth>1</bitWidth> |
||
| 2075 | </field> |
||
| 2076 | <field> |
||
| 2077 | <name>IDR3</name> |
||
| 2078 | <description>Port input data (y = |
||
| 2079 | 0..15)</description> |
||
| 2080 | <bitOffset>3</bitOffset> |
||
| 2081 | <bitWidth>1</bitWidth> |
||
| 2082 | </field> |
||
| 2083 | <field> |
||
| 2084 | <name>IDR2</name> |
||
| 2085 | <description>Port input data (y = |
||
| 2086 | 0..15)</description> |
||
| 2087 | <bitOffset>2</bitOffset> |
||
| 2088 | <bitWidth>1</bitWidth> |
||
| 2089 | </field> |
||
| 2090 | <field> |
||
| 2091 | <name>IDR1</name> |
||
| 2092 | <description>Port input data (y = |
||
| 2093 | 0..15)</description> |
||
| 2094 | <bitOffset>1</bitOffset> |
||
| 2095 | <bitWidth>1</bitWidth> |
||
| 2096 | </field> |
||
| 2097 | <field> |
||
| 2098 | <name>IDR0</name> |
||
| 2099 | <description>Port input data (y = |
||
| 2100 | 0..15)</description> |
||
| 2101 | <bitOffset>0</bitOffset> |
||
| 2102 | <bitWidth>1</bitWidth> |
||
| 2103 | </field> |
||
| 2104 | </fields> |
||
| 2105 | </register> |
||
| 2106 | <register> |
||
| 2107 | <name>ODR</name> |
||
| 2108 | <displayName>ODR</displayName> |
||
| 2109 | <description>GPIO port output data register</description> |
||
| 2110 | <addressOffset>0x14</addressOffset> |
||
| 2111 | <size>0x20</size> |
||
| 2112 | <access>read-write</access> |
||
| 2113 | <resetValue>0x00000000</resetValue> |
||
| 2114 | <fields> |
||
| 2115 | <field> |
||
| 2116 | <name>ODR15</name> |
||
| 2117 | <description>Port output data (y = |
||
| 2118 | 0..15)</description> |
||
| 2119 | <bitOffset>15</bitOffset> |
||
| 2120 | <bitWidth>1</bitWidth> |
||
| 2121 | </field> |
||
| 2122 | <field> |
||
| 2123 | <name>ODR14</name> |
||
| 2124 | <description>Port output data (y = |
||
| 2125 | 0..15)</description> |
||
| 2126 | <bitOffset>14</bitOffset> |
||
| 2127 | <bitWidth>1</bitWidth> |
||
| 2128 | </field> |
||
| 2129 | <field> |
||
| 2130 | <name>ODR13</name> |
||
| 2131 | <description>Port output data (y = |
||
| 2132 | 0..15)</description> |
||
| 2133 | <bitOffset>13</bitOffset> |
||
| 2134 | <bitWidth>1</bitWidth> |
||
| 2135 | </field> |
||
| 2136 | <field> |
||
| 2137 | <name>ODR12</name> |
||
| 2138 | <description>Port output data (y = |
||
| 2139 | 0..15)</description> |
||
| 2140 | <bitOffset>12</bitOffset> |
||
| 2141 | <bitWidth>1</bitWidth> |
||
| 2142 | </field> |
||
| 2143 | <field> |
||
| 2144 | <name>ODR11</name> |
||
| 2145 | <description>Port output data (y = |
||
| 2146 | 0..15)</description> |
||
| 2147 | <bitOffset>11</bitOffset> |
||
| 2148 | <bitWidth>1</bitWidth> |
||
| 2149 | </field> |
||
| 2150 | <field> |
||
| 2151 | <name>ODR10</name> |
||
| 2152 | <description>Port output data (y = |
||
| 2153 | 0..15)</description> |
||
| 2154 | <bitOffset>10</bitOffset> |
||
| 2155 | <bitWidth>1</bitWidth> |
||
| 2156 | </field> |
||
| 2157 | <field> |
||
| 2158 | <name>ODR9</name> |
||
| 2159 | <description>Port output data (y = |
||
| 2160 | 0..15)</description> |
||
| 2161 | <bitOffset>9</bitOffset> |
||
| 2162 | <bitWidth>1</bitWidth> |
||
| 2163 | </field> |
||
| 2164 | <field> |
||
| 2165 | <name>ODR8</name> |
||
| 2166 | <description>Port output data (y = |
||
| 2167 | 0..15)</description> |
||
| 2168 | <bitOffset>8</bitOffset> |
||
| 2169 | <bitWidth>1</bitWidth> |
||
| 2170 | </field> |
||
| 2171 | <field> |
||
| 2172 | <name>ODR7</name> |
||
| 2173 | <description>Port output data (y = |
||
| 2174 | 0..15)</description> |
||
| 2175 | <bitOffset>7</bitOffset> |
||
| 2176 | <bitWidth>1</bitWidth> |
||
| 2177 | </field> |
||
| 2178 | <field> |
||
| 2179 | <name>ODR6</name> |
||
| 2180 | <description>Port output data (y = |
||
| 2181 | 0..15)</description> |
||
| 2182 | <bitOffset>6</bitOffset> |
||
| 2183 | <bitWidth>1</bitWidth> |
||
| 2184 | </field> |
||
| 2185 | <field> |
||
| 2186 | <name>ODR5</name> |
||
| 2187 | <description>Port output data (y = |
||
| 2188 | 0..15)</description> |
||
| 2189 | <bitOffset>5</bitOffset> |
||
| 2190 | <bitWidth>1</bitWidth> |
||
| 2191 | </field> |
||
| 2192 | <field> |
||
| 2193 | <name>ODR4</name> |
||
| 2194 | <description>Port output data (y = |
||
| 2195 | 0..15)</description> |
||
| 2196 | <bitOffset>4</bitOffset> |
||
| 2197 | <bitWidth>1</bitWidth> |
||
| 2198 | </field> |
||
| 2199 | <field> |
||
| 2200 | <name>ODR3</name> |
||
| 2201 | <description>Port output data (y = |
||
| 2202 | 0..15)</description> |
||
| 2203 | <bitOffset>3</bitOffset> |
||
| 2204 | <bitWidth>1</bitWidth> |
||
| 2205 | </field> |
||
| 2206 | <field> |
||
| 2207 | <name>ODR2</name> |
||
| 2208 | <description>Port output data (y = |
||
| 2209 | 0..15)</description> |
||
| 2210 | <bitOffset>2</bitOffset> |
||
| 2211 | <bitWidth>1</bitWidth> |
||
| 2212 | </field> |
||
| 2213 | <field> |
||
| 2214 | <name>ODR1</name> |
||
| 2215 | <description>Port output data (y = |
||
| 2216 | 0..15)</description> |
||
| 2217 | <bitOffset>1</bitOffset> |
||
| 2218 | <bitWidth>1</bitWidth> |
||
| 2219 | </field> |
||
| 2220 | <field> |
||
| 2221 | <name>ODR0</name> |
||
| 2222 | <description>Port output data (y = |
||
| 2223 | 0..15)</description> |
||
| 2224 | <bitOffset>0</bitOffset> |
||
| 2225 | <bitWidth>1</bitWidth> |
||
| 2226 | </field> |
||
| 2227 | </fields> |
||
| 2228 | </register> |
||
| 2229 | <register> |
||
| 2230 | <name>BSRR</name> |
||
| 2231 | <displayName>BSRR</displayName> |
||
| 2232 | <description>GPIO port bit set/reset |
||
| 2233 | register</description> |
||
| 2234 | <addressOffset>0x18</addressOffset> |
||
| 2235 | <size>0x20</size> |
||
| 2236 | <access>write-only</access> |
||
| 2237 | <resetValue>0x00000000</resetValue> |
||
| 2238 | <fields> |
||
| 2239 | <field> |
||
| 2240 | <name>BR15</name> |
||
| 2241 | <description>Port x reset bit y (y = |
||
| 2242 | 0..15)</description> |
||
| 2243 | <bitOffset>31</bitOffset> |
||
| 2244 | <bitWidth>1</bitWidth> |
||
| 2245 | </field> |
||
| 2246 | <field> |
||
| 2247 | <name>BR14</name> |
||
| 2248 | <description>Port x reset bit y (y = |
||
| 2249 | 0..15)</description> |
||
| 2250 | <bitOffset>30</bitOffset> |
||
| 2251 | <bitWidth>1</bitWidth> |
||
| 2252 | </field> |
||
| 2253 | <field> |
||
| 2254 | <name>BR13</name> |
||
| 2255 | <description>Port x reset bit y (y = |
||
| 2256 | 0..15)</description> |
||
| 2257 | <bitOffset>29</bitOffset> |
||
| 2258 | <bitWidth>1</bitWidth> |
||
| 2259 | </field> |
||
| 2260 | <field> |
||
| 2261 | <name>BR12</name> |
||
| 2262 | <description>Port x reset bit y (y = |
||
| 2263 | 0..15)</description> |
||
| 2264 | <bitOffset>28</bitOffset> |
||
| 2265 | <bitWidth>1</bitWidth> |
||
| 2266 | </field> |
||
| 2267 | <field> |
||
| 2268 | <name>BR11</name> |
||
| 2269 | <description>Port x reset bit y (y = |
||
| 2270 | 0..15)</description> |
||
| 2271 | <bitOffset>27</bitOffset> |
||
| 2272 | <bitWidth>1</bitWidth> |
||
| 2273 | </field> |
||
| 2274 | <field> |
||
| 2275 | <name>BR10</name> |
||
| 2276 | <description>Port x reset bit y (y = |
||
| 2277 | 0..15)</description> |
||
| 2278 | <bitOffset>26</bitOffset> |
||
| 2279 | <bitWidth>1</bitWidth> |
||
| 2280 | </field> |
||
| 2281 | <field> |
||
| 2282 | <name>BR9</name> |
||
| 2283 | <description>Port x reset bit y (y = |
||
| 2284 | 0..15)</description> |
||
| 2285 | <bitOffset>25</bitOffset> |
||
| 2286 | <bitWidth>1</bitWidth> |
||
| 2287 | </field> |
||
| 2288 | <field> |
||
| 2289 | <name>BR8</name> |
||
| 2290 | <description>Port x reset bit y (y = |
||
| 2291 | 0..15)</description> |
||
| 2292 | <bitOffset>24</bitOffset> |
||
| 2293 | <bitWidth>1</bitWidth> |
||
| 2294 | </field> |
||
| 2295 | <field> |
||
| 2296 | <name>BR7</name> |
||
| 2297 | <description>Port x reset bit y (y = |
||
| 2298 | 0..15)</description> |
||
| 2299 | <bitOffset>23</bitOffset> |
||
| 2300 | <bitWidth>1</bitWidth> |
||
| 2301 | </field> |
||
| 2302 | <field> |
||
| 2303 | <name>BR6</name> |
||
| 2304 | <description>Port x reset bit y (y = |
||
| 2305 | 0..15)</description> |
||
| 2306 | <bitOffset>22</bitOffset> |
||
| 2307 | <bitWidth>1</bitWidth> |
||
| 2308 | </field> |
||
| 2309 | <field> |
||
| 2310 | <name>BR5</name> |
||
| 2311 | <description>Port x reset bit y (y = |
||
| 2312 | 0..15)</description> |
||
| 2313 | <bitOffset>21</bitOffset> |
||
| 2314 | <bitWidth>1</bitWidth> |
||
| 2315 | </field> |
||
| 2316 | <field> |
||
| 2317 | <name>BR4</name> |
||
| 2318 | <description>Port x reset bit y (y = |
||
| 2319 | 0..15)</description> |
||
| 2320 | <bitOffset>20</bitOffset> |
||
| 2321 | <bitWidth>1</bitWidth> |
||
| 2322 | </field> |
||
| 2323 | <field> |
||
| 2324 | <name>BR3</name> |
||
| 2325 | <description>Port x reset bit y (y = |
||
| 2326 | 0..15)</description> |
||
| 2327 | <bitOffset>19</bitOffset> |
||
| 2328 | <bitWidth>1</bitWidth> |
||
| 2329 | </field> |
||
| 2330 | <field> |
||
| 2331 | <name>BR2</name> |
||
| 2332 | <description>Port x reset bit y (y = |
||
| 2333 | 0..15)</description> |
||
| 2334 | <bitOffset>18</bitOffset> |
||
| 2335 | <bitWidth>1</bitWidth> |
||
| 2336 | </field> |
||
| 2337 | <field> |
||
| 2338 | <name>BR1</name> |
||
| 2339 | <description>Port x reset bit y (y = |
||
| 2340 | 0..15)</description> |
||
| 2341 | <bitOffset>17</bitOffset> |
||
| 2342 | <bitWidth>1</bitWidth> |
||
| 2343 | </field> |
||
| 2344 | <field> |
||
| 2345 | <name>BR0</name> |
||
| 2346 | <description>Port x set bit y (y= |
||
| 2347 | 0..15)</description> |
||
| 2348 | <bitOffset>16</bitOffset> |
||
| 2349 | <bitWidth>1</bitWidth> |
||
| 2350 | </field> |
||
| 2351 | <field> |
||
| 2352 | <name>BS15</name> |
||
| 2353 | <description>Port x set bit y (y= |
||
| 2354 | 0..15)</description> |
||
| 2355 | <bitOffset>15</bitOffset> |
||
| 2356 | <bitWidth>1</bitWidth> |
||
| 2357 | </field> |
||
| 2358 | <field> |
||
| 2359 | <name>BS14</name> |
||
| 2360 | <description>Port x set bit y (y= |
||
| 2361 | 0..15)</description> |
||
| 2362 | <bitOffset>14</bitOffset> |
||
| 2363 | <bitWidth>1</bitWidth> |
||
| 2364 | </field> |
||
| 2365 | <field> |
||
| 2366 | <name>BS13</name> |
||
| 2367 | <description>Port x set bit y (y= |
||
| 2368 | 0..15)</description> |
||
| 2369 | <bitOffset>13</bitOffset> |
||
| 2370 | <bitWidth>1</bitWidth> |
||
| 2371 | </field> |
||
| 2372 | <field> |
||
| 2373 | <name>BS12</name> |
||
| 2374 | <description>Port x set bit y (y= |
||
| 2375 | 0..15)</description> |
||
| 2376 | <bitOffset>12</bitOffset> |
||
| 2377 | <bitWidth>1</bitWidth> |
||
| 2378 | </field> |
||
| 2379 | <field> |
||
| 2380 | <name>BS11</name> |
||
| 2381 | <description>Port x set bit y (y= |
||
| 2382 | 0..15)</description> |
||
| 2383 | <bitOffset>11</bitOffset> |
||
| 2384 | <bitWidth>1</bitWidth> |
||
| 2385 | </field> |
||
| 2386 | <field> |
||
| 2387 | <name>BS10</name> |
||
| 2388 | <description>Port x set bit y (y= |
||
| 2389 | 0..15)</description> |
||
| 2390 | <bitOffset>10</bitOffset> |
||
| 2391 | <bitWidth>1</bitWidth> |
||
| 2392 | </field> |
||
| 2393 | <field> |
||
| 2394 | <name>BS9</name> |
||
| 2395 | <description>Port x set bit y (y= |
||
| 2396 | 0..15)</description> |
||
| 2397 | <bitOffset>9</bitOffset> |
||
| 2398 | <bitWidth>1</bitWidth> |
||
| 2399 | </field> |
||
| 2400 | <field> |
||
| 2401 | <name>BS8</name> |
||
| 2402 | <description>Port x set bit y (y= |
||
| 2403 | 0..15)</description> |
||
| 2404 | <bitOffset>8</bitOffset> |
||
| 2405 | <bitWidth>1</bitWidth> |
||
| 2406 | </field> |
||
| 2407 | <field> |
||
| 2408 | <name>BS7</name> |
||
| 2409 | <description>Port x set bit y (y= |
||
| 2410 | 0..15)</description> |
||
| 2411 | <bitOffset>7</bitOffset> |
||
| 2412 | <bitWidth>1</bitWidth> |
||
| 2413 | </field> |
||
| 2414 | <field> |
||
| 2415 | <name>BS6</name> |
||
| 2416 | <description>Port x set bit y (y= |
||
| 2417 | 0..15)</description> |
||
| 2418 | <bitOffset>6</bitOffset> |
||
| 2419 | <bitWidth>1</bitWidth> |
||
| 2420 | </field> |
||
| 2421 | <field> |
||
| 2422 | <name>BS5</name> |
||
| 2423 | <description>Port x set bit y (y= |
||
| 2424 | 0..15)</description> |
||
| 2425 | <bitOffset>5</bitOffset> |
||
| 2426 | <bitWidth>1</bitWidth> |
||
| 2427 | </field> |
||
| 2428 | <field> |
||
| 2429 | <name>BS4</name> |
||
| 2430 | <description>Port x set bit y (y= |
||
| 2431 | 0..15)</description> |
||
| 2432 | <bitOffset>4</bitOffset> |
||
| 2433 | <bitWidth>1</bitWidth> |
||
| 2434 | </field> |
||
| 2435 | <field> |
||
| 2436 | <name>BS3</name> |
||
| 2437 | <description>Port x set bit y (y= |
||
| 2438 | 0..15)</description> |
||
| 2439 | <bitOffset>3</bitOffset> |
||
| 2440 | <bitWidth>1</bitWidth> |
||
| 2441 | </field> |
||
| 2442 | <field> |
||
| 2443 | <name>BS2</name> |
||
| 2444 | <description>Port x set bit y (y= |
||
| 2445 | 0..15)</description> |
||
| 2446 | <bitOffset>2</bitOffset> |
||
| 2447 | <bitWidth>1</bitWidth> |
||
| 2448 | </field> |
||
| 2449 | <field> |
||
| 2450 | <name>BS1</name> |
||
| 2451 | <description>Port x set bit y (y= |
||
| 2452 | 0..15)</description> |
||
| 2453 | <bitOffset>1</bitOffset> |
||
| 2454 | <bitWidth>1</bitWidth> |
||
| 2455 | </field> |
||
| 2456 | <field> |
||
| 2457 | <name>BS0</name> |
||
| 2458 | <description>Port x set bit y (y= |
||
| 2459 | 0..15)</description> |
||
| 2460 | <bitOffset>0</bitOffset> |
||
| 2461 | <bitWidth>1</bitWidth> |
||
| 2462 | </field> |
||
| 2463 | </fields> |
||
| 2464 | </register> |
||
| 2465 | <register> |
||
| 2466 | <name>LCKR</name> |
||
| 2467 | <displayName>LCKR</displayName> |
||
| 2468 | <description>GPIO port configuration lock |
||
| 2469 | register</description> |
||
| 2470 | <addressOffset>0x1C</addressOffset> |
||
| 2471 | <size>0x20</size> |
||
| 2472 | <access>read-write</access> |
||
| 2473 | <resetValue>0x00000000</resetValue> |
||
| 2474 | <fields> |
||
| 2475 | <field> |
||
| 2476 | <name>LCKK</name> |
||
| 2477 | <description>Port x lock bit y (y= |
||
| 2478 | 0..15)</description> |
||
| 2479 | <bitOffset>16</bitOffset> |
||
| 2480 | <bitWidth>1</bitWidth> |
||
| 2481 | </field> |
||
| 2482 | <field> |
||
| 2483 | <name>LCK15</name> |
||
| 2484 | <description>Port x lock bit y (y= |
||
| 2485 | 0..15)</description> |
||
| 2486 | <bitOffset>15</bitOffset> |
||
| 2487 | <bitWidth>1</bitWidth> |
||
| 2488 | </field> |
||
| 2489 | <field> |
||
| 2490 | <name>LCK14</name> |
||
| 2491 | <description>Port x lock bit y (y= |
||
| 2492 | 0..15)</description> |
||
| 2493 | <bitOffset>14</bitOffset> |
||
| 2494 | <bitWidth>1</bitWidth> |
||
| 2495 | </field> |
||
| 2496 | <field> |
||
| 2497 | <name>LCK13</name> |
||
| 2498 | <description>Port x lock bit y (y= |
||
| 2499 | 0..15)</description> |
||
| 2500 | <bitOffset>13</bitOffset> |
||
| 2501 | <bitWidth>1</bitWidth> |
||
| 2502 | </field> |
||
| 2503 | <field> |
||
| 2504 | <name>LCK12</name> |
||
| 2505 | <description>Port x lock bit y (y= |
||
| 2506 | 0..15)</description> |
||
| 2507 | <bitOffset>12</bitOffset> |
||
| 2508 | <bitWidth>1</bitWidth> |
||
| 2509 | </field> |
||
| 2510 | <field> |
||
| 2511 | <name>LCK11</name> |
||
| 2512 | <description>Port x lock bit y (y= |
||
| 2513 | 0..15)</description> |
||
| 2514 | <bitOffset>11</bitOffset> |
||
| 2515 | <bitWidth>1</bitWidth> |
||
| 2516 | </field> |
||
| 2517 | <field> |
||
| 2518 | <name>LCK10</name> |
||
| 2519 | <description>Port x lock bit y (y= |
||
| 2520 | 0..15)</description> |
||
| 2521 | <bitOffset>10</bitOffset> |
||
| 2522 | <bitWidth>1</bitWidth> |
||
| 2523 | </field> |
||
| 2524 | <field> |
||
| 2525 | <name>LCK9</name> |
||
| 2526 | <description>Port x lock bit y (y= |
||
| 2527 | 0..15)</description> |
||
| 2528 | <bitOffset>9</bitOffset> |
||
| 2529 | <bitWidth>1</bitWidth> |
||
| 2530 | </field> |
||
| 2531 | <field> |
||
| 2532 | <name>LCK8</name> |
||
| 2533 | <description>Port x lock bit y (y= |
||
| 2534 | 0..15)</description> |
||
| 2535 | <bitOffset>8</bitOffset> |
||
| 2536 | <bitWidth>1</bitWidth> |
||
| 2537 | </field> |
||
| 2538 | <field> |
||
| 2539 | <name>LCK7</name> |
||
| 2540 | <description>Port x lock bit y (y= |
||
| 2541 | 0..15)</description> |
||
| 2542 | <bitOffset>7</bitOffset> |
||
| 2543 | <bitWidth>1</bitWidth> |
||
| 2544 | </field> |
||
| 2545 | <field> |
||
| 2546 | <name>LCK6</name> |
||
| 2547 | <description>Port x lock bit y (y= |
||
| 2548 | 0..15)</description> |
||
| 2549 | <bitOffset>6</bitOffset> |
||
| 2550 | <bitWidth>1</bitWidth> |
||
| 2551 | </field> |
||
| 2552 | <field> |
||
| 2553 | <name>LCK5</name> |
||
| 2554 | <description>Port x lock bit y (y= |
||
| 2555 | 0..15)</description> |
||
| 2556 | <bitOffset>5</bitOffset> |
||
| 2557 | <bitWidth>1</bitWidth> |
||
| 2558 | </field> |
||
| 2559 | <field> |
||
| 2560 | <name>LCK4</name> |
||
| 2561 | <description>Port x lock bit y (y= |
||
| 2562 | 0..15)</description> |
||
| 2563 | <bitOffset>4</bitOffset> |
||
| 2564 | <bitWidth>1</bitWidth> |
||
| 2565 | </field> |
||
| 2566 | <field> |
||
| 2567 | <name>LCK3</name> |
||
| 2568 | <description>Port x lock bit y (y= |
||
| 2569 | 0..15)</description> |
||
| 2570 | <bitOffset>3</bitOffset> |
||
| 2571 | <bitWidth>1</bitWidth> |
||
| 2572 | </field> |
||
| 2573 | <field> |
||
| 2574 | <name>LCK2</name> |
||
| 2575 | <description>Port x lock bit y (y= |
||
| 2576 | 0..15)</description> |
||
| 2577 | <bitOffset>2</bitOffset> |
||
| 2578 | <bitWidth>1</bitWidth> |
||
| 2579 | </field> |
||
| 2580 | <field> |
||
| 2581 | <name>LCK1</name> |
||
| 2582 | <description>Port x lock bit y (y= |
||
| 2583 | 0..15)</description> |
||
| 2584 | <bitOffset>1</bitOffset> |
||
| 2585 | <bitWidth>1</bitWidth> |
||
| 2586 | </field> |
||
| 2587 | <field> |
||
| 2588 | <name>LCK0</name> |
||
| 2589 | <description>Port x lock bit y (y= |
||
| 2590 | 0..15)</description> |
||
| 2591 | <bitOffset>0</bitOffset> |
||
| 2592 | <bitWidth>1</bitWidth> |
||
| 2593 | </field> |
||
| 2594 | </fields> |
||
| 2595 | </register> |
||
| 2596 | <register> |
||
| 2597 | <name>AFRL</name> |
||
| 2598 | <displayName>AFRL</displayName> |
||
| 2599 | <description>GPIO alternate function low |
||
| 2600 | register</description> |
||
| 2601 | <addressOffset>0x20</addressOffset> |
||
| 2602 | <size>0x20</size> |
||
| 2603 | <access>read-write</access> |
||
| 2604 | <resetValue>0x00000000</resetValue> |
||
| 2605 | <fields> |
||
| 2606 | <field> |
||
| 2607 | <name>AFRL7</name> |
||
| 2608 | <description>Alternate function selection for port x |
||
| 2609 | bit y (y = 0..7)</description> |
||
| 2610 | <bitOffset>28</bitOffset> |
||
| 2611 | <bitWidth>4</bitWidth> |
||
| 2612 | </field> |
||
| 2613 | <field> |
||
| 2614 | <name>AFRL6</name> |
||
| 2615 | <description>Alternate function selection for port x |
||
| 2616 | bit y (y = 0..7)</description> |
||
| 2617 | <bitOffset>24</bitOffset> |
||
| 2618 | <bitWidth>4</bitWidth> |
||
| 2619 | </field> |
||
| 2620 | <field> |
||
| 2621 | <name>AFRL5</name> |
||
| 2622 | <description>Alternate function selection for port x |
||
| 2623 | bit y (y = 0..7)</description> |
||
| 2624 | <bitOffset>20</bitOffset> |
||
| 2625 | <bitWidth>4</bitWidth> |
||
| 2626 | </field> |
||
| 2627 | <field> |
||
| 2628 | <name>AFRL4</name> |
||
| 2629 | <description>Alternate function selection for port x |
||
| 2630 | bit y (y = 0..7)</description> |
||
| 2631 | <bitOffset>16</bitOffset> |
||
| 2632 | <bitWidth>4</bitWidth> |
||
| 2633 | </field> |
||
| 2634 | <field> |
||
| 2635 | <name>AFRL3</name> |
||
| 2636 | <description>Alternate function selection for port x |
||
| 2637 | bit y (y = 0..7)</description> |
||
| 2638 | <bitOffset>12</bitOffset> |
||
| 2639 | <bitWidth>4</bitWidth> |
||
| 2640 | </field> |
||
| 2641 | <field> |
||
| 2642 | <name>AFRL2</name> |
||
| 2643 | <description>Alternate function selection for port x |
||
| 2644 | bit y (y = 0..7)</description> |
||
| 2645 | <bitOffset>8</bitOffset> |
||
| 2646 | <bitWidth>4</bitWidth> |
||
| 2647 | </field> |
||
| 2648 | <field> |
||
| 2649 | <name>AFRL1</name> |
||
| 2650 | <description>Alternate function selection for port x |
||
| 2651 | bit y (y = 0..7)</description> |
||
| 2652 | <bitOffset>4</bitOffset> |
||
| 2653 | <bitWidth>4</bitWidth> |
||
| 2654 | </field> |
||
| 2655 | <field> |
||
| 2656 | <name>AFRL0</name> |
||
| 2657 | <description>Alternate function selection for port x |
||
| 2658 | bit y (y = 0..7)</description> |
||
| 2659 | <bitOffset>0</bitOffset> |
||
| 2660 | <bitWidth>4</bitWidth> |
||
| 2661 | </field> |
||
| 2662 | </fields> |
||
| 2663 | </register> |
||
| 2664 | <register> |
||
| 2665 | <name>AFRH</name> |
||
| 2666 | <displayName>AFRH</displayName> |
||
| 2667 | <description>GPIO alternate function high |
||
| 2668 | register</description> |
||
| 2669 | <addressOffset>0x24</addressOffset> |
||
| 2670 | <size>0x20</size> |
||
| 2671 | <access>read-write</access> |
||
| 2672 | <resetValue>0x00000000</resetValue> |
||
| 2673 | <fields> |
||
| 2674 | <field> |
||
| 2675 | <name>AFRH15</name> |
||
| 2676 | <description>Alternate function selection for port x |
||
| 2677 | bit y (y = 8..15)</description> |
||
| 2678 | <bitOffset>28</bitOffset> |
||
| 2679 | <bitWidth>4</bitWidth> |
||
| 2680 | </field> |
||
| 2681 | <field> |
||
| 2682 | <name>AFRH14</name> |
||
| 2683 | <description>Alternate function selection for port x |
||
| 2684 | bit y (y = 8..15)</description> |
||
| 2685 | <bitOffset>24</bitOffset> |
||
| 2686 | <bitWidth>4</bitWidth> |
||
| 2687 | </field> |
||
| 2688 | <field> |
||
| 2689 | <name>AFRH13</name> |
||
| 2690 | <description>Alternate function selection for port x |
||
| 2691 | bit y (y = 8..15)</description> |
||
| 2692 | <bitOffset>20</bitOffset> |
||
| 2693 | <bitWidth>4</bitWidth> |
||
| 2694 | </field> |
||
| 2695 | <field> |
||
| 2696 | <name>AFRH12</name> |
||
| 2697 | <description>Alternate function selection for port x |
||
| 2698 | bit y (y = 8..15)</description> |
||
| 2699 | <bitOffset>16</bitOffset> |
||
| 2700 | <bitWidth>4</bitWidth> |
||
| 2701 | </field> |
||
| 2702 | <field> |
||
| 2703 | <name>AFRH11</name> |
||
| 2704 | <description>Alternate function selection for port x |
||
| 2705 | bit y (y = 8..15)</description> |
||
| 2706 | <bitOffset>12</bitOffset> |
||
| 2707 | <bitWidth>4</bitWidth> |
||
| 2708 | </field> |
||
| 2709 | <field> |
||
| 2710 | <name>AFRH10</name> |
||
| 2711 | <description>Alternate function selection for port x |
||
| 2712 | bit y (y = 8..15)</description> |
||
| 2713 | <bitOffset>8</bitOffset> |
||
| 2714 | <bitWidth>4</bitWidth> |
||
| 2715 | </field> |
||
| 2716 | <field> |
||
| 2717 | <name>AFRH9</name> |
||
| 2718 | <description>Alternate function selection for port x |
||
| 2719 | bit y (y = 8..15)</description> |
||
| 2720 | <bitOffset>4</bitOffset> |
||
| 2721 | <bitWidth>4</bitWidth> |
||
| 2722 | </field> |
||
| 2723 | <field> |
||
| 2724 | <name>AFRH8</name> |
||
| 2725 | <description>Alternate function selection for port x |
||
| 2726 | bit y (y = 8..15)</description> |
||
| 2727 | <bitOffset>0</bitOffset> |
||
| 2728 | <bitWidth>4</bitWidth> |
||
| 2729 | </field> |
||
| 2730 | </fields> |
||
| 2731 | </register> |
||
| 2732 | <register> |
||
| 2733 | <name>BRR</name> |
||
| 2734 | <displayName>BRR</displayName> |
||
| 2735 | <description>Port bit reset register</description> |
||
| 2736 | <addressOffset>0x28</addressOffset> |
||
| 2737 | <size>0x20</size> |
||
| 2738 | <access>write-only</access> |
||
| 2739 | <resetValue>0x00000000</resetValue> |
||
| 2740 | <fields> |
||
| 2741 | <field> |
||
| 2742 | <name>BR0</name> |
||
| 2743 | <description>Port x Reset bit y</description> |
||
| 2744 | <bitOffset>0</bitOffset> |
||
| 2745 | <bitWidth>1</bitWidth> |
||
| 2746 | </field> |
||
| 2747 | <field> |
||
| 2748 | <name>BR1</name> |
||
| 2749 | <description>Port x Reset bit y</description> |
||
| 2750 | <bitOffset>1</bitOffset> |
||
| 2751 | <bitWidth>1</bitWidth> |
||
| 2752 | </field> |
||
| 2753 | <field> |
||
| 2754 | <name>BR2</name> |
||
| 2755 | <description>Port x Reset bit y</description> |
||
| 2756 | <bitOffset>2</bitOffset> |
||
| 2757 | <bitWidth>1</bitWidth> |
||
| 2758 | </field> |
||
| 2759 | <field> |
||
| 2760 | <name>BR3</name> |
||
| 2761 | <description>Port x Reset bit y</description> |
||
| 2762 | <bitOffset>3</bitOffset> |
||
| 2763 | <bitWidth>1</bitWidth> |
||
| 2764 | </field> |
||
| 2765 | <field> |
||
| 2766 | <name>BR4</name> |
||
| 2767 | <description>Port x Reset bit y</description> |
||
| 2768 | <bitOffset>4</bitOffset> |
||
| 2769 | <bitWidth>1</bitWidth> |
||
| 2770 | </field> |
||
| 2771 | <field> |
||
| 2772 | <name>BR5</name> |
||
| 2773 | <description>Port x Reset bit y</description> |
||
| 2774 | <bitOffset>5</bitOffset> |
||
| 2775 | <bitWidth>1</bitWidth> |
||
| 2776 | </field> |
||
| 2777 | <field> |
||
| 2778 | <name>BR6</name> |
||
| 2779 | <description>Port x Reset bit y</description> |
||
| 2780 | <bitOffset>6</bitOffset> |
||
| 2781 | <bitWidth>1</bitWidth> |
||
| 2782 | </field> |
||
| 2783 | <field> |
||
| 2784 | <name>BR7</name> |
||
| 2785 | <description>Port x Reset bit y</description> |
||
| 2786 | <bitOffset>7</bitOffset> |
||
| 2787 | <bitWidth>1</bitWidth> |
||
| 2788 | </field> |
||
| 2789 | <field> |
||
| 2790 | <name>BR8</name> |
||
| 2791 | <description>Port x Reset bit y</description> |
||
| 2792 | <bitOffset>8</bitOffset> |
||
| 2793 | <bitWidth>1</bitWidth> |
||
| 2794 | </field> |
||
| 2795 | <field> |
||
| 2796 | <name>BR9</name> |
||
| 2797 | <description>Port x Reset bit y</description> |
||
| 2798 | <bitOffset>9</bitOffset> |
||
| 2799 | <bitWidth>1</bitWidth> |
||
| 2800 | </field> |
||
| 2801 | <field> |
||
| 2802 | <name>BR10</name> |
||
| 2803 | <description>Port x Reset bit y</description> |
||
| 2804 | <bitOffset>10</bitOffset> |
||
| 2805 | <bitWidth>1</bitWidth> |
||
| 2806 | </field> |
||
| 2807 | <field> |
||
| 2808 | <name>BR11</name> |
||
| 2809 | <description>Port x Reset bit y</description> |
||
| 2810 | <bitOffset>11</bitOffset> |
||
| 2811 | <bitWidth>1</bitWidth> |
||
| 2812 | </field> |
||
| 2813 | <field> |
||
| 2814 | <name>BR12</name> |
||
| 2815 | <description>Port x Reset bit y</description> |
||
| 2816 | <bitOffset>12</bitOffset> |
||
| 2817 | <bitWidth>1</bitWidth> |
||
| 2818 | </field> |
||
| 2819 | <field> |
||
| 2820 | <name>BR13</name> |
||
| 2821 | <description>Port x Reset bit y</description> |
||
| 2822 | <bitOffset>13</bitOffset> |
||
| 2823 | <bitWidth>1</bitWidth> |
||
| 2824 | </field> |
||
| 2825 | <field> |
||
| 2826 | <name>BR14</name> |
||
| 2827 | <description>Port x Reset bit y</description> |
||
| 2828 | <bitOffset>14</bitOffset> |
||
| 2829 | <bitWidth>1</bitWidth> |
||
| 2830 | </field> |
||
| 2831 | <field> |
||
| 2832 | <name>BR15</name> |
||
| 2833 | <description>Port x Reset bit y</description> |
||
| 2834 | <bitOffset>15</bitOffset> |
||
| 2835 | <bitWidth>1</bitWidth> |
||
| 2836 | </field> |
||
| 2837 | </fields> |
||
| 2838 | </register> |
||
| 2839 | </registers> |
||
| 2840 | </peripheral> |
||
| 2841 | <peripheral> |
||
| 2842 | <name>SPI1</name> |
||
| 2843 | <description>Serial peripheral interface</description> |
||
| 2844 | <groupName>SPI</groupName> |
||
| 2845 | <baseAddress>0x40013000</baseAddress> |
||
| 2846 | <addressBlock> |
||
| 2847 | <offset>0x0</offset> |
||
| 2848 | <size>0x400</size> |
||
| 2849 | <usage>registers</usage> |
||
| 2850 | </addressBlock> |
||
| 2851 | <interrupt> |
||
| 2852 | <name>SPI1</name> |
||
| 2853 | <description>SPI1_global_interrupt</description> |
||
| 2854 | <value>25</value> |
||
| 2855 | </interrupt> |
||
| 2856 | <registers> |
||
| 2857 | <register> |
||
| 2858 | <name>CR1</name> |
||
| 2859 | <displayName>CR1</displayName> |
||
| 2860 | <description>control register 1</description> |
||
| 2861 | <addressOffset>0x0</addressOffset> |
||
| 2862 | <size>0x20</size> |
||
| 2863 | <access>read-write</access> |
||
| 2864 | <resetValue>0x0000</resetValue> |
||
| 2865 | <fields> |
||
| 2866 | <field> |
||
| 2867 | <name>BIDIMODE</name> |
||
| 2868 | <description>Bidirectional data mode |
||
| 2869 | enable</description> |
||
| 2870 | <bitOffset>15</bitOffset> |
||
| 2871 | <bitWidth>1</bitWidth> |
||
| 2872 | </field> |
||
| 2873 | <field> |
||
| 2874 | <name>BIDIOE</name> |
||
| 2875 | <description>Output enable in bidirectional |
||
| 2876 | mode</description> |
||
| 2877 | <bitOffset>14</bitOffset> |
||
| 2878 | <bitWidth>1</bitWidth> |
||
| 2879 | </field> |
||
| 2880 | <field> |
||
| 2881 | <name>CRCEN</name> |
||
| 2882 | <description>Hardware CRC calculation |
||
| 2883 | enable</description> |
||
| 2884 | <bitOffset>13</bitOffset> |
||
| 2885 | <bitWidth>1</bitWidth> |
||
| 2886 | </field> |
||
| 2887 | <field> |
||
| 2888 | <name>CRCNEXT</name> |
||
| 2889 | <description>CRC transfer next</description> |
||
| 2890 | <bitOffset>12</bitOffset> |
||
| 2891 | <bitWidth>1</bitWidth> |
||
| 2892 | </field> |
||
| 2893 | <field> |
||
| 2894 | <name>DFF</name> |
||
| 2895 | <description>Data frame format</description> |
||
| 2896 | <bitOffset>11</bitOffset> |
||
| 2897 | <bitWidth>1</bitWidth> |
||
| 2898 | </field> |
||
| 2899 | <field> |
||
| 2900 | <name>RXONLY</name> |
||
| 2901 | <description>Receive only</description> |
||
| 2902 | <bitOffset>10</bitOffset> |
||
| 2903 | <bitWidth>1</bitWidth> |
||
| 2904 | </field> |
||
| 2905 | <field> |
||
| 2906 | <name>SSM</name> |
||
| 2907 | <description>Software slave management</description> |
||
| 2908 | <bitOffset>9</bitOffset> |
||
| 2909 | <bitWidth>1</bitWidth> |
||
| 2910 | </field> |
||
| 2911 | <field> |
||
| 2912 | <name>SSI</name> |
||
| 2913 | <description>Internal slave select</description> |
||
| 2914 | <bitOffset>8</bitOffset> |
||
| 2915 | <bitWidth>1</bitWidth> |
||
| 2916 | </field> |
||
| 2917 | <field> |
||
| 2918 | <name>LSBFIRST</name> |
||
| 2919 | <description>Frame format</description> |
||
| 2920 | <bitOffset>7</bitOffset> |
||
| 2921 | <bitWidth>1</bitWidth> |
||
| 2922 | </field> |
||
| 2923 | <field> |
||
| 2924 | <name>SPE</name> |
||
| 2925 | <description>SPI enable</description> |
||
| 2926 | <bitOffset>6</bitOffset> |
||
| 2927 | <bitWidth>1</bitWidth> |
||
| 2928 | </field> |
||
| 2929 | <field> |
||
| 2930 | <name>BR</name> |
||
| 2931 | <description>Baud rate control</description> |
||
| 2932 | <bitOffset>3</bitOffset> |
||
| 2933 | <bitWidth>3</bitWidth> |
||
| 2934 | </field> |
||
| 2935 | <field> |
||
| 2936 | <name>MSTR</name> |
||
| 2937 | <description>Master selection</description> |
||
| 2938 | <bitOffset>2</bitOffset> |
||
| 2939 | <bitWidth>1</bitWidth> |
||
| 2940 | </field> |
||
| 2941 | <field> |
||
| 2942 | <name>CPOL</name> |
||
| 2943 | <description>Clock polarity</description> |
||
| 2944 | <bitOffset>1</bitOffset> |
||
| 2945 | <bitWidth>1</bitWidth> |
||
| 2946 | </field> |
||
| 2947 | <field> |
||
| 2948 | <name>CPHA</name> |
||
| 2949 | <description>Clock phase</description> |
||
| 2950 | <bitOffset>0</bitOffset> |
||
| 2951 | <bitWidth>1</bitWidth> |
||
| 2952 | </field> |
||
| 2953 | </fields> |
||
| 2954 | </register> |
||
| 2955 | <register> |
||
| 2956 | <name>CR2</name> |
||
| 2957 | <displayName>CR2</displayName> |
||
| 2958 | <description>control register 2</description> |
||
| 2959 | <addressOffset>0x4</addressOffset> |
||
| 2960 | <size>0x20</size> |
||
| 2961 | <access>read-write</access> |
||
| 2962 | <resetValue>0x0000</resetValue> |
||
| 2963 | <fields> |
||
| 2964 | <field> |
||
| 2965 | <name>RXDMAEN</name> |
||
| 2966 | <description>Rx buffer DMA enable</description> |
||
| 2967 | <bitOffset>0</bitOffset> |
||
| 2968 | <bitWidth>1</bitWidth> |
||
| 2969 | </field> |
||
| 2970 | <field> |
||
| 2971 | <name>TXDMAEN</name> |
||
| 2972 | <description>Tx buffer DMA enable</description> |
||
| 2973 | <bitOffset>1</bitOffset> |
||
| 2974 | <bitWidth>1</bitWidth> |
||
| 2975 | </field> |
||
| 2976 | <field> |
||
| 2977 | <name>SSOE</name> |
||
| 2978 | <description>SS output enable</description> |
||
| 2979 | <bitOffset>2</bitOffset> |
||
| 2980 | <bitWidth>1</bitWidth> |
||
| 2981 | </field> |
||
| 2982 | <field> |
||
| 2983 | <name>NSSP</name> |
||
| 2984 | <description>NSS pulse management</description> |
||
| 2985 | <bitOffset>3</bitOffset> |
||
| 2986 | <bitWidth>1</bitWidth> |
||
| 2987 | </field> |
||
| 2988 | <field> |
||
| 2989 | <name>FRF</name> |
||
| 2990 | <description>Frame format</description> |
||
| 2991 | <bitOffset>4</bitOffset> |
||
| 2992 | <bitWidth>1</bitWidth> |
||
| 2993 | </field> |
||
| 2994 | <field> |
||
| 2995 | <name>ERRIE</name> |
||
| 2996 | <description>Error interrupt enable</description> |
||
| 2997 | <bitOffset>5</bitOffset> |
||
| 2998 | <bitWidth>1</bitWidth> |
||
| 2999 | </field> |
||
| 3000 | <field> |
||
| 3001 | <name>RXNEIE</name> |
||
| 3002 | <description>RX buffer not empty interrupt |
||
| 3003 | enable</description> |
||
| 3004 | <bitOffset>6</bitOffset> |
||
| 3005 | <bitWidth>1</bitWidth> |
||
| 3006 | </field> |
||
| 3007 | <field> |
||
| 3008 | <name>TXEIE</name> |
||
| 3009 | <description>Tx buffer empty interrupt |
||
| 3010 | enable</description> |
||
| 3011 | <bitOffset>7</bitOffset> |
||
| 3012 | <bitWidth>1</bitWidth> |
||
| 3013 | </field> |
||
| 3014 | <field> |
||
| 3015 | <name>DS</name> |
||
| 3016 | <description>Data size</description> |
||
| 3017 | <bitOffset>8</bitOffset> |
||
| 3018 | <bitWidth>4</bitWidth> |
||
| 3019 | </field> |
||
| 3020 | <field> |
||
| 3021 | <name>FRXTH</name> |
||
| 3022 | <description>FIFO reception threshold</description> |
||
| 3023 | <bitOffset>12</bitOffset> |
||
| 3024 | <bitWidth>1</bitWidth> |
||
| 3025 | </field> |
||
| 3026 | <field> |
||
| 3027 | <name>LDMA_RX</name> |
||
| 3028 | <description>Last DMA transfer for |
||
| 3029 | reception</description> |
||
| 3030 | <bitOffset>13</bitOffset> |
||
| 3031 | <bitWidth>1</bitWidth> |
||
| 3032 | </field> |
||
| 3033 | <field> |
||
| 3034 | <name>LDMA_TX</name> |
||
| 3035 | <description>Last DMA transfer for |
||
| 3036 | transmission</description> |
||
| 3037 | <bitOffset>14</bitOffset> |
||
| 3038 | <bitWidth>1</bitWidth> |
||
| 3039 | </field> |
||
| 3040 | </fields> |
||
| 3041 | </register> |
||
| 3042 | <register> |
||
| 3043 | <name>SR</name> |
||
| 3044 | <displayName>SR</displayName> |
||
| 3045 | <description>status register</description> |
||
| 3046 | <addressOffset>0x8</addressOffset> |
||
| 3047 | <size>0x20</size> |
||
| 3048 | <resetValue>0x0002</resetValue> |
||
| 3049 | <fields> |
||
| 3050 | <field> |
||
| 3051 | <name>RXNE</name> |
||
| 3052 | <description>Receive buffer not empty</description> |
||
| 3053 | <bitOffset>0</bitOffset> |
||
| 3054 | <bitWidth>1</bitWidth> |
||
| 3055 | <access>read-only</access> |
||
| 3056 | </field> |
||
| 3057 | <field> |
||
| 3058 | <name>TXE</name> |
||
| 3059 | <description>Transmit buffer empty</description> |
||
| 3060 | <bitOffset>1</bitOffset> |
||
| 3061 | <bitWidth>1</bitWidth> |
||
| 3062 | <access>read-only</access> |
||
| 3063 | </field> |
||
| 3064 | <field> |
||
| 3065 | <name>CHSIDE</name> |
||
| 3066 | <description>Channel side</description> |
||
| 3067 | <bitOffset>2</bitOffset> |
||
| 3068 | <bitWidth>1</bitWidth> |
||
| 3069 | <access>read-only</access> |
||
| 3070 | </field> |
||
| 3071 | <field> |
||
| 3072 | <name>UDR</name> |
||
| 3073 | <description>Underrun flag</description> |
||
| 3074 | <bitOffset>3</bitOffset> |
||
| 3075 | <bitWidth>1</bitWidth> |
||
| 3076 | <access>read-only</access> |
||
| 3077 | </field> |
||
| 3078 | <field> |
||
| 3079 | <name>CRCERR</name> |
||
| 3080 | <description>CRC error flag</description> |
||
| 3081 | <bitOffset>4</bitOffset> |
||
| 3082 | <bitWidth>1</bitWidth> |
||
| 3083 | <access>read-write</access> |
||
| 3084 | </field> |
||
| 3085 | <field> |
||
| 3086 | <name>MODF</name> |
||
| 3087 | <description>Mode fault</description> |
||
| 3088 | <bitOffset>5</bitOffset> |
||
| 3089 | <bitWidth>1</bitWidth> |
||
| 3090 | <access>read-only</access> |
||
| 3091 | </field> |
||
| 3092 | <field> |
||
| 3093 | <name>OVR</name> |
||
| 3094 | <description>Overrun flag</description> |
||
| 3095 | <bitOffset>6</bitOffset> |
||
| 3096 | <bitWidth>1</bitWidth> |
||
| 3097 | <access>read-only</access> |
||
| 3098 | </field> |
||
| 3099 | <field> |
||
| 3100 | <name>BSY</name> |
||
| 3101 | <description>Busy flag</description> |
||
| 3102 | <bitOffset>7</bitOffset> |
||
| 3103 | <bitWidth>1</bitWidth> |
||
| 3104 | <access>read-only</access> |
||
| 3105 | </field> |
||
| 3106 | <field> |
||
| 3107 | <name>TIFRFE</name> |
||
| 3108 | <description>TI frame format error</description> |
||
| 3109 | <bitOffset>8</bitOffset> |
||
| 3110 | <bitWidth>1</bitWidth> |
||
| 3111 | <access>read-only</access> |
||
| 3112 | </field> |
||
| 3113 | <field> |
||
| 3114 | <name>FRLVL</name> |
||
| 3115 | <description>FIFO reception level</description> |
||
| 3116 | <bitOffset>9</bitOffset> |
||
| 3117 | <bitWidth>2</bitWidth> |
||
| 3118 | <access>read-only</access> |
||
| 3119 | </field> |
||
| 3120 | <field> |
||
| 3121 | <name>FTLVL</name> |
||
| 3122 | <description>FIFO transmission level</description> |
||
| 3123 | <bitOffset>11</bitOffset> |
||
| 3124 | <bitWidth>2</bitWidth> |
||
| 3125 | <access>read-only</access> |
||
| 3126 | </field> |
||
| 3127 | </fields> |
||
| 3128 | </register> |
||
| 3129 | <register> |
||
| 3130 | <name>DR</name> |
||
| 3131 | <displayName>DR</displayName> |
||
| 3132 | <description>data register</description> |
||
| 3133 | <addressOffset>0xC</addressOffset> |
||
| 3134 | <size>0x20</size> |
||
| 3135 | <access>read-write</access> |
||
| 3136 | <resetValue>0x0000</resetValue> |
||
| 3137 | <fields> |
||
| 3138 | <field> |
||
| 3139 | <name>DR</name> |
||
| 3140 | <description>Data register</description> |
||
| 3141 | <bitOffset>0</bitOffset> |
||
| 3142 | <bitWidth>16</bitWidth> |
||
| 3143 | </field> |
||
| 3144 | </fields> |
||
| 3145 | </register> |
||
| 3146 | <register> |
||
| 3147 | <name>CRCPR</name> |
||
| 3148 | <displayName>CRCPR</displayName> |
||
| 3149 | <description>CRC polynomial register</description> |
||
| 3150 | <addressOffset>0x10</addressOffset> |
||
| 3151 | <size>0x20</size> |
||
| 3152 | <access>read-write</access> |
||
| 3153 | <resetValue>0x0007</resetValue> |
||
| 3154 | <fields> |
||
| 3155 | <field> |
||
| 3156 | <name>CRCPOLY</name> |
||
| 3157 | <description>CRC polynomial register</description> |
||
| 3158 | <bitOffset>0</bitOffset> |
||
| 3159 | <bitWidth>16</bitWidth> |
||
| 3160 | </field> |
||
| 3161 | </fields> |
||
| 3162 | </register> |
||
| 3163 | <register> |
||
| 3164 | <name>RXCRCR</name> |
||
| 3165 | <displayName>RXCRCR</displayName> |
||
| 3166 | <description>RX CRC register</description> |
||
| 3167 | <addressOffset>0x14</addressOffset> |
||
| 3168 | <size>0x20</size> |
||
| 3169 | <access>read-only</access> |
||
| 3170 | <resetValue>0x0000</resetValue> |
||
| 3171 | <fields> |
||
| 3172 | <field> |
||
| 3173 | <name>RxCRC</name> |
||
| 3174 | <description>Rx CRC register</description> |
||
| 3175 | <bitOffset>0</bitOffset> |
||
| 3176 | <bitWidth>16</bitWidth> |
||
| 3177 | </field> |
||
| 3178 | </fields> |
||
| 3179 | </register> |
||
| 3180 | <register> |
||
| 3181 | <name>TXCRCR</name> |
||
| 3182 | <displayName>TXCRCR</displayName> |
||
| 3183 | <description>TX CRC register</description> |
||
| 3184 | <addressOffset>0x18</addressOffset> |
||
| 3185 | <size>0x20</size> |
||
| 3186 | <access>read-only</access> |
||
| 3187 | <resetValue>0x0000</resetValue> |
||
| 3188 | <fields> |
||
| 3189 | <field> |
||
| 3190 | <name>TxCRC</name> |
||
| 3191 | <description>Tx CRC register</description> |
||
| 3192 | <bitOffset>0</bitOffset> |
||
| 3193 | <bitWidth>16</bitWidth> |
||
| 3194 | </field> |
||
| 3195 | </fields> |
||
| 3196 | </register> |
||
| 3197 | <register> |
||
| 3198 | <name>I2SCFGR</name> |
||
| 3199 | <displayName>I2SCFGR</displayName> |
||
| 3200 | <description>I2S configuration register</description> |
||
| 3201 | <addressOffset>0x1C</addressOffset> |
||
| 3202 | <size>0x20</size> |
||
| 3203 | <access>read-write</access> |
||
| 3204 | <resetValue>0x0000</resetValue> |
||
| 3205 | <fields> |
||
| 3206 | <field> |
||
| 3207 | <name>I2SMOD</name> |
||
| 3208 | <description>I2S mode selection</description> |
||
| 3209 | <bitOffset>11</bitOffset> |
||
| 3210 | <bitWidth>1</bitWidth> |
||
| 3211 | </field> |
||
| 3212 | <field> |
||
| 3213 | <name>I2SE</name> |
||
| 3214 | <description>I2S Enable</description> |
||
| 3215 | <bitOffset>10</bitOffset> |
||
| 3216 | <bitWidth>1</bitWidth> |
||
| 3217 | </field> |
||
| 3218 | <field> |
||
| 3219 | <name>I2SCFG</name> |
||
| 3220 | <description>I2S configuration mode</description> |
||
| 3221 | <bitOffset>8</bitOffset> |
||
| 3222 | <bitWidth>2</bitWidth> |
||
| 3223 | </field> |
||
| 3224 | <field> |
||
| 3225 | <name>PCMSYNC</name> |
||
| 3226 | <description>PCM frame synchronization</description> |
||
| 3227 | <bitOffset>7</bitOffset> |
||
| 3228 | <bitWidth>1</bitWidth> |
||
| 3229 | </field> |
||
| 3230 | <field> |
||
| 3231 | <name>I2SSTD</name> |
||
| 3232 | <description>I2S standard selection</description> |
||
| 3233 | <bitOffset>4</bitOffset> |
||
| 3234 | <bitWidth>2</bitWidth> |
||
| 3235 | </field> |
||
| 3236 | <field> |
||
| 3237 | <name>CKPOL</name> |
||
| 3238 | <description>Steady state clock |
||
| 3239 | polarity</description> |
||
| 3240 | <bitOffset>3</bitOffset> |
||
| 3241 | <bitWidth>1</bitWidth> |
||
| 3242 | </field> |
||
| 3243 | <field> |
||
| 3244 | <name>DATLEN</name> |
||
| 3245 | <description>Data length to be |
||
| 3246 | transferred</description> |
||
| 3247 | <bitOffset>1</bitOffset> |
||
| 3248 | <bitWidth>2</bitWidth> |
||
| 3249 | </field> |
||
| 3250 | <field> |
||
| 3251 | <name>CHLEN</name> |
||
| 3252 | <description>Channel length (number of bits per audio |
||
| 3253 | channel)</description> |
||
| 3254 | <bitOffset>0</bitOffset> |
||
| 3255 | <bitWidth>1</bitWidth> |
||
| 3256 | </field> |
||
| 3257 | </fields> |
||
| 3258 | </register> |
||
| 3259 | <register> |
||
| 3260 | <name>I2SPR</name> |
||
| 3261 | <displayName>I2SPR</displayName> |
||
| 3262 | <description>I2S prescaler register</description> |
||
| 3263 | <addressOffset>0x20</addressOffset> |
||
| 3264 | <size>0x20</size> |
||
| 3265 | <access>read-write</access> |
||
| 3266 | <resetValue>0x00000010</resetValue> |
||
| 3267 | <fields> |
||
| 3268 | <field> |
||
| 3269 | <name>MCKOE</name> |
||
| 3270 | <description>Master clock output enable</description> |
||
| 3271 | <bitOffset>9</bitOffset> |
||
| 3272 | <bitWidth>1</bitWidth> |
||
| 3273 | </field> |
||
| 3274 | <field> |
||
| 3275 | <name>ODD</name> |
||
| 3276 | <description>Odd factor for the |
||
| 3277 | prescaler</description> |
||
| 3278 | <bitOffset>8</bitOffset> |
||
| 3279 | <bitWidth>1</bitWidth> |
||
| 3280 | </field> |
||
| 3281 | <field> |
||
| 3282 | <name>I2SDIV</name> |
||
| 3283 | <description>I2S Linear prescaler</description> |
||
| 3284 | <bitOffset>0</bitOffset> |
||
| 3285 | <bitWidth>8</bitWidth> |
||
| 3286 | </field> |
||
| 3287 | </fields> |
||
| 3288 | </register> |
||
| 3289 | </registers> |
||
| 3290 | </peripheral> |
||
| 3291 | <peripheral derivedFrom="SPI1"> |
||
| 3292 | <name>SPI2</name> |
||
| 3293 | <baseAddress>0x40003800</baseAddress> |
||
| 3294 | <interrupt> |
||
| 3295 | <name>SPI2</name> |
||
| 3296 | <description>SPI2 global interrupt</description> |
||
| 3297 | <value>26</value> |
||
| 3298 | </interrupt> |
||
| 3299 | </peripheral> |
||
| 3300 | <peripheral> |
||
| 3301 | <name>PWR</name> |
||
| 3302 | <description>Power control</description> |
||
| 3303 | <groupName>PWR</groupName> |
||
| 3304 | <baseAddress>0x40007000</baseAddress> |
||
| 3305 | <addressBlock> |
||
| 3306 | <offset>0x0</offset> |
||
| 3307 | <size>0x400</size> |
||
| 3308 | <usage>registers</usage> |
||
| 3309 | </addressBlock> |
||
| 3310 | <interrupt> |
||
| 3311 | <name>TIM6_DAC</name> |
||
| 3312 | <description>TIM6 global interrupt and DAC underrun |
||
| 3313 | interrupt</description> |
||
| 3314 | <value>17</value> |
||
| 3315 | </interrupt> |
||
| 3316 | <registers> |
||
| 3317 | <register> |
||
| 3318 | <name>CR</name> |
||
| 3319 | <displayName>CR</displayName> |
||
| 3320 | <description>power control register</description> |
||
| 3321 | <addressOffset>0x0</addressOffset> |
||
| 3322 | <size>0x20</size> |
||
| 3323 | <access>read-write</access> |
||
| 3324 | <resetValue>0x00000000</resetValue> |
||
| 3325 | <fields> |
||
| 3326 | <field> |
||
| 3327 | <name>FPDS</name> |
||
| 3328 | <description>Flash power down in Stop |
||
| 3329 | mode</description> |
||
| 3330 | <bitOffset>9</bitOffset> |
||
| 3331 | <bitWidth>1</bitWidth> |
||
| 3332 | </field> |
||
| 3333 | <field> |
||
| 3334 | <name>DBP</name> |
||
| 3335 | <description>Disable backup domain write |
||
| 3336 | protection</description> |
||
| 3337 | <bitOffset>8</bitOffset> |
||
| 3338 | <bitWidth>1</bitWidth> |
||
| 3339 | </field> |
||
| 3340 | <field> |
||
| 3341 | <name>PLS</name> |
||
| 3342 | <description>PVD level selection</description> |
||
| 3343 | <bitOffset>5</bitOffset> |
||
| 3344 | <bitWidth>3</bitWidth> |
||
| 3345 | </field> |
||
| 3346 | <field> |
||
| 3347 | <name>PVDE</name> |
||
| 3348 | <description>Power voltage detector |
||
| 3349 | enable</description> |
||
| 3350 | <bitOffset>4</bitOffset> |
||
| 3351 | <bitWidth>1</bitWidth> |
||
| 3352 | </field> |
||
| 3353 | <field> |
||
| 3354 | <name>CSBF</name> |
||
| 3355 | <description>Clear standby flag</description> |
||
| 3356 | <bitOffset>3</bitOffset> |
||
| 3357 | <bitWidth>1</bitWidth> |
||
| 3358 | </field> |
||
| 3359 | <field> |
||
| 3360 | <name>CWUF</name> |
||
| 3361 | <description>Clear wakeup flag</description> |
||
| 3362 | <bitOffset>2</bitOffset> |
||
| 3363 | <bitWidth>1</bitWidth> |
||
| 3364 | </field> |
||
| 3365 | <field> |
||
| 3366 | <name>PDDS</name> |
||
| 3367 | <description>Power down deepsleep</description> |
||
| 3368 | <bitOffset>1</bitOffset> |
||
| 3369 | <bitWidth>1</bitWidth> |
||
| 3370 | </field> |
||
| 3371 | <field> |
||
| 3372 | <name>LPDS</name> |
||
| 3373 | <description>Low-power deep sleep</description> |
||
| 3374 | <bitOffset>0</bitOffset> |
||
| 3375 | <bitWidth>1</bitWidth> |
||
| 3376 | </field> |
||
| 3377 | </fields> |
||
| 3378 | </register> |
||
| 3379 | <register> |
||
| 3380 | <name>CSR</name> |
||
| 3381 | <displayName>CSR</displayName> |
||
| 3382 | <description>power control/status register</description> |
||
| 3383 | <addressOffset>0x4</addressOffset> |
||
| 3384 | <size>0x20</size> |
||
| 3385 | <resetValue>0x00000000</resetValue> |
||
| 3386 | <fields> |
||
| 3387 | <field> |
||
| 3388 | <name>BRE</name> |
||
| 3389 | <description>Backup regulator enable</description> |
||
| 3390 | <bitOffset>9</bitOffset> |
||
| 3391 | <bitWidth>1</bitWidth> |
||
| 3392 | <access>read-write</access> |
||
| 3393 | </field> |
||
| 3394 | <field> |
||
| 3395 | <name>EWUP</name> |
||
| 3396 | <description>Enable WKUP pin</description> |
||
| 3397 | <bitOffset>8</bitOffset> |
||
| 3398 | <bitWidth>1</bitWidth> |
||
| 3399 | <access>read-write</access> |
||
| 3400 | </field> |
||
| 3401 | <field> |
||
| 3402 | <name>BRR</name> |
||
| 3403 | <description>Backup regulator ready</description> |
||
| 3404 | <bitOffset>3</bitOffset> |
||
| 3405 | <bitWidth>1</bitWidth> |
||
| 3406 | <access>read-only</access> |
||
| 3407 | </field> |
||
| 3408 | <field> |
||
| 3409 | <name>PVDO</name> |
||
| 3410 | <description>PVD output</description> |
||
| 3411 | <bitOffset>2</bitOffset> |
||
| 3412 | <bitWidth>1</bitWidth> |
||
| 3413 | <access>read-only</access> |
||
| 3414 | </field> |
||
| 3415 | <field> |
||
| 3416 | <name>SBF</name> |
||
| 3417 | <description>Standby flag</description> |
||
| 3418 | <bitOffset>1</bitOffset> |
||
| 3419 | <bitWidth>1</bitWidth> |
||
| 3420 | <access>read-only</access> |
||
| 3421 | </field> |
||
| 3422 | <field> |
||
| 3423 | <name>WUF</name> |
||
| 3424 | <description>Wakeup flag</description> |
||
| 3425 | <bitOffset>0</bitOffset> |
||
| 3426 | <bitWidth>1</bitWidth> |
||
| 3427 | <access>read-only</access> |
||
| 3428 | </field> |
||
| 3429 | </fields> |
||
| 3430 | </register> |
||
| 3431 | </registers> |
||
| 3432 | </peripheral> |
||
| 3433 | <peripheral> |
||
| 3434 | <name>I2C1</name> |
||
| 3435 | <description>Inter-integrated circuit</description> |
||
| 3436 | <groupName>I2C</groupName> |
||
| 3437 | <baseAddress>0x40005400</baseAddress> |
||
| 3438 | <addressBlock> |
||
| 3439 | <offset>0x0</offset> |
||
| 3440 | <size>0x400</size> |
||
| 3441 | <usage>registers</usage> |
||
| 3442 | </addressBlock> |
||
| 3443 | <registers> |
||
| 3444 | <register> |
||
| 3445 | <name>CR1</name> |
||
| 3446 | <displayName>CR1</displayName> |
||
| 3447 | <description>Control register 1</description> |
||
| 3448 | <addressOffset>0x0</addressOffset> |
||
| 3449 | <size>0x20</size> |
||
| 3450 | <resetValue>0x00000000</resetValue> |
||
| 3451 | <fields> |
||
| 3452 | <field> |
||
| 3453 | <name>PE</name> |
||
| 3454 | <description>Peripheral enable</description> |
||
| 3455 | <bitOffset>0</bitOffset> |
||
| 3456 | <bitWidth>1</bitWidth> |
||
| 3457 | <access>read-write</access> |
||
| 3458 | </field> |
||
| 3459 | <field> |
||
| 3460 | <name>TXIE</name> |
||
| 3461 | <description>TX Interrupt enable</description> |
||
| 3462 | <bitOffset>1</bitOffset> |
||
| 3463 | <bitWidth>1</bitWidth> |
||
| 3464 | <access>read-write</access> |
||
| 3465 | </field> |
||
| 3466 | <field> |
||
| 3467 | <name>RXIE</name> |
||
| 3468 | <description>RX Interrupt enable</description> |
||
| 3469 | <bitOffset>2</bitOffset> |
||
| 3470 | <bitWidth>1</bitWidth> |
||
| 3471 | <access>read-write</access> |
||
| 3472 | </field> |
||
| 3473 | <field> |
||
| 3474 | <name>ADDRIE</name> |
||
| 3475 | <description>Address match interrupt enable (slave |
||
| 3476 | only)</description> |
||
| 3477 | <bitOffset>3</bitOffset> |
||
| 3478 | <bitWidth>1</bitWidth> |
||
| 3479 | <access>read-write</access> |
||
| 3480 | </field> |
||
| 3481 | <field> |
||
| 3482 | <name>NACKIE</name> |
||
| 3483 | <description>Not acknowledge received interrupt |
||
| 3484 | enable</description> |
||
| 3485 | <bitOffset>4</bitOffset> |
||
| 3486 | <bitWidth>1</bitWidth> |
||
| 3487 | <access>read-write</access> |
||
| 3488 | </field> |
||
| 3489 | <field> |
||
| 3490 | <name>STOPIE</name> |
||
| 3491 | <description>STOP detection Interrupt |
||
| 3492 | enable</description> |
||
| 3493 | <bitOffset>5</bitOffset> |
||
| 3494 | <bitWidth>1</bitWidth> |
||
| 3495 | <access>read-write</access> |
||
| 3496 | </field> |
||
| 3497 | <field> |
||
| 3498 | <name>TCIE</name> |
||
| 3499 | <description>Transfer Complete interrupt |
||
| 3500 | enable</description> |
||
| 3501 | <bitOffset>6</bitOffset> |
||
| 3502 | <bitWidth>1</bitWidth> |
||
| 3503 | <access>read-write</access> |
||
| 3504 | </field> |
||
| 3505 | <field> |
||
| 3506 | <name>ERRIE</name> |
||
| 3507 | <description>Error interrupts enable</description> |
||
| 3508 | <bitOffset>7</bitOffset> |
||
| 3509 | <bitWidth>1</bitWidth> |
||
| 3510 | <access>read-write</access> |
||
| 3511 | </field> |
||
| 3512 | <field> |
||
| 3513 | <name>DNF</name> |
||
| 3514 | <description>Digital noise filter</description> |
||
| 3515 | <bitOffset>8</bitOffset> |
||
| 3516 | <bitWidth>4</bitWidth> |
||
| 3517 | <access>read-write</access> |
||
| 3518 | </field> |
||
| 3519 | <field> |
||
| 3520 | <name>ANFOFF</name> |
||
| 3521 | <description>Analog noise filter OFF</description> |
||
| 3522 | <bitOffset>12</bitOffset> |
||
| 3523 | <bitWidth>1</bitWidth> |
||
| 3524 | <access>read-write</access> |
||
| 3525 | </field> |
||
| 3526 | <field> |
||
| 3527 | <name>SWRST</name> |
||
| 3528 | <description>Software reset</description> |
||
| 3529 | <bitOffset>13</bitOffset> |
||
| 3530 | <bitWidth>1</bitWidth> |
||
| 3531 | <access>write-only</access> |
||
| 3532 | </field> |
||
| 3533 | <field> |
||
| 3534 | <name>TXDMAEN</name> |
||
| 3535 | <description>DMA transmission requests |
||
| 3536 | enable</description> |
||
| 3537 | <bitOffset>14</bitOffset> |
||
| 3538 | <bitWidth>1</bitWidth> |
||
| 3539 | <access>read-write</access> |
||
| 3540 | </field> |
||
| 3541 | <field> |
||
| 3542 | <name>RXDMAEN</name> |
||
| 3543 | <description>DMA reception requests |
||
| 3544 | enable</description> |
||
| 3545 | <bitOffset>15</bitOffset> |
||
| 3546 | <bitWidth>1</bitWidth> |
||
| 3547 | <access>read-write</access> |
||
| 3548 | </field> |
||
| 3549 | <field> |
||
| 3550 | <name>SBC</name> |
||
| 3551 | <description>Slave byte control</description> |
||
| 3552 | <bitOffset>16</bitOffset> |
||
| 3553 | <bitWidth>1</bitWidth> |
||
| 3554 | <access>read-write</access> |
||
| 3555 | </field> |
||
| 3556 | <field> |
||
| 3557 | <name>NOSTRETCH</name> |
||
| 3558 | <description>Clock stretching disable</description> |
||
| 3559 | <bitOffset>17</bitOffset> |
||
| 3560 | <bitWidth>1</bitWidth> |
||
| 3561 | <access>read-write</access> |
||
| 3562 | </field> |
||
| 3563 | <field> |
||
| 3564 | <name>WUPEN</name> |
||
| 3565 | <description>Wakeup from STOP enable</description> |
||
| 3566 | <bitOffset>18</bitOffset> |
||
| 3567 | <bitWidth>1</bitWidth> |
||
| 3568 | <access>read-write</access> |
||
| 3569 | </field> |
||
| 3570 | <field> |
||
| 3571 | <name>GCEN</name> |
||
| 3572 | <description>General call enable</description> |
||
| 3573 | <bitOffset>19</bitOffset> |
||
| 3574 | <bitWidth>1</bitWidth> |
||
| 3575 | <access>read-write</access> |
||
| 3576 | </field> |
||
| 3577 | <field> |
||
| 3578 | <name>SMBHEN</name> |
||
| 3579 | <description>SMBus Host address enable</description> |
||
| 3580 | <bitOffset>20</bitOffset> |
||
| 3581 | <bitWidth>1</bitWidth> |
||
| 3582 | <access>read-write</access> |
||
| 3583 | </field> |
||
| 3584 | <field> |
||
| 3585 | <name>SMBDEN</name> |
||
| 3586 | <description>SMBus Device Default address |
||
| 3587 | enable</description> |
||
| 3588 | <bitOffset>21</bitOffset> |
||
| 3589 | <bitWidth>1</bitWidth> |
||
| 3590 | <access>read-write</access> |
||
| 3591 | </field> |
||
| 3592 | <field> |
||
| 3593 | <name>ALERTEN</name> |
||
| 3594 | <description>SMBUS alert enable</description> |
||
| 3595 | <bitOffset>22</bitOffset> |
||
| 3596 | <bitWidth>1</bitWidth> |
||
| 3597 | <access>read-write</access> |
||
| 3598 | </field> |
||
| 3599 | <field> |
||
| 3600 | <name>PECEN</name> |
||
| 3601 | <description>PEC enable</description> |
||
| 3602 | <bitOffset>23</bitOffset> |
||
| 3603 | <bitWidth>1</bitWidth> |
||
| 3604 | <access>read-write</access> |
||
| 3605 | </field> |
||
| 3606 | </fields> |
||
| 3607 | </register> |
||
| 3608 | <register> |
||
| 3609 | <name>CR2</name> |
||
| 3610 | <displayName>CR2</displayName> |
||
| 3611 | <description>Control register 2</description> |
||
| 3612 | <addressOffset>0x4</addressOffset> |
||
| 3613 | <size>0x20</size> |
||
| 3614 | <access>read-write</access> |
||
| 3615 | <resetValue>0x00000000</resetValue> |
||
| 3616 | <fields> |
||
| 3617 | <field> |
||
| 3618 | <name>PECBYTE</name> |
||
| 3619 | <description>Packet error checking byte</description> |
||
| 3620 | <bitOffset>26</bitOffset> |
||
| 3621 | <bitWidth>1</bitWidth> |
||
| 3622 | </field> |
||
| 3623 | <field> |
||
| 3624 | <name>AUTOEND</name> |
||
| 3625 | <description>Automatic end mode (master |
||
| 3626 | mode)</description> |
||
| 3627 | <bitOffset>25</bitOffset> |
||
| 3628 | <bitWidth>1</bitWidth> |
||
| 3629 | </field> |
||
| 3630 | <field> |
||
| 3631 | <name>RELOAD</name> |
||
| 3632 | <description>NBYTES reload mode</description> |
||
| 3633 | <bitOffset>24</bitOffset> |
||
| 3634 | <bitWidth>1</bitWidth> |
||
| 3635 | </field> |
||
| 3636 | <field> |
||
| 3637 | <name>NBYTES</name> |
||
| 3638 | <description>Number of bytes</description> |
||
| 3639 | <bitOffset>16</bitOffset> |
||
| 3640 | <bitWidth>8</bitWidth> |
||
| 3641 | </field> |
||
| 3642 | <field> |
||
| 3643 | <name>NACK</name> |
||
| 3644 | <description>NACK generation (slave |
||
| 3645 | mode)</description> |
||
| 3646 | <bitOffset>15</bitOffset> |
||
| 3647 | <bitWidth>1</bitWidth> |
||
| 3648 | </field> |
||
| 3649 | <field> |
||
| 3650 | <name>STOP</name> |
||
| 3651 | <description>Stop generation (master |
||
| 3652 | mode)</description> |
||
| 3653 | <bitOffset>14</bitOffset> |
||
| 3654 | <bitWidth>1</bitWidth> |
||
| 3655 | </field> |
||
| 3656 | <field> |
||
| 3657 | <name>START</name> |
||
| 3658 | <description>Start generation</description> |
||
| 3659 | <bitOffset>13</bitOffset> |
||
| 3660 | <bitWidth>1</bitWidth> |
||
| 3661 | </field> |
||
| 3662 | <field> |
||
| 3663 | <name>HEAD10R</name> |
||
| 3664 | <description>10-bit address header only read |
||
| 3665 | direction (master receiver mode)</description> |
||
| 3666 | <bitOffset>12</bitOffset> |
||
| 3667 | <bitWidth>1</bitWidth> |
||
| 3668 | </field> |
||
| 3669 | <field> |
||
| 3670 | <name>ADD10</name> |
||
| 3671 | <description>10-bit addressing mode (master |
||
| 3672 | mode)</description> |
||
| 3673 | <bitOffset>11</bitOffset> |
||
| 3674 | <bitWidth>1</bitWidth> |
||
| 3675 | </field> |
||
| 3676 | <field> |
||
| 3677 | <name>RD_WRN</name> |
||
| 3678 | <description>Transfer direction (master |
||
| 3679 | mode)</description> |
||
| 3680 | <bitOffset>10</bitOffset> |
||
| 3681 | <bitWidth>1</bitWidth> |
||
| 3682 | </field> |
||
| 3683 | <field> |
||
| 3684 | <name>SADD8</name> |
||
| 3685 | <description>Slave address bit 9:8 (master |
||
| 3686 | mode)</description> |
||
| 3687 | <bitOffset>8</bitOffset> |
||
| 3688 | <bitWidth>2</bitWidth> |
||
| 3689 | </field> |
||
| 3690 | <field> |
||
| 3691 | <name>SADD1</name> |
||
| 3692 | <description>Slave address bit 7:1 (master |
||
| 3693 | mode)</description> |
||
| 3694 | <bitOffset>1</bitOffset> |
||
| 3695 | <bitWidth>7</bitWidth> |
||
| 3696 | </field> |
||
| 3697 | <field> |
||
| 3698 | <name>SADD0</name> |
||
| 3699 | <description>Slave address bit 0 (master |
||
| 3700 | mode)</description> |
||
| 3701 | <bitOffset>0</bitOffset> |
||
| 3702 | <bitWidth>1</bitWidth> |
||
| 3703 | </field> |
||
| 3704 | </fields> |
||
| 3705 | </register> |
||
| 3706 | <register> |
||
| 3707 | <name>OAR1</name> |
||
| 3708 | <displayName>OAR1</displayName> |
||
| 3709 | <description>Own address register 1</description> |
||
| 3710 | <addressOffset>0x8</addressOffset> |
||
| 3711 | <size>0x20</size> |
||
| 3712 | <access>read-write</access> |
||
| 3713 | <resetValue>0x00000000</resetValue> |
||
| 3714 | <fields> |
||
| 3715 | <field> |
||
| 3716 | <name>OA1_0</name> |
||
| 3717 | <description>Interface address</description> |
||
| 3718 | <bitOffset>0</bitOffset> |
||
| 3719 | <bitWidth>1</bitWidth> |
||
| 3720 | </field> |
||
| 3721 | <field> |
||
| 3722 | <name>OA1_1</name> |
||
| 3723 | <description>Interface address</description> |
||
| 3724 | <bitOffset>1</bitOffset> |
||
| 3725 | <bitWidth>7</bitWidth> |
||
| 3726 | </field> |
||
| 3727 | <field> |
||
| 3728 | <name>OA1_8</name> |
||
| 3729 | <description>Interface address</description> |
||
| 3730 | <bitOffset>8</bitOffset> |
||
| 3731 | <bitWidth>2</bitWidth> |
||
| 3732 | </field> |
||
| 3733 | <field> |
||
| 3734 | <name>OA1MODE</name> |
||
| 3735 | <description>Own Address 1 10-bit mode</description> |
||
| 3736 | <bitOffset>10</bitOffset> |
||
| 3737 | <bitWidth>1</bitWidth> |
||
| 3738 | </field> |
||
| 3739 | <field> |
||
| 3740 | <name>OA1EN</name> |
||
| 3741 | <description>Own Address 1 enable</description> |
||
| 3742 | <bitOffset>15</bitOffset> |
||
| 3743 | <bitWidth>1</bitWidth> |
||
| 3744 | </field> |
||
| 3745 | </fields> |
||
| 3746 | </register> |
||
| 3747 | <register> |
||
| 3748 | <name>OAR2</name> |
||
| 3749 | <displayName>OAR2</displayName> |
||
| 3750 | <description>Own address register 2</description> |
||
| 3751 | <addressOffset>0xC</addressOffset> |
||
| 3752 | <size>0x20</size> |
||
| 3753 | <access>read-write</access> |
||
| 3754 | <resetValue>0x00000000</resetValue> |
||
| 3755 | <fields> |
||
| 3756 | <field> |
||
| 3757 | <name>OA2</name> |
||
| 3758 | <description>Interface address</description> |
||
| 3759 | <bitOffset>1</bitOffset> |
||
| 3760 | <bitWidth>7</bitWidth> |
||
| 3761 | </field> |
||
| 3762 | <field> |
||
| 3763 | <name>OA2MSK</name> |
||
| 3764 | <description>Own Address 2 masks</description> |
||
| 3765 | <bitOffset>8</bitOffset> |
||
| 3766 | <bitWidth>3</bitWidth> |
||
| 3767 | </field> |
||
| 3768 | <field> |
||
| 3769 | <name>OA2EN</name> |
||
| 3770 | <description>Own Address 2 enable</description> |
||
| 3771 | <bitOffset>15</bitOffset> |
||
| 3772 | <bitWidth>1</bitWidth> |
||
| 3773 | </field> |
||
| 3774 | </fields> |
||
| 3775 | </register> |
||
| 3776 | <register> |
||
| 3777 | <name>TIMINGR</name> |
||
| 3778 | <displayName>TIMINGR</displayName> |
||
| 3779 | <description>Timing register</description> |
||
| 3780 | <addressOffset>0x10</addressOffset> |
||
| 3781 | <size>0x20</size> |
||
| 3782 | <access>read-write</access> |
||
| 3783 | <resetValue>0x00000000</resetValue> |
||
| 3784 | <fields> |
||
| 3785 | <field> |
||
| 3786 | <name>SCLL</name> |
||
| 3787 | <description>SCL low period (master |
||
| 3788 | mode)</description> |
||
| 3789 | <bitOffset>0</bitOffset> |
||
| 3790 | <bitWidth>8</bitWidth> |
||
| 3791 | </field> |
||
| 3792 | <field> |
||
| 3793 | <name>SCLH</name> |
||
| 3794 | <description>SCL high period (master |
||
| 3795 | mode)</description> |
||
| 3796 | <bitOffset>8</bitOffset> |
||
| 3797 | <bitWidth>8</bitWidth> |
||
| 3798 | </field> |
||
| 3799 | <field> |
||
| 3800 | <name>SDADEL</name> |
||
| 3801 | <description>Data hold time</description> |
||
| 3802 | <bitOffset>16</bitOffset> |
||
| 3803 | <bitWidth>4</bitWidth> |
||
| 3804 | </field> |
||
| 3805 | <field> |
||
| 3806 | <name>SCLDEL</name> |
||
| 3807 | <description>Data setup time</description> |
||
| 3808 | <bitOffset>20</bitOffset> |
||
| 3809 | <bitWidth>4</bitWidth> |
||
| 3810 | </field> |
||
| 3811 | <field> |
||
| 3812 | <name>PRESC</name> |
||
| 3813 | <description>Timing prescaler</description> |
||
| 3814 | <bitOffset>28</bitOffset> |
||
| 3815 | <bitWidth>4</bitWidth> |
||
| 3816 | </field> |
||
| 3817 | </fields> |
||
| 3818 | </register> |
||
| 3819 | <register> |
||
| 3820 | <name>TIMEOUTR</name> |
||
| 3821 | <displayName>TIMEOUTR</displayName> |
||
| 3822 | <description>Status register 1</description> |
||
| 3823 | <addressOffset>0x14</addressOffset> |
||
| 3824 | <size>0x20</size> |
||
| 3825 | <access>read-write</access> |
||
| 3826 | <resetValue>0x00000000</resetValue> |
||
| 3827 | <fields> |
||
| 3828 | <field> |
||
| 3829 | <name>TIMEOUTA</name> |
||
| 3830 | <description>Bus timeout A</description> |
||
| 3831 | <bitOffset>0</bitOffset> |
||
| 3832 | <bitWidth>12</bitWidth> |
||
| 3833 | </field> |
||
| 3834 | <field> |
||
| 3835 | <name>TIDLE</name> |
||
| 3836 | <description>Idle clock timeout |
||
| 3837 | detection</description> |
||
| 3838 | <bitOffset>12</bitOffset> |
||
| 3839 | <bitWidth>1</bitWidth> |
||
| 3840 | </field> |
||
| 3841 | <field> |
||
| 3842 | <name>TIMOUTEN</name> |
||
| 3843 | <description>Clock timeout enable</description> |
||
| 3844 | <bitOffset>15</bitOffset> |
||
| 3845 | <bitWidth>1</bitWidth> |
||
| 3846 | </field> |
||
| 3847 | <field> |
||
| 3848 | <name>TIMEOUTB</name> |
||
| 3849 | <description>Bus timeout B</description> |
||
| 3850 | <bitOffset>16</bitOffset> |
||
| 3851 | <bitWidth>12</bitWidth> |
||
| 3852 | </field> |
||
| 3853 | <field> |
||
| 3854 | <name>TEXTEN</name> |
||
| 3855 | <description>Extended clock timeout |
||
| 3856 | enable</description> |
||
| 3857 | <bitOffset>31</bitOffset> |
||
| 3858 | <bitWidth>1</bitWidth> |
||
| 3859 | </field> |
||
| 3860 | </fields> |
||
| 3861 | </register> |
||
| 3862 | <register> |
||
| 3863 | <name>ISR</name> |
||
| 3864 | <displayName>ISR</displayName> |
||
| 3865 | <description>Interrupt and Status register</description> |
||
| 3866 | <addressOffset>0x18</addressOffset> |
||
| 3867 | <size>0x20</size> |
||
| 3868 | <resetValue>0x00000001</resetValue> |
||
| 3869 | <fields> |
||
| 3870 | <field> |
||
| 3871 | <name>ADDCODE</name> |
||
| 3872 | <description>Address match code (Slave |
||
| 3873 | mode)</description> |
||
| 3874 | <bitOffset>17</bitOffset> |
||
| 3875 | <bitWidth>7</bitWidth> |
||
| 3876 | <access>read-only</access> |
||
| 3877 | </field> |
||
| 3878 | <field> |
||
| 3879 | <name>DIR</name> |
||
| 3880 | <description>Transfer direction (Slave |
||
| 3881 | mode)</description> |
||
| 3882 | <bitOffset>16</bitOffset> |
||
| 3883 | <bitWidth>1</bitWidth> |
||
| 3884 | <access>read-only</access> |
||
| 3885 | </field> |
||
| 3886 | <field> |
||
| 3887 | <name>BUSY</name> |
||
| 3888 | <description>Bus busy</description> |
||
| 3889 | <bitOffset>15</bitOffset> |
||
| 3890 | <bitWidth>1</bitWidth> |
||
| 3891 | <access>read-only</access> |
||
| 3892 | </field> |
||
| 3893 | <field> |
||
| 3894 | <name>ALERT</name> |
||
| 3895 | <description>SMBus alert</description> |
||
| 3896 | <bitOffset>13</bitOffset> |
||
| 3897 | <bitWidth>1</bitWidth> |
||
| 3898 | <access>read-only</access> |
||
| 3899 | </field> |
||
| 3900 | <field> |
||
| 3901 | <name>TIMEOUT</name> |
||
| 3902 | <description>Timeout or t_low detection |
||
| 3903 | flag</description> |
||
| 3904 | <bitOffset>12</bitOffset> |
||
| 3905 | <bitWidth>1</bitWidth> |
||
| 3906 | <access>read-only</access> |
||
| 3907 | </field> |
||
| 3908 | <field> |
||
| 3909 | <name>PECERR</name> |
||
| 3910 | <description>PEC Error in reception</description> |
||
| 3911 | <bitOffset>11</bitOffset> |
||
| 3912 | <bitWidth>1</bitWidth> |
||
| 3913 | <access>read-only</access> |
||
| 3914 | </field> |
||
| 3915 | <field> |
||
| 3916 | <name>OVR</name> |
||
| 3917 | <description>Overrun/Underrun (slave |
||
| 3918 | mode)</description> |
||
| 3919 | <bitOffset>10</bitOffset> |
||
| 3920 | <bitWidth>1</bitWidth> |
||
| 3921 | <access>read-only</access> |
||
| 3922 | </field> |
||
| 3923 | <field> |
||
| 3924 | <name>ARLO</name> |
||
| 3925 | <description>Arbitration lost</description> |
||
| 3926 | <bitOffset>9</bitOffset> |
||
| 3927 | <bitWidth>1</bitWidth> |
||
| 3928 | <access>read-only</access> |
||
| 3929 | </field> |
||
| 3930 | <field> |
||
| 3931 | <name>BERR</name> |
||
| 3932 | <description>Bus error</description> |
||
| 3933 | <bitOffset>8</bitOffset> |
||
| 3934 | <bitWidth>1</bitWidth> |
||
| 3935 | <access>read-only</access> |
||
| 3936 | </field> |
||
| 3937 | <field> |
||
| 3938 | <name>TCR</name> |
||
| 3939 | <description>Transfer Complete Reload</description> |
||
| 3940 | <bitOffset>7</bitOffset> |
||
| 3941 | <bitWidth>1</bitWidth> |
||
| 3942 | <access>read-only</access> |
||
| 3943 | </field> |
||
| 3944 | <field> |
||
| 3945 | <name>TC</name> |
||
| 3946 | <description>Transfer Complete (master |
||
| 3947 | mode)</description> |
||
| 3948 | <bitOffset>6</bitOffset> |
||
| 3949 | <bitWidth>1</bitWidth> |
||
| 3950 | <access>read-only</access> |
||
| 3951 | </field> |
||
| 3952 | <field> |
||
| 3953 | <name>STOPF</name> |
||
| 3954 | <description>Stop detection flag</description> |
||
| 3955 | <bitOffset>5</bitOffset> |
||
| 3956 | <bitWidth>1</bitWidth> |
||
| 3957 | <access>read-only</access> |
||
| 3958 | </field> |
||
| 3959 | <field> |
||
| 3960 | <name>NACKF</name> |
||
| 3961 | <description>Not acknowledge received |
||
| 3962 | flag</description> |
||
| 3963 | <bitOffset>4</bitOffset> |
||
| 3964 | <bitWidth>1</bitWidth> |
||
| 3965 | <access>read-only</access> |
||
| 3966 | </field> |
||
| 3967 | <field> |
||
| 3968 | <name>ADDR</name> |
||
| 3969 | <description>Address matched (slave |
||
| 3970 | mode)</description> |
||
| 3971 | <bitOffset>3</bitOffset> |
||
| 3972 | <bitWidth>1</bitWidth> |
||
| 3973 | <access>read-only</access> |
||
| 3974 | </field> |
||
| 3975 | <field> |
||
| 3976 | <name>RXNE</name> |
||
| 3977 | <description>Receive data register not empty |
||
| 3978 | (receivers)</description> |
||
| 3979 | <bitOffset>2</bitOffset> |
||
| 3980 | <bitWidth>1</bitWidth> |
||
| 3981 | <access>read-only</access> |
||
| 3982 | </field> |
||
| 3983 | <field> |
||
| 3984 | <name>TXIS</name> |
||
| 3985 | <description>Transmit interrupt status |
||
| 3986 | (transmitters)</description> |
||
| 3987 | <bitOffset>1</bitOffset> |
||
| 3988 | <bitWidth>1</bitWidth> |
||
| 3989 | <access>read-write</access> |
||
| 3990 | </field> |
||
| 3991 | <field> |
||
| 3992 | <name>TXE</name> |
||
| 3993 | <description>Transmit data register empty |
||
| 3994 | (transmitters)</description> |
||
| 3995 | <bitOffset>0</bitOffset> |
||
| 3996 | <bitWidth>1</bitWidth> |
||
| 3997 | <access>read-write</access> |
||
| 3998 | </field> |
||
| 3999 | </fields> |
||
| 4000 | </register> |
||
| 4001 | <register> |
||
| 4002 | <name>ICR</name> |
||
| 4003 | <displayName>ICR</displayName> |
||
| 4004 | <description>Interrupt clear register</description> |
||
| 4005 | <addressOffset>0x1C</addressOffset> |
||
| 4006 | <size>0x20</size> |
||
| 4007 | <access>write-only</access> |
||
| 4008 | <resetValue>0x00000000</resetValue> |
||
| 4009 | <fields> |
||
| 4010 | <field> |
||
| 4011 | <name>ALERTCF</name> |
||
| 4012 | <description>Alert flag clear</description> |
||
| 4013 | <bitOffset>13</bitOffset> |
||
| 4014 | <bitWidth>1</bitWidth> |
||
| 4015 | </field> |
||
| 4016 | <field> |
||
| 4017 | <name>TIMOUTCF</name> |
||
| 4018 | <description>Timeout detection flag |
||
| 4019 | clear</description> |
||
| 4020 | <bitOffset>12</bitOffset> |
||
| 4021 | <bitWidth>1</bitWidth> |
||
| 4022 | </field> |
||
| 4023 | <field> |
||
| 4024 | <name>PECCF</name> |
||
| 4025 | <description>PEC Error flag clear</description> |
||
| 4026 | <bitOffset>11</bitOffset> |
||
| 4027 | <bitWidth>1</bitWidth> |
||
| 4028 | </field> |
||
| 4029 | <field> |
||
| 4030 | <name>OVRCF</name> |
||
| 4031 | <description>Overrun/Underrun flag |
||
| 4032 | clear</description> |
||
| 4033 | <bitOffset>10</bitOffset> |
||
| 4034 | <bitWidth>1</bitWidth> |
||
| 4035 | </field> |
||
| 4036 | <field> |
||
| 4037 | <name>ARLOCF</name> |
||
| 4038 | <description>Arbitration lost flag |
||
| 4039 | clear</description> |
||
| 4040 | <bitOffset>9</bitOffset> |
||
| 4041 | <bitWidth>1</bitWidth> |
||
| 4042 | </field> |
||
| 4043 | <field> |
||
| 4044 | <name>BERRCF</name> |
||
| 4045 | <description>Bus error flag clear</description> |
||
| 4046 | <bitOffset>8</bitOffset> |
||
| 4047 | <bitWidth>1</bitWidth> |
||
| 4048 | </field> |
||
| 4049 | <field> |
||
| 4050 | <name>STOPCF</name> |
||
| 4051 | <description>Stop detection flag clear</description> |
||
| 4052 | <bitOffset>5</bitOffset> |
||
| 4053 | <bitWidth>1</bitWidth> |
||
| 4054 | </field> |
||
| 4055 | <field> |
||
| 4056 | <name>NACKCF</name> |
||
| 4057 | <description>Not Acknowledge flag clear</description> |
||
| 4058 | <bitOffset>4</bitOffset> |
||
| 4059 | <bitWidth>1</bitWidth> |
||
| 4060 | </field> |
||
| 4061 | <field> |
||
| 4062 | <name>ADDRCF</name> |
||
| 4063 | <description>Address Matched flag clear</description> |
||
| 4064 | <bitOffset>3</bitOffset> |
||
| 4065 | <bitWidth>1</bitWidth> |
||
| 4066 | </field> |
||
| 4067 | </fields> |
||
| 4068 | </register> |
||
| 4069 | <register> |
||
| 4070 | <name>PECR</name> |
||
| 4071 | <displayName>PECR</displayName> |
||
| 4072 | <description>PEC register</description> |
||
| 4073 | <addressOffset>0x20</addressOffset> |
||
| 4074 | <size>0x20</size> |
||
| 4075 | <access>read-only</access> |
||
| 4076 | <resetValue>0x00000000</resetValue> |
||
| 4077 | <fields> |
||
| 4078 | <field> |
||
| 4079 | <name>PEC</name> |
||
| 4080 | <description>Packet error checking |
||
| 4081 | register</description> |
||
| 4082 | <bitOffset>0</bitOffset> |
||
| 4083 | <bitWidth>8</bitWidth> |
||
| 4084 | </field> |
||
| 4085 | </fields> |
||
| 4086 | </register> |
||
| 4087 | <register> |
||
| 4088 | <name>RXDR</name> |
||
| 4089 | <displayName>RXDR</displayName> |
||
| 4090 | <description>Receive data register</description> |
||
| 4091 | <addressOffset>0x24</addressOffset> |
||
| 4092 | <size>0x20</size> |
||
| 4093 | <access>read-only</access> |
||
| 4094 | <resetValue>0x00000000</resetValue> |
||
| 4095 | <fields> |
||
| 4096 | <field> |
||
| 4097 | <name>RXDATA</name> |
||
| 4098 | <description>8-bit receive data</description> |
||
| 4099 | <bitOffset>0</bitOffset> |
||
| 4100 | <bitWidth>8</bitWidth> |
||
| 4101 | </field> |
||
| 4102 | </fields> |
||
| 4103 | </register> |
||
| 4104 | <register> |
||
| 4105 | <name>TXDR</name> |
||
| 4106 | <displayName>TXDR</displayName> |
||
| 4107 | <description>Transmit data register</description> |
||
| 4108 | <addressOffset>0x28</addressOffset> |
||
| 4109 | <size>0x20</size> |
||
| 4110 | <access>read-write</access> |
||
| 4111 | <resetValue>0x00000000</resetValue> |
||
| 4112 | <fields> |
||
| 4113 | <field> |
||
| 4114 | <name>TXDATA</name> |
||
| 4115 | <description>8-bit transmit data</description> |
||
| 4116 | <bitOffset>0</bitOffset> |
||
| 4117 | <bitWidth>8</bitWidth> |
||
| 4118 | </field> |
||
| 4119 | </fields> |
||
| 4120 | </register> |
||
| 4121 | </registers> |
||
| 4122 | </peripheral> |
||
| 4123 | <peripheral derivedFrom="I2C1"> |
||
| 4124 | <name>I2C2</name> |
||
| 4125 | <baseAddress>0x40005800</baseAddress> |
||
| 4126 | <interrupt> |
||
| 4127 | <name>I2C1</name> |
||
| 4128 | <description>I2C1 global interrupt</description> |
||
| 4129 | <value>23</value> |
||
| 4130 | </interrupt> |
||
| 4131 | </peripheral> |
||
| 4132 | <peripheral> |
||
| 4133 | <name>IWDG</name> |
||
| 4134 | <description>Independent watchdog</description> |
||
| 4135 | <groupName>IWDG</groupName> |
||
| 4136 | <baseAddress>0x40003000</baseAddress> |
||
| 4137 | <addressBlock> |
||
| 4138 | <offset>0x0</offset> |
||
| 4139 | <size>0x400</size> |
||
| 4140 | <usage>registers</usage> |
||
| 4141 | </addressBlock> |
||
| 4142 | <interrupt> |
||
| 4143 | <name>I2C2</name> |
||
| 4144 | <description>I2C2 global interrupt</description> |
||
| 4145 | <value>24</value> |
||
| 4146 | </interrupt> |
||
| 4147 | <registers> |
||
| 4148 | <register> |
||
| 4149 | <name>KR</name> |
||
| 4150 | <displayName>KR</displayName> |
||
| 4151 | <description>Key register</description> |
||
| 4152 | <addressOffset>0x0</addressOffset> |
||
| 4153 | <size>0x20</size> |
||
| 4154 | <access>write-only</access> |
||
| 4155 | <resetValue>0x00000000</resetValue> |
||
| 4156 | <fields> |
||
| 4157 | <field> |
||
| 4158 | <name>KEY</name> |
||
| 4159 | <description>Key value</description> |
||
| 4160 | <bitOffset>0</bitOffset> |
||
| 4161 | <bitWidth>16</bitWidth> |
||
| 4162 | </field> |
||
| 4163 | </fields> |
||
| 4164 | </register> |
||
| 4165 | <register> |
||
| 4166 | <name>PR</name> |
||
| 4167 | <displayName>PR</displayName> |
||
| 4168 | <description>Prescaler register</description> |
||
| 4169 | <addressOffset>0x4</addressOffset> |
||
| 4170 | <size>0x20</size> |
||
| 4171 | <access>read-write</access> |
||
| 4172 | <resetValue>0x00000000</resetValue> |
||
| 4173 | <fields> |
||
| 4174 | <field> |
||
| 4175 | <name>PR</name> |
||
| 4176 | <description>Prescaler divider</description> |
||
| 4177 | <bitOffset>0</bitOffset> |
||
| 4178 | <bitWidth>3</bitWidth> |
||
| 4179 | </field> |
||
| 4180 | </fields> |
||
| 4181 | </register> |
||
| 4182 | <register> |
||
| 4183 | <name>RLR</name> |
||
| 4184 | <displayName>RLR</displayName> |
||
| 4185 | <description>Reload register</description> |
||
| 4186 | <addressOffset>0x8</addressOffset> |
||
| 4187 | <size>0x20</size> |
||
| 4188 | <access>read-write</access> |
||
| 4189 | <resetValue>0x00000FFF</resetValue> |
||
| 4190 | <fields> |
||
| 4191 | <field> |
||
| 4192 | <name>RL</name> |
||
| 4193 | <description>Watchdog counter reload |
||
| 4194 | value</description> |
||
| 4195 | <bitOffset>0</bitOffset> |
||
| 4196 | <bitWidth>12</bitWidth> |
||
| 4197 | </field> |
||
| 4198 | </fields> |
||
| 4199 | </register> |
||
| 4200 | <register> |
||
| 4201 | <name>SR</name> |
||
| 4202 | <displayName>SR</displayName> |
||
| 4203 | <description>Status register</description> |
||
| 4204 | <addressOffset>0xC</addressOffset> |
||
| 4205 | <size>0x20</size> |
||
| 4206 | <access>read-only</access> |
||
| 4207 | <resetValue>0x00000000</resetValue> |
||
| 4208 | <fields> |
||
| 4209 | <field> |
||
| 4210 | <name>PVU</name> |
||
| 4211 | <description>Watchdog prescaler value |
||
| 4212 | update</description> |
||
| 4213 | <bitOffset>0</bitOffset> |
||
| 4214 | <bitWidth>1</bitWidth> |
||
| 4215 | </field> |
||
| 4216 | <field> |
||
| 4217 | <name>RVU</name> |
||
| 4218 | <description>Watchdog counter reload value |
||
| 4219 | update</description> |
||
| 4220 | <bitOffset>1</bitOffset> |
||
| 4221 | <bitWidth>1</bitWidth> |
||
| 4222 | </field> |
||
| 4223 | <field> |
||
| 4224 | <name>WVU</name> |
||
| 4225 | <description>Watchdog counter window value |
||
| 4226 | update</description> |
||
| 4227 | <bitOffset>2</bitOffset> |
||
| 4228 | <bitWidth>1</bitWidth> |
||
| 4229 | </field> |
||
| 4230 | </fields> |
||
| 4231 | </register> |
||
| 4232 | <register> |
||
| 4233 | <name>WINR</name> |
||
| 4234 | <displayName>WINR</displayName> |
||
| 4235 | <description>Window register</description> |
||
| 4236 | <addressOffset>0x10</addressOffset> |
||
| 4237 | <size>0x20</size> |
||
| 4238 | <access>read-write</access> |
||
| 4239 | <resetValue>0x00000FFF</resetValue> |
||
| 4240 | <fields> |
||
| 4241 | <field> |
||
| 4242 | <name>WIN</name> |
||
| 4243 | <description>Watchdog counter window |
||
| 4244 | value</description> |
||
| 4245 | <bitOffset>0</bitOffset> |
||
| 4246 | <bitWidth>12</bitWidth> |
||
| 4247 | </field> |
||
| 4248 | </fields> |
||
| 4249 | </register> |
||
| 4250 | </registers> |
||
| 4251 | </peripheral> |
||
| 4252 | <peripheral> |
||
| 4253 | <name>WWDG</name> |
||
| 4254 | <description>Window watchdog</description> |
||
| 4255 | <groupName>WWDG</groupName> |
||
| 4256 | <baseAddress>0x40002C00</baseAddress> |
||
| 4257 | <addressBlock> |
||
| 4258 | <offset>0x0</offset> |
||
| 4259 | <size>0x400</size> |
||
| 4260 | <usage>registers</usage> |
||
| 4261 | </addressBlock> |
||
| 4262 | <registers> |
||
| 4263 | <register> |
||
| 4264 | <name>CR</name> |
||
| 4265 | <displayName>CR</displayName> |
||
| 4266 | <description>Control register</description> |
||
| 4267 | <addressOffset>0x0</addressOffset> |
||
| 4268 | <size>0x20</size> |
||
| 4269 | <access>read-write</access> |
||
| 4270 | <resetValue>0x0000007F</resetValue> |
||
| 4271 | <fields> |
||
| 4272 | <field> |
||
| 4273 | <name>WDGA</name> |
||
| 4274 | <description>Activation bit</description> |
||
| 4275 | <bitOffset>7</bitOffset> |
||
| 4276 | <bitWidth>1</bitWidth> |
||
| 4277 | </field> |
||
| 4278 | <field> |
||
| 4279 | <name>T</name> |
||
| 4280 | <description>7-bit counter</description> |
||
| 4281 | <bitOffset>0</bitOffset> |
||
| 4282 | <bitWidth>7</bitWidth> |
||
| 4283 | </field> |
||
| 4284 | </fields> |
||
| 4285 | </register> |
||
| 4286 | <register> |
||
| 4287 | <name>CFR</name> |
||
| 4288 | <displayName>CFR</displayName> |
||
| 4289 | <description>Configuration register</description> |
||
| 4290 | <addressOffset>0x4</addressOffset> |
||
| 4291 | <size>0x20</size> |
||
| 4292 | <access>read-write</access> |
||
| 4293 | <resetValue>0x0000007F</resetValue> |
||
| 4294 | <fields> |
||
| 4295 | <field> |
||
| 4296 | <name>EWI</name> |
||
| 4297 | <description>Early wakeup interrupt</description> |
||
| 4298 | <bitOffset>9</bitOffset> |
||
| 4299 | <bitWidth>1</bitWidth> |
||
| 4300 | </field> |
||
| 4301 | <field> |
||
| 4302 | <name>WDGTB</name> |
||
| 4303 | <description>Timer base</description> |
||
| 4304 | <bitOffset>7</bitOffset> |
||
| 4305 | <bitWidth>2</bitWidth> |
||
| 4306 | </field> |
||
| 4307 | <field> |
||
| 4308 | <name>W</name> |
||
| 4309 | <description>7-bit window value</description> |
||
| 4310 | <bitOffset>0</bitOffset> |
||
| 4311 | <bitWidth>7</bitWidth> |
||
| 4312 | </field> |
||
| 4313 | </fields> |
||
| 4314 | </register> |
||
| 4315 | <register> |
||
| 4316 | <name>SR</name> |
||
| 4317 | <displayName>SR</displayName> |
||
| 4318 | <description>Status register</description> |
||
| 4319 | <addressOffset>0x8</addressOffset> |
||
| 4320 | <size>0x20</size> |
||
| 4321 | <access>read-write</access> |
||
| 4322 | <resetValue>0x00000000</resetValue> |
||
| 4323 | <fields> |
||
| 4324 | <field> |
||
| 4325 | <name>EWIF</name> |
||
| 4326 | <description>Early wakeup interrupt |
||
| 4327 | flag</description> |
||
| 4328 | <bitOffset>0</bitOffset> |
||
| 4329 | <bitWidth>1</bitWidth> |
||
| 4330 | </field> |
||
| 4331 | </fields> |
||
| 4332 | </register> |
||
| 4333 | </registers> |
||
| 4334 | </peripheral> |
||
| 4335 | <peripheral> |
||
| 4336 | <name>TIM1</name> |
||
| 4337 | <description>Advanced-timers</description> |
||
| 4338 | <groupName>TIM</groupName> |
||
| 4339 | <baseAddress>0x40012C00</baseAddress> |
||
| 4340 | <addressBlock> |
||
| 4341 | <offset>0x0</offset> |
||
| 4342 | <size>0x400</size> |
||
| 4343 | <usage>registers</usage> |
||
| 4344 | </addressBlock> |
||
| 4345 | <interrupt> |
||
| 4346 | <name>WWDG</name> |
||
| 4347 | <description>Window Watchdog interrupt</description> |
||
| 4348 | <value>0</value> |
||
| 4349 | </interrupt> |
||
| 4350 | <registers> |
||
| 4351 | <register> |
||
| 4352 | <name>CR1</name> |
||
| 4353 | <displayName>CR1</displayName> |
||
| 4354 | <description>control register 1</description> |
||
| 4355 | <addressOffset>0x0</addressOffset> |
||
| 4356 | <size>0x20</size> |
||
| 4357 | <access>read-write</access> |
||
| 4358 | <resetValue>0x0000</resetValue> |
||
| 4359 | <fields> |
||
| 4360 | <field> |
||
| 4361 | <name>CKD</name> |
||
| 4362 | <description>Clock division</description> |
||
| 4363 | <bitOffset>8</bitOffset> |
||
| 4364 | <bitWidth>2</bitWidth> |
||
| 4365 | </field> |
||
| 4366 | <field> |
||
| 4367 | <name>ARPE</name> |
||
| 4368 | <description>Auto-reload preload enable</description> |
||
| 4369 | <bitOffset>7</bitOffset> |
||
| 4370 | <bitWidth>1</bitWidth> |
||
| 4371 | </field> |
||
| 4372 | <field> |
||
| 4373 | <name>CMS</name> |
||
| 4374 | <description>Center-aligned mode |
||
| 4375 | selection</description> |
||
| 4376 | <bitOffset>5</bitOffset> |
||
| 4377 | <bitWidth>2</bitWidth> |
||
| 4378 | </field> |
||
| 4379 | <field> |
||
| 4380 | <name>DIR</name> |
||
| 4381 | <description>Direction</description> |
||
| 4382 | <bitOffset>4</bitOffset> |
||
| 4383 | <bitWidth>1</bitWidth> |
||
| 4384 | </field> |
||
| 4385 | <field> |
||
| 4386 | <name>OPM</name> |
||
| 4387 | <description>One-pulse mode</description> |
||
| 4388 | <bitOffset>3</bitOffset> |
||
| 4389 | <bitWidth>1</bitWidth> |
||
| 4390 | </field> |
||
| 4391 | <field> |
||
| 4392 | <name>URS</name> |
||
| 4393 | <description>Update request source</description> |
||
| 4394 | <bitOffset>2</bitOffset> |
||
| 4395 | <bitWidth>1</bitWidth> |
||
| 4396 | </field> |
||
| 4397 | <field> |
||
| 4398 | <name>UDIS</name> |
||
| 4399 | <description>Update disable</description> |
||
| 4400 | <bitOffset>1</bitOffset> |
||
| 4401 | <bitWidth>1</bitWidth> |
||
| 4402 | </field> |
||
| 4403 | <field> |
||
| 4404 | <name>CEN</name> |
||
| 4405 | <description>Counter enable</description> |
||
| 4406 | <bitOffset>0</bitOffset> |
||
| 4407 | <bitWidth>1</bitWidth> |
||
| 4408 | </field> |
||
| 4409 | </fields> |
||
| 4410 | </register> |
||
| 4411 | <register> |
||
| 4412 | <name>CR2</name> |
||
| 4413 | <displayName>CR2</displayName> |
||
| 4414 | <description>control register 2</description> |
||
| 4415 | <addressOffset>0x4</addressOffset> |
||
| 4416 | <size>0x20</size> |
||
| 4417 | <access>read-write</access> |
||
| 4418 | <resetValue>0x0000</resetValue> |
||
| 4419 | <fields> |
||
| 4420 | <field> |
||
| 4421 | <name>OIS4</name> |
||
| 4422 | <description>Output Idle state 4</description> |
||
| 4423 | <bitOffset>14</bitOffset> |
||
| 4424 | <bitWidth>1</bitWidth> |
||
| 4425 | </field> |
||
| 4426 | <field> |
||
| 4427 | <name>OIS3N</name> |
||
| 4428 | <description>Output Idle state 3</description> |
||
| 4429 | <bitOffset>13</bitOffset> |
||
| 4430 | <bitWidth>1</bitWidth> |
||
| 4431 | </field> |
||
| 4432 | <field> |
||
| 4433 | <name>OIS3</name> |
||
| 4434 | <description>Output Idle state 3</description> |
||
| 4435 | <bitOffset>12</bitOffset> |
||
| 4436 | <bitWidth>1</bitWidth> |
||
| 4437 | </field> |
||
| 4438 | <field> |
||
| 4439 | <name>OIS2N</name> |
||
| 4440 | <description>Output Idle state 2</description> |
||
| 4441 | <bitOffset>11</bitOffset> |
||
| 4442 | <bitWidth>1</bitWidth> |
||
| 4443 | </field> |
||
| 4444 | <field> |
||
| 4445 | <name>OIS2</name> |
||
| 4446 | <description>Output Idle state 2</description> |
||
| 4447 | <bitOffset>10</bitOffset> |
||
| 4448 | <bitWidth>1</bitWidth> |
||
| 4449 | </field> |
||
| 4450 | <field> |
||
| 4451 | <name>OIS1N</name> |
||
| 4452 | <description>Output Idle state 1</description> |
||
| 4453 | <bitOffset>9</bitOffset> |
||
| 4454 | <bitWidth>1</bitWidth> |
||
| 4455 | </field> |
||
| 4456 | <field> |
||
| 4457 | <name>OIS1</name> |
||
| 4458 | <description>Output Idle state 1</description> |
||
| 4459 | <bitOffset>8</bitOffset> |
||
| 4460 | <bitWidth>1</bitWidth> |
||
| 4461 | </field> |
||
| 4462 | <field> |
||
| 4463 | <name>TI1S</name> |
||
| 4464 | <description>TI1 selection</description> |
||
| 4465 | <bitOffset>7</bitOffset> |
||
| 4466 | <bitWidth>1</bitWidth> |
||
| 4467 | </field> |
||
| 4468 | <field> |
||
| 4469 | <name>MMS</name> |
||
| 4470 | <description>Master mode selection</description> |
||
| 4471 | <bitOffset>4</bitOffset> |
||
| 4472 | <bitWidth>3</bitWidth> |
||
| 4473 | </field> |
||
| 4474 | <field> |
||
| 4475 | <name>CCDS</name> |
||
| 4476 | <description>Capture/compare DMA |
||
| 4477 | selection</description> |
||
| 4478 | <bitOffset>3</bitOffset> |
||
| 4479 | <bitWidth>1</bitWidth> |
||
| 4480 | </field> |
||
| 4481 | <field> |
||
| 4482 | <name>CCUS</name> |
||
| 4483 | <description>Capture/compare control update |
||
| 4484 | selection</description> |
||
| 4485 | <bitOffset>2</bitOffset> |
||
| 4486 | <bitWidth>1</bitWidth> |
||
| 4487 | </field> |
||
| 4488 | <field> |
||
| 4489 | <name>CCPC</name> |
||
| 4490 | <description>Capture/compare preloaded |
||
| 4491 | control</description> |
||
| 4492 | <bitOffset>0</bitOffset> |
||
| 4493 | <bitWidth>1</bitWidth> |
||
| 4494 | </field> |
||
| 4495 | </fields> |
||
| 4496 | </register> |
||
| 4497 | <register> |
||
| 4498 | <name>SMCR</name> |
||
| 4499 | <displayName>SMCR</displayName> |
||
| 4500 | <description>slave mode control register</description> |
||
| 4501 | <addressOffset>0x8</addressOffset> |
||
| 4502 | <size>0x20</size> |
||
| 4503 | <access>read-write</access> |
||
| 4504 | <resetValue>0x0000</resetValue> |
||
| 4505 | <fields> |
||
| 4506 | <field> |
||
| 4507 | <name>ETP</name> |
||
| 4508 | <description>External trigger polarity</description> |
||
| 4509 | <bitOffset>15</bitOffset> |
||
| 4510 | <bitWidth>1</bitWidth> |
||
| 4511 | </field> |
||
| 4512 | <field> |
||
| 4513 | <name>ECE</name> |
||
| 4514 | <description>External clock enable</description> |
||
| 4515 | <bitOffset>14</bitOffset> |
||
| 4516 | <bitWidth>1</bitWidth> |
||
| 4517 | </field> |
||
| 4518 | <field> |
||
| 4519 | <name>ETPS</name> |
||
| 4520 | <description>External trigger prescaler</description> |
||
| 4521 | <bitOffset>12</bitOffset> |
||
| 4522 | <bitWidth>2</bitWidth> |
||
| 4523 | </field> |
||
| 4524 | <field> |
||
| 4525 | <name>ETF</name> |
||
| 4526 | <description>External trigger filter</description> |
||
| 4527 | <bitOffset>8</bitOffset> |
||
| 4528 | <bitWidth>4</bitWidth> |
||
| 4529 | </field> |
||
| 4530 | <field> |
||
| 4531 | <name>MSM</name> |
||
| 4532 | <description>Master/Slave mode</description> |
||
| 4533 | <bitOffset>7</bitOffset> |
||
| 4534 | <bitWidth>1</bitWidth> |
||
| 4535 | </field> |
||
| 4536 | <field> |
||
| 4537 | <name>TS</name> |
||
| 4538 | <description>Trigger selection</description> |
||
| 4539 | <bitOffset>4</bitOffset> |
||
| 4540 | <bitWidth>3</bitWidth> |
||
| 4541 | </field> |
||
| 4542 | <field> |
||
| 4543 | <name>SMS</name> |
||
| 4544 | <description>Slave mode selection</description> |
||
| 4545 | <bitOffset>0</bitOffset> |
||
| 4546 | <bitWidth>3</bitWidth> |
||
| 4547 | </field> |
||
| 4548 | </fields> |
||
| 4549 | </register> |
||
| 4550 | <register> |
||
| 4551 | <name>DIER</name> |
||
| 4552 | <displayName>DIER</displayName> |
||
| 4553 | <description>DMA/Interrupt enable register</description> |
||
| 4554 | <addressOffset>0xC</addressOffset> |
||
| 4555 | <size>0x20</size> |
||
| 4556 | <access>read-write</access> |
||
| 4557 | <resetValue>0x0000</resetValue> |
||
| 4558 | <fields> |
||
| 4559 | <field> |
||
| 4560 | <name>TDE</name> |
||
| 4561 | <description>Trigger DMA request enable</description> |
||
| 4562 | <bitOffset>14</bitOffset> |
||
| 4563 | <bitWidth>1</bitWidth> |
||
| 4564 | </field> |
||
| 4565 | <field> |
||
| 4566 | <name>COMDE</name> |
||
| 4567 | <description>Reserved</description> |
||
| 4568 | <bitOffset>13</bitOffset> |
||
| 4569 | <bitWidth>1</bitWidth> |
||
| 4570 | </field> |
||
| 4571 | <field> |
||
| 4572 | <name>CC4DE</name> |
||
| 4573 | <description>Capture/Compare 4 DMA request |
||
| 4574 | enable</description> |
||
| 4575 | <bitOffset>12</bitOffset> |
||
| 4576 | <bitWidth>1</bitWidth> |
||
| 4577 | </field> |
||
| 4578 | <field> |
||
| 4579 | <name>CC3DE</name> |
||
| 4580 | <description>Capture/Compare 3 DMA request |
||
| 4581 | enable</description> |
||
| 4582 | <bitOffset>11</bitOffset> |
||
| 4583 | <bitWidth>1</bitWidth> |
||
| 4584 | </field> |
||
| 4585 | <field> |
||
| 4586 | <name>CC2DE</name> |
||
| 4587 | <description>Capture/Compare 2 DMA request |
||
| 4588 | enable</description> |
||
| 4589 | <bitOffset>10</bitOffset> |
||
| 4590 | <bitWidth>1</bitWidth> |
||
| 4591 | </field> |
||
| 4592 | <field> |
||
| 4593 | <name>CC1DE</name> |
||
| 4594 | <description>Capture/Compare 1 DMA request |
||
| 4595 | enable</description> |
||
| 4596 | <bitOffset>9</bitOffset> |
||
| 4597 | <bitWidth>1</bitWidth> |
||
| 4598 | </field> |
||
| 4599 | <field> |
||
| 4600 | <name>UDE</name> |
||
| 4601 | <description>Update DMA request enable</description> |
||
| 4602 | <bitOffset>8</bitOffset> |
||
| 4603 | <bitWidth>1</bitWidth> |
||
| 4604 | </field> |
||
| 4605 | <field> |
||
| 4606 | <name>BIE</name> |
||
| 4607 | <description>Break interrupt enable</description> |
||
| 4608 | <bitOffset>7</bitOffset> |
||
| 4609 | <bitWidth>1</bitWidth> |
||
| 4610 | </field> |
||
| 4611 | <field> |
||
| 4612 | <name>TIE</name> |
||
| 4613 | <description>Trigger interrupt enable</description> |
||
| 4614 | <bitOffset>6</bitOffset> |
||
| 4615 | <bitWidth>1</bitWidth> |
||
| 4616 | </field> |
||
| 4617 | <field> |
||
| 4618 | <name>COMIE</name> |
||
| 4619 | <description>COM interrupt enable</description> |
||
| 4620 | <bitOffset>5</bitOffset> |
||
| 4621 | <bitWidth>1</bitWidth> |
||
| 4622 | </field> |
||
| 4623 | <field> |
||
| 4624 | <name>CC4IE</name> |
||
| 4625 | <description>Capture/Compare 4 interrupt |
||
| 4626 | enable</description> |
||
| 4627 | <bitOffset>4</bitOffset> |
||
| 4628 | <bitWidth>1</bitWidth> |
||
| 4629 | </field> |
||
| 4630 | <field> |
||
| 4631 | <name>CC3IE</name> |
||
| 4632 | <description>Capture/Compare 3 interrupt |
||
| 4633 | enable</description> |
||
| 4634 | <bitOffset>3</bitOffset> |
||
| 4635 | <bitWidth>1</bitWidth> |
||
| 4636 | </field> |
||
| 4637 | <field> |
||
| 4638 | <name>CC2IE</name> |
||
| 4639 | <description>Capture/Compare 2 interrupt |
||
| 4640 | enable</description> |
||
| 4641 | <bitOffset>2</bitOffset> |
||
| 4642 | <bitWidth>1</bitWidth> |
||
| 4643 | </field> |
||
| 4644 | <field> |
||
| 4645 | <name>CC1IE</name> |
||
| 4646 | <description>Capture/Compare 1 interrupt |
||
| 4647 | enable</description> |
||
| 4648 | <bitOffset>1</bitOffset> |
||
| 4649 | <bitWidth>1</bitWidth> |
||
| 4650 | </field> |
||
| 4651 | <field> |
||
| 4652 | <name>UIE</name> |
||
| 4653 | <description>Update interrupt enable</description> |
||
| 4654 | <bitOffset>0</bitOffset> |
||
| 4655 | <bitWidth>1</bitWidth> |
||
| 4656 | </field> |
||
| 4657 | </fields> |
||
| 4658 | </register> |
||
| 4659 | <register> |
||
| 4660 | <name>SR</name> |
||
| 4661 | <displayName>SR</displayName> |
||
| 4662 | <description>status register</description> |
||
| 4663 | <addressOffset>0x10</addressOffset> |
||
| 4664 | <size>0x20</size> |
||
| 4665 | <access>read-write</access> |
||
| 4666 | <resetValue>0x0000</resetValue> |
||
| 4667 | <fields> |
||
| 4668 | <field> |
||
| 4669 | <name>CC4OF</name> |
||
| 4670 | <description>Capture/Compare 4 overcapture |
||
| 4671 | flag</description> |
||
| 4672 | <bitOffset>12</bitOffset> |
||
| 4673 | <bitWidth>1</bitWidth> |
||
| 4674 | </field> |
||
| 4675 | <field> |
||
| 4676 | <name>CC3OF</name> |
||
| 4677 | <description>Capture/Compare 3 overcapture |
||
| 4678 | flag</description> |
||
| 4679 | <bitOffset>11</bitOffset> |
||
| 4680 | <bitWidth>1</bitWidth> |
||
| 4681 | </field> |
||
| 4682 | <field> |
||
| 4683 | <name>CC2OF</name> |
||
| 4684 | <description>Capture/compare 2 overcapture |
||
| 4685 | flag</description> |
||
| 4686 | <bitOffset>10</bitOffset> |
||
| 4687 | <bitWidth>1</bitWidth> |
||
| 4688 | </field> |
||
| 4689 | <field> |
||
| 4690 | <name>CC1OF</name> |
||
| 4691 | <description>Capture/Compare 1 overcapture |
||
| 4692 | flag</description> |
||
| 4693 | <bitOffset>9</bitOffset> |
||
| 4694 | <bitWidth>1</bitWidth> |
||
| 4695 | </field> |
||
| 4696 | <field> |
||
| 4697 | <name>BIF</name> |
||
| 4698 | <description>Break interrupt flag</description> |
||
| 4699 | <bitOffset>7</bitOffset> |
||
| 4700 | <bitWidth>1</bitWidth> |
||
| 4701 | </field> |
||
| 4702 | <field> |
||
| 4703 | <name>TIF</name> |
||
| 4704 | <description>Trigger interrupt flag</description> |
||
| 4705 | <bitOffset>6</bitOffset> |
||
| 4706 | <bitWidth>1</bitWidth> |
||
| 4707 | </field> |
||
| 4708 | <field> |
||
| 4709 | <name>COMIF</name> |
||
| 4710 | <description>COM interrupt flag</description> |
||
| 4711 | <bitOffset>5</bitOffset> |
||
| 4712 | <bitWidth>1</bitWidth> |
||
| 4713 | </field> |
||
| 4714 | <field> |
||
| 4715 | <name>CC4IF</name> |
||
| 4716 | <description>Capture/Compare 4 interrupt |
||
| 4717 | flag</description> |
||
| 4718 | <bitOffset>4</bitOffset> |
||
| 4719 | <bitWidth>1</bitWidth> |
||
| 4720 | </field> |
||
| 4721 | <field> |
||
| 4722 | <name>CC3IF</name> |
||
| 4723 | <description>Capture/Compare 3 interrupt |
||
| 4724 | flag</description> |
||
| 4725 | <bitOffset>3</bitOffset> |
||
| 4726 | <bitWidth>1</bitWidth> |
||
| 4727 | </field> |
||
| 4728 | <field> |
||
| 4729 | <name>CC2IF</name> |
||
| 4730 | <description>Capture/Compare 2 interrupt |
||
| 4731 | flag</description> |
||
| 4732 | <bitOffset>2</bitOffset> |
||
| 4733 | <bitWidth>1</bitWidth> |
||
| 4734 | </field> |
||
| 4735 | <field> |
||
| 4736 | <name>CC1IF</name> |
||
| 4737 | <description>Capture/compare 1 interrupt |
||
| 4738 | flag</description> |
||
| 4739 | <bitOffset>1</bitOffset> |
||
| 4740 | <bitWidth>1</bitWidth> |
||
| 4741 | </field> |
||
| 4742 | <field> |
||
| 4743 | <name>UIF</name> |
||
| 4744 | <description>Update interrupt flag</description> |
||
| 4745 | <bitOffset>0</bitOffset> |
||
| 4746 | <bitWidth>1</bitWidth> |
||
| 4747 | </field> |
||
| 4748 | </fields> |
||
| 4749 | </register> |
||
| 4750 | <register> |
||
| 4751 | <name>EGR</name> |
||
| 4752 | <displayName>EGR</displayName> |
||
| 4753 | <description>event generation register</description> |
||
| 4754 | <addressOffset>0x14</addressOffset> |
||
| 4755 | <size>0x20</size> |
||
| 4756 | <access>write-only</access> |
||
| 4757 | <resetValue>0x0000</resetValue> |
||
| 4758 | <fields> |
||
| 4759 | <field> |
||
| 4760 | <name>BG</name> |
||
| 4761 | <description>Break generation</description> |
||
| 4762 | <bitOffset>7</bitOffset> |
||
| 4763 | <bitWidth>1</bitWidth> |
||
| 4764 | </field> |
||
| 4765 | <field> |
||
| 4766 | <name>TG</name> |
||
| 4767 | <description>Trigger generation</description> |
||
| 4768 | <bitOffset>6</bitOffset> |
||
| 4769 | <bitWidth>1</bitWidth> |
||
| 4770 | </field> |
||
| 4771 | <field> |
||
| 4772 | <name>COMG</name> |
||
| 4773 | <description>Capture/Compare control update |
||
| 4774 | generation</description> |
||
| 4775 | <bitOffset>5</bitOffset> |
||
| 4776 | <bitWidth>1</bitWidth> |
||
| 4777 | </field> |
||
| 4778 | <field> |
||
| 4779 | <name>CC4G</name> |
||
| 4780 | <description>Capture/compare 4 |
||
| 4781 | generation</description> |
||
| 4782 | <bitOffset>4</bitOffset> |
||
| 4783 | <bitWidth>1</bitWidth> |
||
| 4784 | </field> |
||
| 4785 | <field> |
||
| 4786 | <name>CC3G</name> |
||
| 4787 | <description>Capture/compare 3 |
||
| 4788 | generation</description> |
||
| 4789 | <bitOffset>3</bitOffset> |
||
| 4790 | <bitWidth>1</bitWidth> |
||
| 4791 | </field> |
||
| 4792 | <field> |
||
| 4793 | <name>CC2G</name> |
||
| 4794 | <description>Capture/compare 2 |
||
| 4795 | generation</description> |
||
| 4796 | <bitOffset>2</bitOffset> |
||
| 4797 | <bitWidth>1</bitWidth> |
||
| 4798 | </field> |
||
| 4799 | <field> |
||
| 4800 | <name>CC1G</name> |
||
| 4801 | <description>Capture/compare 1 |
||
| 4802 | generation</description> |
||
| 4803 | <bitOffset>1</bitOffset> |
||
| 4804 | <bitWidth>1</bitWidth> |
||
| 4805 | </field> |
||
| 4806 | <field> |
||
| 4807 | <name>UG</name> |
||
| 4808 | <description>Update generation</description> |
||
| 4809 | <bitOffset>0</bitOffset> |
||
| 4810 | <bitWidth>1</bitWidth> |
||
| 4811 | </field> |
||
| 4812 | </fields> |
||
| 4813 | </register> |
||
| 4814 | <register> |
||
| 4815 | <name>CCMR1_Output</name> |
||
| 4816 | <displayName>CCMR1_Output</displayName> |
||
| 4817 | <description>capture/compare mode register (output |
||
| 4818 | mode)</description> |
||
| 4819 | <addressOffset>0x18</addressOffset> |
||
| 4820 | <size>0x20</size> |
||
| 4821 | <access>read-write</access> |
||
| 4822 | <resetValue>0x00000000</resetValue> |
||
| 4823 | <fields> |
||
| 4824 | <field> |
||
| 4825 | <name>OC2CE</name> |
||
| 4826 | <description>Output Compare 2 clear |
||
| 4827 | enable</description> |
||
| 4828 | <bitOffset>15</bitOffset> |
||
| 4829 | <bitWidth>1</bitWidth> |
||
| 4830 | </field> |
||
| 4831 | <field> |
||
| 4832 | <name>OC2M</name> |
||
| 4833 | <description>Output Compare 2 mode</description> |
||
| 4834 | <bitOffset>12</bitOffset> |
||
| 4835 | <bitWidth>3</bitWidth> |
||
| 4836 | </field> |
||
| 4837 | <field> |
||
| 4838 | <name>OC2PE</name> |
||
| 4839 | <description>Output Compare 2 preload |
||
| 4840 | enable</description> |
||
| 4841 | <bitOffset>11</bitOffset> |
||
| 4842 | <bitWidth>1</bitWidth> |
||
| 4843 | </field> |
||
| 4844 | <field> |
||
| 4845 | <name>OC2FE</name> |
||
| 4846 | <description>Output Compare 2 fast |
||
| 4847 | enable</description> |
||
| 4848 | <bitOffset>10</bitOffset> |
||
| 4849 | <bitWidth>1</bitWidth> |
||
| 4850 | </field> |
||
| 4851 | <field> |
||
| 4852 | <name>CC2S</name> |
||
| 4853 | <description>Capture/Compare 2 |
||
| 4854 | selection</description> |
||
| 4855 | <bitOffset>8</bitOffset> |
||
| 4856 | <bitWidth>2</bitWidth> |
||
| 4857 | </field> |
||
| 4858 | <field> |
||
| 4859 | <name>OC1CE</name> |
||
| 4860 | <description>Output Compare 1 clear |
||
| 4861 | enable</description> |
||
| 4862 | <bitOffset>7</bitOffset> |
||
| 4863 | <bitWidth>1</bitWidth> |
||
| 4864 | </field> |
||
| 4865 | <field> |
||
| 4866 | <name>OC1M</name> |
||
| 4867 | <description>Output Compare 1 mode</description> |
||
| 4868 | <bitOffset>4</bitOffset> |
||
| 4869 | <bitWidth>3</bitWidth> |
||
| 4870 | </field> |
||
| 4871 | <field> |
||
| 4872 | <name>OC1PE</name> |
||
| 4873 | <description>Output Compare 1 preload |
||
| 4874 | enable</description> |
||
| 4875 | <bitOffset>3</bitOffset> |
||
| 4876 | <bitWidth>1</bitWidth> |
||
| 4877 | </field> |
||
| 4878 | <field> |
||
| 4879 | <name>OC1FE</name> |
||
| 4880 | <description>Output Compare 1 fast |
||
| 4881 | enable</description> |
||
| 4882 | <bitOffset>2</bitOffset> |
||
| 4883 | <bitWidth>1</bitWidth> |
||
| 4884 | </field> |
||
| 4885 | <field> |
||
| 4886 | <name>CC1S</name> |
||
| 4887 | <description>Capture/Compare 1 |
||
| 4888 | selection</description> |
||
| 4889 | <bitOffset>0</bitOffset> |
||
| 4890 | <bitWidth>2</bitWidth> |
||
| 4891 | </field> |
||
| 4892 | </fields> |
||
| 4893 | </register> |
||
| 4894 | <register> |
||
| 4895 | <name>CCMR1_Input</name> |
||
| 4896 | <displayName>CCMR1_Input</displayName> |
||
| 4897 | <description>capture/compare mode register 1 (input |
||
| 4898 | mode)</description> |
||
| 4899 | <alternateRegister>CCMR1_Output</alternateRegister> |
||
| 4900 | <addressOffset>0x18</addressOffset> |
||
| 4901 | <size>0x20</size> |
||
| 4902 | <access>read-write</access> |
||
| 4903 | <resetValue>0x00000000</resetValue> |
||
| 4904 | <fields> |
||
| 4905 | <field> |
||
| 4906 | <name>IC2F</name> |
||
| 4907 | <description>Input capture 2 filter</description> |
||
| 4908 | <bitOffset>12</bitOffset> |
||
| 4909 | <bitWidth>4</bitWidth> |
||
| 4910 | </field> |
||
| 4911 | <field> |
||
| 4912 | <name>IC2PCS</name> |
||
| 4913 | <description>Input capture 2 prescaler</description> |
||
| 4914 | <bitOffset>10</bitOffset> |
||
| 4915 | <bitWidth>2</bitWidth> |
||
| 4916 | </field> |
||
| 4917 | <field> |
||
| 4918 | <name>CC2S</name> |
||
| 4919 | <description>Capture/Compare 2 |
||
| 4920 | selection</description> |
||
| 4921 | <bitOffset>8</bitOffset> |
||
| 4922 | <bitWidth>2</bitWidth> |
||
| 4923 | </field> |
||
| 4924 | <field> |
||
| 4925 | <name>IC1F</name> |
||
| 4926 | <description>Input capture 1 filter</description> |
||
| 4927 | <bitOffset>4</bitOffset> |
||
| 4928 | <bitWidth>4</bitWidth> |
||
| 4929 | </field> |
||
| 4930 | <field> |
||
| 4931 | <name>IC1PCS</name> |
||
| 4932 | <description>Input capture 1 prescaler</description> |
||
| 4933 | <bitOffset>2</bitOffset> |
||
| 4934 | <bitWidth>2</bitWidth> |
||
| 4935 | </field> |
||
| 4936 | <field> |
||
| 4937 | <name>CC1S</name> |
||
| 4938 | <description>Capture/Compare 1 |
||
| 4939 | selection</description> |
||
| 4940 | <bitOffset>0</bitOffset> |
||
| 4941 | <bitWidth>2</bitWidth> |
||
| 4942 | </field> |
||
| 4943 | </fields> |
||
| 4944 | </register> |
||
| 4945 | <register> |
||
| 4946 | <name>CCMR2_Output</name> |
||
| 4947 | <displayName>CCMR2_Output</displayName> |
||
| 4948 | <description>capture/compare mode register (output |
||
| 4949 | mode)</description> |
||
| 4950 | <addressOffset>0x1C</addressOffset> |
||
| 4951 | <size>0x20</size> |
||
| 4952 | <access>read-write</access> |
||
| 4953 | <resetValue>0x00000000</resetValue> |
||
| 4954 | <fields> |
||
| 4955 | <field> |
||
| 4956 | <name>OC4CE</name> |
||
| 4957 | <description>Output compare 4 clear |
||
| 4958 | enable</description> |
||
| 4959 | <bitOffset>15</bitOffset> |
||
| 4960 | <bitWidth>1</bitWidth> |
||
| 4961 | </field> |
||
| 4962 | <field> |
||
| 4963 | <name>OC4M</name> |
||
| 4964 | <description>Output compare 4 mode</description> |
||
| 4965 | <bitOffset>12</bitOffset> |
||
| 4966 | <bitWidth>3</bitWidth> |
||
| 4967 | </field> |
||
| 4968 | <field> |
||
| 4969 | <name>OC4PE</name> |
||
| 4970 | <description>Output compare 4 preload |
||
| 4971 | enable</description> |
||
| 4972 | <bitOffset>11</bitOffset> |
||
| 4973 | <bitWidth>1</bitWidth> |
||
| 4974 | </field> |
||
| 4975 | <field> |
||
| 4976 | <name>OC4FE</name> |
||
| 4977 | <description>Output compare 4 fast |
||
| 4978 | enable</description> |
||
| 4979 | <bitOffset>10</bitOffset> |
||
| 4980 | <bitWidth>1</bitWidth> |
||
| 4981 | </field> |
||
| 4982 | <field> |
||
| 4983 | <name>CC4S</name> |
||
| 4984 | <description>Capture/Compare 4 |
||
| 4985 | selection</description> |
||
| 4986 | <bitOffset>8</bitOffset> |
||
| 4987 | <bitWidth>2</bitWidth> |
||
| 4988 | </field> |
||
| 4989 | <field> |
||
| 4990 | <name>OC3CE</name> |
||
| 4991 | <description>Output compare 3 clear |
||
| 4992 | enable</description> |
||
| 4993 | <bitOffset>7</bitOffset> |
||
| 4994 | <bitWidth>1</bitWidth> |
||
| 4995 | </field> |
||
| 4996 | <field> |
||
| 4997 | <name>OC3M</name> |
||
| 4998 | <description>Output compare 3 mode</description> |
||
| 4999 | <bitOffset>4</bitOffset> |
||
| 5000 | <bitWidth>3</bitWidth> |
||
| 5001 | </field> |
||
| 5002 | <field> |
||
| 5003 | <name>OC3PE</name> |
||
| 5004 | <description>Output compare 3 preload |
||
| 5005 | enable</description> |
||
| 5006 | <bitOffset>3</bitOffset> |
||
| 5007 | <bitWidth>1</bitWidth> |
||
| 5008 | </field> |
||
| 5009 | <field> |
||
| 5010 | <name>OC3FE</name> |
||
| 5011 | <description>Output compare 3 fast |
||
| 5012 | enable</description> |
||
| 5013 | <bitOffset>2</bitOffset> |
||
| 5014 | <bitWidth>1</bitWidth> |
||
| 5015 | </field> |
||
| 5016 | <field> |
||
| 5017 | <name>CC3S</name> |
||
| 5018 | <description>Capture/Compare 3 |
||
| 5019 | selection</description> |
||
| 5020 | <bitOffset>0</bitOffset> |
||
| 5021 | <bitWidth>2</bitWidth> |
||
| 5022 | </field> |
||
| 5023 | </fields> |
||
| 5024 | </register> |
||
| 5025 | <register> |
||
| 5026 | <name>CCMR2_Input</name> |
||
| 5027 | <displayName>CCMR2_Input</displayName> |
||
| 5028 | <description>capture/compare mode register 2 (input |
||
| 5029 | mode)</description> |
||
| 5030 | <alternateRegister>CCMR2_Output</alternateRegister> |
||
| 5031 | <addressOffset>0x1C</addressOffset> |
||
| 5032 | <size>0x20</size> |
||
| 5033 | <access>read-write</access> |
||
| 5034 | <resetValue>0x00000000</resetValue> |
||
| 5035 | <fields> |
||
| 5036 | <field> |
||
| 5037 | <name>IC4F</name> |
||
| 5038 | <description>Input capture 4 filter</description> |
||
| 5039 | <bitOffset>12</bitOffset> |
||
| 5040 | <bitWidth>4</bitWidth> |
||
| 5041 | </field> |
||
| 5042 | <field> |
||
| 5043 | <name>IC4PSC</name> |
||
| 5044 | <description>Input capture 4 prescaler</description> |
||
| 5045 | <bitOffset>10</bitOffset> |
||
| 5046 | <bitWidth>2</bitWidth> |
||
| 5047 | </field> |
||
| 5048 | <field> |
||
| 5049 | <name>CC4S</name> |
||
| 5050 | <description>Capture/Compare 4 |
||
| 5051 | selection</description> |
||
| 5052 | <bitOffset>8</bitOffset> |
||
| 5053 | <bitWidth>2</bitWidth> |
||
| 5054 | </field> |
||
| 5055 | <field> |
||
| 5056 | <name>IC3F</name> |
||
| 5057 | <description>Input capture 3 filter</description> |
||
| 5058 | <bitOffset>4</bitOffset> |
||
| 5059 | <bitWidth>4</bitWidth> |
||
| 5060 | </field> |
||
| 5061 | <field> |
||
| 5062 | <name>IC3PSC</name> |
||
| 5063 | <description>Input capture 3 prescaler</description> |
||
| 5064 | <bitOffset>2</bitOffset> |
||
| 5065 | <bitWidth>2</bitWidth> |
||
| 5066 | </field> |
||
| 5067 | <field> |
||
| 5068 | <name>CC3S</name> |
||
| 5069 | <description>Capture/compare 3 |
||
| 5070 | selection</description> |
||
| 5071 | <bitOffset>0</bitOffset> |
||
| 5072 | <bitWidth>2</bitWidth> |
||
| 5073 | </field> |
||
| 5074 | </fields> |
||
| 5075 | </register> |
||
| 5076 | <register> |
||
| 5077 | <name>CCER</name> |
||
| 5078 | <displayName>CCER</displayName> |
||
| 5079 | <description>capture/compare enable |
||
| 5080 | register</description> |
||
| 5081 | <addressOffset>0x20</addressOffset> |
||
| 5082 | <size>0x20</size> |
||
| 5083 | <access>read-write</access> |
||
| 5084 | <resetValue>0x0000</resetValue> |
||
| 5085 | <fields> |
||
| 5086 | <field> |
||
| 5087 | <name>CC4P</name> |
||
| 5088 | <description>Capture/Compare 3 output |
||
| 5089 | Polarity</description> |
||
| 5090 | <bitOffset>13</bitOffset> |
||
| 5091 | <bitWidth>1</bitWidth> |
||
| 5092 | </field> |
||
| 5093 | <field> |
||
| 5094 | <name>CC4E</name> |
||
| 5095 | <description>Capture/Compare 4 output |
||
| 5096 | enable</description> |
||
| 5097 | <bitOffset>12</bitOffset> |
||
| 5098 | <bitWidth>1</bitWidth> |
||
| 5099 | </field> |
||
| 5100 | <field> |
||
| 5101 | <name>CC3NP</name> |
||
| 5102 | <description>Capture/Compare 3 output |
||
| 5103 | Polarity</description> |
||
| 5104 | <bitOffset>11</bitOffset> |
||
| 5105 | <bitWidth>1</bitWidth> |
||
| 5106 | </field> |
||
| 5107 | <field> |
||
| 5108 | <name>CC3NE</name> |
||
| 5109 | <description>Capture/Compare 3 complementary output |
||
| 5110 | enable</description> |
||
| 5111 | <bitOffset>10</bitOffset> |
||
| 5112 | <bitWidth>1</bitWidth> |
||
| 5113 | </field> |
||
| 5114 | <field> |
||
| 5115 | <name>CC3P</name> |
||
| 5116 | <description>Capture/Compare 3 output |
||
| 5117 | Polarity</description> |
||
| 5118 | <bitOffset>9</bitOffset> |
||
| 5119 | <bitWidth>1</bitWidth> |
||
| 5120 | </field> |
||
| 5121 | <field> |
||
| 5122 | <name>CC3E</name> |
||
| 5123 | <description>Capture/Compare 3 output |
||
| 5124 | enable</description> |
||
| 5125 | <bitOffset>8</bitOffset> |
||
| 5126 | <bitWidth>1</bitWidth> |
||
| 5127 | </field> |
||
| 5128 | <field> |
||
| 5129 | <name>CC2NP</name> |
||
| 5130 | <description>Capture/Compare 2 output |
||
| 5131 | Polarity</description> |
||
| 5132 | <bitOffset>7</bitOffset> |
||
| 5133 | <bitWidth>1</bitWidth> |
||
| 5134 | </field> |
||
| 5135 | <field> |
||
| 5136 | <name>CC2NE</name> |
||
| 5137 | <description>Capture/Compare 2 complementary output |
||
| 5138 | enable</description> |
||
| 5139 | <bitOffset>6</bitOffset> |
||
| 5140 | <bitWidth>1</bitWidth> |
||
| 5141 | </field> |
||
| 5142 | <field> |
||
| 5143 | <name>CC2P</name> |
||
| 5144 | <description>Capture/Compare 2 output |
||
| 5145 | Polarity</description> |
||
| 5146 | <bitOffset>5</bitOffset> |
||
| 5147 | <bitWidth>1</bitWidth> |
||
| 5148 | </field> |
||
| 5149 | <field> |
||
| 5150 | <name>CC2E</name> |
||
| 5151 | <description>Capture/Compare 2 output |
||
| 5152 | enable</description> |
||
| 5153 | <bitOffset>4</bitOffset> |
||
| 5154 | <bitWidth>1</bitWidth> |
||
| 5155 | </field> |
||
| 5156 | <field> |
||
| 5157 | <name>CC1NP</name> |
||
| 5158 | <description>Capture/Compare 1 output |
||
| 5159 | Polarity</description> |
||
| 5160 | <bitOffset>3</bitOffset> |
||
| 5161 | <bitWidth>1</bitWidth> |
||
| 5162 | </field> |
||
| 5163 | <field> |
||
| 5164 | <name>CC1NE</name> |
||
| 5165 | <description>Capture/Compare 1 complementary output |
||
| 5166 | enable</description> |
||
| 5167 | <bitOffset>2</bitOffset> |
||
| 5168 | <bitWidth>1</bitWidth> |
||
| 5169 | </field> |
||
| 5170 | <field> |
||
| 5171 | <name>CC1P</name> |
||
| 5172 | <description>Capture/Compare 1 output |
||
| 5173 | Polarity</description> |
||
| 5174 | <bitOffset>1</bitOffset> |
||
| 5175 | <bitWidth>1</bitWidth> |
||
| 5176 | </field> |
||
| 5177 | <field> |
||
| 5178 | <name>CC1E</name> |
||
| 5179 | <description>Capture/Compare 1 output |
||
| 5180 | enable</description> |
||
| 5181 | <bitOffset>0</bitOffset> |
||
| 5182 | <bitWidth>1</bitWidth> |
||
| 5183 | </field> |
||
| 5184 | </fields> |
||
| 5185 | </register> |
||
| 5186 | <register> |
||
| 5187 | <name>CNT</name> |
||
| 5188 | <displayName>CNT</displayName> |
||
| 5189 | <description>counter</description> |
||
| 5190 | <addressOffset>0x24</addressOffset> |
||
| 5191 | <size>0x20</size> |
||
| 5192 | <access>read-write</access> |
||
| 5193 | <resetValue>0x00000000</resetValue> |
||
| 5194 | <fields> |
||
| 5195 | <field> |
||
| 5196 | <name>CNT</name> |
||
| 5197 | <description>counter value</description> |
||
| 5198 | <bitOffset>0</bitOffset> |
||
| 5199 | <bitWidth>16</bitWidth> |
||
| 5200 | </field> |
||
| 5201 | </fields> |
||
| 5202 | </register> |
||
| 5203 | <register> |
||
| 5204 | <name>PSC</name> |
||
| 5205 | <displayName>PSC</displayName> |
||
| 5206 | <description>prescaler</description> |
||
| 5207 | <addressOffset>0x28</addressOffset> |
||
| 5208 | <size>0x20</size> |
||
| 5209 | <access>read-write</access> |
||
| 5210 | <resetValue>0x0000</resetValue> |
||
| 5211 | <fields> |
||
| 5212 | <field> |
||
| 5213 | <name>PSC</name> |
||
| 5214 | <description>Prescaler value</description> |
||
| 5215 | <bitOffset>0</bitOffset> |
||
| 5216 | <bitWidth>16</bitWidth> |
||
| 5217 | </field> |
||
| 5218 | </fields> |
||
| 5219 | </register> |
||
| 5220 | <register> |
||
| 5221 | <name>ARR</name> |
||
| 5222 | <displayName>ARR</displayName> |
||
| 5223 | <description>auto-reload register</description> |
||
| 5224 | <addressOffset>0x2C</addressOffset> |
||
| 5225 | <size>0x20</size> |
||
| 5226 | <access>read-write</access> |
||
| 5227 | <resetValue>0x00000000</resetValue> |
||
| 5228 | <fields> |
||
| 5229 | <field> |
||
| 5230 | <name>ARR</name> |
||
| 5231 | <description>Auto-reload value</description> |
||
| 5232 | <bitOffset>0</bitOffset> |
||
| 5233 | <bitWidth>16</bitWidth> |
||
| 5234 | </field> |
||
| 5235 | </fields> |
||
| 5236 | </register> |
||
| 5237 | <register> |
||
| 5238 | <name>RCR</name> |
||
| 5239 | <displayName>RCR</displayName> |
||
| 5240 | <description>repetition counter register</description> |
||
| 5241 | <addressOffset>0x30</addressOffset> |
||
| 5242 | <size>0x20</size> |
||
| 5243 | <access>read-write</access> |
||
| 5244 | <resetValue>0x0000</resetValue> |
||
| 5245 | <fields> |
||
| 5246 | <field> |
||
| 5247 | <name>REP</name> |
||
| 5248 | <description>Repetition counter value</description> |
||
| 5249 | <bitOffset>0</bitOffset> |
||
| 5250 | <bitWidth>8</bitWidth> |
||
| 5251 | </field> |
||
| 5252 | </fields> |
||
| 5253 | </register> |
||
| 5254 | <register> |
||
| 5255 | <name>CCR1</name> |
||
| 5256 | <displayName>CCR1</displayName> |
||
| 5257 | <description>capture/compare register 1</description> |
||
| 5258 | <addressOffset>0x34</addressOffset> |
||
| 5259 | <size>0x20</size> |
||
| 5260 | <access>read-write</access> |
||
| 5261 | <resetValue>0x00000000</resetValue> |
||
| 5262 | <fields> |
||
| 5263 | <field> |
||
| 5264 | <name>CCR1</name> |
||
| 5265 | <description>Capture/Compare 1 value</description> |
||
| 5266 | <bitOffset>0</bitOffset> |
||
| 5267 | <bitWidth>16</bitWidth> |
||
| 5268 | </field> |
||
| 5269 | </fields> |
||
| 5270 | </register> |
||
| 5271 | <register> |
||
| 5272 | <name>CCR2</name> |
||
| 5273 | <displayName>CCR2</displayName> |
||
| 5274 | <description>capture/compare register 2</description> |
||
| 5275 | <addressOffset>0x38</addressOffset> |
||
| 5276 | <size>0x20</size> |
||
| 5277 | <access>read-write</access> |
||
| 5278 | <resetValue>0x00000000</resetValue> |
||
| 5279 | <fields> |
||
| 5280 | <field> |
||
| 5281 | <name>CCR2</name> |
||
| 5282 | <description>Capture/Compare 2 value</description> |
||
| 5283 | <bitOffset>0</bitOffset> |
||
| 5284 | <bitWidth>16</bitWidth> |
||
| 5285 | </field> |
||
| 5286 | </fields> |
||
| 5287 | </register> |
||
| 5288 | <register> |
||
| 5289 | <name>CCR3</name> |
||
| 5290 | <displayName>CCR3</displayName> |
||
| 5291 | <description>capture/compare register 3</description> |
||
| 5292 | <addressOffset>0x3C</addressOffset> |
||
| 5293 | <size>0x20</size> |
||
| 5294 | <access>read-write</access> |
||
| 5295 | <resetValue>0x00000000</resetValue> |
||
| 5296 | <fields> |
||
| 5297 | <field> |
||
| 5298 | <name>CCR3</name> |
||
| 5299 | <description>Capture/Compare 3 value</description> |
||
| 5300 | <bitOffset>0</bitOffset> |
||
| 5301 | <bitWidth>16</bitWidth> |
||
| 5302 | </field> |
||
| 5303 | </fields> |
||
| 5304 | </register> |
||
| 5305 | <register> |
||
| 5306 | <name>CCR4</name> |
||
| 5307 | <displayName>CCR4</displayName> |
||
| 5308 | <description>capture/compare register 4</description> |
||
| 5309 | <addressOffset>0x40</addressOffset> |
||
| 5310 | <size>0x20</size> |
||
| 5311 | <access>read-write</access> |
||
| 5312 | <resetValue>0x00000000</resetValue> |
||
| 5313 | <fields> |
||
| 5314 | <field> |
||
| 5315 | <name>CCR4</name> |
||
| 5316 | <description>Capture/Compare 3 value</description> |
||
| 5317 | <bitOffset>0</bitOffset> |
||
| 5318 | <bitWidth>16</bitWidth> |
||
| 5319 | </field> |
||
| 5320 | </fields> |
||
| 5321 | </register> |
||
| 5322 | <register> |
||
| 5323 | <name>BDTR</name> |
||
| 5324 | <displayName>BDTR</displayName> |
||
| 5325 | <description>break and dead-time register</description> |
||
| 5326 | <addressOffset>0x44</addressOffset> |
||
| 5327 | <size>0x20</size> |
||
| 5328 | <access>read-write</access> |
||
| 5329 | <resetValue>0x0000</resetValue> |
||
| 5330 | <fields> |
||
| 5331 | <field> |
||
| 5332 | <name>MOE</name> |
||
| 5333 | <description>Main output enable</description> |
||
| 5334 | <bitOffset>15</bitOffset> |
||
| 5335 | <bitWidth>1</bitWidth> |
||
| 5336 | </field> |
||
| 5337 | <field> |
||
| 5338 | <name>AOE</name> |
||
| 5339 | <description>Automatic output enable</description> |
||
| 5340 | <bitOffset>14</bitOffset> |
||
| 5341 | <bitWidth>1</bitWidth> |
||
| 5342 | </field> |
||
| 5343 | <field> |
||
| 5344 | <name>BKP</name> |
||
| 5345 | <description>Break polarity</description> |
||
| 5346 | <bitOffset>13</bitOffset> |
||
| 5347 | <bitWidth>1</bitWidth> |
||
| 5348 | </field> |
||
| 5349 | <field> |
||
| 5350 | <name>BKE</name> |
||
| 5351 | <description>Break enable</description> |
||
| 5352 | <bitOffset>12</bitOffset> |
||
| 5353 | <bitWidth>1</bitWidth> |
||
| 5354 | </field> |
||
| 5355 | <field> |
||
| 5356 | <name>OSSR</name> |
||
| 5357 | <description>Off-state selection for Run |
||
| 5358 | mode</description> |
||
| 5359 | <bitOffset>11</bitOffset> |
||
| 5360 | <bitWidth>1</bitWidth> |
||
| 5361 | </field> |
||
| 5362 | <field> |
||
| 5363 | <name>OSSI</name> |
||
| 5364 | <description>Off-state selection for Idle |
||
| 5365 | mode</description> |
||
| 5366 | <bitOffset>10</bitOffset> |
||
| 5367 | <bitWidth>1</bitWidth> |
||
| 5368 | </field> |
||
| 5369 | <field> |
||
| 5370 | <name>LOCK</name> |
||
| 5371 | <description>Lock configuration</description> |
||
| 5372 | <bitOffset>8</bitOffset> |
||
| 5373 | <bitWidth>2</bitWidth> |
||
| 5374 | </field> |
||
| 5375 | <field> |
||
| 5376 | <name>DTG</name> |
||
| 5377 | <description>Dead-time generator setup</description> |
||
| 5378 | <bitOffset>0</bitOffset> |
||
| 5379 | <bitWidth>8</bitWidth> |
||
| 5380 | </field> |
||
| 5381 | </fields> |
||
| 5382 | </register> |
||
| 5383 | <register> |
||
| 5384 | <name>DCR</name> |
||
| 5385 | <displayName>DCR</displayName> |
||
| 5386 | <description>DMA control register</description> |
||
| 5387 | <addressOffset>0x48</addressOffset> |
||
| 5388 | <size>0x20</size> |
||
| 5389 | <access>read-write</access> |
||
| 5390 | <resetValue>0x0000</resetValue> |
||
| 5391 | <fields> |
||
| 5392 | <field> |
||
| 5393 | <name>DBL</name> |
||
| 5394 | <description>DMA burst length</description> |
||
| 5395 | <bitOffset>8</bitOffset> |
||
| 5396 | <bitWidth>5</bitWidth> |
||
| 5397 | </field> |
||
| 5398 | <field> |
||
| 5399 | <name>DBA</name> |
||
| 5400 | <description>DMA base address</description> |
||
| 5401 | <bitOffset>0</bitOffset> |
||
| 5402 | <bitWidth>5</bitWidth> |
||
| 5403 | </field> |
||
| 5404 | </fields> |
||
| 5405 | </register> |
||
| 5406 | <register> |
||
| 5407 | <name>DMAR</name> |
||
| 5408 | <displayName>DMAR</displayName> |
||
| 5409 | <description>DMA address for full transfer</description> |
||
| 5410 | <addressOffset>0x4C</addressOffset> |
||
| 5411 | <size>0x20</size> |
||
| 5412 | <access>read-write</access> |
||
| 5413 | <resetValue>0x0000</resetValue> |
||
| 5414 | <fields> |
||
| 5415 | <field> |
||
| 5416 | <name>DMAB</name> |
||
| 5417 | <description>DMA register for burst |
||
| 5418 | accesses</description> |
||
| 5419 | <bitOffset>0</bitOffset> |
||
| 5420 | <bitWidth>16</bitWidth> |
||
| 5421 | </field> |
||
| 5422 | </fields> |
||
| 5423 | </register> |
||
| 5424 | </registers> |
||
| 5425 | </peripheral> |
||
| 5426 | <peripheral> |
||
| 5427 | <name>TIM3</name> |
||
| 5428 | <description>General-purpose-timers</description> |
||
| 5429 | <groupName>TIM</groupName> |
||
| 5430 | <baseAddress>0x40000400</baseAddress> |
||
| 5431 | <addressBlock> |
||
| 5432 | <offset>0x0</offset> |
||
| 5433 | <size>0x400</size> |
||
| 5434 | <usage>registers</usage> |
||
| 5435 | </addressBlock> |
||
| 5436 | <interrupt> |
||
| 5437 | <name>TIM1_BRK_UP_TRG_COM</name> |
||
| 5438 | <description>TIM1 break, update, trigger and commutation |
||
| 5439 | interrupt</description> |
||
| 5440 | <value>13</value> |
||
| 5441 | </interrupt> |
||
| 5442 | <interrupt> |
||
| 5443 | <name>TIM1_CC</name> |
||
| 5444 | <description>TIM1 Capture Compare interrupt</description> |
||
| 5445 | <value>14</value> |
||
| 5446 | </interrupt> |
||
| 5447 | <registers> |
||
| 5448 | <register> |
||
| 5449 | <name>CR1</name> |
||
| 5450 | <displayName>CR1</displayName> |
||
| 5451 | <description>control register 1</description> |
||
| 5452 | <addressOffset>0x0</addressOffset> |
||
| 5453 | <size>0x20</size> |
||
| 5454 | <access>read-write</access> |
||
| 5455 | <resetValue>0x0000</resetValue> |
||
| 5456 | <fields> |
||
| 5457 | <field> |
||
| 5458 | <name>CKD</name> |
||
| 5459 | <description>Clock division</description> |
||
| 5460 | <bitOffset>8</bitOffset> |
||
| 5461 | <bitWidth>2</bitWidth> |
||
| 5462 | </field> |
||
| 5463 | <field> |
||
| 5464 | <name>ARPE</name> |
||
| 5465 | <description>Auto-reload preload enable</description> |
||
| 5466 | <bitOffset>7</bitOffset> |
||
| 5467 | <bitWidth>1</bitWidth> |
||
| 5468 | </field> |
||
| 5469 | <field> |
||
| 5470 | <name>CMS</name> |
||
| 5471 | <description>Center-aligned mode |
||
| 5472 | selection</description> |
||
| 5473 | <bitOffset>5</bitOffset> |
||
| 5474 | <bitWidth>2</bitWidth> |
||
| 5475 | </field> |
||
| 5476 | <field> |
||
| 5477 | <name>DIR</name> |
||
| 5478 | <description>Direction</description> |
||
| 5479 | <bitOffset>4</bitOffset> |
||
| 5480 | <bitWidth>1</bitWidth> |
||
| 5481 | </field> |
||
| 5482 | <field> |
||
| 5483 | <name>OPM</name> |
||
| 5484 | <description>One-pulse mode</description> |
||
| 5485 | <bitOffset>3</bitOffset> |
||
| 5486 | <bitWidth>1</bitWidth> |
||
| 5487 | </field> |
||
| 5488 | <field> |
||
| 5489 | <name>URS</name> |
||
| 5490 | <description>Update request source</description> |
||
| 5491 | <bitOffset>2</bitOffset> |
||
| 5492 | <bitWidth>1</bitWidth> |
||
| 5493 | </field> |
||
| 5494 | <field> |
||
| 5495 | <name>UDIS</name> |
||
| 5496 | <description>Update disable</description> |
||
| 5497 | <bitOffset>1</bitOffset> |
||
| 5498 | <bitWidth>1</bitWidth> |
||
| 5499 | </field> |
||
| 5500 | <field> |
||
| 5501 | <name>CEN</name> |
||
| 5502 | <description>Counter enable</description> |
||
| 5503 | <bitOffset>0</bitOffset> |
||
| 5504 | <bitWidth>1</bitWidth> |
||
| 5505 | </field> |
||
| 5506 | </fields> |
||
| 5507 | </register> |
||
| 5508 | <register> |
||
| 5509 | <name>CR2</name> |
||
| 5510 | <displayName>CR2</displayName> |
||
| 5511 | <description>control register 2</description> |
||
| 5512 | <addressOffset>0x4</addressOffset> |
||
| 5513 | <size>0x20</size> |
||
| 5514 | <access>read-write</access> |
||
| 5515 | <resetValue>0x0000</resetValue> |
||
| 5516 | <fields> |
||
| 5517 | <field> |
||
| 5518 | <name>TI1S</name> |
||
| 5519 | <description>TI1 selection</description> |
||
| 5520 | <bitOffset>7</bitOffset> |
||
| 5521 | <bitWidth>1</bitWidth> |
||
| 5522 | </field> |
||
| 5523 | <field> |
||
| 5524 | <name>MMS</name> |
||
| 5525 | <description>Master mode selection</description> |
||
| 5526 | <bitOffset>4</bitOffset> |
||
| 5527 | <bitWidth>3</bitWidth> |
||
| 5528 | </field> |
||
| 5529 | <field> |
||
| 5530 | <name>CCDS</name> |
||
| 5531 | <description>Capture/compare DMA |
||
| 5532 | selection</description> |
||
| 5533 | <bitOffset>3</bitOffset> |
||
| 5534 | <bitWidth>1</bitWidth> |
||
| 5535 | </field> |
||
| 5536 | </fields> |
||
| 5537 | </register> |
||
| 5538 | <register> |
||
| 5539 | <name>SMCR</name> |
||
| 5540 | <displayName>SMCR</displayName> |
||
| 5541 | <description>slave mode control register</description> |
||
| 5542 | <addressOffset>0x8</addressOffset> |
||
| 5543 | <size>0x20</size> |
||
| 5544 | <access>read-write</access> |
||
| 5545 | <resetValue>0x0000</resetValue> |
||
| 5546 | <fields> |
||
| 5547 | <field> |
||
| 5548 | <name>ETP</name> |
||
| 5549 | <description>External trigger polarity</description> |
||
| 5550 | <bitOffset>15</bitOffset> |
||
| 5551 | <bitWidth>1</bitWidth> |
||
| 5552 | </field> |
||
| 5553 | <field> |
||
| 5554 | <name>ECE</name> |
||
| 5555 | <description>External clock enable</description> |
||
| 5556 | <bitOffset>14</bitOffset> |
||
| 5557 | <bitWidth>1</bitWidth> |
||
| 5558 | </field> |
||
| 5559 | <field> |
||
| 5560 | <name>ETPS</name> |
||
| 5561 | <description>External trigger prescaler</description> |
||
| 5562 | <bitOffset>12</bitOffset> |
||
| 5563 | <bitWidth>2</bitWidth> |
||
| 5564 | </field> |
||
| 5565 | <field> |
||
| 5566 | <name>ETF</name> |
||
| 5567 | <description>External trigger filter</description> |
||
| 5568 | <bitOffset>8</bitOffset> |
||
| 5569 | <bitWidth>4</bitWidth> |
||
| 5570 | </field> |
||
| 5571 | <field> |
||
| 5572 | <name>MSM</name> |
||
| 5573 | <description>Master/Slave mode</description> |
||
| 5574 | <bitOffset>7</bitOffset> |
||
| 5575 | <bitWidth>1</bitWidth> |
||
| 5576 | </field> |
||
| 5577 | <field> |
||
| 5578 | <name>TS</name> |
||
| 5579 | <description>Trigger selection</description> |
||
| 5580 | <bitOffset>4</bitOffset> |
||
| 5581 | <bitWidth>3</bitWidth> |
||
| 5582 | </field> |
||
| 5583 | <field> |
||
| 5584 | <name>SMS</name> |
||
| 5585 | <description>Slave mode selection</description> |
||
| 5586 | <bitOffset>0</bitOffset> |
||
| 5587 | <bitWidth>3</bitWidth> |
||
| 5588 | </field> |
||
| 5589 | </fields> |
||
| 5590 | </register> |
||
| 5591 | <register> |
||
| 5592 | <name>DIER</name> |
||
| 5593 | <displayName>DIER</displayName> |
||
| 5594 | <description>DMA/Interrupt enable register</description> |
||
| 5595 | <addressOffset>0xC</addressOffset> |
||
| 5596 | <size>0x20</size> |
||
| 5597 | <access>read-write</access> |
||
| 5598 | <resetValue>0x0000</resetValue> |
||
| 5599 | <fields> |
||
| 5600 | <field> |
||
| 5601 | <name>TDE</name> |
||
| 5602 | <description>Trigger DMA request enable</description> |
||
| 5603 | <bitOffset>14</bitOffset> |
||
| 5604 | <bitWidth>1</bitWidth> |
||
| 5605 | </field> |
||
| 5606 | <field> |
||
| 5607 | <name>COMDE</name> |
||
| 5608 | <description>Reserved</description> |
||
| 5609 | <bitOffset>13</bitOffset> |
||
| 5610 | <bitWidth>1</bitWidth> |
||
| 5611 | </field> |
||
| 5612 | <field> |
||
| 5613 | <name>CC4DE</name> |
||
| 5614 | <description>Capture/Compare 4 DMA request |
||
| 5615 | enable</description> |
||
| 5616 | <bitOffset>12</bitOffset> |
||
| 5617 | <bitWidth>1</bitWidth> |
||
| 5618 | </field> |
||
| 5619 | <field> |
||
| 5620 | <name>CC3DE</name> |
||
| 5621 | <description>Capture/Compare 3 DMA request |
||
| 5622 | enable</description> |
||
| 5623 | <bitOffset>11</bitOffset> |
||
| 5624 | <bitWidth>1</bitWidth> |
||
| 5625 | </field> |
||
| 5626 | <field> |
||
| 5627 | <name>CC2DE</name> |
||
| 5628 | <description>Capture/Compare 2 DMA request |
||
| 5629 | enable</description> |
||
| 5630 | <bitOffset>10</bitOffset> |
||
| 5631 | <bitWidth>1</bitWidth> |
||
| 5632 | </field> |
||
| 5633 | <field> |
||
| 5634 | <name>CC1DE</name> |
||
| 5635 | <description>Capture/Compare 1 DMA request |
||
| 5636 | enable</description> |
||
| 5637 | <bitOffset>9</bitOffset> |
||
| 5638 | <bitWidth>1</bitWidth> |
||
| 5639 | </field> |
||
| 5640 | <field> |
||
| 5641 | <name>UDE</name> |
||
| 5642 | <description>Update DMA request enable</description> |
||
| 5643 | <bitOffset>8</bitOffset> |
||
| 5644 | <bitWidth>1</bitWidth> |
||
| 5645 | </field> |
||
| 5646 | <field> |
||
| 5647 | <name>TIE</name> |
||
| 5648 | <description>Trigger interrupt enable</description> |
||
| 5649 | <bitOffset>6</bitOffset> |
||
| 5650 | <bitWidth>1</bitWidth> |
||
| 5651 | </field> |
||
| 5652 | <field> |
||
| 5653 | <name>CC4IE</name> |
||
| 5654 | <description>Capture/Compare 4 interrupt |
||
| 5655 | enable</description> |
||
| 5656 | <bitOffset>4</bitOffset> |
||
| 5657 | <bitWidth>1</bitWidth> |
||
| 5658 | </field> |
||
| 5659 | <field> |
||
| 5660 | <name>CC3IE</name> |
||
| 5661 | <description>Capture/Compare 3 interrupt |
||
| 5662 | enable</description> |
||
| 5663 | <bitOffset>3</bitOffset> |
||
| 5664 | <bitWidth>1</bitWidth> |
||
| 5665 | </field> |
||
| 5666 | <field> |
||
| 5667 | <name>CC2IE</name> |
||
| 5668 | <description>Capture/Compare 2 interrupt |
||
| 5669 | enable</description> |
||
| 5670 | <bitOffset>2</bitOffset> |
||
| 5671 | <bitWidth>1</bitWidth> |
||
| 5672 | </field> |
||
| 5673 | <field> |
||
| 5674 | <name>CC1IE</name> |
||
| 5675 | <description>Capture/Compare 1 interrupt |
||
| 5676 | enable</description> |
||
| 5677 | <bitOffset>1</bitOffset> |
||
| 5678 | <bitWidth>1</bitWidth> |
||
| 5679 | </field> |
||
| 5680 | <field> |
||
| 5681 | <name>UIE</name> |
||
| 5682 | <description>Update interrupt enable</description> |
||
| 5683 | <bitOffset>0</bitOffset> |
||
| 5684 | <bitWidth>1</bitWidth> |
||
| 5685 | </field> |
||
| 5686 | </fields> |
||
| 5687 | </register> |
||
| 5688 | <register> |
||
| 5689 | <name>SR</name> |
||
| 5690 | <displayName>SR</displayName> |
||
| 5691 | <description>status register</description> |
||
| 5692 | <addressOffset>0x10</addressOffset> |
||
| 5693 | <size>0x20</size> |
||
| 5694 | <access>read-write</access> |
||
| 5695 | <resetValue>0x0000</resetValue> |
||
| 5696 | <fields> |
||
| 5697 | <field> |
||
| 5698 | <name>CC4OF</name> |
||
| 5699 | <description>Capture/Compare 4 overcapture |
||
| 5700 | flag</description> |
||
| 5701 | <bitOffset>12</bitOffset> |
||
| 5702 | <bitWidth>1</bitWidth> |
||
| 5703 | </field> |
||
| 5704 | <field> |
||
| 5705 | <name>CC3OF</name> |
||
| 5706 | <description>Capture/Compare 3 overcapture |
||
| 5707 | flag</description> |
||
| 5708 | <bitOffset>11</bitOffset> |
||
| 5709 | <bitWidth>1</bitWidth> |
||
| 5710 | </field> |
||
| 5711 | <field> |
||
| 5712 | <name>CC2OF</name> |
||
| 5713 | <description>Capture/compare 2 overcapture |
||
| 5714 | flag</description> |
||
| 5715 | <bitOffset>10</bitOffset> |
||
| 5716 | <bitWidth>1</bitWidth> |
||
| 5717 | </field> |
||
| 5718 | <field> |
||
| 5719 | <name>CC1OF</name> |
||
| 5720 | <description>Capture/Compare 1 overcapture |
||
| 5721 | flag</description> |
||
| 5722 | <bitOffset>9</bitOffset> |
||
| 5723 | <bitWidth>1</bitWidth> |
||
| 5724 | </field> |
||
| 5725 | <field> |
||
| 5726 | <name>TIF</name> |
||
| 5727 | <description>Trigger interrupt flag</description> |
||
| 5728 | <bitOffset>6</bitOffset> |
||
| 5729 | <bitWidth>1</bitWidth> |
||
| 5730 | </field> |
||
| 5731 | <field> |
||
| 5732 | <name>CC4IF</name> |
||
| 5733 | <description>Capture/Compare 4 interrupt |
||
| 5734 | flag</description> |
||
| 5735 | <bitOffset>4</bitOffset> |
||
| 5736 | <bitWidth>1</bitWidth> |
||
| 5737 | </field> |
||
| 5738 | <field> |
||
| 5739 | <name>CC3IF</name> |
||
| 5740 | <description>Capture/Compare 3 interrupt |
||
| 5741 | flag</description> |
||
| 5742 | <bitOffset>3</bitOffset> |
||
| 5743 | <bitWidth>1</bitWidth> |
||
| 5744 | </field> |
||
| 5745 | <field> |
||
| 5746 | <name>CC2IF</name> |
||
| 5747 | <description>Capture/Compare 2 interrupt |
||
| 5748 | flag</description> |
||
| 5749 | <bitOffset>2</bitOffset> |
||
| 5750 | <bitWidth>1</bitWidth> |
||
| 5751 | </field> |
||
| 5752 | <field> |
||
| 5753 | <name>CC1IF</name> |
||
| 5754 | <description>Capture/compare 1 interrupt |
||
| 5755 | flag</description> |
||
| 5756 | <bitOffset>1</bitOffset> |
||
| 5757 | <bitWidth>1</bitWidth> |
||
| 5758 | </field> |
||
| 5759 | <field> |
||
| 5760 | <name>UIF</name> |
||
| 5761 | <description>Update interrupt flag</description> |
||
| 5762 | <bitOffset>0</bitOffset> |
||
| 5763 | <bitWidth>1</bitWidth> |
||
| 5764 | </field> |
||
| 5765 | </fields> |
||
| 5766 | </register> |
||
| 5767 | <register> |
||
| 5768 | <name>EGR</name> |
||
| 5769 | <displayName>EGR</displayName> |
||
| 5770 | <description>event generation register</description> |
||
| 5771 | <addressOffset>0x14</addressOffset> |
||
| 5772 | <size>0x20</size> |
||
| 5773 | <access>write-only</access> |
||
| 5774 | <resetValue>0x0000</resetValue> |
||
| 5775 | <fields> |
||
| 5776 | <field> |
||
| 5777 | <name>TG</name> |
||
| 5778 | <description>Trigger generation</description> |
||
| 5779 | <bitOffset>6</bitOffset> |
||
| 5780 | <bitWidth>1</bitWidth> |
||
| 5781 | </field> |
||
| 5782 | <field> |
||
| 5783 | <name>CC4G</name> |
||
| 5784 | <description>Capture/compare 4 |
||
| 5785 | generation</description> |
||
| 5786 | <bitOffset>4</bitOffset> |
||
| 5787 | <bitWidth>1</bitWidth> |
||
| 5788 | </field> |
||
| 5789 | <field> |
||
| 5790 | <name>CC3G</name> |
||
| 5791 | <description>Capture/compare 3 |
||
| 5792 | generation</description> |
||
| 5793 | <bitOffset>3</bitOffset> |
||
| 5794 | <bitWidth>1</bitWidth> |
||
| 5795 | </field> |
||
| 5796 | <field> |
||
| 5797 | <name>CC2G</name> |
||
| 5798 | <description>Capture/compare 2 |
||
| 5799 | generation</description> |
||
| 5800 | <bitOffset>2</bitOffset> |
||
| 5801 | <bitWidth>1</bitWidth> |
||
| 5802 | </field> |
||
| 5803 | <field> |
||
| 5804 | <name>CC1G</name> |
||
| 5805 | <description>Capture/compare 1 |
||
| 5806 | generation</description> |
||
| 5807 | <bitOffset>1</bitOffset> |
||
| 5808 | <bitWidth>1</bitWidth> |
||
| 5809 | </field> |
||
| 5810 | <field> |
||
| 5811 | <name>UG</name> |
||
| 5812 | <description>Update generation</description> |
||
| 5813 | <bitOffset>0</bitOffset> |
||
| 5814 | <bitWidth>1</bitWidth> |
||
| 5815 | </field> |
||
| 5816 | </fields> |
||
| 5817 | </register> |
||
| 5818 | <register> |
||
| 5819 | <name>CCMR1_Output</name> |
||
| 5820 | <displayName>CCMR1_Output</displayName> |
||
| 5821 | <description>capture/compare mode register 1 (output |
||
| 5822 | mode)</description> |
||
| 5823 | <addressOffset>0x18</addressOffset> |
||
| 5824 | <size>0x20</size> |
||
| 5825 | <access>read-write</access> |
||
| 5826 | <resetValue>0x00000000</resetValue> |
||
| 5827 | <fields> |
||
| 5828 | <field> |
||
| 5829 | <name>OC2CE</name> |
||
| 5830 | <description>Output compare 2 clear |
||
| 5831 | enable</description> |
||
| 5832 | <bitOffset>15</bitOffset> |
||
| 5833 | <bitWidth>1</bitWidth> |
||
| 5834 | </field> |
||
| 5835 | <field> |
||
| 5836 | <name>OC2M</name> |
||
| 5837 | <description>Output compare 2 mode</description> |
||
| 5838 | <bitOffset>12</bitOffset> |
||
| 5839 | <bitWidth>3</bitWidth> |
||
| 5840 | </field> |
||
| 5841 | <field> |
||
| 5842 | <name>OC2PE</name> |
||
| 5843 | <description>Output compare 2 preload |
||
| 5844 | enable</description> |
||
| 5845 | <bitOffset>11</bitOffset> |
||
| 5846 | <bitWidth>1</bitWidth> |
||
| 5847 | </field> |
||
| 5848 | <field> |
||
| 5849 | <name>OC2FE</name> |
||
| 5850 | <description>Output compare 2 fast |
||
| 5851 | enable</description> |
||
| 5852 | <bitOffset>10</bitOffset> |
||
| 5853 | <bitWidth>1</bitWidth> |
||
| 5854 | </field> |
||
| 5855 | <field> |
||
| 5856 | <name>CC2S</name> |
||
| 5857 | <description>Capture/Compare 2 |
||
| 5858 | selection</description> |
||
| 5859 | <bitOffset>8</bitOffset> |
||
| 5860 | <bitWidth>2</bitWidth> |
||
| 5861 | </field> |
||
| 5862 | <field> |
||
| 5863 | <name>OC1CE</name> |
||
| 5864 | <description>Output compare 1 clear |
||
| 5865 | enable</description> |
||
| 5866 | <bitOffset>7</bitOffset> |
||
| 5867 | <bitWidth>1</bitWidth> |
||
| 5868 | </field> |
||
| 5869 | <field> |
||
| 5870 | <name>OC1M</name> |
||
| 5871 | <description>Output compare 1 mode</description> |
||
| 5872 | <bitOffset>4</bitOffset> |
||
| 5873 | <bitWidth>3</bitWidth> |
||
| 5874 | </field> |
||
| 5875 | <field> |
||
| 5876 | <name>OC1PE</name> |
||
| 5877 | <description>Output compare 1 preload |
||
| 5878 | enable</description> |
||
| 5879 | <bitOffset>3</bitOffset> |
||
| 5880 | <bitWidth>1</bitWidth> |
||
| 5881 | </field> |
||
| 5882 | <field> |
||
| 5883 | <name>OC1FE</name> |
||
| 5884 | <description>Output compare 1 fast |
||
| 5885 | enable</description> |
||
| 5886 | <bitOffset>2</bitOffset> |
||
| 5887 | <bitWidth>1</bitWidth> |
||
| 5888 | </field> |
||
| 5889 | <field> |
||
| 5890 | <name>CC1S</name> |
||
| 5891 | <description>Capture/Compare 1 |
||
| 5892 | selection</description> |
||
| 5893 | <bitOffset>0</bitOffset> |
||
| 5894 | <bitWidth>2</bitWidth> |
||
| 5895 | </field> |
||
| 5896 | </fields> |
||
| 5897 | </register> |
||
| 5898 | <register> |
||
| 5899 | <name>CCMR1_Input</name> |
||
| 5900 | <displayName>CCMR1_Input</displayName> |
||
| 5901 | <description>capture/compare mode register 1 (input |
||
| 5902 | mode)</description> |
||
| 5903 | <alternateRegister>CCMR1_Output</alternateRegister> |
||
| 5904 | <addressOffset>0x18</addressOffset> |
||
| 5905 | <size>0x20</size> |
||
| 5906 | <access>read-write</access> |
||
| 5907 | <resetValue>0x00000000</resetValue> |
||
| 5908 | <fields> |
||
| 5909 | <field> |
||
| 5910 | <name>IC2F</name> |
||
| 5911 | <description>Input capture 2 filter</description> |
||
| 5912 | <bitOffset>12</bitOffset> |
||
| 5913 | <bitWidth>4</bitWidth> |
||
| 5914 | </field> |
||
| 5915 | <field> |
||
| 5916 | <name>IC2PSC</name> |
||
| 5917 | <description>Input capture 2 prescaler</description> |
||
| 5918 | <bitOffset>10</bitOffset> |
||
| 5919 | <bitWidth>2</bitWidth> |
||
| 5920 | </field> |
||
| 5921 | <field> |
||
| 5922 | <name>CC2S</name> |
||
| 5923 | <description>Capture/compare 2 |
||
| 5924 | selection</description> |
||
| 5925 | <bitOffset>8</bitOffset> |
||
| 5926 | <bitWidth>2</bitWidth> |
||
| 5927 | </field> |
||
| 5928 | <field> |
||
| 5929 | <name>IC1F</name> |
||
| 5930 | <description>Input capture 1 filter</description> |
||
| 5931 | <bitOffset>4</bitOffset> |
||
| 5932 | <bitWidth>4</bitWidth> |
||
| 5933 | </field> |
||
| 5934 | <field> |
||
| 5935 | <name>IC1PSC</name> |
||
| 5936 | <description>Input capture 1 prescaler</description> |
||
| 5937 | <bitOffset>2</bitOffset> |
||
| 5938 | <bitWidth>2</bitWidth> |
||
| 5939 | </field> |
||
| 5940 | <field> |
||
| 5941 | <name>CC1S</name> |
||
| 5942 | <description>Capture/Compare 1 |
||
| 5943 | selection</description> |
||
| 5944 | <bitOffset>0</bitOffset> |
||
| 5945 | <bitWidth>2</bitWidth> |
||
| 5946 | </field> |
||
| 5947 | </fields> |
||
| 5948 | </register> |
||
| 5949 | <register> |
||
| 5950 | <name>CCMR2_Output</name> |
||
| 5951 | <displayName>CCMR2_Output</displayName> |
||
| 5952 | <description>capture/compare mode register 2 (output |
||
| 5953 | mode)</description> |
||
| 5954 | <addressOffset>0x1C</addressOffset> |
||
| 5955 | <size>0x20</size> |
||
| 5956 | <access>read-write</access> |
||
| 5957 | <resetValue>0x00000000</resetValue> |
||
| 5958 | <fields> |
||
| 5959 | <field> |
||
| 5960 | <name>OC4CE</name> |
||
| 5961 | <description>Output compare 4 clear |
||
| 5962 | enable</description> |
||
| 5963 | <bitOffset>15</bitOffset> |
||
| 5964 | <bitWidth>1</bitWidth> |
||
| 5965 | </field> |
||
| 5966 | <field> |
||
| 5967 | <name>OC4M</name> |
||
| 5968 | <description>Output compare 4 mode</description> |
||
| 5969 | <bitOffset>12</bitOffset> |
||
| 5970 | <bitWidth>3</bitWidth> |
||
| 5971 | </field> |
||
| 5972 | <field> |
||
| 5973 | <name>OC4PE</name> |
||
| 5974 | <description>Output compare 4 preload |
||
| 5975 | enable</description> |
||
| 5976 | <bitOffset>11</bitOffset> |
||
| 5977 | <bitWidth>1</bitWidth> |
||
| 5978 | </field> |
||
| 5979 | <field> |
||
| 5980 | <name>OC4FE</name> |
||
| 5981 | <description>Output compare 4 fast |
||
| 5982 | enable</description> |
||
| 5983 | <bitOffset>10</bitOffset> |
||
| 5984 | <bitWidth>1</bitWidth> |
||
| 5985 | </field> |
||
| 5986 | <field> |
||
| 5987 | <name>CC4S</name> |
||
| 5988 | <description>Capture/Compare 4 |
||
| 5989 | selection</description> |
||
| 5990 | <bitOffset>8</bitOffset> |
||
| 5991 | <bitWidth>2</bitWidth> |
||
| 5992 | </field> |
||
| 5993 | <field> |
||
| 5994 | <name>OC3CE</name> |
||
| 5995 | <description>Output compare 3 clear |
||
| 5996 | enable</description> |
||
| 5997 | <bitOffset>7</bitOffset> |
||
| 5998 | <bitWidth>1</bitWidth> |
||
| 5999 | </field> |
||
| 6000 | <field> |
||
| 6001 | <name>OC3M</name> |
||
| 6002 | <description>Output compare 3 mode</description> |
||
| 6003 | <bitOffset>4</bitOffset> |
||
| 6004 | <bitWidth>3</bitWidth> |
||
| 6005 | </field> |
||
| 6006 | <field> |
||
| 6007 | <name>OC3PE</name> |
||
| 6008 | <description>Output compare 3 preload |
||
| 6009 | enable</description> |
||
| 6010 | <bitOffset>3</bitOffset> |
||
| 6011 | <bitWidth>1</bitWidth> |
||
| 6012 | </field> |
||
| 6013 | <field> |
||
| 6014 | <name>OC3FE</name> |
||
| 6015 | <description>Output compare 3 fast |
||
| 6016 | enable</description> |
||
| 6017 | <bitOffset>2</bitOffset> |
||
| 6018 | <bitWidth>1</bitWidth> |
||
| 6019 | </field> |
||
| 6020 | <field> |
||
| 6021 | <name>CC3S</name> |
||
| 6022 | <description>Capture/Compare 3 |
||
| 6023 | selection</description> |
||
| 6024 | <bitOffset>0</bitOffset> |
||
| 6025 | <bitWidth>2</bitWidth> |
||
| 6026 | </field> |
||
| 6027 | </fields> |
||
| 6028 | </register> |
||
| 6029 | <register> |
||
| 6030 | <name>CCMR2_Input</name> |
||
| 6031 | <displayName>CCMR2_Input</displayName> |
||
| 6032 | <description>capture/compare mode register 2 (input |
||
| 6033 | mode)</description> |
||
| 6034 | <alternateRegister>CCMR2_Output</alternateRegister> |
||
| 6035 | <addressOffset>0x1C</addressOffset> |
||
| 6036 | <size>0x20</size> |
||
| 6037 | <access>read-write</access> |
||
| 6038 | <resetValue>0x00000000</resetValue> |
||
| 6039 | <fields> |
||
| 6040 | <field> |
||
| 6041 | <name>IC4F</name> |
||
| 6042 | <description>Input capture 4 filter</description> |
||
| 6043 | <bitOffset>12</bitOffset> |
||
| 6044 | <bitWidth>4</bitWidth> |
||
| 6045 | </field> |
||
| 6046 | <field> |
||
| 6047 | <name>IC4PSC</name> |
||
| 6048 | <description>Input capture 4 prescaler</description> |
||
| 6049 | <bitOffset>10</bitOffset> |
||
| 6050 | <bitWidth>2</bitWidth> |
||
| 6051 | </field> |
||
| 6052 | <field> |
||
| 6053 | <name>CC4S</name> |
||
| 6054 | <description>Capture/Compare 4 |
||
| 6055 | selection</description> |
||
| 6056 | <bitOffset>8</bitOffset> |
||
| 6057 | <bitWidth>2</bitWidth> |
||
| 6058 | </field> |
||
| 6059 | <field> |
||
| 6060 | <name>IC3F</name> |
||
| 6061 | <description>Input capture 3 filter</description> |
||
| 6062 | <bitOffset>4</bitOffset> |
||
| 6063 | <bitWidth>4</bitWidth> |
||
| 6064 | </field> |
||
| 6065 | <field> |
||
| 6066 | <name>IC3PSC</name> |
||
| 6067 | <description>Input capture 3 prescaler</description> |
||
| 6068 | <bitOffset>2</bitOffset> |
||
| 6069 | <bitWidth>2</bitWidth> |
||
| 6070 | </field> |
||
| 6071 | <field> |
||
| 6072 | <name>CC3S</name> |
||
| 6073 | <description>Capture/Compare 3 |
||
| 6074 | selection</description> |
||
| 6075 | <bitOffset>0</bitOffset> |
||
| 6076 | <bitWidth>2</bitWidth> |
||
| 6077 | </field> |
||
| 6078 | </fields> |
||
| 6079 | </register> |
||
| 6080 | <register> |
||
| 6081 | <name>CCER</name> |
||
| 6082 | <displayName>CCER</displayName> |
||
| 6083 | <description>capture/compare enable |
||
| 6084 | register</description> |
||
| 6085 | <addressOffset>0x20</addressOffset> |
||
| 6086 | <size>0x20</size> |
||
| 6087 | <access>read-write</access> |
||
| 6088 | <resetValue>0x0000</resetValue> |
||
| 6089 | <fields> |
||
| 6090 | <field> |
||
| 6091 | <name>CC4NP</name> |
||
| 6092 | <description>Capture/Compare 4 output |
||
| 6093 | Polarity</description> |
||
| 6094 | <bitOffset>15</bitOffset> |
||
| 6095 | <bitWidth>1</bitWidth> |
||
| 6096 | </field> |
||
| 6097 | <field> |
||
| 6098 | <name>CC4P</name> |
||
| 6099 | <description>Capture/Compare 3 output |
||
| 6100 | Polarity</description> |
||
| 6101 | <bitOffset>13</bitOffset> |
||
| 6102 | <bitWidth>1</bitWidth> |
||
| 6103 | </field> |
||
| 6104 | <field> |
||
| 6105 | <name>CC4E</name> |
||
| 6106 | <description>Capture/Compare 4 output |
||
| 6107 | enable</description> |
||
| 6108 | <bitOffset>12</bitOffset> |
||
| 6109 | <bitWidth>1</bitWidth> |
||
| 6110 | </field> |
||
| 6111 | <field> |
||
| 6112 | <name>CC3NP</name> |
||
| 6113 | <description>Capture/Compare 3 output |
||
| 6114 | Polarity</description> |
||
| 6115 | <bitOffset>11</bitOffset> |
||
| 6116 | <bitWidth>1</bitWidth> |
||
| 6117 | </field> |
||
| 6118 | <field> |
||
| 6119 | <name>CC3P</name> |
||
| 6120 | <description>Capture/Compare 3 output |
||
| 6121 | Polarity</description> |
||
| 6122 | <bitOffset>9</bitOffset> |
||
| 6123 | <bitWidth>1</bitWidth> |
||
| 6124 | </field> |
||
| 6125 | <field> |
||
| 6126 | <name>CC3E</name> |
||
| 6127 | <description>Capture/Compare 3 output |
||
| 6128 | enable</description> |
||
| 6129 | <bitOffset>8</bitOffset> |
||
| 6130 | <bitWidth>1</bitWidth> |
||
| 6131 | </field> |
||
| 6132 | <field> |
||
| 6133 | <name>CC2NP</name> |
||
| 6134 | <description>Capture/Compare 2 output |
||
| 6135 | Polarity</description> |
||
| 6136 | <bitOffset>7</bitOffset> |
||
| 6137 | <bitWidth>1</bitWidth> |
||
| 6138 | </field> |
||
| 6139 | <field> |
||
| 6140 | <name>CC2P</name> |
||
| 6141 | <description>Capture/Compare 2 output |
||
| 6142 | Polarity</description> |
||
| 6143 | <bitOffset>5</bitOffset> |
||
| 6144 | <bitWidth>1</bitWidth> |
||
| 6145 | </field> |
||
| 6146 | <field> |
||
| 6147 | <name>CC2E</name> |
||
| 6148 | <description>Capture/Compare 2 output |
||
| 6149 | enable</description> |
||
| 6150 | <bitOffset>4</bitOffset> |
||
| 6151 | <bitWidth>1</bitWidth> |
||
| 6152 | </field> |
||
| 6153 | <field> |
||
| 6154 | <name>CC1NP</name> |
||
| 6155 | <description>Capture/Compare 1 output |
||
| 6156 | Polarity</description> |
||
| 6157 | <bitOffset>3</bitOffset> |
||
| 6158 | <bitWidth>1</bitWidth> |
||
| 6159 | </field> |
||
| 6160 | <field> |
||
| 6161 | <name>CC1P</name> |
||
| 6162 | <description>Capture/Compare 1 output |
||
| 6163 | Polarity</description> |
||
| 6164 | <bitOffset>1</bitOffset> |
||
| 6165 | <bitWidth>1</bitWidth> |
||
| 6166 | </field> |
||
| 6167 | <field> |
||
| 6168 | <name>CC1E</name> |
||
| 6169 | <description>Capture/Compare 1 output |
||
| 6170 | enable</description> |
||
| 6171 | <bitOffset>0</bitOffset> |
||
| 6172 | <bitWidth>1</bitWidth> |
||
| 6173 | </field> |
||
| 6174 | </fields> |
||
| 6175 | </register> |
||
| 6176 | <register> |
||
| 6177 | <name>CNT</name> |
||
| 6178 | <displayName>CNT</displayName> |
||
| 6179 | <description>counter</description> |
||
| 6180 | <addressOffset>0x24</addressOffset> |
||
| 6181 | <size>0x20</size> |
||
| 6182 | <access>read-write</access> |
||
| 6183 | <resetValue>0x00000000</resetValue> |
||
| 6184 | <fields> |
||
| 6185 | <field> |
||
| 6186 | <name>CNT_H</name> |
||
| 6187 | <description>High counter value (TIM2 |
||
| 6188 | only)</description> |
||
| 6189 | <bitOffset>16</bitOffset> |
||
| 6190 | <bitWidth>16</bitWidth> |
||
| 6191 | </field> |
||
| 6192 | <field> |
||
| 6193 | <name>CNT_L</name> |
||
| 6194 | <description>Low counter value</description> |
||
| 6195 | <bitOffset>0</bitOffset> |
||
| 6196 | <bitWidth>16</bitWidth> |
||
| 6197 | </field> |
||
| 6198 | </fields> |
||
| 6199 | </register> |
||
| 6200 | <register> |
||
| 6201 | <name>PSC</name> |
||
| 6202 | <displayName>PSC</displayName> |
||
| 6203 | <description>prescaler</description> |
||
| 6204 | <addressOffset>0x28</addressOffset> |
||
| 6205 | <size>0x20</size> |
||
| 6206 | <access>read-write</access> |
||
| 6207 | <resetValue>0x0000</resetValue> |
||
| 6208 | <fields> |
||
| 6209 | <field> |
||
| 6210 | <name>PSC</name> |
||
| 6211 | <description>Prescaler value</description> |
||
| 6212 | <bitOffset>0</bitOffset> |
||
| 6213 | <bitWidth>16</bitWidth> |
||
| 6214 | </field> |
||
| 6215 | </fields> |
||
| 6216 | </register> |
||
| 6217 | <register> |
||
| 6218 | <name>ARR</name> |
||
| 6219 | <displayName>ARR</displayName> |
||
| 6220 | <description>auto-reload register</description> |
||
| 6221 | <addressOffset>0x2C</addressOffset> |
||
| 6222 | <size>0x20</size> |
||
| 6223 | <access>read-write</access> |
||
| 6224 | <resetValue>0x00000000</resetValue> |
||
| 6225 | <fields> |
||
| 6226 | <field> |
||
| 6227 | <name>ARR_H</name> |
||
| 6228 | <description>High Auto-reload value (TIM2 |
||
| 6229 | only)</description> |
||
| 6230 | <bitOffset>16</bitOffset> |
||
| 6231 | <bitWidth>16</bitWidth> |
||
| 6232 | </field> |
||
| 6233 | <field> |
||
| 6234 | <name>ARR_L</name> |
||
| 6235 | <description>Low Auto-reload value</description> |
||
| 6236 | <bitOffset>0</bitOffset> |
||
| 6237 | <bitWidth>16</bitWidth> |
||
| 6238 | </field> |
||
| 6239 | </fields> |
||
| 6240 | </register> |
||
| 6241 | <register> |
||
| 6242 | <name>CCR1</name> |
||
| 6243 | <displayName>CCR1</displayName> |
||
| 6244 | <description>capture/compare register 1</description> |
||
| 6245 | <addressOffset>0x34</addressOffset> |
||
| 6246 | <size>0x20</size> |
||
| 6247 | <access>read-write</access> |
||
| 6248 | <resetValue>0x00000000</resetValue> |
||
| 6249 | <fields> |
||
| 6250 | <field> |
||
| 6251 | <name>CCR1_H</name> |
||
| 6252 | <description>High Capture/Compare 1 value (TIM2 |
||
| 6253 | only)</description> |
||
| 6254 | <bitOffset>16</bitOffset> |
||
| 6255 | <bitWidth>16</bitWidth> |
||
| 6256 | </field> |
||
| 6257 | <field> |
||
| 6258 | <name>CCR1_L</name> |
||
| 6259 | <description>Low Capture/Compare 1 |
||
| 6260 | value</description> |
||
| 6261 | <bitOffset>0</bitOffset> |
||
| 6262 | <bitWidth>16</bitWidth> |
||
| 6263 | </field> |
||
| 6264 | </fields> |
||
| 6265 | </register> |
||
| 6266 | <register> |
||
| 6267 | <name>CCR2</name> |
||
| 6268 | <displayName>CCR2</displayName> |
||
| 6269 | <description>capture/compare register 2</description> |
||
| 6270 | <addressOffset>0x38</addressOffset> |
||
| 6271 | <size>0x20</size> |
||
| 6272 | <access>read-write</access> |
||
| 6273 | <resetValue>0x00000000</resetValue> |
||
| 6274 | <fields> |
||
| 6275 | <field> |
||
| 6276 | <name>CCR2_H</name> |
||
| 6277 | <description>High Capture/Compare 2 value (TIM2 |
||
| 6278 | only)</description> |
||
| 6279 | <bitOffset>16</bitOffset> |
||
| 6280 | <bitWidth>16</bitWidth> |
||
| 6281 | </field> |
||
| 6282 | <field> |
||
| 6283 | <name>CCR2_L</name> |
||
| 6284 | <description>Low Capture/Compare 2 |
||
| 6285 | value</description> |
||
| 6286 | <bitOffset>0</bitOffset> |
||
| 6287 | <bitWidth>16</bitWidth> |
||
| 6288 | </field> |
||
| 6289 | </fields> |
||
| 6290 | </register> |
||
| 6291 | <register> |
||
| 6292 | <name>CCR3</name> |
||
| 6293 | <displayName>CCR3</displayName> |
||
| 6294 | <description>capture/compare register 3</description> |
||
| 6295 | <addressOffset>0x3C</addressOffset> |
||
| 6296 | <size>0x20</size> |
||
| 6297 | <access>read-write</access> |
||
| 6298 | <resetValue>0x00000000</resetValue> |
||
| 6299 | <fields> |
||
| 6300 | <field> |
||
| 6301 | <name>CCR3_H</name> |
||
| 6302 | <description>High Capture/Compare value (TIM2 |
||
| 6303 | only)</description> |
||
| 6304 | <bitOffset>16</bitOffset> |
||
| 6305 | <bitWidth>16</bitWidth> |
||
| 6306 | </field> |
||
| 6307 | <field> |
||
| 6308 | <name>CCR3_L</name> |
||
| 6309 | <description>Low Capture/Compare value</description> |
||
| 6310 | <bitOffset>0</bitOffset> |
||
| 6311 | <bitWidth>16</bitWidth> |
||
| 6312 | </field> |
||
| 6313 | </fields> |
||
| 6314 | </register> |
||
| 6315 | <register> |
||
| 6316 | <name>CCR4</name> |
||
| 6317 | <displayName>CCR4</displayName> |
||
| 6318 | <description>capture/compare register 4</description> |
||
| 6319 | <addressOffset>0x40</addressOffset> |
||
| 6320 | <size>0x20</size> |
||
| 6321 | <access>read-write</access> |
||
| 6322 | <resetValue>0x00000000</resetValue> |
||
| 6323 | <fields> |
||
| 6324 | <field> |
||
| 6325 | <name>CCR4_H</name> |
||
| 6326 | <description>High Capture/Compare value (TIM2 |
||
| 6327 | only)</description> |
||
| 6328 | <bitOffset>16</bitOffset> |
||
| 6329 | <bitWidth>16</bitWidth> |
||
| 6330 | </field> |
||
| 6331 | <field> |
||
| 6332 | <name>CCR4_L</name> |
||
| 6333 | <description>Low Capture/Compare value</description> |
||
| 6334 | <bitOffset>0</bitOffset> |
||
| 6335 | <bitWidth>16</bitWidth> |
||
| 6336 | </field> |
||
| 6337 | </fields> |
||
| 6338 | </register> |
||
| 6339 | <register> |
||
| 6340 | <name>DCR</name> |
||
| 6341 | <displayName>DCR</displayName> |
||
| 6342 | <description>DMA control register</description> |
||
| 6343 | <addressOffset>0x48</addressOffset> |
||
| 6344 | <size>0x20</size> |
||
| 6345 | <access>read-write</access> |
||
| 6346 | <resetValue>0x0000</resetValue> |
||
| 6347 | <fields> |
||
| 6348 | <field> |
||
| 6349 | <name>DBL</name> |
||
| 6350 | <description>DMA burst length</description> |
||
| 6351 | <bitOffset>8</bitOffset> |
||
| 6352 | <bitWidth>5</bitWidth> |
||
| 6353 | </field> |
||
| 6354 | <field> |
||
| 6355 | <name>DBA</name> |
||
| 6356 | <description>DMA base address</description> |
||
| 6357 | <bitOffset>0</bitOffset> |
||
| 6358 | <bitWidth>5</bitWidth> |
||
| 6359 | </field> |
||
| 6360 | </fields> |
||
| 6361 | </register> |
||
| 6362 | <register> |
||
| 6363 | <name>DMAR</name> |
||
| 6364 | <displayName>DMAR</displayName> |
||
| 6365 | <description>DMA address for full transfer</description> |
||
| 6366 | <addressOffset>0x4C</addressOffset> |
||
| 6367 | <size>0x20</size> |
||
| 6368 | <access>read-write</access> |
||
| 6369 | <resetValue>0x0000</resetValue> |
||
| 6370 | <fields> |
||
| 6371 | <field> |
||
| 6372 | <name>DMAR</name> |
||
| 6373 | <description>DMA register for burst |
||
| 6374 | accesses</description> |
||
| 6375 | <bitOffset>0</bitOffset> |
||
| 6376 | <bitWidth>16</bitWidth> |
||
| 6377 | </field> |
||
| 6378 | </fields> |
||
| 6379 | </register> |
||
| 6380 | </registers> |
||
| 6381 | </peripheral> |
||
| 6382 | <peripheral> |
||
| 6383 | <name>TIM14</name> |
||
| 6384 | <description>General-purpose-timers</description> |
||
| 6385 | <groupName>TIM</groupName> |
||
| 6386 | <baseAddress>0x40002000</baseAddress> |
||
| 6387 | <addressBlock> |
||
| 6388 | <offset>0x0</offset> |
||
| 6389 | <size>0x400</size> |
||
| 6390 | <usage>registers</usage> |
||
| 6391 | </addressBlock> |
||
| 6392 | <interrupt> |
||
| 6393 | <name>TIM2</name> |
||
| 6394 | <description>TIM2 global interrupt</description> |
||
| 6395 | <value>15</value> |
||
| 6396 | </interrupt> |
||
| 6397 | <registers> |
||
| 6398 | <register> |
||
| 6399 | <name>CR1</name> |
||
| 6400 | <displayName>CR1</displayName> |
||
| 6401 | <description>control register 1</description> |
||
| 6402 | <addressOffset>0x0</addressOffset> |
||
| 6403 | <size>0x20</size> |
||
| 6404 | <access>read-write</access> |
||
| 6405 | <resetValue>0x0000</resetValue> |
||
| 6406 | <fields> |
||
| 6407 | <field> |
||
| 6408 | <name>CKD</name> |
||
| 6409 | <description>Clock division</description> |
||
| 6410 | <bitOffset>8</bitOffset> |
||
| 6411 | <bitWidth>2</bitWidth> |
||
| 6412 | </field> |
||
| 6413 | <field> |
||
| 6414 | <name>ARPE</name> |
||
| 6415 | <description>Auto-reload preload enable</description> |
||
| 6416 | <bitOffset>7</bitOffset> |
||
| 6417 | <bitWidth>1</bitWidth> |
||
| 6418 | </field> |
||
| 6419 | <field> |
||
| 6420 | <name>URS</name> |
||
| 6421 | <description>Update request source</description> |
||
| 6422 | <bitOffset>2</bitOffset> |
||
| 6423 | <bitWidth>1</bitWidth> |
||
| 6424 | </field> |
||
| 6425 | <field> |
||
| 6426 | <name>UDIS</name> |
||
| 6427 | <description>Update disable</description> |
||
| 6428 | <bitOffset>1</bitOffset> |
||
| 6429 | <bitWidth>1</bitWidth> |
||
| 6430 | </field> |
||
| 6431 | <field> |
||
| 6432 | <name>CEN</name> |
||
| 6433 | <description>Counter enable</description> |
||
| 6434 | <bitOffset>0</bitOffset> |
||
| 6435 | <bitWidth>1</bitWidth> |
||
| 6436 | </field> |
||
| 6437 | </fields> |
||
| 6438 | </register> |
||
| 6439 | <register> |
||
| 6440 | <name>DIER</name> |
||
| 6441 | <displayName>DIER</displayName> |
||
| 6442 | <description>DMA/Interrupt enable register</description> |
||
| 6443 | <addressOffset>0xC</addressOffset> |
||
| 6444 | <size>0x20</size> |
||
| 6445 | <access>read-write</access> |
||
| 6446 | <resetValue>0x0000</resetValue> |
||
| 6447 | <fields> |
||
| 6448 | <field> |
||
| 6449 | <name>CC1IE</name> |
||
| 6450 | <description>Capture/Compare 1 interrupt |
||
| 6451 | enable</description> |
||
| 6452 | <bitOffset>1</bitOffset> |
||
| 6453 | <bitWidth>1</bitWidth> |
||
| 6454 | </field> |
||
| 6455 | <field> |
||
| 6456 | <name>UIE</name> |
||
| 6457 | <description>Update interrupt enable</description> |
||
| 6458 | <bitOffset>0</bitOffset> |
||
| 6459 | <bitWidth>1</bitWidth> |
||
| 6460 | </field> |
||
| 6461 | </fields> |
||
| 6462 | </register> |
||
| 6463 | <register> |
||
| 6464 | <name>SR</name> |
||
| 6465 | <displayName>SR</displayName> |
||
| 6466 | <description>status register</description> |
||
| 6467 | <addressOffset>0x10</addressOffset> |
||
| 6468 | <size>0x20</size> |
||
| 6469 | <access>read-write</access> |
||
| 6470 | <resetValue>0x0000</resetValue> |
||
| 6471 | <fields> |
||
| 6472 | <field> |
||
| 6473 | <name>CC1OF</name> |
||
| 6474 | <description>Capture/Compare 1 overcapture |
||
| 6475 | flag</description> |
||
| 6476 | <bitOffset>9</bitOffset> |
||
| 6477 | <bitWidth>1</bitWidth> |
||
| 6478 | </field> |
||
| 6479 | <field> |
||
| 6480 | <name>CC1IF</name> |
||
| 6481 | <description>Capture/compare 1 interrupt |
||
| 6482 | flag</description> |
||
| 6483 | <bitOffset>1</bitOffset> |
||
| 6484 | <bitWidth>1</bitWidth> |
||
| 6485 | </field> |
||
| 6486 | <field> |
||
| 6487 | <name>UIF</name> |
||
| 6488 | <description>Update interrupt flag</description> |
||
| 6489 | <bitOffset>0</bitOffset> |
||
| 6490 | <bitWidth>1</bitWidth> |
||
| 6491 | </field> |
||
| 6492 | </fields> |
||
| 6493 | </register> |
||
| 6494 | <register> |
||
| 6495 | <name>EGR</name> |
||
| 6496 | <displayName>EGR</displayName> |
||
| 6497 | <description>event generation register</description> |
||
| 6498 | <addressOffset>0x14</addressOffset> |
||
| 6499 | <size>0x20</size> |
||
| 6500 | <access>write-only</access> |
||
| 6501 | <resetValue>0x0000</resetValue> |
||
| 6502 | <fields> |
||
| 6503 | <field> |
||
| 6504 | <name>CC1G</name> |
||
| 6505 | <description>Capture/compare 1 |
||
| 6506 | generation</description> |
||
| 6507 | <bitOffset>1</bitOffset> |
||
| 6508 | <bitWidth>1</bitWidth> |
||
| 6509 | </field> |
||
| 6510 | <field> |
||
| 6511 | <name>UG</name> |
||
| 6512 | <description>Update generation</description> |
||
| 6513 | <bitOffset>0</bitOffset> |
||
| 6514 | <bitWidth>1</bitWidth> |
||
| 6515 | </field> |
||
| 6516 | </fields> |
||
| 6517 | </register> |
||
| 6518 | <register> |
||
| 6519 | <name>CCMR1_Output</name> |
||
| 6520 | <displayName>CCMR1_Output</displayName> |
||
| 6521 | <description>capture/compare mode register (output |
||
| 6522 | mode)</description> |
||
| 6523 | <addressOffset>0x18</addressOffset> |
||
| 6524 | <size>0x20</size> |
||
| 6525 | <access>read-write</access> |
||
| 6526 | <resetValue>0x00000000</resetValue> |
||
| 6527 | <fields> |
||
| 6528 | <field> |
||
| 6529 | <name>CC1S</name> |
||
| 6530 | <description>Capture/Compare 1 |
||
| 6531 | selection</description> |
||
| 6532 | <bitOffset>0</bitOffset> |
||
| 6533 | <bitWidth>2</bitWidth> |
||
| 6534 | </field> |
||
| 6535 | <field> |
||
| 6536 | <name>OC1FE</name> |
||
| 6537 | <description>Output compare 1 fast |
||
| 6538 | enable</description> |
||
| 6539 | <bitOffset>2</bitOffset> |
||
| 6540 | <bitWidth>1</bitWidth> |
||
| 6541 | </field> |
||
| 6542 | <field> |
||
| 6543 | <name>OC1PE</name> |
||
| 6544 | <description>Output Compare 1 preload |
||
| 6545 | enable</description> |
||
| 6546 | <bitOffset>3</bitOffset> |
||
| 6547 | <bitWidth>1</bitWidth> |
||
| 6548 | </field> |
||
| 6549 | <field> |
||
| 6550 | <name>OC1M</name> |
||
| 6551 | <description>Output Compare 1 mode</description> |
||
| 6552 | <bitOffset>4</bitOffset> |
||
| 6553 | <bitWidth>3</bitWidth> |
||
| 6554 | </field> |
||
| 6555 | </fields> |
||
| 6556 | </register> |
||
| 6557 | <register> |
||
| 6558 | <name>CCMR1_Input</name> |
||
| 6559 | <displayName>CCMR1_Input</displayName> |
||
| 6560 | <description>capture/compare mode register (input |
||
| 6561 | mode)</description> |
||
| 6562 | <alternateRegister>CCMR1_Output</alternateRegister> |
||
| 6563 | <addressOffset>0x18</addressOffset> |
||
| 6564 | <size>0x20</size> |
||
| 6565 | <access>read-write</access> |
||
| 6566 | <resetValue>0x00000000</resetValue> |
||
| 6567 | <fields> |
||
| 6568 | <field> |
||
| 6569 | <name>IC1F</name> |
||
| 6570 | <description>Input capture 1 filter</description> |
||
| 6571 | <bitOffset>4</bitOffset> |
||
| 6572 | <bitWidth>4</bitWidth> |
||
| 6573 | </field> |
||
| 6574 | <field> |
||
| 6575 | <name>IC1PSC</name> |
||
| 6576 | <description>Input capture 1 prescaler</description> |
||
| 6577 | <bitOffset>2</bitOffset> |
||
| 6578 | <bitWidth>2</bitWidth> |
||
| 6579 | </field> |
||
| 6580 | <field> |
||
| 6581 | <name>CC1S</name> |
||
| 6582 | <description>Capture/Compare 1 |
||
| 6583 | selection</description> |
||
| 6584 | <bitOffset>0</bitOffset> |
||
| 6585 | <bitWidth>2</bitWidth> |
||
| 6586 | </field> |
||
| 6587 | </fields> |
||
| 6588 | </register> |
||
| 6589 | <register> |
||
| 6590 | <name>CCER</name> |
||
| 6591 | <displayName>CCER</displayName> |
||
| 6592 | <description>capture/compare enable |
||
| 6593 | register</description> |
||
| 6594 | <addressOffset>0x20</addressOffset> |
||
| 6595 | <size>0x20</size> |
||
| 6596 | <access>read-write</access> |
||
| 6597 | <resetValue>0x0000</resetValue> |
||
| 6598 | <fields> |
||
| 6599 | <field> |
||
| 6600 | <name>CC1NP</name> |
||
| 6601 | <description>Capture/Compare 1 output |
||
| 6602 | Polarity</description> |
||
| 6603 | <bitOffset>3</bitOffset> |
||
| 6604 | <bitWidth>1</bitWidth> |
||
| 6605 | </field> |
||
| 6606 | <field> |
||
| 6607 | <name>CC1P</name> |
||
| 6608 | <description>Capture/Compare 1 output |
||
| 6609 | Polarity</description> |
||
| 6610 | <bitOffset>1</bitOffset> |
||
| 6611 | <bitWidth>1</bitWidth> |
||
| 6612 | </field> |
||
| 6613 | <field> |
||
| 6614 | <name>CC1E</name> |
||
| 6615 | <description>Capture/Compare 1 output |
||
| 6616 | enable</description> |
||
| 6617 | <bitOffset>0</bitOffset> |
||
| 6618 | <bitWidth>1</bitWidth> |
||
| 6619 | </field> |
||
| 6620 | </fields> |
||
| 6621 | </register> |
||
| 6622 | <register> |
||
| 6623 | <name>CNT</name> |
||
| 6624 | <displayName>CNT</displayName> |
||
| 6625 | <description>counter</description> |
||
| 6626 | <addressOffset>0x24</addressOffset> |
||
| 6627 | <size>0x20</size> |
||
| 6628 | <access>read-write</access> |
||
| 6629 | <resetValue>0x00000000</resetValue> |
||
| 6630 | <fields> |
||
| 6631 | <field> |
||
| 6632 | <name>CNT</name> |
||
| 6633 | <description>counter value</description> |
||
| 6634 | <bitOffset>0</bitOffset> |
||
| 6635 | <bitWidth>16</bitWidth> |
||
| 6636 | </field> |
||
| 6637 | </fields> |
||
| 6638 | </register> |
||
| 6639 | <register> |
||
| 6640 | <name>PSC</name> |
||
| 6641 | <displayName>PSC</displayName> |
||
| 6642 | <description>prescaler</description> |
||
| 6643 | <addressOffset>0x28</addressOffset> |
||
| 6644 | <size>0x20</size> |
||
| 6645 | <access>read-write</access> |
||
| 6646 | <resetValue>0x0000</resetValue> |
||
| 6647 | <fields> |
||
| 6648 | <field> |
||
| 6649 | <name>PSC</name> |
||
| 6650 | <description>Prescaler value</description> |
||
| 6651 | <bitOffset>0</bitOffset> |
||
| 6652 | <bitWidth>16</bitWidth> |
||
| 6653 | </field> |
||
| 6654 | </fields> |
||
| 6655 | </register> |
||
| 6656 | <register> |
||
| 6657 | <name>ARR</name> |
||
| 6658 | <displayName>ARR</displayName> |
||
| 6659 | <description>auto-reload register</description> |
||
| 6660 | <addressOffset>0x2C</addressOffset> |
||
| 6661 | <size>0x20</size> |
||
| 6662 | <access>read-write</access> |
||
| 6663 | <resetValue>0x00000000</resetValue> |
||
| 6664 | <fields> |
||
| 6665 | <field> |
||
| 6666 | <name>ARR</name> |
||
| 6667 | <description>Auto-reload value</description> |
||
| 6668 | <bitOffset>0</bitOffset> |
||
| 6669 | <bitWidth>16</bitWidth> |
||
| 6670 | </field> |
||
| 6671 | </fields> |
||
| 6672 | </register> |
||
| 6673 | <register> |
||
| 6674 | <name>CCR1</name> |
||
| 6675 | <displayName>CCR1</displayName> |
||
| 6676 | <description>capture/compare register 1</description> |
||
| 6677 | <addressOffset>0x34</addressOffset> |
||
| 6678 | <size>0x20</size> |
||
| 6679 | <access>read-write</access> |
||
| 6680 | <resetValue>0x00000000</resetValue> |
||
| 6681 | <fields> |
||
| 6682 | <field> |
||
| 6683 | <name>CCR1</name> |
||
| 6684 | <description>Capture/Compare 1 value</description> |
||
| 6685 | <bitOffset>0</bitOffset> |
||
| 6686 | <bitWidth>16</bitWidth> |
||
| 6687 | </field> |
||
| 6688 | </fields> |
||
| 6689 | </register> |
||
| 6690 | <register> |
||
| 6691 | <name>OR</name> |
||
| 6692 | <displayName>OR</displayName> |
||
| 6693 | <description>option register</description> |
||
| 6694 | <addressOffset>0x50</addressOffset> |
||
| 6695 | <size>0x20</size> |
||
| 6696 | <access>read-write</access> |
||
| 6697 | <resetValue>0x00000000</resetValue> |
||
| 6698 | <fields> |
||
| 6699 | <field> |
||
| 6700 | <name>RMP</name> |
||
| 6701 | <description>Timer input 1 remap</description> |
||
| 6702 | <bitOffset>0</bitOffset> |
||
| 6703 | <bitWidth>2</bitWidth> |
||
| 6704 | </field> |
||
| 6705 | </fields> |
||
| 6706 | </register> |
||
| 6707 | </registers> |
||
| 6708 | </peripheral> |
||
| 6709 | <peripheral> |
||
| 6710 | <name>TIM6</name> |
||
| 6711 | <description>Basic-timers</description> |
||
| 6712 | <groupName>TIM</groupName> |
||
| 6713 | <baseAddress>0x40001000</baseAddress> |
||
| 6714 | <addressBlock> |
||
| 6715 | <offset>0x0</offset> |
||
| 6716 | <size>0x400</size> |
||
| 6717 | <usage>registers</usage> |
||
| 6718 | </addressBlock> |
||
| 6719 | <interrupt> |
||
| 6720 | <name>TIM3</name> |
||
| 6721 | <description>TIM3 global interrupt</description> |
||
| 6722 | <value>16</value> |
||
| 6723 | </interrupt> |
||
| 6724 | <registers> |
||
| 6725 | <register> |
||
| 6726 | <name>CR1</name> |
||
| 6727 | <displayName>CR1</displayName> |
||
| 6728 | <description>control register 1</description> |
||
| 6729 | <addressOffset>0x0</addressOffset> |
||
| 6730 | <size>0x20</size> |
||
| 6731 | <access>read-write</access> |
||
| 6732 | <resetValue>0x0000</resetValue> |
||
| 6733 | <fields> |
||
| 6734 | <field> |
||
| 6735 | <name>ARPE</name> |
||
| 6736 | <description>Auto-reload preload enable</description> |
||
| 6737 | <bitOffset>7</bitOffset> |
||
| 6738 | <bitWidth>1</bitWidth> |
||
| 6739 | </field> |
||
| 6740 | <field> |
||
| 6741 | <name>OPM</name> |
||
| 6742 | <description>One-pulse mode</description> |
||
| 6743 | <bitOffset>3</bitOffset> |
||
| 6744 | <bitWidth>1</bitWidth> |
||
| 6745 | </field> |
||
| 6746 | <field> |
||
| 6747 | <name>URS</name> |
||
| 6748 | <description>Update request source</description> |
||
| 6749 | <bitOffset>2</bitOffset> |
||
| 6750 | <bitWidth>1</bitWidth> |
||
| 6751 | </field> |
||
| 6752 | <field> |
||
| 6753 | <name>UDIS</name> |
||
| 6754 | <description>Update disable</description> |
||
| 6755 | <bitOffset>1</bitOffset> |
||
| 6756 | <bitWidth>1</bitWidth> |
||
| 6757 | </field> |
||
| 6758 | <field> |
||
| 6759 | <name>CEN</name> |
||
| 6760 | <description>Counter enable</description> |
||
| 6761 | <bitOffset>0</bitOffset> |
||
| 6762 | <bitWidth>1</bitWidth> |
||
| 6763 | </field> |
||
| 6764 | </fields> |
||
| 6765 | </register> |
||
| 6766 | <register> |
||
| 6767 | <name>CR2</name> |
||
| 6768 | <displayName>CR2</displayName> |
||
| 6769 | <description>control register 2</description> |
||
| 6770 | <addressOffset>0x4</addressOffset> |
||
| 6771 | <size>0x20</size> |
||
| 6772 | <access>read-write</access> |
||
| 6773 | <resetValue>0x0000</resetValue> |
||
| 6774 | <fields> |
||
| 6775 | <field> |
||
| 6776 | <name>MMS</name> |
||
| 6777 | <description>Master mode selection</description> |
||
| 6778 | <bitOffset>4</bitOffset> |
||
| 6779 | <bitWidth>3</bitWidth> |
||
| 6780 | </field> |
||
| 6781 | </fields> |
||
| 6782 | </register> |
||
| 6783 | <register> |
||
| 6784 | <name>DIER</name> |
||
| 6785 | <displayName>DIER</displayName> |
||
| 6786 | <description>DMA/Interrupt enable register</description> |
||
| 6787 | <addressOffset>0xC</addressOffset> |
||
| 6788 | <size>0x20</size> |
||
| 6789 | <access>read-write</access> |
||
| 6790 | <resetValue>0x0000</resetValue> |
||
| 6791 | <fields> |
||
| 6792 | <field> |
||
| 6793 | <name>UDE</name> |
||
| 6794 | <description>Update DMA request enable</description> |
||
| 6795 | <bitOffset>8</bitOffset> |
||
| 6796 | <bitWidth>1</bitWidth> |
||
| 6797 | </field> |
||
| 6798 | <field> |
||
| 6799 | <name>UIE</name> |
||
| 6800 | <description>Update interrupt enable</description> |
||
| 6801 | <bitOffset>0</bitOffset> |
||
| 6802 | <bitWidth>1</bitWidth> |
||
| 6803 | </field> |
||
| 6804 | </fields> |
||
| 6805 | </register> |
||
| 6806 | <register> |
||
| 6807 | <name>SR</name> |
||
| 6808 | <displayName>SR</displayName> |
||
| 6809 | <description>status register</description> |
||
| 6810 | <addressOffset>0x10</addressOffset> |
||
| 6811 | <size>0x20</size> |
||
| 6812 | <access>read-write</access> |
||
| 6813 | <resetValue>0x0000</resetValue> |
||
| 6814 | <fields> |
||
| 6815 | <field> |
||
| 6816 | <name>UIF</name> |
||
| 6817 | <description>Update interrupt flag</description> |
||
| 6818 | <bitOffset>0</bitOffset> |
||
| 6819 | <bitWidth>1</bitWidth> |
||
| 6820 | </field> |
||
| 6821 | </fields> |
||
| 6822 | </register> |
||
| 6823 | <register> |
||
| 6824 | <name>EGR</name> |
||
| 6825 | <displayName>EGR</displayName> |
||
| 6826 | <description>event generation register</description> |
||
| 6827 | <addressOffset>0x14</addressOffset> |
||
| 6828 | <size>0x20</size> |
||
| 6829 | <access>write-only</access> |
||
| 6830 | <resetValue>0x0000</resetValue> |
||
| 6831 | <fields> |
||
| 6832 | <field> |
||
| 6833 | <name>UG</name> |
||
| 6834 | <description>Update generation</description> |
||
| 6835 | <bitOffset>0</bitOffset> |
||
| 6836 | <bitWidth>1</bitWidth> |
||
| 6837 | </field> |
||
| 6838 | </fields> |
||
| 6839 | </register> |
||
| 6840 | <register> |
||
| 6841 | <name>CNT</name> |
||
| 6842 | <displayName>CNT</displayName> |
||
| 6843 | <description>counter</description> |
||
| 6844 | <addressOffset>0x24</addressOffset> |
||
| 6845 | <size>0x20</size> |
||
| 6846 | <access>read-write</access> |
||
| 6847 | <resetValue>0x00000000</resetValue> |
||
| 6848 | <fields> |
||
| 6849 | <field> |
||
| 6850 | <name>CNT</name> |
||
| 6851 | <description>Low counter value</description> |
||
| 6852 | <bitOffset>0</bitOffset> |
||
| 6853 | <bitWidth>16</bitWidth> |
||
| 6854 | </field> |
||
| 6855 | </fields> |
||
| 6856 | </register> |
||
| 6857 | <register> |
||
| 6858 | <name>PSC</name> |
||
| 6859 | <displayName>PSC</displayName> |
||
| 6860 | <description>prescaler</description> |
||
| 6861 | <addressOffset>0x28</addressOffset> |
||
| 6862 | <size>0x20</size> |
||
| 6863 | <access>read-write</access> |
||
| 6864 | <resetValue>0x0000</resetValue> |
||
| 6865 | <fields> |
||
| 6866 | <field> |
||
| 6867 | <name>PSC</name> |
||
| 6868 | <description>Prescaler value</description> |
||
| 6869 | <bitOffset>0</bitOffset> |
||
| 6870 | <bitWidth>16</bitWidth> |
||
| 6871 | </field> |
||
| 6872 | </fields> |
||
| 6873 | </register> |
||
| 6874 | <register> |
||
| 6875 | <name>ARR</name> |
||
| 6876 | <displayName>ARR</displayName> |
||
| 6877 | <description>auto-reload register</description> |
||
| 6878 | <addressOffset>0x2C</addressOffset> |
||
| 6879 | <size>0x20</size> |
||
| 6880 | <access>read-write</access> |
||
| 6881 | <resetValue>0x00000000</resetValue> |
||
| 6882 | <fields> |
||
| 6883 | <field> |
||
| 6884 | <name>ARR</name> |
||
| 6885 | <description>Low Auto-reload value</description> |
||
| 6886 | <bitOffset>0</bitOffset> |
||
| 6887 | <bitWidth>16</bitWidth> |
||
| 6888 | </field> |
||
| 6889 | </fields> |
||
| 6890 | </register> |
||
| 6891 | </registers> |
||
| 6892 | </peripheral> |
||
| 6893 | <peripheral> |
||
| 6894 | <name>EXTI</name> |
||
| 6895 | <description>External interrupt/event |
||
| 6896 | controller</description> |
||
| 6897 | <groupName>EXTI</groupName> |
||
| 6898 | <baseAddress>0x40010400</baseAddress> |
||
| 6899 | <addressBlock> |
||
| 6900 | <offset>0x0</offset> |
||
| 6901 | <size>0x400</size> |
||
| 6902 | <usage>registers</usage> |
||
| 6903 | </addressBlock> |
||
| 6904 | <interrupt> |
||
| 6905 | <name>TIM14</name> |
||
| 6906 | <description>TIM14 global interrupt</description> |
||
| 6907 | <value>19</value> |
||
| 6908 | </interrupt> |
||
| 6909 | <registers> |
||
| 6910 | <register> |
||
| 6911 | <name>IMR</name> |
||
| 6912 | <displayName>IMR</displayName> |
||
| 6913 | <description>Interrupt mask register |
||
| 6914 | (EXTI_IMR)</description> |
||
| 6915 | <addressOffset>0x0</addressOffset> |
||
| 6916 | <size>0x20</size> |
||
| 6917 | <access>read-write</access> |
||
| 6918 | <resetValue>0x0F940000</resetValue> |
||
| 6919 | <fields> |
||
| 6920 | <field> |
||
| 6921 | <name>MR0</name> |
||
| 6922 | <description>Interrupt Mask on line 0</description> |
||
| 6923 | <bitOffset>0</bitOffset> |
||
| 6924 | <bitWidth>1</bitWidth> |
||
| 6925 | </field> |
||
| 6926 | <field> |
||
| 6927 | <name>MR1</name> |
||
| 6928 | <description>Interrupt Mask on line 1</description> |
||
| 6929 | <bitOffset>1</bitOffset> |
||
| 6930 | <bitWidth>1</bitWidth> |
||
| 6931 | </field> |
||
| 6932 | <field> |
||
| 6933 | <name>MR2</name> |
||
| 6934 | <description>Interrupt Mask on line 2</description> |
||
| 6935 | <bitOffset>2</bitOffset> |
||
| 6936 | <bitWidth>1</bitWidth> |
||
| 6937 | </field> |
||
| 6938 | <field> |
||
| 6939 | <name>MR3</name> |
||
| 6940 | <description>Interrupt Mask on line 3</description> |
||
| 6941 | <bitOffset>3</bitOffset> |
||
| 6942 | <bitWidth>1</bitWidth> |
||
| 6943 | </field> |
||
| 6944 | <field> |
||
| 6945 | <name>MR4</name> |
||
| 6946 | <description>Interrupt Mask on line 4</description> |
||
| 6947 | <bitOffset>4</bitOffset> |
||
| 6948 | <bitWidth>1</bitWidth> |
||
| 6949 | </field> |
||
| 6950 | <field> |
||
| 6951 | <name>MR5</name> |
||
| 6952 | <description>Interrupt Mask on line 5</description> |
||
| 6953 | <bitOffset>5</bitOffset> |
||
| 6954 | <bitWidth>1</bitWidth> |
||
| 6955 | </field> |
||
| 6956 | <field> |
||
| 6957 | <name>MR6</name> |
||
| 6958 | <description>Interrupt Mask on line 6</description> |
||
| 6959 | <bitOffset>6</bitOffset> |
||
| 6960 | <bitWidth>1</bitWidth> |
||
| 6961 | </field> |
||
| 6962 | <field> |
||
| 6963 | <name>MR7</name> |
||
| 6964 | <description>Interrupt Mask on line 7</description> |
||
| 6965 | <bitOffset>7</bitOffset> |
||
| 6966 | <bitWidth>1</bitWidth> |
||
| 6967 | </field> |
||
| 6968 | <field> |
||
| 6969 | <name>MR8</name> |
||
| 6970 | <description>Interrupt Mask on line 8</description> |
||
| 6971 | <bitOffset>8</bitOffset> |
||
| 6972 | <bitWidth>1</bitWidth> |
||
| 6973 | </field> |
||
| 6974 | <field> |
||
| 6975 | <name>MR9</name> |
||
| 6976 | <description>Interrupt Mask on line 9</description> |
||
| 6977 | <bitOffset>9</bitOffset> |
||
| 6978 | <bitWidth>1</bitWidth> |
||
| 6979 | </field> |
||
| 6980 | <field> |
||
| 6981 | <name>MR10</name> |
||
| 6982 | <description>Interrupt Mask on line 10</description> |
||
| 6983 | <bitOffset>10</bitOffset> |
||
| 6984 | <bitWidth>1</bitWidth> |
||
| 6985 | </field> |
||
| 6986 | <field> |
||
| 6987 | <name>MR11</name> |
||
| 6988 | <description>Interrupt Mask on line 11</description> |
||
| 6989 | <bitOffset>11</bitOffset> |
||
| 6990 | <bitWidth>1</bitWidth> |
||
| 6991 | </field> |
||
| 6992 | <field> |
||
| 6993 | <name>MR12</name> |
||
| 6994 | <description>Interrupt Mask on line 12</description> |
||
| 6995 | <bitOffset>12</bitOffset> |
||
| 6996 | <bitWidth>1</bitWidth> |
||
| 6997 | </field> |
||
| 6998 | <field> |
||
| 6999 | <name>MR13</name> |
||
| 7000 | <description>Interrupt Mask on line 13</description> |
||
| 7001 | <bitOffset>13</bitOffset> |
||
| 7002 | <bitWidth>1</bitWidth> |
||
| 7003 | </field> |
||
| 7004 | <field> |
||
| 7005 | <name>MR14</name> |
||
| 7006 | <description>Interrupt Mask on line 14</description> |
||
| 7007 | <bitOffset>14</bitOffset> |
||
| 7008 | <bitWidth>1</bitWidth> |
||
| 7009 | </field> |
||
| 7010 | <field> |
||
| 7011 | <name>MR15</name> |
||
| 7012 | <description>Interrupt Mask on line 15</description> |
||
| 7013 | <bitOffset>15</bitOffset> |
||
| 7014 | <bitWidth>1</bitWidth> |
||
| 7015 | </field> |
||
| 7016 | <field> |
||
| 7017 | <name>MR16</name> |
||
| 7018 | <description>Interrupt Mask on line 16</description> |
||
| 7019 | <bitOffset>16</bitOffset> |
||
| 7020 | <bitWidth>1</bitWidth> |
||
| 7021 | </field> |
||
| 7022 | <field> |
||
| 7023 | <name>MR17</name> |
||
| 7024 | <description>Interrupt Mask on line 17</description> |
||
| 7025 | <bitOffset>17</bitOffset> |
||
| 7026 | <bitWidth>1</bitWidth> |
||
| 7027 | </field> |
||
| 7028 | <field> |
||
| 7029 | <name>MR18</name> |
||
| 7030 | <description>Interrupt Mask on line 18</description> |
||
| 7031 | <bitOffset>18</bitOffset> |
||
| 7032 | <bitWidth>1</bitWidth> |
||
| 7033 | </field> |
||
| 7034 | <field> |
||
| 7035 | <name>MR19</name> |
||
| 7036 | <description>Interrupt Mask on line 19</description> |
||
| 7037 | <bitOffset>19</bitOffset> |
||
| 7038 | <bitWidth>1</bitWidth> |
||
| 7039 | </field> |
||
| 7040 | <field> |
||
| 7041 | <name>MR20</name> |
||
| 7042 | <description>Interrupt Mask on line 20</description> |
||
| 7043 | <bitOffset>20</bitOffset> |
||
| 7044 | <bitWidth>1</bitWidth> |
||
| 7045 | </field> |
||
| 7046 | <field> |
||
| 7047 | <name>MR21</name> |
||
| 7048 | <description>Interrupt Mask on line 21</description> |
||
| 7049 | <bitOffset>21</bitOffset> |
||
| 7050 | <bitWidth>1</bitWidth> |
||
| 7051 | </field> |
||
| 7052 | <field> |
||
| 7053 | <name>MR22</name> |
||
| 7054 | <description>Interrupt Mask on line 22</description> |
||
| 7055 | <bitOffset>22</bitOffset> |
||
| 7056 | <bitWidth>1</bitWidth> |
||
| 7057 | </field> |
||
| 7058 | <field> |
||
| 7059 | <name>MR23</name> |
||
| 7060 | <description>Interrupt Mask on line 23</description> |
||
| 7061 | <bitOffset>23</bitOffset> |
||
| 7062 | <bitWidth>1</bitWidth> |
||
| 7063 | </field> |
||
| 7064 | <field> |
||
| 7065 | <name>MR24</name> |
||
| 7066 | <description>Interrupt Mask on line 24</description> |
||
| 7067 | <bitOffset>24</bitOffset> |
||
| 7068 | <bitWidth>1</bitWidth> |
||
| 7069 | </field> |
||
| 7070 | <field> |
||
| 7071 | <name>MR25</name> |
||
| 7072 | <description>Interrupt Mask on line 25</description> |
||
| 7073 | <bitOffset>25</bitOffset> |
||
| 7074 | <bitWidth>1</bitWidth> |
||
| 7075 | </field> |
||
| 7076 | <field> |
||
| 7077 | <name>MR26</name> |
||
| 7078 | <description>Interrupt Mask on line 26</description> |
||
| 7079 | <bitOffset>26</bitOffset> |
||
| 7080 | <bitWidth>1</bitWidth> |
||
| 7081 | </field> |
||
| 7082 | <field> |
||
| 7083 | <name>MR27</name> |
||
| 7084 | <description>Interrupt Mask on line 27</description> |
||
| 7085 | <bitOffset>27</bitOffset> |
||
| 7086 | <bitWidth>1</bitWidth> |
||
| 7087 | </field> |
||
| 7088 | </fields> |
||
| 7089 | </register> |
||
| 7090 | <register> |
||
| 7091 | <name>EMR</name> |
||
| 7092 | <displayName>EMR</displayName> |
||
| 7093 | <description>Event mask register (EXTI_EMR)</description> |
||
| 7094 | <addressOffset>0x4</addressOffset> |
||
| 7095 | <size>0x20</size> |
||
| 7096 | <access>read-write</access> |
||
| 7097 | <resetValue>0x00000000</resetValue> |
||
| 7098 | <fields> |
||
| 7099 | <field> |
||
| 7100 | <name>MR0</name> |
||
| 7101 | <description>Event Mask on line 0</description> |
||
| 7102 | <bitOffset>0</bitOffset> |
||
| 7103 | <bitWidth>1</bitWidth> |
||
| 7104 | </field> |
||
| 7105 | <field> |
||
| 7106 | <name>MR1</name> |
||
| 7107 | <description>Event Mask on line 1</description> |
||
| 7108 | <bitOffset>1</bitOffset> |
||
| 7109 | <bitWidth>1</bitWidth> |
||
| 7110 | </field> |
||
| 7111 | <field> |
||
| 7112 | <name>MR2</name> |
||
| 7113 | <description>Event Mask on line 2</description> |
||
| 7114 | <bitOffset>2</bitOffset> |
||
| 7115 | <bitWidth>1</bitWidth> |
||
| 7116 | </field> |
||
| 7117 | <field> |
||
| 7118 | <name>MR3</name> |
||
| 7119 | <description>Event Mask on line 3</description> |
||
| 7120 | <bitOffset>3</bitOffset> |
||
| 7121 | <bitWidth>1</bitWidth> |
||
| 7122 | </field> |
||
| 7123 | <field> |
||
| 7124 | <name>MR4</name> |
||
| 7125 | <description>Event Mask on line 4</description> |
||
| 7126 | <bitOffset>4</bitOffset> |
||
| 7127 | <bitWidth>1</bitWidth> |
||
| 7128 | </field> |
||
| 7129 | <field> |
||
| 7130 | <name>MR5</name> |
||
| 7131 | <description>Event Mask on line 5</description> |
||
| 7132 | <bitOffset>5</bitOffset> |
||
| 7133 | <bitWidth>1</bitWidth> |
||
| 7134 | </field> |
||
| 7135 | <field> |
||
| 7136 | <name>MR6</name> |
||
| 7137 | <description>Event Mask on line 6</description> |
||
| 7138 | <bitOffset>6</bitOffset> |
||
| 7139 | <bitWidth>1</bitWidth> |
||
| 7140 | </field> |
||
| 7141 | <field> |
||
| 7142 | <name>MR7</name> |
||
| 7143 | <description>Event Mask on line 7</description> |
||
| 7144 | <bitOffset>7</bitOffset> |
||
| 7145 | <bitWidth>1</bitWidth> |
||
| 7146 | </field> |
||
| 7147 | <field> |
||
| 7148 | <name>MR8</name> |
||
| 7149 | <description>Event Mask on line 8</description> |
||
| 7150 | <bitOffset>8</bitOffset> |
||
| 7151 | <bitWidth>1</bitWidth> |
||
| 7152 | </field> |
||
| 7153 | <field> |
||
| 7154 | <name>MR9</name> |
||
| 7155 | <description>Event Mask on line 9</description> |
||
| 7156 | <bitOffset>9</bitOffset> |
||
| 7157 | <bitWidth>1</bitWidth> |
||
| 7158 | </field> |
||
| 7159 | <field> |
||
| 7160 | <name>MR10</name> |
||
| 7161 | <description>Event Mask on line 10</description> |
||
| 7162 | <bitOffset>10</bitOffset> |
||
| 7163 | <bitWidth>1</bitWidth> |
||
| 7164 | </field> |
||
| 7165 | <field> |
||
| 7166 | <name>MR11</name> |
||
| 7167 | <description>Event Mask on line 11</description> |
||
| 7168 | <bitOffset>11</bitOffset> |
||
| 7169 | <bitWidth>1</bitWidth> |
||
| 7170 | </field> |
||
| 7171 | <field> |
||
| 7172 | <name>MR12</name> |
||
| 7173 | <description>Event Mask on line 12</description> |
||
| 7174 | <bitOffset>12</bitOffset> |
||
| 7175 | <bitWidth>1</bitWidth> |
||
| 7176 | </field> |
||
| 7177 | <field> |
||
| 7178 | <name>MR13</name> |
||
| 7179 | <description>Event Mask on line 13</description> |
||
| 7180 | <bitOffset>13</bitOffset> |
||
| 7181 | <bitWidth>1</bitWidth> |
||
| 7182 | </field> |
||
| 7183 | <field> |
||
| 7184 | <name>MR14</name> |
||
| 7185 | <description>Event Mask on line 14</description> |
||
| 7186 | <bitOffset>14</bitOffset> |
||
| 7187 | <bitWidth>1</bitWidth> |
||
| 7188 | </field> |
||
| 7189 | <field> |
||
| 7190 | <name>MR15</name> |
||
| 7191 | <description>Event Mask on line 15</description> |
||
| 7192 | <bitOffset>15</bitOffset> |
||
| 7193 | <bitWidth>1</bitWidth> |
||
| 7194 | </field> |
||
| 7195 | <field> |
||
| 7196 | <name>MR16</name> |
||
| 7197 | <description>Event Mask on line 16</description> |
||
| 7198 | <bitOffset>16</bitOffset> |
||
| 7199 | <bitWidth>1</bitWidth> |
||
| 7200 | </field> |
||
| 7201 | <field> |
||
| 7202 | <name>MR17</name> |
||
| 7203 | <description>Event Mask on line 17</description> |
||
| 7204 | <bitOffset>17</bitOffset> |
||
| 7205 | <bitWidth>1</bitWidth> |
||
| 7206 | </field> |
||
| 7207 | <field> |
||
| 7208 | <name>MR18</name> |
||
| 7209 | <description>Event Mask on line 18</description> |
||
| 7210 | <bitOffset>18</bitOffset> |
||
| 7211 | <bitWidth>1</bitWidth> |
||
| 7212 | </field> |
||
| 7213 | <field> |
||
| 7214 | <name>MR19</name> |
||
| 7215 | <description>Event Mask on line 19</description> |
||
| 7216 | <bitOffset>19</bitOffset> |
||
| 7217 | <bitWidth>1</bitWidth> |
||
| 7218 | </field> |
||
| 7219 | <field> |
||
| 7220 | <name>MR20</name> |
||
| 7221 | <description>Event Mask on line 20</description> |
||
| 7222 | <bitOffset>20</bitOffset> |
||
| 7223 | <bitWidth>1</bitWidth> |
||
| 7224 | </field> |
||
| 7225 | <field> |
||
| 7226 | <name>MR21</name> |
||
| 7227 | <description>Event Mask on line 21</description> |
||
| 7228 | <bitOffset>21</bitOffset> |
||
| 7229 | <bitWidth>1</bitWidth> |
||
| 7230 | </field> |
||
| 7231 | <field> |
||
| 7232 | <name>MR22</name> |
||
| 7233 | <description>Event Mask on line 22</description> |
||
| 7234 | <bitOffset>22</bitOffset> |
||
| 7235 | <bitWidth>1</bitWidth> |
||
| 7236 | </field> |
||
| 7237 | <field> |
||
| 7238 | <name>MR23</name> |
||
| 7239 | <description>Event Mask on line 23</description> |
||
| 7240 | <bitOffset>23</bitOffset> |
||
| 7241 | <bitWidth>1</bitWidth> |
||
| 7242 | </field> |
||
| 7243 | <field> |
||
| 7244 | <name>MR24</name> |
||
| 7245 | <description>Event Mask on line 24</description> |
||
| 7246 | <bitOffset>24</bitOffset> |
||
| 7247 | <bitWidth>1</bitWidth> |
||
| 7248 | </field> |
||
| 7249 | <field> |
||
| 7250 | <name>MR25</name> |
||
| 7251 | <description>Event Mask on line 25</description> |
||
| 7252 | <bitOffset>25</bitOffset> |
||
| 7253 | <bitWidth>1</bitWidth> |
||
| 7254 | </field> |
||
| 7255 | <field> |
||
| 7256 | <name>MR26</name> |
||
| 7257 | <description>Event Mask on line 26</description> |
||
| 7258 | <bitOffset>26</bitOffset> |
||
| 7259 | <bitWidth>1</bitWidth> |
||
| 7260 | </field> |
||
| 7261 | <field> |
||
| 7262 | <name>MR27</name> |
||
| 7263 | <description>Event Mask on line 27</description> |
||
| 7264 | <bitOffset>27</bitOffset> |
||
| 7265 | <bitWidth>1</bitWidth> |
||
| 7266 | </field> |
||
| 7267 | </fields> |
||
| 7268 | </register> |
||
| 7269 | <register> |
||
| 7270 | <name>RTSR</name> |
||
| 7271 | <displayName>RTSR</displayName> |
||
| 7272 | <description>Rising Trigger selection register |
||
| 7273 | (EXTI_RTSR)</description> |
||
| 7274 | <addressOffset>0x8</addressOffset> |
||
| 7275 | <size>0x20</size> |
||
| 7276 | <access>read-write</access> |
||
| 7277 | <resetValue>0x00000000</resetValue> |
||
| 7278 | <fields> |
||
| 7279 | <field> |
||
| 7280 | <name>TR0</name> |
||
| 7281 | <description>Rising trigger event configuration of |
||
| 7282 | line 0</description> |
||
| 7283 | <bitOffset>0</bitOffset> |
||
| 7284 | <bitWidth>1</bitWidth> |
||
| 7285 | </field> |
||
| 7286 | <field> |
||
| 7287 | <name>TR1</name> |
||
| 7288 | <description>Rising trigger event configuration of |
||
| 7289 | line 1</description> |
||
| 7290 | <bitOffset>1</bitOffset> |
||
| 7291 | <bitWidth>1</bitWidth> |
||
| 7292 | </field> |
||
| 7293 | <field> |
||
| 7294 | <name>TR2</name> |
||
| 7295 | <description>Rising trigger event configuration of |
||
| 7296 | line 2</description> |
||
| 7297 | <bitOffset>2</bitOffset> |
||
| 7298 | <bitWidth>1</bitWidth> |
||
| 7299 | </field> |
||
| 7300 | <field> |
||
| 7301 | <name>TR3</name> |
||
| 7302 | <description>Rising trigger event configuration of |
||
| 7303 | line 3</description> |
||
| 7304 | <bitOffset>3</bitOffset> |
||
| 7305 | <bitWidth>1</bitWidth> |
||
| 7306 | </field> |
||
| 7307 | <field> |
||
| 7308 | <name>TR4</name> |
||
| 7309 | <description>Rising trigger event configuration of |
||
| 7310 | line 4</description> |
||
| 7311 | <bitOffset>4</bitOffset> |
||
| 7312 | <bitWidth>1</bitWidth> |
||
| 7313 | </field> |
||
| 7314 | <field> |
||
| 7315 | <name>TR5</name> |
||
| 7316 | <description>Rising trigger event configuration of |
||
| 7317 | line 5</description> |
||
| 7318 | <bitOffset>5</bitOffset> |
||
| 7319 | <bitWidth>1</bitWidth> |
||
| 7320 | </field> |
||
| 7321 | <field> |
||
| 7322 | <name>TR6</name> |
||
| 7323 | <description>Rising trigger event configuration of |
||
| 7324 | line 6</description> |
||
| 7325 | <bitOffset>6</bitOffset> |
||
| 7326 | <bitWidth>1</bitWidth> |
||
| 7327 | </field> |
||
| 7328 | <field> |
||
| 7329 | <name>TR7</name> |
||
| 7330 | <description>Rising trigger event configuration of |
||
| 7331 | line 7</description> |
||
| 7332 | <bitOffset>7</bitOffset> |
||
| 7333 | <bitWidth>1</bitWidth> |
||
| 7334 | </field> |
||
| 7335 | <field> |
||
| 7336 | <name>TR8</name> |
||
| 7337 | <description>Rising trigger event configuration of |
||
| 7338 | line 8</description> |
||
| 7339 | <bitOffset>8</bitOffset> |
||
| 7340 | <bitWidth>1</bitWidth> |
||
| 7341 | </field> |
||
| 7342 | <field> |
||
| 7343 | <name>TR9</name> |
||
| 7344 | <description>Rising trigger event configuration of |
||
| 7345 | line 9</description> |
||
| 7346 | <bitOffset>9</bitOffset> |
||
| 7347 | <bitWidth>1</bitWidth> |
||
| 7348 | </field> |
||
| 7349 | <field> |
||
| 7350 | <name>TR10</name> |
||
| 7351 | <description>Rising trigger event configuration of |
||
| 7352 | line 10</description> |
||
| 7353 | <bitOffset>10</bitOffset> |
||
| 7354 | <bitWidth>1</bitWidth> |
||
| 7355 | </field> |
||
| 7356 | <field> |
||
| 7357 | <name>TR11</name> |
||
| 7358 | <description>Rising trigger event configuration of |
||
| 7359 | line 11</description> |
||
| 7360 | <bitOffset>11</bitOffset> |
||
| 7361 | <bitWidth>1</bitWidth> |
||
| 7362 | </field> |
||
| 7363 | <field> |
||
| 7364 | <name>TR12</name> |
||
| 7365 | <description>Rising trigger event configuration of |
||
| 7366 | line 12</description> |
||
| 7367 | <bitOffset>12</bitOffset> |
||
| 7368 | <bitWidth>1</bitWidth> |
||
| 7369 | </field> |
||
| 7370 | <field> |
||
| 7371 | <name>TR13</name> |
||
| 7372 | <description>Rising trigger event configuration of |
||
| 7373 | line 13</description> |
||
| 7374 | <bitOffset>13</bitOffset> |
||
| 7375 | <bitWidth>1</bitWidth> |
||
| 7376 | </field> |
||
| 7377 | <field> |
||
| 7378 | <name>TR14</name> |
||
| 7379 | <description>Rising trigger event configuration of |
||
| 7380 | line 14</description> |
||
| 7381 | <bitOffset>14</bitOffset> |
||
| 7382 | <bitWidth>1</bitWidth> |
||
| 7383 | </field> |
||
| 7384 | <field> |
||
| 7385 | <name>TR15</name> |
||
| 7386 | <description>Rising trigger event configuration of |
||
| 7387 | line 15</description> |
||
| 7388 | <bitOffset>15</bitOffset> |
||
| 7389 | <bitWidth>1</bitWidth> |
||
| 7390 | </field> |
||
| 7391 | <field> |
||
| 7392 | <name>TR16</name> |
||
| 7393 | <description>Rising trigger event configuration of |
||
| 7394 | line 16</description> |
||
| 7395 | <bitOffset>16</bitOffset> |
||
| 7396 | <bitWidth>1</bitWidth> |
||
| 7397 | </field> |
||
| 7398 | <field> |
||
| 7399 | <name>TR17</name> |
||
| 7400 | <description>Rising trigger event configuration of |
||
| 7401 | line 17</description> |
||
| 7402 | <bitOffset>17</bitOffset> |
||
| 7403 | <bitWidth>1</bitWidth> |
||
| 7404 | </field> |
||
| 7405 | <field> |
||
| 7406 | <name>TR19</name> |
||
| 7407 | <description>Rising trigger event configuration of |
||
| 7408 | line 19</description> |
||
| 7409 | <bitOffset>19</bitOffset> |
||
| 7410 | <bitWidth>1</bitWidth> |
||
| 7411 | </field> |
||
| 7412 | </fields> |
||
| 7413 | </register> |
||
| 7414 | <register> |
||
| 7415 | <name>FTSR</name> |
||
| 7416 | <displayName>FTSR</displayName> |
||
| 7417 | <description>Falling Trigger selection register |
||
| 7418 | (EXTI_FTSR)</description> |
||
| 7419 | <addressOffset>0xC</addressOffset> |
||
| 7420 | <size>0x20</size> |
||
| 7421 | <access>read-write</access> |
||
| 7422 | <resetValue>0x00000000</resetValue> |
||
| 7423 | <fields> |
||
| 7424 | <field> |
||
| 7425 | <name>TR0</name> |
||
| 7426 | <description>Falling trigger event configuration of |
||
| 7427 | line 0</description> |
||
| 7428 | <bitOffset>0</bitOffset> |
||
| 7429 | <bitWidth>1</bitWidth> |
||
| 7430 | </field> |
||
| 7431 | <field> |
||
| 7432 | <name>TR1</name> |
||
| 7433 | <description>Falling trigger event configuration of |
||
| 7434 | line 1</description> |
||
| 7435 | <bitOffset>1</bitOffset> |
||
| 7436 | <bitWidth>1</bitWidth> |
||
| 7437 | </field> |
||
| 7438 | <field> |
||
| 7439 | <name>TR2</name> |
||
| 7440 | <description>Falling trigger event configuration of |
||
| 7441 | line 2</description> |
||
| 7442 | <bitOffset>2</bitOffset> |
||
| 7443 | <bitWidth>1</bitWidth> |
||
| 7444 | </field> |
||
| 7445 | <field> |
||
| 7446 | <name>TR3</name> |
||
| 7447 | <description>Falling trigger event configuration of |
||
| 7448 | line 3</description> |
||
| 7449 | <bitOffset>3</bitOffset> |
||
| 7450 | <bitWidth>1</bitWidth> |
||
| 7451 | </field> |
||
| 7452 | <field> |
||
| 7453 | <name>TR4</name> |
||
| 7454 | <description>Falling trigger event configuration of |
||
| 7455 | line 4</description> |
||
| 7456 | <bitOffset>4</bitOffset> |
||
| 7457 | <bitWidth>1</bitWidth> |
||
| 7458 | </field> |
||
| 7459 | <field> |
||
| 7460 | <name>TR5</name> |
||
| 7461 | <description>Falling trigger event configuration of |
||
| 7462 | line 5</description> |
||
| 7463 | <bitOffset>5</bitOffset> |
||
| 7464 | <bitWidth>1</bitWidth> |
||
| 7465 | </field> |
||
| 7466 | <field> |
||
| 7467 | <name>TR6</name> |
||
| 7468 | <description>Falling trigger event configuration of |
||
| 7469 | line 6</description> |
||
| 7470 | <bitOffset>6</bitOffset> |
||
| 7471 | <bitWidth>1</bitWidth> |
||
| 7472 | </field> |
||
| 7473 | <field> |
||
| 7474 | <name>TR7</name> |
||
| 7475 | <description>Falling trigger event configuration of |
||
| 7476 | line 7</description> |
||
| 7477 | <bitOffset>7</bitOffset> |
||
| 7478 | <bitWidth>1</bitWidth> |
||
| 7479 | </field> |
||
| 7480 | <field> |
||
| 7481 | <name>TR8</name> |
||
| 7482 | <description>Falling trigger event configuration of |
||
| 7483 | line 8</description> |
||
| 7484 | <bitOffset>8</bitOffset> |
||
| 7485 | <bitWidth>1</bitWidth> |
||
| 7486 | </field> |
||
| 7487 | <field> |
||
| 7488 | <name>TR9</name> |
||
| 7489 | <description>Falling trigger event configuration of |
||
| 7490 | line 9</description> |
||
| 7491 | <bitOffset>9</bitOffset> |
||
| 7492 | <bitWidth>1</bitWidth> |
||
| 7493 | </field> |
||
| 7494 | <field> |
||
| 7495 | <name>TR10</name> |
||
| 7496 | <description>Falling trigger event configuration of |
||
| 7497 | line 10</description> |
||
| 7498 | <bitOffset>10</bitOffset> |
||
| 7499 | <bitWidth>1</bitWidth> |
||
| 7500 | </field> |
||
| 7501 | <field> |
||
| 7502 | <name>TR11</name> |
||
| 7503 | <description>Falling trigger event configuration of |
||
| 7504 | line 11</description> |
||
| 7505 | <bitOffset>11</bitOffset> |
||
| 7506 | <bitWidth>1</bitWidth> |
||
| 7507 | </field> |
||
| 7508 | <field> |
||
| 7509 | <name>TR12</name> |
||
| 7510 | <description>Falling trigger event configuration of |
||
| 7511 | line 12</description> |
||
| 7512 | <bitOffset>12</bitOffset> |
||
| 7513 | <bitWidth>1</bitWidth> |
||
| 7514 | </field> |
||
| 7515 | <field> |
||
| 7516 | <name>TR13</name> |
||
| 7517 | <description>Falling trigger event configuration of |
||
| 7518 | line 13</description> |
||
| 7519 | <bitOffset>13</bitOffset> |
||
| 7520 | <bitWidth>1</bitWidth> |
||
| 7521 | </field> |
||
| 7522 | <field> |
||
| 7523 | <name>TR14</name> |
||
| 7524 | <description>Falling trigger event configuration of |
||
| 7525 | line 14</description> |
||
| 7526 | <bitOffset>14</bitOffset> |
||
| 7527 | <bitWidth>1</bitWidth> |
||
| 7528 | </field> |
||
| 7529 | <field> |
||
| 7530 | <name>TR15</name> |
||
| 7531 | <description>Falling trigger event configuration of |
||
| 7532 | line 15</description> |
||
| 7533 | <bitOffset>15</bitOffset> |
||
| 7534 | <bitWidth>1</bitWidth> |
||
| 7535 | </field> |
||
| 7536 | <field> |
||
| 7537 | <name>TR16</name> |
||
| 7538 | <description>Falling trigger event configuration of |
||
| 7539 | line 16</description> |
||
| 7540 | <bitOffset>16</bitOffset> |
||
| 7541 | <bitWidth>1</bitWidth> |
||
| 7542 | </field> |
||
| 7543 | <field> |
||
| 7544 | <name>TR17</name> |
||
| 7545 | <description>Falling trigger event configuration of |
||
| 7546 | line 17</description> |
||
| 7547 | <bitOffset>17</bitOffset> |
||
| 7548 | <bitWidth>1</bitWidth> |
||
| 7549 | </field> |
||
| 7550 | <field> |
||
| 7551 | <name>TR19</name> |
||
| 7552 | <description>Falling trigger event configuration of |
||
| 7553 | line 19</description> |
||
| 7554 | <bitOffset>19</bitOffset> |
||
| 7555 | <bitWidth>1</bitWidth> |
||
| 7556 | </field> |
||
| 7557 | </fields> |
||
| 7558 | </register> |
||
| 7559 | <register> |
||
| 7560 | <name>SWIER</name> |
||
| 7561 | <displayName>SWIER</displayName> |
||
| 7562 | <description>Software interrupt event register |
||
| 7563 | (EXTI_SWIER)</description> |
||
| 7564 | <addressOffset>0x10</addressOffset> |
||
| 7565 | <size>0x20</size> |
||
| 7566 | <access>read-write</access> |
||
| 7567 | <resetValue>0x00000000</resetValue> |
||
| 7568 | <fields> |
||
| 7569 | <field> |
||
| 7570 | <name>SWIER0</name> |
||
| 7571 | <description>Software Interrupt on line |
||
| 7572 | 0</description> |
||
| 7573 | <bitOffset>0</bitOffset> |
||
| 7574 | <bitWidth>1</bitWidth> |
||
| 7575 | </field> |
||
| 7576 | <field> |
||
| 7577 | <name>SWIER1</name> |
||
| 7578 | <description>Software Interrupt on line |
||
| 7579 | 1</description> |
||
| 7580 | <bitOffset>1</bitOffset> |
||
| 7581 | <bitWidth>1</bitWidth> |
||
| 7582 | </field> |
||
| 7583 | <field> |
||
| 7584 | <name>SWIER2</name> |
||
| 7585 | <description>Software Interrupt on line |
||
| 7586 | 2</description> |
||
| 7587 | <bitOffset>2</bitOffset> |
||
| 7588 | <bitWidth>1</bitWidth> |
||
| 7589 | </field> |
||
| 7590 | <field> |
||
| 7591 | <name>SWIER3</name> |
||
| 7592 | <description>Software Interrupt on line |
||
| 7593 | 3</description> |
||
| 7594 | <bitOffset>3</bitOffset> |
||
| 7595 | <bitWidth>1</bitWidth> |
||
| 7596 | </field> |
||
| 7597 | <field> |
||
| 7598 | <name>SWIER4</name> |
||
| 7599 | <description>Software Interrupt on line |
||
| 7600 | 4</description> |
||
| 7601 | <bitOffset>4</bitOffset> |
||
| 7602 | <bitWidth>1</bitWidth> |
||
| 7603 | </field> |
||
| 7604 | <field> |
||
| 7605 | <name>SWIER5</name> |
||
| 7606 | <description>Software Interrupt on line |
||
| 7607 | 5</description> |
||
| 7608 | <bitOffset>5</bitOffset> |
||
| 7609 | <bitWidth>1</bitWidth> |
||
| 7610 | </field> |
||
| 7611 | <field> |
||
| 7612 | <name>SWIER6</name> |
||
| 7613 | <description>Software Interrupt on line |
||
| 7614 | 6</description> |
||
| 7615 | <bitOffset>6</bitOffset> |
||
| 7616 | <bitWidth>1</bitWidth> |
||
| 7617 | </field> |
||
| 7618 | <field> |
||
| 7619 | <name>SWIER7</name> |
||
| 7620 | <description>Software Interrupt on line |
||
| 7621 | 7</description> |
||
| 7622 | <bitOffset>7</bitOffset> |
||
| 7623 | <bitWidth>1</bitWidth> |
||
| 7624 | </field> |
||
| 7625 | <field> |
||
| 7626 | <name>SWIER8</name> |
||
| 7627 | <description>Software Interrupt on line |
||
| 7628 | 8</description> |
||
| 7629 | <bitOffset>8</bitOffset> |
||
| 7630 | <bitWidth>1</bitWidth> |
||
| 7631 | </field> |
||
| 7632 | <field> |
||
| 7633 | <name>SWIER9</name> |
||
| 7634 | <description>Software Interrupt on line |
||
| 7635 | 9</description> |
||
| 7636 | <bitOffset>9</bitOffset> |
||
| 7637 | <bitWidth>1</bitWidth> |
||
| 7638 | </field> |
||
| 7639 | <field> |
||
| 7640 | <name>SWIER10</name> |
||
| 7641 | <description>Software Interrupt on line |
||
| 7642 | 10</description> |
||
| 7643 | <bitOffset>10</bitOffset> |
||
| 7644 | <bitWidth>1</bitWidth> |
||
| 7645 | </field> |
||
| 7646 | <field> |
||
| 7647 | <name>SWIER11</name> |
||
| 7648 | <description>Software Interrupt on line |
||
| 7649 | 11</description> |
||
| 7650 | <bitOffset>11</bitOffset> |
||
| 7651 | <bitWidth>1</bitWidth> |
||
| 7652 | </field> |
||
| 7653 | <field> |
||
| 7654 | <name>SWIER12</name> |
||
| 7655 | <description>Software Interrupt on line |
||
| 7656 | 12</description> |
||
| 7657 | <bitOffset>12</bitOffset> |
||
| 7658 | <bitWidth>1</bitWidth> |
||
| 7659 | </field> |
||
| 7660 | <field> |
||
| 7661 | <name>SWIER13</name> |
||
| 7662 | <description>Software Interrupt on line |
||
| 7663 | 13</description> |
||
| 7664 | <bitOffset>13</bitOffset> |
||
| 7665 | <bitWidth>1</bitWidth> |
||
| 7666 | </field> |
||
| 7667 | <field> |
||
| 7668 | <name>SWIER14</name> |
||
| 7669 | <description>Software Interrupt on line |
||
| 7670 | 14</description> |
||
| 7671 | <bitOffset>14</bitOffset> |
||
| 7672 | <bitWidth>1</bitWidth> |
||
| 7673 | </field> |
||
| 7674 | <field> |
||
| 7675 | <name>SWIER15</name> |
||
| 7676 | <description>Software Interrupt on line |
||
| 7677 | 15</description> |
||
| 7678 | <bitOffset>15</bitOffset> |
||
| 7679 | <bitWidth>1</bitWidth> |
||
| 7680 | </field> |
||
| 7681 | <field> |
||
| 7682 | <name>SWIER16</name> |
||
| 7683 | <description>Software Interrupt on line |
||
| 7684 | 16</description> |
||
| 7685 | <bitOffset>16</bitOffset> |
||
| 7686 | <bitWidth>1</bitWidth> |
||
| 7687 | </field> |
||
| 7688 | <field> |
||
| 7689 | <name>SWIER17</name> |
||
| 7690 | <description>Software Interrupt on line |
||
| 7691 | 17</description> |
||
| 7692 | <bitOffset>17</bitOffset> |
||
| 7693 | <bitWidth>1</bitWidth> |
||
| 7694 | </field> |
||
| 7695 | <field> |
||
| 7696 | <name>SWIER19</name> |
||
| 7697 | <description>Software Interrupt on line |
||
| 7698 | 19</description> |
||
| 7699 | <bitOffset>19</bitOffset> |
||
| 7700 | <bitWidth>1</bitWidth> |
||
| 7701 | </field> |
||
| 7702 | </fields> |
||
| 7703 | </register> |
||
| 7704 | <register> |
||
| 7705 | <name>PR</name> |
||
| 7706 | <displayName>PR</displayName> |
||
| 7707 | <description>Pending register (EXTI_PR)</description> |
||
| 7708 | <addressOffset>0x14</addressOffset> |
||
| 7709 | <size>0x20</size> |
||
| 7710 | <access>read-write</access> |
||
| 7711 | <resetValue>0x00000000</resetValue> |
||
| 7712 | <fields> |
||
| 7713 | <field> |
||
| 7714 | <name>PR0</name> |
||
| 7715 | <description>Pending bit 0</description> |
||
| 7716 | <bitOffset>0</bitOffset> |
||
| 7717 | <bitWidth>1</bitWidth> |
||
| 7718 | </field> |
||
| 7719 | <field> |
||
| 7720 | <name>PR1</name> |
||
| 7721 | <description>Pending bit 1</description> |
||
| 7722 | <bitOffset>1</bitOffset> |
||
| 7723 | <bitWidth>1</bitWidth> |
||
| 7724 | </field> |
||
| 7725 | <field> |
||
| 7726 | <name>PR2</name> |
||
| 7727 | <description>Pending bit 2</description> |
||
| 7728 | <bitOffset>2</bitOffset> |
||
| 7729 | <bitWidth>1</bitWidth> |
||
| 7730 | </field> |
||
| 7731 | <field> |
||
| 7732 | <name>PR3</name> |
||
| 7733 | <description>Pending bit 3</description> |
||
| 7734 | <bitOffset>3</bitOffset> |
||
| 7735 | <bitWidth>1</bitWidth> |
||
| 7736 | </field> |
||
| 7737 | <field> |
||
| 7738 | <name>PR4</name> |
||
| 7739 | <description>Pending bit 4</description> |
||
| 7740 | <bitOffset>4</bitOffset> |
||
| 7741 | <bitWidth>1</bitWidth> |
||
| 7742 | </field> |
||
| 7743 | <field> |
||
| 7744 | <name>PR5</name> |
||
| 7745 | <description>Pending bit 5</description> |
||
| 7746 | <bitOffset>5</bitOffset> |
||
| 7747 | <bitWidth>1</bitWidth> |
||
| 7748 | </field> |
||
| 7749 | <field> |
||
| 7750 | <name>PR6</name> |
||
| 7751 | <description>Pending bit 6</description> |
||
| 7752 | <bitOffset>6</bitOffset> |
||
| 7753 | <bitWidth>1</bitWidth> |
||
| 7754 | </field> |
||
| 7755 | <field> |
||
| 7756 | <name>PR7</name> |
||
| 7757 | <description>Pending bit 7</description> |
||
| 7758 | <bitOffset>7</bitOffset> |
||
| 7759 | <bitWidth>1</bitWidth> |
||
| 7760 | </field> |
||
| 7761 | <field> |
||
| 7762 | <name>PR8</name> |
||
| 7763 | <description>Pending bit 8</description> |
||
| 7764 | <bitOffset>8</bitOffset> |
||
| 7765 | <bitWidth>1</bitWidth> |
||
| 7766 | </field> |
||
| 7767 | <field> |
||
| 7768 | <name>PR9</name> |
||
| 7769 | <description>Pending bit 9</description> |
||
| 7770 | <bitOffset>9</bitOffset> |
||
| 7771 | <bitWidth>1</bitWidth> |
||
| 7772 | </field> |
||
| 7773 | <field> |
||
| 7774 | <name>PR10</name> |
||
| 7775 | <description>Pending bit 10</description> |
||
| 7776 | <bitOffset>10</bitOffset> |
||
| 7777 | <bitWidth>1</bitWidth> |
||
| 7778 | </field> |
||
| 7779 | <field> |
||
| 7780 | <name>PR11</name> |
||
| 7781 | <description>Pending bit 11</description> |
||
| 7782 | <bitOffset>11</bitOffset> |
||
| 7783 | <bitWidth>1</bitWidth> |
||
| 7784 | </field> |
||
| 7785 | <field> |
||
| 7786 | <name>PR12</name> |
||
| 7787 | <description>Pending bit 12</description> |
||
| 7788 | <bitOffset>12</bitOffset> |
||
| 7789 | <bitWidth>1</bitWidth> |
||
| 7790 | </field> |
||
| 7791 | <field> |
||
| 7792 | <name>PR13</name> |
||
| 7793 | <description>Pending bit 13</description> |
||
| 7794 | <bitOffset>13</bitOffset> |
||
| 7795 | <bitWidth>1</bitWidth> |
||
| 7796 | </field> |
||
| 7797 | <field> |
||
| 7798 | <name>PR14</name> |
||
| 7799 | <description>Pending bit 14</description> |
||
| 7800 | <bitOffset>14</bitOffset> |
||
| 7801 | <bitWidth>1</bitWidth> |
||
| 7802 | </field> |
||
| 7803 | <field> |
||
| 7804 | <name>PR15</name> |
||
| 7805 | <description>Pending bit 15</description> |
||
| 7806 | <bitOffset>15</bitOffset> |
||
| 7807 | <bitWidth>1</bitWidth> |
||
| 7808 | </field> |
||
| 7809 | <field> |
||
| 7810 | <name>PR16</name> |
||
| 7811 | <description>Pending bit 16</description> |
||
| 7812 | <bitOffset>16</bitOffset> |
||
| 7813 | <bitWidth>1</bitWidth> |
||
| 7814 | </field> |
||
| 7815 | <field> |
||
| 7816 | <name>PR17</name> |
||
| 7817 | <description>Pending bit 17</description> |
||
| 7818 | <bitOffset>17</bitOffset> |
||
| 7819 | <bitWidth>1</bitWidth> |
||
| 7820 | </field> |
||
| 7821 | <field> |
||
| 7822 | <name>PR19</name> |
||
| 7823 | <description>Pending bit 19</description> |
||
| 7824 | <bitOffset>19</bitOffset> |
||
| 7825 | <bitWidth>1</bitWidth> |
||
| 7826 | </field> |
||
| 7827 | </fields> |
||
| 7828 | </register> |
||
| 7829 | </registers> |
||
| 7830 | </peripheral> |
||
| 7831 | <peripheral> |
||
| 7832 | <name>NVIC</name> |
||
| 7833 | <description>Nested Vectored Interrupt |
||
| 7834 | Controller</description> |
||
| 7835 | <groupName>NVIC</groupName> |
||
| 7836 | <baseAddress>0xE000E100</baseAddress> |
||
| 7837 | <addressBlock> |
||
| 7838 | <offset>0x0</offset> |
||
| 7839 | <size>0x33D</size> |
||
| 7840 | <usage>registers</usage> |
||
| 7841 | </addressBlock> |
||
| 7842 | <interrupt> |
||
| 7843 | <name>TIM6_DAC</name> |
||
| 7844 | <description>TIM6 global interrupt and DAC underrun |
||
| 7845 | interrupt</description> |
||
| 7846 | <value>17</value> |
||
| 7847 | </interrupt> |
||
| 7848 | <registers> |
||
| 7849 | <register> |
||
| 7850 | <name>ISER</name> |
||
| 7851 | <displayName>ISER</displayName> |
||
| 7852 | <description>Interrupt Set Enable Register</description> |
||
| 7853 | <addressOffset>0x0</addressOffset> |
||
| 7854 | <size>0x20</size> |
||
| 7855 | <access>read-write</access> |
||
| 7856 | <resetValue>0x00000000</resetValue> |
||
| 7857 | <fields> |
||
| 7858 | <field> |
||
| 7859 | <name>SETENA</name> |
||
| 7860 | <description>SETENA</description> |
||
| 7861 | <bitOffset>0</bitOffset> |
||
| 7862 | <bitWidth>32</bitWidth> |
||
| 7863 | </field> |
||
| 7864 | </fields> |
||
| 7865 | </register> |
||
| 7866 | <register> |
||
| 7867 | <name>ICER</name> |
||
| 7868 | <displayName>ICER</displayName> |
||
| 7869 | <description>Interrupt Clear Enable |
||
| 7870 | Register</description> |
||
| 7871 | <addressOffset>0x80</addressOffset> |
||
| 7872 | <size>0x20</size> |
||
| 7873 | <access>read-write</access> |
||
| 7874 | <resetValue>0x00000000</resetValue> |
||
| 7875 | <fields> |
||
| 7876 | <field> |
||
| 7877 | <name>CLRENA</name> |
||
| 7878 | <description>CLRENA</description> |
||
| 7879 | <bitOffset>0</bitOffset> |
||
| 7880 | <bitWidth>32</bitWidth> |
||
| 7881 | </field> |
||
| 7882 | </fields> |
||
| 7883 | </register> |
||
| 7884 | <register> |
||
| 7885 | <name>ISPR</name> |
||
| 7886 | <displayName>ISPR</displayName> |
||
| 7887 | <description>Interrupt Set-Pending Register</description> |
||
| 7888 | <addressOffset>0x100</addressOffset> |
||
| 7889 | <size>0x20</size> |
||
| 7890 | <access>read-write</access> |
||
| 7891 | <resetValue>0x00000000</resetValue> |
||
| 7892 | <fields> |
||
| 7893 | <field> |
||
| 7894 | <name>SETPEND</name> |
||
| 7895 | <description>SETPEND</description> |
||
| 7896 | <bitOffset>0</bitOffset> |
||
| 7897 | <bitWidth>32</bitWidth> |
||
| 7898 | </field> |
||
| 7899 | </fields> |
||
| 7900 | </register> |
||
| 7901 | <register> |
||
| 7902 | <name>ICPR</name> |
||
| 7903 | <displayName>ICPR</displayName> |
||
| 7904 | <description>Interrupt Clear-Pending |
||
| 7905 | Register</description> |
||
| 7906 | <addressOffset>0x180</addressOffset> |
||
| 7907 | <size>0x20</size> |
||
| 7908 | <access>read-write</access> |
||
| 7909 | <resetValue>0x00000000</resetValue> |
||
| 7910 | <fields> |
||
| 7911 | <field> |
||
| 7912 | <name>CLRPEND</name> |
||
| 7913 | <description>CLRPEND</description> |
||
| 7914 | <bitOffset>0</bitOffset> |
||
| 7915 | <bitWidth>32</bitWidth> |
||
| 7916 | </field> |
||
| 7917 | </fields> |
||
| 7918 | </register> |
||
| 7919 | <register> |
||
| 7920 | <name>IPR0</name> |
||
| 7921 | <displayName>IPR0</displayName> |
||
| 7922 | <description>Interrupt Priority Register 0</description> |
||
| 7923 | <addressOffset>0x300</addressOffset> |
||
| 7924 | <size>0x20</size> |
||
| 7925 | <access>read-write</access> |
||
| 7926 | <resetValue>0x00000000</resetValue> |
||
| 7927 | <fields> |
||
| 7928 | <field> |
||
| 7929 | <name>PRI_00</name> |
||
| 7930 | <description>PRI_00</description> |
||
| 7931 | <bitOffset>6</bitOffset> |
||
| 7932 | <bitWidth>2</bitWidth> |
||
| 7933 | </field> |
||
| 7934 | <field> |
||
| 7935 | <name>PRI_01</name> |
||
| 7936 | <description>PRI_01</description> |
||
| 7937 | <bitOffset>14</bitOffset> |
||
| 7938 | <bitWidth>2</bitWidth> |
||
| 7939 | </field> |
||
| 7940 | <field> |
||
| 7941 | <name>PRI_02</name> |
||
| 7942 | <description>PRI_02</description> |
||
| 7943 | <bitOffset>22</bitOffset> |
||
| 7944 | <bitWidth>2</bitWidth> |
||
| 7945 | </field> |
||
| 7946 | <field> |
||
| 7947 | <name>PRI_03</name> |
||
| 7948 | <description>PRI_03</description> |
||
| 7949 | <bitOffset>30</bitOffset> |
||
| 7950 | <bitWidth>2</bitWidth> |
||
| 7951 | </field> |
||
| 7952 | </fields> |
||
| 7953 | </register> |
||
| 7954 | <register> |
||
| 7955 | <name>IPR1</name> |
||
| 7956 | <displayName>IPR1</displayName> |
||
| 7957 | <description>Interrupt Priority Register 1</description> |
||
| 7958 | <addressOffset>0x304</addressOffset> |
||
| 7959 | <size>0x20</size> |
||
| 7960 | <access>read-write</access> |
||
| 7961 | <resetValue>0x00000000</resetValue> |
||
| 7962 | <fields> |
||
| 7963 | <field> |
||
| 7964 | <name>PRI_40</name> |
||
| 7965 | <description>PRI_40</description> |
||
| 7966 | <bitOffset>6</bitOffset> |
||
| 7967 | <bitWidth>2</bitWidth> |
||
| 7968 | </field> |
||
| 7969 | <field> |
||
| 7970 | <name>PRI_41</name> |
||
| 7971 | <description>PRI_41</description> |
||
| 7972 | <bitOffset>14</bitOffset> |
||
| 7973 | <bitWidth>2</bitWidth> |
||
| 7974 | </field> |
||
| 7975 | <field> |
||
| 7976 | <name>PRI_42</name> |
||
| 7977 | <description>PRI_42</description> |
||
| 7978 | <bitOffset>22</bitOffset> |
||
| 7979 | <bitWidth>2</bitWidth> |
||
| 7980 | </field> |
||
| 7981 | <field> |
||
| 7982 | <name>PRI_43</name> |
||
| 7983 | <description>PRI_43</description> |
||
| 7984 | <bitOffset>30</bitOffset> |
||
| 7985 | <bitWidth>2</bitWidth> |
||
| 7986 | </field> |
||
| 7987 | </fields> |
||
| 7988 | </register> |
||
| 7989 | <register> |
||
| 7990 | <name>IPR2</name> |
||
| 7991 | <displayName>IPR2</displayName> |
||
| 7992 | <description>Interrupt Priority Register 2</description> |
||
| 7993 | <addressOffset>0x308</addressOffset> |
||
| 7994 | <size>0x20</size> |
||
| 7995 | <access>read-write</access> |
||
| 7996 | <resetValue>0x00000000</resetValue> |
||
| 7997 | <fields> |
||
| 7998 | <field> |
||
| 7999 | <name>PRI_80</name> |
||
| 8000 | <description>PRI_80</description> |
||
| 8001 | <bitOffset>6</bitOffset> |
||
| 8002 | <bitWidth>2</bitWidth> |
||
| 8003 | </field> |
||
| 8004 | <field> |
||
| 8005 | <name>PRI_81</name> |
||
| 8006 | <description>PRI_81</description> |
||
| 8007 | <bitOffset>14</bitOffset> |
||
| 8008 | <bitWidth>2</bitWidth> |
||
| 8009 | </field> |
||
| 8010 | <field> |
||
| 8011 | <name>PRI_82</name> |
||
| 8012 | <description>PRI_82</description> |
||
| 8013 | <bitOffset>22</bitOffset> |
||
| 8014 | <bitWidth>2</bitWidth> |
||
| 8015 | </field> |
||
| 8016 | <field> |
||
| 8017 | <name>PRI_83</name> |
||
| 8018 | <description>PRI_83</description> |
||
| 8019 | <bitOffset>30</bitOffset> |
||
| 8020 | <bitWidth>2</bitWidth> |
||
| 8021 | </field> |
||
| 8022 | </fields> |
||
| 8023 | </register> |
||
| 8024 | <register> |
||
| 8025 | <name>IPR3</name> |
||
| 8026 | <displayName>IPR3</displayName> |
||
| 8027 | <description>Interrupt Priority Register 3</description> |
||
| 8028 | <addressOffset>0x30C</addressOffset> |
||
| 8029 | <size>0x20</size> |
||
| 8030 | <access>read-write</access> |
||
| 8031 | <resetValue>0x00000000</resetValue> |
||
| 8032 | <fields> |
||
| 8033 | <field> |
||
| 8034 | <name>PRI_120</name> |
||
| 8035 | <description>PRI_120</description> |
||
| 8036 | <bitOffset>6</bitOffset> |
||
| 8037 | <bitWidth>2</bitWidth> |
||
| 8038 | </field> |
||
| 8039 | <field> |
||
| 8040 | <name>PRI_121</name> |
||
| 8041 | <description>PRI_121</description> |
||
| 8042 | <bitOffset>14</bitOffset> |
||
| 8043 | <bitWidth>2</bitWidth> |
||
| 8044 | </field> |
||
| 8045 | <field> |
||
| 8046 | <name>PRI_122</name> |
||
| 8047 | <description>PRI_122</description> |
||
| 8048 | <bitOffset>22</bitOffset> |
||
| 8049 | <bitWidth>2</bitWidth> |
||
| 8050 | </field> |
||
| 8051 | <field> |
||
| 8052 | <name>PRI_123</name> |
||
| 8053 | <description>PRI_123</description> |
||
| 8054 | <bitOffset>30</bitOffset> |
||
| 8055 | <bitWidth>2</bitWidth> |
||
| 8056 | </field> |
||
| 8057 | </fields> |
||
| 8058 | </register> |
||
| 8059 | <register> |
||
| 8060 | <name>IPR4</name> |
||
| 8061 | <displayName>IPR4</displayName> |
||
| 8062 | <description>Interrupt Priority Register 4</description> |
||
| 8063 | <addressOffset>0x310</addressOffset> |
||
| 8064 | <size>0x20</size> |
||
| 8065 | <access>read-write</access> |
||
| 8066 | <resetValue>0x00000000</resetValue> |
||
| 8067 | <fields> |
||
| 8068 | <field> |
||
| 8069 | <name>PRI_160</name> |
||
| 8070 | <description>PRI_160</description> |
||
| 8071 | <bitOffset>6</bitOffset> |
||
| 8072 | <bitWidth>2</bitWidth> |
||
| 8073 | </field> |
||
| 8074 | <field> |
||
| 8075 | <name>PRI_161</name> |
||
| 8076 | <description>PRI_161</description> |
||
| 8077 | <bitOffset>14</bitOffset> |
||
| 8078 | <bitWidth>2</bitWidth> |
||
| 8079 | </field> |
||
| 8080 | <field> |
||
| 8081 | <name>PRI_162</name> |
||
| 8082 | <description>PRI_162</description> |
||
| 8083 | <bitOffset>22</bitOffset> |
||
| 8084 | <bitWidth>2</bitWidth> |
||
| 8085 | </field> |
||
| 8086 | <field> |
||
| 8087 | <name>PRI_163</name> |
||
| 8088 | <description>PRI_163</description> |
||
| 8089 | <bitOffset>30</bitOffset> |
||
| 8090 | <bitWidth>2</bitWidth> |
||
| 8091 | </field> |
||
| 8092 | </fields> |
||
| 8093 | </register> |
||
| 8094 | <register> |
||
| 8095 | <name>IPR5</name> |
||
| 8096 | <displayName>IPR5</displayName> |
||
| 8097 | <description>Interrupt Priority Register 5</description> |
||
| 8098 | <addressOffset>0x314</addressOffset> |
||
| 8099 | <size>0x20</size> |
||
| 8100 | <access>read-write</access> |
||
| 8101 | <resetValue>0x00000000</resetValue> |
||
| 8102 | <fields> |
||
| 8103 | <field> |
||
| 8104 | <name>PRI_200</name> |
||
| 8105 | <description>PRI_200</description> |
||
| 8106 | <bitOffset>6</bitOffset> |
||
| 8107 | <bitWidth>2</bitWidth> |
||
| 8108 | </field> |
||
| 8109 | <field> |
||
| 8110 | <name>PRI_201</name> |
||
| 8111 | <description>PRI_201</description> |
||
| 8112 | <bitOffset>14</bitOffset> |
||
| 8113 | <bitWidth>2</bitWidth> |
||
| 8114 | </field> |
||
| 8115 | <field> |
||
| 8116 | <name>PRI_202</name> |
||
| 8117 | <description>PRI_202</description> |
||
| 8118 | <bitOffset>22</bitOffset> |
||
| 8119 | <bitWidth>2</bitWidth> |
||
| 8120 | </field> |
||
| 8121 | <field> |
||
| 8122 | <name>PRI_203</name> |
||
| 8123 | <description>PRI_203</description> |
||
| 8124 | <bitOffset>30</bitOffset> |
||
| 8125 | <bitWidth>2</bitWidth> |
||
| 8126 | </field> |
||
| 8127 | </fields> |
||
| 8128 | </register> |
||
| 8129 | <register> |
||
| 8130 | <name>IPR6</name> |
||
| 8131 | <displayName>IPR6</displayName> |
||
| 8132 | <description>Interrupt Priority Register 6</description> |
||
| 8133 | <addressOffset>0x318</addressOffset> |
||
| 8134 | <size>0x20</size> |
||
| 8135 | <access>read-write</access> |
||
| 8136 | <resetValue>0x00000000</resetValue> |
||
| 8137 | <fields> |
||
| 8138 | <field> |
||
| 8139 | <name>PRI_240</name> |
||
| 8140 | <description>PRI_240</description> |
||
| 8141 | <bitOffset>6</bitOffset> |
||
| 8142 | <bitWidth>2</bitWidth> |
||
| 8143 | </field> |
||
| 8144 | <field> |
||
| 8145 | <name>PRI_241</name> |
||
| 8146 | <description>PRI_241</description> |
||
| 8147 | <bitOffset>14</bitOffset> |
||
| 8148 | <bitWidth>2</bitWidth> |
||
| 8149 | </field> |
||
| 8150 | <field> |
||
| 8151 | <name>PRI_242</name> |
||
| 8152 | <description>PRI_242</description> |
||
| 8153 | <bitOffset>22</bitOffset> |
||
| 8154 | <bitWidth>2</bitWidth> |
||
| 8155 | </field> |
||
| 8156 | <field> |
||
| 8157 | <name>PRI_243</name> |
||
| 8158 | <description>PRI_243</description> |
||
| 8159 | <bitOffset>30</bitOffset> |
||
| 8160 | <bitWidth>2</bitWidth> |
||
| 8161 | </field> |
||
| 8162 | </fields> |
||
| 8163 | </register> |
||
| 8164 | <register> |
||
| 8165 | <name>IPR7</name> |
||
| 8166 | <displayName>IPR7</displayName> |
||
| 8167 | <description>Interrupt Priority Register 7</description> |
||
| 8168 | <addressOffset>0x31C</addressOffset> |
||
| 8169 | <size>0x20</size> |
||
| 8170 | <access>read-write</access> |
||
| 8171 | <resetValue>0x00000000</resetValue> |
||
| 8172 | <fields> |
||
| 8173 | <field> |
||
| 8174 | <name>PRI_280</name> |
||
| 8175 | <description>PRI_280</description> |
||
| 8176 | <bitOffset>6</bitOffset> |
||
| 8177 | <bitWidth>2</bitWidth> |
||
| 8178 | </field> |
||
| 8179 | <field> |
||
| 8180 | <name>PRI_281</name> |
||
| 8181 | <description>PRI_281</description> |
||
| 8182 | <bitOffset>14</bitOffset> |
||
| 8183 | <bitWidth>2</bitWidth> |
||
| 8184 | </field> |
||
| 8185 | <field> |
||
| 8186 | <name>PRI_282</name> |
||
| 8187 | <description>PRI_282</description> |
||
| 8188 | <bitOffset>22</bitOffset> |
||
| 8189 | <bitWidth>2</bitWidth> |
||
| 8190 | </field> |
||
| 8191 | <field> |
||
| 8192 | <name>PRI_283</name> |
||
| 8193 | <description>PRI_283</description> |
||
| 8194 | <bitOffset>30</bitOffset> |
||
| 8195 | <bitWidth>2</bitWidth> |
||
| 8196 | </field> |
||
| 8197 | </fields> |
||
| 8198 | </register> |
||
| 8199 | </registers> |
||
| 8200 | </peripheral> |
||
| 8201 | <peripheral> |
||
| 8202 | <name>DMA</name> |
||
| 8203 | <description>DMA controller</description> |
||
| 8204 | <groupName>DMA</groupName> |
||
| 8205 | <baseAddress>0x40020000</baseAddress> |
||
| 8206 | <addressBlock> |
||
| 8207 | <offset>0x0</offset> |
||
| 8208 | <size>0x400</size> |
||
| 8209 | <usage>registers</usage> |
||
| 8210 | </addressBlock> |
||
| 8211 | <interrupt> |
||
| 8212 | <name>TIM7</name> |
||
| 8213 | <description>TIM7 global interrupt</description> |
||
| 8214 | <value>18</value> |
||
| 8215 | </interrupt> |
||
| 8216 | <registers> |
||
| 8217 | <register> |
||
| 8218 | <name>ISR</name> |
||
| 8219 | <displayName>ISR</displayName> |
||
| 8220 | <description>DMA interrupt status register |
||
| 8221 | (DMA_ISR)</description> |
||
| 8222 | <addressOffset>0x0</addressOffset> |
||
| 8223 | <size>0x20</size> |
||
| 8224 | <access>read-only</access> |
||
| 8225 | <resetValue>0x00000000</resetValue> |
||
| 8226 | <fields> |
||
| 8227 | <field> |
||
| 8228 | <name>GIF1</name> |
||
| 8229 | <description>Channel 1 Global interrupt |
||
| 8230 | flag</description> |
||
| 8231 | <bitOffset>0</bitOffset> |
||
| 8232 | <bitWidth>1</bitWidth> |
||
| 8233 | </field> |
||
| 8234 | <field> |
||
| 8235 | <name>TCIF1</name> |
||
| 8236 | <description>Channel 1 Transfer Complete |
||
| 8237 | flag</description> |
||
| 8238 | <bitOffset>1</bitOffset> |
||
| 8239 | <bitWidth>1</bitWidth> |
||
| 8240 | </field> |
||
| 8241 | <field> |
||
| 8242 | <name>HTIF1</name> |
||
| 8243 | <description>Channel 1 Half Transfer Complete |
||
| 8244 | flag</description> |
||
| 8245 | <bitOffset>2</bitOffset> |
||
| 8246 | <bitWidth>1</bitWidth> |
||
| 8247 | </field> |
||
| 8248 | <field> |
||
| 8249 | <name>TEIF1</name> |
||
| 8250 | <description>Channel 1 Transfer Error |
||
| 8251 | flag</description> |
||
| 8252 | <bitOffset>3</bitOffset> |
||
| 8253 | <bitWidth>1</bitWidth> |
||
| 8254 | </field> |
||
| 8255 | <field> |
||
| 8256 | <name>GIF2</name> |
||
| 8257 | <description>Channel 2 Global interrupt |
||
| 8258 | flag</description> |
||
| 8259 | <bitOffset>4</bitOffset> |
||
| 8260 | <bitWidth>1</bitWidth> |
||
| 8261 | </field> |
||
| 8262 | <field> |
||
| 8263 | <name>TCIF2</name> |
||
| 8264 | <description>Channel 2 Transfer Complete |
||
| 8265 | flag</description> |
||
| 8266 | <bitOffset>5</bitOffset> |
||
| 8267 | <bitWidth>1</bitWidth> |
||
| 8268 | </field> |
||
| 8269 | <field> |
||
| 8270 | <name>HTIF2</name> |
||
| 8271 | <description>Channel 2 Half Transfer Complete |
||
| 8272 | flag</description> |
||
| 8273 | <bitOffset>6</bitOffset> |
||
| 8274 | <bitWidth>1</bitWidth> |
||
| 8275 | </field> |
||
| 8276 | <field> |
||
| 8277 | <name>TEIF2</name> |
||
| 8278 | <description>Channel 2 Transfer Error |
||
| 8279 | flag</description> |
||
| 8280 | <bitOffset>7</bitOffset> |
||
| 8281 | <bitWidth>1</bitWidth> |
||
| 8282 | </field> |
||
| 8283 | <field> |
||
| 8284 | <name>GIF3</name> |
||
| 8285 | <description>Channel 3 Global interrupt |
||
| 8286 | flag</description> |
||
| 8287 | <bitOffset>8</bitOffset> |
||
| 8288 | <bitWidth>1</bitWidth> |
||
| 8289 | </field> |
||
| 8290 | <field> |
||
| 8291 | <name>TCIF3</name> |
||
| 8292 | <description>Channel 3 Transfer Complete |
||
| 8293 | flag</description> |
||
| 8294 | <bitOffset>9</bitOffset> |
||
| 8295 | <bitWidth>1</bitWidth> |
||
| 8296 | </field> |
||
| 8297 | <field> |
||
| 8298 | <name>HTIF3</name> |
||
| 8299 | <description>Channel 3 Half Transfer Complete |
||
| 8300 | flag</description> |
||
| 8301 | <bitOffset>10</bitOffset> |
||
| 8302 | <bitWidth>1</bitWidth> |
||
| 8303 | </field> |
||
| 8304 | <field> |
||
| 8305 | <name>TEIF3</name> |
||
| 8306 | <description>Channel 3 Transfer Error |
||
| 8307 | flag</description> |
||
| 8308 | <bitOffset>11</bitOffset> |
||
| 8309 | <bitWidth>1</bitWidth> |
||
| 8310 | </field> |
||
| 8311 | <field> |
||
| 8312 | <name>GIF4</name> |
||
| 8313 | <description>Channel 4 Global interrupt |
||
| 8314 | flag</description> |
||
| 8315 | <bitOffset>12</bitOffset> |
||
| 8316 | <bitWidth>1</bitWidth> |
||
| 8317 | </field> |
||
| 8318 | <field> |
||
| 8319 | <name>TCIF4</name> |
||
| 8320 | <description>Channel 4 Transfer Complete |
||
| 8321 | flag</description> |
||
| 8322 | <bitOffset>13</bitOffset> |
||
| 8323 | <bitWidth>1</bitWidth> |
||
| 8324 | </field> |
||
| 8325 | <field> |
||
| 8326 | <name>HTIF4</name> |
||
| 8327 | <description>Channel 4 Half Transfer Complete |
||
| 8328 | flag</description> |
||
| 8329 | <bitOffset>14</bitOffset> |
||
| 8330 | <bitWidth>1</bitWidth> |
||
| 8331 | </field> |
||
| 8332 | <field> |
||
| 8333 | <name>TEIF4</name> |
||
| 8334 | <description>Channel 4 Transfer Error |
||
| 8335 | flag</description> |
||
| 8336 | <bitOffset>15</bitOffset> |
||
| 8337 | <bitWidth>1</bitWidth> |
||
| 8338 | </field> |
||
| 8339 | <field> |
||
| 8340 | <name>GIF5</name> |
||
| 8341 | <description>Channel 5 Global interrupt |
||
| 8342 | flag</description> |
||
| 8343 | <bitOffset>16</bitOffset> |
||
| 8344 | <bitWidth>1</bitWidth> |
||
| 8345 | </field> |
||
| 8346 | <field> |
||
| 8347 | <name>TCIF5</name> |
||
| 8348 | <description>Channel 5 Transfer Complete |
||
| 8349 | flag</description> |
||
| 8350 | <bitOffset>17</bitOffset> |
||
| 8351 | <bitWidth>1</bitWidth> |
||
| 8352 | </field> |
||
| 8353 | <field> |
||
| 8354 | <name>HTIF5</name> |
||
| 8355 | <description>Channel 5 Half Transfer Complete |
||
| 8356 | flag</description> |
||
| 8357 | <bitOffset>18</bitOffset> |
||
| 8358 | <bitWidth>1</bitWidth> |
||
| 8359 | </field> |
||
| 8360 | <field> |
||
| 8361 | <name>TEIF5</name> |
||
| 8362 | <description>Channel 5 Transfer Error |
||
| 8363 | flag</description> |
||
| 8364 | <bitOffset>19</bitOffset> |
||
| 8365 | <bitWidth>1</bitWidth> |
||
| 8366 | </field> |
||
| 8367 | <field> |
||
| 8368 | <name>GIF6</name> |
||
| 8369 | <description>Channel 6 Global interrupt |
||
| 8370 | flag</description> |
||
| 8371 | <bitOffset>20</bitOffset> |
||
| 8372 | <bitWidth>1</bitWidth> |
||
| 8373 | </field> |
||
| 8374 | <field> |
||
| 8375 | <name>TCIF6</name> |
||
| 8376 | <description>Channel 6 Transfer Complete |
||
| 8377 | flag</description> |
||
| 8378 | <bitOffset>21</bitOffset> |
||
| 8379 | <bitWidth>1</bitWidth> |
||
| 8380 | </field> |
||
| 8381 | <field> |
||
| 8382 | <name>HTIF6</name> |
||
| 8383 | <description>Channel 6 Half Transfer Complete |
||
| 8384 | flag</description> |
||
| 8385 | <bitOffset>22</bitOffset> |
||
| 8386 | <bitWidth>1</bitWidth> |
||
| 8387 | </field> |
||
| 8388 | <field> |
||
| 8389 | <name>TEIF6</name> |
||
| 8390 | <description>Channel 6 Transfer Error |
||
| 8391 | flag</description> |
||
| 8392 | <bitOffset>23</bitOffset> |
||
| 8393 | <bitWidth>1</bitWidth> |
||
| 8394 | </field> |
||
| 8395 | <field> |
||
| 8396 | <name>GIF7</name> |
||
| 8397 | <description>Channel 7 Global interrupt |
||
| 8398 | flag</description> |
||
| 8399 | <bitOffset>24</bitOffset> |
||
| 8400 | <bitWidth>1</bitWidth> |
||
| 8401 | </field> |
||
| 8402 | <field> |
||
| 8403 | <name>TCIF7</name> |
||
| 8404 | <description>Channel 7 Transfer Complete |
||
| 8405 | flag</description> |
||
| 8406 | <bitOffset>25</bitOffset> |
||
| 8407 | <bitWidth>1</bitWidth> |
||
| 8408 | </field> |
||
| 8409 | <field> |
||
| 8410 | <name>HTIF7</name> |
||
| 8411 | <description>Channel 7 Half Transfer Complete |
||
| 8412 | flag</description> |
||
| 8413 | <bitOffset>26</bitOffset> |
||
| 8414 | <bitWidth>1</bitWidth> |
||
| 8415 | </field> |
||
| 8416 | <field> |
||
| 8417 | <name>TEIF7</name> |
||
| 8418 | <description>Channel 7 Transfer Error |
||
| 8419 | flag</description> |
||
| 8420 | <bitOffset>27</bitOffset> |
||
| 8421 | <bitWidth>1</bitWidth> |
||
| 8422 | </field> |
||
| 8423 | </fields> |
||
| 8424 | </register> |
||
| 8425 | <register> |
||
| 8426 | <name>IFCR</name> |
||
| 8427 | <displayName>IFCR</displayName> |
||
| 8428 | <description>DMA interrupt flag clear register |
||
| 8429 | (DMA_IFCR)</description> |
||
| 8430 | <addressOffset>0x4</addressOffset> |
||
| 8431 | <size>0x20</size> |
||
| 8432 | <access>write-only</access> |
||
| 8433 | <resetValue>0x00000000</resetValue> |
||
| 8434 | <fields> |
||
| 8435 | <field> |
||
| 8436 | <name>CGIF1</name> |
||
| 8437 | <description>Channel 1 Global interrupt |
||
| 8438 | clear</description> |
||
| 8439 | <bitOffset>0</bitOffset> |
||
| 8440 | <bitWidth>1</bitWidth> |
||
| 8441 | </field> |
||
| 8442 | <field> |
||
| 8443 | <name>CTCIF1</name> |
||
| 8444 | <description>Channel 1 Transfer Complete |
||
| 8445 | clear</description> |
||
| 8446 | <bitOffset>1</bitOffset> |
||
| 8447 | <bitWidth>1</bitWidth> |
||
| 8448 | </field> |
||
| 8449 | <field> |
||
| 8450 | <name>CHTIF1</name> |
||
| 8451 | <description>Channel 1 Half Transfer |
||
| 8452 | clear</description> |
||
| 8453 | <bitOffset>2</bitOffset> |
||
| 8454 | <bitWidth>1</bitWidth> |
||
| 8455 | </field> |
||
| 8456 | <field> |
||
| 8457 | <name>CTEIF1</name> |
||
| 8458 | <description>Channel 1 Transfer Error |
||
| 8459 | clear</description> |
||
| 8460 | <bitOffset>3</bitOffset> |
||
| 8461 | <bitWidth>1</bitWidth> |
||
| 8462 | </field> |
||
| 8463 | <field> |
||
| 8464 | <name>CGIF2</name> |
||
| 8465 | <description>Channel 2 Global interrupt |
||
| 8466 | clear</description> |
||
| 8467 | <bitOffset>4</bitOffset> |
||
| 8468 | <bitWidth>1</bitWidth> |
||
| 8469 | </field> |
||
| 8470 | <field> |
||
| 8471 | <name>CTCIF2</name> |
||
| 8472 | <description>Channel 2 Transfer Complete |
||
| 8473 | clear</description> |
||
| 8474 | <bitOffset>5</bitOffset> |
||
| 8475 | <bitWidth>1</bitWidth> |
||
| 8476 | </field> |
||
| 8477 | <field> |
||
| 8478 | <name>CHTIF2</name> |
||
| 8479 | <description>Channel 2 Half Transfer |
||
| 8480 | clear</description> |
||
| 8481 | <bitOffset>6</bitOffset> |
||
| 8482 | <bitWidth>1</bitWidth> |
||
| 8483 | </field> |
||
| 8484 | <field> |
||
| 8485 | <name>CTEIF2</name> |
||
| 8486 | <description>Channel 2 Transfer Error |
||
| 8487 | clear</description> |
||
| 8488 | <bitOffset>7</bitOffset> |
||
| 8489 | <bitWidth>1</bitWidth> |
||
| 8490 | </field> |
||
| 8491 | <field> |
||
| 8492 | <name>CGIF3</name> |
||
| 8493 | <description>Channel 3 Global interrupt |
||
| 8494 | clear</description> |
||
| 8495 | <bitOffset>8</bitOffset> |
||
| 8496 | <bitWidth>1</bitWidth> |
||
| 8497 | </field> |
||
| 8498 | <field> |
||
| 8499 | <name>CTCIF3</name> |
||
| 8500 | <description>Channel 3 Transfer Complete |
||
| 8501 | clear</description> |
||
| 8502 | <bitOffset>9</bitOffset> |
||
| 8503 | <bitWidth>1</bitWidth> |
||
| 8504 | </field> |
||
| 8505 | <field> |
||
| 8506 | <name>CHTIF3</name> |
||
| 8507 | <description>Channel 3 Half Transfer |
||
| 8508 | clear</description> |
||
| 8509 | <bitOffset>10</bitOffset> |
||
| 8510 | <bitWidth>1</bitWidth> |
||
| 8511 | </field> |
||
| 8512 | <field> |
||
| 8513 | <name>CTEIF3</name> |
||
| 8514 | <description>Channel 3 Transfer Error |
||
| 8515 | clear</description> |
||
| 8516 | <bitOffset>11</bitOffset> |
||
| 8517 | <bitWidth>1</bitWidth> |
||
| 8518 | </field> |
||
| 8519 | <field> |
||
| 8520 | <name>CGIF4</name> |
||
| 8521 | <description>Channel 4 Global interrupt |
||
| 8522 | clear</description> |
||
| 8523 | <bitOffset>12</bitOffset> |
||
| 8524 | <bitWidth>1</bitWidth> |
||
| 8525 | </field> |
||
| 8526 | <field> |
||
| 8527 | <name>CTCIF4</name> |
||
| 8528 | <description>Channel 4 Transfer Complete |
||
| 8529 | clear</description> |
||
| 8530 | <bitOffset>13</bitOffset> |
||
| 8531 | <bitWidth>1</bitWidth> |
||
| 8532 | </field> |
||
| 8533 | <field> |
||
| 8534 | <name>CHTIF4</name> |
||
| 8535 | <description>Channel 4 Half Transfer |
||
| 8536 | clear</description> |
||
| 8537 | <bitOffset>14</bitOffset> |
||
| 8538 | <bitWidth>1</bitWidth> |
||
| 8539 | </field> |
||
| 8540 | <field> |
||
| 8541 | <name>CTEIF4</name> |
||
| 8542 | <description>Channel 4 Transfer Error |
||
| 8543 | clear</description> |
||
| 8544 | <bitOffset>15</bitOffset> |
||
| 8545 | <bitWidth>1</bitWidth> |
||
| 8546 | </field> |
||
| 8547 | <field> |
||
| 8548 | <name>CGIF5</name> |
||
| 8549 | <description>Channel 5 Global interrupt |
||
| 8550 | clear</description> |
||
| 8551 | <bitOffset>16</bitOffset> |
||
| 8552 | <bitWidth>1</bitWidth> |
||
| 8553 | </field> |
||
| 8554 | <field> |
||
| 8555 | <name>CTCIF5</name> |
||
| 8556 | <description>Channel 5 Transfer Complete |
||
| 8557 | clear</description> |
||
| 8558 | <bitOffset>17</bitOffset> |
||
| 8559 | <bitWidth>1</bitWidth> |
||
| 8560 | </field> |
||
| 8561 | <field> |
||
| 8562 | <name>CHTIF5</name> |
||
| 8563 | <description>Channel 5 Half Transfer |
||
| 8564 | clear</description> |
||
| 8565 | <bitOffset>18</bitOffset> |
||
| 8566 | <bitWidth>1</bitWidth> |
||
| 8567 | </field> |
||
| 8568 | <field> |
||
| 8569 | <name>CTEIF5</name> |
||
| 8570 | <description>Channel 5 Transfer Error |
||
| 8571 | clear</description> |
||
| 8572 | <bitOffset>19</bitOffset> |
||
| 8573 | <bitWidth>1</bitWidth> |
||
| 8574 | </field> |
||
| 8575 | <field> |
||
| 8576 | <name>CGIF6</name> |
||
| 8577 | <description>Channel 6 Global interrupt |
||
| 8578 | clear</description> |
||
| 8579 | <bitOffset>20</bitOffset> |
||
| 8580 | <bitWidth>1</bitWidth> |
||
| 8581 | </field> |
||
| 8582 | <field> |
||
| 8583 | <name>CTCIF6</name> |
||
| 8584 | <description>Channel 6 Transfer Complete |
||
| 8585 | clear</description> |
||
| 8586 | <bitOffset>21</bitOffset> |
||
| 8587 | <bitWidth>1</bitWidth> |
||
| 8588 | </field> |
||
| 8589 | <field> |
||
| 8590 | <name>CHTIF6</name> |
||
| 8591 | <description>Channel 6 Half Transfer |
||
| 8592 | clear</description> |
||
| 8593 | <bitOffset>22</bitOffset> |
||
| 8594 | <bitWidth>1</bitWidth> |
||
| 8595 | </field> |
||
| 8596 | <field> |
||
| 8597 | <name>CTEIF6</name> |
||
| 8598 | <description>Channel 6 Transfer Error |
||
| 8599 | clear</description> |
||
| 8600 | <bitOffset>23</bitOffset> |
||
| 8601 | <bitWidth>1</bitWidth> |
||
| 8602 | </field> |
||
| 8603 | <field> |
||
| 8604 | <name>CGIF7</name> |
||
| 8605 | <description>Channel 7 Global interrupt |
||
| 8606 | clear</description> |
||
| 8607 | <bitOffset>24</bitOffset> |
||
| 8608 | <bitWidth>1</bitWidth> |
||
| 8609 | </field> |
||
| 8610 | <field> |
||
| 8611 | <name>CTCIF7</name> |
||
| 8612 | <description>Channel 7 Transfer Complete |
||
| 8613 | clear</description> |
||
| 8614 | <bitOffset>25</bitOffset> |
||
| 8615 | <bitWidth>1</bitWidth> |
||
| 8616 | </field> |
||
| 8617 | <field> |
||
| 8618 | <name>CHTIF7</name> |
||
| 8619 | <description>Channel 7 Half Transfer |
||
| 8620 | clear</description> |
||
| 8621 | <bitOffset>26</bitOffset> |
||
| 8622 | <bitWidth>1</bitWidth> |
||
| 8623 | </field> |
||
| 8624 | <field> |
||
| 8625 | <name>CTEIF7</name> |
||
| 8626 | <description>Channel 7 Transfer Error |
||
| 8627 | clear</description> |
||
| 8628 | <bitOffset>27</bitOffset> |
||
| 8629 | <bitWidth>1</bitWidth> |
||
| 8630 | </field> |
||
| 8631 | </fields> |
||
| 8632 | </register> |
||
| 8633 | <register> |
||
| 8634 | <name>CCR1</name> |
||
| 8635 | <displayName>CCR1</displayName> |
||
| 8636 | <description>DMA channel configuration register |
||
| 8637 | (DMA_CCR)</description> |
||
| 8638 | <addressOffset>0x8</addressOffset> |
||
| 8639 | <size>0x20</size> |
||
| 8640 | <access>read-write</access> |
||
| 8641 | <resetValue>0x00000000</resetValue> |
||
| 8642 | <fields> |
||
| 8643 | <field> |
||
| 8644 | <name>EN</name> |
||
| 8645 | <description>Channel enable</description> |
||
| 8646 | <bitOffset>0</bitOffset> |
||
| 8647 | <bitWidth>1</bitWidth> |
||
| 8648 | </field> |
||
| 8649 | <field> |
||
| 8650 | <name>TCIE</name> |
||
| 8651 | <description>Transfer complete interrupt |
||
| 8652 | enable</description> |
||
| 8653 | <bitOffset>1</bitOffset> |
||
| 8654 | <bitWidth>1</bitWidth> |
||
| 8655 | </field> |
||
| 8656 | <field> |
||
| 8657 | <name>HTIE</name> |
||
| 8658 | <description>Half Transfer interrupt |
||
| 8659 | enable</description> |
||
| 8660 | <bitOffset>2</bitOffset> |
||
| 8661 | <bitWidth>1</bitWidth> |
||
| 8662 | </field> |
||
| 8663 | <field> |
||
| 8664 | <name>TEIE</name> |
||
| 8665 | <description>Transfer error interrupt |
||
| 8666 | enable</description> |
||
| 8667 | <bitOffset>3</bitOffset> |
||
| 8668 | <bitWidth>1</bitWidth> |
||
| 8669 | </field> |
||
| 8670 | <field> |
||
| 8671 | <name>DIR</name> |
||
| 8672 | <description>Data transfer direction</description> |
||
| 8673 | <bitOffset>4</bitOffset> |
||
| 8674 | <bitWidth>1</bitWidth> |
||
| 8675 | </field> |
||
| 8676 | <field> |
||
| 8677 | <name>CIRC</name> |
||
| 8678 | <description>Circular mode</description> |
||
| 8679 | <bitOffset>5</bitOffset> |
||
| 8680 | <bitWidth>1</bitWidth> |
||
| 8681 | </field> |
||
| 8682 | <field> |
||
| 8683 | <name>PINC</name> |
||
| 8684 | <description>Peripheral increment mode</description> |
||
| 8685 | <bitOffset>6</bitOffset> |
||
| 8686 | <bitWidth>1</bitWidth> |
||
| 8687 | </field> |
||
| 8688 | <field> |
||
| 8689 | <name>MINC</name> |
||
| 8690 | <description>Memory increment mode</description> |
||
| 8691 | <bitOffset>7</bitOffset> |
||
| 8692 | <bitWidth>1</bitWidth> |
||
| 8693 | </field> |
||
| 8694 | <field> |
||
| 8695 | <name>PSIZE</name> |
||
| 8696 | <description>Peripheral size</description> |
||
| 8697 | <bitOffset>8</bitOffset> |
||
| 8698 | <bitWidth>2</bitWidth> |
||
| 8699 | </field> |
||
| 8700 | <field> |
||
| 8701 | <name>MSIZE</name> |
||
| 8702 | <description>Memory size</description> |
||
| 8703 | <bitOffset>10</bitOffset> |
||
| 8704 | <bitWidth>2</bitWidth> |
||
| 8705 | </field> |
||
| 8706 | <field> |
||
| 8707 | <name>PL</name> |
||
| 8708 | <description>Channel Priority level</description> |
||
| 8709 | <bitOffset>12</bitOffset> |
||
| 8710 | <bitWidth>2</bitWidth> |
||
| 8711 | </field> |
||
| 8712 | <field> |
||
| 8713 | <name>MEM2MEM</name> |
||
| 8714 | <description>Memory to memory mode</description> |
||
| 8715 | <bitOffset>14</bitOffset> |
||
| 8716 | <bitWidth>1</bitWidth> |
||
| 8717 | </field> |
||
| 8718 | </fields> |
||
| 8719 | </register> |
||
| 8720 | <register> |
||
| 8721 | <name>CNDTR1</name> |
||
| 8722 | <displayName>CNDTR1</displayName> |
||
| 8723 | <description>DMA channel 1 number of data |
||
| 8724 | register</description> |
||
| 8725 | <addressOffset>0xC</addressOffset> |
||
| 8726 | <size>0x20</size> |
||
| 8727 | <access>read-write</access> |
||
| 8728 | <resetValue>0x00000000</resetValue> |
||
| 8729 | <fields> |
||
| 8730 | <field> |
||
| 8731 | <name>NDT</name> |
||
| 8732 | <description>Number of data to transfer</description> |
||
| 8733 | <bitOffset>0</bitOffset> |
||
| 8734 | <bitWidth>16</bitWidth> |
||
| 8735 | </field> |
||
| 8736 | </fields> |
||
| 8737 | </register> |
||
| 8738 | <register> |
||
| 8739 | <name>CPAR1</name> |
||
| 8740 | <displayName>CPAR1</displayName> |
||
| 8741 | <description>DMA channel 1 peripheral address |
||
| 8742 | register</description> |
||
| 8743 | <addressOffset>0x10</addressOffset> |
||
| 8744 | <size>0x20</size> |
||
| 8745 | <access>read-write</access> |
||
| 8746 | <resetValue>0x00000000</resetValue> |
||
| 8747 | <fields> |
||
| 8748 | <field> |
||
| 8749 | <name>PA</name> |
||
| 8750 | <description>Peripheral address</description> |
||
| 8751 | <bitOffset>0</bitOffset> |
||
| 8752 | <bitWidth>32</bitWidth> |
||
| 8753 | </field> |
||
| 8754 | </fields> |
||
| 8755 | </register> |
||
| 8756 | <register> |
||
| 8757 | <name>CMAR1</name> |
||
| 8758 | <displayName>CMAR1</displayName> |
||
| 8759 | <description>DMA channel 1 memory address |
||
| 8760 | register</description> |
||
| 8761 | <addressOffset>0x14</addressOffset> |
||
| 8762 | <size>0x20</size> |
||
| 8763 | <access>read-write</access> |
||
| 8764 | <resetValue>0x00000000</resetValue> |
||
| 8765 | <fields> |
||
| 8766 | <field> |
||
| 8767 | <name>MA</name> |
||
| 8768 | <description>Memory address</description> |
||
| 8769 | <bitOffset>0</bitOffset> |
||
| 8770 | <bitWidth>32</bitWidth> |
||
| 8771 | </field> |
||
| 8772 | </fields> |
||
| 8773 | </register> |
||
| 8774 | <register> |
||
| 8775 | <name>CCR2</name> |
||
| 8776 | <displayName>CCR2</displayName> |
||
| 8777 | <description>DMA channel configuration register |
||
| 8778 | (DMA_CCR)</description> |
||
| 8779 | <addressOffset>0x1C</addressOffset> |
||
| 8780 | <size>0x20</size> |
||
| 8781 | <access>read-write</access> |
||
| 8782 | <resetValue>0x00000000</resetValue> |
||
| 8783 | <fields> |
||
| 8784 | <field> |
||
| 8785 | <name>EN</name> |
||
| 8786 | <description>Channel enable</description> |
||
| 8787 | <bitOffset>0</bitOffset> |
||
| 8788 | <bitWidth>1</bitWidth> |
||
| 8789 | </field> |
||
| 8790 | <field> |
||
| 8791 | <name>TCIE</name> |
||
| 8792 | <description>Transfer complete interrupt |
||
| 8793 | enable</description> |
||
| 8794 | <bitOffset>1</bitOffset> |
||
| 8795 | <bitWidth>1</bitWidth> |
||
| 8796 | </field> |
||
| 8797 | <field> |
||
| 8798 | <name>HTIE</name> |
||
| 8799 | <description>Half Transfer interrupt |
||
| 8800 | enable</description> |
||
| 8801 | <bitOffset>2</bitOffset> |
||
| 8802 | <bitWidth>1</bitWidth> |
||
| 8803 | </field> |
||
| 8804 | <field> |
||
| 8805 | <name>TEIE</name> |
||
| 8806 | <description>Transfer error interrupt |
||
| 8807 | enable</description> |
||
| 8808 | <bitOffset>3</bitOffset> |
||
| 8809 | <bitWidth>1</bitWidth> |
||
| 8810 | </field> |
||
| 8811 | <field> |
||
| 8812 | <name>DIR</name> |
||
| 8813 | <description>Data transfer direction</description> |
||
| 8814 | <bitOffset>4</bitOffset> |
||
| 8815 | <bitWidth>1</bitWidth> |
||
| 8816 | </field> |
||
| 8817 | <field> |
||
| 8818 | <name>CIRC</name> |
||
| 8819 | <description>Circular mode</description> |
||
| 8820 | <bitOffset>5</bitOffset> |
||
| 8821 | <bitWidth>1</bitWidth> |
||
| 8822 | </field> |
||
| 8823 | <field> |
||
| 8824 | <name>PINC</name> |
||
| 8825 | <description>Peripheral increment mode</description> |
||
| 8826 | <bitOffset>6</bitOffset> |
||
| 8827 | <bitWidth>1</bitWidth> |
||
| 8828 | </field> |
||
| 8829 | <field> |
||
| 8830 | <name>MINC</name> |
||
| 8831 | <description>Memory increment mode</description> |
||
| 8832 | <bitOffset>7</bitOffset> |
||
| 8833 | <bitWidth>1</bitWidth> |
||
| 8834 | </field> |
||
| 8835 | <field> |
||
| 8836 | <name>PSIZE</name> |
||
| 8837 | <description>Peripheral size</description> |
||
| 8838 | <bitOffset>8</bitOffset> |
||
| 8839 | <bitWidth>2</bitWidth> |
||
| 8840 | </field> |
||
| 8841 | <field> |
||
| 8842 | <name>MSIZE</name> |
||
| 8843 | <description>Memory size</description> |
||
| 8844 | <bitOffset>10</bitOffset> |
||
| 8845 | <bitWidth>2</bitWidth> |
||
| 8846 | </field> |
||
| 8847 | <field> |
||
| 8848 | <name>PL</name> |
||
| 8849 | <description>Channel Priority level</description> |
||
| 8850 | <bitOffset>12</bitOffset> |
||
| 8851 | <bitWidth>2</bitWidth> |
||
| 8852 | </field> |
||
| 8853 | <field> |
||
| 8854 | <name>MEM2MEM</name> |
||
| 8855 | <description>Memory to memory mode</description> |
||
| 8856 | <bitOffset>14</bitOffset> |
||
| 8857 | <bitWidth>1</bitWidth> |
||
| 8858 | </field> |
||
| 8859 | </fields> |
||
| 8860 | </register> |
||
| 8861 | <register> |
||
| 8862 | <name>CNDTR2</name> |
||
| 8863 | <displayName>CNDTR2</displayName> |
||
| 8864 | <description>DMA channel 2 number of data |
||
| 8865 | register</description> |
||
| 8866 | <addressOffset>0x20</addressOffset> |
||
| 8867 | <size>0x20</size> |
||
| 8868 | <access>read-write</access> |
||
| 8869 | <resetValue>0x00000000</resetValue> |
||
| 8870 | <fields> |
||
| 8871 | <field> |
||
| 8872 | <name>NDT</name> |
||
| 8873 | <description>Number of data to transfer</description> |
||
| 8874 | <bitOffset>0</bitOffset> |
||
| 8875 | <bitWidth>16</bitWidth> |
||
| 8876 | </field> |
||
| 8877 | </fields> |
||
| 8878 | </register> |
||
| 8879 | <register> |
||
| 8880 | <name>CPAR2</name> |
||
| 8881 | <displayName>CPAR2</displayName> |
||
| 8882 | <description>DMA channel 2 peripheral address |
||
| 8883 | register</description> |
||
| 8884 | <addressOffset>0x24</addressOffset> |
||
| 8885 | <size>0x20</size> |
||
| 8886 | <access>read-write</access> |
||
| 8887 | <resetValue>0x00000000</resetValue> |
||
| 8888 | <fields> |
||
| 8889 | <field> |
||
| 8890 | <name>PA</name> |
||
| 8891 | <description>Peripheral address</description> |
||
| 8892 | <bitOffset>0</bitOffset> |
||
| 8893 | <bitWidth>32</bitWidth> |
||
| 8894 | </field> |
||
| 8895 | </fields> |
||
| 8896 | </register> |
||
| 8897 | <register> |
||
| 8898 | <name>CMAR2</name> |
||
| 8899 | <displayName>CMAR2</displayName> |
||
| 8900 | <description>DMA channel 2 memory address |
||
| 8901 | register</description> |
||
| 8902 | <addressOffset>0x28</addressOffset> |
||
| 8903 | <size>0x20</size> |
||
| 8904 | <access>read-write</access> |
||
| 8905 | <resetValue>0x00000000</resetValue> |
||
| 8906 | <fields> |
||
| 8907 | <field> |
||
| 8908 | <name>MA</name> |
||
| 8909 | <description>Memory address</description> |
||
| 8910 | <bitOffset>0</bitOffset> |
||
| 8911 | <bitWidth>32</bitWidth> |
||
| 8912 | </field> |
||
| 8913 | </fields> |
||
| 8914 | </register> |
||
| 8915 | <register> |
||
| 8916 | <name>CCR3</name> |
||
| 8917 | <displayName>CCR3</displayName> |
||
| 8918 | <description>DMA channel configuration register |
||
| 8919 | (DMA_CCR)</description> |
||
| 8920 | <addressOffset>0x30</addressOffset> |
||
| 8921 | <size>0x20</size> |
||
| 8922 | <access>read-write</access> |
||
| 8923 | <resetValue>0x00000000</resetValue> |
||
| 8924 | <fields> |
||
| 8925 | <field> |
||
| 8926 | <name>EN</name> |
||
| 8927 | <description>Channel enable</description> |
||
| 8928 | <bitOffset>0</bitOffset> |
||
| 8929 | <bitWidth>1</bitWidth> |
||
| 8930 | </field> |
||
| 8931 | <field> |
||
| 8932 | <name>TCIE</name> |
||
| 8933 | <description>Transfer complete interrupt |
||
| 8934 | enable</description> |
||
| 8935 | <bitOffset>1</bitOffset> |
||
| 8936 | <bitWidth>1</bitWidth> |
||
| 8937 | </field> |
||
| 8938 | <field> |
||
| 8939 | <name>HTIE</name> |
||
| 8940 | <description>Half Transfer interrupt |
||
| 8941 | enable</description> |
||
| 8942 | <bitOffset>2</bitOffset> |
||
| 8943 | <bitWidth>1</bitWidth> |
||
| 8944 | </field> |
||
| 8945 | <field> |
||
| 8946 | <name>TEIE</name> |
||
| 8947 | <description>Transfer error interrupt |
||
| 8948 | enable</description> |
||
| 8949 | <bitOffset>3</bitOffset> |
||
| 8950 | <bitWidth>1</bitWidth> |
||
| 8951 | </field> |
||
| 8952 | <field> |
||
| 8953 | <name>DIR</name> |
||
| 8954 | <description>Data transfer direction</description> |
||
| 8955 | <bitOffset>4</bitOffset> |
||
| 8956 | <bitWidth>1</bitWidth> |
||
| 8957 | </field> |
||
| 8958 | <field> |
||
| 8959 | <name>CIRC</name> |
||
| 8960 | <description>Circular mode</description> |
||
| 8961 | <bitOffset>5</bitOffset> |
||
| 8962 | <bitWidth>1</bitWidth> |
||
| 8963 | </field> |
||
| 8964 | <field> |
||
| 8965 | <name>PINC</name> |
||
| 8966 | <description>Peripheral increment mode</description> |
||
| 8967 | <bitOffset>6</bitOffset> |
||
| 8968 | <bitWidth>1</bitWidth> |
||
| 8969 | </field> |
||
| 8970 | <field> |
||
| 8971 | <name>MINC</name> |
||
| 8972 | <description>Memory increment mode</description> |
||
| 8973 | <bitOffset>7</bitOffset> |
||
| 8974 | <bitWidth>1</bitWidth> |
||
| 8975 | </field> |
||
| 8976 | <field> |
||
| 8977 | <name>PSIZE</name> |
||
| 8978 | <description>Peripheral size</description> |
||
| 8979 | <bitOffset>8</bitOffset> |
||
| 8980 | <bitWidth>2</bitWidth> |
||
| 8981 | </field> |
||
| 8982 | <field> |
||
| 8983 | <name>MSIZE</name> |
||
| 8984 | <description>Memory size</description> |
||
| 8985 | <bitOffset>10</bitOffset> |
||
| 8986 | <bitWidth>2</bitWidth> |
||
| 8987 | </field> |
||
| 8988 | <field> |
||
| 8989 | <name>PL</name> |
||
| 8990 | <description>Channel Priority level</description> |
||
| 8991 | <bitOffset>12</bitOffset> |
||
| 8992 | <bitWidth>2</bitWidth> |
||
| 8993 | </field> |
||
| 8994 | <field> |
||
| 8995 | <name>MEM2MEM</name> |
||
| 8996 | <description>Memory to memory mode</description> |
||
| 8997 | <bitOffset>14</bitOffset> |
||
| 8998 | <bitWidth>1</bitWidth> |
||
| 8999 | </field> |
||
| 9000 | </fields> |
||
| 9001 | </register> |
||
| 9002 | <register> |
||
| 9003 | <name>CNDTR3</name> |
||
| 9004 | <displayName>CNDTR3</displayName> |
||
| 9005 | <description>DMA channel 3 number of data |
||
| 9006 | register</description> |
||
| 9007 | <addressOffset>0x34</addressOffset> |
||
| 9008 | <size>0x20</size> |
||
| 9009 | <access>read-write</access> |
||
| 9010 | <resetValue>0x00000000</resetValue> |
||
| 9011 | <fields> |
||
| 9012 | <field> |
||
| 9013 | <name>NDT</name> |
||
| 9014 | <description>Number of data to transfer</description> |
||
| 9015 | <bitOffset>0</bitOffset> |
||
| 9016 | <bitWidth>16</bitWidth> |
||
| 9017 | </field> |
||
| 9018 | </fields> |
||
| 9019 | </register> |
||
| 9020 | <register> |
||
| 9021 | <name>CPAR3</name> |
||
| 9022 | <displayName>CPAR3</displayName> |
||
| 9023 | <description>DMA channel 3 peripheral address |
||
| 9024 | register</description> |
||
| 9025 | <addressOffset>0x38</addressOffset> |
||
| 9026 | <size>0x20</size> |
||
| 9027 | <access>read-write</access> |
||
| 9028 | <resetValue>0x00000000</resetValue> |
||
| 9029 | <fields> |
||
| 9030 | <field> |
||
| 9031 | <name>PA</name> |
||
| 9032 | <description>Peripheral address</description> |
||
| 9033 | <bitOffset>0</bitOffset> |
||
| 9034 | <bitWidth>32</bitWidth> |
||
| 9035 | </field> |
||
| 9036 | </fields> |
||
| 9037 | </register> |
||
| 9038 | <register> |
||
| 9039 | <name>CMAR3</name> |
||
| 9040 | <displayName>CMAR3</displayName> |
||
| 9041 | <description>DMA channel 3 memory address |
||
| 9042 | register</description> |
||
| 9043 | <addressOffset>0x3C</addressOffset> |
||
| 9044 | <size>0x20</size> |
||
| 9045 | <access>read-write</access> |
||
| 9046 | <resetValue>0x00000000</resetValue> |
||
| 9047 | <fields> |
||
| 9048 | <field> |
||
| 9049 | <name>MA</name> |
||
| 9050 | <description>Memory address</description> |
||
| 9051 | <bitOffset>0</bitOffset> |
||
| 9052 | <bitWidth>32</bitWidth> |
||
| 9053 | </field> |
||
| 9054 | </fields> |
||
| 9055 | </register> |
||
| 9056 | <register> |
||
| 9057 | <name>CCR4</name> |
||
| 9058 | <displayName>CCR4</displayName> |
||
| 9059 | <description>DMA channel configuration register |
||
| 9060 | (DMA_CCR)</description> |
||
| 9061 | <addressOffset>0x44</addressOffset> |
||
| 9062 | <size>0x20</size> |
||
| 9063 | <access>read-write</access> |
||
| 9064 | <resetValue>0x00000000</resetValue> |
||
| 9065 | <fields> |
||
| 9066 | <field> |
||
| 9067 | <name>EN</name> |
||
| 9068 | <description>Channel enable</description> |
||
| 9069 | <bitOffset>0</bitOffset> |
||
| 9070 | <bitWidth>1</bitWidth> |
||
| 9071 | </field> |
||
| 9072 | <field> |
||
| 9073 | <name>TCIE</name> |
||
| 9074 | <description>Transfer complete interrupt |
||
| 9075 | enable</description> |
||
| 9076 | <bitOffset>1</bitOffset> |
||
| 9077 | <bitWidth>1</bitWidth> |
||
| 9078 | </field> |
||
| 9079 | <field> |
||
| 9080 | <name>HTIE</name> |
||
| 9081 | <description>Half Transfer interrupt |
||
| 9082 | enable</description> |
||
| 9083 | <bitOffset>2</bitOffset> |
||
| 9084 | <bitWidth>1</bitWidth> |
||
| 9085 | </field> |
||
| 9086 | <field> |
||
| 9087 | <name>TEIE</name> |
||
| 9088 | <description>Transfer error interrupt |
||
| 9089 | enable</description> |
||
| 9090 | <bitOffset>3</bitOffset> |
||
| 9091 | <bitWidth>1</bitWidth> |
||
| 9092 | </field> |
||
| 9093 | <field> |
||
| 9094 | <name>DIR</name> |
||
| 9095 | <description>Data transfer direction</description> |
||
| 9096 | <bitOffset>4</bitOffset> |
||
| 9097 | <bitWidth>1</bitWidth> |
||
| 9098 | </field> |
||
| 9099 | <field> |
||
| 9100 | <name>CIRC</name> |
||
| 9101 | <description>Circular mode</description> |
||
| 9102 | <bitOffset>5</bitOffset> |
||
| 9103 | <bitWidth>1</bitWidth> |
||
| 9104 | </field> |
||
| 9105 | <field> |
||
| 9106 | <name>PINC</name> |
||
| 9107 | <description>Peripheral increment mode</description> |
||
| 9108 | <bitOffset>6</bitOffset> |
||
| 9109 | <bitWidth>1</bitWidth> |
||
| 9110 | </field> |
||
| 9111 | <field> |
||
| 9112 | <name>MINC</name> |
||
| 9113 | <description>Memory increment mode</description> |
||
| 9114 | <bitOffset>7</bitOffset> |
||
| 9115 | <bitWidth>1</bitWidth> |
||
| 9116 | </field> |
||
| 9117 | <field> |
||
| 9118 | <name>PSIZE</name> |
||
| 9119 | <description>Peripheral size</description> |
||
| 9120 | <bitOffset>8</bitOffset> |
||
| 9121 | <bitWidth>2</bitWidth> |
||
| 9122 | </field> |
||
| 9123 | <field> |
||
| 9124 | <name>MSIZE</name> |
||
| 9125 | <description>Memory size</description> |
||
| 9126 | <bitOffset>10</bitOffset> |
||
| 9127 | <bitWidth>2</bitWidth> |
||
| 9128 | </field> |
||
| 9129 | <field> |
||
| 9130 | <name>PL</name> |
||
| 9131 | <description>Channel Priority level</description> |
||
| 9132 | <bitOffset>12</bitOffset> |
||
| 9133 | <bitWidth>2</bitWidth> |
||
| 9134 | </field> |
||
| 9135 | <field> |
||
| 9136 | <name>MEM2MEM</name> |
||
| 9137 | <description>Memory to memory mode</description> |
||
| 9138 | <bitOffset>14</bitOffset> |
||
| 9139 | <bitWidth>1</bitWidth> |
||
| 9140 | </field> |
||
| 9141 | </fields> |
||
| 9142 | </register> |
||
| 9143 | <register> |
||
| 9144 | <name>CNDTR4</name> |
||
| 9145 | <displayName>CNDTR4</displayName> |
||
| 9146 | <description>DMA channel 4 number of data |
||
| 9147 | register</description> |
||
| 9148 | <addressOffset>0x48</addressOffset> |
||
| 9149 | <size>0x20</size> |
||
| 9150 | <access>read-write</access> |
||
| 9151 | <resetValue>0x00000000</resetValue> |
||
| 9152 | <fields> |
||
| 9153 | <field> |
||
| 9154 | <name>NDT</name> |
||
| 9155 | <description>Number of data to transfer</description> |
||
| 9156 | <bitOffset>0</bitOffset> |
||
| 9157 | <bitWidth>16</bitWidth> |
||
| 9158 | </field> |
||
| 9159 | </fields> |
||
| 9160 | </register> |
||
| 9161 | <register> |
||
| 9162 | <name>CPAR4</name> |
||
| 9163 | <displayName>CPAR4</displayName> |
||
| 9164 | <description>DMA channel 4 peripheral address |
||
| 9165 | register</description> |
||
| 9166 | <addressOffset>0x4C</addressOffset> |
||
| 9167 | <size>0x20</size> |
||
| 9168 | <access>read-write</access> |
||
| 9169 | <resetValue>0x00000000</resetValue> |
||
| 9170 | <fields> |
||
| 9171 | <field> |
||
| 9172 | <name>PA</name> |
||
| 9173 | <description>Peripheral address</description> |
||
| 9174 | <bitOffset>0</bitOffset> |
||
| 9175 | <bitWidth>32</bitWidth> |
||
| 9176 | </field> |
||
| 9177 | </fields> |
||
| 9178 | </register> |
||
| 9179 | <register> |
||
| 9180 | <name>CMAR4</name> |
||
| 9181 | <displayName>CMAR4</displayName> |
||
| 9182 | <description>DMA channel 4 memory address |
||
| 9183 | register</description> |
||
| 9184 | <addressOffset>0x50</addressOffset> |
||
| 9185 | <size>0x20</size> |
||
| 9186 | <access>read-write</access> |
||
| 9187 | <resetValue>0x00000000</resetValue> |
||
| 9188 | <fields> |
||
| 9189 | <field> |
||
| 9190 | <name>MA</name> |
||
| 9191 | <description>Memory address</description> |
||
| 9192 | <bitOffset>0</bitOffset> |
||
| 9193 | <bitWidth>32</bitWidth> |
||
| 9194 | </field> |
||
| 9195 | </fields> |
||
| 9196 | </register> |
||
| 9197 | <register> |
||
| 9198 | <name>CCR5</name> |
||
| 9199 | <displayName>CCR5</displayName> |
||
| 9200 | <description>DMA channel configuration register |
||
| 9201 | (DMA_CCR)</description> |
||
| 9202 | <addressOffset>0x58</addressOffset> |
||
| 9203 | <size>0x20</size> |
||
| 9204 | <access>read-write</access> |
||
| 9205 | <resetValue>0x00000000</resetValue> |
||
| 9206 | <fields> |
||
| 9207 | <field> |
||
| 9208 | <name>EN</name> |
||
| 9209 | <description>Channel enable</description> |
||
| 9210 | <bitOffset>0</bitOffset> |
||
| 9211 | <bitWidth>1</bitWidth> |
||
| 9212 | </field> |
||
| 9213 | <field> |
||
| 9214 | <name>TCIE</name> |
||
| 9215 | <description>Transfer complete interrupt |
||
| 9216 | enable</description> |
||
| 9217 | <bitOffset>1</bitOffset> |
||
| 9218 | <bitWidth>1</bitWidth> |
||
| 9219 | </field> |
||
| 9220 | <field> |
||
| 9221 | <name>HTIE</name> |
||
| 9222 | <description>Half Transfer interrupt |
||
| 9223 | enable</description> |
||
| 9224 | <bitOffset>2</bitOffset> |
||
| 9225 | <bitWidth>1</bitWidth> |
||
| 9226 | </field> |
||
| 9227 | <field> |
||
| 9228 | <name>TEIE</name> |
||
| 9229 | <description>Transfer error interrupt |
||
| 9230 | enable</description> |
||
| 9231 | <bitOffset>3</bitOffset> |
||
| 9232 | <bitWidth>1</bitWidth> |
||
| 9233 | </field> |
||
| 9234 | <field> |
||
| 9235 | <name>DIR</name> |
||
| 9236 | <description>Data transfer direction</description> |
||
| 9237 | <bitOffset>4</bitOffset> |
||
| 9238 | <bitWidth>1</bitWidth> |
||
| 9239 | </field> |
||
| 9240 | <field> |
||
| 9241 | <name>CIRC</name> |
||
| 9242 | <description>Circular mode</description> |
||
| 9243 | <bitOffset>5</bitOffset> |
||
| 9244 | <bitWidth>1</bitWidth> |
||
| 9245 | </field> |
||
| 9246 | <field> |
||
| 9247 | <name>PINC</name> |
||
| 9248 | <description>Peripheral increment mode</description> |
||
| 9249 | <bitOffset>6</bitOffset> |
||
| 9250 | <bitWidth>1</bitWidth> |
||
| 9251 | </field> |
||
| 9252 | <field> |
||
| 9253 | <name>MINC</name> |
||
| 9254 | <description>Memory increment mode</description> |
||
| 9255 | <bitOffset>7</bitOffset> |
||
| 9256 | <bitWidth>1</bitWidth> |
||
| 9257 | </field> |
||
| 9258 | <field> |
||
| 9259 | <name>PSIZE</name> |
||
| 9260 | <description>Peripheral size</description> |
||
| 9261 | <bitOffset>8</bitOffset> |
||
| 9262 | <bitWidth>2</bitWidth> |
||
| 9263 | </field> |
||
| 9264 | <field> |
||
| 9265 | <name>MSIZE</name> |
||
| 9266 | <description>Memory size</description> |
||
| 9267 | <bitOffset>10</bitOffset> |
||
| 9268 | <bitWidth>2</bitWidth> |
||
| 9269 | </field> |
||
| 9270 | <field> |
||
| 9271 | <name>PL</name> |
||
| 9272 | <description>Channel Priority level</description> |
||
| 9273 | <bitOffset>12</bitOffset> |
||
| 9274 | <bitWidth>2</bitWidth> |
||
| 9275 | </field> |
||
| 9276 | <field> |
||
| 9277 | <name>MEM2MEM</name> |
||
| 9278 | <description>Memory to memory mode</description> |
||
| 9279 | <bitOffset>14</bitOffset> |
||
| 9280 | <bitWidth>1</bitWidth> |
||
| 9281 | </field> |
||
| 9282 | </fields> |
||
| 9283 | </register> |
||
| 9284 | <register> |
||
| 9285 | <name>CNDTR5</name> |
||
| 9286 | <displayName>CNDTR5</displayName> |
||
| 9287 | <description>DMA channel 5 number of data |
||
| 9288 | register</description> |
||
| 9289 | <addressOffset>0x5C</addressOffset> |
||
| 9290 | <size>0x20</size> |
||
| 9291 | <access>read-write</access> |
||
| 9292 | <resetValue>0x00000000</resetValue> |
||
| 9293 | <fields> |
||
| 9294 | <field> |
||
| 9295 | <name>NDT</name> |
||
| 9296 | <description>Number of data to transfer</description> |
||
| 9297 | <bitOffset>0</bitOffset> |
||
| 9298 | <bitWidth>16</bitWidth> |
||
| 9299 | </field> |
||
| 9300 | </fields> |
||
| 9301 | </register> |
||
| 9302 | <register> |
||
| 9303 | <name>CPAR5</name> |
||
| 9304 | <displayName>CPAR5</displayName> |
||
| 9305 | <description>DMA channel 5 peripheral address |
||
| 9306 | register</description> |
||
| 9307 | <addressOffset>0x60</addressOffset> |
||
| 9308 | <size>0x20</size> |
||
| 9309 | <access>read-write</access> |
||
| 9310 | <resetValue>0x00000000</resetValue> |
||
| 9311 | <fields> |
||
| 9312 | <field> |
||
| 9313 | <name>PA</name> |
||
| 9314 | <description>Peripheral address</description> |
||
| 9315 | <bitOffset>0</bitOffset> |
||
| 9316 | <bitWidth>32</bitWidth> |
||
| 9317 | </field> |
||
| 9318 | </fields> |
||
| 9319 | </register> |
||
| 9320 | <register> |
||
| 9321 | <name>CMAR5</name> |
||
| 9322 | <displayName>CMAR5</displayName> |
||
| 9323 | <description>DMA channel 5 memory address |
||
| 9324 | register</description> |
||
| 9325 | <addressOffset>0x64</addressOffset> |
||
| 9326 | <size>0x20</size> |
||
| 9327 | <access>read-write</access> |
||
| 9328 | <resetValue>0x00000000</resetValue> |
||
| 9329 | <fields> |
||
| 9330 | <field> |
||
| 9331 | <name>MA</name> |
||
| 9332 | <description>Memory address</description> |
||
| 9333 | <bitOffset>0</bitOffset> |
||
| 9334 | <bitWidth>32</bitWidth> |
||
| 9335 | </field> |
||
| 9336 | </fields> |
||
| 9337 | </register> |
||
| 9338 | <register> |
||
| 9339 | <name>CCR6</name> |
||
| 9340 | <displayName>CCR6</displayName> |
||
| 9341 | <description>DMA channel configuration register |
||
| 9342 | (DMA_CCR)</description> |
||
| 9343 | <addressOffset>0x6C</addressOffset> |
||
| 9344 | <size>0x20</size> |
||
| 9345 | <access>read-write</access> |
||
| 9346 | <resetValue>0x00000000</resetValue> |
||
| 9347 | <fields> |
||
| 9348 | <field> |
||
| 9349 | <name>EN</name> |
||
| 9350 | <description>Channel enable</description> |
||
| 9351 | <bitOffset>0</bitOffset> |
||
| 9352 | <bitWidth>1</bitWidth> |
||
| 9353 | </field> |
||
| 9354 | <field> |
||
| 9355 | <name>TCIE</name> |
||
| 9356 | <description>Transfer complete interrupt |
||
| 9357 | enable</description> |
||
| 9358 | <bitOffset>1</bitOffset> |
||
| 9359 | <bitWidth>1</bitWidth> |
||
| 9360 | </field> |
||
| 9361 | <field> |
||
| 9362 | <name>HTIE</name> |
||
| 9363 | <description>Half Transfer interrupt |
||
| 9364 | enable</description> |
||
| 9365 | <bitOffset>2</bitOffset> |
||
| 9366 | <bitWidth>1</bitWidth> |
||
| 9367 | </field> |
||
| 9368 | <field> |
||
| 9369 | <name>TEIE</name> |
||
| 9370 | <description>Transfer error interrupt |
||
| 9371 | enable</description> |
||
| 9372 | <bitOffset>3</bitOffset> |
||
| 9373 | <bitWidth>1</bitWidth> |
||
| 9374 | </field> |
||
| 9375 | <field> |
||
| 9376 | <name>DIR</name> |
||
| 9377 | <description>Data transfer direction</description> |
||
| 9378 | <bitOffset>4</bitOffset> |
||
| 9379 | <bitWidth>1</bitWidth> |
||
| 9380 | </field> |
||
| 9381 | <field> |
||
| 9382 | <name>CIRC</name> |
||
| 9383 | <description>Circular mode</description> |
||
| 9384 | <bitOffset>5</bitOffset> |
||
| 9385 | <bitWidth>1</bitWidth> |
||
| 9386 | </field> |
||
| 9387 | <field> |
||
| 9388 | <name>PINC</name> |
||
| 9389 | <description>Peripheral increment mode</description> |
||
| 9390 | <bitOffset>6</bitOffset> |
||
| 9391 | <bitWidth>1</bitWidth> |
||
| 9392 | </field> |
||
| 9393 | <field> |
||
| 9394 | <name>MINC</name> |
||
| 9395 | <description>Memory increment mode</description> |
||
| 9396 | <bitOffset>7</bitOffset> |
||
| 9397 | <bitWidth>1</bitWidth> |
||
| 9398 | </field> |
||
| 9399 | <field> |
||
| 9400 | <name>PSIZE</name> |
||
| 9401 | <description>Peripheral size</description> |
||
| 9402 | <bitOffset>8</bitOffset> |
||
| 9403 | <bitWidth>2</bitWidth> |
||
| 9404 | </field> |
||
| 9405 | <field> |
||
| 9406 | <name>MSIZE</name> |
||
| 9407 | <description>Memory size</description> |
||
| 9408 | <bitOffset>10</bitOffset> |
||
| 9409 | <bitWidth>2</bitWidth> |
||
| 9410 | </field> |
||
| 9411 | <field> |
||
| 9412 | <name>PL</name> |
||
| 9413 | <description>Channel Priority level</description> |
||
| 9414 | <bitOffset>12</bitOffset> |
||
| 9415 | <bitWidth>2</bitWidth> |
||
| 9416 | </field> |
||
| 9417 | <field> |
||
| 9418 | <name>MEM2MEM</name> |
||
| 9419 | <description>Memory to memory mode</description> |
||
| 9420 | <bitOffset>14</bitOffset> |
||
| 9421 | <bitWidth>1</bitWidth> |
||
| 9422 | </field> |
||
| 9423 | </fields> |
||
| 9424 | </register> |
||
| 9425 | <register> |
||
| 9426 | <name>CNDTR6</name> |
||
| 9427 | <displayName>CNDTR6</displayName> |
||
| 9428 | <description>DMA channel 6 number of data |
||
| 9429 | register</description> |
||
| 9430 | <addressOffset>0x70</addressOffset> |
||
| 9431 | <size>0x20</size> |
||
| 9432 | <access>read-write</access> |
||
| 9433 | <resetValue>0x00000000</resetValue> |
||
| 9434 | <fields> |
||
| 9435 | <field> |
||
| 9436 | <name>NDT</name> |
||
| 9437 | <description>Number of data to transfer</description> |
||
| 9438 | <bitOffset>0</bitOffset> |
||
| 9439 | <bitWidth>16</bitWidth> |
||
| 9440 | </field> |
||
| 9441 | </fields> |
||
| 9442 | </register> |
||
| 9443 | <register> |
||
| 9444 | <name>CPAR6</name> |
||
| 9445 | <displayName>CPAR6</displayName> |
||
| 9446 | <description>DMA channel 6 peripheral address |
||
| 9447 | register</description> |
||
| 9448 | <addressOffset>0x74</addressOffset> |
||
| 9449 | <size>0x20</size> |
||
| 9450 | <access>read-write</access> |
||
| 9451 | <resetValue>0x00000000</resetValue> |
||
| 9452 | <fields> |
||
| 9453 | <field> |
||
| 9454 | <name>PA</name> |
||
| 9455 | <description>Peripheral address</description> |
||
| 9456 | <bitOffset>0</bitOffset> |
||
| 9457 | <bitWidth>32</bitWidth> |
||
| 9458 | </field> |
||
| 9459 | </fields> |
||
| 9460 | </register> |
||
| 9461 | <register> |
||
| 9462 | <name>CMAR6</name> |
||
| 9463 | <displayName>CMAR6</displayName> |
||
| 9464 | <description>DMA channel 6 memory address |
||
| 9465 | register</description> |
||
| 9466 | <addressOffset>0x78</addressOffset> |
||
| 9467 | <size>0x20</size> |
||
| 9468 | <access>read-write</access> |
||
| 9469 | <resetValue>0x00000000</resetValue> |
||
| 9470 | <fields> |
||
| 9471 | <field> |
||
| 9472 | <name>MA</name> |
||
| 9473 | <description>Memory address</description> |
||
| 9474 | <bitOffset>0</bitOffset> |
||
| 9475 | <bitWidth>32</bitWidth> |
||
| 9476 | </field> |
||
| 9477 | </fields> |
||
| 9478 | </register> |
||
| 9479 | <register> |
||
| 9480 | <name>CCR7</name> |
||
| 9481 | <displayName>CCR7</displayName> |
||
| 9482 | <description>DMA channel configuration register |
||
| 9483 | (DMA_CCR)</description> |
||
| 9484 | <addressOffset>0x80</addressOffset> |
||
| 9485 | <size>0x20</size> |
||
| 9486 | <access>read-write</access> |
||
| 9487 | <resetValue>0x00000000</resetValue> |
||
| 9488 | <fields> |
||
| 9489 | <field> |
||
| 9490 | <name>EN</name> |
||
| 9491 | <description>Channel enable</description> |
||
| 9492 | <bitOffset>0</bitOffset> |
||
| 9493 | <bitWidth>1</bitWidth> |
||
| 9494 | </field> |
||
| 9495 | <field> |
||
| 9496 | <name>TCIE</name> |
||
| 9497 | <description>Transfer complete interrupt |
||
| 9498 | enable</description> |
||
| 9499 | <bitOffset>1</bitOffset> |
||
| 9500 | <bitWidth>1</bitWidth> |
||
| 9501 | </field> |
||
| 9502 | <field> |
||
| 9503 | <name>HTIE</name> |
||
| 9504 | <description>Half Transfer interrupt |
||
| 9505 | enable</description> |
||
| 9506 | <bitOffset>2</bitOffset> |
||
| 9507 | <bitWidth>1</bitWidth> |
||
| 9508 | </field> |
||
| 9509 | <field> |
||
| 9510 | <name>TEIE</name> |
||
| 9511 | <description>Transfer error interrupt |
||
| 9512 | enable</description> |
||
| 9513 | <bitOffset>3</bitOffset> |
||
| 9514 | <bitWidth>1</bitWidth> |
||
| 9515 | </field> |
||
| 9516 | <field> |
||
| 9517 | <name>DIR</name> |
||
| 9518 | <description>Data transfer direction</description> |
||
| 9519 | <bitOffset>4</bitOffset> |
||
| 9520 | <bitWidth>1</bitWidth> |
||
| 9521 | </field> |
||
| 9522 | <field> |
||
| 9523 | <name>CIRC</name> |
||
| 9524 | <description>Circular mode</description> |
||
| 9525 | <bitOffset>5</bitOffset> |
||
| 9526 | <bitWidth>1</bitWidth> |
||
| 9527 | </field> |
||
| 9528 | <field> |
||
| 9529 | <name>PINC</name> |
||
| 9530 | <description>Peripheral increment mode</description> |
||
| 9531 | <bitOffset>6</bitOffset> |
||
| 9532 | <bitWidth>1</bitWidth> |
||
| 9533 | </field> |
||
| 9534 | <field> |
||
| 9535 | <name>MINC</name> |
||
| 9536 | <description>Memory increment mode</description> |
||
| 9537 | <bitOffset>7</bitOffset> |
||
| 9538 | <bitWidth>1</bitWidth> |
||
| 9539 | </field> |
||
| 9540 | <field> |
||
| 9541 | <name>PSIZE</name> |
||
| 9542 | <description>Peripheral size</description> |
||
| 9543 | <bitOffset>8</bitOffset> |
||
| 9544 | <bitWidth>2</bitWidth> |
||
| 9545 | </field> |
||
| 9546 | <field> |
||
| 9547 | <name>MSIZE</name> |
||
| 9548 | <description>Memory size</description> |
||
| 9549 | <bitOffset>10</bitOffset> |
||
| 9550 | <bitWidth>2</bitWidth> |
||
| 9551 | </field> |
||
| 9552 | <field> |
||
| 9553 | <name>PL</name> |
||
| 9554 | <description>Channel Priority level</description> |
||
| 9555 | <bitOffset>12</bitOffset> |
||
| 9556 | <bitWidth>2</bitWidth> |
||
| 9557 | </field> |
||
| 9558 | <field> |
||
| 9559 | <name>MEM2MEM</name> |
||
| 9560 | <description>Memory to memory mode</description> |
||
| 9561 | <bitOffset>14</bitOffset> |
||
| 9562 | <bitWidth>1</bitWidth> |
||
| 9563 | </field> |
||
| 9564 | </fields> |
||
| 9565 | </register> |
||
| 9566 | <register> |
||
| 9567 | <name>CNDTR7</name> |
||
| 9568 | <displayName>CNDTR7</displayName> |
||
| 9569 | <description>DMA channel 7 number of data |
||
| 9570 | register</description> |
||
| 9571 | <addressOffset>0x84</addressOffset> |
||
| 9572 | <size>0x20</size> |
||
| 9573 | <access>read-write</access> |
||
| 9574 | <resetValue>0x00000000</resetValue> |
||
| 9575 | <fields> |
||
| 9576 | <field> |
||
| 9577 | <name>NDT</name> |
||
| 9578 | <description>Number of data to transfer</description> |
||
| 9579 | <bitOffset>0</bitOffset> |
||
| 9580 | <bitWidth>16</bitWidth> |
||
| 9581 | </field> |
||
| 9582 | </fields> |
||
| 9583 | </register> |
||
| 9584 | <register> |
||
| 9585 | <name>CPAR7</name> |
||
| 9586 | <displayName>CPAR7</displayName> |
||
| 9587 | <description>DMA channel 7 peripheral address |
||
| 9588 | register</description> |
||
| 9589 | <addressOffset>0x88</addressOffset> |
||
| 9590 | <size>0x20</size> |
||
| 9591 | <access>read-write</access> |
||
| 9592 | <resetValue>0x00000000</resetValue> |
||
| 9593 | <fields> |
||
| 9594 | <field> |
||
| 9595 | <name>PA</name> |
||
| 9596 | <description>Peripheral address</description> |
||
| 9597 | <bitOffset>0</bitOffset> |
||
| 9598 | <bitWidth>32</bitWidth> |
||
| 9599 | </field> |
||
| 9600 | </fields> |
||
| 9601 | </register> |
||
| 9602 | <register> |
||
| 9603 | <name>CMAR7</name> |
||
| 9604 | <displayName>CMAR7</displayName> |
||
| 9605 | <description>DMA channel 7 memory address |
||
| 9606 | register</description> |
||
| 9607 | <addressOffset>0x8C</addressOffset> |
||
| 9608 | <size>0x20</size> |
||
| 9609 | <access>read-write</access> |
||
| 9610 | <resetValue>0x00000000</resetValue> |
||
| 9611 | <fields> |
||
| 9612 | <field> |
||
| 9613 | <name>MA</name> |
||
| 9614 | <description>Memory address</description> |
||
| 9615 | <bitOffset>0</bitOffset> |
||
| 9616 | <bitWidth>32</bitWidth> |
||
| 9617 | </field> |
||
| 9618 | </fields> |
||
| 9619 | </register> |
||
| 9620 | </registers> |
||
| 9621 | </peripheral> |
||
| 9622 | <peripheral> |
||
| 9623 | <name>RCC</name> |
||
| 9624 | <description>Reset and clock control</description> |
||
| 9625 | <groupName>RCC</groupName> |
||
| 9626 | <baseAddress>0x40021000</baseAddress> |
||
| 9627 | <addressBlock> |
||
| 9628 | <offset>0x0</offset> |
||
| 9629 | <size>0x400</size> |
||
| 9630 | <usage>registers</usage> |
||
| 9631 | </addressBlock> |
||
| 9632 | <interrupt> |
||
| 9633 | <name>PVD</name> |
||
| 9634 | <description>PVD and VDDIO2 supply comparator |
||
| 9635 | interrupt</description> |
||
| 9636 | <value>1</value> |
||
| 9637 | </interrupt> |
||
| 9638 | <interrupt> |
||
| 9639 | <name>EXTI0_1</name> |
||
| 9640 | <description>EXTI Line[1:0] interrupts</description> |
||
| 9641 | <value>5</value> |
||
| 9642 | </interrupt> |
||
| 9643 | <interrupt> |
||
| 9644 | <name>EXTI2_3</name> |
||
| 9645 | <description>EXTI Line[3:2] interrupts</description> |
||
| 9646 | <value>6</value> |
||
| 9647 | </interrupt> |
||
| 9648 | <interrupt> |
||
| 9649 | <name>EXTI4_15</name> |
||
| 9650 | <description>EXTI Line15 and EXTI4 interrupts</description> |
||
| 9651 | <value>7</value> |
||
| 9652 | </interrupt> |
||
| 9653 | <registers> |
||
| 9654 | <register> |
||
| 9655 | <name>CR</name> |
||
| 9656 | <displayName>CR</displayName> |
||
| 9657 | <description>Clock control register</description> |
||
| 9658 | <addressOffset>0x0</addressOffset> |
||
| 9659 | <size>0x20</size> |
||
| 9660 | <resetValue>0x00000083</resetValue> |
||
| 9661 | <fields> |
||
| 9662 | <field> |
||
| 9663 | <name>HSION</name> |
||
| 9664 | <description>Internal High Speed clock |
||
| 9665 | enable</description> |
||
| 9666 | <bitOffset>0</bitOffset> |
||
| 9667 | <bitWidth>1</bitWidth> |
||
| 9668 | <access>read-write</access> |
||
| 9669 | </field> |
||
| 9670 | <field> |
||
| 9671 | <name>HSIRDY</name> |
||
| 9672 | <description>Internal High Speed clock ready |
||
| 9673 | flag</description> |
||
| 9674 | <bitOffset>1</bitOffset> |
||
| 9675 | <bitWidth>1</bitWidth> |
||
| 9676 | <access>read-only</access> |
||
| 9677 | </field> |
||
| 9678 | <field> |
||
| 9679 | <name>HSITRIM</name> |
||
| 9680 | <description>Internal High Speed clock |
||
| 9681 | trimming</description> |
||
| 9682 | <bitOffset>3</bitOffset> |
||
| 9683 | <bitWidth>5</bitWidth> |
||
| 9684 | <access>read-write</access> |
||
| 9685 | </field> |
||
| 9686 | <field> |
||
| 9687 | <name>HSICAL</name> |
||
| 9688 | <description>Internal High Speed clock |
||
| 9689 | Calibration</description> |
||
| 9690 | <bitOffset>8</bitOffset> |
||
| 9691 | <bitWidth>8</bitWidth> |
||
| 9692 | <access>read-only</access> |
||
| 9693 | </field> |
||
| 9694 | <field> |
||
| 9695 | <name>HSEON</name> |
||
| 9696 | <description>External High Speed clock |
||
| 9697 | enable</description> |
||
| 9698 | <bitOffset>16</bitOffset> |
||
| 9699 | <bitWidth>1</bitWidth> |
||
| 9700 | <access>read-write</access> |
||
| 9701 | </field> |
||
| 9702 | <field> |
||
| 9703 | <name>HSERDY</name> |
||
| 9704 | <description>External High Speed clock ready |
||
| 9705 | flag</description> |
||
| 9706 | <bitOffset>17</bitOffset> |
||
| 9707 | <bitWidth>1</bitWidth> |
||
| 9708 | <access>read-only</access> |
||
| 9709 | </field> |
||
| 9710 | <field> |
||
| 9711 | <name>HSEBYP</name> |
||
| 9712 | <description>External High Speed clock |
||
| 9713 | Bypass</description> |
||
| 9714 | <bitOffset>18</bitOffset> |
||
| 9715 | <bitWidth>1</bitWidth> |
||
| 9716 | <access>read-write</access> |
||
| 9717 | </field> |
||
| 9718 | <field> |
||
| 9719 | <name>CSSON</name> |
||
| 9720 | <description>Clock Security System |
||
| 9721 | enable</description> |
||
| 9722 | <bitOffset>19</bitOffset> |
||
| 9723 | <bitWidth>1</bitWidth> |
||
| 9724 | <access>read-write</access> |
||
| 9725 | </field> |
||
| 9726 | <field> |
||
| 9727 | <name>PLLON</name> |
||
| 9728 | <description>PLL enable</description> |
||
| 9729 | <bitOffset>24</bitOffset> |
||
| 9730 | <bitWidth>1</bitWidth> |
||
| 9731 | <access>read-write</access> |
||
| 9732 | </field> |
||
| 9733 | <field> |
||
| 9734 | <name>PLLRDY</name> |
||
| 9735 | <description>PLL clock ready flag</description> |
||
| 9736 | <bitOffset>25</bitOffset> |
||
| 9737 | <bitWidth>1</bitWidth> |
||
| 9738 | <access>read-only</access> |
||
| 9739 | </field> |
||
| 9740 | </fields> |
||
| 9741 | </register> |
||
| 9742 | <register> |
||
| 9743 | <name>CFGR</name> |
||
| 9744 | <displayName>CFGR</displayName> |
||
| 9745 | <description>Clock configuration register |
||
| 9746 | (RCC_CFGR)</description> |
||
| 9747 | <addressOffset>0x4</addressOffset> |
||
| 9748 | <size>0x20</size> |
||
| 9749 | <resetValue>0x00000000</resetValue> |
||
| 9750 | <fields> |
||
| 9751 | <field> |
||
| 9752 | <name>SW</name> |
||
| 9753 | <description>System clock Switch</description> |
||
| 9754 | <bitOffset>0</bitOffset> |
||
| 9755 | <bitWidth>2</bitWidth> |
||
| 9756 | <access>read-write</access> |
||
| 9757 | </field> |
||
| 9758 | <field> |
||
| 9759 | <name>SWS</name> |
||
| 9760 | <description>System Clock Switch Status</description> |
||
| 9761 | <bitOffset>2</bitOffset> |
||
| 9762 | <bitWidth>2</bitWidth> |
||
| 9763 | <access>read-only</access> |
||
| 9764 | </field> |
||
| 9765 | <field> |
||
| 9766 | <name>HPRE</name> |
||
| 9767 | <description>AHB prescaler</description> |
||
| 9768 | <bitOffset>4</bitOffset> |
||
| 9769 | <bitWidth>4</bitWidth> |
||
| 9770 | <access>read-write</access> |
||
| 9771 | </field> |
||
| 9772 | <field> |
||
| 9773 | <name>PPRE</name> |
||
| 9774 | <description>APB Low speed prescaler |
||
| 9775 | (APB1)</description> |
||
| 9776 | <bitOffset>8</bitOffset> |
||
| 9777 | <bitWidth>3</bitWidth> |
||
| 9778 | <access>read-write</access> |
||
| 9779 | </field> |
||
| 9780 | <field> |
||
| 9781 | <name>ADCPRE</name> |
||
| 9782 | <description>ADC prescaler</description> |
||
| 9783 | <bitOffset>14</bitOffset> |
||
| 9784 | <bitWidth>1</bitWidth> |
||
| 9785 | <access>read-write</access> |
||
| 9786 | </field> |
||
| 9787 | <field> |
||
| 9788 | <name>PLLSRC</name> |
||
| 9789 | <description>PLL input clock source</description> |
||
| 9790 | <bitOffset>15</bitOffset> |
||
| 9791 | <bitWidth>2</bitWidth> |
||
| 9792 | <access>read-write</access> |
||
| 9793 | </field> |
||
| 9794 | <field> |
||
| 9795 | <name>PLLXTPRE</name> |
||
| 9796 | <description>HSE divider for PLL entry</description> |
||
| 9797 | <bitOffset>17</bitOffset> |
||
| 9798 | <bitWidth>1</bitWidth> |
||
| 9799 | <access>read-write</access> |
||
| 9800 | </field> |
||
| 9801 | <field> |
||
| 9802 | <name>PLLMUL</name> |
||
| 9803 | <description>PLL Multiplication Factor</description> |
||
| 9804 | <bitOffset>18</bitOffset> |
||
| 9805 | <bitWidth>4</bitWidth> |
||
| 9806 | <access>read-write</access> |
||
| 9807 | </field> |
||
| 9808 | <field> |
||
| 9809 | <name>MCO</name> |
||
| 9810 | <description>Microcontroller clock |
||
| 9811 | output</description> |
||
| 9812 | <bitOffset>24</bitOffset> |
||
| 9813 | <bitWidth>3</bitWidth> |
||
| 9814 | <access>read-write</access> |
||
| 9815 | </field> |
||
| 9816 | <field> |
||
| 9817 | <name>MCOPRE</name> |
||
| 9818 | <description>Microcontroller Clock Output |
||
| 9819 | Prescaler</description> |
||
| 9820 | <bitOffset>28</bitOffset> |
||
| 9821 | <bitWidth>3</bitWidth> |
||
| 9822 | <access>read-write</access> |
||
| 9823 | </field> |
||
| 9824 | <field> |
||
| 9825 | <name>PLLNODIV</name> |
||
| 9826 | <description>PLL clock not divided for |
||
| 9827 | MCO</description> |
||
| 9828 | <bitOffset>31</bitOffset> |
||
| 9829 | <bitWidth>1</bitWidth> |
||
| 9830 | <access>read-write</access> |
||
| 9831 | </field> |
||
| 9832 | </fields> |
||
| 9833 | </register> |
||
| 9834 | <register> |
||
| 9835 | <name>CIR</name> |
||
| 9836 | <displayName>CIR</displayName> |
||
| 9837 | <description>Clock interrupt register |
||
| 9838 | (RCC_CIR)</description> |
||
| 9839 | <addressOffset>0x8</addressOffset> |
||
| 9840 | <size>0x20</size> |
||
| 9841 | <resetValue>0x00000000</resetValue> |
||
| 9842 | <fields> |
||
| 9843 | <field> |
||
| 9844 | <name>LSIRDYF</name> |
||
| 9845 | <description>LSI Ready Interrupt flag</description> |
||
| 9846 | <bitOffset>0</bitOffset> |
||
| 9847 | <bitWidth>1</bitWidth> |
||
| 9848 | <access>read-only</access> |
||
| 9849 | </field> |
||
| 9850 | <field> |
||
| 9851 | <name>LSERDYF</name> |
||
| 9852 | <description>LSE Ready Interrupt flag</description> |
||
| 9853 | <bitOffset>1</bitOffset> |
||
| 9854 | <bitWidth>1</bitWidth> |
||
| 9855 | <access>read-only</access> |
||
| 9856 | </field> |
||
| 9857 | <field> |
||
| 9858 | <name>HSIRDYF</name> |
||
| 9859 | <description>HSI Ready Interrupt flag</description> |
||
| 9860 | <bitOffset>2</bitOffset> |
||
| 9861 | <bitWidth>1</bitWidth> |
||
| 9862 | <access>read-only</access> |
||
| 9863 | </field> |
||
| 9864 | <field> |
||
| 9865 | <name>HSERDYF</name> |
||
| 9866 | <description>HSE Ready Interrupt flag</description> |
||
| 9867 | <bitOffset>3</bitOffset> |
||
| 9868 | <bitWidth>1</bitWidth> |
||
| 9869 | <access>read-only</access> |
||
| 9870 | </field> |
||
| 9871 | <field> |
||
| 9872 | <name>PLLRDYF</name> |
||
| 9873 | <description>PLL Ready Interrupt flag</description> |
||
| 9874 | <bitOffset>4</bitOffset> |
||
| 9875 | <bitWidth>1</bitWidth> |
||
| 9876 | <access>read-only</access> |
||
| 9877 | </field> |
||
| 9878 | <field> |
||
| 9879 | <name>HSI14RDYF</name> |
||
| 9880 | <description>HSI14 ready interrupt flag</description> |
||
| 9881 | <bitOffset>5</bitOffset> |
||
| 9882 | <bitWidth>1</bitWidth> |
||
| 9883 | <access>read-only</access> |
||
| 9884 | </field> |
||
| 9885 | <field> |
||
| 9886 | <name>HSI48RDYF</name> |
||
| 9887 | <description>HSI48 ready interrupt flag</description> |
||
| 9888 | <bitOffset>6</bitOffset> |
||
| 9889 | <bitWidth>1</bitWidth> |
||
| 9890 | <access>read-only</access> |
||
| 9891 | </field> |
||
| 9892 | <field> |
||
| 9893 | <name>CSSF</name> |
||
| 9894 | <description>Clock Security System Interrupt |
||
| 9895 | flag</description> |
||
| 9896 | <bitOffset>7</bitOffset> |
||
| 9897 | <bitWidth>1</bitWidth> |
||
| 9898 | <access>read-only</access> |
||
| 9899 | </field> |
||
| 9900 | <field> |
||
| 9901 | <name>LSIRDYIE</name> |
||
| 9902 | <description>LSI Ready Interrupt Enable</description> |
||
| 9903 | <bitOffset>8</bitOffset> |
||
| 9904 | <bitWidth>1</bitWidth> |
||
| 9905 | <access>read-write</access> |
||
| 9906 | </field> |
||
| 9907 | <field> |
||
| 9908 | <name>LSERDYIE</name> |
||
| 9909 | <description>LSE Ready Interrupt Enable</description> |
||
| 9910 | <bitOffset>9</bitOffset> |
||
| 9911 | <bitWidth>1</bitWidth> |
||
| 9912 | <access>read-write</access> |
||
| 9913 | </field> |
||
| 9914 | <field> |
||
| 9915 | <name>HSIRDYIE</name> |
||
| 9916 | <description>HSI Ready Interrupt Enable</description> |
||
| 9917 | <bitOffset>10</bitOffset> |
||
| 9918 | <bitWidth>1</bitWidth> |
||
| 9919 | <access>read-write</access> |
||
| 9920 | </field> |
||
| 9921 | <field> |
||
| 9922 | <name>HSERDYIE</name> |
||
| 9923 | <description>HSE Ready Interrupt Enable</description> |
||
| 9924 | <bitOffset>11</bitOffset> |
||
| 9925 | <bitWidth>1</bitWidth> |
||
| 9926 | <access>read-write</access> |
||
| 9927 | </field> |
||
| 9928 | <field> |
||
| 9929 | <name>PLLRDYIE</name> |
||
| 9930 | <description>PLL Ready Interrupt Enable</description> |
||
| 9931 | <bitOffset>12</bitOffset> |
||
| 9932 | <bitWidth>1</bitWidth> |
||
| 9933 | <access>read-write</access> |
||
| 9934 | </field> |
||
| 9935 | <field> |
||
| 9936 | <name>HSI14RDYE</name> |
||
| 9937 | <description>HSI14 ready interrupt |
||
| 9938 | enable</description> |
||
| 9939 | <bitOffset>13</bitOffset> |
||
| 9940 | <bitWidth>1</bitWidth> |
||
| 9941 | <access>read-write</access> |
||
| 9942 | </field> |
||
| 9943 | <field> |
||
| 9944 | <name>HSI48RDYIE</name> |
||
| 9945 | <description>HSI48 ready interrupt |
||
| 9946 | enable</description> |
||
| 9947 | <bitOffset>14</bitOffset> |
||
| 9948 | <bitWidth>1</bitWidth> |
||
| 9949 | <access>read-write</access> |
||
| 9950 | </field> |
||
| 9951 | <field> |
||
| 9952 | <name>LSIRDYC</name> |
||
| 9953 | <description>LSI Ready Interrupt Clear</description> |
||
| 9954 | <bitOffset>16</bitOffset> |
||
| 9955 | <bitWidth>1</bitWidth> |
||
| 9956 | <access>write-only</access> |
||
| 9957 | </field> |
||
| 9958 | <field> |
||
| 9959 | <name>LSERDYC</name> |
||
| 9960 | <description>LSE Ready Interrupt Clear</description> |
||
| 9961 | <bitOffset>17</bitOffset> |
||
| 9962 | <bitWidth>1</bitWidth> |
||
| 9963 | <access>write-only</access> |
||
| 9964 | </field> |
||
| 9965 | <field> |
||
| 9966 | <name>HSIRDYC</name> |
||
| 9967 | <description>HSI Ready Interrupt Clear</description> |
||
| 9968 | <bitOffset>18</bitOffset> |
||
| 9969 | <bitWidth>1</bitWidth> |
||
| 9970 | <access>write-only</access> |
||
| 9971 | </field> |
||
| 9972 | <field> |
||
| 9973 | <name>HSERDYC</name> |
||
| 9974 | <description>HSE Ready Interrupt Clear</description> |
||
| 9975 | <bitOffset>19</bitOffset> |
||
| 9976 | <bitWidth>1</bitWidth> |
||
| 9977 | <access>write-only</access> |
||
| 9978 | </field> |
||
| 9979 | <field> |
||
| 9980 | <name>PLLRDYC</name> |
||
| 9981 | <description>PLL Ready Interrupt Clear</description> |
||
| 9982 | <bitOffset>20</bitOffset> |
||
| 9983 | <bitWidth>1</bitWidth> |
||
| 9984 | <access>write-only</access> |
||
| 9985 | </field> |
||
| 9986 | <field> |
||
| 9987 | <name>HSI14RDYC</name> |
||
| 9988 | <description>HSI 14 MHz Ready Interrupt |
||
| 9989 | Clear</description> |
||
| 9990 | <bitOffset>21</bitOffset> |
||
| 9991 | <bitWidth>1</bitWidth> |
||
| 9992 | <access>write-only</access> |
||
| 9993 | </field> |
||
| 9994 | <field> |
||
| 9995 | <name>HSI48RDYC</name> |
||
| 9996 | <description>HSI48 Ready Interrupt |
||
| 9997 | Clear</description> |
||
| 9998 | <bitOffset>22</bitOffset> |
||
| 9999 | <bitWidth>1</bitWidth> |
||
| 10000 | <access>write-only</access> |
||
| 10001 | </field> |
||
| 10002 | <field> |
||
| 10003 | <name>CSSC</name> |
||
| 10004 | <description>Clock security system interrupt |
||
| 10005 | clear</description> |
||
| 10006 | <bitOffset>23</bitOffset> |
||
| 10007 | <bitWidth>1</bitWidth> |
||
| 10008 | <access>write-only</access> |
||
| 10009 | </field> |
||
| 10010 | </fields> |
||
| 10011 | </register> |
||
| 10012 | <register> |
||
| 10013 | <name>APB2RSTR</name> |
||
| 10014 | <displayName>APB2RSTR</displayName> |
||
| 10015 | <description>APB2 peripheral reset register |
||
| 10016 | (RCC_APB2RSTR)</description> |
||
| 10017 | <addressOffset>0xC</addressOffset> |
||
| 10018 | <size>0x20</size> |
||
| 10019 | <access>read-write</access> |
||
| 10020 | <resetValue>0x00000000</resetValue> |
||
| 10021 | <fields> |
||
| 10022 | <field> |
||
| 10023 | <name>SYSCFGRST</name> |
||
| 10024 | <description>SYSCFG and COMP reset</description> |
||
| 10025 | <bitOffset>0</bitOffset> |
||
| 10026 | <bitWidth>1</bitWidth> |
||
| 10027 | </field> |
||
| 10028 | <field> |
||
| 10029 | <name>ADCRST</name> |
||
| 10030 | <description>ADC interface reset</description> |
||
| 10031 | <bitOffset>9</bitOffset> |
||
| 10032 | <bitWidth>1</bitWidth> |
||
| 10033 | </field> |
||
| 10034 | <field> |
||
| 10035 | <name>TIM1RST</name> |
||
| 10036 | <description>TIM1 timer reset</description> |
||
| 10037 | <bitOffset>11</bitOffset> |
||
| 10038 | <bitWidth>1</bitWidth> |
||
| 10039 | </field> |
||
| 10040 | <field> |
||
| 10041 | <name>SPI1RST</name> |
||
| 10042 | <description>SPI 1 reset</description> |
||
| 10043 | <bitOffset>12</bitOffset> |
||
| 10044 | <bitWidth>1</bitWidth> |
||
| 10045 | </field> |
||
| 10046 | <field> |
||
| 10047 | <name>USART1RST</name> |
||
| 10048 | <description>USART1 reset</description> |
||
| 10049 | <bitOffset>14</bitOffset> |
||
| 10050 | <bitWidth>1</bitWidth> |
||
| 10051 | </field> |
||
| 10052 | <field> |
||
| 10053 | <name>TIM15RST</name> |
||
| 10054 | <description>TIM15 timer reset</description> |
||
| 10055 | <bitOffset>16</bitOffset> |
||
| 10056 | <bitWidth>1</bitWidth> |
||
| 10057 | </field> |
||
| 10058 | <field> |
||
| 10059 | <name>TIM16RST</name> |
||
| 10060 | <description>TIM16 timer reset</description> |
||
| 10061 | <bitOffset>17</bitOffset> |
||
| 10062 | <bitWidth>1</bitWidth> |
||
| 10063 | </field> |
||
| 10064 | <field> |
||
| 10065 | <name>TIM17RST</name> |
||
| 10066 | <description>TIM17 timer reset</description> |
||
| 10067 | <bitOffset>18</bitOffset> |
||
| 10068 | <bitWidth>1</bitWidth> |
||
| 10069 | </field> |
||
| 10070 | <field> |
||
| 10071 | <name>DBGMCURST</name> |
||
| 10072 | <description>Debug MCU reset</description> |
||
| 10073 | <bitOffset>22</bitOffset> |
||
| 10074 | <bitWidth>1</bitWidth> |
||
| 10075 | </field> |
||
| 10076 | </fields> |
||
| 10077 | </register> |
||
| 10078 | <register> |
||
| 10079 | <name>APB1RSTR</name> |
||
| 10080 | <displayName>APB1RSTR</displayName> |
||
| 10081 | <description>APB1 peripheral reset register |
||
| 10082 | (RCC_APB1RSTR)</description> |
||
| 10083 | <addressOffset>0x10</addressOffset> |
||
| 10084 | <size>0x20</size> |
||
| 10085 | <access>read-write</access> |
||
| 10086 | <resetValue>0x00000000</resetValue> |
||
| 10087 | <fields> |
||
| 10088 | <field> |
||
| 10089 | <name>TIM3RST</name> |
||
| 10090 | <description>Timer 3 reset</description> |
||
| 10091 | <bitOffset>1</bitOffset> |
||
| 10092 | <bitWidth>1</bitWidth> |
||
| 10093 | </field> |
||
| 10094 | <field> |
||
| 10095 | <name>TIM6RST</name> |
||
| 10096 | <description>Timer 6 reset</description> |
||
| 10097 | <bitOffset>4</bitOffset> |
||
| 10098 | <bitWidth>1</bitWidth> |
||
| 10099 | </field> |
||
| 10100 | <field> |
||
| 10101 | <name>TIM14RST</name> |
||
| 10102 | <description>Timer 14 reset</description> |
||
| 10103 | <bitOffset>8</bitOffset> |
||
| 10104 | <bitWidth>1</bitWidth> |
||
| 10105 | </field> |
||
| 10106 | <field> |
||
| 10107 | <name>WWDGRST</name> |
||
| 10108 | <description>Window watchdog reset</description> |
||
| 10109 | <bitOffset>11</bitOffset> |
||
| 10110 | <bitWidth>1</bitWidth> |
||
| 10111 | </field> |
||
| 10112 | <field> |
||
| 10113 | <name>SPI2RST</name> |
||
| 10114 | <description>SPI2 reset</description> |
||
| 10115 | <bitOffset>14</bitOffset> |
||
| 10116 | <bitWidth>1</bitWidth> |
||
| 10117 | </field> |
||
| 10118 | <field> |
||
| 10119 | <name>USART2RST</name> |
||
| 10120 | <description>USART 2 reset</description> |
||
| 10121 | <bitOffset>17</bitOffset> |
||
| 10122 | <bitWidth>1</bitWidth> |
||
| 10123 | </field> |
||
| 10124 | <field> |
||
| 10125 | <name>I2C1RST</name> |
||
| 10126 | <description>I2C1 reset</description> |
||
| 10127 | <bitOffset>21</bitOffset> |
||
| 10128 | <bitWidth>1</bitWidth> |
||
| 10129 | </field> |
||
| 10130 | <field> |
||
| 10131 | <name>I2C2RST</name> |
||
| 10132 | <description>I2C2 reset</description> |
||
| 10133 | <bitOffset>22</bitOffset> |
||
| 10134 | <bitWidth>1</bitWidth> |
||
| 10135 | </field> |
||
| 10136 | <field> |
||
| 10137 | <name>PWRRST</name> |
||
| 10138 | <description>Power interface reset</description> |
||
| 10139 | <bitOffset>28</bitOffset> |
||
| 10140 | <bitWidth>1</bitWidth> |
||
| 10141 | </field> |
||
| 10142 | </fields> |
||
| 10143 | </register> |
||
| 10144 | <register> |
||
| 10145 | <name>AHBENR</name> |
||
| 10146 | <displayName>AHBENR</displayName> |
||
| 10147 | <description>AHB Peripheral Clock enable register |
||
| 10148 | (RCC_AHBENR)</description> |
||
| 10149 | <addressOffset>0x14</addressOffset> |
||
| 10150 | <size>0x20</size> |
||
| 10151 | <access>read-write</access> |
||
| 10152 | <resetValue>0x00000014</resetValue> |
||
| 10153 | <fields> |
||
| 10154 | <field> |
||
| 10155 | <name>DMAEN</name> |
||
| 10156 | <description>DMA1 clock enable</description> |
||
| 10157 | <bitOffset>0</bitOffset> |
||
| 10158 | <bitWidth>1</bitWidth> |
||
| 10159 | </field> |
||
| 10160 | <field> |
||
| 10161 | <name>SRAMEN</name> |
||
| 10162 | <description>SRAM interface clock |
||
| 10163 | enable</description> |
||
| 10164 | <bitOffset>2</bitOffset> |
||
| 10165 | <bitWidth>1</bitWidth> |
||
| 10166 | </field> |
||
| 10167 | <field> |
||
| 10168 | <name>FLITFEN</name> |
||
| 10169 | <description>FLITF clock enable</description> |
||
| 10170 | <bitOffset>4</bitOffset> |
||
| 10171 | <bitWidth>1</bitWidth> |
||
| 10172 | </field> |
||
| 10173 | <field> |
||
| 10174 | <name>CRCEN</name> |
||
| 10175 | <description>CRC clock enable</description> |
||
| 10176 | <bitOffset>6</bitOffset> |
||
| 10177 | <bitWidth>1</bitWidth> |
||
| 10178 | </field> |
||
| 10179 | <field> |
||
| 10180 | <name>IOPAEN</name> |
||
| 10181 | <description>I/O port A clock enable</description> |
||
| 10182 | <bitOffset>17</bitOffset> |
||
| 10183 | <bitWidth>1</bitWidth> |
||
| 10184 | </field> |
||
| 10185 | <field> |
||
| 10186 | <name>IOPBEN</name> |
||
| 10187 | <description>I/O port B clock enable</description> |
||
| 10188 | <bitOffset>18</bitOffset> |
||
| 10189 | <bitWidth>1</bitWidth> |
||
| 10190 | </field> |
||
| 10191 | <field> |
||
| 10192 | <name>IOPCEN</name> |
||
| 10193 | <description>I/O port C clock enable</description> |
||
| 10194 | <bitOffset>19</bitOffset> |
||
| 10195 | <bitWidth>1</bitWidth> |
||
| 10196 | </field> |
||
| 10197 | <field> |
||
| 10198 | <name>IOPDEN</name> |
||
| 10199 | <description>I/O port D clock enable</description> |
||
| 10200 | <bitOffset>20</bitOffset> |
||
| 10201 | <bitWidth>1</bitWidth> |
||
| 10202 | </field> |
||
| 10203 | <field> |
||
| 10204 | <name>IOPFEN</name> |
||
| 10205 | <description>I/O port F clock enable</description> |
||
| 10206 | <bitOffset>22</bitOffset> |
||
| 10207 | <bitWidth>1</bitWidth> |
||
| 10208 | </field> |
||
| 10209 | </fields> |
||
| 10210 | </register> |
||
| 10211 | <register> |
||
| 10212 | <name>APB2ENR</name> |
||
| 10213 | <displayName>APB2ENR</displayName> |
||
| 10214 | <description>APB2 peripheral clock enable register |
||
| 10215 | (RCC_APB2ENR)</description> |
||
| 10216 | <addressOffset>0x18</addressOffset> |
||
| 10217 | <size>0x20</size> |
||
| 10218 | <access>read-write</access> |
||
| 10219 | <resetValue>0x00000000</resetValue> |
||
| 10220 | <fields> |
||
| 10221 | <field> |
||
| 10222 | <name>SYSCFGEN</name> |
||
| 10223 | <description>SYSCFG clock enable</description> |
||
| 10224 | <bitOffset>0</bitOffset> |
||
| 10225 | <bitWidth>1</bitWidth> |
||
| 10226 | </field> |
||
| 10227 | <field> |
||
| 10228 | <name>ADCEN</name> |
||
| 10229 | <description>ADC 1 interface clock |
||
| 10230 | enable</description> |
||
| 10231 | <bitOffset>9</bitOffset> |
||
| 10232 | <bitWidth>1</bitWidth> |
||
| 10233 | </field> |
||
| 10234 | <field> |
||
| 10235 | <name>TIM1EN</name> |
||
| 10236 | <description>TIM1 Timer clock enable</description> |
||
| 10237 | <bitOffset>11</bitOffset> |
||
| 10238 | <bitWidth>1</bitWidth> |
||
| 10239 | </field> |
||
| 10240 | <field> |
||
| 10241 | <name>SPI1EN</name> |
||
| 10242 | <description>SPI 1 clock enable</description> |
||
| 10243 | <bitOffset>12</bitOffset> |
||
| 10244 | <bitWidth>1</bitWidth> |
||
| 10245 | </field> |
||
| 10246 | <field> |
||
| 10247 | <name>USART1EN</name> |
||
| 10248 | <description>USART1 clock enable</description> |
||
| 10249 | <bitOffset>14</bitOffset> |
||
| 10250 | <bitWidth>1</bitWidth> |
||
| 10251 | </field> |
||
| 10252 | <field> |
||
| 10253 | <name>TIM15EN</name> |
||
| 10254 | <description>TIM15 timer clock enable</description> |
||
| 10255 | <bitOffset>16</bitOffset> |
||
| 10256 | <bitWidth>1</bitWidth> |
||
| 10257 | </field> |
||
| 10258 | <field> |
||
| 10259 | <name>TIM16EN</name> |
||
| 10260 | <description>TIM16 timer clock enable</description> |
||
| 10261 | <bitOffset>17</bitOffset> |
||
| 10262 | <bitWidth>1</bitWidth> |
||
| 10263 | </field> |
||
| 10264 | <field> |
||
| 10265 | <name>TIM17EN</name> |
||
| 10266 | <description>TIM17 timer clock enable</description> |
||
| 10267 | <bitOffset>18</bitOffset> |
||
| 10268 | <bitWidth>1</bitWidth> |
||
| 10269 | </field> |
||
| 10270 | <field> |
||
| 10271 | <name>DBGMCUEN</name> |
||
| 10272 | <description>MCU debug module clock |
||
| 10273 | enable</description> |
||
| 10274 | <bitOffset>22</bitOffset> |
||
| 10275 | <bitWidth>1</bitWidth> |
||
| 10276 | </field> |
||
| 10277 | </fields> |
||
| 10278 | </register> |
||
| 10279 | <register> |
||
| 10280 | <name>APB1ENR</name> |
||
| 10281 | <displayName>APB1ENR</displayName> |
||
| 10282 | <description>APB1 peripheral clock enable register |
||
| 10283 | (RCC_APB1ENR)</description> |
||
| 10284 | <addressOffset>0x1C</addressOffset> |
||
| 10285 | <size>0x20</size> |
||
| 10286 | <access>read-write</access> |
||
| 10287 | <resetValue>0x00000000</resetValue> |
||
| 10288 | <fields> |
||
| 10289 | <field> |
||
| 10290 | <name>TIM3EN</name> |
||
| 10291 | <description>Timer 3 clock enable</description> |
||
| 10292 | <bitOffset>1</bitOffset> |
||
| 10293 | <bitWidth>1</bitWidth> |
||
| 10294 | </field> |
||
| 10295 | <field> |
||
| 10296 | <name>TIM6EN</name> |
||
| 10297 | <description>Timer 6 clock enable</description> |
||
| 10298 | <bitOffset>4</bitOffset> |
||
| 10299 | <bitWidth>1</bitWidth> |
||
| 10300 | </field> |
||
| 10301 | <field> |
||
| 10302 | <name>TIM14EN</name> |
||
| 10303 | <description>Timer 14 clock enable</description> |
||
| 10304 | <bitOffset>8</bitOffset> |
||
| 10305 | <bitWidth>1</bitWidth> |
||
| 10306 | </field> |
||
| 10307 | <field> |
||
| 10308 | <name>WWDGEN</name> |
||
| 10309 | <description>Window watchdog clock |
||
| 10310 | enable</description> |
||
| 10311 | <bitOffset>11</bitOffset> |
||
| 10312 | <bitWidth>1</bitWidth> |
||
| 10313 | </field> |
||
| 10314 | <field> |
||
| 10315 | <name>SPI2EN</name> |
||
| 10316 | <description>SPI 2 clock enable</description> |
||
| 10317 | <bitOffset>14</bitOffset> |
||
| 10318 | <bitWidth>1</bitWidth> |
||
| 10319 | </field> |
||
| 10320 | <field> |
||
| 10321 | <name>USART2EN</name> |
||
| 10322 | <description>USART 2 clock enable</description> |
||
| 10323 | <bitOffset>17</bitOffset> |
||
| 10324 | <bitWidth>1</bitWidth> |
||
| 10325 | </field> |
||
| 10326 | <field> |
||
| 10327 | <name>I2C1EN</name> |
||
| 10328 | <description>I2C 1 clock enable</description> |
||
| 10329 | <bitOffset>21</bitOffset> |
||
| 10330 | <bitWidth>1</bitWidth> |
||
| 10331 | </field> |
||
| 10332 | <field> |
||
| 10333 | <name>I2C2EN</name> |
||
| 10334 | <description>I2C 2 clock enable</description> |
||
| 10335 | <bitOffset>22</bitOffset> |
||
| 10336 | <bitWidth>1</bitWidth> |
||
| 10337 | </field> |
||
| 10338 | <field> |
||
| 10339 | <name>PWREN</name> |
||
| 10340 | <description>Power interface clock |
||
| 10341 | enable</description> |
||
| 10342 | <bitOffset>28</bitOffset> |
||
| 10343 | <bitWidth>1</bitWidth> |
||
| 10344 | </field> |
||
| 10345 | </fields> |
||
| 10346 | </register> |
||
| 10347 | <register> |
||
| 10348 | <name>BDCR</name> |
||
| 10349 | <displayName>BDCR</displayName> |
||
| 10350 | <description>Backup domain control register |
||
| 10351 | (RCC_BDCR)</description> |
||
| 10352 | <addressOffset>0x20</addressOffset> |
||
| 10353 | <size>0x20</size> |
||
| 10354 | <resetValue>0x00000000</resetValue> |
||
| 10355 | <fields> |
||
| 10356 | <field> |
||
| 10357 | <name>LSEON</name> |
||
| 10358 | <description>External Low Speed oscillator |
||
| 10359 | enable</description> |
||
| 10360 | <bitOffset>0</bitOffset> |
||
| 10361 | <bitWidth>1</bitWidth> |
||
| 10362 | <access>read-write</access> |
||
| 10363 | </field> |
||
| 10364 | <field> |
||
| 10365 | <name>LSERDY</name> |
||
| 10366 | <description>External Low Speed oscillator |
||
| 10367 | ready</description> |
||
| 10368 | <bitOffset>1</bitOffset> |
||
| 10369 | <bitWidth>1</bitWidth> |
||
| 10370 | <access>read-only</access> |
||
| 10371 | </field> |
||
| 10372 | <field> |
||
| 10373 | <name>LSEBYP</name> |
||
| 10374 | <description>External Low Speed oscillator |
||
| 10375 | bypass</description> |
||
| 10376 | <bitOffset>2</bitOffset> |
||
| 10377 | <bitWidth>1</bitWidth> |
||
| 10378 | <access>read-write</access> |
||
| 10379 | </field> |
||
| 10380 | <field> |
||
| 10381 | <name>LSEDRV</name> |
||
| 10382 | <description>LSE oscillator drive |
||
| 10383 | capability</description> |
||
| 10384 | <bitOffset>3</bitOffset> |
||
| 10385 | <bitWidth>2</bitWidth> |
||
| 10386 | <access>read-write</access> |
||
| 10387 | </field> |
||
| 10388 | <field> |
||
| 10389 | <name>RTCSEL</name> |
||
| 10390 | <description>RTC clock source selection</description> |
||
| 10391 | <bitOffset>8</bitOffset> |
||
| 10392 | <bitWidth>2</bitWidth> |
||
| 10393 | <access>read-write</access> |
||
| 10394 | </field> |
||
| 10395 | <field> |
||
| 10396 | <name>RTCEN</name> |
||
| 10397 | <description>RTC clock enable</description> |
||
| 10398 | <bitOffset>15</bitOffset> |
||
| 10399 | <bitWidth>1</bitWidth> |
||
| 10400 | <access>read-write</access> |
||
| 10401 | </field> |
||
| 10402 | <field> |
||
| 10403 | <name>BDRST</name> |
||
| 10404 | <description>Backup domain software |
||
| 10405 | reset</description> |
||
| 10406 | <bitOffset>16</bitOffset> |
||
| 10407 | <bitWidth>1</bitWidth> |
||
| 10408 | <access>read-write</access> |
||
| 10409 | </field> |
||
| 10410 | </fields> |
||
| 10411 | </register> |
||
| 10412 | <register> |
||
| 10413 | <name>CSR</name> |
||
| 10414 | <displayName>CSR</displayName> |
||
| 10415 | <description>Control/status register |
||
| 10416 | (RCC_CSR)</description> |
||
| 10417 | <addressOffset>0x24</addressOffset> |
||
| 10418 | <size>0x20</size> |
||
| 10419 | <resetValue>0x0C000000</resetValue> |
||
| 10420 | <fields> |
||
| 10421 | <field> |
||
| 10422 | <name>LSION</name> |
||
| 10423 | <description>Internal low speed oscillator |
||
| 10424 | enable</description> |
||
| 10425 | <bitOffset>0</bitOffset> |
||
| 10426 | <bitWidth>1</bitWidth> |
||
| 10427 | <access>read-write</access> |
||
| 10428 | </field> |
||
| 10429 | <field> |
||
| 10430 | <name>LSIRDY</name> |
||
| 10431 | <description>Internal low speed oscillator |
||
| 10432 | ready</description> |
||
| 10433 | <bitOffset>1</bitOffset> |
||
| 10434 | <bitWidth>1</bitWidth> |
||
| 10435 | <access>read-only</access> |
||
| 10436 | </field> |
||
| 10437 | <field> |
||
| 10438 | <name>RMVF</name> |
||
| 10439 | <description>Remove reset flag</description> |
||
| 10440 | <bitOffset>24</bitOffset> |
||
| 10441 | <bitWidth>1</bitWidth> |
||
| 10442 | <access>read-write</access> |
||
| 10443 | </field> |
||
| 10444 | <field> |
||
| 10445 | <name>OBLRSTF</name> |
||
| 10446 | <description>Option byte loader reset |
||
| 10447 | flag</description> |
||
| 10448 | <bitOffset>25</bitOffset> |
||
| 10449 | <bitWidth>1</bitWidth> |
||
| 10450 | <access>read-write</access> |
||
| 10451 | </field> |
||
| 10452 | <field> |
||
| 10453 | <name>PINRSTF</name> |
||
| 10454 | <description>PIN reset flag</description> |
||
| 10455 | <bitOffset>26</bitOffset> |
||
| 10456 | <bitWidth>1</bitWidth> |
||
| 10457 | <access>read-write</access> |
||
| 10458 | </field> |
||
| 10459 | <field> |
||
| 10460 | <name>PORRSTF</name> |
||
| 10461 | <description>POR/PDR reset flag</description> |
||
| 10462 | <bitOffset>27</bitOffset> |
||
| 10463 | <bitWidth>1</bitWidth> |
||
| 10464 | <access>read-write</access> |
||
| 10465 | </field> |
||
| 10466 | <field> |
||
| 10467 | <name>SFTRSTF</name> |
||
| 10468 | <description>Software reset flag</description> |
||
| 10469 | <bitOffset>28</bitOffset> |
||
| 10470 | <bitWidth>1</bitWidth> |
||
| 10471 | <access>read-write</access> |
||
| 10472 | </field> |
||
| 10473 | <field> |
||
| 10474 | <name>IWDGRSTF</name> |
||
| 10475 | <description>Independent watchdog reset |
||
| 10476 | flag</description> |
||
| 10477 | <bitOffset>29</bitOffset> |
||
| 10478 | <bitWidth>1</bitWidth> |
||
| 10479 | <access>read-write</access> |
||
| 10480 | </field> |
||
| 10481 | <field> |
||
| 10482 | <name>WWDGRSTF</name> |
||
| 10483 | <description>Window watchdog reset flag</description> |
||
| 10484 | <bitOffset>30</bitOffset> |
||
| 10485 | <bitWidth>1</bitWidth> |
||
| 10486 | <access>read-write</access> |
||
| 10487 | </field> |
||
| 10488 | <field> |
||
| 10489 | <name>LPWRRSTF</name> |
||
| 10490 | <description>Low-power reset flag</description> |
||
| 10491 | <bitOffset>31</bitOffset> |
||
| 10492 | <bitWidth>1</bitWidth> |
||
| 10493 | <access>read-write</access> |
||
| 10494 | </field> |
||
| 10495 | </fields> |
||
| 10496 | </register> |
||
| 10497 | <register> |
||
| 10498 | <name>AHBRSTR</name> |
||
| 10499 | <displayName>AHBRSTR</displayName> |
||
| 10500 | <description>AHB peripheral reset register</description> |
||
| 10501 | <addressOffset>0x28</addressOffset> |
||
| 10502 | <size>0x20</size> |
||
| 10503 | <access>read-write</access> |
||
| 10504 | <resetValue>0x00000000</resetValue> |
||
| 10505 | <fields> |
||
| 10506 | <field> |
||
| 10507 | <name>IOPARST</name> |
||
| 10508 | <description>I/O port A reset</description> |
||
| 10509 | <bitOffset>17</bitOffset> |
||
| 10510 | <bitWidth>1</bitWidth> |
||
| 10511 | </field> |
||
| 10512 | <field> |
||
| 10513 | <name>IOPBRST</name> |
||
| 10514 | <description>I/O port B reset</description> |
||
| 10515 | <bitOffset>18</bitOffset> |
||
| 10516 | <bitWidth>1</bitWidth> |
||
| 10517 | </field> |
||
| 10518 | <field> |
||
| 10519 | <name>IOPCRST</name> |
||
| 10520 | <description>I/O port C reset</description> |
||
| 10521 | <bitOffset>19</bitOffset> |
||
| 10522 | <bitWidth>1</bitWidth> |
||
| 10523 | </field> |
||
| 10524 | <field> |
||
| 10525 | <name>IOPDRST</name> |
||
| 10526 | <description>I/O port D reset</description> |
||
| 10527 | <bitOffset>20</bitOffset> |
||
| 10528 | <bitWidth>1</bitWidth> |
||
| 10529 | </field> |
||
| 10530 | <field> |
||
| 10531 | <name>IOPFRST</name> |
||
| 10532 | <description>I/O port F reset</description> |
||
| 10533 | <bitOffset>22</bitOffset> |
||
| 10534 | <bitWidth>1</bitWidth> |
||
| 10535 | </field> |
||
| 10536 | </fields> |
||
| 10537 | </register> |
||
| 10538 | <register> |
||
| 10539 | <name>CFGR2</name> |
||
| 10540 | <displayName>CFGR2</displayName> |
||
| 10541 | <description>Clock configuration register 2</description> |
||
| 10542 | <addressOffset>0x2C</addressOffset> |
||
| 10543 | <size>0x20</size> |
||
| 10544 | <access>read-write</access> |
||
| 10545 | <resetValue>0x00000000</resetValue> |
||
| 10546 | <fields> |
||
| 10547 | <field> |
||
| 10548 | <name>PREDIV</name> |
||
| 10549 | <description>PREDIV division factor</description> |
||
| 10550 | <bitOffset>0</bitOffset> |
||
| 10551 | <bitWidth>4</bitWidth> |
||
| 10552 | </field> |
||
| 10553 | </fields> |
||
| 10554 | </register> |
||
| 10555 | <register> |
||
| 10556 | <name>CFGR3</name> |
||
| 10557 | <displayName>CFGR3</displayName> |
||
| 10558 | <description>Clock configuration register 3</description> |
||
| 10559 | <addressOffset>0x30</addressOffset> |
||
| 10560 | <size>0x20</size> |
||
| 10561 | <access>read-write</access> |
||
| 10562 | <resetValue>0x00000000</resetValue> |
||
| 10563 | <fields> |
||
| 10564 | <field> |
||
| 10565 | <name>USART1SW</name> |
||
| 10566 | <description>USART1 clock source |
||
| 10567 | selection</description> |
||
| 10568 | <bitOffset>0</bitOffset> |
||
| 10569 | <bitWidth>2</bitWidth> |
||
| 10570 | </field> |
||
| 10571 | <field> |
||
| 10572 | <name>I2C1SW</name> |
||
| 10573 | <description>I2C1 clock source |
||
| 10574 | selection</description> |
||
| 10575 | <bitOffset>4</bitOffset> |
||
| 10576 | <bitWidth>1</bitWidth> |
||
| 10577 | </field> |
||
| 10578 | <field> |
||
| 10579 | <name>ADCSW</name> |
||
| 10580 | <description>ADC clock source selection</description> |
||
| 10581 | <bitOffset>8</bitOffset> |
||
| 10582 | <bitWidth>1</bitWidth> |
||
| 10583 | </field> |
||
| 10584 | <field> |
||
| 10585 | <name>USART2SW</name> |
||
| 10586 | <description>USART2 clock source |
||
| 10587 | selection</description> |
||
| 10588 | <bitOffset>16</bitOffset> |
||
| 10589 | <bitWidth>2</bitWidth> |
||
| 10590 | </field> |
||
| 10591 | </fields> |
||
| 10592 | </register> |
||
| 10593 | <register> |
||
| 10594 | <name>CR2</name> |
||
| 10595 | <displayName>CR2</displayName> |
||
| 10596 | <description>Clock control register 2</description> |
||
| 10597 | <addressOffset>0x34</addressOffset> |
||
| 10598 | <size>0x20</size> |
||
| 10599 | <resetValue>0x00000080</resetValue> |
||
| 10600 | <fields> |
||
| 10601 | <field> |
||
| 10602 | <name>HSI14ON</name> |
||
| 10603 | <description>HSI14 clock enable</description> |
||
| 10604 | <bitOffset>0</bitOffset> |
||
| 10605 | <bitWidth>1</bitWidth> |
||
| 10606 | <access>read-write</access> |
||
| 10607 | </field> |
||
| 10608 | <field> |
||
| 10609 | <name>HSI14RDY</name> |
||
| 10610 | <description>HR14 clock ready flag</description> |
||
| 10611 | <bitOffset>1</bitOffset> |
||
| 10612 | <bitWidth>1</bitWidth> |
||
| 10613 | <access>read-only</access> |
||
| 10614 | </field> |
||
| 10615 | <field> |
||
| 10616 | <name>HSI14DIS</name> |
||
| 10617 | <description>HSI14 clock request from ADC |
||
| 10618 | disable</description> |
||
| 10619 | <bitOffset>2</bitOffset> |
||
| 10620 | <bitWidth>1</bitWidth> |
||
| 10621 | <access>read-write</access> |
||
| 10622 | </field> |
||
| 10623 | <field> |
||
| 10624 | <name>HSI14TRIM</name> |
||
| 10625 | <description>HSI14 clock trimming</description> |
||
| 10626 | <bitOffset>3</bitOffset> |
||
| 10627 | <bitWidth>5</bitWidth> |
||
| 10628 | <access>read-write</access> |
||
| 10629 | </field> |
||
| 10630 | <field> |
||
| 10631 | <name>HSI14CAL</name> |
||
| 10632 | <description>HSI14 clock calibration</description> |
||
| 10633 | <bitOffset>8</bitOffset> |
||
| 10634 | <bitWidth>8</bitWidth> |
||
| 10635 | <access>read-only</access> |
||
| 10636 | </field> |
||
| 10637 | <field> |
||
| 10638 | <name>HSI48ON</name> |
||
| 10639 | <description>HSI48 clock enable</description> |
||
| 10640 | <bitOffset>16</bitOffset> |
||
| 10641 | <bitWidth>1</bitWidth> |
||
| 10642 | <access>read-write</access> |
||
| 10643 | </field> |
||
| 10644 | <field> |
||
| 10645 | <name>HSI48RDY</name> |
||
| 10646 | <description>HSI48 clock ready flag</description> |
||
| 10647 | <bitOffset>17</bitOffset> |
||
| 10648 | <bitWidth>1</bitWidth> |
||
| 10649 | <access>read-only</access> |
||
| 10650 | </field> |
||
| 10651 | <field> |
||
| 10652 | <name>HSI48CAL</name> |
||
| 10653 | <description>HSI48 factory clock |
||
| 10654 | calibration</description> |
||
| 10655 | <bitOffset>24</bitOffset> |
||
| 10656 | <bitWidth>1</bitWidth> |
||
| 10657 | <access>read-only</access> |
||
| 10658 | </field> |
||
| 10659 | </fields> |
||
| 10660 | </register> |
||
| 10661 | </registers> |
||
| 10662 | </peripheral> |
||
| 10663 | <peripheral> |
||
| 10664 | <name>SYSCFG</name> |
||
| 10665 | <description>System configuration controller</description> |
||
| 10666 | <groupName>SYSCFG</groupName> |
||
| 10667 | <baseAddress>0x40010000</baseAddress> |
||
| 10668 | <addressBlock> |
||
| 10669 | <offset>0x0</offset> |
||
| 10670 | <size>0x400</size> |
||
| 10671 | <usage>registers</usage> |
||
| 10672 | </addressBlock> |
||
| 10673 | <registers> |
||
| 10674 | <register> |
||
| 10675 | <name>CFGR1</name> |
||
| 10676 | <displayName>CFGR1</displayName> |
||
| 10677 | <description>configuration register 1</description> |
||
| 10678 | <addressOffset>0x0</addressOffset> |
||
| 10679 | <size>0x20</size> |
||
| 10680 | <access>read-write</access> |
||
| 10681 | <resetValue>0x00000000</resetValue> |
||
| 10682 | <fields> |
||
| 10683 | <field> |
||
| 10684 | <name>MEM_MODE</name> |
||
| 10685 | <description>Memory mapping selection |
||
| 10686 | bits</description> |
||
| 10687 | <bitOffset>0</bitOffset> |
||
| 10688 | <bitWidth>2</bitWidth> |
||
| 10689 | </field> |
||
| 10690 | <field> |
||
| 10691 | <name>ADC_DMA_RMP</name> |
||
| 10692 | <description>ADC DMA remapping bit</description> |
||
| 10693 | <bitOffset>8</bitOffset> |
||
| 10694 | <bitWidth>1</bitWidth> |
||
| 10695 | </field> |
||
| 10696 | <field> |
||
| 10697 | <name>USART1_TX_DMA_RMP</name> |
||
| 10698 | <description>USART1_TX DMA remapping |
||
| 10699 | bit</description> |
||
| 10700 | <bitOffset>9</bitOffset> |
||
| 10701 | <bitWidth>1</bitWidth> |
||
| 10702 | </field> |
||
| 10703 | <field> |
||
| 10704 | <name>USART1_RX_DMA_RMP</name> |
||
| 10705 | <description>USART1_RX DMA request remapping |
||
| 10706 | bit</description> |
||
| 10707 | <bitOffset>10</bitOffset> |
||
| 10708 | <bitWidth>1</bitWidth> |
||
| 10709 | </field> |
||
| 10710 | <field> |
||
| 10711 | <name>TIM16_DMA_RMP</name> |
||
| 10712 | <description>TIM16 DMA request remapping |
||
| 10713 | bit</description> |
||
| 10714 | <bitOffset>11</bitOffset> |
||
| 10715 | <bitWidth>1</bitWidth> |
||
| 10716 | </field> |
||
| 10717 | <field> |
||
| 10718 | <name>TIM17_DMA_RMP</name> |
||
| 10719 | <description>TIM17 DMA request remapping |
||
| 10720 | bit</description> |
||
| 10721 | <bitOffset>12</bitOffset> |
||
| 10722 | <bitWidth>1</bitWidth> |
||
| 10723 | </field> |
||
| 10724 | <field> |
||
| 10725 | <name>I2C_PB6_FM</name> |
||
| 10726 | <description>Fast Mode Plus (FM plus) driving |
||
| 10727 | capability activation bits.</description> |
||
| 10728 | <bitOffset>16</bitOffset> |
||
| 10729 | <bitWidth>1</bitWidth> |
||
| 10730 | </field> |
||
| 10731 | <field> |
||
| 10732 | <name>I2C_PB7_FM</name> |
||
| 10733 | <description>Fast Mode Plus (FM+) driving capability |
||
| 10734 | activation bits.</description> |
||
| 10735 | <bitOffset>17</bitOffset> |
||
| 10736 | <bitWidth>1</bitWidth> |
||
| 10737 | </field> |
||
| 10738 | <field> |
||
| 10739 | <name>I2C_PB8_FM</name> |
||
| 10740 | <description>Fast Mode Plus (FM+) driving capability |
||
| 10741 | activation bits.</description> |
||
| 10742 | <bitOffset>18</bitOffset> |
||
| 10743 | <bitWidth>1</bitWidth> |
||
| 10744 | </field> |
||
| 10745 | <field> |
||
| 10746 | <name>I2C_PB9_FM</name> |
||
| 10747 | <description>Fast Mode Plus (FM+) driving capability |
||
| 10748 | activation bits.</description> |
||
| 10749 | <bitOffset>19</bitOffset> |
||
| 10750 | <bitWidth>1</bitWidth> |
||
| 10751 | </field> |
||
| 10752 | <field> |
||
| 10753 | <name>I2C1_FM_plus</name> |
||
| 10754 | <description>FM+ driving capability activation for |
||
| 10755 | I2C1</description> |
||
| 10756 | <bitOffset>20</bitOffset> |
||
| 10757 | <bitWidth>1</bitWidth> |
||
| 10758 | </field> |
||
| 10759 | <field> |
||
| 10760 | <name>I2C2_FM_plus</name> |
||
| 10761 | <description>FM+ driving capability activation for |
||
| 10762 | I2C2</description> |
||
| 10763 | <bitOffset>21</bitOffset> |
||
| 10764 | <bitWidth>1</bitWidth> |
||
| 10765 | </field> |
||
| 10766 | <field> |
||
| 10767 | <name>SPI2_DMA_RMP</name> |
||
| 10768 | <description>SPI2 DMA request remapping |
||
| 10769 | bit</description> |
||
| 10770 | <bitOffset>24</bitOffset> |
||
| 10771 | <bitWidth>1</bitWidth> |
||
| 10772 | </field> |
||
| 10773 | <field> |
||
| 10774 | <name>USART2_DMA_RMP</name> |
||
| 10775 | <description>USART2 DMA request remapping |
||
| 10776 | bit</description> |
||
| 10777 | <bitOffset>25</bitOffset> |
||
| 10778 | <bitWidth>1</bitWidth> |
||
| 10779 | </field> |
||
| 10780 | <field> |
||
| 10781 | <name>USART3_DMA_RMP</name> |
||
| 10782 | <description>USART3 DMA request remapping |
||
| 10783 | bit</description> |
||
| 10784 | <bitOffset>26</bitOffset> |
||
| 10785 | <bitWidth>1</bitWidth> |
||
| 10786 | </field> |
||
| 10787 | <field> |
||
| 10788 | <name>I2C1_DMA_RMP</name> |
||
| 10789 | <description>I2C1 DMA request remapping |
||
| 10790 | bit</description> |
||
| 10791 | <bitOffset>27</bitOffset> |
||
| 10792 | <bitWidth>1</bitWidth> |
||
| 10793 | </field> |
||
| 10794 | <field> |
||
| 10795 | <name>TIM1_DMA_RMP</name> |
||
| 10796 | <description>TIM1 DMA request remapping |
||
| 10797 | bit</description> |
||
| 10798 | <bitOffset>28</bitOffset> |
||
| 10799 | <bitWidth>1</bitWidth> |
||
| 10800 | </field> |
||
| 10801 | <field> |
||
| 10802 | <name>TIM2_DMA_RMP</name> |
||
| 10803 | <description>TIM2 DMA request remapping |
||
| 10804 | bit</description> |
||
| 10805 | <bitOffset>29</bitOffset> |
||
| 10806 | <bitWidth>1</bitWidth> |
||
| 10807 | </field> |
||
| 10808 | <field> |
||
| 10809 | <name>TIM3_DMA_RMP</name> |
||
| 10810 | <description>TIM3 DMA request remapping |
||
| 10811 | bit</description> |
||
| 10812 | <bitOffset>30</bitOffset> |
||
| 10813 | <bitWidth>1</bitWidth> |
||
| 10814 | </field> |
||
| 10815 | </fields> |
||
| 10816 | </register> |
||
| 10817 | <register> |
||
| 10818 | <name>EXTICR1</name> |
||
| 10819 | <displayName>EXTICR1</displayName> |
||
| 10820 | <description>external interrupt configuration register |
||
| 10821 | 1</description> |
||
| 10822 | <addressOffset>0x8</addressOffset> |
||
| 10823 | <size>0x20</size> |
||
| 10824 | <access>read-write</access> |
||
| 10825 | <resetValue>0x0000</resetValue> |
||
| 10826 | <fields> |
||
| 10827 | <field> |
||
| 10828 | <name>EXTI3</name> |
||
| 10829 | <description>EXTI 3 configuration bits</description> |
||
| 10830 | <bitOffset>12</bitOffset> |
||
| 10831 | <bitWidth>4</bitWidth> |
||
| 10832 | </field> |
||
| 10833 | <field> |
||
| 10834 | <name>EXTI2</name> |
||
| 10835 | <description>EXTI 2 configuration bits</description> |
||
| 10836 | <bitOffset>8</bitOffset> |
||
| 10837 | <bitWidth>4</bitWidth> |
||
| 10838 | </field> |
||
| 10839 | <field> |
||
| 10840 | <name>EXTI1</name> |
||
| 10841 | <description>EXTI 1 configuration bits</description> |
||
| 10842 | <bitOffset>4</bitOffset> |
||
| 10843 | <bitWidth>4</bitWidth> |
||
| 10844 | </field> |
||
| 10845 | <field> |
||
| 10846 | <name>EXTI0</name> |
||
| 10847 | <description>EXTI 0 configuration bits</description> |
||
| 10848 | <bitOffset>0</bitOffset> |
||
| 10849 | <bitWidth>4</bitWidth> |
||
| 10850 | </field> |
||
| 10851 | </fields> |
||
| 10852 | </register> |
||
| 10853 | <register> |
||
| 10854 | <name>EXTICR2</name> |
||
| 10855 | <displayName>EXTICR2</displayName> |
||
| 10856 | <description>external interrupt configuration register |
||
| 10857 | 2</description> |
||
| 10858 | <addressOffset>0xC</addressOffset> |
||
| 10859 | <size>0x20</size> |
||
| 10860 | <access>read-write</access> |
||
| 10861 | <resetValue>0x0000</resetValue> |
||
| 10862 | <fields> |
||
| 10863 | <field> |
||
| 10864 | <name>EXTI7</name> |
||
| 10865 | <description>EXTI 7 configuration bits</description> |
||
| 10866 | <bitOffset>12</bitOffset> |
||
| 10867 | <bitWidth>4</bitWidth> |
||
| 10868 | </field> |
||
| 10869 | <field> |
||
| 10870 | <name>EXTI6</name> |
||
| 10871 | <description>EXTI 6 configuration bits</description> |
||
| 10872 | <bitOffset>8</bitOffset> |
||
| 10873 | <bitWidth>4</bitWidth> |
||
| 10874 | </field> |
||
| 10875 | <field> |
||
| 10876 | <name>EXTI5</name> |
||
| 10877 | <description>EXTI 5 configuration bits</description> |
||
| 10878 | <bitOffset>4</bitOffset> |
||
| 10879 | <bitWidth>4</bitWidth> |
||
| 10880 | </field> |
||
| 10881 | <field> |
||
| 10882 | <name>EXTI4</name> |
||
| 10883 | <description>EXTI 4 configuration bits</description> |
||
| 10884 | <bitOffset>0</bitOffset> |
||
| 10885 | <bitWidth>4</bitWidth> |
||
| 10886 | </field> |
||
| 10887 | </fields> |
||
| 10888 | </register> |
||
| 10889 | <register> |
||
| 10890 | <name>EXTICR3</name> |
||
| 10891 | <displayName>EXTICR3</displayName> |
||
| 10892 | <description>external interrupt configuration register |
||
| 10893 | 3</description> |
||
| 10894 | <addressOffset>0x10</addressOffset> |
||
| 10895 | <size>0x20</size> |
||
| 10896 | <access>read-write</access> |
||
| 10897 | <resetValue>0x0000</resetValue> |
||
| 10898 | <fields> |
||
| 10899 | <field> |
||
| 10900 | <name>EXTI11</name> |
||
| 10901 | <description>EXTI 11 configuration bits</description> |
||
| 10902 | <bitOffset>12</bitOffset> |
||
| 10903 | <bitWidth>4</bitWidth> |
||
| 10904 | </field> |
||
| 10905 | <field> |
||
| 10906 | <name>EXTI10</name> |
||
| 10907 | <description>EXTI 10 configuration bits</description> |
||
| 10908 | <bitOffset>8</bitOffset> |
||
| 10909 | <bitWidth>4</bitWidth> |
||
| 10910 | </field> |
||
| 10911 | <field> |
||
| 10912 | <name>EXTI9</name> |
||
| 10913 | <description>EXTI 9 configuration bits</description> |
||
| 10914 | <bitOffset>4</bitOffset> |
||
| 10915 | <bitWidth>4</bitWidth> |
||
| 10916 | </field> |
||
| 10917 | <field> |
||
| 10918 | <name>EXTI8</name> |
||
| 10919 | <description>EXTI 8 configuration bits</description> |
||
| 10920 | <bitOffset>0</bitOffset> |
||
| 10921 | <bitWidth>4</bitWidth> |
||
| 10922 | </field> |
||
| 10923 | </fields> |
||
| 10924 | </register> |
||
| 10925 | <register> |
||
| 10926 | <name>EXTICR4</name> |
||
| 10927 | <displayName>EXTICR4</displayName> |
||
| 10928 | <description>external interrupt configuration register |
||
| 10929 | 4</description> |
||
| 10930 | <addressOffset>0x14</addressOffset> |
||
| 10931 | <size>0x20</size> |
||
| 10932 | <access>read-write</access> |
||
| 10933 | <resetValue>0x0000</resetValue> |
||
| 10934 | <fields> |
||
| 10935 | <field> |
||
| 10936 | <name>EXTI15</name> |
||
| 10937 | <description>EXTI 15 configuration bits</description> |
||
| 10938 | <bitOffset>12</bitOffset> |
||
| 10939 | <bitWidth>4</bitWidth> |
||
| 10940 | </field> |
||
| 10941 | <field> |
||
| 10942 | <name>EXTI14</name> |
||
| 10943 | <description>EXTI 14 configuration bits</description> |
||
| 10944 | <bitOffset>8</bitOffset> |
||
| 10945 | <bitWidth>4</bitWidth> |
||
| 10946 | </field> |
||
| 10947 | <field> |
||
| 10948 | <name>EXTI13</name> |
||
| 10949 | <description>EXTI 13 configuration bits</description> |
||
| 10950 | <bitOffset>4</bitOffset> |
||
| 10951 | <bitWidth>4</bitWidth> |
||
| 10952 | </field> |
||
| 10953 | <field> |
||
| 10954 | <name>EXTI12</name> |
||
| 10955 | <description>EXTI 12 configuration bits</description> |
||
| 10956 | <bitOffset>0</bitOffset> |
||
| 10957 | <bitWidth>4</bitWidth> |
||
| 10958 | </field> |
||
| 10959 | </fields> |
||
| 10960 | </register> |
||
| 10961 | <register> |
||
| 10962 | <name>CFGR2</name> |
||
| 10963 | <displayName>CFGR2</displayName> |
||
| 10964 | <description>configuration register 2</description> |
||
| 10965 | <addressOffset>0x18</addressOffset> |
||
| 10966 | <size>0x20</size> |
||
| 10967 | <access>read-write</access> |
||
| 10968 | <resetValue>0x0000</resetValue> |
||
| 10969 | <fields> |
||
| 10970 | <field> |
||
| 10971 | <name>SRAM_PEF</name> |
||
| 10972 | <description>SRAM parity flag</description> |
||
| 10973 | <bitOffset>8</bitOffset> |
||
| 10974 | <bitWidth>1</bitWidth> |
||
| 10975 | </field> |
||
| 10976 | <field> |
||
| 10977 | <name>PVD_LOCK</name> |
||
| 10978 | <description>PVD lock enable bit</description> |
||
| 10979 | <bitOffset>2</bitOffset> |
||
| 10980 | <bitWidth>1</bitWidth> |
||
| 10981 | </field> |
||
| 10982 | <field> |
||
| 10983 | <name>SRAM_PARITY_LOCK</name> |
||
| 10984 | <description>SRAM parity lock bit</description> |
||
| 10985 | <bitOffset>1</bitOffset> |
||
| 10986 | <bitWidth>1</bitWidth> |
||
| 10987 | </field> |
||
| 10988 | <field> |
||
| 10989 | <name>LOCUP_LOCK</name> |
||
| 10990 | <description>Cortex-M0 LOCKUP bit enable |
||
| 10991 | bit</description> |
||
| 10992 | <bitOffset>0</bitOffset> |
||
| 10993 | <bitWidth>1</bitWidth> |
||
| 10994 | </field> |
||
| 10995 | </fields> |
||
| 10996 | </register> |
||
| 10997 | </registers> |
||
| 10998 | </peripheral> |
||
| 10999 | <peripheral> |
||
| 11000 | <name>ADC</name> |
||
| 11001 | <description>Analog-to-digital converter</description> |
||
| 11002 | <groupName>ADC</groupName> |
||
| 11003 | <baseAddress>0x40012400</baseAddress> |
||
| 11004 | <addressBlock> |
||
| 11005 | <offset>0x0</offset> |
||
| 11006 | <size>0x400</size> |
||
| 11007 | <usage>registers</usage> |
||
| 11008 | </addressBlock> |
||
| 11009 | <interrupt> |
||
| 11010 | <name>DMA_CH1</name> |
||
| 11011 | <description>DMA channel 1 interrupt</description> |
||
| 11012 | <value>9</value> |
||
| 11013 | </interrupt> |
||
| 11014 | <interrupt> |
||
| 11015 | <name>DMA_CH2_3</name> |
||
| 11016 | <description>DMA channel 2 and 3 interrupts</description> |
||
| 11017 | <value>10</value> |
||
| 11018 | </interrupt> |
||
| 11019 | <interrupt> |
||
| 11020 | <name>DMA_CH4_5_6_7</name> |
||
| 11021 | <description>DMA channel 4, 5, 6 and 7 |
||
| 11022 | interrupts</description> |
||
| 11023 | <value>11</value> |
||
| 11024 | </interrupt> |
||
| 11025 | <registers> |
||
| 11026 | <register> |
||
| 11027 | <name>ISR</name> |
||
| 11028 | <displayName>ISR</displayName> |
||
| 11029 | <description>interrupt and status register</description> |
||
| 11030 | <addressOffset>0x0</addressOffset> |
||
| 11031 | <size>0x20</size> |
||
| 11032 | <access>read-write</access> |
||
| 11033 | <resetValue>0x00000000</resetValue> |
||
| 11034 | <fields> |
||
| 11035 | <field> |
||
| 11036 | <name>AWD</name> |
||
| 11037 | <description>Analog watchdog flag</description> |
||
| 11038 | <bitOffset>7</bitOffset> |
||
| 11039 | <bitWidth>1</bitWidth> |
||
| 11040 | </field> |
||
| 11041 | <field> |
||
| 11042 | <name>OVR</name> |
||
| 11043 | <description>ADC overrun</description> |
||
| 11044 | <bitOffset>4</bitOffset> |
||
| 11045 | <bitWidth>1</bitWidth> |
||
| 11046 | </field> |
||
| 11047 | <field> |
||
| 11048 | <name>EOS</name> |
||
| 11049 | <description>End of sequence flag</description> |
||
| 11050 | <bitOffset>3</bitOffset> |
||
| 11051 | <bitWidth>1</bitWidth> |
||
| 11052 | </field> |
||
| 11053 | <field> |
||
| 11054 | <name>EOC</name> |
||
| 11055 | <description>End of conversion flag</description> |
||
| 11056 | <bitOffset>2</bitOffset> |
||
| 11057 | <bitWidth>1</bitWidth> |
||
| 11058 | </field> |
||
| 11059 | <field> |
||
| 11060 | <name>EOSMP</name> |
||
| 11061 | <description>End of sampling flag</description> |
||
| 11062 | <bitOffset>1</bitOffset> |
||
| 11063 | <bitWidth>1</bitWidth> |
||
| 11064 | </field> |
||
| 11065 | <field> |
||
| 11066 | <name>ADRDY</name> |
||
| 11067 | <description>ADC ready</description> |
||
| 11068 | <bitOffset>0</bitOffset> |
||
| 11069 | <bitWidth>1</bitWidth> |
||
| 11070 | </field> |
||
| 11071 | </fields> |
||
| 11072 | </register> |
||
| 11073 | <register> |
||
| 11074 | <name>IER</name> |
||
| 11075 | <displayName>IER</displayName> |
||
| 11076 | <description>interrupt enable register</description> |
||
| 11077 | <addressOffset>0x4</addressOffset> |
||
| 11078 | <size>0x20</size> |
||
| 11079 | <access>read-write</access> |
||
| 11080 | <resetValue>0x00000000</resetValue> |
||
| 11081 | <fields> |
||
| 11082 | <field> |
||
| 11083 | <name>AWDIE</name> |
||
| 11084 | <description>Analog watchdog interrupt |
||
| 11085 | enable</description> |
||
| 11086 | <bitOffset>7</bitOffset> |
||
| 11087 | <bitWidth>1</bitWidth> |
||
| 11088 | </field> |
||
| 11089 | <field> |
||
| 11090 | <name>OVRIE</name> |
||
| 11091 | <description>Overrun interrupt enable</description> |
||
| 11092 | <bitOffset>4</bitOffset> |
||
| 11093 | <bitWidth>1</bitWidth> |
||
| 11094 | </field> |
||
| 11095 | <field> |
||
| 11096 | <name>EOSIE</name> |
||
| 11097 | <description>End of conversion sequence interrupt |
||
| 11098 | enable</description> |
||
| 11099 | <bitOffset>3</bitOffset> |
||
| 11100 | <bitWidth>1</bitWidth> |
||
| 11101 | </field> |
||
| 11102 | <field> |
||
| 11103 | <name>EOCIE</name> |
||
| 11104 | <description>End of conversion interrupt |
||
| 11105 | enable</description> |
||
| 11106 | <bitOffset>2</bitOffset> |
||
| 11107 | <bitWidth>1</bitWidth> |
||
| 11108 | </field> |
||
| 11109 | <field> |
||
| 11110 | <name>EOSMPIE</name> |
||
| 11111 | <description>End of sampling flag interrupt |
||
| 11112 | enable</description> |
||
| 11113 | <bitOffset>1</bitOffset> |
||
| 11114 | <bitWidth>1</bitWidth> |
||
| 11115 | </field> |
||
| 11116 | <field> |
||
| 11117 | <name>ADRDYIE</name> |
||
| 11118 | <description>ADC ready interrupt enable</description> |
||
| 11119 | <bitOffset>0</bitOffset> |
||
| 11120 | <bitWidth>1</bitWidth> |
||
| 11121 | </field> |
||
| 11122 | </fields> |
||
| 11123 | </register> |
||
| 11124 | <register> |
||
| 11125 | <name>CR</name> |
||
| 11126 | <displayName>CR</displayName> |
||
| 11127 | <description>control register</description> |
||
| 11128 | <addressOffset>0x8</addressOffset> |
||
| 11129 | <size>0x20</size> |
||
| 11130 | <access>read-write</access> |
||
| 11131 | <resetValue>0x00000000</resetValue> |
||
| 11132 | <fields> |
||
| 11133 | <field> |
||
| 11134 | <name>ADCAL</name> |
||
| 11135 | <description>ADC calibration</description> |
||
| 11136 | <bitOffset>31</bitOffset> |
||
| 11137 | <bitWidth>1</bitWidth> |
||
| 11138 | </field> |
||
| 11139 | <field> |
||
| 11140 | <name>ADSTP</name> |
||
| 11141 | <description>ADC stop conversion |
||
| 11142 | command</description> |
||
| 11143 | <bitOffset>4</bitOffset> |
||
| 11144 | <bitWidth>1</bitWidth> |
||
| 11145 | </field> |
||
| 11146 | <field> |
||
| 11147 | <name>ADSTART</name> |
||
| 11148 | <description>ADC start conversion |
||
| 11149 | command</description> |
||
| 11150 | <bitOffset>2</bitOffset> |
||
| 11151 | <bitWidth>1</bitWidth> |
||
| 11152 | </field> |
||
| 11153 | <field> |
||
| 11154 | <name>ADDIS</name> |
||
| 11155 | <description>ADC disable command</description> |
||
| 11156 | <bitOffset>1</bitOffset> |
||
| 11157 | <bitWidth>1</bitWidth> |
||
| 11158 | </field> |
||
| 11159 | <field> |
||
| 11160 | <name>ADEN</name> |
||
| 11161 | <description>ADC enable command</description> |
||
| 11162 | <bitOffset>0</bitOffset> |
||
| 11163 | <bitWidth>1</bitWidth> |
||
| 11164 | </field> |
||
| 11165 | </fields> |
||
| 11166 | </register> |
||
| 11167 | <register> |
||
| 11168 | <name>CFGR1</name> |
||
| 11169 | <displayName>CFGR1</displayName> |
||
| 11170 | <description>configuration register 1</description> |
||
| 11171 | <addressOffset>0xC</addressOffset> |
||
| 11172 | <size>0x20</size> |
||
| 11173 | <access>read-write</access> |
||
| 11174 | <resetValue>0x00000000</resetValue> |
||
| 11175 | <fields> |
||
| 11176 | <field> |
||
| 11177 | <name>AWDCH</name> |
||
| 11178 | <description>Analog watchdog channel |
||
| 11179 | selection</description> |
||
| 11180 | <bitOffset>26</bitOffset> |
||
| 11181 | <bitWidth>5</bitWidth> |
||
| 11182 | </field> |
||
| 11183 | <field> |
||
| 11184 | <name>AWDEN</name> |
||
| 11185 | <description>Analog watchdog enable</description> |
||
| 11186 | <bitOffset>23</bitOffset> |
||
| 11187 | <bitWidth>1</bitWidth> |
||
| 11188 | </field> |
||
| 11189 | <field> |
||
| 11190 | <name>AWDSGL</name> |
||
| 11191 | <description>Enable the watchdog on a single channel |
||
| 11192 | or on all channels</description> |
||
| 11193 | <bitOffset>22</bitOffset> |
||
| 11194 | <bitWidth>1</bitWidth> |
||
| 11195 | </field> |
||
| 11196 | <field> |
||
| 11197 | <name>DISCEN</name> |
||
| 11198 | <description>Discontinuous mode</description> |
||
| 11199 | <bitOffset>16</bitOffset> |
||
| 11200 | <bitWidth>1</bitWidth> |
||
| 11201 | </field> |
||
| 11202 | <field> |
||
| 11203 | <name>AUTOFF</name> |
||
| 11204 | <description>Auto-off mode</description> |
||
| 11205 | <bitOffset>15</bitOffset> |
||
| 11206 | <bitWidth>1</bitWidth> |
||
| 11207 | </field> |
||
| 11208 | <field> |
||
| 11209 | <name>AUTDLY</name> |
||
| 11210 | <description>Auto-delayed conversion |
||
| 11211 | mode</description> |
||
| 11212 | <bitOffset>14</bitOffset> |
||
| 11213 | <bitWidth>1</bitWidth> |
||
| 11214 | </field> |
||
| 11215 | <field> |
||
| 11216 | <name>CONT</name> |
||
| 11217 | <description>Single / continuous conversion |
||
| 11218 | mode</description> |
||
| 11219 | <bitOffset>13</bitOffset> |
||
| 11220 | <bitWidth>1</bitWidth> |
||
| 11221 | </field> |
||
| 11222 | <field> |
||
| 11223 | <name>OVRMOD</name> |
||
| 11224 | <description>Overrun management mode</description> |
||
| 11225 | <bitOffset>12</bitOffset> |
||
| 11226 | <bitWidth>1</bitWidth> |
||
| 11227 | </field> |
||
| 11228 | <field> |
||
| 11229 | <name>EXTEN</name> |
||
| 11230 | <description>External trigger enable and polarity |
||
| 11231 | selection</description> |
||
| 11232 | <bitOffset>10</bitOffset> |
||
| 11233 | <bitWidth>2</bitWidth> |
||
| 11234 | </field> |
||
| 11235 | <field> |
||
| 11236 | <name>EXTSEL</name> |
||
| 11237 | <description>External trigger selection</description> |
||
| 11238 | <bitOffset>6</bitOffset> |
||
| 11239 | <bitWidth>3</bitWidth> |
||
| 11240 | </field> |
||
| 11241 | <field> |
||
| 11242 | <name>ALIGN</name> |
||
| 11243 | <description>Data alignment</description> |
||
| 11244 | <bitOffset>5</bitOffset> |
||
| 11245 | <bitWidth>1</bitWidth> |
||
| 11246 | </field> |
||
| 11247 | <field> |
||
| 11248 | <name>RES</name> |
||
| 11249 | <description>Data resolution</description> |
||
| 11250 | <bitOffset>3</bitOffset> |
||
| 11251 | <bitWidth>2</bitWidth> |
||
| 11252 | </field> |
||
| 11253 | <field> |
||
| 11254 | <name>SCANDIR</name> |
||
| 11255 | <description>Scan sequence direction</description> |
||
| 11256 | <bitOffset>2</bitOffset> |
||
| 11257 | <bitWidth>1</bitWidth> |
||
| 11258 | </field> |
||
| 11259 | <field> |
||
| 11260 | <name>DMACFG</name> |
||
| 11261 | <description>Direct memery access |
||
| 11262 | configuration</description> |
||
| 11263 | <bitOffset>1</bitOffset> |
||
| 11264 | <bitWidth>1</bitWidth> |
||
| 11265 | </field> |
||
| 11266 | <field> |
||
| 11267 | <name>DMAEN</name> |
||
| 11268 | <description>Direct memory access |
||
| 11269 | enable</description> |
||
| 11270 | <bitOffset>0</bitOffset> |
||
| 11271 | <bitWidth>1</bitWidth> |
||
| 11272 | </field> |
||
| 11273 | </fields> |
||
| 11274 | </register> |
||
| 11275 | <register> |
||
| 11276 | <name>CFGR2</name> |
||
| 11277 | <displayName>CFGR2</displayName> |
||
| 11278 | <description>configuration register 2</description> |
||
| 11279 | <addressOffset>0x10</addressOffset> |
||
| 11280 | <size>0x20</size> |
||
| 11281 | <access>read-write</access> |
||
| 11282 | <resetValue>0x00008000</resetValue> |
||
| 11283 | <fields> |
||
| 11284 | <field> |
||
| 11285 | <name>JITOFF_D4</name> |
||
| 11286 | <description>JITOFF_D4</description> |
||
| 11287 | <bitOffset>31</bitOffset> |
||
| 11288 | <bitWidth>1</bitWidth> |
||
| 11289 | </field> |
||
| 11290 | <field> |
||
| 11291 | <name>JITOFF_D2</name> |
||
| 11292 | <description>JITOFF_D2</description> |
||
| 11293 | <bitOffset>30</bitOffset> |
||
| 11294 | <bitWidth>1</bitWidth> |
||
| 11295 | </field> |
||
| 11296 | </fields> |
||
| 11297 | </register> |
||
| 11298 | <register> |
||
| 11299 | <name>SMPR</name> |
||
| 11300 | <displayName>SMPR</displayName> |
||
| 11301 | <description>sampling time register</description> |
||
| 11302 | <addressOffset>0x14</addressOffset> |
||
| 11303 | <size>0x20</size> |
||
| 11304 | <access>read-write</access> |
||
| 11305 | <resetValue>0x00000000</resetValue> |
||
| 11306 | <fields> |
||
| 11307 | <field> |
||
| 11308 | <name>SMPR</name> |
||
| 11309 | <description>Sampling time selection</description> |
||
| 11310 | <bitOffset>0</bitOffset> |
||
| 11311 | <bitWidth>3</bitWidth> |
||
| 11312 | </field> |
||
| 11313 | </fields> |
||
| 11314 | </register> |
||
| 11315 | <register> |
||
| 11316 | <name>TR</name> |
||
| 11317 | <displayName>TR</displayName> |
||
| 11318 | <description>watchdog threshold register</description> |
||
| 11319 | <addressOffset>0x20</addressOffset> |
||
| 11320 | <size>0x20</size> |
||
| 11321 | <access>read-write</access> |
||
| 11322 | <resetValue>0x00000FFF</resetValue> |
||
| 11323 | <fields> |
||
| 11324 | <field> |
||
| 11325 | <name>HT</name> |
||
| 11326 | <description>Analog watchdog higher |
||
| 11327 | threshold</description> |
||
| 11328 | <bitOffset>16</bitOffset> |
||
| 11329 | <bitWidth>12</bitWidth> |
||
| 11330 | </field> |
||
| 11331 | <field> |
||
| 11332 | <name>LT</name> |
||
| 11333 | <description>Analog watchdog lower |
||
| 11334 | threshold</description> |
||
| 11335 | <bitOffset>0</bitOffset> |
||
| 11336 | <bitWidth>12</bitWidth> |
||
| 11337 | </field> |
||
| 11338 | </fields> |
||
| 11339 | </register> |
||
| 11340 | <register> |
||
| 11341 | <name>CHSELR</name> |
||
| 11342 | <displayName>CHSELR</displayName> |
||
| 11343 | <description>channel selection register</description> |
||
| 11344 | <addressOffset>0x28</addressOffset> |
||
| 11345 | <size>0x20</size> |
||
| 11346 | <access>read-write</access> |
||
| 11347 | <resetValue>0x00000000</resetValue> |
||
| 11348 | <fields> |
||
| 11349 | <field> |
||
| 11350 | <name>CHSEL18</name> |
||
| 11351 | <description>Channel-x selection</description> |
||
| 11352 | <bitOffset>18</bitOffset> |
||
| 11353 | <bitWidth>1</bitWidth> |
||
| 11354 | </field> |
||
| 11355 | <field> |
||
| 11356 | <name>CHSEL17</name> |
||
| 11357 | <description>Channel-x selection</description> |
||
| 11358 | <bitOffset>17</bitOffset> |
||
| 11359 | <bitWidth>1</bitWidth> |
||
| 11360 | </field> |
||
| 11361 | <field> |
||
| 11362 | <name>CHSEL16</name> |
||
| 11363 | <description>Channel-x selection</description> |
||
| 11364 | <bitOffset>16</bitOffset> |
||
| 11365 | <bitWidth>1</bitWidth> |
||
| 11366 | </field> |
||
| 11367 | <field> |
||
| 11368 | <name>CHSEL15</name> |
||
| 11369 | <description>Channel-x selection</description> |
||
| 11370 | <bitOffset>15</bitOffset> |
||
| 11371 | <bitWidth>1</bitWidth> |
||
| 11372 | </field> |
||
| 11373 | <field> |
||
| 11374 | <name>CHSEL14</name> |
||
| 11375 | <description>Channel-x selection</description> |
||
| 11376 | <bitOffset>14</bitOffset> |
||
| 11377 | <bitWidth>1</bitWidth> |
||
| 11378 | </field> |
||
| 11379 | <field> |
||
| 11380 | <name>CHSEL13</name> |
||
| 11381 | <description>Channel-x selection</description> |
||
| 11382 | <bitOffset>13</bitOffset> |
||
| 11383 | <bitWidth>1</bitWidth> |
||
| 11384 | </field> |
||
| 11385 | <field> |
||
| 11386 | <name>CHSEL12</name> |
||
| 11387 | <description>Channel-x selection</description> |
||
| 11388 | <bitOffset>12</bitOffset> |
||
| 11389 | <bitWidth>1</bitWidth> |
||
| 11390 | </field> |
||
| 11391 | <field> |
||
| 11392 | <name>CHSEL11</name> |
||
| 11393 | <description>Channel-x selection</description> |
||
| 11394 | <bitOffset>11</bitOffset> |
||
| 11395 | <bitWidth>1</bitWidth> |
||
| 11396 | </field> |
||
| 11397 | <field> |
||
| 11398 | <name>CHSEL10</name> |
||
| 11399 | <description>Channel-x selection</description> |
||
| 11400 | <bitOffset>10</bitOffset> |
||
| 11401 | <bitWidth>1</bitWidth> |
||
| 11402 | </field> |
||
| 11403 | <field> |
||
| 11404 | <name>CHSEL9</name> |
||
| 11405 | <description>Channel-x selection</description> |
||
| 11406 | <bitOffset>9</bitOffset> |
||
| 11407 | <bitWidth>1</bitWidth> |
||
| 11408 | </field> |
||
| 11409 | <field> |
||
| 11410 | <name>CHSEL8</name> |
||
| 11411 | <description>Channel-x selection</description> |
||
| 11412 | <bitOffset>8</bitOffset> |
||
| 11413 | <bitWidth>1</bitWidth> |
||
| 11414 | </field> |
||
| 11415 | <field> |
||
| 11416 | <name>CHSEL7</name> |
||
| 11417 | <description>Channel-x selection</description> |
||
| 11418 | <bitOffset>7</bitOffset> |
||
| 11419 | <bitWidth>1</bitWidth> |
||
| 11420 | </field> |
||
| 11421 | <field> |
||
| 11422 | <name>CHSEL6</name> |
||
| 11423 | <description>Channel-x selection</description> |
||
| 11424 | <bitOffset>6</bitOffset> |
||
| 11425 | <bitWidth>1</bitWidth> |
||
| 11426 | </field> |
||
| 11427 | <field> |
||
| 11428 | <name>CHSEL5</name> |
||
| 11429 | <description>Channel-x selection</description> |
||
| 11430 | <bitOffset>5</bitOffset> |
||
| 11431 | <bitWidth>1</bitWidth> |
||
| 11432 | </field> |
||
| 11433 | <field> |
||
| 11434 | <name>CHSEL4</name> |
||
| 11435 | <description>Channel-x selection</description> |
||
| 11436 | <bitOffset>4</bitOffset> |
||
| 11437 | <bitWidth>1</bitWidth> |
||
| 11438 | </field> |
||
| 11439 | <field> |
||
| 11440 | <name>CHSEL3</name> |
||
| 11441 | <description>Channel-x selection</description> |
||
| 11442 | <bitOffset>3</bitOffset> |
||
| 11443 | <bitWidth>1</bitWidth> |
||
| 11444 | </field> |
||
| 11445 | <field> |
||
| 11446 | <name>CHSEL2</name> |
||
| 11447 | <description>Channel-x selection</description> |
||
| 11448 | <bitOffset>2</bitOffset> |
||
| 11449 | <bitWidth>1</bitWidth> |
||
| 11450 | </field> |
||
| 11451 | <field> |
||
| 11452 | <name>CHSEL1</name> |
||
| 11453 | <description>Channel-x selection</description> |
||
| 11454 | <bitOffset>1</bitOffset> |
||
| 11455 | <bitWidth>1</bitWidth> |
||
| 11456 | </field> |
||
| 11457 | <field> |
||
| 11458 | <name>CHSEL0</name> |
||
| 11459 | <description>Channel-x selection</description> |
||
| 11460 | <bitOffset>0</bitOffset> |
||
| 11461 | <bitWidth>1</bitWidth> |
||
| 11462 | </field> |
||
| 11463 | </fields> |
||
| 11464 | </register> |
||
| 11465 | <register> |
||
| 11466 | <name>DR</name> |
||
| 11467 | <displayName>DR</displayName> |
||
| 11468 | <description>data register</description> |
||
| 11469 | <addressOffset>0x40</addressOffset> |
||
| 11470 | <size>0x20</size> |
||
| 11471 | <access>read-only</access> |
||
| 11472 | <resetValue>0x00000000</resetValue> |
||
| 11473 | <fields> |
||
| 11474 | <field> |
||
| 11475 | <name>DATA</name> |
||
| 11476 | <description>Converted data</description> |
||
| 11477 | <bitOffset>0</bitOffset> |
||
| 11478 | <bitWidth>16</bitWidth> |
||
| 11479 | </field> |
||
| 11480 | </fields> |
||
| 11481 | </register> |
||
| 11482 | <register> |
||
| 11483 | <name>CCR</name> |
||
| 11484 | <displayName>CCR</displayName> |
||
| 11485 | <description>common configuration register</description> |
||
| 11486 | <addressOffset>0x308</addressOffset> |
||
| 11487 | <size>0x20</size> |
||
| 11488 | <access>read-write</access> |
||
| 11489 | <resetValue>0x00000000</resetValue> |
||
| 11490 | <fields> |
||
| 11491 | <field> |
||
| 11492 | <name>VBATEN</name> |
||
| 11493 | <description>VBAT enable</description> |
||
| 11494 | <bitOffset>24</bitOffset> |
||
| 11495 | <bitWidth>1</bitWidth> |
||
| 11496 | </field> |
||
| 11497 | <field> |
||
| 11498 | <name>TSEN</name> |
||
| 11499 | <description>Temperature sensor enable</description> |
||
| 11500 | <bitOffset>23</bitOffset> |
||
| 11501 | <bitWidth>1</bitWidth> |
||
| 11502 | </field> |
||
| 11503 | <field> |
||
| 11504 | <name>VREFEN</name> |
||
| 11505 | <description>Temperature sensor and VREFINT |
||
| 11506 | enable</description> |
||
| 11507 | <bitOffset>22</bitOffset> |
||
| 11508 | <bitWidth>1</bitWidth> |
||
| 11509 | </field> |
||
| 11510 | </fields> |
||
| 11511 | </register> |
||
| 11512 | </registers> |
||
| 11513 | </peripheral> |
||
| 11514 | <peripheral> |
||
| 11515 | <name>USART1</name> |
||
| 11516 | <description>Universal synchronous asynchronous receiver |
||
| 11517 | transmitter</description> |
||
| 11518 | <groupName>USART</groupName> |
||
| 11519 | <baseAddress>0x40013800</baseAddress> |
||
| 11520 | <addressBlock> |
||
| 11521 | <offset>0x0</offset> |
||
| 11522 | <size>0x400</size> |
||
| 11523 | <usage>registers</usage> |
||
| 11524 | </addressBlock> |
||
| 11525 | <interrupt> |
||
| 11526 | <name>RCC_CRS</name> |
||
| 11527 | <description>RCC and CRS global interrupts</description> |
||
| 11528 | <value>4</value> |
||
| 11529 | </interrupt> |
||
| 11530 | <registers> |
||
| 11531 | <register> |
||
| 11532 | <name>CR1</name> |
||
| 11533 | <displayName>CR1</displayName> |
||
| 11534 | <description>Control register 1</description> |
||
| 11535 | <addressOffset>0x0</addressOffset> |
||
| 11536 | <size>0x20</size> |
||
| 11537 | <access>read-write</access> |
||
| 11538 | <resetValue>0x0000</resetValue> |
||
| 11539 | <fields> |
||
| 11540 | <field> |
||
| 11541 | <name>UE</name> |
||
| 11542 | <description>USART enable</description> |
||
| 11543 | <bitOffset>0</bitOffset> |
||
| 11544 | <bitWidth>1</bitWidth> |
||
| 11545 | </field> |
||
| 11546 | <field> |
||
| 11547 | <name>UESM</name> |
||
| 11548 | <description>USART enable in Stop mode</description> |
||
| 11549 | <bitOffset>1</bitOffset> |
||
| 11550 | <bitWidth>1</bitWidth> |
||
| 11551 | </field> |
||
| 11552 | <field> |
||
| 11553 | <name>RE</name> |
||
| 11554 | <description>Receiver enable</description> |
||
| 11555 | <bitOffset>2</bitOffset> |
||
| 11556 | <bitWidth>1</bitWidth> |
||
| 11557 | </field> |
||
| 11558 | <field> |
||
| 11559 | <name>TE</name> |
||
| 11560 | <description>Transmitter enable</description> |
||
| 11561 | <bitOffset>3</bitOffset> |
||
| 11562 | <bitWidth>1</bitWidth> |
||
| 11563 | </field> |
||
| 11564 | <field> |
||
| 11565 | <name>IDLEIE</name> |
||
| 11566 | <description>IDLE interrupt enable</description> |
||
| 11567 | <bitOffset>4</bitOffset> |
||
| 11568 | <bitWidth>1</bitWidth> |
||
| 11569 | </field> |
||
| 11570 | <field> |
||
| 11571 | <name>RXNEIE</name> |
||
| 11572 | <description>RXNE interrupt enable</description> |
||
| 11573 | <bitOffset>5</bitOffset> |
||
| 11574 | <bitWidth>1</bitWidth> |
||
| 11575 | </field> |
||
| 11576 | <field> |
||
| 11577 | <name>TCIE</name> |
||
| 11578 | <description>Transmission complete interrupt |
||
| 11579 | enable</description> |
||
| 11580 | <bitOffset>6</bitOffset> |
||
| 11581 | <bitWidth>1</bitWidth> |
||
| 11582 | </field> |
||
| 11583 | <field> |
||
| 11584 | <name>TXEIE</name> |
||
| 11585 | <description>interrupt enable</description> |
||
| 11586 | <bitOffset>7</bitOffset> |
||
| 11587 | <bitWidth>1</bitWidth> |
||
| 11588 | </field> |
||
| 11589 | <field> |
||
| 11590 | <name>PEIE</name> |
||
| 11591 | <description>PE interrupt enable</description> |
||
| 11592 | <bitOffset>8</bitOffset> |
||
| 11593 | <bitWidth>1</bitWidth> |
||
| 11594 | </field> |
||
| 11595 | <field> |
||
| 11596 | <name>PS</name> |
||
| 11597 | <description>Parity selection</description> |
||
| 11598 | <bitOffset>9</bitOffset> |
||
| 11599 | <bitWidth>1</bitWidth> |
||
| 11600 | </field> |
||
| 11601 | <field> |
||
| 11602 | <name>PCE</name> |
||
| 11603 | <description>Parity control enable</description> |
||
| 11604 | <bitOffset>10</bitOffset> |
||
| 11605 | <bitWidth>1</bitWidth> |
||
| 11606 | </field> |
||
| 11607 | <field> |
||
| 11608 | <name>WAKE</name> |
||
| 11609 | <description>Receiver wakeup method</description> |
||
| 11610 | <bitOffset>11</bitOffset> |
||
| 11611 | <bitWidth>1</bitWidth> |
||
| 11612 | </field> |
||
| 11613 | <field> |
||
| 11614 | <name>M</name> |
||
| 11615 | <description>Word length</description> |
||
| 11616 | <bitOffset>12</bitOffset> |
||
| 11617 | <bitWidth>1</bitWidth> |
||
| 11618 | </field> |
||
| 11619 | <field> |
||
| 11620 | <name>MME</name> |
||
| 11621 | <description>Mute mode enable</description> |
||
| 11622 | <bitOffset>13</bitOffset> |
||
| 11623 | <bitWidth>1</bitWidth> |
||
| 11624 | </field> |
||
| 11625 | <field> |
||
| 11626 | <name>CMIE</name> |
||
| 11627 | <description>Character match interrupt |
||
| 11628 | enable</description> |
||
| 11629 | <bitOffset>14</bitOffset> |
||
| 11630 | <bitWidth>1</bitWidth> |
||
| 11631 | </field> |
||
| 11632 | <field> |
||
| 11633 | <name>OVER8</name> |
||
| 11634 | <description>Oversampling mode</description> |
||
| 11635 | <bitOffset>15</bitOffset> |
||
| 11636 | <bitWidth>1</bitWidth> |
||
| 11637 | </field> |
||
| 11638 | <field> |
||
| 11639 | <name>DEDT</name> |
||
| 11640 | <description>Driver Enable deassertion |
||
| 11641 | time</description> |
||
| 11642 | <bitOffset>16</bitOffset> |
||
| 11643 | <bitWidth>5</bitWidth> |
||
| 11644 | </field> |
||
| 11645 | <field> |
||
| 11646 | <name>DEAT</name> |
||
| 11647 | <description>Driver Enable assertion |
||
| 11648 | time</description> |
||
| 11649 | <bitOffset>21</bitOffset> |
||
| 11650 | <bitWidth>5</bitWidth> |
||
| 11651 | </field> |
||
| 11652 | <field> |
||
| 11653 | <name>RTOIE</name> |
||
| 11654 | <description>Receiver timeout interrupt |
||
| 11655 | enable</description> |
||
| 11656 | <bitOffset>26</bitOffset> |
||
| 11657 | <bitWidth>1</bitWidth> |
||
| 11658 | </field> |
||
| 11659 | <field> |
||
| 11660 | <name>EOBIE</name> |
||
| 11661 | <description>End of Block interrupt |
||
| 11662 | enable</description> |
||
| 11663 | <bitOffset>27</bitOffset> |
||
| 11664 | <bitWidth>1</bitWidth> |
||
| 11665 | </field> |
||
| 11666 | <field> |
||
| 11667 | <name>M1</name> |
||
| 11668 | <description>Word length</description> |
||
| 11669 | <bitOffset>28</bitOffset> |
||
| 11670 | <bitWidth>1</bitWidth> |
||
| 11671 | </field> |
||
| 11672 | </fields> |
||
| 11673 | </register> |
||
| 11674 | <register> |
||
| 11675 | <name>CR2</name> |
||
| 11676 | <displayName>CR2</displayName> |
||
| 11677 | <description>Control register 2</description> |
||
| 11678 | <addressOffset>0x4</addressOffset> |
||
| 11679 | <size>0x20</size> |
||
| 11680 | <access>read-write</access> |
||
| 11681 | <resetValue>0x0000</resetValue> |
||
| 11682 | <fields> |
||
| 11683 | <field> |
||
| 11684 | <name>ADD4</name> |
||
| 11685 | <description>Address of the USART node</description> |
||
| 11686 | <bitOffset>28</bitOffset> |
||
| 11687 | <bitWidth>4</bitWidth> |
||
| 11688 | </field> |
||
| 11689 | <field> |
||
| 11690 | <name>ADD0</name> |
||
| 11691 | <description>Address of the USART node</description> |
||
| 11692 | <bitOffset>24</bitOffset> |
||
| 11693 | <bitWidth>4</bitWidth> |
||
| 11694 | </field> |
||
| 11695 | <field> |
||
| 11696 | <name>RTOEN</name> |
||
| 11697 | <description>Receiver timeout enable</description> |
||
| 11698 | <bitOffset>23</bitOffset> |
||
| 11699 | <bitWidth>1</bitWidth> |
||
| 11700 | </field> |
||
| 11701 | <field> |
||
| 11702 | <name>ABRMOD</name> |
||
| 11703 | <description>Auto baud rate mode</description> |
||
| 11704 | <bitOffset>21</bitOffset> |
||
| 11705 | <bitWidth>2</bitWidth> |
||
| 11706 | </field> |
||
| 11707 | <field> |
||
| 11708 | <name>ABREN</name> |
||
| 11709 | <description>Auto baud rate enable</description> |
||
| 11710 | <bitOffset>20</bitOffset> |
||
| 11711 | <bitWidth>1</bitWidth> |
||
| 11712 | </field> |
||
| 11713 | <field> |
||
| 11714 | <name>MSBFIRST</name> |
||
| 11715 | <description>Most significant bit first</description> |
||
| 11716 | <bitOffset>19</bitOffset> |
||
| 11717 | <bitWidth>1</bitWidth> |
||
| 11718 | </field> |
||
| 11719 | <field> |
||
| 11720 | <name>DATAINV</name> |
||
| 11721 | <description>Binary data inversion</description> |
||
| 11722 | <bitOffset>18</bitOffset> |
||
| 11723 | <bitWidth>1</bitWidth> |
||
| 11724 | </field> |
||
| 11725 | <field> |
||
| 11726 | <name>TXINV</name> |
||
| 11727 | <description>TX pin active level |
||
| 11728 | inversion</description> |
||
| 11729 | <bitOffset>17</bitOffset> |
||
| 11730 | <bitWidth>1</bitWidth> |
||
| 11731 | </field> |
||
| 11732 | <field> |
||
| 11733 | <name>RXINV</name> |
||
| 11734 | <description>RX pin active level |
||
| 11735 | inversion</description> |
||
| 11736 | <bitOffset>16</bitOffset> |
||
| 11737 | <bitWidth>1</bitWidth> |
||
| 11738 | </field> |
||
| 11739 | <field> |
||
| 11740 | <name>SWAP</name> |
||
| 11741 | <description>Swap TX/RX pins</description> |
||
| 11742 | <bitOffset>15</bitOffset> |
||
| 11743 | <bitWidth>1</bitWidth> |
||
| 11744 | </field> |
||
| 11745 | <field> |
||
| 11746 | <name>LINEN</name> |
||
| 11747 | <description>LIN mode enable</description> |
||
| 11748 | <bitOffset>14</bitOffset> |
||
| 11749 | <bitWidth>1</bitWidth> |
||
| 11750 | </field> |
||
| 11751 | <field> |
||
| 11752 | <name>STOP</name> |
||
| 11753 | <description>STOP bits</description> |
||
| 11754 | <bitOffset>12</bitOffset> |
||
| 11755 | <bitWidth>2</bitWidth> |
||
| 11756 | </field> |
||
| 11757 | <field> |
||
| 11758 | <name>CLKEN</name> |
||
| 11759 | <description>Clock enable</description> |
||
| 11760 | <bitOffset>11</bitOffset> |
||
| 11761 | <bitWidth>1</bitWidth> |
||
| 11762 | </field> |
||
| 11763 | <field> |
||
| 11764 | <name>CPOL</name> |
||
| 11765 | <description>Clock polarity</description> |
||
| 11766 | <bitOffset>10</bitOffset> |
||
| 11767 | <bitWidth>1</bitWidth> |
||
| 11768 | </field> |
||
| 11769 | <field> |
||
| 11770 | <name>CPHA</name> |
||
| 11771 | <description>Clock phase</description> |
||
| 11772 | <bitOffset>9</bitOffset> |
||
| 11773 | <bitWidth>1</bitWidth> |
||
| 11774 | </field> |
||
| 11775 | <field> |
||
| 11776 | <name>LBCL</name> |
||
| 11777 | <description>Last bit clock pulse</description> |
||
| 11778 | <bitOffset>8</bitOffset> |
||
| 11779 | <bitWidth>1</bitWidth> |
||
| 11780 | </field> |
||
| 11781 | <field> |
||
| 11782 | <name>LBDIE</name> |
||
| 11783 | <description>LIN break detection interrupt |
||
| 11784 | enable</description> |
||
| 11785 | <bitOffset>6</bitOffset> |
||
| 11786 | <bitWidth>1</bitWidth> |
||
| 11787 | </field> |
||
| 11788 | <field> |
||
| 11789 | <name>LBDL</name> |
||
| 11790 | <description>LIN break detection length</description> |
||
| 11791 | <bitOffset>5</bitOffset> |
||
| 11792 | <bitWidth>1</bitWidth> |
||
| 11793 | </field> |
||
| 11794 | <field> |
||
| 11795 | <name>ADDM7</name> |
||
| 11796 | <description>7-bit Address Detection/4-bit Address |
||
| 11797 | Detection</description> |
||
| 11798 | <bitOffset>4</bitOffset> |
||
| 11799 | <bitWidth>1</bitWidth> |
||
| 11800 | </field> |
||
| 11801 | </fields> |
||
| 11802 | </register> |
||
| 11803 | <register> |
||
| 11804 | <name>CR3</name> |
||
| 11805 | <displayName>CR3</displayName> |
||
| 11806 | <description>Control register 3</description> |
||
| 11807 | <addressOffset>0x8</addressOffset> |
||
| 11808 | <size>0x20</size> |
||
| 11809 | <access>read-write</access> |
||
| 11810 | <resetValue>0x0000</resetValue> |
||
| 11811 | <fields> |
||
| 11812 | <field> |
||
| 11813 | <name>WUFIE</name> |
||
| 11814 | <description>Wakeup from Stop mode interrupt |
||
| 11815 | enable</description> |
||
| 11816 | <bitOffset>22</bitOffset> |
||
| 11817 | <bitWidth>1</bitWidth> |
||
| 11818 | </field> |
||
| 11819 | <field> |
||
| 11820 | <name>WUS</name> |
||
| 11821 | <description>Wakeup from Stop mode interrupt flag |
||
| 11822 | selection</description> |
||
| 11823 | <bitOffset>20</bitOffset> |
||
| 11824 | <bitWidth>2</bitWidth> |
||
| 11825 | </field> |
||
| 11826 | <field> |
||
| 11827 | <name>SCARCNT</name> |
||
| 11828 | <description>Smartcard auto-retry count</description> |
||
| 11829 | <bitOffset>17</bitOffset> |
||
| 11830 | <bitWidth>3</bitWidth> |
||
| 11831 | </field> |
||
| 11832 | <field> |
||
| 11833 | <name>DEP</name> |
||
| 11834 | <description>Driver enable polarity |
||
| 11835 | selection</description> |
||
| 11836 | <bitOffset>15</bitOffset> |
||
| 11837 | <bitWidth>1</bitWidth> |
||
| 11838 | </field> |
||
| 11839 | <field> |
||
| 11840 | <name>DEM</name> |
||
| 11841 | <description>Driver enable mode</description> |
||
| 11842 | <bitOffset>14</bitOffset> |
||
| 11843 | <bitWidth>1</bitWidth> |
||
| 11844 | </field> |
||
| 11845 | <field> |
||
| 11846 | <name>DDRE</name> |
||
| 11847 | <description>DMA Disable on Reception |
||
| 11848 | Error</description> |
||
| 11849 | <bitOffset>13</bitOffset> |
||
| 11850 | <bitWidth>1</bitWidth> |
||
| 11851 | </field> |
||
| 11852 | <field> |
||
| 11853 | <name>OVRDIS</name> |
||
| 11854 | <description>Overrun Disable</description> |
||
| 11855 | <bitOffset>12</bitOffset> |
||
| 11856 | <bitWidth>1</bitWidth> |
||
| 11857 | </field> |
||
| 11858 | <field> |
||
| 11859 | <name>ONEBIT</name> |
||
| 11860 | <description>One sample bit method |
||
| 11861 | enable</description> |
||
| 11862 | <bitOffset>11</bitOffset> |
||
| 11863 | <bitWidth>1</bitWidth> |
||
| 11864 | </field> |
||
| 11865 | <field> |
||
| 11866 | <name>CTSIE</name> |
||
| 11867 | <description>CTS interrupt enable</description> |
||
| 11868 | <bitOffset>10</bitOffset> |
||
| 11869 | <bitWidth>1</bitWidth> |
||
| 11870 | </field> |
||
| 11871 | <field> |
||
| 11872 | <name>CTSE</name> |
||
| 11873 | <description>CTS enable</description> |
||
| 11874 | <bitOffset>9</bitOffset> |
||
| 11875 | <bitWidth>1</bitWidth> |
||
| 11876 | </field> |
||
| 11877 | <field> |
||
| 11878 | <name>RTSE</name> |
||
| 11879 | <description>RTS enable</description> |
||
| 11880 | <bitOffset>8</bitOffset> |
||
| 11881 | <bitWidth>1</bitWidth> |
||
| 11882 | </field> |
||
| 11883 | <field> |
||
| 11884 | <name>DMAT</name> |
||
| 11885 | <description>DMA enable transmitter</description> |
||
| 11886 | <bitOffset>7</bitOffset> |
||
| 11887 | <bitWidth>1</bitWidth> |
||
| 11888 | </field> |
||
| 11889 | <field> |
||
| 11890 | <name>DMAR</name> |
||
| 11891 | <description>DMA enable receiver</description> |
||
| 11892 | <bitOffset>6</bitOffset> |
||
| 11893 | <bitWidth>1</bitWidth> |
||
| 11894 | </field> |
||
| 11895 | <field> |
||
| 11896 | <name>SCEN</name> |
||
| 11897 | <description>Smartcard mode enable</description> |
||
| 11898 | <bitOffset>5</bitOffset> |
||
| 11899 | <bitWidth>1</bitWidth> |
||
| 11900 | </field> |
||
| 11901 | <field> |
||
| 11902 | <name>NACK</name> |
||
| 11903 | <description>Smartcard NACK enable</description> |
||
| 11904 | <bitOffset>4</bitOffset> |
||
| 11905 | <bitWidth>1</bitWidth> |
||
| 11906 | </field> |
||
| 11907 | <field> |
||
| 11908 | <name>HDSEL</name> |
||
| 11909 | <description>Half-duplex selection</description> |
||
| 11910 | <bitOffset>3</bitOffset> |
||
| 11911 | <bitWidth>1</bitWidth> |
||
| 11912 | </field> |
||
| 11913 | <field> |
||
| 11914 | <name>IRLP</name> |
||
| 11915 | <description>IrDA low-power</description> |
||
| 11916 | <bitOffset>2</bitOffset> |
||
| 11917 | <bitWidth>1</bitWidth> |
||
| 11918 | </field> |
||
| 11919 | <field> |
||
| 11920 | <name>IREN</name> |
||
| 11921 | <description>IrDA mode enable</description> |
||
| 11922 | <bitOffset>1</bitOffset> |
||
| 11923 | <bitWidth>1</bitWidth> |
||
| 11924 | </field> |
||
| 11925 | <field> |
||
| 11926 | <name>EIE</name> |
||
| 11927 | <description>Error interrupt enable</description> |
||
| 11928 | <bitOffset>0</bitOffset> |
||
| 11929 | <bitWidth>1</bitWidth> |
||
| 11930 | </field> |
||
| 11931 | </fields> |
||
| 11932 | </register> |
||
| 11933 | <register> |
||
| 11934 | <name>BRR</name> |
||
| 11935 | <displayName>BRR</displayName> |
||
| 11936 | <description>Baud rate register</description> |
||
| 11937 | <addressOffset>0xC</addressOffset> |
||
| 11938 | <size>0x20</size> |
||
| 11939 | <access>read-write</access> |
||
| 11940 | <resetValue>0x0000</resetValue> |
||
| 11941 | <fields> |
||
| 11942 | <field> |
||
| 11943 | <name>DIV_Mantissa</name> |
||
| 11944 | <description>mantissa of USARTDIV</description> |
||
| 11945 | <bitOffset>4</bitOffset> |
||
| 11946 | <bitWidth>12</bitWidth> |
||
| 11947 | </field> |
||
| 11948 | <field> |
||
| 11949 | <name>DIV_Fraction</name> |
||
| 11950 | <description>fraction of USARTDIV</description> |
||
| 11951 | <bitOffset>0</bitOffset> |
||
| 11952 | <bitWidth>4</bitWidth> |
||
| 11953 | </field> |
||
| 11954 | </fields> |
||
| 11955 | </register> |
||
| 11956 | <register> |
||
| 11957 | <name>GTPR</name> |
||
| 11958 | <displayName>GTPR</displayName> |
||
| 11959 | <description>Guard time and prescaler |
||
| 11960 | register</description> |
||
| 11961 | <addressOffset>0x10</addressOffset> |
||
| 11962 | <size>0x20</size> |
||
| 11963 | <access>read-write</access> |
||
| 11964 | <resetValue>0x0000</resetValue> |
||
| 11965 | <fields> |
||
| 11966 | <field> |
||
| 11967 | <name>GT</name> |
||
| 11968 | <description>Guard time value</description> |
||
| 11969 | <bitOffset>8</bitOffset> |
||
| 11970 | <bitWidth>8</bitWidth> |
||
| 11971 | </field> |
||
| 11972 | <field> |
||
| 11973 | <name>PSC</name> |
||
| 11974 | <description>Prescaler value</description> |
||
| 11975 | <bitOffset>0</bitOffset> |
||
| 11976 | <bitWidth>8</bitWidth> |
||
| 11977 | </field> |
||
| 11978 | </fields> |
||
| 11979 | </register> |
||
| 11980 | <register> |
||
| 11981 | <name>RTOR</name> |
||
| 11982 | <displayName>RTOR</displayName> |
||
| 11983 | <description>Receiver timeout register</description> |
||
| 11984 | <addressOffset>0x14</addressOffset> |
||
| 11985 | <size>0x20</size> |
||
| 11986 | <access>read-write</access> |
||
| 11987 | <resetValue>0x0000</resetValue> |
||
| 11988 | <fields> |
||
| 11989 | <field> |
||
| 11990 | <name>BLEN</name> |
||
| 11991 | <description>Block Length</description> |
||
| 11992 | <bitOffset>24</bitOffset> |
||
| 11993 | <bitWidth>8</bitWidth> |
||
| 11994 | </field> |
||
| 11995 | <field> |
||
| 11996 | <name>RTO</name> |
||
| 11997 | <description>Receiver timeout value</description> |
||
| 11998 | <bitOffset>0</bitOffset> |
||
| 11999 | <bitWidth>24</bitWidth> |
||
| 12000 | </field> |
||
| 12001 | </fields> |
||
| 12002 | </register> |
||
| 12003 | <register> |
||
| 12004 | <name>RQR</name> |
||
| 12005 | <displayName>RQR</displayName> |
||
| 12006 | <description>Request register</description> |
||
| 12007 | <addressOffset>0x18</addressOffset> |
||
| 12008 | <size>0x20</size> |
||
| 12009 | <access>read-write</access> |
||
| 12010 | <resetValue>0x0000</resetValue> |
||
| 12011 | <fields> |
||
| 12012 | <field> |
||
| 12013 | <name>TXFRQ</name> |
||
| 12014 | <description>Transmit data flush |
||
| 12015 | request</description> |
||
| 12016 | <bitOffset>4</bitOffset> |
||
| 12017 | <bitWidth>1</bitWidth> |
||
| 12018 | </field> |
||
| 12019 | <field> |
||
| 12020 | <name>RXFRQ</name> |
||
| 12021 | <description>Receive data flush request</description> |
||
| 12022 | <bitOffset>3</bitOffset> |
||
| 12023 | <bitWidth>1</bitWidth> |
||
| 12024 | </field> |
||
| 12025 | <field> |
||
| 12026 | <name>MMRQ</name> |
||
| 12027 | <description>Mute mode request</description> |
||
| 12028 | <bitOffset>2</bitOffset> |
||
| 12029 | <bitWidth>1</bitWidth> |
||
| 12030 | </field> |
||
| 12031 | <field> |
||
| 12032 | <name>SBKRQ</name> |
||
| 12033 | <description>Send break request</description> |
||
| 12034 | <bitOffset>1</bitOffset> |
||
| 12035 | <bitWidth>1</bitWidth> |
||
| 12036 | </field> |
||
| 12037 | <field> |
||
| 12038 | <name>ABRRQ</name> |
||
| 12039 | <description>Auto baud rate request</description> |
||
| 12040 | <bitOffset>0</bitOffset> |
||
| 12041 | <bitWidth>1</bitWidth> |
||
| 12042 | </field> |
||
| 12043 | </fields> |
||
| 12044 | </register> |
||
| 12045 | <register> |
||
| 12046 | <name>ISR</name> |
||
| 12047 | <displayName>ISR</displayName> |
||
| 12048 | <description>Interrupt & status |
||
| 12049 | register</description> |
||
| 12050 | <addressOffset>0x1C</addressOffset> |
||
| 12051 | <size>0x20</size> |
||
| 12052 | <access>read-only</access> |
||
| 12053 | <resetValue>0x00C0</resetValue> |
||
| 12054 | <fields> |
||
| 12055 | <field> |
||
| 12056 | <name>REACK</name> |
||
| 12057 | <description>Receive enable acknowledge |
||
| 12058 | flag</description> |
||
| 12059 | <bitOffset>22</bitOffset> |
||
| 12060 | <bitWidth>1</bitWidth> |
||
| 12061 | </field> |
||
| 12062 | <field> |
||
| 12063 | <name>TEACK</name> |
||
| 12064 | <description>Transmit enable acknowledge |
||
| 12065 | flag</description> |
||
| 12066 | <bitOffset>21</bitOffset> |
||
| 12067 | <bitWidth>1</bitWidth> |
||
| 12068 | </field> |
||
| 12069 | <field> |
||
| 12070 | <name>WUF</name> |
||
| 12071 | <description>Wakeup from Stop mode flag</description> |
||
| 12072 | <bitOffset>20</bitOffset> |
||
| 12073 | <bitWidth>1</bitWidth> |
||
| 12074 | </field> |
||
| 12075 | <field> |
||
| 12076 | <name>RWU</name> |
||
| 12077 | <description>Receiver wakeup from Mute |
||
| 12078 | mode</description> |
||
| 12079 | <bitOffset>19</bitOffset> |
||
| 12080 | <bitWidth>1</bitWidth> |
||
| 12081 | </field> |
||
| 12082 | <field> |
||
| 12083 | <name>SBKF</name> |
||
| 12084 | <description>Send break flag</description> |
||
| 12085 | <bitOffset>18</bitOffset> |
||
| 12086 | <bitWidth>1</bitWidth> |
||
| 12087 | </field> |
||
| 12088 | <field> |
||
| 12089 | <name>CMF</name> |
||
| 12090 | <description>character match flag</description> |
||
| 12091 | <bitOffset>17</bitOffset> |
||
| 12092 | <bitWidth>1</bitWidth> |
||
| 12093 | </field> |
||
| 12094 | <field> |
||
| 12095 | <name>BUSY</name> |
||
| 12096 | <description>Busy flag</description> |
||
| 12097 | <bitOffset>16</bitOffset> |
||
| 12098 | <bitWidth>1</bitWidth> |
||
| 12099 | </field> |
||
| 12100 | <field> |
||
| 12101 | <name>ABRF</name> |
||
| 12102 | <description>Auto baud rate flag</description> |
||
| 12103 | <bitOffset>15</bitOffset> |
||
| 12104 | <bitWidth>1</bitWidth> |
||
| 12105 | </field> |
||
| 12106 | <field> |
||
| 12107 | <name>ABRE</name> |
||
| 12108 | <description>Auto baud rate error</description> |
||
| 12109 | <bitOffset>14</bitOffset> |
||
| 12110 | <bitWidth>1</bitWidth> |
||
| 12111 | </field> |
||
| 12112 | <field> |
||
| 12113 | <name>EOBF</name> |
||
| 12114 | <description>End of block flag</description> |
||
| 12115 | <bitOffset>12</bitOffset> |
||
| 12116 | <bitWidth>1</bitWidth> |
||
| 12117 | </field> |
||
| 12118 | <field> |
||
| 12119 | <name>RTOF</name> |
||
| 12120 | <description>Receiver timeout</description> |
||
| 12121 | <bitOffset>11</bitOffset> |
||
| 12122 | <bitWidth>1</bitWidth> |
||
| 12123 | </field> |
||
| 12124 | <field> |
||
| 12125 | <name>CTS</name> |
||
| 12126 | <description>CTS flag</description> |
||
| 12127 | <bitOffset>10</bitOffset> |
||
| 12128 | <bitWidth>1</bitWidth> |
||
| 12129 | </field> |
||
| 12130 | <field> |
||
| 12131 | <name>CTSIF</name> |
||
| 12132 | <description>CTS interrupt flag</description> |
||
| 12133 | <bitOffset>9</bitOffset> |
||
| 12134 | <bitWidth>1</bitWidth> |
||
| 12135 | </field> |
||
| 12136 | <field> |
||
| 12137 | <name>LBDF</name> |
||
| 12138 | <description>LIN break detection flag</description> |
||
| 12139 | <bitOffset>8</bitOffset> |
||
| 12140 | <bitWidth>1</bitWidth> |
||
| 12141 | </field> |
||
| 12142 | <field> |
||
| 12143 | <name>TXE</name> |
||
| 12144 | <description>Transmit data register |
||
| 12145 | empty</description> |
||
| 12146 | <bitOffset>7</bitOffset> |
||
| 12147 | <bitWidth>1</bitWidth> |
||
| 12148 | </field> |
||
| 12149 | <field> |
||
| 12150 | <name>TC</name> |
||
| 12151 | <description>Transmission complete</description> |
||
| 12152 | <bitOffset>6</bitOffset> |
||
| 12153 | <bitWidth>1</bitWidth> |
||
| 12154 | </field> |
||
| 12155 | <field> |
||
| 12156 | <name>RXNE</name> |
||
| 12157 | <description>Read data register not |
||
| 12158 | empty</description> |
||
| 12159 | <bitOffset>5</bitOffset> |
||
| 12160 | <bitWidth>1</bitWidth> |
||
| 12161 | </field> |
||
| 12162 | <field> |
||
| 12163 | <name>IDLE</name> |
||
| 12164 | <description>Idle line detected</description> |
||
| 12165 | <bitOffset>4</bitOffset> |
||
| 12166 | <bitWidth>1</bitWidth> |
||
| 12167 | </field> |
||
| 12168 | <field> |
||
| 12169 | <name>ORE</name> |
||
| 12170 | <description>Overrun error</description> |
||
| 12171 | <bitOffset>3</bitOffset> |
||
| 12172 | <bitWidth>1</bitWidth> |
||
| 12173 | </field> |
||
| 12174 | <field> |
||
| 12175 | <name>NF</name> |
||
| 12176 | <description>Noise detected flag</description> |
||
| 12177 | <bitOffset>2</bitOffset> |
||
| 12178 | <bitWidth>1</bitWidth> |
||
| 12179 | </field> |
||
| 12180 | <field> |
||
| 12181 | <name>FE</name> |
||
| 12182 | <description>Framing error</description> |
||
| 12183 | <bitOffset>1</bitOffset> |
||
| 12184 | <bitWidth>1</bitWidth> |
||
| 12185 | </field> |
||
| 12186 | <field> |
||
| 12187 | <name>PE</name> |
||
| 12188 | <description>Parity error</description> |
||
| 12189 | <bitOffset>0</bitOffset> |
||
| 12190 | <bitWidth>1</bitWidth> |
||
| 12191 | </field> |
||
| 12192 | </fields> |
||
| 12193 | </register> |
||
| 12194 | <register> |
||
| 12195 | <name>ICR</name> |
||
| 12196 | <displayName>ICR</displayName> |
||
| 12197 | <description>Interrupt flag clear register</description> |
||
| 12198 | <addressOffset>0x20</addressOffset> |
||
| 12199 | <size>0x20</size> |
||
| 12200 | <access>read-write</access> |
||
| 12201 | <resetValue>0x0000</resetValue> |
||
| 12202 | <fields> |
||
| 12203 | <field> |
||
| 12204 | <name>WUCF</name> |
||
| 12205 | <description>Wakeup from Stop mode clear |
||
| 12206 | flag</description> |
||
| 12207 | <bitOffset>20</bitOffset> |
||
| 12208 | <bitWidth>1</bitWidth> |
||
| 12209 | </field> |
||
| 12210 | <field> |
||
| 12211 | <name>CMCF</name> |
||
| 12212 | <description>Character match clear flag</description> |
||
| 12213 | <bitOffset>17</bitOffset> |
||
| 12214 | <bitWidth>1</bitWidth> |
||
| 12215 | </field> |
||
| 12216 | <field> |
||
| 12217 | <name>EOBCF</name> |
||
| 12218 | <description>End of timeout clear flag</description> |
||
| 12219 | <bitOffset>12</bitOffset> |
||
| 12220 | <bitWidth>1</bitWidth> |
||
| 12221 | </field> |
||
| 12222 | <field> |
||
| 12223 | <name>RTOCF</name> |
||
| 12224 | <description>Receiver timeout clear |
||
| 12225 | flag</description> |
||
| 12226 | <bitOffset>11</bitOffset> |
||
| 12227 | <bitWidth>1</bitWidth> |
||
| 12228 | </field> |
||
| 12229 | <field> |
||
| 12230 | <name>CTSCF</name> |
||
| 12231 | <description>CTS clear flag</description> |
||
| 12232 | <bitOffset>9</bitOffset> |
||
| 12233 | <bitWidth>1</bitWidth> |
||
| 12234 | </field> |
||
| 12235 | <field> |
||
| 12236 | <name>LBDCF</name> |
||
| 12237 | <description>LIN break detection clear |
||
| 12238 | flag</description> |
||
| 12239 | <bitOffset>8</bitOffset> |
||
| 12240 | <bitWidth>1</bitWidth> |
||
| 12241 | </field> |
||
| 12242 | <field> |
||
| 12243 | <name>TCCF</name> |
||
| 12244 | <description>Transmission complete clear |
||
| 12245 | flag</description> |
||
| 12246 | <bitOffset>6</bitOffset> |
||
| 12247 | <bitWidth>1</bitWidth> |
||
| 12248 | </field> |
||
| 12249 | <field> |
||
| 12250 | <name>IDLECF</name> |
||
| 12251 | <description>Idle line detected clear |
||
| 12252 | flag</description> |
||
| 12253 | <bitOffset>4</bitOffset> |
||
| 12254 | <bitWidth>1</bitWidth> |
||
| 12255 | </field> |
||
| 12256 | <field> |
||
| 12257 | <name>ORECF</name> |
||
| 12258 | <description>Overrun error clear flag</description> |
||
| 12259 | <bitOffset>3</bitOffset> |
||
| 12260 | <bitWidth>1</bitWidth> |
||
| 12261 | </field> |
||
| 12262 | <field> |
||
| 12263 | <name>NCF</name> |
||
| 12264 | <description>Noise detected clear flag</description> |
||
| 12265 | <bitOffset>2</bitOffset> |
||
| 12266 | <bitWidth>1</bitWidth> |
||
| 12267 | </field> |
||
| 12268 | <field> |
||
| 12269 | <name>FECF</name> |
||
| 12270 | <description>Framing error clear flag</description> |
||
| 12271 | <bitOffset>1</bitOffset> |
||
| 12272 | <bitWidth>1</bitWidth> |
||
| 12273 | </field> |
||
| 12274 | <field> |
||
| 12275 | <name>PECF</name> |
||
| 12276 | <description>Parity error clear flag</description> |
||
| 12277 | <bitOffset>0</bitOffset> |
||
| 12278 | <bitWidth>1</bitWidth> |
||
| 12279 | </field> |
||
| 12280 | </fields> |
||
| 12281 | </register> |
||
| 12282 | <register> |
||
| 12283 | <name>RDR</name> |
||
| 12284 | <displayName>RDR</displayName> |
||
| 12285 | <description>Receive data register</description> |
||
| 12286 | <addressOffset>0x24</addressOffset> |
||
| 12287 | <size>0x20</size> |
||
| 12288 | <access>read-only</access> |
||
| 12289 | <resetValue>0x0000</resetValue> |
||
| 12290 | <fields> |
||
| 12291 | <field> |
||
| 12292 | <name>RDR</name> |
||
| 12293 | <description>Receive data value</description> |
||
| 12294 | <bitOffset>0</bitOffset> |
||
| 12295 | <bitWidth>9</bitWidth> |
||
| 12296 | </field> |
||
| 12297 | </fields> |
||
| 12298 | </register> |
||
| 12299 | <register> |
||
| 12300 | <name>TDR</name> |
||
| 12301 | <displayName>TDR</displayName> |
||
| 12302 | <description>Transmit data register</description> |
||
| 12303 | <addressOffset>0x28</addressOffset> |
||
| 12304 | <size>0x20</size> |
||
| 12305 | <access>read-write</access> |
||
| 12306 | <resetValue>0x0000</resetValue> |
||
| 12307 | <fields> |
||
| 12308 | <field> |
||
| 12309 | <name>TDR</name> |
||
| 12310 | <description>Transmit data value</description> |
||
| 12311 | <bitOffset>0</bitOffset> |
||
| 12312 | <bitWidth>9</bitWidth> |
||
| 12313 | </field> |
||
| 12314 | </fields> |
||
| 12315 | </register> |
||
| 12316 | </registers> |
||
| 12317 | </peripheral> |
||
| 12318 | <peripheral derivedFrom="USART1"> |
||
| 12319 | <name>USART2</name> |
||
| 12320 | <baseAddress>0x40004400</baseAddress> |
||
| 12321 | </peripheral> |
||
| 12322 | <peripheral> |
||
| 12323 | <name>RTC</name> |
||
| 12324 | <description>Real-time clock</description> |
||
| 12325 | <groupName>RTC</groupName> |
||
| 12326 | <baseAddress>0x40002800</baseAddress> |
||
| 12327 | <addressBlock> |
||
| 12328 | <offset>0x0</offset> |
||
| 12329 | <size>0x400</size> |
||
| 12330 | <usage>registers</usage> |
||
| 12331 | </addressBlock> |
||
| 12332 | <interrupt> |
||
| 12333 | <name>ADC_COMP</name> |
||
| 12334 | <description>ADC and comparator interrupts</description> |
||
| 12335 | <value>12</value> |
||
| 12336 | </interrupt> |
||
| 12337 | <registers> |
||
| 12338 | <register> |
||
| 12339 | <name>TR</name> |
||
| 12340 | <displayName>TR</displayName> |
||
| 12341 | <description>time register</description> |
||
| 12342 | <addressOffset>0x0</addressOffset> |
||
| 12343 | <size>0x20</size> |
||
| 12344 | <access>read-write</access> |
||
| 12345 | <resetValue>0x00000000</resetValue> |
||
| 12346 | <fields> |
||
| 12347 | <field> |
||
| 12348 | <name>PM</name> |
||
| 12349 | <description>AM/PM notation</description> |
||
| 12350 | <bitOffset>22</bitOffset> |
||
| 12351 | <bitWidth>1</bitWidth> |
||
| 12352 | </field> |
||
| 12353 | <field> |
||
| 12354 | <name>HT</name> |
||
| 12355 | <description>Hour tens in BCD format</description> |
||
| 12356 | <bitOffset>20</bitOffset> |
||
| 12357 | <bitWidth>2</bitWidth> |
||
| 12358 | </field> |
||
| 12359 | <field> |
||
| 12360 | <name>HU</name> |
||
| 12361 | <description>Hour units in BCD format</description> |
||
| 12362 | <bitOffset>16</bitOffset> |
||
| 12363 | <bitWidth>4</bitWidth> |
||
| 12364 | </field> |
||
| 12365 | <field> |
||
| 12366 | <name>MNT</name> |
||
| 12367 | <description>Minute tens in BCD format</description> |
||
| 12368 | <bitOffset>12</bitOffset> |
||
| 12369 | <bitWidth>3</bitWidth> |
||
| 12370 | </field> |
||
| 12371 | <field> |
||
| 12372 | <name>MNU</name> |
||
| 12373 | <description>Minute units in BCD format</description> |
||
| 12374 | <bitOffset>8</bitOffset> |
||
| 12375 | <bitWidth>4</bitWidth> |
||
| 12376 | </field> |
||
| 12377 | <field> |
||
| 12378 | <name>ST</name> |
||
| 12379 | <description>Second tens in BCD format</description> |
||
| 12380 | <bitOffset>4</bitOffset> |
||
| 12381 | <bitWidth>3</bitWidth> |
||
| 12382 | </field> |
||
| 12383 | <field> |
||
| 12384 | <name>SU</name> |
||
| 12385 | <description>Second units in BCD format</description> |
||
| 12386 | <bitOffset>0</bitOffset> |
||
| 12387 | <bitWidth>4</bitWidth> |
||
| 12388 | </field> |
||
| 12389 | </fields> |
||
| 12390 | </register> |
||
| 12391 | <register> |
||
| 12392 | <name>DR</name> |
||
| 12393 | <displayName>DR</displayName> |
||
| 12394 | <description>date register</description> |
||
| 12395 | <addressOffset>0x4</addressOffset> |
||
| 12396 | <size>0x20</size> |
||
| 12397 | <access>read-write</access> |
||
| 12398 | <resetValue>0x00002101</resetValue> |
||
| 12399 | <fields> |
||
| 12400 | <field> |
||
| 12401 | <name>YT</name> |
||
| 12402 | <description>Year tens in BCD format</description> |
||
| 12403 | <bitOffset>20</bitOffset> |
||
| 12404 | <bitWidth>4</bitWidth> |
||
| 12405 | </field> |
||
| 12406 | <field> |
||
| 12407 | <name>YU</name> |
||
| 12408 | <description>Year units in BCD format</description> |
||
| 12409 | <bitOffset>16</bitOffset> |
||
| 12410 | <bitWidth>4</bitWidth> |
||
| 12411 | </field> |
||
| 12412 | <field> |
||
| 12413 | <name>WDU</name> |
||
| 12414 | <description>Week day units</description> |
||
| 12415 | <bitOffset>13</bitOffset> |
||
| 12416 | <bitWidth>3</bitWidth> |
||
| 12417 | </field> |
||
| 12418 | <field> |
||
| 12419 | <name>MT</name> |
||
| 12420 | <description>Month tens in BCD format</description> |
||
| 12421 | <bitOffset>12</bitOffset> |
||
| 12422 | <bitWidth>1</bitWidth> |
||
| 12423 | </field> |
||
| 12424 | <field> |
||
| 12425 | <name>MU</name> |
||
| 12426 | <description>Month units in BCD format</description> |
||
| 12427 | <bitOffset>8</bitOffset> |
||
| 12428 | <bitWidth>4</bitWidth> |
||
| 12429 | </field> |
||
| 12430 | <field> |
||
| 12431 | <name>DT</name> |
||
| 12432 | <description>Date tens in BCD format</description> |
||
| 12433 | <bitOffset>4</bitOffset> |
||
| 12434 | <bitWidth>2</bitWidth> |
||
| 12435 | </field> |
||
| 12436 | <field> |
||
| 12437 | <name>DU</name> |
||
| 12438 | <description>Date units in BCD format</description> |
||
| 12439 | <bitOffset>0</bitOffset> |
||
| 12440 | <bitWidth>4</bitWidth> |
||
| 12441 | </field> |
||
| 12442 | </fields> |
||
| 12443 | </register> |
||
| 12444 | <register> |
||
| 12445 | <name>CR</name> |
||
| 12446 | <displayName>CR</displayName> |
||
| 12447 | <description>control register</description> |
||
| 12448 | <addressOffset>0x8</addressOffset> |
||
| 12449 | <size>0x20</size> |
||
| 12450 | <resetValue>0x00000000</resetValue> |
||
| 12451 | <fields> |
||
| 12452 | <field> |
||
| 12453 | <name>TSEDGE</name> |
||
| 12454 | <description>Time-stamp event active |
||
| 12455 | edge</description> |
||
| 12456 | <bitOffset>3</bitOffset> |
||
| 12457 | <bitWidth>1</bitWidth> |
||
| 12458 | <access>read-write</access> |
||
| 12459 | </field> |
||
| 12460 | <field> |
||
| 12461 | <name>REFCKON</name> |
||
| 12462 | <description>RTC_REFIN reference clock detection |
||
| 12463 | enable (50 or 60 Hz)</description> |
||
| 12464 | <bitOffset>4</bitOffset> |
||
| 12465 | <bitWidth>1</bitWidth> |
||
| 12466 | <access>read-write</access> |
||
| 12467 | </field> |
||
| 12468 | <field> |
||
| 12469 | <name>BYPSHAD</name> |
||
| 12470 | <description>Bypass the shadow |
||
| 12471 | registers</description> |
||
| 12472 | <bitOffset>5</bitOffset> |
||
| 12473 | <bitWidth>1</bitWidth> |
||
| 12474 | <access>read-write</access> |
||
| 12475 | </field> |
||
| 12476 | <field> |
||
| 12477 | <name>FMT</name> |
||
| 12478 | <description>Hour format</description> |
||
| 12479 | <bitOffset>6</bitOffset> |
||
| 12480 | <bitWidth>1</bitWidth> |
||
| 12481 | <access>read-write</access> |
||
| 12482 | </field> |
||
| 12483 | <field> |
||
| 12484 | <name>ALRAE</name> |
||
| 12485 | <description>Alarm A enable</description> |
||
| 12486 | <bitOffset>8</bitOffset> |
||
| 12487 | <bitWidth>1</bitWidth> |
||
| 12488 | <access>read-write</access> |
||
| 12489 | </field> |
||
| 12490 | <field> |
||
| 12491 | <name>TSE</name> |
||
| 12492 | <description>timestamp enable</description> |
||
| 12493 | <bitOffset>11</bitOffset> |
||
| 12494 | <bitWidth>1</bitWidth> |
||
| 12495 | <access>read-write</access> |
||
| 12496 | </field> |
||
| 12497 | <field> |
||
| 12498 | <name>ALRAIE</name> |
||
| 12499 | <description>Alarm A interrupt enable</description> |
||
| 12500 | <bitOffset>12</bitOffset> |
||
| 12501 | <bitWidth>1</bitWidth> |
||
| 12502 | <access>read-write</access> |
||
| 12503 | </field> |
||
| 12504 | <field> |
||
| 12505 | <name>TSIE</name> |
||
| 12506 | <description>Time-stamp interrupt |
||
| 12507 | enable</description> |
||
| 12508 | <bitOffset>15</bitOffset> |
||
| 12509 | <bitWidth>1</bitWidth> |
||
| 12510 | <access>read-write</access> |
||
| 12511 | </field> |
||
| 12512 | <field> |
||
| 12513 | <name>ADD1H</name> |
||
| 12514 | <description>Add 1 hour (summer time |
||
| 12515 | change)</description> |
||
| 12516 | <bitOffset>16</bitOffset> |
||
| 12517 | <bitWidth>1</bitWidth> |
||
| 12518 | <access>write-only</access> |
||
| 12519 | </field> |
||
| 12520 | <field> |
||
| 12521 | <name>SUB1H</name> |
||
| 12522 | <description>Subtract 1 hour (winter time |
||
| 12523 | change)</description> |
||
| 12524 | <bitOffset>17</bitOffset> |
||
| 12525 | <bitWidth>1</bitWidth> |
||
| 12526 | <access>write-only</access> |
||
| 12527 | </field> |
||
| 12528 | <field> |
||
| 12529 | <name>BKP</name> |
||
| 12530 | <description>Backup</description> |
||
| 12531 | <bitOffset>18</bitOffset> |
||
| 12532 | <bitWidth>1</bitWidth> |
||
| 12533 | <access>read-write</access> |
||
| 12534 | </field> |
||
| 12535 | <field> |
||
| 12536 | <name>COSEL</name> |
||
| 12537 | <description>Calibration output |
||
| 12538 | selection</description> |
||
| 12539 | <bitOffset>19</bitOffset> |
||
| 12540 | <bitWidth>1</bitWidth> |
||
| 12541 | <access>read-write</access> |
||
| 12542 | </field> |
||
| 12543 | <field> |
||
| 12544 | <name>POL</name> |
||
| 12545 | <description>Output polarity</description> |
||
| 12546 | <bitOffset>20</bitOffset> |
||
| 12547 | <bitWidth>1</bitWidth> |
||
| 12548 | <access>read-write</access> |
||
| 12549 | </field> |
||
| 12550 | <field> |
||
| 12551 | <name>OSEL</name> |
||
| 12552 | <description>Output selection</description> |
||
| 12553 | <bitOffset>21</bitOffset> |
||
| 12554 | <bitWidth>2</bitWidth> |
||
| 12555 | <access>read-write</access> |
||
| 12556 | </field> |
||
| 12557 | <field> |
||
| 12558 | <name>COE</name> |
||
| 12559 | <description>Calibration output enable</description> |
||
| 12560 | <bitOffset>23</bitOffset> |
||
| 12561 | <bitWidth>1</bitWidth> |
||
| 12562 | <access>read-write</access> |
||
| 12563 | </field> |
||
| 12564 | </fields> |
||
| 12565 | </register> |
||
| 12566 | <register> |
||
| 12567 | <name>ISR</name> |
||
| 12568 | <displayName>ISR</displayName> |
||
| 12569 | <description>initialization and status |
||
| 12570 | register</description> |
||
| 12571 | <addressOffset>0xC</addressOffset> |
||
| 12572 | <size>0x20</size> |
||
| 12573 | <resetValue>0x00000007</resetValue> |
||
| 12574 | <fields> |
||
| 12575 | <field> |
||
| 12576 | <name>ALRAWF</name> |
||
| 12577 | <description>Alarm A write flag</description> |
||
| 12578 | <bitOffset>0</bitOffset> |
||
| 12579 | <bitWidth>1</bitWidth> |
||
| 12580 | <access>read-only</access> |
||
| 12581 | </field> |
||
| 12582 | <field> |
||
| 12583 | <name>SHPF</name> |
||
| 12584 | <description>Shift operation pending</description> |
||
| 12585 | <bitOffset>3</bitOffset> |
||
| 12586 | <bitWidth>1</bitWidth> |
||
| 12587 | <access>read-write</access> |
||
| 12588 | </field> |
||
| 12589 | <field> |
||
| 12590 | <name>INITS</name> |
||
| 12591 | <description>Initialization status flag</description> |
||
| 12592 | <bitOffset>4</bitOffset> |
||
| 12593 | <bitWidth>1</bitWidth> |
||
| 12594 | <access>read-only</access> |
||
| 12595 | </field> |
||
| 12596 | <field> |
||
| 12597 | <name>RSF</name> |
||
| 12598 | <description>Registers synchronization |
||
| 12599 | flag</description> |
||
| 12600 | <bitOffset>5</bitOffset> |
||
| 12601 | <bitWidth>1</bitWidth> |
||
| 12602 | <access>read-write</access> |
||
| 12603 | </field> |
||
| 12604 | <field> |
||
| 12605 | <name>INITF</name> |
||
| 12606 | <description>Initialization flag</description> |
||
| 12607 | <bitOffset>6</bitOffset> |
||
| 12608 | <bitWidth>1</bitWidth> |
||
| 12609 | <access>read-only</access> |
||
| 12610 | </field> |
||
| 12611 | <field> |
||
| 12612 | <name>INIT</name> |
||
| 12613 | <description>Initialization mode</description> |
||
| 12614 | <bitOffset>7</bitOffset> |
||
| 12615 | <bitWidth>1</bitWidth> |
||
| 12616 | <access>read-write</access> |
||
| 12617 | </field> |
||
| 12618 | <field> |
||
| 12619 | <name>ALRAF</name> |
||
| 12620 | <description>Alarm A flag</description> |
||
| 12621 | <bitOffset>8</bitOffset> |
||
| 12622 | <bitWidth>1</bitWidth> |
||
| 12623 | <access>read-write</access> |
||
| 12624 | </field> |
||
| 12625 | <field> |
||
| 12626 | <name>TSF</name> |
||
| 12627 | <description>Time-stamp flag</description> |
||
| 12628 | <bitOffset>11</bitOffset> |
||
| 12629 | <bitWidth>1</bitWidth> |
||
| 12630 | <access>read-write</access> |
||
| 12631 | </field> |
||
| 12632 | <field> |
||
| 12633 | <name>TSOVF</name> |
||
| 12634 | <description>Time-stamp overflow flag</description> |
||
| 12635 | <bitOffset>12</bitOffset> |
||
| 12636 | <bitWidth>1</bitWidth> |
||
| 12637 | <access>read-write</access> |
||
| 12638 | </field> |
||
| 12639 | <field> |
||
| 12640 | <name>TAMP1F</name> |
||
| 12641 | <description>RTC_TAMP1 detection flag</description> |
||
| 12642 | <bitOffset>13</bitOffset> |
||
| 12643 | <bitWidth>1</bitWidth> |
||
| 12644 | <access>read-write</access> |
||
| 12645 | </field> |
||
| 12646 | <field> |
||
| 12647 | <name>TAMP2F</name> |
||
| 12648 | <description>RTC_TAMP2 detection flag</description> |
||
| 12649 | <bitOffset>14</bitOffset> |
||
| 12650 | <bitWidth>1</bitWidth> |
||
| 12651 | <access>read-write</access> |
||
| 12652 | </field> |
||
| 12653 | <field> |
||
| 12654 | <name>RECALPF</name> |
||
| 12655 | <description>Recalibration pending Flag</description> |
||
| 12656 | <bitOffset>16</bitOffset> |
||
| 12657 | <bitWidth>1</bitWidth> |
||
| 12658 | <access>read-only</access> |
||
| 12659 | </field> |
||
| 12660 | </fields> |
||
| 12661 | </register> |
||
| 12662 | <register> |
||
| 12663 | <name>PRER</name> |
||
| 12664 | <displayName>PRER</displayName> |
||
| 12665 | <description>prescaler register</description> |
||
| 12666 | <addressOffset>0x10</addressOffset> |
||
| 12667 | <size>0x20</size> |
||
| 12668 | <access>read-write</access> |
||
| 12669 | <resetValue>0x007F00FF</resetValue> |
||
| 12670 | <fields> |
||
| 12671 | <field> |
||
| 12672 | <name>PREDIV_A</name> |
||
| 12673 | <description>Asynchronous prescaler |
||
| 12674 | factor</description> |
||
| 12675 | <bitOffset>16</bitOffset> |
||
| 12676 | <bitWidth>7</bitWidth> |
||
| 12677 | </field> |
||
| 12678 | <field> |
||
| 12679 | <name>PREDIV_S</name> |
||
| 12680 | <description>Synchronous prescaler |
||
| 12681 | factor</description> |
||
| 12682 | <bitOffset>0</bitOffset> |
||
| 12683 | <bitWidth>15</bitWidth> |
||
| 12684 | </field> |
||
| 12685 | </fields> |
||
| 12686 | </register> |
||
| 12687 | <register> |
||
| 12688 | <name>ALRMAR</name> |
||
| 12689 | <displayName>ALRMAR</displayName> |
||
| 12690 | <description>alarm A register</description> |
||
| 12691 | <addressOffset>0x1C</addressOffset> |
||
| 12692 | <size>0x20</size> |
||
| 12693 | <access>read-write</access> |
||
| 12694 | <resetValue>0x00000000</resetValue> |
||
| 12695 | <fields> |
||
| 12696 | <field> |
||
| 12697 | <name>MSK4</name> |
||
| 12698 | <description>Alarm A date mask</description> |
||
| 12699 | <bitOffset>31</bitOffset> |
||
| 12700 | <bitWidth>1</bitWidth> |
||
| 12701 | </field> |
||
| 12702 | <field> |
||
| 12703 | <name>WDSEL</name> |
||
| 12704 | <description>Week day selection</description> |
||
| 12705 | <bitOffset>30</bitOffset> |
||
| 12706 | <bitWidth>1</bitWidth> |
||
| 12707 | </field> |
||
| 12708 | <field> |
||
| 12709 | <name>DT</name> |
||
| 12710 | <description>Date tens in BCD format.</description> |
||
| 12711 | <bitOffset>28</bitOffset> |
||
| 12712 | <bitWidth>2</bitWidth> |
||
| 12713 | </field> |
||
| 12714 | <field> |
||
| 12715 | <name>DU</name> |
||
| 12716 | <description>Date units or day in BCD |
||
| 12717 | format.</description> |
||
| 12718 | <bitOffset>24</bitOffset> |
||
| 12719 | <bitWidth>4</bitWidth> |
||
| 12720 | </field> |
||
| 12721 | <field> |
||
| 12722 | <name>MSK3</name> |
||
| 12723 | <description>Alarm A hours mask</description> |
||
| 12724 | <bitOffset>23</bitOffset> |
||
| 12725 | <bitWidth>1</bitWidth> |
||
| 12726 | </field> |
||
| 12727 | <field> |
||
| 12728 | <name>PM</name> |
||
| 12729 | <description>AM/PM notation</description> |
||
| 12730 | <bitOffset>22</bitOffset> |
||
| 12731 | <bitWidth>1</bitWidth> |
||
| 12732 | </field> |
||
| 12733 | <field> |
||
| 12734 | <name>HT</name> |
||
| 12735 | <description>Hour tens in BCD format.</description> |
||
| 12736 | <bitOffset>20</bitOffset> |
||
| 12737 | <bitWidth>2</bitWidth> |
||
| 12738 | </field> |
||
| 12739 | <field> |
||
| 12740 | <name>HU</name> |
||
| 12741 | <description>Hour units in BCD format.</description> |
||
| 12742 | <bitOffset>16</bitOffset> |
||
| 12743 | <bitWidth>4</bitWidth> |
||
| 12744 | </field> |
||
| 12745 | <field> |
||
| 12746 | <name>MSK2</name> |
||
| 12747 | <description>Alarm A minutes mask</description> |
||
| 12748 | <bitOffset>15</bitOffset> |
||
| 12749 | <bitWidth>1</bitWidth> |
||
| 12750 | </field> |
||
| 12751 | <field> |
||
| 12752 | <name>MNT</name> |
||
| 12753 | <description>Minute tens in BCD format.</description> |
||
| 12754 | <bitOffset>12</bitOffset> |
||
| 12755 | <bitWidth>3</bitWidth> |
||
| 12756 | </field> |
||
| 12757 | <field> |
||
| 12758 | <name>MNU</name> |
||
| 12759 | <description>Minute units in BCD |
||
| 12760 | format.</description> |
||
| 12761 | <bitOffset>8</bitOffset> |
||
| 12762 | <bitWidth>4</bitWidth> |
||
| 12763 | </field> |
||
| 12764 | <field> |
||
| 12765 | <name>MSK1</name> |
||
| 12766 | <description>Alarm A seconds mask</description> |
||
| 12767 | <bitOffset>7</bitOffset> |
||
| 12768 | <bitWidth>1</bitWidth> |
||
| 12769 | </field> |
||
| 12770 | <field> |
||
| 12771 | <name>ST</name> |
||
| 12772 | <description>Second tens in BCD format.</description> |
||
| 12773 | <bitOffset>4</bitOffset> |
||
| 12774 | <bitWidth>3</bitWidth> |
||
| 12775 | </field> |
||
| 12776 | <field> |
||
| 12777 | <name>SU</name> |
||
| 12778 | <description>Second units in BCD |
||
| 12779 | format.</description> |
||
| 12780 | <bitOffset>0</bitOffset> |
||
| 12781 | <bitWidth>4</bitWidth> |
||
| 12782 | </field> |
||
| 12783 | </fields> |
||
| 12784 | </register> |
||
| 12785 | <register> |
||
| 12786 | <name>WPR</name> |
||
| 12787 | <displayName>WPR</displayName> |
||
| 12788 | <description>write protection register</description> |
||
| 12789 | <addressOffset>0x24</addressOffset> |
||
| 12790 | <size>0x20</size> |
||
| 12791 | <access>write-only</access> |
||
| 12792 | <resetValue>0x00000000</resetValue> |
||
| 12793 | <fields> |
||
| 12794 | <field> |
||
| 12795 | <name>KEY</name> |
||
| 12796 | <description>Write protection key</description> |
||
| 12797 | <bitOffset>0</bitOffset> |
||
| 12798 | <bitWidth>8</bitWidth> |
||
| 12799 | </field> |
||
| 12800 | </fields> |
||
| 12801 | </register> |
||
| 12802 | <register> |
||
| 12803 | <name>SSR</name> |
||
| 12804 | <displayName>SSR</displayName> |
||
| 12805 | <description>sub second register</description> |
||
| 12806 | <addressOffset>0x28</addressOffset> |
||
| 12807 | <size>0x20</size> |
||
| 12808 | <access>read-only</access> |
||
| 12809 | <resetValue>0x00000000</resetValue> |
||
| 12810 | <fields> |
||
| 12811 | <field> |
||
| 12812 | <name>SS</name> |
||
| 12813 | <description>Sub second value</description> |
||
| 12814 | <bitOffset>0</bitOffset> |
||
| 12815 | <bitWidth>16</bitWidth> |
||
| 12816 | </field> |
||
| 12817 | </fields> |
||
| 12818 | </register> |
||
| 12819 | <register> |
||
| 12820 | <name>SHIFTR</name> |
||
| 12821 | <displayName>SHIFTR</displayName> |
||
| 12822 | <description>shift control register</description> |
||
| 12823 | <addressOffset>0x2C</addressOffset> |
||
| 12824 | <size>0x20</size> |
||
| 12825 | <access>write-only</access> |
||
| 12826 | <resetValue>0x00000000</resetValue> |
||
| 12827 | <fields> |
||
| 12828 | <field> |
||
| 12829 | <name>ADD1S</name> |
||
| 12830 | <description>Reserved</description> |
||
| 12831 | <bitOffset>31</bitOffset> |
||
| 12832 | <bitWidth>1</bitWidth> |
||
| 12833 | </field> |
||
| 12834 | <field> |
||
| 12835 | <name>SUBFS</name> |
||
| 12836 | <description>Subtract a fraction of a |
||
| 12837 | second</description> |
||
| 12838 | <bitOffset>0</bitOffset> |
||
| 12839 | <bitWidth>15</bitWidth> |
||
| 12840 | </field> |
||
| 12841 | </fields> |
||
| 12842 | </register> |
||
| 12843 | <register> |
||
| 12844 | <name>TSTR</name> |
||
| 12845 | <displayName>TSTR</displayName> |
||
| 12846 | <description>timestamp time register</description> |
||
| 12847 | <addressOffset>0x30</addressOffset> |
||
| 12848 | <size>0x20</size> |
||
| 12849 | <access>read-only</access> |
||
| 12850 | <resetValue>0x00000000</resetValue> |
||
| 12851 | <fields> |
||
| 12852 | <field> |
||
| 12853 | <name>PM</name> |
||
| 12854 | <description>AM/PM notation</description> |
||
| 12855 | <bitOffset>22</bitOffset> |
||
| 12856 | <bitWidth>1</bitWidth> |
||
| 12857 | </field> |
||
| 12858 | <field> |
||
| 12859 | <name>HT</name> |
||
| 12860 | <description>Hour tens in BCD format.</description> |
||
| 12861 | <bitOffset>20</bitOffset> |
||
| 12862 | <bitWidth>2</bitWidth> |
||
| 12863 | </field> |
||
| 12864 | <field> |
||
| 12865 | <name>HU</name> |
||
| 12866 | <description>Hour units in BCD format.</description> |
||
| 12867 | <bitOffset>16</bitOffset> |
||
| 12868 | <bitWidth>4</bitWidth> |
||
| 12869 | </field> |
||
| 12870 | <field> |
||
| 12871 | <name>MNT</name> |
||
| 12872 | <description>Minute tens in BCD format.</description> |
||
| 12873 | <bitOffset>12</bitOffset> |
||
| 12874 | <bitWidth>3</bitWidth> |
||
| 12875 | </field> |
||
| 12876 | <field> |
||
| 12877 | <name>MNU</name> |
||
| 12878 | <description>Minute units in BCD |
||
| 12879 | format.</description> |
||
| 12880 | <bitOffset>8</bitOffset> |
||
| 12881 | <bitWidth>4</bitWidth> |
||
| 12882 | </field> |
||
| 12883 | <field> |
||
| 12884 | <name>ST</name> |
||
| 12885 | <description>Second tens in BCD format.</description> |
||
| 12886 | <bitOffset>4</bitOffset> |
||
| 12887 | <bitWidth>3</bitWidth> |
||
| 12888 | </field> |
||
| 12889 | <field> |
||
| 12890 | <name>SU</name> |
||
| 12891 | <description>Second units in BCD |
||
| 12892 | format.</description> |
||
| 12893 | <bitOffset>0</bitOffset> |
||
| 12894 | <bitWidth>4</bitWidth> |
||
| 12895 | </field> |
||
| 12896 | </fields> |
||
| 12897 | </register> |
||
| 12898 | <register> |
||
| 12899 | <name>TSDR</name> |
||
| 12900 | <displayName>TSDR</displayName> |
||
| 12901 | <description>timestamp date register</description> |
||
| 12902 | <addressOffset>0x34</addressOffset> |
||
| 12903 | <size>0x20</size> |
||
| 12904 | <access>read-only</access> |
||
| 12905 | <resetValue>0x00000000</resetValue> |
||
| 12906 | <fields> |
||
| 12907 | <field> |
||
| 12908 | <name>WDU</name> |
||
| 12909 | <description>Week day units</description> |
||
| 12910 | <bitOffset>13</bitOffset> |
||
| 12911 | <bitWidth>3</bitWidth> |
||
| 12912 | </field> |
||
| 12913 | <field> |
||
| 12914 | <name>MT</name> |
||
| 12915 | <description>Month tens in BCD format</description> |
||
| 12916 | <bitOffset>12</bitOffset> |
||
| 12917 | <bitWidth>1</bitWidth> |
||
| 12918 | </field> |
||
| 12919 | <field> |
||
| 12920 | <name>MU</name> |
||
| 12921 | <description>Month units in BCD format</description> |
||
| 12922 | <bitOffset>8</bitOffset> |
||
| 12923 | <bitWidth>4</bitWidth> |
||
| 12924 | </field> |
||
| 12925 | <field> |
||
| 12926 | <name>DT</name> |
||
| 12927 | <description>Date tens in BCD format</description> |
||
| 12928 | <bitOffset>4</bitOffset> |
||
| 12929 | <bitWidth>2</bitWidth> |
||
| 12930 | </field> |
||
| 12931 | <field> |
||
| 12932 | <name>DU</name> |
||
| 12933 | <description>Date units in BCD format</description> |
||
| 12934 | <bitOffset>0</bitOffset> |
||
| 12935 | <bitWidth>4</bitWidth> |
||
| 12936 | </field> |
||
| 12937 | </fields> |
||
| 12938 | </register> |
||
| 12939 | <register> |
||
| 12940 | <name>TSSSR</name> |
||
| 12941 | <displayName>TSSSR</displayName> |
||
| 12942 | <description>time-stamp sub second register</description> |
||
| 12943 | <addressOffset>0x38</addressOffset> |
||
| 12944 | <size>0x20</size> |
||
| 12945 | <access>read-only</access> |
||
| 12946 | <resetValue>0x00000000</resetValue> |
||
| 12947 | <fields> |
||
| 12948 | <field> |
||
| 12949 | <name>SS</name> |
||
| 12950 | <description>Sub second value</description> |
||
| 12951 | <bitOffset>0</bitOffset> |
||
| 12952 | <bitWidth>16</bitWidth> |
||
| 12953 | </field> |
||
| 12954 | </fields> |
||
| 12955 | </register> |
||
| 12956 | <register> |
||
| 12957 | <name>CALR</name> |
||
| 12958 | <displayName>CALR</displayName> |
||
| 12959 | <description>calibration register</description> |
||
| 12960 | <addressOffset>0x3C</addressOffset> |
||
| 12961 | <size>0x20</size> |
||
| 12962 | <access>read-write</access> |
||
| 12963 | <resetValue>0x00000000</resetValue> |
||
| 12964 | <fields> |
||
| 12965 | <field> |
||
| 12966 | <name>CALP</name> |
||
| 12967 | <description>Use an 8-second calibration cycle |
||
| 12968 | period</description> |
||
| 12969 | <bitOffset>15</bitOffset> |
||
| 12970 | <bitWidth>1</bitWidth> |
||
| 12971 | </field> |
||
| 12972 | <field> |
||
| 12973 | <name>CALW8</name> |
||
| 12974 | <description>Use a 16-second calibration cycle |
||
| 12975 | period</description> |
||
| 12976 | <bitOffset>14</bitOffset> |
||
| 12977 | <bitWidth>1</bitWidth> |
||
| 12978 | </field> |
||
| 12979 | <field> |
||
| 12980 | <name>CALW16</name> |
||
| 12981 | <description>Reserved</description> |
||
| 12982 | <bitOffset>13</bitOffset> |
||
| 12983 | <bitWidth>1</bitWidth> |
||
| 12984 | </field> |
||
| 12985 | <field> |
||
| 12986 | <name>CALM</name> |
||
| 12987 | <description>Calibration minus</description> |
||
| 12988 | <bitOffset>0</bitOffset> |
||
| 12989 | <bitWidth>9</bitWidth> |
||
| 12990 | </field> |
||
| 12991 | </fields> |
||
| 12992 | </register> |
||
| 12993 | <register> |
||
| 12994 | <name>TAFCR</name> |
||
| 12995 | <displayName>TAFCR</displayName> |
||
| 12996 | <description>tamper and alternate function configuration |
||
| 12997 | register</description> |
||
| 12998 | <addressOffset>0x40</addressOffset> |
||
| 12999 | <size>0x20</size> |
||
| 13000 | <access>read-write</access> |
||
| 13001 | <resetValue>0x00000000</resetValue> |
||
| 13002 | <fields> |
||
| 13003 | <field> |
||
| 13004 | <name>PC15MODE</name> |
||
| 13005 | <description>PC15 mode</description> |
||
| 13006 | <bitOffset>23</bitOffset> |
||
| 13007 | <bitWidth>1</bitWidth> |
||
| 13008 | </field> |
||
| 13009 | <field> |
||
| 13010 | <name>PC15VALUE</name> |
||
| 13011 | <description>PC15 value</description> |
||
| 13012 | <bitOffset>22</bitOffset> |
||
| 13013 | <bitWidth>1</bitWidth> |
||
| 13014 | </field> |
||
| 13015 | <field> |
||
| 13016 | <name>PC14MODE</name> |
||
| 13017 | <description>PC14 mode</description> |
||
| 13018 | <bitOffset>21</bitOffset> |
||
| 13019 | <bitWidth>1</bitWidth> |
||
| 13020 | </field> |
||
| 13021 | <field> |
||
| 13022 | <name>PC14VALUE</name> |
||
| 13023 | <description>PC14 value</description> |
||
| 13024 | <bitOffset>20</bitOffset> |
||
| 13025 | <bitWidth>1</bitWidth> |
||
| 13026 | </field> |
||
| 13027 | <field> |
||
| 13028 | <name>PC13MODE</name> |
||
| 13029 | <description>PC13 mode</description> |
||
| 13030 | <bitOffset>19</bitOffset> |
||
| 13031 | <bitWidth>1</bitWidth> |
||
| 13032 | </field> |
||
| 13033 | <field> |
||
| 13034 | <name>PC13VALUE</name> |
||
| 13035 | <description>RTC_ALARM output type/PC13 |
||
| 13036 | value</description> |
||
| 13037 | <bitOffset>18</bitOffset> |
||
| 13038 | <bitWidth>1</bitWidth> |
||
| 13039 | </field> |
||
| 13040 | <field> |
||
| 13041 | <name>TAMP_PUDIS</name> |
||
| 13042 | <description>RTC_TAMPx pull-up disable</description> |
||
| 13043 | <bitOffset>15</bitOffset> |
||
| 13044 | <bitWidth>1</bitWidth> |
||
| 13045 | </field> |
||
| 13046 | <field> |
||
| 13047 | <name>TAMP_PRCH</name> |
||
| 13048 | <description>RTC_TAMPx precharge |
||
| 13049 | duration</description> |
||
| 13050 | <bitOffset>13</bitOffset> |
||
| 13051 | <bitWidth>2</bitWidth> |
||
| 13052 | </field> |
||
| 13053 | <field> |
||
| 13054 | <name>TAMPFLT</name> |
||
| 13055 | <description>RTC_TAMPx filter count</description> |
||
| 13056 | <bitOffset>11</bitOffset> |
||
| 13057 | <bitWidth>2</bitWidth> |
||
| 13058 | </field> |
||
| 13059 | <field> |
||
| 13060 | <name>TAMPFREQ</name> |
||
| 13061 | <description>Tamper sampling frequency</description> |
||
| 13062 | <bitOffset>8</bitOffset> |
||
| 13063 | <bitWidth>3</bitWidth> |
||
| 13064 | </field> |
||
| 13065 | <field> |
||
| 13066 | <name>TAMPTS</name> |
||
| 13067 | <description>Activate timestamp on tamper detection |
||
| 13068 | event</description> |
||
| 13069 | <bitOffset>7</bitOffset> |
||
| 13070 | <bitWidth>1</bitWidth> |
||
| 13071 | </field> |
||
| 13072 | <field> |
||
| 13073 | <name>TAMP2_TRG</name> |
||
| 13074 | <description>Active level for RTC_TAMP2 |
||
| 13075 | input</description> |
||
| 13076 | <bitOffset>4</bitOffset> |
||
| 13077 | <bitWidth>1</bitWidth> |
||
| 13078 | </field> |
||
| 13079 | <field> |
||
| 13080 | <name>TAMP2E</name> |
||
| 13081 | <description>RTC_TAMP2 input detection |
||
| 13082 | enable</description> |
||
| 13083 | <bitOffset>3</bitOffset> |
||
| 13084 | <bitWidth>1</bitWidth> |
||
| 13085 | </field> |
||
| 13086 | <field> |
||
| 13087 | <name>TAMPIE</name> |
||
| 13088 | <description>Tamper interrupt enable</description> |
||
| 13089 | <bitOffset>2</bitOffset> |
||
| 13090 | <bitWidth>1</bitWidth> |
||
| 13091 | </field> |
||
| 13092 | <field> |
||
| 13093 | <name>TAMP1TRG</name> |
||
| 13094 | <description>Active level for RTC_TAMP1 |
||
| 13095 | input</description> |
||
| 13096 | <bitOffset>1</bitOffset> |
||
| 13097 | <bitWidth>1</bitWidth> |
||
| 13098 | </field> |
||
| 13099 | <field> |
||
| 13100 | <name>TAMP1E</name> |
||
| 13101 | <description>RTC_TAMP1 input detection |
||
| 13102 | enable</description> |
||
| 13103 | <bitOffset>0</bitOffset> |
||
| 13104 | <bitWidth>1</bitWidth> |
||
| 13105 | </field> |
||
| 13106 | </fields> |
||
| 13107 | </register> |
||
| 13108 | <register> |
||
| 13109 | <name>ALRMASSR</name> |
||
| 13110 | <displayName>ALRMASSR</displayName> |
||
| 13111 | <description>alarm A sub second register</description> |
||
| 13112 | <addressOffset>0x44</addressOffset> |
||
| 13113 | <size>0x20</size> |
||
| 13114 | <access>read-write</access> |
||
| 13115 | <resetValue>0x00000000</resetValue> |
||
| 13116 | <fields> |
||
| 13117 | <field> |
||
| 13118 | <name>MASKSS</name> |
||
| 13119 | <description>Mask the most-significant bits starting |
||
| 13120 | at this bit</description> |
||
| 13121 | <bitOffset>24</bitOffset> |
||
| 13122 | <bitWidth>4</bitWidth> |
||
| 13123 | </field> |
||
| 13124 | <field> |
||
| 13125 | <name>SS</name> |
||
| 13126 | <description>Sub seconds value</description> |
||
| 13127 | <bitOffset>0</bitOffset> |
||
| 13128 | <bitWidth>15</bitWidth> |
||
| 13129 | </field> |
||
| 13130 | </fields> |
||
| 13131 | </register> |
||
| 13132 | <register> |
||
| 13133 | <name>BKP0R</name> |
||
| 13134 | <displayName>BKP0R</displayName> |
||
| 13135 | <description>backup register</description> |
||
| 13136 | <addressOffset>0x50</addressOffset> |
||
| 13137 | <size>0x20</size> |
||
| 13138 | <access>read-write</access> |
||
| 13139 | <resetValue>0x00000000</resetValue> |
||
| 13140 | <fields> |
||
| 13141 | <field> |
||
| 13142 | <name>BKP</name> |
||
| 13143 | <description>BKP</description> |
||
| 13144 | <bitOffset>0</bitOffset> |
||
| 13145 | <bitWidth>32</bitWidth> |
||
| 13146 | </field> |
||
| 13147 | </fields> |
||
| 13148 | </register> |
||
| 13149 | <register> |
||
| 13150 | <name>BKP1R</name> |
||
| 13151 | <displayName>BKP1R</displayName> |
||
| 13152 | <description>backup register</description> |
||
| 13153 | <addressOffset>0x54</addressOffset> |
||
| 13154 | <size>0x20</size> |
||
| 13155 | <access>read-write</access> |
||
| 13156 | <resetValue>0x00000000</resetValue> |
||
| 13157 | <fields> |
||
| 13158 | <field> |
||
| 13159 | <name>BKP</name> |
||
| 13160 | <description>BKP</description> |
||
| 13161 | <bitOffset>0</bitOffset> |
||
| 13162 | <bitWidth>32</bitWidth> |
||
| 13163 | </field> |
||
| 13164 | </fields> |
||
| 13165 | </register> |
||
| 13166 | <register> |
||
| 13167 | <name>BKP2R</name> |
||
| 13168 | <displayName>BKP2R</displayName> |
||
| 13169 | <description>backup register</description> |
||
| 13170 | <addressOffset>0x58</addressOffset> |
||
| 13171 | <size>0x20</size> |
||
| 13172 | <access>read-write</access> |
||
| 13173 | <resetValue>0x00000000</resetValue> |
||
| 13174 | <fields> |
||
| 13175 | <field> |
||
| 13176 | <name>BKP</name> |
||
| 13177 | <description>BKP</description> |
||
| 13178 | <bitOffset>0</bitOffset> |
||
| 13179 | <bitWidth>32</bitWidth> |
||
| 13180 | </field> |
||
| 13181 | </fields> |
||
| 13182 | </register> |
||
| 13183 | <register> |
||
| 13184 | <name>BKP3R</name> |
||
| 13185 | <displayName>BKP3R</displayName> |
||
| 13186 | <description>backup register</description> |
||
| 13187 | <addressOffset>0x5C</addressOffset> |
||
| 13188 | <size>0x20</size> |
||
| 13189 | <access>read-write</access> |
||
| 13190 | <resetValue>0x00000000</resetValue> |
||
| 13191 | <fields> |
||
| 13192 | <field> |
||
| 13193 | <name>BKP</name> |
||
| 13194 | <description>BKP</description> |
||
| 13195 | <bitOffset>0</bitOffset> |
||
| 13196 | <bitWidth>32</bitWidth> |
||
| 13197 | </field> |
||
| 13198 | </fields> |
||
| 13199 | </register> |
||
| 13200 | <register> |
||
| 13201 | <name>BKP4R</name> |
||
| 13202 | <displayName>BKP4R</displayName> |
||
| 13203 | <description>backup register</description> |
||
| 13204 | <addressOffset>0x60</addressOffset> |
||
| 13205 | <size>0x20</size> |
||
| 13206 | <access>read-write</access> |
||
| 13207 | <resetValue>0x00000000</resetValue> |
||
| 13208 | <fields> |
||
| 13209 | <field> |
||
| 13210 | <name>BKP</name> |
||
| 13211 | <description>BKP</description> |
||
| 13212 | <bitOffset>0</bitOffset> |
||
| 13213 | <bitWidth>32</bitWidth> |
||
| 13214 | </field> |
||
| 13215 | </fields> |
||
| 13216 | </register> |
||
| 13217 | </registers> |
||
| 13218 | </peripheral> |
||
| 13219 | <peripheral> |
||
| 13220 | <name>TIM15</name> |
||
| 13221 | <description>General-purpose-timers</description> |
||
| 13222 | <groupName>TIM</groupName> |
||
| 13223 | <baseAddress>0x40014000</baseAddress> |
||
| 13224 | <addressBlock> |
||
| 13225 | <offset>0x0</offset> |
||
| 13226 | <size>0x400</size> |
||
| 13227 | <usage>registers</usage> |
||
| 13228 | </addressBlock> |
||
| 13229 | <interrupt> |
||
| 13230 | <name>USART1</name> |
||
| 13231 | <description>USART1 global interrupt</description> |
||
| 13232 | <value>27</value> |
||
| 13233 | </interrupt> |
||
| 13234 | <registers> |
||
| 13235 | <register> |
||
| 13236 | <name>CR1</name> |
||
| 13237 | <displayName>CR1</displayName> |
||
| 13238 | <description>control register 1</description> |
||
| 13239 | <addressOffset>0x0</addressOffset> |
||
| 13240 | <size>0x20</size> |
||
| 13241 | <access>read-write</access> |
||
| 13242 | <resetValue>0x0000</resetValue> |
||
| 13243 | <fields> |
||
| 13244 | <field> |
||
| 13245 | <name>CKD</name> |
||
| 13246 | <description>Clock division</description> |
||
| 13247 | <bitOffset>8</bitOffset> |
||
| 13248 | <bitWidth>2</bitWidth> |
||
| 13249 | </field> |
||
| 13250 | <field> |
||
| 13251 | <name>ARPE</name> |
||
| 13252 | <description>Auto-reload preload enable</description> |
||
| 13253 | <bitOffset>7</bitOffset> |
||
| 13254 | <bitWidth>1</bitWidth> |
||
| 13255 | </field> |
||
| 13256 | <field> |
||
| 13257 | <name>OPM</name> |
||
| 13258 | <description>One-pulse mode</description> |
||
| 13259 | <bitOffset>3</bitOffset> |
||
| 13260 | <bitWidth>1</bitWidth> |
||
| 13261 | </field> |
||
| 13262 | <field> |
||
| 13263 | <name>URS</name> |
||
| 13264 | <description>Update request source</description> |
||
| 13265 | <bitOffset>2</bitOffset> |
||
| 13266 | <bitWidth>1</bitWidth> |
||
| 13267 | </field> |
||
| 13268 | <field> |
||
| 13269 | <name>UDIS</name> |
||
| 13270 | <description>Update disable</description> |
||
| 13271 | <bitOffset>1</bitOffset> |
||
| 13272 | <bitWidth>1</bitWidth> |
||
| 13273 | </field> |
||
| 13274 | <field> |
||
| 13275 | <name>CEN</name> |
||
| 13276 | <description>Counter enable</description> |
||
| 13277 | <bitOffset>0</bitOffset> |
||
| 13278 | <bitWidth>1</bitWidth> |
||
| 13279 | </field> |
||
| 13280 | </fields> |
||
| 13281 | </register> |
||
| 13282 | <register> |
||
| 13283 | <name>CR2</name> |
||
| 13284 | <displayName>CR2</displayName> |
||
| 13285 | <description>control register 2</description> |
||
| 13286 | <addressOffset>0x4</addressOffset> |
||
| 13287 | <size>0x20</size> |
||
| 13288 | <access>read-write</access> |
||
| 13289 | <resetValue>0x0000</resetValue> |
||
| 13290 | <fields> |
||
| 13291 | <field> |
||
| 13292 | <name>OIS2</name> |
||
| 13293 | <description>Output Idle state 2</description> |
||
| 13294 | <bitOffset>10</bitOffset> |
||
| 13295 | <bitWidth>1</bitWidth> |
||
| 13296 | </field> |
||
| 13297 | <field> |
||
| 13298 | <name>OIS1N</name> |
||
| 13299 | <description>Output Idle state 1</description> |
||
| 13300 | <bitOffset>9</bitOffset> |
||
| 13301 | <bitWidth>1</bitWidth> |
||
| 13302 | </field> |
||
| 13303 | <field> |
||
| 13304 | <name>OIS1</name> |
||
| 13305 | <description>Output Idle state 1</description> |
||
| 13306 | <bitOffset>8</bitOffset> |
||
| 13307 | <bitWidth>1</bitWidth> |
||
| 13308 | </field> |
||
| 13309 | <field> |
||
| 13310 | <name>MMS</name> |
||
| 13311 | <description>Master mode selection</description> |
||
| 13312 | <bitOffset>4</bitOffset> |
||
| 13313 | <bitWidth>3</bitWidth> |
||
| 13314 | </field> |
||
| 13315 | <field> |
||
| 13316 | <name>CCDS</name> |
||
| 13317 | <description>Capture/compare DMA |
||
| 13318 | selection</description> |
||
| 13319 | <bitOffset>3</bitOffset> |
||
| 13320 | <bitWidth>1</bitWidth> |
||
| 13321 | </field> |
||
| 13322 | <field> |
||
| 13323 | <name>CCUS</name> |
||
| 13324 | <description>Capture/compare control update |
||
| 13325 | selection</description> |
||
| 13326 | <bitOffset>2</bitOffset> |
||
| 13327 | <bitWidth>1</bitWidth> |
||
| 13328 | </field> |
||
| 13329 | <field> |
||
| 13330 | <name>CCPC</name> |
||
| 13331 | <description>Capture/compare preloaded |
||
| 13332 | control</description> |
||
| 13333 | <bitOffset>0</bitOffset> |
||
| 13334 | <bitWidth>1</bitWidth> |
||
| 13335 | </field> |
||
| 13336 | </fields> |
||
| 13337 | </register> |
||
| 13338 | <register> |
||
| 13339 | <name>SMCR</name> |
||
| 13340 | <displayName>SMCR</displayName> |
||
| 13341 | <description>slave mode control register</description> |
||
| 13342 | <addressOffset>0x8</addressOffset> |
||
| 13343 | <size>0x20</size> |
||
| 13344 | <access>read-write</access> |
||
| 13345 | <resetValue>0x0000</resetValue> |
||
| 13346 | <fields> |
||
| 13347 | <field> |
||
| 13348 | <name>MSM</name> |
||
| 13349 | <description>Master/Slave mode</description> |
||
| 13350 | <bitOffset>7</bitOffset> |
||
| 13351 | <bitWidth>1</bitWidth> |
||
| 13352 | </field> |
||
| 13353 | <field> |
||
| 13354 | <name>TS</name> |
||
| 13355 | <description>Trigger selection</description> |
||
| 13356 | <bitOffset>4</bitOffset> |
||
| 13357 | <bitWidth>3</bitWidth> |
||
| 13358 | </field> |
||
| 13359 | <field> |
||
| 13360 | <name>SMS</name> |
||
| 13361 | <description>Slave mode selection</description> |
||
| 13362 | <bitOffset>0</bitOffset> |
||
| 13363 | <bitWidth>3</bitWidth> |
||
| 13364 | </field> |
||
| 13365 | </fields> |
||
| 13366 | </register> |
||
| 13367 | <register> |
||
| 13368 | <name>DIER</name> |
||
| 13369 | <displayName>DIER</displayName> |
||
| 13370 | <description>DMA/Interrupt enable register</description> |
||
| 13371 | <addressOffset>0xC</addressOffset> |
||
| 13372 | <size>0x20</size> |
||
| 13373 | <access>read-write</access> |
||
| 13374 | <resetValue>0x0000</resetValue> |
||
| 13375 | <fields> |
||
| 13376 | <field> |
||
| 13377 | <name>TDE</name> |
||
| 13378 | <description>Trigger DMA request enable</description> |
||
| 13379 | <bitOffset>14</bitOffset> |
||
| 13380 | <bitWidth>1</bitWidth> |
||
| 13381 | </field> |
||
| 13382 | <field> |
||
| 13383 | <name>CC2DE</name> |
||
| 13384 | <description>Capture/Compare 2 DMA request |
||
| 13385 | enable</description> |
||
| 13386 | <bitOffset>10</bitOffset> |
||
| 13387 | <bitWidth>1</bitWidth> |
||
| 13388 | </field> |
||
| 13389 | <field> |
||
| 13390 | <name>CC1DE</name> |
||
| 13391 | <description>Capture/Compare 1 DMA request |
||
| 13392 | enable</description> |
||
| 13393 | <bitOffset>9</bitOffset> |
||
| 13394 | <bitWidth>1</bitWidth> |
||
| 13395 | </field> |
||
| 13396 | <field> |
||
| 13397 | <name>UDE</name> |
||
| 13398 | <description>Update DMA request enable</description> |
||
| 13399 | <bitOffset>8</bitOffset> |
||
| 13400 | <bitWidth>1</bitWidth> |
||
| 13401 | </field> |
||
| 13402 | <field> |
||
| 13403 | <name>BIE</name> |
||
| 13404 | <description>Break interrupt enable</description> |
||
| 13405 | <bitOffset>7</bitOffset> |
||
| 13406 | <bitWidth>1</bitWidth> |
||
| 13407 | </field> |
||
| 13408 | <field> |
||
| 13409 | <name>TIE</name> |
||
| 13410 | <description>Trigger interrupt enable</description> |
||
| 13411 | <bitOffset>6</bitOffset> |
||
| 13412 | <bitWidth>1</bitWidth> |
||
| 13413 | </field> |
||
| 13414 | <field> |
||
| 13415 | <name>COMIE</name> |
||
| 13416 | <description>COM interrupt enable</description> |
||
| 13417 | <bitOffset>5</bitOffset> |
||
| 13418 | <bitWidth>1</bitWidth> |
||
| 13419 | </field> |
||
| 13420 | <field> |
||
| 13421 | <name>CC2IE</name> |
||
| 13422 | <description>Capture/Compare 2 interrupt |
||
| 13423 | enable</description> |
||
| 13424 | <bitOffset>2</bitOffset> |
||
| 13425 | <bitWidth>1</bitWidth> |
||
| 13426 | </field> |
||
| 13427 | <field> |
||
| 13428 | <name>CC1IE</name> |
||
| 13429 | <description>Capture/Compare 1 interrupt |
||
| 13430 | enable</description> |
||
| 13431 | <bitOffset>1</bitOffset> |
||
| 13432 | <bitWidth>1</bitWidth> |
||
| 13433 | </field> |
||
| 13434 | <field> |
||
| 13435 | <name>UIE</name> |
||
| 13436 | <description>Update interrupt enable</description> |
||
| 13437 | <bitOffset>0</bitOffset> |
||
| 13438 | <bitWidth>1</bitWidth> |
||
| 13439 | </field> |
||
| 13440 | </fields> |
||
| 13441 | </register> |
||
| 13442 | <register> |
||
| 13443 | <name>SR</name> |
||
| 13444 | <displayName>SR</displayName> |
||
| 13445 | <description>status register</description> |
||
| 13446 | <addressOffset>0x10</addressOffset> |
||
| 13447 | <size>0x20</size> |
||
| 13448 | <access>read-write</access> |
||
| 13449 | <resetValue>0x0000</resetValue> |
||
| 13450 | <fields> |
||
| 13451 | <field> |
||
| 13452 | <name>CC2OF</name> |
||
| 13453 | <description>Capture/compare 2 overcapture |
||
| 13454 | flag</description> |
||
| 13455 | <bitOffset>10</bitOffset> |
||
| 13456 | <bitWidth>1</bitWidth> |
||
| 13457 | </field> |
||
| 13458 | <field> |
||
| 13459 | <name>CC1OF</name> |
||
| 13460 | <description>Capture/Compare 1 overcapture |
||
| 13461 | flag</description> |
||
| 13462 | <bitOffset>9</bitOffset> |
||
| 13463 | <bitWidth>1</bitWidth> |
||
| 13464 | </field> |
||
| 13465 | <field> |
||
| 13466 | <name>BIF</name> |
||
| 13467 | <description>Break interrupt flag</description> |
||
| 13468 | <bitOffset>7</bitOffset> |
||
| 13469 | <bitWidth>1</bitWidth> |
||
| 13470 | </field> |
||
| 13471 | <field> |
||
| 13472 | <name>TIF</name> |
||
| 13473 | <description>Trigger interrupt flag</description> |
||
| 13474 | <bitOffset>6</bitOffset> |
||
| 13475 | <bitWidth>1</bitWidth> |
||
| 13476 | </field> |
||
| 13477 | <field> |
||
| 13478 | <name>COMIF</name> |
||
| 13479 | <description>COM interrupt flag</description> |
||
| 13480 | <bitOffset>5</bitOffset> |
||
| 13481 | <bitWidth>1</bitWidth> |
||
| 13482 | </field> |
||
| 13483 | <field> |
||
| 13484 | <name>CC2IF</name> |
||
| 13485 | <description>Capture/Compare 2 interrupt |
||
| 13486 | flag</description> |
||
| 13487 | <bitOffset>2</bitOffset> |
||
| 13488 | <bitWidth>1</bitWidth> |
||
| 13489 | </field> |
||
| 13490 | <field> |
||
| 13491 | <name>CC1IF</name> |
||
| 13492 | <description>Capture/compare 1 interrupt |
||
| 13493 | flag</description> |
||
| 13494 | <bitOffset>1</bitOffset> |
||
| 13495 | <bitWidth>1</bitWidth> |
||
| 13496 | </field> |
||
| 13497 | <field> |
||
| 13498 | <name>UIF</name> |
||
| 13499 | <description>Update interrupt flag</description> |
||
| 13500 | <bitOffset>0</bitOffset> |
||
| 13501 | <bitWidth>1</bitWidth> |
||
| 13502 | </field> |
||
| 13503 | </fields> |
||
| 13504 | </register> |
||
| 13505 | <register> |
||
| 13506 | <name>EGR</name> |
||
| 13507 | <displayName>EGR</displayName> |
||
| 13508 | <description>event generation register</description> |
||
| 13509 | <addressOffset>0x14</addressOffset> |
||
| 13510 | <size>0x20</size> |
||
| 13511 | <access>write-only</access> |
||
| 13512 | <resetValue>0x0000</resetValue> |
||
| 13513 | <fields> |
||
| 13514 | <field> |
||
| 13515 | <name>BG</name> |
||
| 13516 | <description>Break generation</description> |
||
| 13517 | <bitOffset>7</bitOffset> |
||
| 13518 | <bitWidth>1</bitWidth> |
||
| 13519 | </field> |
||
| 13520 | <field> |
||
| 13521 | <name>TG</name> |
||
| 13522 | <description>Trigger generation</description> |
||
| 13523 | <bitOffset>6</bitOffset> |
||
| 13524 | <bitWidth>1</bitWidth> |
||
| 13525 | </field> |
||
| 13526 | <field> |
||
| 13527 | <name>COMG</name> |
||
| 13528 | <description>Capture/Compare control update |
||
| 13529 | generation</description> |
||
| 13530 | <bitOffset>5</bitOffset> |
||
| 13531 | <bitWidth>1</bitWidth> |
||
| 13532 | </field> |
||
| 13533 | <field> |
||
| 13534 | <name>CC2G</name> |
||
| 13535 | <description>Capture/compare 2 |
||
| 13536 | generation</description> |
||
| 13537 | <bitOffset>2</bitOffset> |
||
| 13538 | <bitWidth>1</bitWidth> |
||
| 13539 | </field> |
||
| 13540 | <field> |
||
| 13541 | <name>CC1G</name> |
||
| 13542 | <description>Capture/compare 1 |
||
| 13543 | generation</description> |
||
| 13544 | <bitOffset>1</bitOffset> |
||
| 13545 | <bitWidth>1</bitWidth> |
||
| 13546 | </field> |
||
| 13547 | <field> |
||
| 13548 | <name>UG</name> |
||
| 13549 | <description>Update generation</description> |
||
| 13550 | <bitOffset>0</bitOffset> |
||
| 13551 | <bitWidth>1</bitWidth> |
||
| 13552 | </field> |
||
| 13553 | </fields> |
||
| 13554 | </register> |
||
| 13555 | <register> |
||
| 13556 | <name>CCMR1_Output</name> |
||
| 13557 | <displayName>CCMR1_Output</displayName> |
||
| 13558 | <description>capture/compare mode register (output |
||
| 13559 | mode)</description> |
||
| 13560 | <addressOffset>0x18</addressOffset> |
||
| 13561 | <size>0x20</size> |
||
| 13562 | <access>read-write</access> |
||
| 13563 | <resetValue>0x00000000</resetValue> |
||
| 13564 | <fields> |
||
| 13565 | <field> |
||
| 13566 | <name>OC2M</name> |
||
| 13567 | <description>Output Compare 2 mode</description> |
||
| 13568 | <bitOffset>12</bitOffset> |
||
| 13569 | <bitWidth>3</bitWidth> |
||
| 13570 | </field> |
||
| 13571 | <field> |
||
| 13572 | <name>OC2PE</name> |
||
| 13573 | <description>Output Compare 2 preload |
||
| 13574 | enable</description> |
||
| 13575 | <bitOffset>11</bitOffset> |
||
| 13576 | <bitWidth>1</bitWidth> |
||
| 13577 | </field> |
||
| 13578 | <field> |
||
| 13579 | <name>OC2FE</name> |
||
| 13580 | <description>Output Compare 2 fast |
||
| 13581 | enable</description> |
||
| 13582 | <bitOffset>10</bitOffset> |
||
| 13583 | <bitWidth>1</bitWidth> |
||
| 13584 | </field> |
||
| 13585 | <field> |
||
| 13586 | <name>CC2S</name> |
||
| 13587 | <description>Capture/Compare 2 |
||
| 13588 | selection</description> |
||
| 13589 | <bitOffset>8</bitOffset> |
||
| 13590 | <bitWidth>2</bitWidth> |
||
| 13591 | </field> |
||
| 13592 | <field> |
||
| 13593 | <name>OC1M</name> |
||
| 13594 | <description>Output Compare 1 mode</description> |
||
| 13595 | <bitOffset>4</bitOffset> |
||
| 13596 | <bitWidth>3</bitWidth> |
||
| 13597 | </field> |
||
| 13598 | <field> |
||
| 13599 | <name>OC1PE</name> |
||
| 13600 | <description>Output Compare 1 preload |
||
| 13601 | enable</description> |
||
| 13602 | <bitOffset>3</bitOffset> |
||
| 13603 | <bitWidth>1</bitWidth> |
||
| 13604 | </field> |
||
| 13605 | <field> |
||
| 13606 | <name>OC1FE</name> |
||
| 13607 | <description>Output Compare 1 fast |
||
| 13608 | enable</description> |
||
| 13609 | <bitOffset>2</bitOffset> |
||
| 13610 | <bitWidth>1</bitWidth> |
||
| 13611 | </field> |
||
| 13612 | <field> |
||
| 13613 | <name>CC1S</name> |
||
| 13614 | <description>Capture/Compare 1 |
||
| 13615 | selection</description> |
||
| 13616 | <bitOffset>0</bitOffset> |
||
| 13617 | <bitWidth>2</bitWidth> |
||
| 13618 | </field> |
||
| 13619 | </fields> |
||
| 13620 | </register> |
||
| 13621 | <register> |
||
| 13622 | <name>CCMR1_Input</name> |
||
| 13623 | <displayName>CCMR1_Input</displayName> |
||
| 13624 | <description>capture/compare mode register 1 (input |
||
| 13625 | mode)</description> |
||
| 13626 | <alternateRegister>CCMR1_Output</alternateRegister> |
||
| 13627 | <addressOffset>0x18</addressOffset> |
||
| 13628 | <size>0x20</size> |
||
| 13629 | <access>read-write</access> |
||
| 13630 | <resetValue>0x00000000</resetValue> |
||
| 13631 | <fields> |
||
| 13632 | <field> |
||
| 13633 | <name>IC2F</name> |
||
| 13634 | <description>Input capture 2 filter</description> |
||
| 13635 | <bitOffset>12</bitOffset> |
||
| 13636 | <bitWidth>4</bitWidth> |
||
| 13637 | </field> |
||
| 13638 | <field> |
||
| 13639 | <name>IC2PSC</name> |
||
| 13640 | <description>Input capture 2 prescaler</description> |
||
| 13641 | <bitOffset>10</bitOffset> |
||
| 13642 | <bitWidth>2</bitWidth> |
||
| 13643 | </field> |
||
| 13644 | <field> |
||
| 13645 | <name>CC2S</name> |
||
| 13646 | <description>Capture/Compare 2 |
||
| 13647 | selection</description> |
||
| 13648 | <bitOffset>8</bitOffset> |
||
| 13649 | <bitWidth>2</bitWidth> |
||
| 13650 | </field> |
||
| 13651 | <field> |
||
| 13652 | <name>IC1F</name> |
||
| 13653 | <description>Input capture 1 filter</description> |
||
| 13654 | <bitOffset>4</bitOffset> |
||
| 13655 | <bitWidth>4</bitWidth> |
||
| 13656 | </field> |
||
| 13657 | <field> |
||
| 13658 | <name>IC1PSC</name> |
||
| 13659 | <description>Input capture 1 prescaler</description> |
||
| 13660 | <bitOffset>2</bitOffset> |
||
| 13661 | <bitWidth>2</bitWidth> |
||
| 13662 | </field> |
||
| 13663 | <field> |
||
| 13664 | <name>CC1S</name> |
||
| 13665 | <description>Capture/Compare 1 |
||
| 13666 | selection</description> |
||
| 13667 | <bitOffset>0</bitOffset> |
||
| 13668 | <bitWidth>2</bitWidth> |
||
| 13669 | </field> |
||
| 13670 | </fields> |
||
| 13671 | </register> |
||
| 13672 | <register> |
||
| 13673 | <name>CCER</name> |
||
| 13674 | <displayName>CCER</displayName> |
||
| 13675 | <description>capture/compare enable |
||
| 13676 | register</description> |
||
| 13677 | <addressOffset>0x20</addressOffset> |
||
| 13678 | <size>0x20</size> |
||
| 13679 | <access>read-write</access> |
||
| 13680 | <resetValue>0x0000</resetValue> |
||
| 13681 | <fields> |
||
| 13682 | <field> |
||
| 13683 | <name>CC2NP</name> |
||
| 13684 | <description>Capture/Compare 2 output |
||
| 13685 | Polarity</description> |
||
| 13686 | <bitOffset>7</bitOffset> |
||
| 13687 | <bitWidth>1</bitWidth> |
||
| 13688 | </field> |
||
| 13689 | <field> |
||
| 13690 | <name>CC2P</name> |
||
| 13691 | <description>Capture/Compare 2 output |
||
| 13692 | Polarity</description> |
||
| 13693 | <bitOffset>5</bitOffset> |
||
| 13694 | <bitWidth>1</bitWidth> |
||
| 13695 | </field> |
||
| 13696 | <field> |
||
| 13697 | <name>CC2E</name> |
||
| 13698 | <description>Capture/Compare 2 output |
||
| 13699 | enable</description> |
||
| 13700 | <bitOffset>4</bitOffset> |
||
| 13701 | <bitWidth>1</bitWidth> |
||
| 13702 | </field> |
||
| 13703 | <field> |
||
| 13704 | <name>CC1NP</name> |
||
| 13705 | <description>Capture/Compare 1 output |
||
| 13706 | Polarity</description> |
||
| 13707 | <bitOffset>3</bitOffset> |
||
| 13708 | <bitWidth>1</bitWidth> |
||
| 13709 | </field> |
||
| 13710 | <field> |
||
| 13711 | <name>CC1NE</name> |
||
| 13712 | <description>Capture/Compare 1 complementary output |
||
| 13713 | enable</description> |
||
| 13714 | <bitOffset>2</bitOffset> |
||
| 13715 | <bitWidth>1</bitWidth> |
||
| 13716 | </field> |
||
| 13717 | <field> |
||
| 13718 | <name>CC1P</name> |
||
| 13719 | <description>Capture/Compare 1 output |
||
| 13720 | Polarity</description> |
||
| 13721 | <bitOffset>1</bitOffset> |
||
| 13722 | <bitWidth>1</bitWidth> |
||
| 13723 | </field> |
||
| 13724 | <field> |
||
| 13725 | <name>CC1E</name> |
||
| 13726 | <description>Capture/Compare 1 output |
||
| 13727 | enable</description> |
||
| 13728 | <bitOffset>0</bitOffset> |
||
| 13729 | <bitWidth>1</bitWidth> |
||
| 13730 | </field> |
||
| 13731 | </fields> |
||
| 13732 | </register> |
||
| 13733 | <register> |
||
| 13734 | <name>CNT</name> |
||
| 13735 | <displayName>CNT</displayName> |
||
| 13736 | <description>counter</description> |
||
| 13737 | <addressOffset>0x24</addressOffset> |
||
| 13738 | <size>0x20</size> |
||
| 13739 | <access>read-write</access> |
||
| 13740 | <resetValue>0x00000000</resetValue> |
||
| 13741 | <fields> |
||
| 13742 | <field> |
||
| 13743 | <name>CNT</name> |
||
| 13744 | <description>counter value</description> |
||
| 13745 | <bitOffset>0</bitOffset> |
||
| 13746 | <bitWidth>16</bitWidth> |
||
| 13747 | </field> |
||
| 13748 | </fields> |
||
| 13749 | </register> |
||
| 13750 | <register> |
||
| 13751 | <name>PSC</name> |
||
| 13752 | <displayName>PSC</displayName> |
||
| 13753 | <description>prescaler</description> |
||
| 13754 | <addressOffset>0x28</addressOffset> |
||
| 13755 | <size>0x20</size> |
||
| 13756 | <access>read-write</access> |
||
| 13757 | <resetValue>0x0000</resetValue> |
||
| 13758 | <fields> |
||
| 13759 | <field> |
||
| 13760 | <name>PSC</name> |
||
| 13761 | <description>Prescaler value</description> |
||
| 13762 | <bitOffset>0</bitOffset> |
||
| 13763 | <bitWidth>16</bitWidth> |
||
| 13764 | </field> |
||
| 13765 | </fields> |
||
| 13766 | </register> |
||
| 13767 | <register> |
||
| 13768 | <name>ARR</name> |
||
| 13769 | <displayName>ARR</displayName> |
||
| 13770 | <description>auto-reload register</description> |
||
| 13771 | <addressOffset>0x2C</addressOffset> |
||
| 13772 | <size>0x20</size> |
||
| 13773 | <access>read-write</access> |
||
| 13774 | <resetValue>0x00000000</resetValue> |
||
| 13775 | <fields> |
||
| 13776 | <field> |
||
| 13777 | <name>ARR</name> |
||
| 13778 | <description>Auto-reload value</description> |
||
| 13779 | <bitOffset>0</bitOffset> |
||
| 13780 | <bitWidth>16</bitWidth> |
||
| 13781 | </field> |
||
| 13782 | </fields> |
||
| 13783 | </register> |
||
| 13784 | <register> |
||
| 13785 | <name>RCR</name> |
||
| 13786 | <displayName>RCR</displayName> |
||
| 13787 | <description>repetition counter register</description> |
||
| 13788 | <addressOffset>0x30</addressOffset> |
||
| 13789 | <size>0x20</size> |
||
| 13790 | <access>read-write</access> |
||
| 13791 | <resetValue>0x0000</resetValue> |
||
| 13792 | <fields> |
||
| 13793 | <field> |
||
| 13794 | <name>REP</name> |
||
| 13795 | <description>Repetition counter value</description> |
||
| 13796 | <bitOffset>0</bitOffset> |
||
| 13797 | <bitWidth>8</bitWidth> |
||
| 13798 | </field> |
||
| 13799 | </fields> |
||
| 13800 | </register> |
||
| 13801 | <register> |
||
| 13802 | <name>CCR1</name> |
||
| 13803 | <displayName>CCR1</displayName> |
||
| 13804 | <description>capture/compare register 1</description> |
||
| 13805 | <addressOffset>0x34</addressOffset> |
||
| 13806 | <size>0x20</size> |
||
| 13807 | <access>read-write</access> |
||
| 13808 | <resetValue>0x00000000</resetValue> |
||
| 13809 | <fields> |
||
| 13810 | <field> |
||
| 13811 | <name>CCR1</name> |
||
| 13812 | <description>Capture/Compare 1 value</description> |
||
| 13813 | <bitOffset>0</bitOffset> |
||
| 13814 | <bitWidth>16</bitWidth> |
||
| 13815 | </field> |
||
| 13816 | </fields> |
||
| 13817 | </register> |
||
| 13818 | <register> |
||
| 13819 | <name>CCR2</name> |
||
| 13820 | <displayName>CCR2</displayName> |
||
| 13821 | <description>capture/compare register 2</description> |
||
| 13822 | <addressOffset>0x38</addressOffset> |
||
| 13823 | <size>0x20</size> |
||
| 13824 | <access>read-write</access> |
||
| 13825 | <resetValue>0x00000000</resetValue> |
||
| 13826 | <fields> |
||
| 13827 | <field> |
||
| 13828 | <name>CCR2</name> |
||
| 13829 | <description>Capture/Compare 2 value</description> |
||
| 13830 | <bitOffset>0</bitOffset> |
||
| 13831 | <bitWidth>16</bitWidth> |
||
| 13832 | </field> |
||
| 13833 | </fields> |
||
| 13834 | </register> |
||
| 13835 | <register> |
||
| 13836 | <name>BDTR</name> |
||
| 13837 | <displayName>BDTR</displayName> |
||
| 13838 | <description>break and dead-time register</description> |
||
| 13839 | <addressOffset>0x44</addressOffset> |
||
| 13840 | <size>0x20</size> |
||
| 13841 | <access>read-write</access> |
||
| 13842 | <resetValue>0x0000</resetValue> |
||
| 13843 | <fields> |
||
| 13844 | <field> |
||
| 13845 | <name>MOE</name> |
||
| 13846 | <description>Main output enable</description> |
||
| 13847 | <bitOffset>15</bitOffset> |
||
| 13848 | <bitWidth>1</bitWidth> |
||
| 13849 | </field> |
||
| 13850 | <field> |
||
| 13851 | <name>AOE</name> |
||
| 13852 | <description>Automatic output enable</description> |
||
| 13853 | <bitOffset>14</bitOffset> |
||
| 13854 | <bitWidth>1</bitWidth> |
||
| 13855 | </field> |
||
| 13856 | <field> |
||
| 13857 | <name>BKP</name> |
||
| 13858 | <description>Break polarity</description> |
||
| 13859 | <bitOffset>13</bitOffset> |
||
| 13860 | <bitWidth>1</bitWidth> |
||
| 13861 | </field> |
||
| 13862 | <field> |
||
| 13863 | <name>BKE</name> |
||
| 13864 | <description>Break enable</description> |
||
| 13865 | <bitOffset>12</bitOffset> |
||
| 13866 | <bitWidth>1</bitWidth> |
||
| 13867 | </field> |
||
| 13868 | <field> |
||
| 13869 | <name>OSSR</name> |
||
| 13870 | <description>Off-state selection for Run |
||
| 13871 | mode</description> |
||
| 13872 | <bitOffset>11</bitOffset> |
||
| 13873 | <bitWidth>1</bitWidth> |
||
| 13874 | </field> |
||
| 13875 | <field> |
||
| 13876 | <name>OSSI</name> |
||
| 13877 | <description>Off-state selection for Idle |
||
| 13878 | mode</description> |
||
| 13879 | <bitOffset>10</bitOffset> |
||
| 13880 | <bitWidth>1</bitWidth> |
||
| 13881 | </field> |
||
| 13882 | <field> |
||
| 13883 | <name>LOCK</name> |
||
| 13884 | <description>Lock configuration</description> |
||
| 13885 | <bitOffset>8</bitOffset> |
||
| 13886 | <bitWidth>2</bitWidth> |
||
| 13887 | </field> |
||
| 13888 | <field> |
||
| 13889 | <name>DTG</name> |
||
| 13890 | <description>Dead-time generator setup</description> |
||
| 13891 | <bitOffset>0</bitOffset> |
||
| 13892 | <bitWidth>8</bitWidth> |
||
| 13893 | </field> |
||
| 13894 | </fields> |
||
| 13895 | </register> |
||
| 13896 | <register> |
||
| 13897 | <name>DCR</name> |
||
| 13898 | <displayName>DCR</displayName> |
||
| 13899 | <description>DMA control register</description> |
||
| 13900 | <addressOffset>0x48</addressOffset> |
||
| 13901 | <size>0x20</size> |
||
| 13902 | <access>read-write</access> |
||
| 13903 | <resetValue>0x0000</resetValue> |
||
| 13904 | <fields> |
||
| 13905 | <field> |
||
| 13906 | <name>DBL</name> |
||
| 13907 | <description>DMA burst length</description> |
||
| 13908 | <bitOffset>8</bitOffset> |
||
| 13909 | <bitWidth>5</bitWidth> |
||
| 13910 | </field> |
||
| 13911 | <field> |
||
| 13912 | <name>DBA</name> |
||
| 13913 | <description>DMA base address</description> |
||
| 13914 | <bitOffset>0</bitOffset> |
||
| 13915 | <bitWidth>5</bitWidth> |
||
| 13916 | </field> |
||
| 13917 | </fields> |
||
| 13918 | </register> |
||
| 13919 | <register> |
||
| 13920 | <name>DMAR</name> |
||
| 13921 | <displayName>DMAR</displayName> |
||
| 13922 | <description>DMA address for full transfer</description> |
||
| 13923 | <addressOffset>0x4C</addressOffset> |
||
| 13924 | <size>0x20</size> |
||
| 13925 | <access>read-write</access> |
||
| 13926 | <resetValue>0x0000</resetValue> |
||
| 13927 | <fields> |
||
| 13928 | <field> |
||
| 13929 | <name>DMAB</name> |
||
| 13930 | <description>DMA register for burst |
||
| 13931 | accesses</description> |
||
| 13932 | <bitOffset>0</bitOffset> |
||
| 13933 | <bitWidth>16</bitWidth> |
||
| 13934 | </field> |
||
| 13935 | </fields> |
||
| 13936 | </register> |
||
| 13937 | </registers> |
||
| 13938 | </peripheral> |
||
| 13939 | <peripheral> |
||
| 13940 | <name>TIM16</name> |
||
| 13941 | <description>General-purpose-timers</description> |
||
| 13942 | <groupName>TIM</groupName> |
||
| 13943 | <baseAddress>0x40014400</baseAddress> |
||
| 13944 | <addressBlock> |
||
| 13945 | <offset>0x0</offset> |
||
| 13946 | <size>0x400</size> |
||
| 13947 | <usage>registers</usage> |
||
| 13948 | </addressBlock> |
||
| 13949 | <interrupt> |
||
| 13950 | <name>USART2</name> |
||
| 13951 | <description>USART2 global interrupt</description> |
||
| 13952 | <value>28</value> |
||
| 13953 | </interrupt> |
||
| 13954 | <registers> |
||
| 13955 | <register> |
||
| 13956 | <name>CR1</name> |
||
| 13957 | <displayName>CR1</displayName> |
||
| 13958 | <description>control register 1</description> |
||
| 13959 | <addressOffset>0x0</addressOffset> |
||
| 13960 | <size>0x20</size> |
||
| 13961 | <access>read-write</access> |
||
| 13962 | <resetValue>0x0000</resetValue> |
||
| 13963 | <fields> |
||
| 13964 | <field> |
||
| 13965 | <name>CKD</name> |
||
| 13966 | <description>Clock division</description> |
||
| 13967 | <bitOffset>8</bitOffset> |
||
| 13968 | <bitWidth>2</bitWidth> |
||
| 13969 | </field> |
||
| 13970 | <field> |
||
| 13971 | <name>ARPE</name> |
||
| 13972 | <description>Auto-reload preload enable</description> |
||
| 13973 | <bitOffset>7</bitOffset> |
||
| 13974 | <bitWidth>1</bitWidth> |
||
| 13975 | </field> |
||
| 13976 | <field> |
||
| 13977 | <name>OPM</name> |
||
| 13978 | <description>One-pulse mode</description> |
||
| 13979 | <bitOffset>3</bitOffset> |
||
| 13980 | <bitWidth>1</bitWidth> |
||
| 13981 | </field> |
||
| 13982 | <field> |
||
| 13983 | <name>URS</name> |
||
| 13984 | <description>Update request source</description> |
||
| 13985 | <bitOffset>2</bitOffset> |
||
| 13986 | <bitWidth>1</bitWidth> |
||
| 13987 | </field> |
||
| 13988 | <field> |
||
| 13989 | <name>UDIS</name> |
||
| 13990 | <description>Update disable</description> |
||
| 13991 | <bitOffset>1</bitOffset> |
||
| 13992 | <bitWidth>1</bitWidth> |
||
| 13993 | </field> |
||
| 13994 | <field> |
||
| 13995 | <name>CEN</name> |
||
| 13996 | <description>Counter enable</description> |
||
| 13997 | <bitOffset>0</bitOffset> |
||
| 13998 | <bitWidth>1</bitWidth> |
||
| 13999 | </field> |
||
| 14000 | </fields> |
||
| 14001 | </register> |
||
| 14002 | <register> |
||
| 14003 | <name>CR2</name> |
||
| 14004 | <displayName>CR2</displayName> |
||
| 14005 | <description>control register 2</description> |
||
| 14006 | <addressOffset>0x4</addressOffset> |
||
| 14007 | <size>0x20</size> |
||
| 14008 | <access>read-write</access> |
||
| 14009 | <resetValue>0x0000</resetValue> |
||
| 14010 | <fields> |
||
| 14011 | <field> |
||
| 14012 | <name>OIS1N</name> |
||
| 14013 | <description>Output Idle state 1</description> |
||
| 14014 | <bitOffset>9</bitOffset> |
||
| 14015 | <bitWidth>1</bitWidth> |
||
| 14016 | </field> |
||
| 14017 | <field> |
||
| 14018 | <name>OIS1</name> |
||
| 14019 | <description>Output Idle state 1</description> |
||
| 14020 | <bitOffset>8</bitOffset> |
||
| 14021 | <bitWidth>1</bitWidth> |
||
| 14022 | </field> |
||
| 14023 | <field> |
||
| 14024 | <name>CCDS</name> |
||
| 14025 | <description>Capture/compare DMA |
||
| 14026 | selection</description> |
||
| 14027 | <bitOffset>3</bitOffset> |
||
| 14028 | <bitWidth>1</bitWidth> |
||
| 14029 | </field> |
||
| 14030 | <field> |
||
| 14031 | <name>CCUS</name> |
||
| 14032 | <description>Capture/compare control update |
||
| 14033 | selection</description> |
||
| 14034 | <bitOffset>2</bitOffset> |
||
| 14035 | <bitWidth>1</bitWidth> |
||
| 14036 | </field> |
||
| 14037 | <field> |
||
| 14038 | <name>CCPC</name> |
||
| 14039 | <description>Capture/compare preloaded |
||
| 14040 | control</description> |
||
| 14041 | <bitOffset>0</bitOffset> |
||
| 14042 | <bitWidth>1</bitWidth> |
||
| 14043 | </field> |
||
| 14044 | </fields> |
||
| 14045 | </register> |
||
| 14046 | <register> |
||
| 14047 | <name>DIER</name> |
||
| 14048 | <displayName>DIER</displayName> |
||
| 14049 | <description>DMA/Interrupt enable register</description> |
||
| 14050 | <addressOffset>0xC</addressOffset> |
||
| 14051 | <size>0x20</size> |
||
| 14052 | <access>read-write</access> |
||
| 14053 | <resetValue>0x0000</resetValue> |
||
| 14054 | <fields> |
||
| 14055 | <field> |
||
| 14056 | <name>TDE</name> |
||
| 14057 | <description>Trigger DMA request enable</description> |
||
| 14058 | <bitOffset>14</bitOffset> |
||
| 14059 | <bitWidth>1</bitWidth> |
||
| 14060 | </field> |
||
| 14061 | <field> |
||
| 14062 | <name>CC1DE</name> |
||
| 14063 | <description>Capture/Compare 1 DMA request |
||
| 14064 | enable</description> |
||
| 14065 | <bitOffset>9</bitOffset> |
||
| 14066 | <bitWidth>1</bitWidth> |
||
| 14067 | </field> |
||
| 14068 | <field> |
||
| 14069 | <name>UDE</name> |
||
| 14070 | <description>Update DMA request enable</description> |
||
| 14071 | <bitOffset>8</bitOffset> |
||
| 14072 | <bitWidth>1</bitWidth> |
||
| 14073 | </field> |
||
| 14074 | <field> |
||
| 14075 | <name>BIE</name> |
||
| 14076 | <description>Break interrupt enable</description> |
||
| 14077 | <bitOffset>7</bitOffset> |
||
| 14078 | <bitWidth>1</bitWidth> |
||
| 14079 | </field> |
||
| 14080 | <field> |
||
| 14081 | <name>TIE</name> |
||
| 14082 | <description>Trigger interrupt enable</description> |
||
| 14083 | <bitOffset>6</bitOffset> |
||
| 14084 | <bitWidth>1</bitWidth> |
||
| 14085 | </field> |
||
| 14086 | <field> |
||
| 14087 | <name>COMIE</name> |
||
| 14088 | <description>COM interrupt enable</description> |
||
| 14089 | <bitOffset>5</bitOffset> |
||
| 14090 | <bitWidth>1</bitWidth> |
||
| 14091 | </field> |
||
| 14092 | <field> |
||
| 14093 | <name>CC1IE</name> |
||
| 14094 | <description>Capture/Compare 1 interrupt |
||
| 14095 | enable</description> |
||
| 14096 | <bitOffset>1</bitOffset> |
||
| 14097 | <bitWidth>1</bitWidth> |
||
| 14098 | </field> |
||
| 14099 | <field> |
||
| 14100 | <name>UIE</name> |
||
| 14101 | <description>Update interrupt enable</description> |
||
| 14102 | <bitOffset>0</bitOffset> |
||
| 14103 | <bitWidth>1</bitWidth> |
||
| 14104 | </field> |
||
| 14105 | </fields> |
||
| 14106 | </register> |
||
| 14107 | <register> |
||
| 14108 | <name>SR</name> |
||
| 14109 | <displayName>SR</displayName> |
||
| 14110 | <description>status register</description> |
||
| 14111 | <addressOffset>0x10</addressOffset> |
||
| 14112 | <size>0x20</size> |
||
| 14113 | <access>read-write</access> |
||
| 14114 | <resetValue>0x0000</resetValue> |
||
| 14115 | <fields> |
||
| 14116 | <field> |
||
| 14117 | <name>CC1OF</name> |
||
| 14118 | <description>Capture/Compare 1 overcapture |
||
| 14119 | flag</description> |
||
| 14120 | <bitOffset>9</bitOffset> |
||
| 14121 | <bitWidth>1</bitWidth> |
||
| 14122 | </field> |
||
| 14123 | <field> |
||
| 14124 | <name>BIF</name> |
||
| 14125 | <description>Break interrupt flag</description> |
||
| 14126 | <bitOffset>7</bitOffset> |
||
| 14127 | <bitWidth>1</bitWidth> |
||
| 14128 | </field> |
||
| 14129 | <field> |
||
| 14130 | <name>TIF</name> |
||
| 14131 | <description>Trigger interrupt flag</description> |
||
| 14132 | <bitOffset>6</bitOffset> |
||
| 14133 | <bitWidth>1</bitWidth> |
||
| 14134 | </field> |
||
| 14135 | <field> |
||
| 14136 | <name>COMIF</name> |
||
| 14137 | <description>COM interrupt flag</description> |
||
| 14138 | <bitOffset>5</bitOffset> |
||
| 14139 | <bitWidth>1</bitWidth> |
||
| 14140 | </field> |
||
| 14141 | <field> |
||
| 14142 | <name>CC1IF</name> |
||
| 14143 | <description>Capture/compare 1 interrupt |
||
| 14144 | flag</description> |
||
| 14145 | <bitOffset>1</bitOffset> |
||
| 14146 | <bitWidth>1</bitWidth> |
||
| 14147 | </field> |
||
| 14148 | <field> |
||
| 14149 | <name>UIF</name> |
||
| 14150 | <description>Update interrupt flag</description> |
||
| 14151 | <bitOffset>0</bitOffset> |
||
| 14152 | <bitWidth>1</bitWidth> |
||
| 14153 | </field> |
||
| 14154 | </fields> |
||
| 14155 | </register> |
||
| 14156 | <register> |
||
| 14157 | <name>EGR</name> |
||
| 14158 | <displayName>EGR</displayName> |
||
| 14159 | <description>event generation register</description> |
||
| 14160 | <addressOffset>0x14</addressOffset> |
||
| 14161 | <size>0x20</size> |
||
| 14162 | <access>write-only</access> |
||
| 14163 | <resetValue>0x0000</resetValue> |
||
| 14164 | <fields> |
||
| 14165 | <field> |
||
| 14166 | <name>BG</name> |
||
| 14167 | <description>Break generation</description> |
||
| 14168 | <bitOffset>7</bitOffset> |
||
| 14169 | <bitWidth>1</bitWidth> |
||
| 14170 | </field> |
||
| 14171 | <field> |
||
| 14172 | <name>TG</name> |
||
| 14173 | <description>Trigger generation</description> |
||
| 14174 | <bitOffset>6</bitOffset> |
||
| 14175 | <bitWidth>1</bitWidth> |
||
| 14176 | </field> |
||
| 14177 | <field> |
||
| 14178 | <name>COMG</name> |
||
| 14179 | <description>Capture/Compare control update |
||
| 14180 | generation</description> |
||
| 14181 | <bitOffset>5</bitOffset> |
||
| 14182 | <bitWidth>1</bitWidth> |
||
| 14183 | </field> |
||
| 14184 | <field> |
||
| 14185 | <name>CC1G</name> |
||
| 14186 | <description>Capture/compare 1 |
||
| 14187 | generation</description> |
||
| 14188 | <bitOffset>1</bitOffset> |
||
| 14189 | <bitWidth>1</bitWidth> |
||
| 14190 | </field> |
||
| 14191 | <field> |
||
| 14192 | <name>UG</name> |
||
| 14193 | <description>Update generation</description> |
||
| 14194 | <bitOffset>0</bitOffset> |
||
| 14195 | <bitWidth>1</bitWidth> |
||
| 14196 | </field> |
||
| 14197 | </fields> |
||
| 14198 | </register> |
||
| 14199 | <register> |
||
| 14200 | <name>CCMR1_Output</name> |
||
| 14201 | <displayName>CCMR1_Output</displayName> |
||
| 14202 | <description>capture/compare mode register (output |
||
| 14203 | mode)</description> |
||
| 14204 | <addressOffset>0x18</addressOffset> |
||
| 14205 | <size>0x20</size> |
||
| 14206 | <access>read-write</access> |
||
| 14207 | <resetValue>0x00000000</resetValue> |
||
| 14208 | <fields> |
||
| 14209 | <field> |
||
| 14210 | <name>OC1M</name> |
||
| 14211 | <description>Output Compare 1 mode</description> |
||
| 14212 | <bitOffset>4</bitOffset> |
||
| 14213 | <bitWidth>3</bitWidth> |
||
| 14214 | </field> |
||
| 14215 | <field> |
||
| 14216 | <name>OC1PE</name> |
||
| 14217 | <description>Output Compare 1 preload |
||
| 14218 | enable</description> |
||
| 14219 | <bitOffset>3</bitOffset> |
||
| 14220 | <bitWidth>1</bitWidth> |
||
| 14221 | </field> |
||
| 14222 | <field> |
||
| 14223 | <name>OC1FE</name> |
||
| 14224 | <description>Output Compare 1 fast |
||
| 14225 | enable</description> |
||
| 14226 | <bitOffset>2</bitOffset> |
||
| 14227 | <bitWidth>1</bitWidth> |
||
| 14228 | </field> |
||
| 14229 | <field> |
||
| 14230 | <name>CC1S</name> |
||
| 14231 | <description>Capture/Compare 1 |
||
| 14232 | selection</description> |
||
| 14233 | <bitOffset>0</bitOffset> |
||
| 14234 | <bitWidth>2</bitWidth> |
||
| 14235 | </field> |
||
| 14236 | </fields> |
||
| 14237 | </register> |
||
| 14238 | <register> |
||
| 14239 | <name>CCMR1_Input</name> |
||
| 14240 | <displayName>CCMR1_Input</displayName> |
||
| 14241 | <description>capture/compare mode register 1 (input |
||
| 14242 | mode)</description> |
||
| 14243 | <alternateRegister>CCMR1_Output</alternateRegister> |
||
| 14244 | <addressOffset>0x18</addressOffset> |
||
| 14245 | <size>0x20</size> |
||
| 14246 | <access>read-write</access> |
||
| 14247 | <resetValue>0x00000000</resetValue> |
||
| 14248 | <fields> |
||
| 14249 | <field> |
||
| 14250 | <name>IC1F</name> |
||
| 14251 | <description>Input capture 1 filter</description> |
||
| 14252 | <bitOffset>4</bitOffset> |
||
| 14253 | <bitWidth>4</bitWidth> |
||
| 14254 | </field> |
||
| 14255 | <field> |
||
| 14256 | <name>IC1PSC</name> |
||
| 14257 | <description>Input capture 1 prescaler</description> |
||
| 14258 | <bitOffset>2</bitOffset> |
||
| 14259 | <bitWidth>2</bitWidth> |
||
| 14260 | </field> |
||
| 14261 | <field> |
||
| 14262 | <name>CC1S</name> |
||
| 14263 | <description>Capture/Compare 1 |
||
| 14264 | selection</description> |
||
| 14265 | <bitOffset>0</bitOffset> |
||
| 14266 | <bitWidth>2</bitWidth> |
||
| 14267 | </field> |
||
| 14268 | </fields> |
||
| 14269 | </register> |
||
| 14270 | <register> |
||
| 14271 | <name>CCER</name> |
||
| 14272 | <displayName>CCER</displayName> |
||
| 14273 | <description>capture/compare enable |
||
| 14274 | register</description> |
||
| 14275 | <addressOffset>0x20</addressOffset> |
||
| 14276 | <size>0x20</size> |
||
| 14277 | <access>read-write</access> |
||
| 14278 | <resetValue>0x0000</resetValue> |
||
| 14279 | <fields> |
||
| 14280 | <field> |
||
| 14281 | <name>CC1NP</name> |
||
| 14282 | <description>Capture/Compare 1 output |
||
| 14283 | Polarity</description> |
||
| 14284 | <bitOffset>3</bitOffset> |
||
| 14285 | <bitWidth>1</bitWidth> |
||
| 14286 | </field> |
||
| 14287 | <field> |
||
| 14288 | <name>CC1NE</name> |
||
| 14289 | <description>Capture/Compare 1 complementary output |
||
| 14290 | enable</description> |
||
| 14291 | <bitOffset>2</bitOffset> |
||
| 14292 | <bitWidth>1</bitWidth> |
||
| 14293 | </field> |
||
| 14294 | <field> |
||
| 14295 | <name>CC1P</name> |
||
| 14296 | <description>Capture/Compare 1 output |
||
| 14297 | Polarity</description> |
||
| 14298 | <bitOffset>1</bitOffset> |
||
| 14299 | <bitWidth>1</bitWidth> |
||
| 14300 | </field> |
||
| 14301 | <field> |
||
| 14302 | <name>CC1E</name> |
||
| 14303 | <description>Capture/Compare 1 output |
||
| 14304 | enable</description> |
||
| 14305 | <bitOffset>0</bitOffset> |
||
| 14306 | <bitWidth>1</bitWidth> |
||
| 14307 | </field> |
||
| 14308 | </fields> |
||
| 14309 | </register> |
||
| 14310 | <register> |
||
| 14311 | <name>CNT</name> |
||
| 14312 | <displayName>CNT</displayName> |
||
| 14313 | <description>counter</description> |
||
| 14314 | <addressOffset>0x24</addressOffset> |
||
| 14315 | <size>0x20</size> |
||
| 14316 | <access>read-write</access> |
||
| 14317 | <resetValue>0x00000000</resetValue> |
||
| 14318 | <fields> |
||
| 14319 | <field> |
||
| 14320 | <name>CNT</name> |
||
| 14321 | <description>counter value</description> |
||
| 14322 | <bitOffset>0</bitOffset> |
||
| 14323 | <bitWidth>16</bitWidth> |
||
| 14324 | </field> |
||
| 14325 | </fields> |
||
| 14326 | </register> |
||
| 14327 | <register> |
||
| 14328 | <name>PSC</name> |
||
| 14329 | <displayName>PSC</displayName> |
||
| 14330 | <description>prescaler</description> |
||
| 14331 | <addressOffset>0x28</addressOffset> |
||
| 14332 | <size>0x20</size> |
||
| 14333 | <access>read-write</access> |
||
| 14334 | <resetValue>0x0000</resetValue> |
||
| 14335 | <fields> |
||
| 14336 | <field> |
||
| 14337 | <name>PSC</name> |
||
| 14338 | <description>Prescaler value</description> |
||
| 14339 | <bitOffset>0</bitOffset> |
||
| 14340 | <bitWidth>16</bitWidth> |
||
| 14341 | </field> |
||
| 14342 | </fields> |
||
| 14343 | </register> |
||
| 14344 | <register> |
||
| 14345 | <name>ARR</name> |
||
| 14346 | <displayName>ARR</displayName> |
||
| 14347 | <description>auto-reload register</description> |
||
| 14348 | <addressOffset>0x2C</addressOffset> |
||
| 14349 | <size>0x20</size> |
||
| 14350 | <access>read-write</access> |
||
| 14351 | <resetValue>0x00000000</resetValue> |
||
| 14352 | <fields> |
||
| 14353 | <field> |
||
| 14354 | <name>ARR</name> |
||
| 14355 | <description>Auto-reload value</description> |
||
| 14356 | <bitOffset>0</bitOffset> |
||
| 14357 | <bitWidth>16</bitWidth> |
||
| 14358 | </field> |
||
| 14359 | </fields> |
||
| 14360 | </register> |
||
| 14361 | <register> |
||
| 14362 | <name>RCR</name> |
||
| 14363 | <displayName>RCR</displayName> |
||
| 14364 | <description>repetition counter register</description> |
||
| 14365 | <addressOffset>0x30</addressOffset> |
||
| 14366 | <size>0x20</size> |
||
| 14367 | <access>read-write</access> |
||
| 14368 | <resetValue>0x0000</resetValue> |
||
| 14369 | <fields> |
||
| 14370 | <field> |
||
| 14371 | <name>REP</name> |
||
| 14372 | <description>Repetition counter value</description> |
||
| 14373 | <bitOffset>0</bitOffset> |
||
| 14374 | <bitWidth>8</bitWidth> |
||
| 14375 | </field> |
||
| 14376 | </fields> |
||
| 14377 | </register> |
||
| 14378 | <register> |
||
| 14379 | <name>CCR1</name> |
||
| 14380 | <displayName>CCR1</displayName> |
||
| 14381 | <description>capture/compare register 1</description> |
||
| 14382 | <addressOffset>0x34</addressOffset> |
||
| 14383 | <size>0x20</size> |
||
| 14384 | <access>read-write</access> |
||
| 14385 | <resetValue>0x00000000</resetValue> |
||
| 14386 | <fields> |
||
| 14387 | <field> |
||
| 14388 | <name>CCR1</name> |
||
| 14389 | <description>Capture/Compare 1 value</description> |
||
| 14390 | <bitOffset>0</bitOffset> |
||
| 14391 | <bitWidth>16</bitWidth> |
||
| 14392 | </field> |
||
| 14393 | </fields> |
||
| 14394 | </register> |
||
| 14395 | <register> |
||
| 14396 | <name>BDTR</name> |
||
| 14397 | <displayName>BDTR</displayName> |
||
| 14398 | <description>break and dead-time register</description> |
||
| 14399 | <addressOffset>0x44</addressOffset> |
||
| 14400 | <size>0x20</size> |
||
| 14401 | <access>read-write</access> |
||
| 14402 | <resetValue>0x0000</resetValue> |
||
| 14403 | <fields> |
||
| 14404 | <field> |
||
| 14405 | <name>MOE</name> |
||
| 14406 | <description>Main output enable</description> |
||
| 14407 | <bitOffset>15</bitOffset> |
||
| 14408 | <bitWidth>1</bitWidth> |
||
| 14409 | </field> |
||
| 14410 | <field> |
||
| 14411 | <name>AOE</name> |
||
| 14412 | <description>Automatic output enable</description> |
||
| 14413 | <bitOffset>14</bitOffset> |
||
| 14414 | <bitWidth>1</bitWidth> |
||
| 14415 | </field> |
||
| 14416 | <field> |
||
| 14417 | <name>BKP</name> |
||
| 14418 | <description>Break polarity</description> |
||
| 14419 | <bitOffset>13</bitOffset> |
||
| 14420 | <bitWidth>1</bitWidth> |
||
| 14421 | </field> |
||
| 14422 | <field> |
||
| 14423 | <name>BKE</name> |
||
| 14424 | <description>Break enable</description> |
||
| 14425 | <bitOffset>12</bitOffset> |
||
| 14426 | <bitWidth>1</bitWidth> |
||
| 14427 | </field> |
||
| 14428 | <field> |
||
| 14429 | <name>OSSR</name> |
||
| 14430 | <description>Off-state selection for Run |
||
| 14431 | mode</description> |
||
| 14432 | <bitOffset>11</bitOffset> |
||
| 14433 | <bitWidth>1</bitWidth> |
||
| 14434 | </field> |
||
| 14435 | <field> |
||
| 14436 | <name>OSSI</name> |
||
| 14437 | <description>Off-state selection for Idle |
||
| 14438 | mode</description> |
||
| 14439 | <bitOffset>10</bitOffset> |
||
| 14440 | <bitWidth>1</bitWidth> |
||
| 14441 | </field> |
||
| 14442 | <field> |
||
| 14443 | <name>LOCK</name> |
||
| 14444 | <description>Lock configuration</description> |
||
| 14445 | <bitOffset>8</bitOffset> |
||
| 14446 | <bitWidth>2</bitWidth> |
||
| 14447 | </field> |
||
| 14448 | <field> |
||
| 14449 | <name>DTG</name> |
||
| 14450 | <description>Dead-time generator setup</description> |
||
| 14451 | <bitOffset>0</bitOffset> |
||
| 14452 | <bitWidth>8</bitWidth> |
||
| 14453 | </field> |
||
| 14454 | </fields> |
||
| 14455 | </register> |
||
| 14456 | <register> |
||
| 14457 | <name>DCR</name> |
||
| 14458 | <displayName>DCR</displayName> |
||
| 14459 | <description>DMA control register</description> |
||
| 14460 | <addressOffset>0x48</addressOffset> |
||
| 14461 | <size>0x20</size> |
||
| 14462 | <access>read-write</access> |
||
| 14463 | <resetValue>0x0000</resetValue> |
||
| 14464 | <fields> |
||
| 14465 | <field> |
||
| 14466 | <name>DBL</name> |
||
| 14467 | <description>DMA burst length</description> |
||
| 14468 | <bitOffset>8</bitOffset> |
||
| 14469 | <bitWidth>5</bitWidth> |
||
| 14470 | </field> |
||
| 14471 | <field> |
||
| 14472 | <name>DBA</name> |
||
| 14473 | <description>DMA base address</description> |
||
| 14474 | <bitOffset>0</bitOffset> |
||
| 14475 | <bitWidth>5</bitWidth> |
||
| 14476 | </field> |
||
| 14477 | </fields> |
||
| 14478 | </register> |
||
| 14479 | <register> |
||
| 14480 | <name>DMAR</name> |
||
| 14481 | <displayName>DMAR</displayName> |
||
| 14482 | <description>DMA address for full transfer</description> |
||
| 14483 | <addressOffset>0x4C</addressOffset> |
||
| 14484 | <size>0x20</size> |
||
| 14485 | <access>read-write</access> |
||
| 14486 | <resetValue>0x0000</resetValue> |
||
| 14487 | <fields> |
||
| 14488 | <field> |
||
| 14489 | <name>DMAB</name> |
||
| 14490 | <description>DMA register for burst |
||
| 14491 | accesses</description> |
||
| 14492 | <bitOffset>0</bitOffset> |
||
| 14493 | <bitWidth>16</bitWidth> |
||
| 14494 | </field> |
||
| 14495 | </fields> |
||
| 14496 | </register> |
||
| 14497 | </registers> |
||
| 14498 | </peripheral> |
||
| 14499 | <peripheral derivedFrom="TIM16"> |
||
| 14500 | <name>TIM17</name> |
||
| 14501 | <baseAddress>0x40014800</baseAddress> |
||
| 14502 | <interrupt> |
||
| 14503 | <name>USART3_4</name> |
||
| 14504 | <description>USART3 and USART4 global |
||
| 14505 | interrupt</description> |
||
| 14506 | <value>29</value> |
||
| 14507 | </interrupt> |
||
| 14508 | </peripheral> |
||
| 14509 | <peripheral> |
||
| 14510 | <name>Flash</name> |
||
| 14511 | <description>Flash</description> |
||
| 14512 | <groupName>Flash</groupName> |
||
| 14513 | <baseAddress>0x40022000</baseAddress> |
||
| 14514 | <addressBlock> |
||
| 14515 | <offset>0x0</offset> |
||
| 14516 | <size>0x400</size> |
||
| 14517 | <usage>registers</usage> |
||
| 14518 | </addressBlock> |
||
| 14519 | <interrupt> |
||
| 14520 | <name>USART3_4</name> |
||
| 14521 | <description>USART3 and USART4 global |
||
| 14522 | interrupt</description> |
||
| 14523 | <value>29</value> |
||
| 14524 | </interrupt> |
||
| 14525 | <registers> |
||
| 14526 | <register> |
||
| 14527 | <name>ACR</name> |
||
| 14528 | <displayName>ACR</displayName> |
||
| 14529 | <description>Flash access control register</description> |
||
| 14530 | <addressOffset>0x0</addressOffset> |
||
| 14531 | <size>0x20</size> |
||
| 14532 | <resetValue>0x00000030</resetValue> |
||
| 14533 | <fields> |
||
| 14534 | <field> |
||
| 14535 | <name>LATENCY</name> |
||
| 14536 | <description>LATENCY</description> |
||
| 14537 | <bitOffset>0</bitOffset> |
||
| 14538 | <bitWidth>3</bitWidth> |
||
| 14539 | <access>read-write</access> |
||
| 14540 | </field> |
||
| 14541 | <field> |
||
| 14542 | <name>PRFTBE</name> |
||
| 14543 | <description>PRFTBE</description> |
||
| 14544 | <bitOffset>4</bitOffset> |
||
| 14545 | <bitWidth>1</bitWidth> |
||
| 14546 | <access>read-write</access> |
||
| 14547 | </field> |
||
| 14548 | <field> |
||
| 14549 | <name>PRFTBS</name> |
||
| 14550 | <description>PRFTBS</description> |
||
| 14551 | <bitOffset>5</bitOffset> |
||
| 14552 | <bitWidth>1</bitWidth> |
||
| 14553 | <access>read-only</access> |
||
| 14554 | </field> |
||
| 14555 | </fields> |
||
| 14556 | </register> |
||
| 14557 | <register> |
||
| 14558 | <name>KEYR</name> |
||
| 14559 | <displayName>KEYR</displayName> |
||
| 14560 | <description>Flash key register</description> |
||
| 14561 | <addressOffset>0x4</addressOffset> |
||
| 14562 | <size>0x20</size> |
||
| 14563 | <access>write-only</access> |
||
| 14564 | <resetValue>0x00000000</resetValue> |
||
| 14565 | <fields> |
||
| 14566 | <field> |
||
| 14567 | <name>FKEYR</name> |
||
| 14568 | <description>Flash Key</description> |
||
| 14569 | <bitOffset>0</bitOffset> |
||
| 14570 | <bitWidth>32</bitWidth> |
||
| 14571 | </field> |
||
| 14572 | </fields> |
||
| 14573 | </register> |
||
| 14574 | <register> |
||
| 14575 | <name>OPTKEYR</name> |
||
| 14576 | <displayName>OPTKEYR</displayName> |
||
| 14577 | <description>Flash option key register</description> |
||
| 14578 | <addressOffset>0x8</addressOffset> |
||
| 14579 | <size>0x20</size> |
||
| 14580 | <access>write-only</access> |
||
| 14581 | <resetValue>0x00000000</resetValue> |
||
| 14582 | <fields> |
||
| 14583 | <field> |
||
| 14584 | <name>OPTKEYR</name> |
||
| 14585 | <description>Option byte key</description> |
||
| 14586 | <bitOffset>0</bitOffset> |
||
| 14587 | <bitWidth>32</bitWidth> |
||
| 14588 | </field> |
||
| 14589 | </fields> |
||
| 14590 | </register> |
||
| 14591 | <register> |
||
| 14592 | <name>SR</name> |
||
| 14593 | <displayName>SR</displayName> |
||
| 14594 | <description>Flash status register</description> |
||
| 14595 | <addressOffset>0xC</addressOffset> |
||
| 14596 | <size>0x20</size> |
||
| 14597 | <resetValue>0x00000000</resetValue> |
||
| 14598 | <fields> |
||
| 14599 | <field> |
||
| 14600 | <name>EOP</name> |
||
| 14601 | <description>End of operation</description> |
||
| 14602 | <bitOffset>5</bitOffset> |
||
| 14603 | <bitWidth>1</bitWidth> |
||
| 14604 | <access>read-write</access> |
||
| 14605 | </field> |
||
| 14606 | <field> |
||
| 14607 | <name>WRPRT</name> |
||
| 14608 | <description>Write protection error</description> |
||
| 14609 | <bitOffset>4</bitOffset> |
||
| 14610 | <bitWidth>1</bitWidth> |
||
| 14611 | <access>read-write</access> |
||
| 14612 | </field> |
||
| 14613 | <field> |
||
| 14614 | <name>PGERR</name> |
||
| 14615 | <description>Programming error</description> |
||
| 14616 | <bitOffset>2</bitOffset> |
||
| 14617 | <bitWidth>1</bitWidth> |
||
| 14618 | <access>read-write</access> |
||
| 14619 | </field> |
||
| 14620 | <field> |
||
| 14621 | <name>BSY</name> |
||
| 14622 | <description>Busy</description> |
||
| 14623 | <bitOffset>0</bitOffset> |
||
| 14624 | <bitWidth>1</bitWidth> |
||
| 14625 | <access>read-only</access> |
||
| 14626 | </field> |
||
| 14627 | </fields> |
||
| 14628 | </register> |
||
| 14629 | <register> |
||
| 14630 | <name>CR</name> |
||
| 14631 | <displayName>CR</displayName> |
||
| 14632 | <description>Flash control register</description> |
||
| 14633 | <addressOffset>0x10</addressOffset> |
||
| 14634 | <size>0x20</size> |
||
| 14635 | <access>read-write</access> |
||
| 14636 | <resetValue>0x00000080</resetValue> |
||
| 14637 | <fields> |
||
| 14638 | <field> |
||
| 14639 | <name>FORCE_OPTLOAD</name> |
||
| 14640 | <description>Force option byte loading</description> |
||
| 14641 | <bitOffset>13</bitOffset> |
||
| 14642 | <bitWidth>1</bitWidth> |
||
| 14643 | </field> |
||
| 14644 | <field> |
||
| 14645 | <name>EOPIE</name> |
||
| 14646 | <description>End of operation interrupt |
||
| 14647 | enable</description> |
||
| 14648 | <bitOffset>12</bitOffset> |
||
| 14649 | <bitWidth>1</bitWidth> |
||
| 14650 | </field> |
||
| 14651 | <field> |
||
| 14652 | <name>ERRIE</name> |
||
| 14653 | <description>Error interrupt enable</description> |
||
| 14654 | <bitOffset>10</bitOffset> |
||
| 14655 | <bitWidth>1</bitWidth> |
||
| 14656 | </field> |
||
| 14657 | <field> |
||
| 14658 | <name>OPTWRE</name> |
||
| 14659 | <description>Option bytes write enable</description> |
||
| 14660 | <bitOffset>9</bitOffset> |
||
| 14661 | <bitWidth>1</bitWidth> |
||
| 14662 | </field> |
||
| 14663 | <field> |
||
| 14664 | <name>LOCK</name> |
||
| 14665 | <description>Lock</description> |
||
| 14666 | <bitOffset>7</bitOffset> |
||
| 14667 | <bitWidth>1</bitWidth> |
||
| 14668 | </field> |
||
| 14669 | <field> |
||
| 14670 | <name>STRT</name> |
||
| 14671 | <description>Start</description> |
||
| 14672 | <bitOffset>6</bitOffset> |
||
| 14673 | <bitWidth>1</bitWidth> |
||
| 14674 | </field> |
||
| 14675 | <field> |
||
| 14676 | <name>OPTER</name> |
||
| 14677 | <description>Option byte erase</description> |
||
| 14678 | <bitOffset>5</bitOffset> |
||
| 14679 | <bitWidth>1</bitWidth> |
||
| 14680 | </field> |
||
| 14681 | <field> |
||
| 14682 | <name>OPTPG</name> |
||
| 14683 | <description>Option byte programming</description> |
||
| 14684 | <bitOffset>4</bitOffset> |
||
| 14685 | <bitWidth>1</bitWidth> |
||
| 14686 | </field> |
||
| 14687 | <field> |
||
| 14688 | <name>MER</name> |
||
| 14689 | <description>Mass erase</description> |
||
| 14690 | <bitOffset>2</bitOffset> |
||
| 14691 | <bitWidth>1</bitWidth> |
||
| 14692 | </field> |
||
| 14693 | <field> |
||
| 14694 | <name>PER</name> |
||
| 14695 | <description>Page erase</description> |
||
| 14696 | <bitOffset>1</bitOffset> |
||
| 14697 | <bitWidth>1</bitWidth> |
||
| 14698 | </field> |
||
| 14699 | <field> |
||
| 14700 | <name>PG</name> |
||
| 14701 | <description>Programming</description> |
||
| 14702 | <bitOffset>0</bitOffset> |
||
| 14703 | <bitWidth>1</bitWidth> |
||
| 14704 | </field> |
||
| 14705 | </fields> |
||
| 14706 | </register> |
||
| 14707 | <register> |
||
| 14708 | <name>AR</name> |
||
| 14709 | <displayName>AR</displayName> |
||
| 14710 | <description>Flash address register</description> |
||
| 14711 | <addressOffset>0x14</addressOffset> |
||
| 14712 | <size>0x20</size> |
||
| 14713 | <access>write-only</access> |
||
| 14714 | <resetValue>0x00000000</resetValue> |
||
| 14715 | <fields> |
||
| 14716 | <field> |
||
| 14717 | <name>FAR</name> |
||
| 14718 | <description>Flash address</description> |
||
| 14719 | <bitOffset>0</bitOffset> |
||
| 14720 | <bitWidth>32</bitWidth> |
||
| 14721 | </field> |
||
| 14722 | </fields> |
||
| 14723 | </register> |
||
| 14724 | <register> |
||
| 14725 | <name>OBR</name> |
||
| 14726 | <displayName>OBR</displayName> |
||
| 14727 | <description>Option byte register</description> |
||
| 14728 | <addressOffset>0x1C</addressOffset> |
||
| 14729 | <size>0x20</size> |
||
| 14730 | <access>read-only</access> |
||
| 14731 | <resetValue>0x03FFFFF2</resetValue> |
||
| 14732 | <fields> |
||
| 14733 | <field> |
||
| 14734 | <name>Data1</name> |
||
| 14735 | <description>Data1</description> |
||
| 14736 | <bitOffset>24</bitOffset> |
||
| 14737 | <bitWidth>8</bitWidth> |
||
| 14738 | </field> |
||
| 14739 | <field> |
||
| 14740 | <name>Data0</name> |
||
| 14741 | <description>Data0</description> |
||
| 14742 | <bitOffset>16</bitOffset> |
||
| 14743 | <bitWidth>8</bitWidth> |
||
| 14744 | </field> |
||
| 14745 | <field> |
||
| 14746 | <name>VDDA_MONITOR</name> |
||
| 14747 | <description>VDDA_MONITOR</description> |
||
| 14748 | <bitOffset>13</bitOffset> |
||
| 14749 | <bitWidth>1</bitWidth> |
||
| 14750 | </field> |
||
| 14751 | <field> |
||
| 14752 | <name>BOOT1</name> |
||
| 14753 | <description>BOOT1</description> |
||
| 14754 | <bitOffset>12</bitOffset> |
||
| 14755 | <bitWidth>1</bitWidth> |
||
| 14756 | </field> |
||
| 14757 | <field> |
||
| 14758 | <name>nRST_STDBY</name> |
||
| 14759 | <description>nRST_STDBY</description> |
||
| 14760 | <bitOffset>10</bitOffset> |
||
| 14761 | <bitWidth>1</bitWidth> |
||
| 14762 | </field> |
||
| 14763 | <field> |
||
| 14764 | <name>nRST_STOP</name> |
||
| 14765 | <description>nRST_STOP</description> |
||
| 14766 | <bitOffset>9</bitOffset> |
||
| 14767 | <bitWidth>1</bitWidth> |
||
| 14768 | </field> |
||
| 14769 | <field> |
||
| 14770 | <name>WDG_SW</name> |
||
| 14771 | <description>WDG_SW</description> |
||
| 14772 | <bitOffset>8</bitOffset> |
||
| 14773 | <bitWidth>1</bitWidth> |
||
| 14774 | </field> |
||
| 14775 | <field> |
||
| 14776 | <name>LEVEL2_PROT</name> |
||
| 14777 | <description>Level 2 protection status</description> |
||
| 14778 | <bitOffset>2</bitOffset> |
||
| 14779 | <bitWidth>1</bitWidth> |
||
| 14780 | </field> |
||
| 14781 | <field> |
||
| 14782 | <name>LEVEL1_PROT</name> |
||
| 14783 | <description>Level 1 protection status</description> |
||
| 14784 | <bitOffset>1</bitOffset> |
||
| 14785 | <bitWidth>1</bitWidth> |
||
| 14786 | </field> |
||
| 14787 | <field> |
||
| 14788 | <name>OPTERR</name> |
||
| 14789 | <description>Option byte error</description> |
||
| 14790 | <bitOffset>0</bitOffset> |
||
| 14791 | <bitWidth>1</bitWidth> |
||
| 14792 | </field> |
||
| 14793 | </fields> |
||
| 14794 | </register> |
||
| 14795 | <register> |
||
| 14796 | <name>WRPR</name> |
||
| 14797 | <displayName>WRPR</displayName> |
||
| 14798 | <description>Write protection register</description> |
||
| 14799 | <addressOffset>0x20</addressOffset> |
||
| 14800 | <size>0x20</size> |
||
| 14801 | <access>read-only</access> |
||
| 14802 | <resetValue>0xFFFFFFFF</resetValue> |
||
| 14803 | <fields> |
||
| 14804 | <field> |
||
| 14805 | <name>WRP</name> |
||
| 14806 | <description>Write protect</description> |
||
| 14807 | <bitOffset>0</bitOffset> |
||
| 14808 | <bitWidth>32</bitWidth> |
||
| 14809 | </field> |
||
| 14810 | </fields> |
||
| 14811 | </register> |
||
| 14812 | </registers> |
||
| 14813 | </peripheral> |
||
| 14814 | <peripheral> |
||
| 14815 | <name>DBGMCU</name> |
||
| 14816 | <description>Debug support</description> |
||
| 14817 | <groupName>DBGMCU</groupName> |
||
| 14818 | <baseAddress>0x40015800</baseAddress> |
||
| 14819 | <addressBlock> |
||
| 14820 | <offset>0x0</offset> |
||
| 14821 | <size>0x400</size> |
||
| 14822 | <usage>registers</usage> |
||
| 14823 | </addressBlock> |
||
| 14824 | <interrupt> |
||
| 14825 | <name>ADC_COMP</name> |
||
| 14826 | <description>ADC and comparator interrupts</description> |
||
| 14827 | <value>12</value> |
||
| 14828 | </interrupt> |
||
| 14829 | <registers> |
||
| 14830 | <register> |
||
| 14831 | <name>IDCODE</name> |
||
| 14832 | <displayName>IDCODE</displayName> |
||
| 14833 | <description>MCU Device ID Code Register</description> |
||
| 14834 | <addressOffset>0x0</addressOffset> |
||
| 14835 | <size>0x20</size> |
||
| 14836 | <access>read-only</access> |
||
| 14837 | <resetValue>0x0</resetValue> |
||
| 14838 | <fields> |
||
| 14839 | <field> |
||
| 14840 | <name>DEV_ID</name> |
||
| 14841 | <description>Device Identifier</description> |
||
| 14842 | <bitOffset>0</bitOffset> |
||
| 14843 | <bitWidth>12</bitWidth> |
||
| 14844 | </field> |
||
| 14845 | <field> |
||
| 14846 | <name>DIV_ID</name> |
||
| 14847 | <description>Division Identifier</description> |
||
| 14848 | <bitOffset>12</bitOffset> |
||
| 14849 | <bitWidth>4</bitWidth> |
||
| 14850 | </field> |
||
| 14851 | <field> |
||
| 14852 | <name>REV_ID</name> |
||
| 14853 | <description>Revision Identifier</description> |
||
| 14854 | <bitOffset>16</bitOffset> |
||
| 14855 | <bitWidth>16</bitWidth> |
||
| 14856 | </field> |
||
| 14857 | </fields> |
||
| 14858 | </register> |
||
| 14859 | <register> |
||
| 14860 | <name>CR</name> |
||
| 14861 | <displayName>CR</displayName> |
||
| 14862 | <description>Debug MCU Configuration |
||
| 14863 | Register</description> |
||
| 14864 | <addressOffset>0x4</addressOffset> |
||
| 14865 | <size>0x20</size> |
||
| 14866 | <access>read-write</access> |
||
| 14867 | <resetValue>0x0</resetValue> |
||
| 14868 | <fields> |
||
| 14869 | <field> |
||
| 14870 | <name>DBG_STOP</name> |
||
| 14871 | <description>Debug Stop Mode</description> |
||
| 14872 | <bitOffset>1</bitOffset> |
||
| 14873 | <bitWidth>1</bitWidth> |
||
| 14874 | </field> |
||
| 14875 | <field> |
||
| 14876 | <name>DBG_STANDBY</name> |
||
| 14877 | <description>Debug Standby Mode</description> |
||
| 14878 | <bitOffset>2</bitOffset> |
||
| 14879 | <bitWidth>1</bitWidth> |
||
| 14880 | </field> |
||
| 14881 | </fields> |
||
| 14882 | </register> |
||
| 14883 | <register> |
||
| 14884 | <name>APBLFZ</name> |
||
| 14885 | <displayName>APBLFZ</displayName> |
||
| 14886 | <description>APB Low Freeze Register</description> |
||
| 14887 | <addressOffset>0x8</addressOffset> |
||
| 14888 | <size>0x20</size> |
||
| 14889 | <access>read-write</access> |
||
| 14890 | <resetValue>0x0</resetValue> |
||
| 14891 | <fields> |
||
| 14892 | <field> |
||
| 14893 | <name>DBG_TIMER2_STOP</name> |
||
| 14894 | <description>Debug Timer 2 stopped when Core is |
||
| 14895 | halted</description> |
||
| 14896 | <bitOffset>0</bitOffset> |
||
| 14897 | <bitWidth>1</bitWidth> |
||
| 14898 | </field> |
||
| 14899 | <field> |
||
| 14900 | <name>DBG_TIMER3_STOP</name> |
||
| 14901 | <description>Debug Timer 3 stopped when Core is |
||
| 14902 | halted</description> |
||
| 14903 | <bitOffset>1</bitOffset> |
||
| 14904 | <bitWidth>1</bitWidth> |
||
| 14905 | </field> |
||
| 14906 | <field> |
||
| 14907 | <name>DBG_TIMER6_STOP</name> |
||
| 14908 | <description>Debug Timer 6 stopped when Core is |
||
| 14909 | halted</description> |
||
| 14910 | <bitOffset>4</bitOffset> |
||
| 14911 | <bitWidth>1</bitWidth> |
||
| 14912 | </field> |
||
| 14913 | <field> |
||
| 14914 | <name>DBG_TIMER14_STOP</name> |
||
| 14915 | <description>Debug Timer 14 stopped when Core is |
||
| 14916 | halted</description> |
||
| 14917 | <bitOffset>8</bitOffset> |
||
| 14918 | <bitWidth>1</bitWidth> |
||
| 14919 | </field> |
||
| 14920 | <field> |
||
| 14921 | <name>DBG_RTC_STOP</name> |
||
| 14922 | <description>Debug RTC stopped when Core is |
||
| 14923 | halted</description> |
||
| 14924 | <bitOffset>10</bitOffset> |
||
| 14925 | <bitWidth>1</bitWidth> |
||
| 14926 | </field> |
||
| 14927 | <field> |
||
| 14928 | <name>DBG_WWDG_STOP</name> |
||
| 14929 | <description>Debug Window Wachdog stopped when Core |
||
| 14930 | is halted</description> |
||
| 14931 | <bitOffset>11</bitOffset> |
||
| 14932 | <bitWidth>1</bitWidth> |
||
| 14933 | </field> |
||
| 14934 | <field> |
||
| 14935 | <name>DBG_IWDG_STOP</name> |
||
| 14936 | <description>Debug Independent Wachdog stopped when |
||
| 14937 | Core is halted</description> |
||
| 14938 | <bitOffset>12</bitOffset> |
||
| 14939 | <bitWidth>1</bitWidth> |
||
| 14940 | </field> |
||
| 14941 | <field> |
||
| 14942 | <name>I2C1_SMBUS_TIMEOUT</name> |
||
| 14943 | <description>SMBUS timeout mode stopped when Core is |
||
| 14944 | halted</description> |
||
| 14945 | <bitOffset>21</bitOffset> |
||
| 14946 | <bitWidth>1</bitWidth> |
||
| 14947 | </field> |
||
| 14948 | </fields> |
||
| 14949 | </register> |
||
| 14950 | <register> |
||
| 14951 | <name>APBHFZ</name> |
||
| 14952 | <displayName>APBHFZ</displayName> |
||
| 14953 | <description>APB High Freeze Register</description> |
||
| 14954 | <addressOffset>0xC</addressOffset> |
||
| 14955 | <size>0x20</size> |
||
| 14956 | <access>read-write</access> |
||
| 14957 | <resetValue>0x0</resetValue> |
||
| 14958 | <fields> |
||
| 14959 | <field> |
||
| 14960 | <name>DBG_TIMER1_STOP</name> |
||
| 14961 | <description>Debug Timer 1 stopped when Core is |
||
| 14962 | halted</description> |
||
| 14963 | <bitOffset>11</bitOffset> |
||
| 14964 | <bitWidth>1</bitWidth> |
||
| 14965 | </field> |
||
| 14966 | <field> |
||
| 14967 | <name>DBG_TIMER15_STO</name> |
||
| 14968 | <description>Debug Timer 15 stopped when Core is |
||
| 14969 | halted</description> |
||
| 14970 | <bitOffset>16</bitOffset> |
||
| 14971 | <bitWidth>1</bitWidth> |
||
| 14972 | </field> |
||
| 14973 | <field> |
||
| 14974 | <name>DBG_TIMER16_STO</name> |
||
| 14975 | <description>Debug Timer 16 stopped when Core is |
||
| 14976 | halted</description> |
||
| 14977 | <bitOffset>17</bitOffset> |
||
| 14978 | <bitWidth>1</bitWidth> |
||
| 14979 | </field> |
||
| 14980 | <field> |
||
| 14981 | <name>DBG_TIMER17_STO</name> |
||
| 14982 | <description>Debug Timer 17 stopped when Core is |
||
| 14983 | halted</description> |
||
| 14984 | <bitOffset>18</bitOffset> |
||
| 14985 | <bitWidth>1</bitWidth> |
||
| 14986 | </field> |
||
| 14987 | </fields> |
||
| 14988 | </register> |
||
| 14989 | </registers> |
||
| 14990 | </peripheral> |
||
| 14991 | </peripherals> |
||
| 14992 | </device> |