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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /* |
| 2 | * hardware.c |
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| 3 | * |
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| 4 | * Created on: 19 Aug 2017 |
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| 5 | * Author: Mike |
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| 6 | */ |
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| 7 | #include "ch.h" |
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| 8 | #include "hal.h" |
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| 9 | #include "hardware.h" |
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| 10 | |||
| 3 | mjames | 11 | uint16_t timerSamples[timerSampleSize]; |
| 12 | |||
| 13 | uint8_t timerInIndex; |
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| 14 | uint8_t timerOutIndex; |
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| 15 | |||
| 16 | |||
| 17 | |||
| 2 | mjames | 18 | void TIM1_UP_IRQHandler(void) { |
| 19 | // we have an interrupt here . |
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| 3 | mjames | 20 | if (TIM1->SR & TIM_SR_CC1IF) { |
| 21 | TIM1->SR &= ~TIM_SR_CC1IF; |
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| 22 | timerSamples[timerInIndex++] = TIM1->CCMR1; |
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| 23 | if (timerInIndex == timerSampleSize) { |
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| 24 | timerInIndex = 0; |
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| 25 | } |
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| 2 | mjames | 26 | |
| 3 | mjames | 27 | } |
| 2 | mjames | 28 | |
| 29 | } |
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| 30 | |||
| 31 | void initTimer(void) { |
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| 32 | rccEnableTIM1(FALSE); |
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| 33 | rccResetTIM1(); |
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| 34 | nvicEnableVector(TIM1_UP_IRQn, |
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| 35 | CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); |
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| 36 | //gptp->clock = STM32_TIMCLK2; |
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| 37 | |||
| 38 | TIM1->CR1 = 0; /* Initially stopped. */ |
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| 39 | TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any). */ |
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| 3 | mjames | 40 | TIM1->PSC = 72 * 3; /* Prescaler value : 3 uS tick timer . */ |
| 2 | mjames | 41 | TIM1->DIER = 0; |
| 42 | |||
| 43 | } |
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| 44 | |||
| 45 | void stopTimer(void) { |
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| 46 | nvicDisableVector(TIM1_UP_IRQn); |
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| 47 | rccDisableTIM1(FALSE); |
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| 48 | } |
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| 49 | |||
| 50 | void startTimer(void) { |
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| 3 | mjames | 51 | TIM1->ARR = 0xFFFF; /* Time constant. */ |
| 2 | mjames | 52 | TIM1->EGR = TIM_EGR_UG; /* Update event. */ |
| 53 | TIM1->CNT = 0; /* Reset counter. */ |
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| 54 | /* NOTE: After generating the UG event it takes several clock cycles before |
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| 55 | SR bit 0 goes to 1. This is because the clearing of CNT has been inserted |
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| 56 | before the clearing of SR, to give it some time.*/ |
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| 57 | TIM1->SR = 0; /* Clear pending IRQs (if any). */ |
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| 58 | TIM1->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */ |
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| 59 | TIM1->CR1 = TIM_CR1_URS | TIM_CR1_CEN; |
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| 3 | mjames | 60 | |
| 61 | TIM1->CCMR1 = 3344; |
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| 2 | mjames | 62 | } |