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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /* |
| 2 | * hardware.c |
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| 3 | * |
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| 4 | * Created on: 19 Aug 2017 |
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| 5 | * Author: Mike |
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| 6 | */ |
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| 7 | #include "ch.h" |
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| 8 | #include "hal.h" |
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| 9 | #include "hardware.h" |
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| 10 | |||
| 11 | void TIM1_UP_IRQHandler(void) { |
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| 12 | // we have an interrupt here . |
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| 13 | |||
| 14 | |||
| 15 | |||
| 16 | } |
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| 17 | |||
| 18 | void initTimer(void) { |
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| 19 | rccEnableTIM1(FALSE); |
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| 20 | rccResetTIM1(); |
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| 21 | nvicEnableVector(TIM1_UP_IRQn, |
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| 22 | CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); |
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| 23 | //gptp->clock = STM32_TIMCLK2; |
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| 24 | |||
| 25 | TIM1->CR1 = 0; /* Initially stopped. */ |
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| 26 | TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any). */ |
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| 27 | TIM1->PSC = 72; /* Prescaler value. */ |
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| 28 | TIM1->DIER = 0; |
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| 29 | |||
| 30 | } |
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| 31 | |||
| 32 | void stopTimer(void) { |
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| 33 | nvicDisableVector(TIM1_UP_IRQn); |
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| 34 | rccDisableTIM1(FALSE); |
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| 35 | } |
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| 36 | |||
| 37 | void startTimer(void) { |
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| 38 | TIM1->ARR = 12405; /* Time constant. */ |
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| 39 | TIM1->EGR = TIM_EGR_UG; /* Update event. */ |
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| 40 | TIM1->CNT = 0; /* Reset counter. */ |
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| 41 | /* NOTE: After generating the UG event it takes several clock cycles before |
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| 42 | SR bit 0 goes to 1. This is because the clearing of CNT has been inserted |
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| 43 | before the clearing of SR, to give it some time.*/ |
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| 44 | TIM1->SR = 0; /* Clear pending IRQs (if any). */ |
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| 45 | TIM1->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */ |
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| 46 | TIM1->CR1 = TIM_CR1_URS | TIM_CR1_CEN; |
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| 47 | } |