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-- vertical vhdl

--       FPGA / EPLD / PCB / VHDL tools        --

-- NFL Technologies 1995-2003 --

-- by: Mike James 

-- package version:  ²B  compiled: %²B--

-- Produced by WRITE VHDL (HPUX)

-- at 14:05:20  on 01/04/2019 

LIBRARY IEEE,WORK;

USE IEEE.std_logic_1164.ALL;

-- vertical read_off

ENTITY fred IS

  PORT (

     );

END fred;

-- vertical read_on

LIBRARY IEEE,WORK;

USE IEEE.std_logic_1164.ALL;

ARCHITECTURE top_arch OF  fred IS

BEGIN

-- Bundled signals

-- Buffered signals

-- 

END top_arch;

-- vertical end;