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Rev | Author | Line No. | Line |
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2 | mjames | 1 | -- vertical vhdl |
2 | -- FPGA / EPLD / PCB / VHDL tools -- |
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3 | -- NFL Technologies 1995-2003 -- |
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4 | |||
5 | -- by: Mike James |
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6 | |||
7 | -- package version: ²B compiled: %²B-- |
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8 | |||
9 | -- Produced by WRITE VHDL (HPUX) |
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10 | -- at 14:05:11 on 01/04/2019 |
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11 | |||
12 | LIBRARY IEEE,WORK; |
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13 | USE IEEE.std_logic_1164.ALL; |
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14 | |||
15 | |||
16 | -- vertical read_off |
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17 | ENTITY fred IS |
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18 | PORT ( |
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19 | |||
20 | ); |
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21 | END fred; |
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22 | |||
23 | |||
24 | -- vertical read_on |
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25 | LIBRARY IEEE,WORK; |
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26 | USE IEEE.std_logic_1164.ALL; |
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27 | |||
28 | |||
29 | |||
30 | ARCHITECTURE top_arch OF fred IS |
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31 | |||
32 | |||
33 | |||
34 | |||
35 | |||
36 | BEGIN |
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37 | |||
38 | -- Bundled signals |
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39 | |||
40 | -- Buffered signals |
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41 | |||
42 | -- |
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43 | |||
44 | END top_arch; |
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45 | |||
46 | |||
47 | -- vertical end; |