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2 mjames 1
-- vertical vhdl
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--       FPGA / EPLD / PCB / VHDL tools        --
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-- NFL Technologies 1995-2003 --
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-- by: Mike James 
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-- package version:  ²B  compiled: %²B--
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-- Produced by WRITE VHDL (HPUX)
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-- at 14:05:11	on 01/04/2019 
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LIBRARY IEEE,WORK;
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USE IEEE.std_logic_1164.ALL;
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-- vertical read_off
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ENTITY fred IS
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  PORT (
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     );
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END fred;
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-- vertical read_on
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LIBRARY IEEE,WORK;
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USE IEEE.std_logic_1164.ALL;
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ARCHITECTURE top_arch OF  fred IS
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BEGIN
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-- Bundled signals
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-- Buffered signals
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-- 
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END top_arch;
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-- vertical end;