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%{

/*

 * $Header: C:/cvsroot/Vert03/acf_src/acf_yacc.y,v 1.1.1.1 2003/11/04 23:34:58 mjames Exp $ *//*

 *

 * $Log: acf_yacc.y,v $

 * Revision 1.1.1.1  2003/11/04 23:34:58  mjames

 * Imported into local repositrory

 *

 * Revision 1.38  2002/12/06 23:28:04  mjames

 * Corrected locations where GND was being a

 *  reserved word and in fact was legal as pin/port ident

 *

 * Also error checked problems of duplicate idents appearing

 *

 * Revision 1.37  2002/10/02 18:45:23  MJAMES

 * use routed_net member in place of net member when jumpers are processed

 *

 * Revision 1.36  2002/09/30 13:25:31  MJAMES

 * Upgraded nets to include 'lhs_expression' being the range on the

 * left hand side of a signal connection to a port

 *

 * std_logic_vector (0) <= std_logic , on a port of a chip

 *

 * Revision 1.35  2002/09/16 11:02:44  mjames

 * Added some of the generic string  types  to the input parser.

 *

 * Revision 1.34  2002/09/09 10:14:58  mjames

 * Modified expression parser to match CC as previous one was

 * broken

 *

 * Revision 1.33  2002/08/23 14:21:54  mjames

 * Added the <VHDL> string keyword.

 *

 * Revision 1.32  2002/08/19 14:31:26  mjames

 * Removed an incompatibility with env_string generics where the output

 * of Vertical caused an error under some circumstances.

 *

 * Revision 1.31  2002/08/14 12:00:15  mjames

 * cleaned up on end of file code

 *

 * Revision 1.30  2002/08/06 12:54:14  mjames

 * Merge in from latest version

 *

 *

 * Revision 1.32  2002/03/22 16:16:28  mjames

 * Modifications to undo over-zealous checking of

 * current chip even in incorrect scenarios.

 *

 * Revision 1.31  2002/03/19 11:59:34  mjames

 * Applying paranoid programming to the use of current_chip pointer

 * as there were some address exceptions created in cases of missing

 * components being instantiated in VHDL

 *

 * Revision 1.30  2002/03/08 11:53:57  mjames

 * Corrected verilog module instance code

 *

 * Revision 1.29  2002/01/16 22:02:36  mjames

 * Prevented coredumps while reading Verilog file

 * s.g. Should permit further analysis of added

 * requirements for complete Verilog reading

 *

 * Revision 1.28  2002/01/16 10:06:19  mjames

 * Added package definitions to VHDL syntax

 * According to report by John Marquis

 *

 * Revision 1.27  2002/01/03 16:39:17  mjames

 * Removed unused rule causing coredump

 *

 * Revision 1.26  2001/12/13 22:12:15  mjames

 * Vertical now supports nested include database files

 * This allows wrappers around 'pure' VHDL or Verilog files

 *

 * Revision 1.25  2001/12/11 21:29:56  mjames

 * Verilog syntax now read in by Vertical allows pin templates

 * defined  by Certify to be used.

 *

 * Revision 1.24  2001/11/30 22:47:37  mjames

 * small corrections

 *

 * Revision 1.23  2001/11/30 22:21:19  mjames

 * Modifying Verilog reading syntax to accept valid code.

 *

 * Revision 1.22  2001/11/19 09:46:14  mjames

 * Semicolons missing: caused error with byacc

 *

 * Revision 1.21  2001/10/31 22:19:57  mjames

 * Tidying up problematical comments caused by CVS

 * 'intelligent' comment guessing

 *

 * Revision 1.20  2001/10/31 16:27:25  mjames

 * Added a datastructure to hide regular expression information from programs.

 * Changed call to regexec to indicate 0 subexpressions to be matched

 * rather than a number dependent on strlen(string) which was wrong.

 *

 * Revision 1.19  2001/10/02 20:55:37  mjames

 * Moved documentation about code to main program module.

 *

 * Revision 1.18  2001/09/21 14:13:10  mjames

 * Corrected the creation of chip pinouts from VHDL source so that both

 * ENTITY and COMPONENT port declarations assign a pin identifier that is

 * the same as the pin name. Otherwise templating does not work, to create

 * pin identifiers for a PCB

 *

 * Revision 1.17  2001/08/31 09:36:54  mjames

 * removed DOS line endings

 *

 * Revision 1.16  2001/07/09 09:36:30  mjames

 * Amending the syntax and end of file behaviour to allow Quartus pin fit files

 * to be read .

 * They are harder to read because they are not block structured. The end of file is used as a marker. Vertical has been persuaded to handle end of file events properly.

 *

 * Revision 1.15  2001/07/06 12:50:36  mjames

 * Added the ability to read in Quartus pinfit files

 *

 * Revision 1.14  2001/07/05 15:12:37  MJAMES

 * Amended to read Quartus pin files. not fully working

 *

 * Revision 1.13  2001/06/07 11:59:05  MJAMES

 * Strange GCC optimiser error on line  1172. Changed code to trap possible error that

 * should not happen anyway: probably a PII optimiser bug.

 *

 * Revision 1.12  2001/06/06 14:46:03  mjames

 * Added further Verilog support.

 * Corrected write ext command to not require additional argument.

 * Added write quartus for creation of a pinfit file relevant to Quartus

 *

 * Revision 1.11  2001/06/06 12:10:26  mjames

 * Move from HPUX

 *

 * Revision 1.10  2001/04/30 13:31:44  Administrator

 * Started to add in Verilog parsing

 *

 *

 * Revision 1.1  96/01/04  10:18:07  10:18:07  mjames (Mike James)

 * Initial revision

 *

 *  */

#include <stdio.h>

#include <string.h>

#include <stdlib.h>

#include <ctype.h>

#include "vertcl_main.h"

#include "expression.h"

#include "generic.h"

#include "database.h"

#include "routing.h"

#include "cmdparse.h"

#include "cmdlog.h"

#include "jumpering.h"

#include "unrouted.h"

#include "lx_support.h"

#include "equivalent.h"

#include "acf_lex_ext.h"

#define YYERROR_VERBOSE

int lineno;

/* Structure to hold a set of identifiers for later processing */

struct str * y_first = NULL, * y1_first=NULL;

struct str * y_last  = NULL, * y1_last =NULL  ;

int id_count = 0;

#ident "@(#)$Header: C:/cvsroot/Vert03/acf_src/acf_yacc.y,v 1.1.1.1 2003/11/04 23:34:58 mjames Exp $"

static socket_t * current_chip, * current_comp;

static node_t   * current_node, * current_comp_node;

static net_t    * current_net;

static net_t   ** current_list;

/* used in net joining in the YACC parser */

static net_t    ** join_context;

static JoinMode_t join_mode;

static net_t    * top_net;

static vhdl_t * vhdl;

static generic_info_t ** generic_context;

static equivalent_node_set_t * curr_equiv_list;

static char curr_pin_name[MAXIDLEN];

static char curr_pin_ident[MAXIDLEN];

static int  curr_pin_dir;

static int  curr_pin_group;

static generic_info_t info[1]; /* this is a local scratch area */

/* handed back to the command line expression parser */

static char * rename_pin_string;

static char text_buff[MAXIDLEN];

void process_tdf_pins(struct str * s);

int inside_block = 0;

extern void exit_lex_block(void); /* means to return LEX  to initial state */

extern void create_pins_or_signals(void);

/* is the current component instance running implicit or explicit 

   port mapping ? */

typedef enum { UNKNOWN,IMPLICIT,EXPLICIT } port_map_method;

port_map_method curr_comp_port_map; 

%}

%union { char * string;

         int  integer;

         generic_info_t * range ; 

         expression_t   * exp; };

%token FILEMODE CMDMODE

%token CHIP BEGIN_TOK END DEVICE 

%token COMPONENTS WIRED_NETS CONN

%token END_CONN JOINED_NETS ALIAS JUMPER RENAME_PINS

%token TEMPLATE FIX_LOCATION LOCATION UNROUTED ROUTED NAMED

%token ASSIGN SIG_ASSIGN CONNECTED ROUTE_FLAGS DECLARATION INSTANCE

%token AHDL VERILOG SUBDESIGN OPEN BOOLEAN TRUE FALSE

%token TO DOWNTO  GENERIC RANGE INTEGER NATURAL CONSTANT

%token VHDL PORT ENTITY IS COMPONENT MAP ARCHITECTURE OF

%token EQUIVALENT TO_POW ASIGNAL MODULE ENDMODULE LIBRARY USE ALL

%token PACKAGE FOR PROCESS 

%token ASSIGNED AN WIRE GND GND_RES_IO GND_RES_IN VCC

%token ATTRIBUTE ENV_STRING STRING SHL SHR EQ_EQ N_EQ LOG_AND LOG_OR

%token QUOTE VHDL_CONN

%token <string>  QUOTED_STRING

%token <string>  TXT_STRING

%token <string>  NUM_STRING

%token <integer> PINDIR

%token <string>  VCC

%token <string>  GND

%type  <integer> generic_pindir_opt

%type  <exp>     expr

%type  <exp>     primary_expr

%type  <exp>     add_expr

%type  <exp>     mult_expr

%type  <exp>     shift_expr

%type  <exp>     relational_expr

%type  <exp>     equality_expr

%type  <exp>     and_expr

%type  <exp>     exor_expr

%type  <exp>     or_expr

%type  <exp>     logand_expr

%type  <exp>     logor_expr

%type  <exp>     cond_expr

%type  <exp>     expr1

%type  <exp>     bus_range

%type  <string>  astring

%type  <string>  netname

%type  <string>  vhdl_lib_member_select

%type  <exp>     opt_integer

%type  <exp>     opt_bus_range

%type  <exp>     verilog_bus_expr

%type  <exp>     colon_expr

%type  <exp>     vhdl_type_default_value_opt

%type  <exp>     vhdl_port_map_slice_opt 

%type  <exp>     simple_range_expr

%left UMINUS '~'

%left '('

%%

/* two grammars present, one is vertical .acfp file, 

   the other is from the command line. Eventually these two grammars

   will be merged */

file    : FILEMODE objects 

        | CMDMODE  cmd_objects;

/************************************************************************/

/* COMMAND MODE GRAMMAR                                                 */

/************************************************************************/

cmd_objects : cmd_objects cmd_object

            | cmd_object

            ;

cmd_object : bus_range { cmd_expression = $1; }

           ; 

/************************************************************************/

/* FILE MODE GRAMMAR                                                    */

/************************************************************************/

objects : objects object

        | object

        ;

object  : chip_decl

        | components_decl

        | template_decl

        | joined_decl

        | nets_decl

        | rename_pins_block

        | global_generic_decl

        | vhdl_region

        | verilog_region

        | ahdl_region

        | 

        ;

/****************************************************************/

/* all string types */          

astring : QUOTED_STRING { $$=$1; }

        | TXT_STRING { $$=$1; }

        | NUM_STRING  { $$=$1; };

/****************************************************************/

/* beginning finding the chip declaration */

/****************************************************************/

chip_decl       : chip_id_decl chip_body;

chip_body       : BEGIN_TOK flex_chip_body

                | ASSIGNED  apex_chip_body

                ;

/******************************************************************/

/* old style FLEX/acfp  CHIP declaration */

flex_chip_body :    chip_info_lines

                    pin_declarations

                    pin_equivalences

                    END  end_item { 

                     free_lex_strings();

                     exit_lex_block();

                     current_chip = NULL;}

                ;

chip_id_decl       :  CHIP astring

                      { id_count = 0; /* used in pin ID lists */

                        current_chip=find_socket(Name,$2,Create,&socket_head);

                        /* current_chip is unlikely to be null .. but */

                        if (current_chip)

                          {

                          current_chip->is_template = 0;

                          current_chip->parent_template_ref = NULL;

                          current_chip->route_flags = 0;

                          /*   ensure_socket_ident(current_chip); */

                          if(ISNULLSTR(current_chip->identifier))

                            {

                            socket_t * test = find_socket(Ident,$2,Search,&socket_head);

                            if (!test) 

                              set_socket(current_chip,Ident,$2);

                            else

                              {

                              Log(LOG_ERROR,"-- ERROR :name '%s' clashes with another ID in CHIP declaration\n",$2);

                              set_socket(current_chip,Ident,"name clashes with another chip ident in CHIP declaration");

                              }

                            }

                          }

                      };

chip_info_lines :  chip_info_lines chip_info_line

                 | chip_info_line

                 | /* nothing */

                 ;

chip_info_line :  device_declaration 

               |  route_flags_info 

               | routing_status 

               | chip_generic_decl;

device_declaration :  DEVICE '=' astring end_item

                      { if(current_chip) 

                          set_socket(current_chip,Type,$3);

                      };

pin_equivalences :  pin_equivalence pin_equivalences

                 |  pin_equivalence

                 | /* nothing */

                 ;

/* gap              : NL gap

                  | NL

                  |

                  ;

 */

end_item         : ';'  ;

routing_status   : UNROUTED end_item

                 ;

/* routing flags are used in fasttrack routing */ 

route_flags_info     : ROUTE_FLAGS '=' route_flag_value end_item

                ;

route_flag_value : NUM_STRING {  if(current_chip) 

                                    convert_num($1,&current_chip->route_flags); };  

/****************************************************************/

/* these patterns are shared between CHIP and TEMPLATE .

   A flag is set in the form of chip_context to slightly modify

   undesirable behaviour */

pin_declarations   : pin_declarations pin_declaration

                   | pin_declaration

                   |

                   ;

pin_declaration    : name_part ':' pin_rest end_item

                   ;

/* if the chip pin is given a name in the template , suppress it. It

   will attempt to link the template to a real net if the pin has a name */

name_part : netname  { char * s ;

                      s = make_string($1,&y_first,&y_last);

                      strcpy(curr_pin_name,"Still_Using_pin_name_somewhere");

                      curr_pin_dir = NONE; /* default bidirectional */

                      if(ISNULLSTR(s))/* the null strings tell acfread that the pin exists and */

                        current_list = &routed_list ;/* available for routing */

                      else

                        current_list = &unrouted_list ;

                     };

pin_rest :  pin_dir pin_group '=' pin_ident vhdl_type_opt   

          | UNROUTED                /* no action */

          | LOCATION '=' astring /* no action */

          ; 

pin_dir : PINDIR { curr_pin_dir = $1; }

          ;

pin_group : '(' NUM_STRING ')' { convert_num($2,&curr_pin_group); }

          | /* nothing */        { curr_pin_group = 0; }; 

pin_ident : netname   { strcpy(curr_pin_ident,$1); };

/***********************************************************************************/

/* APEX handler */

apex_chip_body :  apex_device_declaration

                  apex_info_lines ; 

apex_device_declaration :  TO AN astring apex_speed_grade 

                      { if(current_chip) 

                          set_socket(current_chip,Type,$3);

                      };

apex_speed_grade : '-' NUM_STRING  {   generic_info_t info;

                     char * sbuff = malloc(strlen($2)+2);

                     sprintf(sbuff,"-%s",$2);

                     info.expr     = compile_string(sbuff);

                     free(sbuff);

                     info.name = "speed_grade";

                     info.typename = "string";

                     info.g_type   = IS_DECLARATION_DIRECTIVE;

                     if(current_chip)

                        set_generic_value(&current_chip->generics,&info);

                     }

                 | /* nothing */

                 ;

apex_info_lines : apex_info_lines apex_info_line

                | apex_info_line;

apex_info_line  : GND          ':' astring more_colons { /* ground pin .. no op */ }

                | GND_RES_IO   ':' astring more_colons   { /* reserved pin .. no op */ }

                | GND_RES_IN   ':' astring more_colons   { /* reserved pin .. no op */ }

                | VCC          ':' astring ':' NUM_STRING    { /* power pin .. no op */ }

                | VCC          ':' astring more_colons  { /* as this pattern shows..     power pin .. no op */ }

                | TXT_STRING   ':' astring more_colons   {/*printf("ignore pin %s at %s\n",$1,$3);*//* reserved pin .. no op */ }

                | TXT_STRING   ':' astring  ':' PINDIR ':' astring ':'  { current_list = &unrouted_list ;

                               make_string($1,&y_first,&y_last);

                               /*printf("pin %s at %s\n",$1,$3);*/

                               strcpy(curr_pin_ident,$3);

                               curr_pin_dir = $5;

                               vhdl = default_vhdl_datatype; 

                               create_pins_or_signals(); 

                               }

                | TXT_STRING '[' expr ']'   ':' astring  ':' PINDIR ':' astring ':'  { current_list = &unrouted_list ;

                               make_string($1,&y_first,&y_last);

                               /*printf("pin %s at %s\n",$1,$3);*/

                               vhdl = calloc(1,sizeof(vhdl_t));

                               vhdl->is_vector = 1;

                               vhdl->expr = $3; 

                               strcpy(curr_pin_ident,$6);

                               curr_pin_dir = $8;

/*                             vhdl = default_vhdl_datatype; */

                               create_pins_or_signals(); 

                               }

                ;

more_colons : ':' more_colons

           | ':'

           ;

/************************************************************************************/

/* begin to recognise the possible VHDL syntax for a VHDL type */

/* this declaration is where the pin type is purely optional in ACFP files */

vhdl_type_opt : ':' vhdl_type

              | /* nothing */    {    /* use a default type if none given */

              vhdl = default_vhdl_datatype;

              create_pins_or_signals();

              } ;/* altering define pin to take a pointer to VHDL type */

/* this declaration is a 'pure' VHDL that can be used in VHDL chunks */

vhdl_type : astring vhdl_type_default_value_opt { /* single bit types */

                       vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                       if(vhdl){ 

                         vhdl->basetype = allocstr($1);

                         vhdl->is_vector = 0;

                         vhdl->is_downto = 0; 

                         vhdl->expr      = NULL;

                         vhdl->default_expr = $2;/* added default assignment expression */

                        create_pins_or_signals();

                        }

                     }

          | astring '(' bus_range ')'  vhdl_type_default_value_opt { /* vhdl vector types */

                   vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                   if(vhdl){ 

                       vhdl->basetype = allocstr($1); 

                       vhdl->is_vector = 1; /* not known for sure yet */

                       vhdl->is_downto = 0; 

                       vhdl->expr      = $3;

                       vhdl->default_expr = $5;/* added default assignment expression */

                       create_pins_or_signals();                  

                       }

#if defined DEBUG_EXPRESSION

                  print_msg_expression(stdout,"seen bus ",$3);

#endif

                  }

          | INTEGER  vhdl_type_default_value_opt { /* added Nov 2000 */

                   vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                   if(vhdl){ 

                       vhdl->basetype = "integer"; 

                       vhdl->is_vector = 0; /* not known for sure yet */

                       vhdl->is_downto = 0; 

                       vhdl->expr      = NULL;

                       vhdl->default_expr = $2;/* added default assignment expression */

                       create_pins_or_signals();                  

                       }

            }

          | INTEGER RANGE simple_range_expr vhdl_type_default_value_opt { /* added Nov 2000 */

                   vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                   if(vhdl){ 

                       vhdl->basetype = "integer range"; 

                       vhdl->decl_expr = $3;

                       vhdl->is_vector = 0; /* not known for sure yet */

                       vhdl->is_downto = 0; 

                       vhdl->expr      = NULL;

                       vhdl->default_expr = $4;/* added default assignment expression */

                       create_pins_or_signals();                  

                       }

            }

          | NATURAL  vhdl_type_default_value_opt { /* added Nov 2000 */

                   vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                   if(vhdl){ 

                       vhdl->basetype = "natural"; 

                       vhdl->is_vector = 0; /* not known for sure yet */

                       vhdl->is_downto = 0; 

                       vhdl->expr      = NULL;

                       vhdl->default_expr = $2;/* added default assignment expression */

                       create_pins_or_signals();                  

                       }

            }

          | NATURAL RANGE simple_range_expr vhdl_type_default_value_opt { /* added Nov 2000 */

                   vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                   if(vhdl){ 

                       vhdl->basetype = "natural range"; 

                       vhdl->decl_expr = $3;

                       vhdl->is_vector = 0; /* not known for sure yet */

                       vhdl->is_downto = 0; 

                       vhdl->expr      = $3;

                       vhdl->default_expr = $4;/* added default assignment expression */

                       create_pins_or_signals();                  

                       }

            }

          | BOOLEAN  vhdl_type_default_value_opt { /* added May 2001 */

                   vhdl = (vhdl_t *)calloc(1,sizeof(vhdl_t));

                   if(vhdl){ 

                       vhdl->basetype = "boolean"; 

                       vhdl->is_vector = 0; /* not known for sure yet */

                       vhdl->is_downto = 0; 

                       vhdl->expr      = NULL;

                       vhdl->default_expr = $2;/* added default assignment expression */

                       create_pins_or_signals();                  

                       }

            };

 vhdl_type_default_value_opt : ASSIGN bus_range { $$ = $2; /* printf("found default assign\n");*/ }

                             | /* nothing */    { $$ = NULL; }

                             ;

/* general generic stuff */ 

bus_range      :  expr1  

               |  expr

               ;

/* an expression of type range at top level is allowed */                

expr1          : simple_range_expr  {

                    $$ = $1;

                    } 

               |QUOTED_STRING {

                      $$ = compile_string($1);

                      }

               | QUOTE astring QUOTE{

                      $$ = compile_char($2[0]);

                      }

                 ;

simple_range_expr :   expr TO expr  {

                    $$ = compile_expression(TO,$1,$3); 

                    } 

                   |  expr DOWNTO expr  { 

                    $$ = compile_expression(DOWNTO,$1,$3); 

                    }

                 ;

/* an expression calculator that will use the generics 

   attached to the current chip to work out the values */

primary_expr :'(' expr ')'

    {  

    $$ = compile_expression('(',$2,NULL);

    }

  |  '~' expr %prec UMINUS

    {

    $$ = compile_expression('~',$2,NULL);

    }   

  | '-' expr %prec UMINUS

    {

    $$ = compile_expression(UMINUS,$2,NULL);

    }

  | NUM_STRING { int t;

          convert_num($1,&t);

          $$ = compile_constant_string(t,$1);  

        }

  | TXT_STRING

      { 

          $$ = compile_reference($1);

      }

  | TRUE {

      $$=compile_constant_string(1,"true"); /* should really respect boolean type */

      }

  | FALSE {

      $$=compile_constant_string(0,"false");

      }

  ;

mult_expr :  primary_expr

    {

    $$ = $1;

    }

  | mult_expr '*' primary_expr

    {

    $$ = compile_expression('*',$1,$3);

    }

  | mult_expr '/' primary_expr

    { 

    $$ = compile_expression('/',$1,$3);

    }

  | mult_expr '%' primary_expr

    { 

    $$ = compile_expression('%',$1,$3);

    }

  | mult_expr TO_POW primary_expr  {

    $$ = compile_expression(TO_POW,$1,$3); 

    }

  ;

add_expr : mult_expr

    {

    $$ = $1;

    }

  | add_expr '+' mult_expr

    {

    $$ = compile_expression('+',$1,$3);

    }

  | add_expr '-' mult_expr

    {

    $$ = compile_expression('-',$1,$3);

    }

  ;

shift_expr : add_expr

    {

    $$ = $1;

    }

  | shift_expr SHL add_expr 

    {

    $$ = compile_expression(SHL,$1,$3);

    }

  | shift_expr SHR add_expr

    {

    $$ = compile_expression(SHR,$1,$3);

    }

  ;

relational_expr : shift_expr  

    {

    $$ = $1;

    }

  | relational_expr '>' shift_expr 

    {

    $$ = compile_expression('>',$1,$3);

    }

  | relational_expr '<' shift_expr

    {

    $$ = compile_expression('<',$1,$3);

    }

  ;

equality_expr : relational_expr  

    {

    $$ = $1;

    }

  | equality_expr EQ_EQ relational_expr

    {

    $$ = compile_expression(EQ_EQ,$1,$3);

    }

  | equality_expr N_EQ relational_expr

    {

    $$ = compile_expression(N_EQ,$1,$3);

    }

   ;

and_expr : equality_expr

    {

    $$ = $1;

    }

  | and_expr '&' equality_expr

    {

    $$ = compile_expression('&',$1,$3);

    }

  ;

exor_expr : and_expr

    {

    $$ = $1;

    }

  | exor_expr '^' and_expr

    {

    $$ = compile_expression('^',$1,$3);

    } 

  ;  

or_expr : exor_expr

    {

    $$ = $1;

    }

  | or_expr '|' or_expr

    {

    $$ = compile_expression('|',$1,$3);

    } 

  ;  

logand_expr: or_expr

    {

    $$ = $1;

    }

  | logand_expr LOG_AND or_expr

    { 

    $$ = compile_expression(LOG_AND,$1,$3);

    }

  ;

logor_expr : logand_expr

    {

    $$ = $1;

    }

  | logor_expr LOG_OR logand_expr

    { 

    $$ = compile_expression(LOG_OR,$1,$3);

    }

  ;

cond_expr :  logor_expr '?' colon_expr

    {

    $$ = compile_expression('?',$1,$3);

    }

  ;

colon_expr : expr ':' expr

  { /* change from cond_expr on rhs */

  $$ = compile_expression(':',$1,$3);

  };

expr : cond_expr

       {

       $$ = $1;

       } 

     | logor_expr

       {

       $$ = $1;

       }

     ;

/**************************************************************************/

/* pin equivalence  Declarations                                                 */

/**************************************************************************/

pin_equivalence : EQUIVALENT { curr_equiv_list = begin_equivalent_pins(); } 

                    '(' equivalent_pins ')'

                  end_item { if(current_chip)

                                check_equivalent_pins(current_chip,curr_equiv_list); } 

                  ;

equivalent_pins : equivalent_pin end_item equivalent_pins

                | equivalent_pin

                | /* nothing */

                ;               

equivalent_pin : astring { if(current_chip)

                             add_equivalent_pin( current_chip,curr_equiv_list,$1); };

/**************************************************************************/

/* VHDL Block Declarations                                                 */

/**************************************************************************/

vhdl_region       : VHDL

                    vhdl_blocks

                    END  end_item { exit_lex_block(); free_lex_strings(); }

                    ; 

vhdl_blocks   : vhdl_blocks vhdl_block

              | vhdl_block

              ;  

/* now includes the idea of a VHDL architecture as the equivalent of a template */

vhdl_block    : vhdl_chip_decl

              | vhdl_architecture

              | vhdl_package_decl /* but not a package body... */

              | vhdl_library_decl

              | vhdl_use_decl

              | /* nothing */

              ;

/**************************************************************************/

/* VHDL Chip Entity Declaration                                                 */

/**************************************************************************/

vhdl_chip_decl   : ENTITY hdl_entityname_decl IS { 

                      Log(LOG_GENERAL,

                       "(line %d) Using ENTITY declaration for %s : prefer to use COMPONENT\n",lineno,current_chip->type);

                      } 

                   vhdl_generic_decl_opt

                   vhdl_port_decl_opt

                   END TXT_STRING end_item {

                                 current_chip = NULL; }; 

/* this shared with verilog */

hdl_entityname_decl  :  TXT_STRING

                      {

                        current_chip=find_socket(Name,$1,Create,&socket_head);

                        if(current_chip)

                          {

                          current_chip->is_template = 0;

                          current_chip->parent_template_ref = NULL;

                          current_chip->route_flags = 0;

                          set_socket(current_chip,Type,$1);

                          if(ISNULLSTR(current_chip->identifier))

                            set_socket(current_chip,Ident,$1); 

                          if(ISNULLSTR(current_chip->type))

                            set_socket(current_chip,Type,$1); 

                          generic_context = &current_chip->generics;

                          curr_pin_ident[0] = 0;  /* use the signal name instead if this string is empty */                  

                          }

                       };

vhdl_generic_decl_opt : vhdl_generic_decl 

                      | /* nothing */ ;

/* the generic information here shares the standard generic declaration

   from the ACFp declaration */

vhdl_generic_decl : GENERIC '(' { if (current_chip) 

                                    generic_context = &current_chip->generics; }

                    generic_defn_lines

                    ')' end_item

                     ;

/**************************************************************/

/* port list */

/**************************************************************/

vhdl_port_decl_opt : vhdl_port_decl

                   | /* nothing */

                   ;

vhdl_port_decl    : PORT '(' vhdl_port_list ')' end_item; 

vhdl_port_list : vhdl_port_list end_item vhdl_port_item

               | vhdl_port_item

               | /* nothing */

               ;

/* the VHDL Port item , inherits the pin_dir from a standard chip declaration 

 and the vhdl type extraction from the generic type declaration 

  */

vhdl_port_item    : vhdl_name_list ':' pin_dir vhdl_type 

                    vhdl_assign_opt  {if(current_chip)

                                        create_nodes_from_refs(current_chip,0); }; 

vhdl_name_list : vhdl_name_list ',' hdl_name_part

               | hdl_name_part

               ;

/* null the pin identifier to allow for creation of an ident in define_pin 

 */

/* this is a pin on a component declaration */

hdl_name_part : netname {

                   char * s = make_string($1,&y_first,&y_last);

                   if(current_chip) 

                     {

                     curr_pin_dir = NONE; /* default bidirectional */

                     if(current_chip->is_template ==1 || 

                        (ISNULLSTR(s) && id_count ==0))/* the null strings tell acfread that the pin exists and */

                       current_list = &routed_list ;/* available for routing */

                     else

                       current_list = &unrouted_list ;

                     id_count++;

                     }

                   };

vhdl_assign_opt : ASSIGN expr  

                | /* nothing */

                ;

/***********************************************************************/

/* VHDL Architecture Declaration                                       */

/***********************************************************************/

vhdl_architecture    : ARCHITECTURE  astring OF astring IS

                         vhdl_architecture_declarations 

                       BEGIN_TOK

                         vhdl_architecture_body_items

                       END astring end_item;

vhdl_architecture_declarations: vhdl_architecture_declarations vhdl_architecture_decl

                               | vhdl_architecture_decl

                               | /* nothing */                              

                               ;

vhdl_architecture_decl : vhdl_component_decl

                       | vhdl_constant_decl

                       | vhdl_signal_decl

                       | vhdl_configuration_decl

                       ;

/**********************************************************************/

/* VHDL Package Declaration                                           */

/**********************************************************************/

vhdl_package_decl : PACKAGE package_name IS 

                      vhdl_package_declarations

                    END astring end_item ;

package_name : astring { Log(LOG_GENERAL,"-- (line %d)  package %s being read\n",lineno,$1); };

vhdl_package_declarations: vhdl_package_declarations vhdl_package_decl_item

                               | vhdl_package_decl_item

                               | /* nothing */                              

                               ;

vhdl_package_decl_item : vhdl_component_decl

                       | vhdl_constant_decl

                       | vhdl_signal_decl

                       | vhdl_configuration_decl

                       ;

/***********************************************************************/

/* VHDL Component Declaration                                          */

/***********************************************************************/

vhdl_component_decl: COMPONENT

                     hdl_compname_decl

                     vhdl_generic_decl_opt

                     vhdl_port_decl_opt

                     END COMPONENT

                     end_item { if(current_chip)

                                  create_nodes_from_refs(current_chip,0);

                                current_chip = NULL; };

hdl_compname_decl : TXT_STRING 

                      {

                        current_chip=find_socket(Name,$1,Create,&template_head);

                        if(current_chip)

                          {

                          current_chip->is_template = 1;/* components look like templates */

                          current_chip->parent_template_ref = NULL;

                          current_chip->route_flags = 0;

                          ensure_socket_ident(current_chip);

                          set_socket(current_chip,Type,$1); /* socket name is also a type */

                          generic_context = &current_chip->generics;

                          }

                       };

/***********************************************************************/

/* VHDL Constant Declaration                                          */

/***********************************************************************/

vhdl_constant_decl : CONSTANT { generic_context = & global_generics; } 

                     generic_defn_text end_item; 

/***********************************************************************/

/* VHDL Signal Declaration                                             */

/***********************************************************************/

vhdl_signal_decl : ASIGNAL { id_count = 0 ; y_first = NULL;y_last = NULL;  } 

                     hdl_signal_names ':' vhdl_type

/*                   { char buf[200];

                       printf("... type='%s'\n",decode_vhdl_type(buf,vhdl));

                     } 

*/

                     end_item;

/* collect together all of the signal names that share the type declaration */

hdl_signal_names : hdl_signal_names ',' hdl_signal_name

                  | hdl_signal_name

                  ;

hdl_signal_name : astring {

                   /* y_first is defined as null so we do not create any 

                     pins (as they do not belong to any particular chip) */

#if defined DEBUG_EXPRESSION

                   printf("making sig name %s\n",$1);

#endif

                   make_string($1,&y1_first,&y1_last);

                   id_count++;

                   };

/***********************************************************************/

/* VHDL Configuration Declaration                                             */

/***********************************************************************/

/* for <scope> ':' <component> use entity <library>.<entity>(<architecture>)      */

/* for ALL : draw USE ENTITY work.draw(rtl); */

vhdl_configuration_decl : FOR

                   vhdl_lib_member_select ':' astring USE ENTITY 

                   astring '.' astring '(' astring ')' ';'

                   { Log(LOG_GENERAL,"-- (line %d)  for %s: %s use entity %s.%s(%s);\n",lineno,$2,$4,$7,$9,$11); };

/* code currently omitted */

/***********************************************************************/

/* VHDL Architecture body items                                        */

/***********************************************************************/

vhdl_architecture_body_items: vhdl_architecture_body_items vhdl_architecture_body_item

                               | vhdl_architecture_body_item

                               | /* nothing */                              

                               ;

vhdl_architecture_body_item :  vhdl_concurrent_assignment

                            |  vhdl_component_instance

                            ; 

/************************************************************************/

/* VHDL Component Instantiation                                         */

/************************************************************************/

/* this code now sets up all unused ports to  be bound to signals of the

   same name as the ports (makes setting up simple architectures using

   Vertical shorthand easier */

vhdl_component_instance : vhdl_inst_comp_binding 

                          vhdl_inst_generic_map

                          vhdl_inst_port_map end_item {

                            if(current_comp && current_chip) { /* scan for unused nodes */

                              current_comp_node = current_comp->nodes;

                              while(current_comp_node) {

                                if (current_comp_node->in_use == 0) {  

                                  /* hookup to an unroutd signal */

                                  define_pin(&unrouted_list,

                                    current_chip,

                                    current_comp_node->name,

                                    current_comp_node->pindir,

                                    current_comp_node->pin_group,

                                    current_comp_node->identifier,

                                    current_comp_node->vhdltype,

                                    NULL);