WebSVN – Vertical – Blame – /trunk/acf_src/acf_yacc.output

Rev	Author	Line No.	Line
2	mjames	1	Terminals which are not used:
		2
		3	PROCESS
		4
		5
		6	State 1 contains 10 shift/reduce conflicts.
		7	State 9 contains 2 shift/reduce conflicts.
		8	State 10 contains 1 shift/reduce conflict.
		9	State 12 contains 5 shift/reduce conflicts.
		10	State 13 contains 10 shift/reduce conflicts and 1 reduce/reduce conflict.
		11	State 42 contains 4 shift/reduce conflicts.
		12	State 43 contains 2 shift/reduce conflicts.
		13	State 44 contains 2 shift/reduce conflicts.
		14	State 45 contains 2 shift/reduce conflicts.
		15	State 46 contains 2 shift/reduce conflicts.
		16	State 47 contains 1 shift/reduce conflict.
		17	State 48 contains 1 shift/reduce conflict.
		18	State 49 contains 1 shift/reduce conflict.
		19	State 50 contains 1 shift/reduce conflict.
		20	State 51 contains 2 shift/reduce conflicts.
		21	State 58 contains 3 shift/reduce conflicts.
		22	State 60 contains 4 shift/reduce conflicts and 5 reduce/reduce conflicts.
		23	State 67 contains 2 shift/reduce conflicts and 1 reduce/reduce conflict.
		24	State 71 contains 2 shift/reduce conflicts.
		25	State 73 contains 1 shift/reduce conflict.
		26	State 82 contains 6 shift/reduce conflicts.
		27	State 90 contains 4 shift/reduce conflicts.
		28	State 93 contains 2 shift/reduce conflicts.
		29	State 123 contains 4 shift/reduce conflicts.
		30	State 137 contains 1 shift/reduce conflict.
		31	State 153 contains 3 shift/reduce conflicts.
		32	State 154 contains 4 reduce/reduce conflicts.
		33	State 178 contains 5 shift/reduce conflicts.
		34	State 189 contains 7 shift/reduce conflicts and 7 reduce/reduce conflicts.
		35	State 198 contains 4 shift/reduce conflicts.
		36	State 199 contains 4 shift/reduce conflicts.
		37	State 200 contains 2 shift/reduce conflicts.
		38	State 201 contains 2 shift/reduce conflicts.
		39	State 202 contains 2 shift/reduce conflicts.
		40	State 203 contains 2 shift/reduce conflicts.
		41	State 204 contains 2 shift/reduce conflicts.
		42	State 205 contains 2 shift/reduce conflicts.
		43	State 206 contains 2 shift/reduce conflicts.
		44	State 207 contains 1 shift/reduce conflict.
		45	State 208 contains 1 shift/reduce conflict.
		46	State 209 contains 1 shift/reduce conflict.
		47	State 210 contains 1 shift/reduce conflict.
		48	State 222 contains 5 shift/reduce conflicts.
		49	State 227 contains 1 shift/reduce conflict.
		50	State 247 contains 1 shift/reduce conflict.
		51	State 269 contains 4 shift/reduce conflicts.
		52	State 305 contains 3 shift/reduce conflicts.
		53	State 352 contains 1 reduce/reduce conflict.
		54	State 374 contains 4 shift/reduce conflicts.
		55	State 393 contains 4 shift/reduce conflicts.
		56	State 487 contains 3 shift/reduce conflicts.
		57	State 495 contains 1 shift/reduce conflict.
		58	State 513 contains 3 shift/reduce conflicts.
		59	State 537 contains 1 shift/reduce conflict.
		60	State 562 contains 1 shift/reduce conflict.
		61	State 563 contains 1 shift/reduce conflict.
		62	State 564 contains 1 shift/reduce conflict.
		63	State 565 contains 1 shift/reduce conflict.
		64	State 630 contains 1 shift/reduce conflict.
		65	State 632 contains 1 shift/reduce conflict.
		66	State 649 contains 1 shift/reduce conflict.
		67	State 668 contains 1 shift/reduce conflict.
		68
		69
		70	Grammar
		71
		72	Number, Line, Rule
		73	1 282 file -> FILEMODE objects
		74	2 283 file -> CMDMODE cmd_objects
		75	3 289 cmd_objects -> cmd_objects cmd_object
		76	4 290 cmd_objects -> cmd_object
		77	5 293 cmd_object -> bus_range
		78	6 302 objects -> objects object
		79	7 303 objects -> object
		80	8 306 object -> chip_decl
		81	9 307 object -> components_decl
		82	10 308 object -> template_decl
		83	11 309 object -> joined_decl
		84	12 310 object -> nets_decl
		85	13 311 object -> rename_pins_block
		86	14 312 object -> global_generic_decl
		87	15 313 object -> vhdl_region
		88	16 314 object -> verilog_region
		89	17 315 object -> ahdl_region
		90	18 316 object -> /* empty */
		91	19 322 astring -> QUOTED_STRING
		92	20 323 astring -> TXT_STRING
		93	21 324 astring -> NUM_STRING
		94	22 329 chip_decl -> chip_id_decl chip_body
		95	23 331 chip_body -> BEGIN_TOK flex_chip_body
		96	24 332 chip_body -> ASSIGNED apex_chip_body
		97	25 338 flex_chip_body -> chip_info_lines pin_declarations pin_equivalences END end_item
		98	26 347 chip_id_decl -> CHIP astring
		99	27 372 chip_info_lines -> chip_info_lines chip_info_line
		100	28 373 chip_info_lines -> chip_info_line
		101	29 374 chip_info_lines -> /* empty */
		102	30 377 chip_info_line -> device_declaration
		103	31 378 chip_info_line -> route_flags_info
		104	32 379 chip_info_line -> routing_status
		105	33 380 chip_info_line -> chip_generic_decl
		106	34 382 device_declaration -> DEVICE '=' astring end_item
		107	35 387 pin_equivalences -> pin_equivalence pin_equivalences
		108	36 388 pin_equivalences -> pin_equivalence
		109	37 389 pin_equivalences -> /* empty */
		110	38 398 end_item -> ';'
		111	39 400 routing_status -> UNROUTED end_item
		112	40 404 route_flags_info -> ROUTE_FLAGS '=' route_flag_value end_item
		113	41 407 route_flag_value -> NUM_STRING
		114	42 415 pin_declarations -> pin_declarations pin_declaration
		115	43 416 pin_declarations -> pin_declaration
		116	44 417 pin_declarations -> /* empty */
		117	45 420 pin_declaration -> name_part ':' pin_rest end_item
		118	46 426 name_part -> netname
		119	47 437 pin_rest -> pin_dir pin_group '=' pin_ident vhdl_type_opt
		120	48 438 pin_rest -> UNROUTED
		121	49 439 pin_rest -> LOCATION '=' astring
		122	50 442 pin_dir -> PINDIR
		123	51 445 pin_group -> '(' NUM_STRING ')'
		124	52 446 pin_group -> /* empty */
		125	53 448 pin_ident -> netname
		126	54 452 apex_chip_body -> apex_device_declaration apex_info_lines
		127	55 455 apex_device_declaration -> TO AN astring apex_speed_grade
		128	56 460 apex_speed_grade -> '-' NUM_STRING
		129	57 471 apex_speed_grade -> /* empty */
		130	58 474 apex_info_lines -> apex_info_lines apex_info_line
		131	59 475 apex_info_lines -> apex_info_line
		132	60 477 apex_info_line -> GND ':' astring more_colons
		133	61 478 apex_info_line -> GND_RES_IO ':' astring more_colons
		134	62 479 apex_info_line -> GND_RES_IN ':' astring more_colons
		135	63 480 apex_info_line -> VCC ':' astring ':' NUM_STRING
		136	64 481 apex_info_line -> VCC ':' astring more_colons
		137	65 482 apex_info_line -> TXT_STRING ':' astring more_colons
		138	66 483 apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' astring ':'
		139	67 492 apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' astring ':'
		140	68 505 more_colons -> ':' more_colons
		141	69 506 more_colons -> ':'
		142	70 514 vhdl_type_opt -> ':' vhdl_type
		143	71 515 vhdl_type_opt -> /* empty */
		144	72 522 vhdl_type -> astring vhdl_type_default_value_opt
		145	73 533 vhdl_type -> astring '(' bus_range ')' vhdl_type_default_value_opt
		146	74 548 vhdl_type -> INTEGER vhdl_type_default_value_opt
		147	75 559 vhdl_type -> INTEGER RANGE simple_range_expr vhdl_type_default_value_opt
		148	76 571 vhdl_type -> NATURAL vhdl_type_default_value_opt
		149	77 582 vhdl_type -> NATURAL RANGE simple_range_expr vhdl_type_default_value_opt
		150	78 594 vhdl_type -> BOOLEAN vhdl_type_default_value_opt
		151	79 606 vhdl_type_default_value_opt -> ASSIGN bus_range
		152	80 607 vhdl_type_default_value_opt -> /* empty */
		153	81 613 bus_range -> expr1
		154	82 614 bus_range -> expr
		155	83 618 expr1 -> simple_range_expr
		156	84 621 expr1 -> QUOTED_STRING
		157	85 625 expr1 -> QUOTE astring QUOTE
		158	86 630 simple_range_expr -> expr TO expr
		159	87 634 simple_range_expr -> expr DOWNTO expr
		160	88 642 primary_expr -> '(' expr ')'
		161	89 646 primary_expr -> '~' expr
		162	90 650 primary_expr -> '-' expr
		163	91 655 primary_expr -> NUM_STRING
		164	92 659 primary_expr -> TXT_STRING
		165	93 663 primary_expr -> TRUE
		166	94 666 primary_expr -> FALSE
		167	95 671 mult_expr -> primary_expr
		168	96 675 mult_expr -> mult_expr '*' primary_expr
		169	97 679 mult_expr -> mult_expr '/' primary_expr
		170	98 683 mult_expr -> mult_expr '%' primary_expr
		171	99 687 mult_expr -> mult_expr TO_POW primary_expr
		172	100 694 add_expr -> mult_expr
		173	101 698 add_expr -> add_expr '+' mult_expr
		174	102 702 add_expr -> add_expr '-' mult_expr
		175	103 708 shift_expr -> add_expr
		176	104 712 shift_expr -> shift_expr SHL add_expr
		177	105 716 shift_expr -> shift_expr SHR add_expr
		178	106 723 relational_expr -> shift_expr
		179	107 727 relational_expr -> relational_expr '>' shift_expr
		180	108 731 relational_expr -> relational_expr '<' shift_expr
		181	109 738 equality_expr -> relational_expr
		182	110 742 equality_expr -> equality_expr EQ_EQ relational_expr
		183	111 746 equality_expr -> equality_expr N_EQ relational_expr
		184	112 753 and_expr -> equality_expr
		185	113 757 and_expr -> and_expr '&' equality_expr
		186	114 764 exor_expr -> and_expr
		187	115 768 exor_expr -> exor_expr '^' and_expr
		188	116 775 or_expr -> exor_expr
		189	117 779 or_expr -> or_expr '\|' or_expr
		190	118 786 logand_expr -> or_expr
		191	119 790 logand_expr -> logand_expr LOG_AND or_expr
		192	120 796 logor_expr -> logand_expr
		193	121 800 logor_expr -> logor_expr LOG_OR logand_expr
		194	122 807 cond_expr -> logor_expr '?' colon_expr
		195	123 814 colon_expr -> expr ':' expr
		196	124 819 expr -> cond_expr
		197	125 823 expr -> logor_expr
		198	126 834 @1 -> /* empty */
		199	127 834 pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins ')' end_item
		200	128 840 equivalent_pins -> equivalent_pin end_item equivalent_pins
		201	129 841 equivalent_pins -> equivalent_pin
		202	130 842 equivalent_pins -> /* empty */
		203	131 845 equivalent_pin -> astring
		204	132 855 vhdl_region -> VHDL vhdl_blocks END end_item
		205	133 860 vhdl_blocks -> vhdl_blocks vhdl_block
		206	134 861 vhdl_blocks -> vhdl_block
		207	135 865 vhdl_block -> vhdl_chip_decl
		208	136 866 vhdl_block -> vhdl_architecture
		209	137 867 vhdl_block -> vhdl_package_decl
		210	138 868 vhdl_block -> vhdl_library_decl
		211	139 869 vhdl_block -> vhdl_use_decl
		212	140 870 vhdl_block -> /* empty */
		213	141 876 @2 -> /* empty */
		214	142 876 vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item
		215	143 887 hdl_entityname_decl -> TXT_STRING
		216	144 906 vhdl_generic_decl_opt -> vhdl_generic_decl
		217	145 907 vhdl_generic_decl_opt -> /* empty */
		218	146 911 @3 -> /* empty */
		219	147 911 vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines ')' end_item
		220	148 922 vhdl_port_decl_opt -> vhdl_port_decl
		221	149 923 vhdl_port_decl_opt -> /* empty */
		222	150 926 vhdl_port_decl -> PORT '(' vhdl_port_list ')' end_item
		223	151 928 vhdl_port_list -> vhdl_port_list end_item vhdl_port_item
		224	152 929 vhdl_port_list -> vhdl_port_item
		225	153 930 vhdl_port_list -> /* empty */
		226	154 937 vhdl_port_item -> vhdl_name_list ':' pin_dir vhdl_type vhdl_assign_opt
		227	155 942 vhdl_name_list -> vhdl_name_list ',' hdl_name_part
		228	156 943 vhdl_name_list -> hdl_name_part
		229	157 948 hdl_name_part -> netname
		230	158 964 vhdl_assign_opt -> ASSIGN expr
		231	159 965 vhdl_assign_opt -> /* empty */
		232	160 973 vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item
		233	161 979 vhdl_architecture_declarations -> vhdl_architecture_declarations vhdl_architecture_decl
		234	162 980 vhdl_architecture_declarations -> vhdl_architecture_decl
		235	163 981 vhdl_architecture_declarations -> /* empty */
		236	164 984 vhdl_architecture_decl -> vhdl_component_decl
		237	165 985 vhdl_architecture_decl -> vhdl_constant_decl
		238	166 986 vhdl_architecture_decl -> vhdl_signal_decl
		239	167 987 vhdl_architecture_decl -> vhdl_configuration_decl
		240	168 993 vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END astring end_item
		241	169 997 package_name -> astring
		242	170 1000 vhdl_package_declarations -> vhdl_package_declarations vhdl_package_decl_item
		243	171 1001 vhdl_package_declarations -> vhdl_package_decl_item
		244	172 1002 vhdl_package_declarations -> /* empty */
		245	173 1005 vhdl_package_decl_item -> vhdl_component_decl
		246	174 1006 vhdl_package_decl_item -> vhdl_constant_decl
		247	175 1007 vhdl_package_decl_item -> vhdl_signal_decl
		248	176 1008 vhdl_package_decl_item -> vhdl_configuration_decl
		249	177 1014 vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item
		250	178 1022 hdl_compname_decl -> TXT_STRING
		251	179 1041 @4 -> /* empty */
		252	180 1041 vhdl_constant_decl -> CONSTANT @4 generic_defn_text end_item
		253	181 1049 @5 -> /* empty */
		254	182 1049 vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' vhdl_type end_item
		255	183 1061 hdl_signal_names -> hdl_signal_names ',' hdl_signal_name
		256	184 1062 hdl_signal_names -> hdl_signal_name
		257	185 1065 hdl_signal_name -> astring
		258	186 1082 vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' ';'
		259	187 1092 vhdl_architecture_body_items -> vhdl_architecture_body_items vhdl_architecture_body_item
		260	188 1093 vhdl_architecture_body_items -> vhdl_architecture_body_item
		261	189 1094 vhdl_architecture_body_items -> /* empty */
		262	190 1097 vhdl_architecture_body_item -> vhdl_concurrent_assignment
		263	191 1098 vhdl_architecture_body_item -> vhdl_component_instance
		264	192 1111 vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map vhdl_inst_port_map end_item
		265	193 1135 vhdl_inst_comp_binding -> TXT_STRING ':' TXT_STRING
		266	194 1165 @6 -> /* empty */
		267	195 1165 vhdl_inst_generic_map -> GENERIC MAP @6 '(' vhdl_gen_map_list ')'
		268	196 1175 vhdl_inst_generic_map -> /* empty */
		269	197 1178 vhdl_inst_port_map -> PORT MAP '(' vhdl_port_map_list ')'
		270	198 1179 vhdl_inst_port_map -> /* empty */
		271	199 1183 vhdl_gen_map_list -> vhdl_gen_map_list ',' vhdl_gen_map
		272	200 1184 vhdl_gen_map_list -> vhdl_gen_map
		273	201 1187 vhdl_gen_map -> astring CONNECTED bus_range
		274	202 1200 vhdl_port_map_list -> vhdl_port_map_list ',' vhdl_port_map
		275	203 1201 vhdl_port_map_list -> vhdl_port_map
		276	204 1206 vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED rename_new_name
		277	205 1243 vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED OPEN
		278	206 1272 vhdl_port_map -> rename_new_name vhdl_port_map_slice_opt
		279	207 1308 vhdl_port_map -> OPEN
		280	208 1335 vhdl_port_map_slice_opt -> '(' bus_range ')'
		281	209 1340 vhdl_port_map_slice_opt -> /* empty */
		282	210 1348 vhdl_concurrent_assignment -> astring SIG_ASSIGN astring end_item
		283	211 1392 vhdl_library_decl -> LIBRARY vhdl_library_list ';'
		284	212 1394 vhdl_library_list -> vhdl_library_name ',' vhdl_library_list
		285	213 1395 vhdl_library_list -> vhdl_library_name
		286	214 1398 vhdl_library_name -> astring
		287	215 1404 vhdl_use_decl -> USE vhdl_lib_members ';'
		288	216 1406 vhdl_lib_members -> vhdl_lib_member ',' vhdl_lib_members
		289	217 1407 vhdl_lib_members -> vhdl_lib_member
		290	218 1410 vhdl_lib_member -> astring '.' astring '.' vhdl_lib_member_select
		291	219 1411 vhdl_lib_member -> astring '.' vhdl_lib_member_select
		292	220 1415 vhdl_lib_member_select -> ALL
		293	221 1416 vhdl_lib_member_select -> astring
		294	222 1424 verilog_region -> VERILOG verilog_blocks END end_item
		295	223 1429 verilog_blocks -> verilog_blocks verilog_block
		296	224 1430 verilog_blocks -> verilog_block
		297	225 1434 verilog_block -> verilog_module_decl
		298	226 1435 verilog_block -> verilog_toplevel_decl
		299	227 1436 verilog_block -> /* empty */
		300	228 1452 verilog_module_header -> MODULE hdl_compname_decl verilog_port_list verilog_pindir_block
		301	229 1456 verilog_toplevel_decl -> verilog_module_header verilog_module_body ENDMODULE
		302	230 1458 verilog_module_decl -> verilog_module_header ENDMODULE
		303	231 1462 @7 -> /* empty */
		304	232 1462 verilog_port_list -> '(' verilog_ports ')' ';' @7 verilog_pindir_block
		305	233 1465 verilog_port_list -> /* empty */
		306	234 1467 verilog_ports -> verilog_ports ',' verilog_port
		307	235 1468 verilog_ports -> verilog_port
		308	236 1469 verilog_ports -> /* empty */
		309	237 1472 verilog_port -> hdl_name_part
		310	238 1474 verilog_bus_expr -> '[' expr ']'
		311	239 1477 verilog_bus_expr -> '[' expr ':' expr ']'
		312	240 1480 verilog_bus_expr -> /* empty */
		313	241 1486 verilog_module_body -> verilog_wires_block verilog_module_instance_block
		314	242 1491 verilog_pindir_block -> verilog_pindir_block verilog_pindir_decl
		315	243 1492 verilog_pindir_block -> verilog_pindir_decl
		316	244 1493 verilog_pindir_block -> /* empty */
		317	245 1497 @8 -> /* empty */
		318	246 1497 verilog_pindir_decl -> pin_dir @8 verilog_bus_expr hdl_signal_names ';'
		319	247 1505 verilog_wires_block -> verilog_wires_decl verilog_wires_block
		320	248 1506 verilog_wires_block -> verilog_wires_decl
		321	249 1507 verilog_wires_block -> /* empty */
		322	250 1511 verilog_wires_decl -> verilog_wire_start verilog_bus_expr hdl_signal_names verilog_wire_end
		323	251 1516 verilog_wire_start -> WIRE
		324	252 1519 verilog_wire_end -> ';'
		325	253 1525 verilog_module_instance_block -> verilog_module_instances
		326	254 1527 verilog_module_instances -> verilog_module_instances verilog_module_instance
		327	255 1528 verilog_module_instances -> verilog_module_instance
		328	256 1529 verilog_module_instances -> /* empty */
		329	257 1532 verilog_module_instance -> astring astring '(' verilog_port_map_list ')' ';'
		330	258 1566 verilog_port_map_list -> verilog_port_maps
		331	259 1566 verilog_port_map_list -> /* empty */
		332	260 1569 verilog_port_maps -> verilog_port_maps ',' verilog_port_map
		333	261 1570 verilog_port_maps -> verilog_port_map
		334	262 1573 verilog_port_map -> '.' astring '(' astring verilog_bus_expr ')'
		335	263 1616 verilog_port_map -> '.' astring '(' ')'
		336	264 1649 @9 -> /* empty */
		337	265 1649 global_generic_decl -> GENERIC @9 generic_defn_lines END end_item
		338	266 1655 @10 -> /* empty */
		339	267 1655 chip_generic_decl -> GENERIC @10 generic_defn_lines END end_item
		340	268 1663 generic_defn_lines -> generic_defn_lines end_item generic_defn_text
		341	269 1664 generic_defn_lines -> generic_defn_text
		342	270 1665 generic_defn_lines -> /* empty */
		343	271 1669 generic_const_opt -> CONSTANT
		344	272 1670 generic_const_opt -> /* empty */
		345	273 1673 generic_pindir_opt -> PINDIR
		346	274 1674 generic_pindir_opt -> /* empty */
		347	275 1678 generic_defn_text -> generic_const_opt generic_defn_name_list ':' generic_pindir_opt generic_defn_type
		348	276 1680 generic_defn_name_list -> generic_defn_name_list ',' generic_defn_name
		349	277 1681 generic_defn_name_list -> generic_defn_name
		350	278 1683 generic_defn_name -> astring
		351	279 1687 generic_defn_type -> INTEGER opt_integer
		352	280 1702 generic_defn_type -> BOOLEAN opt_integer
		353	281 1717 generic_defn_type -> INTEGER RANGE opt_bus_range
		354	282 1732 @11 -> /* empty */
		355	283 1732 generic_defn_type -> DECLARATION @11 assign_words
		356	284 1748 @12 -> /* empty */
		357	285 1748 generic_defn_type -> INSTANCE @12 assign_words
		358	286 1762 @13 -> /* empty */
		359	287 1762 generic_defn_type -> STRING @13 assign_words
		360	288 1776 @14 -> /* empty */
		361	289 1776 generic_defn_type -> ENV_STRING @14 assign_words
		362	290 1793 generic_defn_type -> ATTRIBUTE opt_integer
		363	291 1810 opt_integer -> ASSIGN expr
		364	292 1811 opt_integer -> /* empty */
		365	293 1814 opt_bus_range -> ASSIGN bus_range
		366	294 1815 opt_bus_range -> /* empty */
		367	295 1822 assign_words -> ASSIGN several_words
		368	296 1823 assign_words -> /* empty */
		369	297 1827 several_words -> word several_words
		370	298 1828 several_words -> word
		371	299 1832 word -> astring
		372	300 1837 components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines END end_item
		373	301 1844 comp_defn_lines -> comp_defn_lines comp_defn_line
		374	302 1845 comp_defn_lines -> comp_defn_line
		375	303 1846 comp_defn_lines -> /* empty */
		376	304 1849 comp_defn_line -> chip_ident ':' chip_name chip_type chip_value end_item
		377	305 1852 chip_ident -> astring
		378	306 1855 chip_name -> astring
		379	307 1858 chip_type -> astring
		380	308 1861 chip_value -> astring
		381	309 1868 joined_decl -> JOINED_NETS BEGIN_TOK join_decls END end_item
		382	310 1874 join_decls -> join_decls join_decl
		383	311 1875 join_decls -> join_decl
		384	312 1876 join_decls -> /* empty */
		385	313 1883 join_decl -> alias_part root_net '=' '(' joined_nets ')' end_item
		386	314 1884 @15 -> /* empty */
		387	315 1884 join_decl -> CONN astring astring @15 end_item
		388	316 1889 join_decl -> VHDL_CONN vhdl_concurrent_assignment
		389	317 1894 alias_part -> ALIAS
		390	318 1897 alias_part -> JUMPER
		391	319 1898 alias_part -> /* empty */
		392	320 1901 root_net -> netname
		393	321 1935 joined_nets -> joined_nets joined_net
		394	322 1936 joined_nets -> joined_net
		395	323 1939 joined_net -> single_net end_item
		396	324 1940 joined_net -> jumper_node end_item
		397	325 1943 single_net -> netname
		398	326 1963 jumper_node -> netname '(' astring ')'
		399	327 2008 rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls END end_item
		400	328 2015 rename_pin_decls -> rename_pin_decls rename_pin_decl
		401	329 2016 rename_pin_decls -> rename_pin_decl
		402	330 2021 rename_pin_decl -> rename_new_name '=' '(' rename_pin_items ')' end_item
		403	331 2023 rename_new_name -> netname
		404	332 2025 rename_new_name -> netname '(' bus_range ')'
		405	333 2034 rename_pin_items -> rename_pin_items rename_pin_item
		406	334 2035 rename_pin_items -> rename_pin_item
		407	335 2038 rename_pin_item -> astring '.' astring end_item
		408	336 2041 rename_pin_item -> /* empty */
		409	337 2051 @16 -> /* empty */
		410	338 2051 nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block END end_item
		411	339 2059 connection_block -> connection_block connection_block_item
		412	340 2060 connection_block -> connection_block_item
		413	341 2063 connection_block_item -> routed_decl
		414	342 2064 connection_block_item -> unrouted_decl
		415	343 2065 connection_block_item -> named_decl
		416	344 2066 connection_block_item -> conn_decls
		417	345 2067 connection_block_item -> /* empty */
		418	346 2071 routed_decl -> ROUTED
		419	347 2074 unrouted_decl -> UNROUTED
		420	348 2077 named_decl -> NAMED
		421	349 2082 conn_decls -> conn_decls conn_decl
		422	350 2083 conn_decls -> conn_decl
		423	351 2087 @17 -> /* empty */
		424	352 2087 conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN @17 end_item
		425	353 2092 conn_ident -> netname
		426	354 2098 conn_name -> astring
		427	355 2102 last_route_status -> astring
		428	356 2105 nodelist -> nodelist net_node
		429	357 2106 nodelist -> net_node
		430	358 2107 nodelist -> /* empty */
		431	359 2110 net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir node_group end_item
		432	360 2119 force_pin_dir -> PINDIR
		433	361 2128 force_pin_dir -> /* empty */
		434	362 2137 skt_id -> astring
		435	363 2141 node_id -> netname
		436	364 2148 fix_loc_part -> FIX_LOCATION
		437	365 2150 fix_loc_part -> /* empty */
		438	366 2154 node_group -> '(' NUM_STRING ')'
		439	367 2155 node_group -> /* empty */
		440	368 2163 netname -> VCC
		441	369 2164 netname -> GND
		442	370 2165 netname -> astring
		443	371 2180 template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences END end_item
		444	372 2201 template_id_decl -> TEMPLATE template_name
		445	373 2203 template_name -> astring
		446	374 2209 template_info_lines -> template_info_lines template_info_line
		447	375 2210 template_info_lines -> template_info_line
		448	376 2213 template_info_line -> chip_generic_decl
		449	377 2214 template_info_line -> alias_to_another_template
		450	378 2215 template_info_line -> /* empty */
		451	379 2219 alias_to_another_template -> ALIAS astring end_item
		452	380 2250 ahdl_region -> AHDL ahdl_chip_decls END end_item
		453	381 2255 ahdl_chip_decls -> ahdl_chip_decl ahdl_chip_decls
		454	382 2256 ahdl_chip_decls -> ahdl_chip_decl
		455	383 2259 ahdl_chip_decl -> ahdl_entityname_decl
		456	384 2260 ahdl_chip_decl -> ahdl_port_decl
		457	385 2261 ahdl_chip_decl -> /* empty */
		458	386 2264 ahdl_entityname_decl -> SUBDESIGN TXT_STRING
		459	387 2281 ahdl_port_decl -> '(' ahdl_port_list ')'
		460	388 2283 ahdl_port_list -> ahdl_port_list end_item ahdl_port_item
		461	389 2284 ahdl_port_list -> ahdl_port_item
		462	390 2285 ahdl_port_list -> /* empty */
		463	391 2292 ahdl_port_item -> ahdl_name_list ':' pin_dir
		464	392 2301 ahdl_name_list -> ahdl_name_list ',' ahdl_name_part
		465	393 2302 ahdl_name_list -> ahdl_name_part
		466	394 2305 ahdl_name_part -> astring
		467
		468
		469	Terminals, with rules where they appear
		470
		471	$ (-1)
		472	'%' (37) 98
		473	'&' (38) 113
		474	'(' (40) 51 73 88 127 147 150 186 195 197 208 232 257 262 263 313 326
		475	330 332 359 366 387
		476	')' (41) 51 73 88 127 147 150 186 195 197 208 232 257 262 263 313 326
		477	330 332 359 366 387
		478	'*' (42) 96
		479	'+' (43) 101
		480	',' (44) 155 183 199 202 212 216 234 260 276 392
		481	'-' (45) 56 90 102
		482	'.' (46) 186 218 219 262 263 335
		483	'/' (47) 97
		484	':' (58) 45 60 61 62 63 64 65 66 67 68 69 70 123 154 182 186 193 239
		485	275 304 391
		486	';' (59) 38 186 211 215 232 246 252 257
		487	'<' (60) 108
		488	'=' (61) 34 40 47 49 313 330
		489	'>' (62) 107
		490	'?' (63) 122
		491	'[' (91) 67 238 239
		492	']' (93) 67 238 239
		493	'^' (94) 115
		494	'\|' (124) 117
		495	'~' (126) 89
		496	error (256)
		497	FILEMODE (257) 1
		498	CMDMODE (258) 2
		499	CHIP (259) 26
		500	BEGIN_TOK (260) 23 160 300 309 327 338 371
		501	END (261) 25 132 142 160 168 177 222 265 267 300 309 327 338 371 380
		502	DEVICE (262) 34
		503	COMPONENTS (263) 300
		504	WIRED_NETS (264) 338
		505	CONN (265) 315 352
		506	END_CONN (266) 352
		507	JOINED_NETS (267) 309
		508	ALIAS (268) 317 379
		509	JUMPER (269) 318
		510	RENAME_PINS (270) 327
		511	TEMPLATE (271) 372
		512	FIX_LOCATION (272) 364
		513	LOCATION (273) 49
		514	UNROUTED (274) 39 48 347
		515	ROUTED (275) 346
		516	NAMED (276) 348
		517	ASSIGN (277) 79 158 291 293 295
		518	SIG_ASSIGN (278) 210
		519	CONNECTED (279) 201 204 205
		520	ROUTE_FLAGS (280) 40
		521	DECLARATION (281) 283
		522	INSTANCE (282) 285
		523	AHDL (283) 380
		524	VERILOG (284) 222
		525	SUBDESIGN (285) 386
		526	OPEN (286) 205 207
		527	BOOLEAN (287) 78 280
		528	TRUE (288) 93
		529	FALSE (289) 94
		530	TO (290) 55 86
		531	DOWNTO (291) 87
		532	GENERIC (292) 147 195 265 267
		533	RANGE (293) 75 77 281
		534	INTEGER (294) 74 75 279 281
		535	NATURAL (295) 76 77
		536	SIGNAL (296) 182
		537	CONSTANT (297) 180 271
		538	VHDL (298) 132
		539	PORT (299) 150 197
		540	ENTITY (300) 142 186
		541	IS (301) 142 160 168
		542	COMPONENT (302) 177
		543	MAP (303) 195 197
		544	ARCHITECTURE (304) 160
		545	OF (305) 160
		546	EQUIVALENT (306) 127
		547	TO_POW (307) 99
		548	MODULE (308) 228
		549	ENDMODULE (309) 229 230
		550	LIBRARY (310) 211
		551	USE (311) 186 215
		552	ALL (312) 220
		553	PACKAGE (313) 168
		554	FOR (314) 186
		555	PROCESS (315)
		556	ASSIGNED (316) 24
		557	AN (317) 55
		558	WIRE (318) 251
		559	GND (319) 60 369
		560	GND_RES_IO (320) 61
		561	GND_RES_IN (321) 62
		562	VCC (322) 63 64 368
		563	ATTRIBUTE (323) 290
		564	ENV_STRING (324) 289
		565	STRING (325) 287
		566	SHL (326) 104
		567	SHR (327) 105
		568	EQ_EQ (328) 110
		569	N_EQ (329) 111
		570	LOG_AND (330) 119
		571	LOG_OR (331) 121
		572	QUOTE (332) 85
		573	VHDL_CONN (333) 316
		574	QUOTED_STRING (334) 19 84
		575	TXT_STRING (335) 20 65 66 67 92 142 143 178 193 386
		576	NUM_STRING (336) 21 41 51 56 63 91 366
		577	PINDIR (337) 50 66 67 273 360
		578	UMINUS (338)
		579
		580
		581	Nonterminals, with rules where they appear
		582
		583	file (106)
		584	on left: 1 2
		585	cmd_objects (107)
		586	on left: 3 4, on right: 2 3
		587	cmd_object (108)
		588	on left: 5, on right: 3 4
		589	objects (109)
		590	on left: 6 7, on right: 1 6
		591	object (110)
		592	on left: 8 9 10 11 12 13 14 15 16 17 18, on right: 6 7
		593	astring (111)
		594	on left: 19 20 21, on right: 26 34 49 55 60 61 62 63 64 65 66 67
		595	72 73 85 131 160 168 169 185 186 201 204 205 210 214 218 219 221
		596	257 262 263 278 299 305 306 307 308 315 326 335 354 355 362 370
		597	373 379 394
		598	chip_decl (112)
		599	on left: 22, on right: 8
		600	chip_body (113)
		601	on left: 23 24, on right: 22
		602	flex_chip_body (114)
		603	on left: 25, on right: 23
		604	chip_id_decl (115)
		605	on left: 26, on right: 22
		606	chip_info_lines (116)
		607	on left: 27 28 29, on right: 25 27
		608	chip_info_line (117)
		609	on left: 30 31 32 33, on right: 27 28
		610	device_declaration (118)
		611	on left: 34, on right: 30
		612	pin_equivalences (119)
		613	on left: 35 36 37, on right: 25 35 371
		614	end_item (120)
		615	on left: 38, on right: 25 34 39 40 45 127 128 132 142 147 150 151
		616	160 168 177 180 182 192 210 222 265 267 268 300 304 309 313 315
		617	323 324 327 330 335 338 352 359 371 379 380 388
		618	routing_status (121)
		619	on left: 39, on right: 32
		620	route_flags_info (122)
		621	on left: 40, on right: 31
		622	route_flag_value (123)
		623	on left: 41, on right: 40
		624	pin_declarations (124)
		625	on left: 42 43 44, on right: 25 42 371
		626	pin_declaration (125)
		627	on left: 45, on right: 42 43
		628	name_part (126)
		629	on left: 46, on right: 45
		630	pin_rest (127)
		631	on left: 47 48 49, on right: 45
		632	pin_dir (128)
		633	on left: 50, on right: 47 154 246 391
		634	pin_group (129)
		635	on left: 51 52, on right: 47
		636	pin_ident (130)
		637	on left: 53, on right: 47
		638	apex_chip_body (131)
		639	on left: 54, on right: 24
		640	apex_device_declaration (132)
		641	on left: 55, on right: 54
		642	apex_speed_grade (133)
		643	on left: 56 57, on right: 55
		644	apex_info_lines (134)
		645	on left: 58 59, on right: 54 58
		646	apex_info_line (135)
		647	on left: 60 61 62 63 64 65 66 67, on right: 58 59
		648	more_colons (136)
		649	on left: 68 69, on right: 60 61 62 64 65 68
		650	vhdl_type_opt (137)
		651	on left: 70 71, on right: 47
		652	vhdl_type (138)
		653	on left: 72 73 74 75 76 77 78, on right: 70 154 182
		654	vhdl_type_default_value_opt (139)
		655	on left: 79 80, on right: 72 73 74 75 76 77 78
		656	bus_range (140)
		657	on left: 81 82, on right: 5 73 79 201 208 293 332
		658	expr1 (141)
		659	on left: 83 84 85, on right: 81
		660	simple_range_expr (142)
		661	on left: 86 87, on right: 75 77 83
		662	primary_expr (143)
		663	on left: 88 89 90 91 92 93 94, on right: 95 96 97 98 99
		664	mult_expr (144)
		665	on left: 95 96 97 98 99, on right: 96 97 98 99 100 101 102
		666	add_expr (145)
		667	on left: 100 101 102, on right: 101 102 103 104 105
		668	shift_expr (146)
		669	on left: 103 104 105, on right: 104 105 106 107 108
		670	relational_expr (147)
		671	on left: 106 107 108, on right: 107 108 109 110 111
		672	equality_expr (148)
		673	on left: 109 110 111, on right: 110 111 112 113
		674	and_expr (149)
		675	on left: 112 113, on right: 113 114 115
		676	exor_expr (150)
		677	on left: 114 115, on right: 115 116
		678	or_expr (151)
		679	on left: 116 117, on right: 117 118 119
		680	logand_expr (152)
		681	on left: 118 119, on right: 119 120 121
		682	logor_expr (153)
		683	on left: 120 121, on right: 121 122 125
		684	cond_expr (154)
		685	on left: 122, on right: 124
		686	colon_expr (155)
		687	on left: 123, on right: 122
		688	expr (156)
		689	on left: 124 125, on right: 67 82 86 87 88 89 90 123 158 238 239
		690	291
		691	pin_equivalence (157)
		692	on left: 127, on right: 35 36
		693	@1 (158)
		694	on left: 126, on right: 127
		695	equivalent_pins (159)
		696	on left: 128 129 130, on right: 127 128
		697	equivalent_pin (160)
		698	on left: 131, on right: 128 129
		699	vhdl_region (161)
		700	on left: 132, on right: 15
		701	vhdl_blocks (162)
		702	on left: 133 134, on right: 132 133
		703	vhdl_block (163)
		704	on left: 135 136 137 138 139 140, on right: 133 134
		705	vhdl_chip_decl (164)
		706	on left: 142, on right: 135
		707	@2 (165)
		708	on left: 141, on right: 142
		709	hdl_entityname_decl (166)
		710	on left: 143, on right: 142
		711	vhdl_generic_decl_opt (167)
		712	on left: 144 145, on right: 142 177
		713	vhdl_generic_decl (168)
		714	on left: 147, on right: 144
		715	@3 (169)
		716	on left: 146, on right: 147
		717	vhdl_port_decl_opt (170)
		718	on left: 148 149, on right: 142 177
		719	vhdl_port_decl (171)
		720	on left: 150, on right: 148
		721	vhdl_port_list (172)
		722	on left: 151 152 153, on right: 150 151
		723	vhdl_port_item (173)
		724	on left: 154, on right: 151 152
		725	vhdl_name_list (174)
		726	on left: 155 156, on right: 154 155
		727	hdl_name_part (175)
		728	on left: 157, on right: 155 156 237
		729	vhdl_assign_opt (176)
		730	on left: 158 159, on right: 154
		731	vhdl_architecture (177)
		732	on left: 160, on right: 136
		733	vhdl_architecture_declarations (178)
		734	on left: 161 162 163, on right: 160 161
		735	vhdl_architecture_decl (179)
		736	on left: 164 165 166 167, on right: 161 162
		737	vhdl_package_decl (180)
		738	on left: 168, on right: 137
		739	package_name (181)
		740	on left: 169, on right: 168
		741	vhdl_package_declarations (182)
		742	on left: 170 171 172, on right: 168 170
		743	vhdl_package_decl_item (183)
		744	on left: 173 174 175 176, on right: 170 171
		745	vhdl_component_decl (184)
		746	on left: 177, on right: 164 173
		747	hdl_compname_decl (185)
		748	on left: 178, on right: 177 228
		749	vhdl_constant_decl (186)
		750	on left: 180, on right: 165 174
		751	@4 (187)
		752	on left: 179, on right: 180
		753	vhdl_signal_decl (188)
		754	on left: 182, on right: 166 175
		755	@5 (189)
		756	on left: 181, on right: 182
		757	hdl_signal_names (190)
		758	on left: 183 184, on right: 182 183 246 250
		759	hdl_signal_name (191)
		760	on left: 185, on right: 183 184
		761	vhdl_configuration_decl (192)
		762	on left: 186, on right: 167 176
		763	vhdl_architecture_body_items (193)
		764	on left: 187 188 189, on right: 160 187
		765	vhdl_architecture_body_item (194)
		766	on left: 190 191, on right: 187 188
		767	vhdl_component_instance (195)
		768	on left: 192, on right: 191
		769	vhdl_inst_comp_binding (196)
		770	on left: 193, on right: 192
		771	vhdl_inst_generic_map (197)
		772	on left: 195 196, on right: 192
		773	@6 (198)
		774	on left: 194, on right: 195
		775	vhdl_inst_port_map (199)
		776	on left: 197 198, on right: 192
		777	vhdl_gen_map_list (200)
		778	on left: 199 200, on right: 195 199
		779	vhdl_gen_map (201)
		780	on left: 201, on right: 199 200
		781	vhdl_port_map_list (202)
		782	on left: 202 203, on right: 197 202
		783	vhdl_port_map (203)
		784	on left: 204 205 206 207, on right: 202 203
		785	vhdl_port_map_slice_opt (204)
		786	on left: 208 209, on right: 204 205 206
		787	vhdl_concurrent_assignment (205)
		788	on left: 210, on right: 190 316
		789	vhdl_library_decl (206)
		790	on left: 211, on right: 138
		791	vhdl_library_list (207)
		792	on left: 212 213, on right: 211 212
		793	vhdl_library_name (208)
		794	on left: 214, on right: 212 213
		795	vhdl_use_decl (209)
		796	on left: 215, on right: 139
		797	vhdl_lib_members (210)
		798	on left: 216 217, on right: 215 216
		799	vhdl_lib_member (211)
		800	on left: 218 219, on right: 216 217
		801	vhdl_lib_member_select (212)
		802	on left: 220 221, on right: 186 218 219
		803	verilog_region (213)
		804	on left: 222, on right: 16
		805	verilog_blocks (214)
		806	on left: 223 224, on right: 222 223
		807	verilog_block (215)
		808	on left: 225 226 227, on right: 223 224
		809	verilog_module_header (216)
		810	on left: 228, on right: 229 230
		811	verilog_toplevel_decl (217)
		812	on left: 229, on right: 226
		813	verilog_module_decl (218)
		814	on left: 230, on right: 225
		815	verilog_port_list (219)
		816	on left: 232 233, on right: 228
		817	@7 (220)
		818	on left: 231, on right: 232
		819	verilog_ports (221)
		820	on left: 234 235 236, on right: 232 234
		821	verilog_port (222)
		822	on left: 237, on right: 234 235
		823	verilog_bus_expr (223)
		824	on left: 238 239 240, on right: 246 250 262
		825	verilog_module_body (224)
		826	on left: 241, on right: 229
		827	verilog_pindir_block (225)
		828	on left: 242 243 244, on right: 228 232 242
		829	verilog_pindir_decl (226)
		830	on left: 246, on right: 242 243
		831	@8 (227)
		832	on left: 245, on right: 246
		833	verilog_wires_block (228)
		834	on left: 247 248 249, on right: 241 247
		835	verilog_wires_decl (229)
		836	on left: 250, on right: 247 248
		837	verilog_wire_start (230)
		838	on left: 251, on right: 250
		839	verilog_wire_end (231)
		840	on left: 252, on right: 250
		841	verilog_module_instance_block (232)
		842	on left: 253, on right: 241
		843	verilog_module_instances (233)
		844	on left: 254 255 256, on right: 253 254
		845	verilog_module_instance (234)
		846	on left: 257, on right: 254 255
		847	verilog_port_map_list (235)
		848	on left: 258 259, on right: 257
		849	verilog_port_maps (236)
		850	on left: 260 261, on right: 258 260
		851	verilog_port_map (237)
		852	on left: 262 263, on right: 260 261
		853	global_generic_decl (238)
		854	on left: 265, on right: 14
		855	@9 (239)
		856	on left: 264, on right: 265
		857	chip_generic_decl (240)
		858	on left: 267, on right: 33 376
		859	@10 (241)
		860	on left: 266, on right: 267
		861	generic_defn_lines (242)
		862	on left: 268 269 270, on right: 147 265 267 268
		863	generic_const_opt (243)
		864	on left: 271 272, on right: 275
		865	generic_pindir_opt (244)
		866	on left: 273 274, on right: 275
		867	generic_defn_text (245)
		868	on left: 275, on right: 180 268 269
		869	generic_defn_name_list (246)
		870	on left: 276 277, on right: 275 276
		871	generic_defn_name (247)
		872	on left: 278, on right: 276 277
		873	generic_defn_type (248)
		874	on left: 279 280 281 283 285 287 289 290, on right: 275
		875	@11 (249)
		876	on left: 282, on right: 283
		877	@12 (250)
		878	on left: 284, on right: 285
		879	@13 (251)
		880	on left: 286, on right: 287
		881	@14 (252)
		882	on left: 288, on right: 289
		883	opt_integer (253)
		884	on left: 291 292, on right: 279 280 290
		885	opt_bus_range (254)
		886	on left: 293 294, on right: 281
		887	assign_words (255)
		888	on left: 295 296, on right: 283 285 287 289
		889	several_words (256)
		890	on left: 297 298, on right: 295 297
		891	word (257)
		892	on left: 299, on right: 297 298
		893	components_decl (258)
		894	on left: 300, on right: 9
		895	comp_defn_lines (259)
		896	on left: 301 302 303, on right: 300 301
		897	comp_defn_line (260)
		898	on left: 304, on right: 301 302
		899	chip_ident (261)
		900	on left: 305, on right: 304
		901	chip_name (262)
		902	on left: 306, on right: 304
		903	chip_type (263)
		904	on left: 307, on right: 304
		905	chip_value (264)
		906	on left: 308, on right: 304
		907	joined_decl (265)
		908	on left: 309, on right: 11
		909	join_decls (266)
		910	on left: 310 311 312, on right: 309 310
		911	join_decl (267)
		912	on left: 313 315 316, on right: 310 311
		913	@15 (268)
		914	on left: 314, on right: 315
		915	alias_part (269)
		916	on left: 317 318 319, on right: 313
		917	root_net (270)
		918	on left: 320, on right: 313
		919	joined_nets (271)
		920	on left: 321 322, on right: 313 321
		921	joined_net (272)
		922	on left: 323 324, on right: 321 322
		923	single_net (273)
		924	on left: 325, on right: 323
		925	jumper_node (274)
		926	on left: 326, on right: 324
		927	rename_pins_block (275)
		928	on left: 327, on right: 13
		929	rename_pin_decls (276)
		930	on left: 328 329, on right: 327 328
		931	rename_pin_decl (277)
		932	on left: 330, on right: 328 329
		933	rename_new_name (278)
		934	on left: 331 332, on right: 204 206 330
		935	rename_pin_items (279)
		936	on left: 333 334, on right: 330 333
		937	rename_pin_item (280)
		938	on left: 335 336, on right: 333 334
		939	nets_decl (281)
		940	on left: 338, on right: 12
		941	@16 (282)
		942	on left: 337, on right: 338
		943	connection_block (283)
		944	on left: 339 340, on right: 338 339
		945	connection_block_item (284)
		946	on left: 341 342 343 344 345, on right: 339 340
		947	routed_decl (285)
		948	on left: 346, on right: 341
		949	unrouted_decl (286)
		950	on left: 347, on right: 342
		951	named_decl (287)
		952	on left: 348, on right: 343
		953	conn_decls (288)
		954	on left: 349 350, on right: 344 349
		955	conn_decl (289)
		956	on left: 352, on right: 349 350
		957	@17 (290)
		958	on left: 351, on right: 352
		959	conn_ident (291)
		960	on left: 353, on right: 352
		961	conn_name (292)
		962	on left: 354, on right: 352
		963	last_route_status (293)
		964	on left: 355, on right: 352
		965	nodelist (294)
		966	on left: 356 357 358, on right: 352 356
		967	net_node (295)
		968	on left: 359, on right: 356 357
		969	force_pin_dir (296)
		970	on left: 360 361, on right: 359
		971	skt_id (297)
		972	on left: 362, on right: 359
		973	node_id (298)
		974	on left: 363, on right: 359
		975	fix_loc_part (299)
		976	on left: 364 365, on right: 359
		977	node_group (300)
		978	on left: 366 367, on right: 359
		979	netname (301)
		980	on left: 368 369 370, on right: 46 53 157 320 325 326 331 332 353
		981	363
		982	template_decl (302)
		983	on left: 371, on right: 10
		984	template_id_decl (303)
		985	on left: 372, on right: 371
		986	template_name (304)
		987	on left: 373, on right: 372
		988	template_info_lines (305)
		989	on left: 374 375, on right: 371 374
		990	template_info_line (306)
		991	on left: 376 377 378, on right: 374 375
		992	alias_to_another_template (307)
		993	on left: 379, on right: 377
		994	ahdl_region (308)
		995	on left: 380, on right: 17
		996	ahdl_chip_decls (309)
		997	on left: 381 382, on right: 380 381
		998	ahdl_chip_decl (310)
		999	on left: 383 384 385, on right: 381 382
		1000	ahdl_entityname_decl (311)
		1001	on left: 386, on right: 383
		1002	ahdl_port_decl (312)
		1003	on left: 387, on right: 384
		1004	ahdl_port_list (313)
		1005	on left: 388 389 390, on right: 387 388
		1006	ahdl_port_item (314)
		1007	on left: 391, on right: 388 389
		1008	ahdl_name_list (315)
		1009	on left: 392 393, on right: 391 392
		1010	ahdl_name_part (316)
		1011	on left: 394, on right: 392 393
		1012
		1013
		1014	state 0
		1015
		1016	FILEMODE shift, and go to state 1
		1017	CMDMODE shift, and go to state 2
		1018
		1019	file go to state 698
		1020
		1021
		1022
		1023	state 1
		1024
		1025	file -> FILEMODE . objects (rule 1)
		1026
		1027	CHIP shift, and go to state 3
		1028	COMPONENTS shift, and go to state 4
		1029	WIRED_NETS shift, and go to state 5
		1030	JOINED_NETS shift, and go to state 6
		1031	RENAME_PINS shift, and go to state 7
		1032	TEMPLATE shift, and go to state 8
		1033	AHDL shift, and go to state 9
		1034	VERILOG shift, and go to state 10
		1035	GENERIC shift, and go to state 11
		1036	VHDL shift, and go to state 12
		1037
		1038	CHIP [reduce using rule 18 (object)]
		1039	COMPONENTS [reduce using rule 18 (object)]
		1040	WIRED_NETS [reduce using rule 18 (object)]
		1041	JOINED_NETS [reduce using rule 18 (object)]
		1042	RENAME_PINS [reduce using rule 18 (object)]
		1043	TEMPLATE [reduce using rule 18 (object)]
		1044	AHDL [reduce using rule 18 (object)]
		1045	VERILOG [reduce using rule 18 (object)]
		1046	GENERIC [reduce using rule 18 (object)]
		1047	VHDL [reduce using rule 18 (object)]
		1048	$default reduce using rule 18 (object)
		1049
		1050	objects go to state 13
		1051	object go to state 14
		1052	chip_decl go to state 15
		1053	chip_id_decl go to state 16
		1054	vhdl_region go to state 17
		1055	verilog_region go to state 18
		1056	global_generic_decl go to state 19
		1057	components_decl go to state 20
		1058	joined_decl go to state 21
		1059	rename_pins_block go to state 22
		1060	nets_decl go to state 23
		1061	template_decl go to state 24
		1062	template_id_decl go to state 25
		1063	ahdl_region go to state 26
		1064
		1065
		1066
		1067	state 2
		1068
		1069	file -> CMDMODE . cmd_objects (rule 2)
		1070
		1071	TRUE shift, and go to state 27
		1072	FALSE shift, and go to state 28
		1073	QUOTE shift, and go to state 29
		1074	QUOTED_STRING shift, and go to state 30
		1075	TXT_STRING shift, and go to state 31
		1076	NUM_STRING shift, and go to state 32
		1077	'~' shift, and go to state 33
		1078	'(' shift, and go to state 34
		1079	'-' shift, and go to state 35
		1080
		1081	cmd_objects go to state 36
		1082	cmd_object go to state 37
		1083	bus_range go to state 38
		1084	expr1 go to state 39
		1085	simple_range_expr go to state 40
		1086	primary_expr go to state 41
		1087	mult_expr go to state 42
		1088	add_expr go to state 43
		1089	shift_expr go to state 44
		1090	relational_expr go to state 45
		1091	equality_expr go to state 46
		1092	and_expr go to state 47
		1093	exor_expr go to state 48
		1094	or_expr go to state 49
		1095	logand_expr go to state 50
		1096	logor_expr go to state 51
		1097	cond_expr go to state 52
		1098	expr go to state 53
		1099
		1100
		1101
		1102	state 3
		1103
		1104	chip_id_decl -> CHIP . astring (rule 26)
		1105
		1106	QUOTED_STRING shift, and go to state 54
		1107	TXT_STRING shift, and go to state 55
		1108	NUM_STRING shift, and go to state 56
		1109
		1110	astring go to state 57
		1111
		1112
		1113
		1114	state 4
		1115
		1116	components_decl -> COMPONENTS . BEGIN_TOK comp_defn_lines END end_item (rule 300)
		1117
		1118	BEGIN_TOK shift, and go to state 58
		1119
		1120
		1121
		1122	state 5
		1123
		1124	nets_decl -> WIRED_NETS . @16 BEGIN_TOK connection_block END end_item (rule 338)
		1125
		1126	$default reduce using rule 337 (@16)
		1127
		1128	@16 go to state 59
		1129
		1130
		1131
		1132	state 6
		1133
		1134	joined_decl -> JOINED_NETS . BEGIN_TOK join_decls END end_item (rule 309)
		1135
		1136	BEGIN_TOK shift, and go to state 60
		1137
		1138
		1139
		1140	state 7
		1141
		1142	rename_pins_block -> RENAME_PINS . BEGIN_TOK rename_pin_decls END end_item (rule 327)
		1143
		1144	BEGIN_TOK shift, and go to state 61
		1145
		1146
		1147
		1148	state 8
		1149
		1150	template_id_decl -> TEMPLATE . template_name (rule 372)
		1151
		1152	QUOTED_STRING shift, and go to state 54
		1153	TXT_STRING shift, and go to state 55
		1154	NUM_STRING shift, and go to state 56
		1155
		1156	astring go to state 62
		1157	template_name go to state 63
		1158
		1159
		1160
		1161	state 9
		1162
		1163	ahdl_region -> AHDL . ahdl_chip_decls END end_item (rule 380)
		1164
		1165	SUBDESIGN shift, and go to state 64
		1166	'(' shift, and go to state 65
		1167
		1168	SUBDESIGN [reduce using rule 385 (ahdl_chip_decl)]
		1169	'(' [reduce using rule 385 (ahdl_chip_decl)]
		1170	$default reduce using rule 385 (ahdl_chip_decl)
		1171
		1172	ahdl_chip_decls go to state 66
		1173	ahdl_chip_decl go to state 67
		1174	ahdl_entityname_decl go to state 68
		1175	ahdl_port_decl go to state 69
		1176
		1177
		1178
		1179	state 10
		1180
		1181	verilog_region -> VERILOG . verilog_blocks END end_item (rule 222)
		1182
		1183	MODULE shift, and go to state 70
		1184
		1185	MODULE [reduce using rule 227 (verilog_block)]
		1186	$default reduce using rule 227 (verilog_block)
		1187
		1188	verilog_blocks go to state 71
		1189	verilog_block go to state 72
		1190	verilog_module_header go to state 73
		1191	verilog_toplevel_decl go to state 74
		1192	verilog_module_decl go to state 75
		1193
		1194
		1195
		1196	state 11
		1197
		1198	global_generic_decl -> GENERIC . @9 generic_defn_lines END end_item (rule 265)
		1199
		1200	$default reduce using rule 264 (@9)
		1201
		1202	@9 go to state 76
		1203
		1204
		1205
		1206	state 12
		1207
		1208	vhdl_region -> VHDL . vhdl_blocks END end_item (rule 132)
		1209
		1210	ENTITY shift, and go to state 77
		1211	ARCHITECTURE shift, and go to state 78
		1212	LIBRARY shift, and go to state 79
		1213	USE shift, and go to state 80
		1214	PACKAGE shift, and go to state 81
		1215
		1216	ENTITY [reduce using rule 140 (vhdl_block)]
		1217	ARCHITECTURE [reduce using rule 140 (vhdl_block)]
		1218	LIBRARY [reduce using rule 140 (vhdl_block)]
		1219	USE [reduce using rule 140 (vhdl_block)]
		1220	PACKAGE [reduce using rule 140 (vhdl_block)]
		1221	$default reduce using rule 140 (vhdl_block)
		1222
		1223	vhdl_blocks go to state 82
		1224	vhdl_block go to state 83
		1225	vhdl_chip_decl go to state 84
		1226	vhdl_architecture go to state 85
		1227	vhdl_package_decl go to state 86
		1228	vhdl_library_decl go to state 87
		1229	vhdl_use_decl go to state 88
		1230
		1231
		1232
		1233	state 13
		1234
		1235	file -> FILEMODE objects . (rule 1)
		1236	objects -> objects . object (rule 6)
		1237
		1238	CHIP shift, and go to state 3
		1239	COMPONENTS shift, and go to state 4
		1240	WIRED_NETS shift, and go to state 5
		1241	JOINED_NETS shift, and go to state 6
		1242	RENAME_PINS shift, and go to state 7
		1243	TEMPLATE shift, and go to state 8
		1244	AHDL shift, and go to state 9
		1245	VERILOG shift, and go to state 10
		1246	GENERIC shift, and go to state 11
		1247	VHDL shift, and go to state 12
		1248
		1249	$ reduce using rule 1 (file)
		1250	$ [reduce using rule 18 (object)]
		1251	CHIP [reduce using rule 18 (object)]
		1252	COMPONENTS [reduce using rule 18 (object)]
		1253	WIRED_NETS [reduce using rule 18 (object)]
		1254	JOINED_NETS [reduce using rule 18 (object)]
		1255	RENAME_PINS [reduce using rule 18 (object)]
		1256	TEMPLATE [reduce using rule 18 (object)]
		1257	AHDL [reduce using rule 18 (object)]
		1258	VERILOG [reduce using rule 18 (object)]
		1259	GENERIC [reduce using rule 18 (object)]
		1260	VHDL [reduce using rule 18 (object)]
		1261	$default reduce using rule 1 (file)
		1262	object go to state 89
		1263	chip_decl go to state 15
		1264	chip_id_decl go to state 16
		1265	vhdl_region go to state 17
		1266	verilog_region go to state 18
		1267	global_generic_decl go to state 19
		1268	components_decl go to state 20
		1269	joined_decl go to state 21
		1270	rename_pins_block go to state 22
		1271	nets_decl go to state 23
		1272	template_decl go to state 24
		1273	template_id_decl go to state 25
		1274	ahdl_region go to state 26
		1275
		1276
		1277
		1278	state 14
		1279
		1280	objects -> object . (rule 7)
		1281
		1282	$default reduce using rule 7 (objects)
		1283
		1284
		1285
		1286	state 15
		1287
		1288	object -> chip_decl . (rule 8)
		1289
		1290	$default reduce using rule 8 (object)
		1291
		1292
		1293
		1294	state 16
		1295
		1296	chip_decl -> chip_id_decl . chip_body (rule 22)
		1297
		1298	BEGIN_TOK shift, and go to state 90
		1299	ASSIGNED shift, and go to state 91
		1300
		1301	chip_body go to state 92
		1302
		1303
		1304
		1305	state 17
		1306
		1307	object -> vhdl_region . (rule 15)
		1308
		1309	$default reduce using rule 15 (object)
		1310
		1311
		1312
		1313	state 18
		1314
		1315	object -> verilog_region . (rule 16)
		1316
		1317	$default reduce using rule 16 (object)
		1318
		1319
		1320
		1321	state 19
		1322
		1323	object -> global_generic_decl . (rule 14)
		1324
		1325	$default reduce using rule 14 (object)
		1326
		1327
		1328
		1329	state 20
		1330
		1331	object -> components_decl . (rule 9)
		1332
		1333	$default reduce using rule 9 (object)
		1334
		1335
		1336
		1337	state 21
		1338
		1339	object -> joined_decl . (rule 11)
		1340
		1341	$default reduce using rule 11 (object)
		1342
		1343
		1344
		1345	state 22
		1346
		1347	object -> rename_pins_block . (rule 13)
		1348
		1349	$default reduce using rule 13 (object)
		1350
		1351
		1352
		1353	state 23
		1354
		1355	object -> nets_decl . (rule 12)
		1356
		1357	$default reduce using rule 12 (object)
		1358
		1359
		1360
		1361	state 24
		1362
		1363	object -> template_decl . (rule 10)
		1364
		1365	$default reduce using rule 10 (object)
		1366
		1367
		1368
		1369	state 25
		1370
		1371	template_decl -> template_id_decl . BEGIN_TOK template_info_lines pin_declarations pin_equivalences END end_item (rule 371)
		1372
		1373	BEGIN_TOK shift, and go to state 93
		1374
		1375
		1376
		1377	state 26
		1378
		1379	object -> ahdl_region . (rule 17)
		1380
		1381	$default reduce using rule 17 (object)
		1382
		1383
		1384
		1385	state 27
		1386
		1387	primary_expr -> TRUE . (rule 93)
		1388
		1389	$default reduce using rule 93 (primary_expr)
		1390
		1391
		1392
		1393	state 28
		1394
		1395	primary_expr -> FALSE . (rule 94)
		1396
		1397	$default reduce using rule 94 (primary_expr)
		1398
		1399
		1400
		1401	state 29
		1402
		1403	expr1 -> QUOTE . astring QUOTE (rule 85)
		1404
		1405	QUOTED_STRING shift, and go to state 54
		1406	TXT_STRING shift, and go to state 55
		1407	NUM_STRING shift, and go to state 56
		1408
		1409	astring go to state 94
		1410
		1411
		1412
		1413	state 30
		1414
		1415	expr1 -> QUOTED_STRING . (rule 84)
		1416
		1417	$default reduce using rule 84 (expr1)
		1418
		1419
		1420
		1421	state 31
		1422
		1423	primary_expr -> TXT_STRING . (rule 92)
		1424
		1425	$default reduce using rule 92 (primary_expr)
		1426
		1427
		1428
		1429	state 32
		1430
		1431	primary_expr -> NUM_STRING . (rule 91)
		1432
		1433	$default reduce using rule 91 (primary_expr)
		1434
		1435
		1436
		1437	state 33
		1438
		1439	primary_expr -> '~' . expr (rule 89)
		1440
		1441	TRUE shift, and go to state 27
		1442	FALSE shift, and go to state 28
		1443	TXT_STRING shift, and go to state 31
		1444	NUM_STRING shift, and go to state 32
		1445	'~' shift, and go to state 33
		1446	'(' shift, and go to state 34
		1447	'-' shift, and go to state 35
		1448
		1449	primary_expr go to state 41
		1450	mult_expr go to state 42
		1451	add_expr go to state 43
		1452	shift_expr go to state 44
		1453	relational_expr go to state 45
		1454	equality_expr go to state 46
		1455	and_expr go to state 47
		1456	exor_expr go to state 48
		1457	or_expr go to state 49
		1458	logand_expr go to state 50
		1459	logor_expr go to state 51
		1460	cond_expr go to state 52
		1461	expr go to state 95
		1462
		1463
		1464
		1465	state 34
		1466
		1467	primary_expr -> '(' . expr ')' (rule 88)
		1468
		1469	TRUE shift, and go to state 27
		1470	FALSE shift, and go to state 28
		1471	TXT_STRING shift, and go to state 31
		1472	NUM_STRING shift, and go to state 32
		1473	'~' shift, and go to state 33
		1474	'(' shift, and go to state 34
		1475	'-' shift, and go to state 35
		1476
		1477	primary_expr go to state 41
		1478	mult_expr go to state 42
		1479	add_expr go to state 43
		1480	shift_expr go to state 44
		1481	relational_expr go to state 45
		1482	equality_expr go to state 46
		1483	and_expr go to state 47
		1484	exor_expr go to state 48
		1485	or_expr go to state 49
		1486	logand_expr go to state 50
		1487	logor_expr go to state 51
		1488	cond_expr go to state 52
		1489	expr go to state 96
		1490
		1491
		1492
		1493	state 35
		1494
		1495	primary_expr -> '-' . expr (rule 90)
		1496
		1497	TRUE shift, and go to state 27
		1498	FALSE shift, and go to state 28
		1499	TXT_STRING shift, and go to state 31
		1500	NUM_STRING shift, and go to state 32
		1501	'~' shift, and go to state 33
		1502	'(' shift, and go to state 34
		1503	'-' shift, and go to state 35
		1504
		1505	primary_expr go to state 41
		1506	mult_expr go to state 42
		1507	add_expr go to state 43
		1508	shift_expr go to state 44
		1509	relational_expr go to state 45
		1510	equality_expr go to state 46
		1511	and_expr go to state 47
		1512	exor_expr go to state 48
		1513	or_expr go to state 49
		1514	logand_expr go to state 50
		1515	logor_expr go to state 51
		1516	cond_expr go to state 52
		1517	expr go to state 97
		1518
		1519
		1520
		1521	state 36
		1522
		1523	file -> CMDMODE cmd_objects . (rule 2)
		1524	cmd_objects -> cmd_objects . cmd_object (rule 3)
		1525
		1526	TRUE shift, and go to state 27
		1527	FALSE shift, and go to state 28
		1528	QUOTE shift, and go to state 29
		1529	QUOTED_STRING shift, and go to state 30
		1530	TXT_STRING shift, and go to state 31
		1531	NUM_STRING shift, and go to state 32
		1532	'~' shift, and go to state 33
		1533	'(' shift, and go to state 34
		1534	'-' shift, and go to state 35
		1535
		1536	$default reduce using rule 2 (file)
		1537
		1538	cmd_object go to state 98
		1539	bus_range go to state 38
		1540	expr1 go to state 39
		1541	simple_range_expr go to state 40
		1542	primary_expr go to state 41
		1543	mult_expr go to state 42
		1544	add_expr go to state 43
		1545	shift_expr go to state 44
		1546	relational_expr go to state 45
		1547	equality_expr go to state 46
		1548	and_expr go to state 47
		1549	exor_expr go to state 48
		1550	or_expr go to state 49
		1551	logand_expr go to state 50
		1552	logor_expr go to state 51
		1553	cond_expr go to state 52
		1554	expr go to state 53
		1555
		1556
		1557
		1558	state 37
		1559
		1560	cmd_objects -> cmd_object . (rule 4)
		1561
		1562	$default reduce using rule 4 (cmd_objects)
		1563
		1564
		1565
		1566	state 38
		1567
		1568	cmd_object -> bus_range . (rule 5)
		1569
		1570	$default reduce using rule 5 (cmd_object)
		1571
		1572
		1573
		1574	state 39
		1575
		1576	bus_range -> expr1 . (rule 81)
		1577
		1578	$default reduce using rule 81 (bus_range)
		1579
		1580
		1581
		1582	state 40
		1583
		1584	expr1 -> simple_range_expr . (rule 83)
		1585
		1586	$default reduce using rule 83 (expr1)
		1587
		1588
		1589
		1590	state 41
		1591
		1592	mult_expr -> primary_expr . (rule 95)
		1593
		1594	$default reduce using rule 95 (mult_expr)
		1595
		1596
		1597
		1598	state 42
		1599
		1600	mult_expr -> mult_expr . '*' primary_expr (rule 96)
		1601	mult_expr -> mult_expr . '/' primary_expr (rule 97)
		1602	mult_expr -> mult_expr . '%' primary_expr (rule 98)
		1603	mult_expr -> mult_expr . TO_POW primary_expr (rule 99)
		1604	add_expr -> mult_expr . (rule 100)
		1605
		1606	TO_POW shift, and go to state 99
		1607	'*' shift, and go to state 100
		1608	'/' shift, and go to state 101
		1609	'%' shift, and go to state 102
		1610
		1611	TO_POW [reduce using rule 100 (add_expr)]
		1612	'*' [reduce using rule 100 (add_expr)]
		1613	'/' [reduce using rule 100 (add_expr)]
		1614	'%' [reduce using rule 100 (add_expr)]
		1615	$default reduce using rule 100 (add_expr)
		1616
		1617
		1618
		1619	state 43
		1620
		1621	add_expr -> add_expr . '+' mult_expr (rule 101)
		1622	add_expr -> add_expr . '-' mult_expr (rule 102)
		1623	shift_expr -> add_expr . (rule 103)
		1624
		1625	'-' shift, and go to state 103
		1626	'+' shift, and go to state 104
		1627
		1628	'-' [reduce using rule 103 (shift_expr)]
		1629	'+' [reduce using rule 103 (shift_expr)]
		1630	$default reduce using rule 103 (shift_expr)
		1631
		1632
		1633
		1634	state 44
		1635
		1636	shift_expr -> shift_expr . SHL add_expr (rule 104)
		1637	shift_expr -> shift_expr . SHR add_expr (rule 105)
		1638	relational_expr -> shift_expr . (rule 106)
		1639
		1640	SHL shift, and go to state 105
		1641	SHR shift, and go to state 106
		1642
		1643	SHL [reduce using rule 106 (relational_expr)]
		1644	SHR [reduce using rule 106 (relational_expr)]
		1645	$default reduce using rule 106 (relational_expr)
		1646
		1647
		1648
		1649	state 45
		1650
		1651	relational_expr -> relational_expr . '>' shift_expr (rule 107)
		1652	relational_expr -> relational_expr . '<' shift_expr (rule 108)
		1653	equality_expr -> relational_expr . (rule 109)
		1654
		1655	'>' shift, and go to state 107
		1656	'<' shift, and go to state 108
		1657
		1658	'>' [reduce using rule 109 (equality_expr)]
		1659	'<' [reduce using rule 109 (equality_expr)]
		1660	$default reduce using rule 109 (equality_expr)
		1661
		1662
		1663
		1664	state 46
		1665
		1666	equality_expr -> equality_expr . EQ_EQ relational_expr (rule 110)
		1667	equality_expr -> equality_expr . N_EQ relational_expr (rule 111)
		1668	and_expr -> equality_expr . (rule 112)
		1669
		1670	EQ_EQ shift, and go to state 109
		1671	N_EQ shift, and go to state 110
		1672
		1673	EQ_EQ [reduce using rule 112 (and_expr)]
		1674	N_EQ [reduce using rule 112 (and_expr)]
		1675	$default reduce using rule 112 (and_expr)
		1676
		1677
		1678
		1679	state 47
		1680
		1681	and_expr -> and_expr . '&' equality_expr (rule 113)
		1682	exor_expr -> and_expr . (rule 114)
		1683
		1684	'&' shift, and go to state 111
		1685
		1686	'&' [reduce using rule 114 (exor_expr)]
		1687	$default reduce using rule 114 (exor_expr)
		1688
		1689
		1690
		1691	state 48
		1692
		1693	exor_expr -> exor_expr . '^' and_expr (rule 115)
		1694	or_expr -> exor_expr . (rule 116)
		1695
		1696	'^' shift, and go to state 112
		1697
		1698	'^' [reduce using rule 116 (or_expr)]
		1699	$default reduce using rule 116 (or_expr)
		1700
		1701
		1702
		1703	state 49
		1704
		1705	or_expr -> or_expr . '\|' or_expr (rule 117)
		1706	logand_expr -> or_expr . (rule 118)
		1707
		1708	'\|' shift, and go to state 113
		1709
		1710	'\|' [reduce using rule 118 (logand_expr)]
		1711	$default reduce using rule 118 (logand_expr)
		1712
		1713
		1714
		1715	state 50
		1716
		1717	logand_expr -> logand_expr . LOG_AND or_expr (rule 119)
		1718	logor_expr -> logand_expr . (rule 120)
		1719
		1720	LOG_AND shift, and go to state 114
		1721
		1722	LOG_AND [reduce using rule 120 (logor_expr)]
		1723	$default reduce using rule 120 (logor_expr)
		1724
		1725
		1726
		1727	state 51
		1728
		1729	logor_expr -> logor_expr . LOG_OR logand_expr (rule 121)
		1730	cond_expr -> logor_expr . '?' colon_expr (rule 122)
		1731	expr -> logor_expr . (rule 125)
		1732
		1733	LOG_OR shift, and go to state 115
		1734	'?' shift, and go to state 116
		1735
		1736	LOG_OR [reduce using rule 125 (expr)]
		1737	'?' [reduce using rule 125 (expr)]
		1738	$default reduce using rule 125 (expr)
		1739
		1740
		1741
		1742	state 52
		1743
		1744	expr -> cond_expr . (rule 124)
		1745
		1746	$default reduce using rule 124 (expr)
		1747
		1748
		1749
		1750	state 53
		1751
		1752	bus_range -> expr . (rule 82)
		1753	simple_range_expr -> expr . TO expr (rule 86)
		1754	simple_range_expr -> expr . DOWNTO expr (rule 87)
		1755
		1756	TO shift, and go to state 117
		1757	DOWNTO shift, and go to state 118
		1758
		1759	$default reduce using rule 82 (bus_range)
		1760
		1761
		1762
		1763	state 54
		1764
		1765	astring -> QUOTED_STRING . (rule 19)
		1766
		1767	$default reduce using rule 19 (astring)
		1768
		1769
		1770
		1771	state 55
		1772
		1773	astring -> TXT_STRING . (rule 20)
		1774
		1775	$default reduce using rule 20 (astring)
		1776
		1777
		1778
		1779	state 56
		1780
		1781	astring -> NUM_STRING . (rule 21)
		1782
		1783	$default reduce using rule 21 (astring)
		1784
		1785
		1786
		1787	state 57
		1788
		1789	chip_id_decl -> CHIP astring . (rule 26)
		1790
		1791	$default reduce using rule 26 (chip_id_decl)
		1792
		1793
		1794
		1795	state 58
		1796
		1797	components_decl -> COMPONENTS BEGIN_TOK . comp_defn_lines END end_item (rule 300)
		1798
		1799	QUOTED_STRING shift, and go to state 54
		1800	TXT_STRING shift, and go to state 55
		1801	NUM_STRING shift, and go to state 56
		1802
		1803	QUOTED_STRING [reduce using rule 303 (comp_defn_lines)]
		1804	TXT_STRING [reduce using rule 303 (comp_defn_lines)]
		1805	NUM_STRING [reduce using rule 303 (comp_defn_lines)]
		1806	$default reduce using rule 303 (comp_defn_lines)
		1807
		1808	astring go to state 119
		1809	comp_defn_lines go to state 120
		1810	comp_defn_line go to state 121
		1811	chip_ident go to state 122
		1812
		1813
		1814
		1815	state 59
		1816
		1817	nets_decl -> WIRED_NETS @16 . BEGIN_TOK connection_block END end_item (rule 338)
		1818
		1819	BEGIN_TOK shift, and go to state 123
		1820
		1821
		1822
		1823	state 60
		1824
		1825	joined_decl -> JOINED_NETS BEGIN_TOK . join_decls END end_item (rule 309)
		1826
		1827	CONN shift, and go to state 124
		1828	ALIAS shift, and go to state 125
		1829	JUMPER shift, and go to state 126
		1830	VHDL_CONN shift, and go to state 127
		1831
		1832	CONN [reduce using rule 312 (join_decls)]
		1833	ALIAS [reduce using rule 312 (join_decls)]
		1834	JUMPER [reduce using rule 312 (join_decls)]
		1835	GND reduce using rule 312 (join_decls)
		1836	GND [reduce using rule 319 (alias_part)]
		1837	VCC reduce using rule 312 (join_decls)
		1838	VCC [reduce using rule 319 (alias_part)]
		1839	VHDL_CONN [reduce using rule 312 (join_decls)]
		1840	QUOTED_STRING reduce using rule 312 (join_decls)
		1841	QUOTED_STRING [reduce using rule 319 (alias_part)]
		1842	TXT_STRING reduce using rule 312 (join_decls)
		1843	TXT_STRING [reduce using rule 319 (alias_part)]
		1844	NUM_STRING reduce using rule 312 (join_decls)
		1845	NUM_STRING [reduce using rule 319 (alias_part)]
		1846	$default reduce using rule 312 (join_decls)
		1847	join_decls go to state 128
		1848	join_decl go to state 129
		1849	alias_part go to state 130
		1850
		1851
		1852
		1853	state 61
		1854
		1855	rename_pins_block -> RENAME_PINS BEGIN_TOK . rename_pin_decls END end_item (rule 327)
		1856
		1857	GND shift, and go to state 131
		1858	VCC shift, and go to state 132
		1859	QUOTED_STRING shift, and go to state 54
		1860	TXT_STRING shift, and go to state 55
		1861	NUM_STRING shift, and go to state 56
		1862
		1863	astring go to state 133
		1864	rename_pin_decls go to state 134
		1865	rename_pin_decl go to state 135
		1866	rename_new_name go to state 136
		1867	netname go to state 137
		1868
		1869
		1870
		1871	state 62
		1872
		1873	template_name -> astring . (rule 373)
		1874
		1875	$default reduce using rule 373 (template_name)
		1876
		1877
		1878
		1879	state 63
		1880
		1881	template_id_decl -> TEMPLATE template_name . (rule 372)
		1882
		1883	$default reduce using rule 372 (template_id_decl)
		1884
		1885
		1886
		1887	state 64
		1888
		1889	ahdl_entityname_decl -> SUBDESIGN . TXT_STRING (rule 386)
		1890
		1891	TXT_STRING shift, and go to state 138
		1892
		1893
		1894
		1895	state 65
		1896
		1897	ahdl_port_decl -> '(' . ahdl_port_list ')' (rule 387)
		1898
		1899	QUOTED_STRING shift, and go to state 54
		1900	TXT_STRING shift, and go to state 55
		1901	NUM_STRING shift, and go to state 56
		1902
		1903	$default reduce using rule 390 (ahdl_port_list)
		1904
		1905	astring go to state 139
		1906	ahdl_port_list go to state 140
		1907	ahdl_port_item go to state 141
		1908	ahdl_name_list go to state 142
		1909	ahdl_name_part go to state 143
		1910
		1911
		1912
		1913	state 66
		1914
		1915	ahdl_region -> AHDL ahdl_chip_decls . END end_item (rule 380)
		1916
		1917	END shift, and go to state 144
		1918
		1919
		1920
		1921	state 67
		1922
		1923	ahdl_chip_decls -> ahdl_chip_decl . ahdl_chip_decls (rule 381)
		1924	ahdl_chip_decls -> ahdl_chip_decl . (rule 382)
		1925
		1926	SUBDESIGN shift, and go to state 64
		1927	'(' shift, and go to state 65
		1928
		1929	END reduce using rule 382 (ahdl_chip_decls)
		1930	END [reduce using rule 385 (ahdl_chip_decl)]
		1931	SUBDESIGN [reduce using rule 385 (ahdl_chip_decl)]
		1932	'(' [reduce using rule 385 (ahdl_chip_decl)]
		1933	$default reduce using rule 382 (ahdl_chip_decls)
		1934	ahdl_chip_decls go to state 145
		1935	ahdl_chip_decl go to state 67
		1936	ahdl_entityname_decl go to state 68
		1937	ahdl_port_decl go to state 69
		1938
		1939
		1940
		1941	state 68
		1942
		1943	ahdl_chip_decl -> ahdl_entityname_decl . (rule 383)
		1944
		1945	$default reduce using rule 383 (ahdl_chip_decl)
		1946
		1947
		1948
		1949	state 69
		1950
		1951	ahdl_chip_decl -> ahdl_port_decl . (rule 384)
		1952
		1953	$default reduce using rule 384 (ahdl_chip_decl)
		1954
		1955
		1956
		1957	state 70
		1958
		1959	verilog_module_header -> MODULE . hdl_compname_decl verilog_port_list verilog_pindir_block (rule 228)
		1960
		1961	TXT_STRING shift, and go to state 146
		1962
		1963	hdl_compname_decl go to state 147
		1964
		1965
		1966
		1967	state 71
		1968
		1969	verilog_region -> VERILOG verilog_blocks . END end_item (rule 222)
		1970	verilog_blocks -> verilog_blocks . verilog_block (rule 223)
		1971
		1972	END shift, and go to state 148
		1973	MODULE shift, and go to state 70
		1974
		1975	END [reduce using rule 227 (verilog_block)]
		1976	MODULE [reduce using rule 227 (verilog_block)]
		1977	$default reduce using rule 227 (verilog_block)
		1978
		1979	verilog_block go to state 149
		1980	verilog_module_header go to state 73
		1981	verilog_toplevel_decl go to state 74
		1982	verilog_module_decl go to state 75
		1983
		1984
		1985
		1986	state 72
		1987
		1988	verilog_blocks -> verilog_block . (rule 224)
		1989
		1990	$default reduce using rule 224 (verilog_blocks)
		1991
		1992
		1993
		1994	state 73
		1995
		1996	verilog_toplevel_decl -> verilog_module_header . verilog_module_body ENDMODULE (rule 229)
		1997	verilog_module_decl -> verilog_module_header . ENDMODULE (rule 230)
		1998
		1999	ENDMODULE shift, and go to state 150
		2000	WIRE shift, and go to state 151
		2001
		2002	ENDMODULE [reduce using rule 249 (verilog_wires_block)]
		2003	$default reduce using rule 249 (verilog_wires_block)
		2004
		2005	verilog_module_body go to state 152
		2006	verilog_wires_block go to state 153
		2007	verilog_wires_decl go to state 154
		2008	verilog_wire_start go to state 155
		2009
		2010
		2011
		2012	state 74
		2013
		2014	verilog_block -> verilog_toplevel_decl . (rule 226)
		2015
		2016	$default reduce using rule 226 (verilog_block)
		2017
		2018
		2019
		2020	state 75
		2021
		2022	verilog_block -> verilog_module_decl . (rule 225)
		2023
		2024	$default reduce using rule 225 (verilog_block)
		2025
		2026
		2027
		2028	state 76
		2029
		2030	global_generic_decl -> GENERIC @9 . generic_defn_lines END end_item (rule 265)
		2031
		2032	CONSTANT shift, and go to state 156
		2033
		2034	END reduce using rule 270 (generic_defn_lines)
		2035	';' reduce using rule 270 (generic_defn_lines)
		2036	$default reduce using rule 272 (generic_const_opt)
		2037	generic_defn_lines go to state 157
		2038	generic_const_opt go to state 158
		2039	generic_defn_text go to state 159
		2040
		2041
		2042
		2043	state 77
		2044
		2045	vhdl_chip_decl -> ENTITY . hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
		2046
		2047	TXT_STRING shift, and go to state 160
		2048
		2049	hdl_entityname_decl go to state 161
		2050
		2051
		2052
		2053	state 78
		2054
		2055	vhdl_architecture -> ARCHITECTURE . astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
		2056
		2057	QUOTED_STRING shift, and go to state 54
		2058	TXT_STRING shift, and go to state 55
		2059	NUM_STRING shift, and go to state 56
		2060
		2061	astring go to state 162
		2062
		2063
		2064
		2065	state 79
		2066
		2067	vhdl_library_decl -> LIBRARY . vhdl_library_list ';' (rule 211)
		2068
		2069	QUOTED_STRING shift, and go to state 54
		2070	TXT_STRING shift, and go to state 55
		2071	NUM_STRING shift, and go to state 56
		2072
		2073	astring go to state 163
		2074	vhdl_library_list go to state 164
		2075	vhdl_library_name go to state 165
		2076
		2077
		2078
		2079	state 80
		2080
		2081	vhdl_use_decl -> USE . vhdl_lib_members ';' (rule 215)
		2082
		2083	QUOTED_STRING shift, and go to state 54
		2084	TXT_STRING shift, and go to state 55
		2085	NUM_STRING shift, and go to state 56
		2086
		2087	astring go to state 166
		2088	vhdl_lib_members go to state 167
		2089	vhdl_lib_member go to state 168
		2090
		2091
		2092
		2093	state 81
		2094
		2095	vhdl_package_decl -> PACKAGE . package_name IS vhdl_package_declarations END astring end_item (rule 168)
		2096
		2097	QUOTED_STRING shift, and go to state 54
		2098	TXT_STRING shift, and go to state 55
		2099	NUM_STRING shift, and go to state 56
		2100
		2101	astring go to state 169
		2102	package_name go to state 170
		2103
		2104
		2105
		2106	state 82
		2107
		2108	vhdl_region -> VHDL vhdl_blocks . END end_item (rule 132)
		2109	vhdl_blocks -> vhdl_blocks . vhdl_block (rule 133)
		2110
		2111	END shift, and go to state 171
		2112	ENTITY shift, and go to state 77
		2113	ARCHITECTURE shift, and go to state 78
		2114	LIBRARY shift, and go to state 79
		2115	USE shift, and go to state 80
		2116	PACKAGE shift, and go to state 81
		2117
		2118	END [reduce using rule 140 (vhdl_block)]
		2119	ENTITY [reduce using rule 140 (vhdl_block)]
		2120	ARCHITECTURE [reduce using rule 140 (vhdl_block)]
		2121	LIBRARY [reduce using rule 140 (vhdl_block)]
		2122	USE [reduce using rule 140 (vhdl_block)]
		2123	PACKAGE [reduce using rule 140 (vhdl_block)]
		2124	$default reduce using rule 140 (vhdl_block)
		2125
		2126	vhdl_block go to state 172
		2127	vhdl_chip_decl go to state 84
		2128	vhdl_architecture go to state 85
		2129	vhdl_package_decl go to state 86
		2130	vhdl_library_decl go to state 87
		2131	vhdl_use_decl go to state 88
		2132
		2133
		2134
		2135	state 83
		2136
		2137	vhdl_blocks -> vhdl_block . (rule 134)
		2138
		2139	$default reduce using rule 134 (vhdl_blocks)
		2140
		2141
		2142
		2143	state 84
		2144
		2145	vhdl_block -> vhdl_chip_decl . (rule 135)
		2146
		2147	$default reduce using rule 135 (vhdl_block)
		2148
		2149
		2150
		2151	state 85
		2152
		2153	vhdl_block -> vhdl_architecture . (rule 136)
		2154
		2155	$default reduce using rule 136 (vhdl_block)
		2156
		2157
		2158
		2159	state 86
		2160
		2161	vhdl_block -> vhdl_package_decl . (rule 137)
		2162
		2163	$default reduce using rule 137 (vhdl_block)
		2164
		2165
		2166
		2167	state 87
		2168
		2169	vhdl_block -> vhdl_library_decl . (rule 138)
		2170
		2171	$default reduce using rule 138 (vhdl_block)
		2172
		2173
		2174
		2175	state 88
		2176
		2177	vhdl_block -> vhdl_use_decl . (rule 139)
		2178
		2179	$default reduce using rule 139 (vhdl_block)
		2180
		2181
		2182
		2183	state 89
		2184
		2185	objects -> objects object . (rule 6)
		2186
		2187	$default reduce using rule 6 (objects)
		2188
		2189
		2190
		2191	state 90
		2192
		2193	chip_body -> BEGIN_TOK . flex_chip_body (rule 23)
		2194
		2195	DEVICE shift, and go to state 173
		2196	UNROUTED shift, and go to state 174
		2197	ROUTE_FLAGS shift, and go to state 175
		2198	GENERIC shift, and go to state 176
		2199
		2200	DEVICE [reduce using rule 29 (chip_info_lines)]
		2201	UNROUTED [reduce using rule 29 (chip_info_lines)]
		2202	ROUTE_FLAGS [reduce using rule 29 (chip_info_lines)]
		2203	GENERIC [reduce using rule 29 (chip_info_lines)]
		2204	$default reduce using rule 29 (chip_info_lines)
		2205
		2206	flex_chip_body go to state 177
		2207	chip_info_lines go to state 178
		2208	chip_info_line go to state 179
		2209	device_declaration go to state 180
		2210	routing_status go to state 181
		2211	route_flags_info go to state 182
		2212	chip_generic_decl go to state 183
		2213
		2214
		2215
		2216	state 91
		2217
		2218	chip_body -> ASSIGNED . apex_chip_body (rule 24)
		2219
		2220	TO shift, and go to state 184
		2221
		2222	apex_chip_body go to state 185
		2223	apex_device_declaration go to state 186
		2224
		2225
		2226
		2227	state 92
		2228
		2229	chip_decl -> chip_id_decl chip_body . (rule 22)
		2230
		2231	$default reduce using rule 22 (chip_decl)
		2232
		2233
		2234
		2235	state 93
		2236
		2237	template_decl -> template_id_decl BEGIN_TOK . template_info_lines pin_declarations pin_equivalences END end_item (rule 371)
		2238
		2239	ALIAS shift, and go to state 187
		2240	GENERIC shift, and go to state 176
		2241
		2242	ALIAS [reduce using rule 378 (template_info_line)]
		2243	GENERIC [reduce using rule 378 (template_info_line)]
		2244	$default reduce using rule 378 (template_info_line)
		2245
		2246	chip_generic_decl go to state 188
		2247	template_info_lines go to state 189
		2248	template_info_line go to state 190
		2249	alias_to_another_template go to state 191
		2250
		2251
		2252
		2253	state 94
		2254
		2255	expr1 -> QUOTE astring . QUOTE (rule 85)
		2256
		2257	QUOTE shift, and go to state 192
		2258
		2259
		2260
		2261	state 95
		2262
		2263	primary_expr -> '~' expr . (rule 89)
		2264
		2265	$default reduce using rule 89 (primary_expr)
		2266
		2267
		2268
		2269	state 96
		2270
		2271	primary_expr -> '(' expr . ')' (rule 88)
		2272
		2273	')' shift, and go to state 193
		2274
		2275
		2276
		2277	state 97
		2278
		2279	primary_expr -> '-' expr . (rule 90)
		2280
		2281	$default reduce using rule 90 (primary_expr)
		2282
		2283
		2284
		2285	state 98
		2286
		2287	cmd_objects -> cmd_objects cmd_object . (rule 3)
		2288
		2289	$default reduce using rule 3 (cmd_objects)
		2290
		2291
		2292
		2293	state 99
		2294
		2295	mult_expr -> mult_expr TO_POW . primary_expr (rule 99)
		2296
		2297	TRUE shift, and go to state 27
		2298	FALSE shift, and go to state 28
		2299	TXT_STRING shift, and go to state 31
		2300	NUM_STRING shift, and go to state 32
		2301	'~' shift, and go to state 33
		2302	'(' shift, and go to state 34
		2303	'-' shift, and go to state 35
		2304
		2305	primary_expr go to state 194
		2306
		2307
		2308
		2309	state 100
		2310
		2311	mult_expr -> mult_expr '*' . primary_expr (rule 96)
		2312
		2313	TRUE shift, and go to state 27
		2314	FALSE shift, and go to state 28
		2315	TXT_STRING shift, and go to state 31
		2316	NUM_STRING shift, and go to state 32
		2317	'~' shift, and go to state 33
		2318	'(' shift, and go to state 34
		2319	'-' shift, and go to state 35
		2320
		2321	primary_expr go to state 195
		2322
		2323
		2324
		2325	state 101
		2326
		2327	mult_expr -> mult_expr '/' . primary_expr (rule 97)
		2328
		2329	TRUE shift, and go to state 27
		2330	FALSE shift, and go to state 28
		2331	TXT_STRING shift, and go to state 31
		2332	NUM_STRING shift, and go to state 32
		2333	'~' shift, and go to state 33
		2334	'(' shift, and go to state 34
		2335	'-' shift, and go to state 35
		2336
		2337	primary_expr go to state 196
		2338
		2339
		2340
		2341	state 102
		2342
		2343	mult_expr -> mult_expr '%' . primary_expr (rule 98)
		2344
		2345	TRUE shift, and go to state 27
		2346	FALSE shift, and go to state 28
		2347	TXT_STRING shift, and go to state 31
		2348	NUM_STRING shift, and go to state 32
		2349	'~' shift, and go to state 33
		2350	'(' shift, and go to state 34
		2351	'-' shift, and go to state 35
		2352
		2353	primary_expr go to state 197
		2354
		2355
		2356
		2357	state 103
		2358
		2359	add_expr -> add_expr '-' . mult_expr (rule 102)
		2360
		2361	TRUE shift, and go to state 27
		2362	FALSE shift, and go to state 28
		2363	TXT_STRING shift, and go to state 31
		2364	NUM_STRING shift, and go to state 32
		2365	'~' shift, and go to state 33
		2366	'(' shift, and go to state 34
		2367	'-' shift, and go to state 35
		2368
		2369	primary_expr go to state 41
		2370	mult_expr go to state 198
		2371
		2372
		2373
		2374	state 104
		2375
		2376	add_expr -> add_expr '+' . mult_expr (rule 101)
		2377
		2378	TRUE shift, and go to state 27
		2379	FALSE shift, and go to state 28
		2380	TXT_STRING shift, and go to state 31
		2381	NUM_STRING shift, and go to state 32
		2382	'~' shift, and go to state 33
		2383	'(' shift, and go to state 34
		2384	'-' shift, and go to state 35
		2385
		2386	primary_expr go to state 41
		2387	mult_expr go to state 199
		2388
		2389
		2390
		2391	state 105
		2392
		2393	shift_expr -> shift_expr SHL . add_expr (rule 104)
		2394
		2395	TRUE shift, and go to state 27
		2396	FALSE shift, and go to state 28
		2397	TXT_STRING shift, and go to state 31
		2398	NUM_STRING shift, and go to state 32
		2399	'~' shift, and go to state 33
		2400	'(' shift, and go to state 34
		2401	'-' shift, and go to state 35
		2402
		2403	primary_expr go to state 41
		2404	mult_expr go to state 42
		2405	add_expr go to state 200
		2406
		2407
		2408
		2409	state 106
		2410
		2411	shift_expr -> shift_expr SHR . add_expr (rule 105)
		2412
		2413	TRUE shift, and go to state 27
		2414	FALSE shift, and go to state 28
		2415	TXT_STRING shift, and go to state 31
		2416	NUM_STRING shift, and go to state 32
		2417	'~' shift, and go to state 33
		2418	'(' shift, and go to state 34
		2419	'-' shift, and go to state 35
		2420
		2421	primary_expr go to state 41
		2422	mult_expr go to state 42
		2423	add_expr go to state 201
		2424
		2425
		2426
		2427	state 107
		2428
		2429	relational_expr -> relational_expr '>' . shift_expr (rule 107)
		2430
		2431	TRUE shift, and go to state 27
		2432	FALSE shift, and go to state 28
		2433	TXT_STRING shift, and go to state 31
		2434	NUM_STRING shift, and go to state 32
		2435	'~' shift, and go to state 33
		2436	'(' shift, and go to state 34
		2437	'-' shift, and go to state 35
		2438
		2439	primary_expr go to state 41
		2440	mult_expr go to state 42
		2441	add_expr go to state 43
		2442	shift_expr go to state 202
		2443
		2444
		2445
		2446	state 108
		2447
		2448	relational_expr -> relational_expr '<' . shift_expr (rule 108)
		2449
		2450	TRUE shift, and go to state 27
		2451	FALSE shift, and go to state 28
		2452	TXT_STRING shift, and go to state 31
		2453	NUM_STRING shift, and go to state 32
		2454	'~' shift, and go to state 33
		2455	'(' shift, and go to state 34
		2456	'-' shift, and go to state 35
		2457
		2458	primary_expr go to state 41
		2459	mult_expr go to state 42
		2460	add_expr go to state 43
		2461	shift_expr go to state 203
		2462
		2463
		2464
		2465	state 109
		2466
		2467	equality_expr -> equality_expr EQ_EQ . relational_expr (rule 110)
		2468
		2469	TRUE shift, and go to state 27
		2470	FALSE shift, and go to state 28
		2471	TXT_STRING shift, and go to state 31
		2472	NUM_STRING shift, and go to state 32
		2473	'~' shift, and go to state 33
		2474	'(' shift, and go to state 34
		2475	'-' shift, and go to state 35
		2476
		2477	primary_expr go to state 41
		2478	mult_expr go to state 42
		2479	add_expr go to state 43
		2480	shift_expr go to state 44
		2481	relational_expr go to state 204
		2482
		2483
		2484
		2485	state 110
		2486
		2487	equality_expr -> equality_expr N_EQ . relational_expr (rule 111)
		2488
		2489	TRUE shift, and go to state 27
		2490	FALSE shift, and go to state 28
		2491	TXT_STRING shift, and go to state 31
		2492	NUM_STRING shift, and go to state 32
		2493	'~' shift, and go to state 33
		2494	'(' shift, and go to state 34
		2495	'-' shift, and go to state 35
		2496
		2497	primary_expr go to state 41
		2498	mult_expr go to state 42
		2499	add_expr go to state 43
		2500	shift_expr go to state 44
		2501	relational_expr go to state 205
		2502
		2503
		2504
		2505	state 111
		2506
		2507	and_expr -> and_expr '&' . equality_expr (rule 113)
		2508
		2509	TRUE shift, and go to state 27
		2510	FALSE shift, and go to state 28
		2511	TXT_STRING shift, and go to state 31
		2512	NUM_STRING shift, and go to state 32
		2513	'~' shift, and go to state 33
		2514	'(' shift, and go to state 34
		2515	'-' shift, and go to state 35
		2516
		2517	primary_expr go to state 41
		2518	mult_expr go to state 42
		2519	add_expr go to state 43
		2520	shift_expr go to state 44
		2521	relational_expr go to state 45
		2522	equality_expr go to state 206
		2523
		2524
		2525
		2526	state 112
		2527
		2528	exor_expr -> exor_expr '^' . and_expr (rule 115)
		2529
		2530	TRUE shift, and go to state 27
		2531	FALSE shift, and go to state 28
		2532	TXT_STRING shift, and go to state 31
		2533	NUM_STRING shift, and go to state 32
		2534	'~' shift, and go to state 33
		2535	'(' shift, and go to state 34
		2536	'-' shift, and go to state 35
		2537
		2538	primary_expr go to state 41
		2539	mult_expr go to state 42
		2540	add_expr go to state 43
		2541	shift_expr go to state 44
		2542	relational_expr go to state 45
		2543	equality_expr go to state 46
		2544	and_expr go to state 207
		2545
		2546
		2547
		2548	state 113
		2549
		2550	or_expr -> or_expr '\|' . or_expr (rule 117)
		2551
		2552	TRUE shift, and go to state 27
		2553	FALSE shift, and go to state 28
		2554	TXT_STRING shift, and go to state 31
		2555	NUM_STRING shift, and go to state 32
		2556	'~' shift, and go to state 33
		2557	'(' shift, and go to state 34
		2558	'-' shift, and go to state 35
		2559
		2560	primary_expr go to state 41
		2561	mult_expr go to state 42
		2562	add_expr go to state 43
		2563	shift_expr go to state 44
		2564	relational_expr go to state 45
		2565	equality_expr go to state 46
		2566	and_expr go to state 47
		2567	exor_expr go to state 48
		2568	or_expr go to state 208
		2569
		2570
		2571
		2572	state 114
		2573
		2574	logand_expr -> logand_expr LOG_AND . or_expr (rule 119)
		2575
		2576	TRUE shift, and go to state 27
		2577	FALSE shift, and go to state 28
		2578	TXT_STRING shift, and go to state 31
		2579	NUM_STRING shift, and go to state 32
		2580	'~' shift, and go to state 33
		2581	'(' shift, and go to state 34
		2582	'-' shift, and go to state 35
		2583
		2584	primary_expr go to state 41
		2585	mult_expr go to state 42
		2586	add_expr go to state 43
		2587	shift_expr go to state 44
		2588	relational_expr go to state 45
		2589	equality_expr go to state 46
		2590	and_expr go to state 47
		2591	exor_expr go to state 48
		2592	or_expr go to state 209
		2593
		2594
		2595
		2596	state 115
		2597
		2598	logor_expr -> logor_expr LOG_OR . logand_expr (rule 121)
		2599
		2600	TRUE shift, and go to state 27
		2601	FALSE shift, and go to state 28
		2602	TXT_STRING shift, and go to state 31
		2603	NUM_STRING shift, and go to state 32
		2604	'~' shift, and go to state 33
		2605	'(' shift, and go to state 34
		2606	'-' shift, and go to state 35
		2607
		2608	primary_expr go to state 41
		2609	mult_expr go to state 42
		2610	add_expr go to state 43
		2611	shift_expr go to state 44
		2612	relational_expr go to state 45
		2613	equality_expr go to state 46
		2614	and_expr go to state 47
		2615	exor_expr go to state 48
		2616	or_expr go to state 49
		2617	logand_expr go to state 210
		2618
		2619
		2620
		2621	state 116
		2622
		2623	cond_expr -> logor_expr '?' . colon_expr (rule 122)
		2624
		2625	TRUE shift, and go to state 27
		2626	FALSE shift, and go to state 28
		2627	TXT_STRING shift, and go to state 31
		2628	NUM_STRING shift, and go to state 32
		2629	'~' shift, and go to state 33
		2630	'(' shift, and go to state 34
		2631	'-' shift, and go to state 35
		2632
		2633	primary_expr go to state 41
		2634	mult_expr go to state 42
		2635	add_expr go to state 43
		2636	shift_expr go to state 44
		2637	relational_expr go to state 45
		2638	equality_expr go to state 46
		2639	and_expr go to state 47
		2640	exor_expr go to state 48
		2641	or_expr go to state 49
		2642	logand_expr go to state 50
		2643	logor_expr go to state 51
		2644	cond_expr go to state 52
		2645	colon_expr go to state 211
		2646	expr go to state 212
		2647
		2648
		2649
		2650	state 117
		2651
		2652	simple_range_expr -> expr TO . expr (rule 86)
		2653
		2654	TRUE shift, and go to state 27
		2655	FALSE shift, and go to state 28
		2656	TXT_STRING shift, and go to state 31
		2657	NUM_STRING shift, and go to state 32
		2658	'~' shift, and go to state 33
		2659	'(' shift, and go to state 34
		2660	'-' shift, and go to state 35
		2661
		2662	primary_expr go to state 41
		2663	mult_expr go to state 42
		2664	add_expr go to state 43
		2665	shift_expr go to state 44
		2666	relational_expr go to state 45
		2667	equality_expr go to state 46
		2668	and_expr go to state 47
		2669	exor_expr go to state 48
		2670	or_expr go to state 49
		2671	logand_expr go to state 50
		2672	logor_expr go to state 51
		2673	cond_expr go to state 52
		2674	expr go to state 213
		2675
		2676
		2677
		2678	state 118
		2679
		2680	simple_range_expr -> expr DOWNTO . expr (rule 87)
		2681
		2682	TRUE shift, and go to state 27
		2683	FALSE shift, and go to state 28
		2684	TXT_STRING shift, and go to state 31
		2685	NUM_STRING shift, and go to state 32
		2686	'~' shift, and go to state 33
		2687	'(' shift, and go to state 34
		2688	'-' shift, and go to state 35
		2689
		2690	primary_expr go to state 41
		2691	mult_expr go to state 42
		2692	add_expr go to state 43
		2693	shift_expr go to state 44
		2694	relational_expr go to state 45
		2695	equality_expr go to state 46
		2696	and_expr go to state 47
		2697	exor_expr go to state 48
		2698	or_expr go to state 49
		2699	logand_expr go to state 50
		2700	logor_expr go to state 51
		2701	cond_expr go to state 52
		2702	expr go to state 214
		2703
		2704
		2705
		2706	state 119
		2707
		2708	chip_ident -> astring . (rule 305)
		2709
		2710	$default reduce using rule 305 (chip_ident)
		2711
		2712
		2713
		2714	state 120
		2715
		2716	components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines . END end_item (rule 300)
		2717	comp_defn_lines -> comp_defn_lines . comp_defn_line (rule 301)
		2718
		2719	END shift, and go to state 215
		2720	QUOTED_STRING shift, and go to state 54
		2721	TXT_STRING shift, and go to state 55
		2722	NUM_STRING shift, and go to state 56
		2723
		2724	astring go to state 119
		2725	comp_defn_line go to state 216
		2726	chip_ident go to state 122
		2727
		2728
		2729
		2730	state 121
		2731
		2732	comp_defn_lines -> comp_defn_line . (rule 302)
		2733
		2734	$default reduce using rule 302 (comp_defn_lines)
		2735
		2736
		2737
		2738	state 122
		2739
		2740	comp_defn_line -> chip_ident . ':' chip_name chip_type chip_value end_item (rule 304)
		2741
		2742	':' shift, and go to state 217
		2743
		2744
		2745
		2746	state 123
		2747
		2748	nets_decl -> WIRED_NETS @16 BEGIN_TOK . connection_block END end_item (rule 338)
		2749
		2750	CONN shift, and go to state 218
		2751	UNROUTED shift, and go to state 219
		2752	ROUTED shift, and go to state 220
		2753	NAMED shift, and go to state 221
		2754
		2755	CONN [reduce using rule 345 (connection_block_item)]
		2756	UNROUTED [reduce using rule 345 (connection_block_item)]
		2757	ROUTED [reduce using rule 345 (connection_block_item)]
		2758	NAMED [reduce using rule 345 (connection_block_item)]
		2759	$default reduce using rule 345 (connection_block_item)
		2760
		2761	connection_block go to state 222
		2762	connection_block_item go to state 223
		2763	routed_decl go to state 224
		2764	unrouted_decl go to state 225
		2765	named_decl go to state 226
		2766	conn_decls go to state 227
		2767	conn_decl go to state 228
		2768
		2769
		2770
		2771	state 124
		2772
		2773	join_decl -> CONN . astring astring @15 end_item (rule 315)
		2774
		2775	QUOTED_STRING shift, and go to state 54
		2776	TXT_STRING shift, and go to state 55
		2777	NUM_STRING shift, and go to state 56
		2778
		2779	astring go to state 229
		2780
		2781
		2782
		2783	state 125
		2784
		2785	alias_part -> ALIAS . (rule 317)
		2786
		2787	$default reduce using rule 317 (alias_part)
		2788
		2789
		2790
		2791	state 126
		2792
		2793	alias_part -> JUMPER . (rule 318)
		2794
		2795	$default reduce using rule 318 (alias_part)
		2796
		2797
		2798
		2799	state 127
		2800
		2801	join_decl -> VHDL_CONN . vhdl_concurrent_assignment (rule 316)
		2802
		2803	QUOTED_STRING shift, and go to state 54
		2804	TXT_STRING shift, and go to state 55
		2805	NUM_STRING shift, and go to state 56
		2806
		2807	astring go to state 230
		2808	vhdl_concurrent_assignment go to state 231
		2809
		2810
		2811
		2812	state 128
		2813
		2814	joined_decl -> JOINED_NETS BEGIN_TOK join_decls . END end_item (rule 309)
		2815	join_decls -> join_decls . join_decl (rule 310)
		2816
		2817	END shift, and go to state 232
		2818	CONN shift, and go to state 124
		2819	ALIAS shift, and go to state 125
		2820	JUMPER shift, and go to state 126
		2821	VHDL_CONN shift, and go to state 127
		2822
		2823	$default reduce using rule 319 (alias_part)
		2824
		2825	join_decl go to state 233
		2826	alias_part go to state 130
		2827
		2828
		2829
		2830	state 129
		2831
		2832	join_decls -> join_decl . (rule 311)
		2833
		2834	$default reduce using rule 311 (join_decls)
		2835
		2836
		2837
		2838	state 130
		2839
		2840	join_decl -> alias_part . root_net '=' '(' joined_nets ')' end_item (rule 313)
		2841
		2842	GND shift, and go to state 131
		2843	VCC shift, and go to state 132
		2844	QUOTED_STRING shift, and go to state 54
		2845	TXT_STRING shift, and go to state 55
		2846	NUM_STRING shift, and go to state 56
		2847
		2848	astring go to state 133
		2849	root_net go to state 234
		2850	netname go to state 235
		2851
		2852
		2853
		2854	state 131
		2855
		2856	netname -> GND . (rule 369)
		2857
		2858	$default reduce using rule 369 (netname)
		2859
		2860
		2861
		2862	state 132
		2863
		2864	netname -> VCC . (rule 368)
		2865
		2866	$default reduce using rule 368 (netname)
		2867
		2868
		2869
		2870	state 133
		2871
		2872	netname -> astring . (rule 370)
		2873
		2874	$default reduce using rule 370 (netname)
		2875
		2876
		2877
		2878	state 134
		2879
		2880	rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls . END end_item (rule 327)
		2881	rename_pin_decls -> rename_pin_decls . rename_pin_decl (rule 328)
		2882
		2883	END shift, and go to state 236
		2884	GND shift, and go to state 131
		2885	VCC shift, and go to state 132
		2886	QUOTED_STRING shift, and go to state 54
		2887	TXT_STRING shift, and go to state 55
		2888	NUM_STRING shift, and go to state 56
		2889
		2890	astring go to state 133
		2891	rename_pin_decl go to state 237
		2892	rename_new_name go to state 136
		2893	netname go to state 137
		2894
		2895
		2896
		2897	state 135
		2898
		2899	rename_pin_decls -> rename_pin_decl . (rule 329)
		2900
		2901	$default reduce using rule 329 (rename_pin_decls)
		2902
		2903
		2904
		2905	state 136
		2906
		2907	rename_pin_decl -> rename_new_name . '=' '(' rename_pin_items ')' end_item (rule 330)
		2908
		2909	'=' shift, and go to state 238
		2910
		2911
		2912
		2913	state 137
		2914
		2915	rename_new_name -> netname . (rule 331)
		2916	rename_new_name -> netname . '(' bus_range ')' (rule 332)
		2917
		2918	'(' shift, and go to state 239
		2919
		2920	'(' [reduce using rule 331 (rename_new_name)]
		2921	$default reduce using rule 331 (rename_new_name)
		2922
		2923
		2924
		2925	state 138
		2926
		2927	ahdl_entityname_decl -> SUBDESIGN TXT_STRING . (rule 386)
		2928
		2929	$default reduce using rule 386 (ahdl_entityname_decl)
		2930
		2931
		2932
		2933	state 139
		2934
		2935	ahdl_name_part -> astring . (rule 394)
		2936
		2937	$default reduce using rule 394 (ahdl_name_part)
		2938
		2939
		2940
		2941	state 140
		2942
		2943	ahdl_port_decl -> '(' ahdl_port_list . ')' (rule 387)
		2944	ahdl_port_list -> ahdl_port_list . end_item ahdl_port_item (rule 388)
		2945
		2946	';' shift, and go to state 240
		2947	')' shift, and go to state 241
		2948
		2949	end_item go to state 242
		2950
		2951
		2952
		2953	state 141
		2954
		2955	ahdl_port_list -> ahdl_port_item . (rule 389)
		2956
		2957	$default reduce using rule 389 (ahdl_port_list)
		2958
		2959
		2960
		2961	state 142
		2962
		2963	ahdl_port_item -> ahdl_name_list . ':' pin_dir (rule 391)
		2964	ahdl_name_list -> ahdl_name_list . ',' ahdl_name_part (rule 392)
		2965
		2966	':' shift, and go to state 243
		2967	',' shift, and go to state 244
		2968
		2969
		2970
		2971	state 143
		2972
		2973	ahdl_name_list -> ahdl_name_part . (rule 393)
		2974
		2975	$default reduce using rule 393 (ahdl_name_list)
		2976
		2977
		2978
		2979	state 144
		2980
		2981	ahdl_region -> AHDL ahdl_chip_decls END . end_item (rule 380)
		2982
		2983	';' shift, and go to state 240
		2984
		2985	end_item go to state 245
		2986
		2987
		2988
		2989	state 145
		2990
		2991	ahdl_chip_decls -> ahdl_chip_decl ahdl_chip_decls . (rule 381)
		2992
		2993	$default reduce using rule 381 (ahdl_chip_decls)
		2994
		2995
		2996
		2997	state 146
		2998
		2999	hdl_compname_decl -> TXT_STRING . (rule 178)
		3000
		3001	$default reduce using rule 178 (hdl_compname_decl)
		3002
		3003
		3004
		3005	state 147
		3006
		3007	verilog_module_header -> MODULE hdl_compname_decl . verilog_port_list verilog_pindir_block (rule 228)
		3008
		3009	'(' shift, and go to state 246
		3010
		3011	$default reduce using rule 233 (verilog_port_list)
		3012
		3013	verilog_port_list go to state 247
		3014
		3015
		3016
		3017	state 148
		3018
		3019	verilog_region -> VERILOG verilog_blocks END . end_item (rule 222)
		3020
		3021	';' shift, and go to state 240
		3022
		3023	end_item go to state 248
		3024
		3025
		3026
		3027	state 149
		3028
		3029	verilog_blocks -> verilog_blocks verilog_block . (rule 223)
		3030
		3031	$default reduce using rule 223 (verilog_blocks)
		3032
		3033
		3034
		3035	state 150
		3036
		3037	verilog_module_decl -> verilog_module_header ENDMODULE . (rule 230)
		3038
		3039	$default reduce using rule 230 (verilog_module_decl)
		3040
		3041
		3042
		3043	state 151
		3044
		3045	verilog_wire_start -> WIRE . (rule 251)
		3046
		3047	$default reduce using rule 251 (verilog_wire_start)
		3048
		3049
		3050
		3051	state 152
		3052
		3053	verilog_toplevel_decl -> verilog_module_header verilog_module_body . ENDMODULE (rule 229)
		3054
		3055	ENDMODULE shift, and go to state 249
		3056
		3057
		3058
		3059	state 153
		3060
		3061	verilog_module_body -> verilog_wires_block . verilog_module_instance_block (rule 241)
		3062
		3063	QUOTED_STRING shift, and go to state 54
		3064	TXT_STRING shift, and go to state 55
		3065	NUM_STRING shift, and go to state 56
		3066
		3067	QUOTED_STRING [reduce using rule 256 (verilog_module_instances)]
		3068	TXT_STRING [reduce using rule 256 (verilog_module_instances)]
		3069	NUM_STRING [reduce using rule 256 (verilog_module_instances)]
		3070	$default reduce using rule 256 (verilog_module_instances)
		3071
		3072	astring go to state 250
		3073	verilog_module_instance_block go to state 251
		3074	verilog_module_instances go to state 252
		3075	verilog_module_instance go to state 253
		3076
		3077
		3078
		3079	state 154
		3080
		3081	verilog_wires_block -> verilog_wires_decl . verilog_wires_block (rule 247)
		3082	verilog_wires_block -> verilog_wires_decl . (rule 248)
		3083
		3084	WIRE shift, and go to state 151
		3085
		3086	ENDMODULE reduce using rule 248 (verilog_wires_block)
		3087	ENDMODULE [reduce using rule 249 (verilog_wires_block)]
		3088	QUOTED_STRING reduce using rule 248 (verilog_wires_block)
		3089	QUOTED_STRING [reduce using rule 249 (verilog_wires_block)]
		3090	TXT_STRING reduce using rule 248 (verilog_wires_block)
		3091	TXT_STRING [reduce using rule 249 (verilog_wires_block)]
		3092	NUM_STRING reduce using rule 248 (verilog_wires_block)
		3093	NUM_STRING [reduce using rule 249 (verilog_wires_block)]
		3094	$default reduce using rule 248 (verilog_wires_block)
		3095	verilog_wires_block go to state 254
		3096	verilog_wires_decl go to state 154
		3097	verilog_wire_start go to state 155
		3098
		3099
		3100
		3101	state 155
		3102
		3103	verilog_wires_decl -> verilog_wire_start . verilog_bus_expr hdl_signal_names verilog_wire_end (rule 250)
		3104
		3105	'[' shift, and go to state 255
		3106
		3107	$default reduce using rule 240 (verilog_bus_expr)
		3108
		3109	verilog_bus_expr go to state 256
		3110
		3111
		3112
		3113	state 156
		3114
		3115	generic_const_opt -> CONSTANT . (rule 271)
		3116
		3117	$default reduce using rule 271 (generic_const_opt)
		3118
		3119
		3120
		3121	state 157
		3122
		3123	global_generic_decl -> GENERIC @9 generic_defn_lines . END end_item (rule 265)
		3124	generic_defn_lines -> generic_defn_lines . end_item generic_defn_text (rule 268)
		3125
		3126	END shift, and go to state 257
		3127	';' shift, and go to state 240
		3128
		3129	end_item go to state 258
		3130
		3131
		3132
		3133	state 158
		3134
		3135	generic_defn_text -> generic_const_opt . generic_defn_name_list ':' generic_pindir_opt generic_defn_type (rule 275)
		3136
		3137	QUOTED_STRING shift, and go to state 54
		3138	TXT_STRING shift, and go to state 55
		3139	NUM_STRING shift, and go to state 56
		3140
		3141	astring go to state 259
		3142	generic_defn_name_list go to state 260
		3143	generic_defn_name go to state 261
		3144
		3145
		3146
		3147	state 159
		3148
		3149	generic_defn_lines -> generic_defn_text . (rule 269)
		3150
		3151	$default reduce using rule 269 (generic_defn_lines)
		3152
		3153
		3154
		3155	state 160
		3156
		3157	hdl_entityname_decl -> TXT_STRING . (rule 143)
		3158
		3159	$default reduce using rule 143 (hdl_entityname_decl)
		3160
		3161
		3162
		3163	state 161
		3164
		3165	vhdl_chip_decl -> ENTITY hdl_entityname_decl . IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
		3166
		3167	IS shift, and go to state 262
		3168
		3169
		3170
		3171	state 162
		3172
		3173	vhdl_architecture -> ARCHITECTURE astring . OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
		3174
		3175	OF shift, and go to state 263
		3176
		3177
		3178
		3179	state 163
		3180
		3181	vhdl_library_name -> astring . (rule 214)
		3182
		3183	$default reduce using rule 214 (vhdl_library_name)
		3184
		3185
		3186
		3187	state 164
		3188
		3189	vhdl_library_decl -> LIBRARY vhdl_library_list . ';' (rule 211)
		3190
		3191	';' shift, and go to state 264
		3192
		3193
		3194
		3195	state 165
		3196
		3197	vhdl_library_list -> vhdl_library_name . ',' vhdl_library_list (rule 212)
		3198	vhdl_library_list -> vhdl_library_name . (rule 213)
		3199
		3200	',' shift, and go to state 265
		3201
		3202	$default reduce using rule 213 (vhdl_library_list)
		3203
		3204
		3205
		3206	state 166
		3207
		3208	vhdl_lib_member -> astring . '.' astring '.' vhdl_lib_member_select (rule 218)
		3209	vhdl_lib_member -> astring . '.' vhdl_lib_member_select (rule 219)
		3210
		3211	'.' shift, and go to state 266
		3212
		3213
		3214
		3215	state 167
		3216
		3217	vhdl_use_decl -> USE vhdl_lib_members . ';' (rule 215)
		3218
		3219	';' shift, and go to state 267
		3220
		3221
		3222
		3223	state 168
		3224
		3225	vhdl_lib_members -> vhdl_lib_member . ',' vhdl_lib_members (rule 216)
		3226	vhdl_lib_members -> vhdl_lib_member . (rule 217)
		3227
		3228	',' shift, and go to state 268
		3229
		3230	$default reduce using rule 217 (vhdl_lib_members)
		3231
		3232
		3233
		3234	state 169
		3235
		3236	package_name -> astring . (rule 169)
		3237
		3238	$default reduce using rule 169 (package_name)
		3239
		3240
		3241
		3242	state 170
		3243
		3244	vhdl_package_decl -> PACKAGE package_name . IS vhdl_package_declarations END astring end_item (rule 168)
		3245
		3246	IS shift, and go to state 269
		3247
		3248
		3249
		3250	state 171
		3251
		3252	vhdl_region -> VHDL vhdl_blocks END . end_item (rule 132)
		3253
		3254	';' shift, and go to state 240
		3255
		3256	end_item go to state 270
		3257
		3258
		3259
		3260	state 172
		3261
		3262	vhdl_blocks -> vhdl_blocks vhdl_block . (rule 133)
		3263
		3264	$default reduce using rule 133 (vhdl_blocks)
		3265
		3266
		3267
		3268	state 173
		3269
		3270	device_declaration -> DEVICE . '=' astring end_item (rule 34)
		3271
		3272	'=' shift, and go to state 271
		3273
		3274
		3275
		3276	state 174
		3277
		3278	routing_status -> UNROUTED . end_item (rule 39)
		3279
		3280	';' shift, and go to state 240
		3281
		3282	end_item go to state 272
		3283
		3284
		3285
		3286	state 175
		3287
		3288	route_flags_info -> ROUTE_FLAGS . '=' route_flag_value end_item (rule 40)
		3289
		3290	'=' shift, and go to state 273
		3291
		3292
		3293
		3294	state 176
		3295
		3296	chip_generic_decl -> GENERIC . @10 generic_defn_lines END end_item (rule 267)
		3297
		3298	$default reduce using rule 266 (@10)
		3299
		3300	@10 go to state 274
		3301
		3302
		3303
		3304	state 177
		3305
		3306	chip_body -> BEGIN_TOK flex_chip_body . (rule 23)
		3307
		3308	$default reduce using rule 23 (chip_body)
		3309
		3310
		3311
		3312	state 178
		3313
		3314	flex_chip_body -> chip_info_lines . pin_declarations pin_equivalences END end_item (rule 25)
		3315	chip_info_lines -> chip_info_lines . chip_info_line (rule 27)
		3316
		3317	DEVICE shift, and go to state 173
		3318	UNROUTED shift, and go to state 174
		3319	ROUTE_FLAGS shift, and go to state 175
		3320	GENERIC shift, and go to state 176
		3321	GND shift, and go to state 131
		3322	VCC shift, and go to state 132
		3323	QUOTED_STRING shift, and go to state 54
		3324	TXT_STRING shift, and go to state 55
		3325	NUM_STRING shift, and go to state 56
		3326
		3327	GND [reduce using rule 44 (pin_declarations)]
		3328	VCC [reduce using rule 44 (pin_declarations)]
		3329	QUOTED_STRING [reduce using rule 44 (pin_declarations)]
		3330	TXT_STRING [reduce using rule 44 (pin_declarations)]
		3331	NUM_STRING [reduce using rule 44 (pin_declarations)]
		3332	$default reduce using rule 44 (pin_declarations)
		3333
		3334	astring go to state 133
		3335	chip_info_line go to state 275
		3336	device_declaration go to state 180
		3337	routing_status go to state 181
		3338	route_flags_info go to state 182
		3339	pin_declarations go to state 276
		3340	pin_declaration go to state 277
		3341	name_part go to state 278
		3342	chip_generic_decl go to state 183
		3343	netname go to state 279
		3344
		3345
		3346
		3347	state 179
		3348
		3349	chip_info_lines -> chip_info_line . (rule 28)
		3350
		3351	$default reduce using rule 28 (chip_info_lines)
		3352
		3353
		3354
		3355	state 180
		3356
		3357	chip_info_line -> device_declaration . (rule 30)
		3358
		3359	$default reduce using rule 30 (chip_info_line)
		3360
		3361
		3362
		3363	state 181
		3364
		3365	chip_info_line -> routing_status . (rule 32)
		3366
		3367	$default reduce using rule 32 (chip_info_line)
		3368
		3369
		3370
		3371	state 182
		3372
		3373	chip_info_line -> route_flags_info . (rule 31)
		3374
		3375	$default reduce using rule 31 (chip_info_line)
		3376
		3377
		3378
		3379	state 183
		3380
		3381	chip_info_line -> chip_generic_decl . (rule 33)
		3382
		3383	$default reduce using rule 33 (chip_info_line)
		3384
		3385
		3386
		3387	state 184
		3388
		3389	apex_device_declaration -> TO . AN astring apex_speed_grade (rule 55)
		3390
		3391	AN shift, and go to state 280
		3392
		3393
		3394
		3395	state 185
		3396
		3397	chip_body -> ASSIGNED apex_chip_body . (rule 24)
		3398
		3399	$default reduce using rule 24 (chip_body)
		3400
		3401
		3402
		3403	state 186
		3404
		3405	apex_chip_body -> apex_device_declaration . apex_info_lines (rule 54)
		3406
		3407	GND shift, and go to state 281
		3408	GND_RES_IO shift, and go to state 282
		3409	GND_RES_IN shift, and go to state 283
		3410	VCC shift, and go to state 284
		3411	TXT_STRING shift, and go to state 285
		3412
		3413	apex_info_lines go to state 286
		3414	apex_info_line go to state 287
		3415
		3416
		3417
		3418	state 187
		3419
		3420	alias_to_another_template -> ALIAS . astring end_item (rule 379)
		3421
		3422	QUOTED_STRING shift, and go to state 54
		3423	TXT_STRING shift, and go to state 55
		3424	NUM_STRING shift, and go to state 56
		3425
		3426	astring go to state 288
		3427
		3428
		3429
		3430	state 188
		3431
		3432	template_info_line -> chip_generic_decl . (rule 376)
		3433
		3434	$default reduce using rule 376 (template_info_line)
		3435
		3436
		3437
		3438	state 189
		3439
		3440	template_decl -> template_id_decl BEGIN_TOK template_info_lines . pin_declarations pin_equivalences END end_item (rule 371)
		3441	template_info_lines -> template_info_lines . template_info_line (rule 374)
		3442
		3443	ALIAS shift, and go to state 187
		3444	GENERIC shift, and go to state 176
		3445	GND shift, and go to state 131
		3446	VCC shift, and go to state 132
		3447	QUOTED_STRING shift, and go to state 54
		3448	TXT_STRING shift, and go to state 55
		3449	NUM_STRING shift, and go to state 56
		3450
		3451	END reduce using rule 44 (pin_declarations)
		3452	END [reduce using rule 378 (template_info_line)]
		3453	ALIAS [reduce using rule 378 (template_info_line)]
		3454	GENERIC [reduce using rule 378 (template_info_line)]
		3455	EQUIVALENT reduce using rule 44 (pin_declarations)
		3456	EQUIVALENT [reduce using rule 378 (template_info_line)]
		3457	GND [reduce using rule 44 (pin_declarations)]
		3458	GND [reduce using rule 378 (template_info_line)]
		3459	VCC [reduce using rule 44 (pin_declarations)]
		3460	VCC [reduce using rule 378 (template_info_line)]
		3461	QUOTED_STRING [reduce using rule 44 (pin_declarations)]
		3462	QUOTED_STRING [reduce using rule 378 (template_info_line)]
		3463	TXT_STRING [reduce using rule 44 (pin_declarations)]
		3464	TXT_STRING [reduce using rule 378 (template_info_line)]
		3465	NUM_STRING [reduce using rule 44 (pin_declarations)]
		3466	NUM_STRING [reduce using rule 378 (template_info_line)]
		3467	$default reduce using rule 44 (pin_declarations)
		3468	astring go to state 133
		3469	pin_declarations go to state 289
		3470	pin_declaration go to state 277
		3471	name_part go to state 278
		3472	chip_generic_decl go to state 188
		3473	netname go to state 279
		3474	template_info_line go to state 290
		3475	alias_to_another_template go to state 191
		3476
		3477
		3478
		3479	state 190
		3480
		3481	template_info_lines -> template_info_line . (rule 375)
		3482
		3483	$default reduce using rule 375 (template_info_lines)
		3484
		3485
		3486
		3487	state 191
		3488
		3489	template_info_line -> alias_to_another_template . (rule 377)
		3490
		3491	$default reduce using rule 377 (template_info_line)
		3492
		3493
		3494
		3495	state 192
		3496
		3497	expr1 -> QUOTE astring QUOTE . (rule 85)
		3498
		3499	$default reduce using rule 85 (expr1)
		3500
		3501
		3502
		3503	state 193
		3504
		3505	primary_expr -> '(' expr ')' . (rule 88)
		3506
		3507	$default reduce using rule 88 (primary_expr)
		3508
		3509
		3510
		3511	state 194
		3512
		3513	mult_expr -> mult_expr TO_POW primary_expr . (rule 99)
		3514
		3515	$default reduce using rule 99 (mult_expr)
		3516
		3517
		3518
		3519	state 195
		3520
		3521	mult_expr -> mult_expr '*' primary_expr . (rule 96)
		3522
		3523	$default reduce using rule 96 (mult_expr)
		3524
		3525
		3526
		3527	state 196
		3528
		3529	mult_expr -> mult_expr '/' primary_expr . (rule 97)
		3530
		3531	$default reduce using rule 97 (mult_expr)
		3532
		3533
		3534
		3535	state 197
		3536
		3537	mult_expr -> mult_expr '%' primary_expr . (rule 98)
		3538
		3539	$default reduce using rule 98 (mult_expr)
		3540
		3541
		3542
		3543	state 198
		3544
		3545	mult_expr -> mult_expr . '*' primary_expr (rule 96)
		3546	mult_expr -> mult_expr . '/' primary_expr (rule 97)
		3547	mult_expr -> mult_expr . '%' primary_expr (rule 98)
		3548	mult_expr -> mult_expr . TO_POW primary_expr (rule 99)
		3549	add_expr -> add_expr '-' mult_expr . (rule 102)
		3550
		3551	TO_POW shift, and go to state 99
		3552	'*' shift, and go to state 100
		3553	'/' shift, and go to state 101
		3554	'%' shift, and go to state 102
		3555
		3556	TO_POW [reduce using rule 102 (add_expr)]
		3557	'*' [reduce using rule 102 (add_expr)]
		3558	'/' [reduce using rule 102 (add_expr)]
		3559	'%' [reduce using rule 102 (add_expr)]
		3560	$default reduce using rule 102 (add_expr)
		3561
		3562
		3563
		3564	state 199
		3565
		3566	mult_expr -> mult_expr . '*' primary_expr (rule 96)
		3567	mult_expr -> mult_expr . '/' primary_expr (rule 97)
		3568	mult_expr -> mult_expr . '%' primary_expr (rule 98)
		3569	mult_expr -> mult_expr . TO_POW primary_expr (rule 99)
		3570	add_expr -> add_expr '+' mult_expr . (rule 101)
		3571
		3572	TO_POW shift, and go to state 99
		3573	'*' shift, and go to state 100
		3574	'/' shift, and go to state 101
		3575	'%' shift, and go to state 102
		3576
		3577	TO_POW [reduce using rule 101 (add_expr)]
		3578	'*' [reduce using rule 101 (add_expr)]
		3579	'/' [reduce using rule 101 (add_expr)]
		3580	'%' [reduce using rule 101 (add_expr)]
		3581	$default reduce using rule 101 (add_expr)
		3582
		3583
		3584
		3585	state 200
		3586
		3587	add_expr -> add_expr . '+' mult_expr (rule 101)
		3588	add_expr -> add_expr . '-' mult_expr (rule 102)
		3589	shift_expr -> shift_expr SHL add_expr . (rule 104)
		3590
		3591	'-' shift, and go to state 103
		3592	'+' shift, and go to state 104
		3593
		3594	'-' [reduce using rule 104 (shift_expr)]
		3595	'+' [reduce using rule 104 (shift_expr)]
		3596	$default reduce using rule 104 (shift_expr)
		3597
		3598
		3599
		3600	state 201
		3601
		3602	add_expr -> add_expr . '+' mult_expr (rule 101)
		3603	add_expr -> add_expr . '-' mult_expr (rule 102)
		3604	shift_expr -> shift_expr SHR add_expr . (rule 105)
		3605
		3606	'-' shift, and go to state 103
		3607	'+' shift, and go to state 104
		3608
		3609	'-' [reduce using rule 105 (shift_expr)]
		3610	'+' [reduce using rule 105 (shift_expr)]
		3611	$default reduce using rule 105 (shift_expr)
		3612
		3613
		3614
		3615	state 202
		3616
		3617	shift_expr -> shift_expr . SHL add_expr (rule 104)
		3618	shift_expr -> shift_expr . SHR add_expr (rule 105)
		3619	relational_expr -> relational_expr '>' shift_expr . (rule 107)
		3620
		3621	SHL shift, and go to state 105
		3622	SHR shift, and go to state 106
		3623
		3624	SHL [reduce using rule 107 (relational_expr)]
		3625	SHR [reduce using rule 107 (relational_expr)]
		3626	$default reduce using rule 107 (relational_expr)
		3627
		3628
		3629
		3630	state 203
		3631
		3632	shift_expr -> shift_expr . SHL add_expr (rule 104)
		3633	shift_expr -> shift_expr . SHR add_expr (rule 105)
		3634	relational_expr -> relational_expr '<' shift_expr . (rule 108)
		3635
		3636	SHL shift, and go to state 105
		3637	SHR shift, and go to state 106
		3638
		3639	SHL [reduce using rule 108 (relational_expr)]
		3640	SHR [reduce using rule 108 (relational_expr)]
		3641	$default reduce using rule 108 (relational_expr)
		3642
		3643
		3644
		3645	state 204
		3646
		3647	relational_expr -> relational_expr . '>' shift_expr (rule 107)
		3648	relational_expr -> relational_expr . '<' shift_expr (rule 108)
		3649	equality_expr -> equality_expr EQ_EQ relational_expr . (rule 110)
		3650
		3651	'>' shift, and go to state 107
		3652	'<' shift, and go to state 108
		3653
		3654	'>' [reduce using rule 110 (equality_expr)]
		3655	'<' [reduce using rule 110 (equality_expr)]
		3656	$default reduce using rule 110 (equality_expr)
		3657
		3658
		3659
		3660	state 205
		3661
		3662	relational_expr -> relational_expr . '>' shift_expr (rule 107)
		3663	relational_expr -> relational_expr . '<' shift_expr (rule 108)
		3664	equality_expr -> equality_expr N_EQ relational_expr . (rule 111)
		3665
		3666	'>' shift, and go to state 107
		3667	'<' shift, and go to state 108
		3668
		3669	'>' [reduce using rule 111 (equality_expr)]
		3670	'<' [reduce using rule 111 (equality_expr)]
		3671	$default reduce using rule 111 (equality_expr)
		3672
		3673
		3674
		3675	state 206
		3676
		3677	equality_expr -> equality_expr . EQ_EQ relational_expr (rule 110)
		3678	equality_expr -> equality_expr . N_EQ relational_expr (rule 111)
		3679	and_expr -> and_expr '&' equality_expr . (rule 113)
		3680
		3681	EQ_EQ shift, and go to state 109
		3682	N_EQ shift, and go to state 110
		3683
		3684	EQ_EQ [reduce using rule 113 (and_expr)]
		3685	N_EQ [reduce using rule 113 (and_expr)]
		3686	$default reduce using rule 113 (and_expr)
		3687
		3688
		3689
		3690	state 207
		3691
		3692	and_expr -> and_expr . '&' equality_expr (rule 113)
		3693	exor_expr -> exor_expr '^' and_expr . (rule 115)
		3694
		3695	'&' shift, and go to state 111
		3696
		3697	'&' [reduce using rule 115 (exor_expr)]
		3698	$default reduce using rule 115 (exor_expr)
		3699
		3700
		3701
		3702	state 208
		3703
		3704	or_expr -> or_expr . '\|' or_expr (rule 117)
		3705	or_expr -> or_expr '\|' or_expr . (rule 117)
		3706
		3707	'\|' shift, and go to state 113
		3708
		3709	'\|' [reduce using rule 117 (or_expr)]
		3710	$default reduce using rule 117 (or_expr)
		3711
		3712
		3713
		3714	state 209
		3715
		3716	or_expr -> or_expr . '\|' or_expr (rule 117)
		3717	logand_expr -> logand_expr LOG_AND or_expr . (rule 119)
		3718
		3719	'\|' shift, and go to state 113
		3720
		3721	'\|' [reduce using rule 119 (logand_expr)]
		3722	$default reduce using rule 119 (logand_expr)
		3723
		3724
		3725
		3726	state 210
		3727
		3728	logand_expr -> logand_expr . LOG_AND or_expr (rule 119)
		3729	logor_expr -> logor_expr LOG_OR logand_expr . (rule 121)
		3730
		3731	LOG_AND shift, and go to state 114
		3732
		3733	LOG_AND [reduce using rule 121 (logor_expr)]
		3734	$default reduce using rule 121 (logor_expr)
		3735
		3736
		3737
		3738	state 211
		3739
		3740	cond_expr -> logor_expr '?' colon_expr . (rule 122)
		3741
		3742	$default reduce using rule 122 (cond_expr)
		3743
		3744
		3745
		3746	state 212
		3747
		3748	colon_expr -> expr . ':' expr (rule 123)
		3749
		3750	':' shift, and go to state 291
		3751
		3752
		3753
		3754	state 213
		3755
		3756	simple_range_expr -> expr TO expr . (rule 86)
		3757
		3758	$default reduce using rule 86 (simple_range_expr)
		3759
		3760
		3761
		3762	state 214
		3763
		3764	simple_range_expr -> expr DOWNTO expr . (rule 87)
		3765
		3766	$default reduce using rule 87 (simple_range_expr)
		3767
		3768
		3769
		3770	state 215
		3771
		3772	components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines END . end_item (rule 300)
		3773
		3774	';' shift, and go to state 240
		3775
		3776	end_item go to state 292
		3777
		3778
		3779
		3780	state 216
		3781
		3782	comp_defn_lines -> comp_defn_lines comp_defn_line . (rule 301)
		3783
		3784	$default reduce using rule 301 (comp_defn_lines)
		3785
		3786
		3787
		3788	state 217
		3789
		3790	comp_defn_line -> chip_ident ':' . chip_name chip_type chip_value end_item (rule 304)
		3791
		3792	QUOTED_STRING shift, and go to state 54
		3793	TXT_STRING shift, and go to state 55
		3794	NUM_STRING shift, and go to state 56
		3795
		3796	astring go to state 293
		3797	chip_name go to state 294
		3798
		3799
		3800
		3801	state 218
		3802
		3803	conn_decl -> CONN . conn_ident conn_name last_route_status end_item nodelist END_CONN @17 end_item (rule 352)
		3804
		3805	GND shift, and go to state 131
		3806	VCC shift, and go to state 132
		3807	QUOTED_STRING shift, and go to state 54
		3808	TXT_STRING shift, and go to state 55
		3809	NUM_STRING shift, and go to state 56
		3810
		3811	astring go to state 133
		3812	conn_ident go to state 295
		3813	netname go to state 296
		3814
		3815
		3816
		3817	state 219
		3818
		3819	unrouted_decl -> UNROUTED . (rule 347)
		3820
		3821	$default reduce using rule 347 (unrouted_decl)
		3822
		3823
		3824
		3825	state 220
		3826
		3827	routed_decl -> ROUTED . (rule 346)
		3828
		3829	$default reduce using rule 346 (routed_decl)
		3830
		3831
		3832
		3833	state 221
		3834
		3835	named_decl -> NAMED . (rule 348)
		3836
		3837	$default reduce using rule 348 (named_decl)
		3838
		3839
		3840
		3841	state 222
		3842
		3843	nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block . END end_item (rule 338)
		3844	connection_block -> connection_block . connection_block_item (rule 339)
		3845
		3846	END shift, and go to state 297
		3847	CONN shift, and go to state 218
		3848	UNROUTED shift, and go to state 219
		3849	ROUTED shift, and go to state 220
		3850	NAMED shift, and go to state 221
		3851
		3852	END [reduce using rule 345 (connection_block_item)]
		3853	CONN [reduce using rule 345 (connection_block_item)]
		3854	UNROUTED [reduce using rule 345 (connection_block_item)]
		3855	ROUTED [reduce using rule 345 (connection_block_item)]
		3856	NAMED [reduce using rule 345 (connection_block_item)]
		3857	$default reduce using rule 345 (connection_block_item)
		3858
		3859	connection_block_item go to state 298
		3860	routed_decl go to state 224
		3861	unrouted_decl go to state 225
		3862	named_decl go to state 226
		3863	conn_decls go to state 227
		3864	conn_decl go to state 228
		3865
		3866
		3867
		3868	state 223
		3869
		3870	connection_block -> connection_block_item . (rule 340)
		3871
		3872	$default reduce using rule 340 (connection_block)
		3873
		3874
		3875
		3876	state 224
		3877
		3878	connection_block_item -> routed_decl . (rule 341)
		3879
		3880	$default reduce using rule 341 (connection_block_item)
		3881
		3882
		3883
		3884	state 225
		3885
		3886	connection_block_item -> unrouted_decl . (rule 342)
		3887
		3888	$default reduce using rule 342 (connection_block_item)
		3889
		3890
		3891
		3892	state 226
		3893
		3894	connection_block_item -> named_decl . (rule 343)
		3895
		3896	$default reduce using rule 343 (connection_block_item)
		3897
		3898
		3899
		3900	state 227
		3901
		3902	connection_block_item -> conn_decls . (rule 344)
		3903	conn_decls -> conn_decls . conn_decl (rule 349)
		3904
		3905	CONN shift, and go to state 218
		3906
		3907	CONN [reduce using rule 344 (connection_block_item)]
		3908	$default reduce using rule 344 (connection_block_item)
		3909
		3910	conn_decl go to state 299
		3911
		3912
		3913
		3914	state 228
		3915
		3916	conn_decls -> conn_decl . (rule 350)
		3917
		3918	$default reduce using rule 350 (conn_decls)
		3919
		3920
		3921
		3922	state 229
		3923
		3924	join_decl -> CONN astring . astring @15 end_item (rule 315)
		3925
		3926	QUOTED_STRING shift, and go to state 54
		3927	TXT_STRING shift, and go to state 55
		3928	NUM_STRING shift, and go to state 56
		3929
		3930	astring go to state 300
		3931
		3932
		3933
		3934	state 230
		3935
		3936	vhdl_concurrent_assignment -> astring . SIG_ASSIGN astring end_item (rule 210)
		3937
		3938	SIG_ASSIGN shift, and go to state 301
		3939
		3940
		3941
		3942	state 231
		3943
		3944	join_decl -> VHDL_CONN vhdl_concurrent_assignment . (rule 316)
		3945
		3946	$default reduce using rule 316 (join_decl)
		3947
		3948
		3949
		3950	state 232
		3951
		3952	joined_decl -> JOINED_NETS BEGIN_TOK join_decls END . end_item (rule 309)
		3953
		3954	';' shift, and go to state 240
		3955
		3956	end_item go to state 302
		3957
		3958
		3959
		3960	state 233
		3961
		3962	join_decls -> join_decls join_decl . (rule 310)
		3963
		3964	$default reduce using rule 310 (join_decls)
		3965
		3966
		3967
		3968	state 234
		3969
		3970	join_decl -> alias_part root_net . '=' '(' joined_nets ')' end_item (rule 313)
		3971
		3972	'=' shift, and go to state 303
		3973
		3974
		3975
		3976	state 235
		3977
		3978	root_net -> netname . (rule 320)
		3979
		3980	$default reduce using rule 320 (root_net)
		3981
		3982
		3983
		3984	state 236
		3985
		3986	rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls END . end_item (rule 327)
		3987
		3988	';' shift, and go to state 240
		3989
		3990	end_item go to state 304
		3991
		3992
		3993
		3994	state 237
		3995
		3996	rename_pin_decls -> rename_pin_decls rename_pin_decl . (rule 328)
		3997
		3998	$default reduce using rule 328 (rename_pin_decls)
		3999
		4000
		4001
		4002	state 238
		4003
		4004	rename_pin_decl -> rename_new_name '=' . '(' rename_pin_items ')' end_item (rule 330)
		4005
		4006	'(' shift, and go to state 305
		4007
		4008
		4009
		4010	state 239
		4011
		4012	rename_new_name -> netname '(' . bus_range ')' (rule 332)
		4013
		4014	TRUE shift, and go to state 27
		4015	FALSE shift, and go to state 28
		4016	QUOTE shift, and go to state 29
		4017	QUOTED_STRING shift, and go to state 30
		4018	TXT_STRING shift, and go to state 31
		4019	NUM_STRING shift, and go to state 32
		4020	'~' shift, and go to state 33
		4021	'(' shift, and go to state 34
		4022	'-' shift, and go to state 35
		4023
		4024	bus_range go to state 306
		4025	expr1 go to state 39
		4026	simple_range_expr go to state 40
		4027	primary_expr go to state 41
		4028	mult_expr go to state 42
		4029	add_expr go to state 43
		4030	shift_expr go to state 44
		4031	relational_expr go to state 45
		4032	equality_expr go to state 46
		4033	and_expr go to state 47
		4034	exor_expr go to state 48
		4035	or_expr go to state 49
		4036	logand_expr go to state 50
		4037	logor_expr go to state 51
		4038	cond_expr go to state 52
		4039	expr go to state 53
		4040
		4041
		4042
		4043	state 240
		4044
		4045	end_item -> ';' . (rule 38)
		4046
		4047	$default reduce using rule 38 (end_item)
		4048
		4049
		4050
		4051	state 241
		4052
		4053	ahdl_port_decl -> '(' ahdl_port_list ')' . (rule 387)
		4054
		4055	$default reduce using rule 387 (ahdl_port_decl)
		4056
		4057
		4058
		4059	state 242
		4060
		4061	ahdl_port_list -> ahdl_port_list end_item . ahdl_port_item (rule 388)
		4062
		4063	QUOTED_STRING shift, and go to state 54
		4064	TXT_STRING shift, and go to state 55
		4065	NUM_STRING shift, and go to state 56
		4066
		4067	astring go to state 139
		4068	ahdl_port_item go to state 307
		4069	ahdl_name_list go to state 142
		4070	ahdl_name_part go to state 143
		4071
		4072
		4073
		4074	state 243
		4075
		4076	ahdl_port_item -> ahdl_name_list ':' . pin_dir (rule 391)
		4077
		4078	PINDIR shift, and go to state 308
		4079
		4080	pin_dir go to state 309
		4081
		4082
		4083
		4084	state 244
		4085
		4086	ahdl_name_list -> ahdl_name_list ',' . ahdl_name_part (rule 392)
		4087
		4088	QUOTED_STRING shift, and go to state 54
		4089	TXT_STRING shift, and go to state 55
		4090	NUM_STRING shift, and go to state 56
		4091
		4092	astring go to state 139
		4093	ahdl_name_part go to state 310
		4094
		4095
		4096
		4097	state 245
		4098
		4099	ahdl_region -> AHDL ahdl_chip_decls END end_item . (rule 380)
		4100
		4101	$default reduce using rule 380 (ahdl_region)
		4102
		4103
		4104
		4105	state 246
		4106
		4107	verilog_port_list -> '(' . verilog_ports ')' ';' @7 verilog_pindir_block (rule 232)
		4108
		4109	GND shift, and go to state 131
		4110	VCC shift, and go to state 132
		4111	QUOTED_STRING shift, and go to state 54
		4112	TXT_STRING shift, and go to state 55
		4113	NUM_STRING shift, and go to state 56
		4114
		4115	$default reduce using rule 236 (verilog_ports)
		4116
		4117	astring go to state 133
		4118	hdl_name_part go to state 311
		4119	verilog_ports go to state 312
		4120	verilog_port go to state 313
		4121	netname go to state 314
		4122
		4123
		4124
		4125	state 247
		4126
		4127	verilog_module_header -> MODULE hdl_compname_decl verilog_port_list . verilog_pindir_block (rule 228)
		4128
		4129	PINDIR shift, and go to state 308
		4130
		4131	PINDIR [reduce using rule 244 (verilog_pindir_block)]
		4132	$default reduce using rule 244 (verilog_pindir_block)
		4133
		4134	pin_dir go to state 315
		4135	verilog_pindir_block go to state 316
		4136	verilog_pindir_decl go to state 317
		4137
		4138
		4139
		4140	state 248
		4141
		4142	verilog_region -> VERILOG verilog_blocks END end_item . (rule 222)
		4143
		4144	$default reduce using rule 222 (verilog_region)
		4145
		4146
		4147
		4148	state 249
		4149
		4150	verilog_toplevel_decl -> verilog_module_header verilog_module_body ENDMODULE . (rule 229)
		4151
		4152	$default reduce using rule 229 (verilog_toplevel_decl)
		4153
		4154
		4155
		4156	state 250
		4157
		4158	verilog_module_instance -> astring . astring '(' verilog_port_map_list ')' ';' (rule 257)
		4159
		4160	QUOTED_STRING shift, and go to state 54
		4161	TXT_STRING shift, and go to state 55
		4162	NUM_STRING shift, and go to state 56
		4163
		4164	astring go to state 318
		4165
		4166
		4167
		4168	state 251
		4169
		4170	verilog_module_body -> verilog_wires_block verilog_module_instance_block . (rule 241)
		4171
		4172	$default reduce using rule 241 (verilog_module_body)
		4173
		4174
		4175
		4176	state 252
		4177
		4178	verilog_module_instance_block -> verilog_module_instances . (rule 253)
		4179	verilog_module_instances -> verilog_module_instances . verilog_module_instance (rule 254)
		4180
		4181	QUOTED_STRING shift, and go to state 54
		4182	TXT_STRING shift, and go to state 55
		4183	NUM_STRING shift, and go to state 56
		4184
		4185	$default reduce using rule 253 (verilog_module_instance_block)
		4186
		4187	astring go to state 250
		4188	verilog_module_instance go to state 319
		4189
		4190
		4191
		4192	state 253
		4193
		4194	verilog_module_instances -> verilog_module_instance . (rule 255)
		4195
		4196	$default reduce using rule 255 (verilog_module_instances)
		4197
		4198
		4199
		4200	state 254
		4201
		4202	verilog_wires_block -> verilog_wires_decl verilog_wires_block . (rule 247)
		4203
		4204	$default reduce using rule 247 (verilog_wires_block)
		4205
		4206
		4207
		4208	state 255
		4209
		4210	verilog_bus_expr -> '[' . expr ']' (rule 238)
		4211	verilog_bus_expr -> '[' . expr ':' expr ']' (rule 239)
		4212
		4213	TRUE shift, and go to state 27
		4214	FALSE shift, and go to state 28
		4215	TXT_STRING shift, and go to state 31
		4216	NUM_STRING shift, and go to state 32
		4217	'~' shift, and go to state 33
		4218	'(' shift, and go to state 34
		4219	'-' shift, and go to state 35
		4220
		4221	primary_expr go to state 41
		4222	mult_expr go to state 42
		4223	add_expr go to state 43
		4224	shift_expr go to state 44
		4225	relational_expr go to state 45
		4226	equality_expr go to state 46
		4227	and_expr go to state 47
		4228	exor_expr go to state 48
		4229	or_expr go to state 49
		4230	logand_expr go to state 50
		4231	logor_expr go to state 51
		4232	cond_expr go to state 52
		4233	expr go to state 320
		4234
		4235
		4236
		4237	state 256
		4238
		4239	verilog_wires_decl -> verilog_wire_start verilog_bus_expr . hdl_signal_names verilog_wire_end (rule 250)
		4240
		4241	QUOTED_STRING shift, and go to state 54
		4242	TXT_STRING shift, and go to state 55
		4243	NUM_STRING shift, and go to state 56
		4244
		4245	astring go to state 321
		4246	hdl_signal_names go to state 322
		4247	hdl_signal_name go to state 323
		4248
		4249
		4250
		4251	state 257
		4252
		4253	global_generic_decl -> GENERIC @9 generic_defn_lines END . end_item (rule 265)
		4254
		4255	';' shift, and go to state 240
		4256
		4257	end_item go to state 324
		4258
		4259
		4260
		4261	state 258
		4262
		4263	generic_defn_lines -> generic_defn_lines end_item . generic_defn_text (rule 268)
		4264
		4265	CONSTANT shift, and go to state 156
		4266
		4267	$default reduce using rule 272 (generic_const_opt)
		4268
		4269	generic_const_opt go to state 158
		4270	generic_defn_text go to state 325
		4271
		4272
		4273
		4274	state 259
		4275
		4276	generic_defn_name -> astring . (rule 278)
		4277
		4278	$default reduce using rule 278 (generic_defn_name)
		4279
		4280
		4281
		4282	state 260
		4283
		4284	generic_defn_text -> generic_const_opt generic_defn_name_list . ':' generic_pindir_opt generic_defn_type (rule 275)
		4285	generic_defn_name_list -> generic_defn_name_list . ',' generic_defn_name (rule 276)
		4286
		4287	':' shift, and go to state 326
		4288	',' shift, and go to state 327
		4289
		4290
		4291
		4292	state 261
		4293
		4294	generic_defn_name_list -> generic_defn_name . (rule 277)
		4295
		4296	$default reduce using rule 277 (generic_defn_name_list)
		4297
		4298
		4299
		4300	state 262
		4301
		4302	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS . @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
		4303
		4304	$default reduce using rule 141 (@2)
		4305
		4306	@2 go to state 328
		4307
		4308
		4309
		4310	state 263
		4311
		4312	vhdl_architecture -> ARCHITECTURE astring OF . astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
		4313
		4314	QUOTED_STRING shift, and go to state 54
		4315	TXT_STRING shift, and go to state 55
		4316	NUM_STRING shift, and go to state 56
		4317
		4318	astring go to state 329
		4319
		4320
		4321
		4322	state 264
		4323
		4324	vhdl_library_decl -> LIBRARY vhdl_library_list ';' . (rule 211)
		4325
		4326	$default reduce using rule 211 (vhdl_library_decl)
		4327
		4328
		4329
		4330	state 265
		4331
		4332	vhdl_library_list -> vhdl_library_name ',' . vhdl_library_list (rule 212)
		4333
		4334	QUOTED_STRING shift, and go to state 54
		4335	TXT_STRING shift, and go to state 55
		4336	NUM_STRING shift, and go to state 56
		4337
		4338	astring go to state 163
		4339	vhdl_library_list go to state 330
		4340	vhdl_library_name go to state 165
		4341
		4342
		4343
		4344	state 266
		4345
		4346	vhdl_lib_member -> astring '.' . astring '.' vhdl_lib_member_select (rule 218)
		4347	vhdl_lib_member -> astring '.' . vhdl_lib_member_select (rule 219)
		4348
		4349	ALL shift, and go to state 331
		4350	QUOTED_STRING shift, and go to state 54
		4351	TXT_STRING shift, and go to state 55
		4352	NUM_STRING shift, and go to state 56
		4353
		4354	astring go to state 332
		4355	vhdl_lib_member_select go to state 333
		4356
		4357
		4358
		4359	state 267
		4360
		4361	vhdl_use_decl -> USE vhdl_lib_members ';' . (rule 215)
		4362
		4363	$default reduce using rule 215 (vhdl_use_decl)
		4364
		4365
		4366
		4367	state 268
		4368
		4369	vhdl_lib_members -> vhdl_lib_member ',' . vhdl_lib_members (rule 216)
		4370
		4371	QUOTED_STRING shift, and go to state 54
		4372	TXT_STRING shift, and go to state 55
		4373	NUM_STRING shift, and go to state 56
		4374
		4375	astring go to state 166
		4376	vhdl_lib_members go to state 334
		4377	vhdl_lib_member go to state 168
		4378
		4379
		4380
		4381	state 269
		4382
		4383	vhdl_package_decl -> PACKAGE package_name IS . vhdl_package_declarations END astring end_item (rule 168)
		4384
		4385	SIGNAL shift, and go to state 335
		4386	CONSTANT shift, and go to state 336
		4387	COMPONENT shift, and go to state 337
		4388	FOR shift, and go to state 338
		4389
		4390	SIGNAL [reduce using rule 172 (vhdl_package_declarations)]
		4391	CONSTANT [reduce using rule 172 (vhdl_package_declarations)]
		4392	COMPONENT [reduce using rule 172 (vhdl_package_declarations)]
		4393	FOR [reduce using rule 172 (vhdl_package_declarations)]
		4394	$default reduce using rule 172 (vhdl_package_declarations)
		4395
		4396	vhdl_package_declarations go to state 339
		4397	vhdl_package_decl_item go to state 340
		4398	vhdl_component_decl go to state 341
		4399	vhdl_constant_decl go to state 342
		4400	vhdl_signal_decl go to state 343
		4401	vhdl_configuration_decl go to state 344
		4402
		4403
		4404
		4405	state 270
		4406
		4407	vhdl_region -> VHDL vhdl_blocks END end_item . (rule 132)
		4408
		4409	$default reduce using rule 132 (vhdl_region)
		4410
		4411
		4412
		4413	state 271
		4414
		4415	device_declaration -> DEVICE '=' . astring end_item (rule 34)
		4416
		4417	QUOTED_STRING shift, and go to state 54
		4418	TXT_STRING shift, and go to state 55
		4419	NUM_STRING shift, and go to state 56
		4420
		4421	astring go to state 345
		4422
		4423
		4424
		4425	state 272
		4426
		4427	routing_status -> UNROUTED end_item . (rule 39)
		4428
		4429	$default reduce using rule 39 (routing_status)
		4430
		4431
		4432
		4433	state 273
		4434
		4435	route_flags_info -> ROUTE_FLAGS '=' . route_flag_value end_item (rule 40)
		4436
		4437	NUM_STRING shift, and go to state 346
		4438
		4439	route_flag_value go to state 347
		4440
		4441
		4442
		4443	state 274
		4444
		4445	chip_generic_decl -> GENERIC @10 . generic_defn_lines END end_item (rule 267)
		4446
		4447	CONSTANT shift, and go to state 156
		4448
		4449	END reduce using rule 270 (generic_defn_lines)
		4450	';' reduce using rule 270 (generic_defn_lines)
		4451	$default reduce using rule 272 (generic_const_opt)
		4452	generic_defn_lines go to state 348
		4453	generic_const_opt go to state 158
		4454	generic_defn_text go to state 159
		4455
		4456
		4457
		4458	state 275
		4459
		4460	chip_info_lines -> chip_info_lines chip_info_line . (rule 27)
		4461
		4462	$default reduce using rule 27 (chip_info_lines)
		4463
		4464
		4465
		4466	state 276
		4467
		4468	flex_chip_body -> chip_info_lines pin_declarations . pin_equivalences END end_item (rule 25)
		4469	pin_declarations -> pin_declarations . pin_declaration (rule 42)
		4470
		4471	EQUIVALENT shift, and go to state 349
		4472	GND shift, and go to state 131
		4473	VCC shift, and go to state 132
		4474	QUOTED_STRING shift, and go to state 54
		4475	TXT_STRING shift, and go to state 55
		4476	NUM_STRING shift, and go to state 56
		4477
		4478	$default reduce using rule 37 (pin_equivalences)
		4479
		4480	astring go to state 133
		4481	pin_equivalences go to state 350
		4482	pin_declaration go to state 351
		4483	name_part go to state 278
		4484	pin_equivalence go to state 352
		4485	netname go to state 279
		4486
		4487
		4488
		4489	state 277
		4490
		4491	pin_declarations -> pin_declaration . (rule 43)
		4492
		4493	$default reduce using rule 43 (pin_declarations)
		4494
		4495
		4496
		4497	state 278
		4498
		4499	pin_declaration -> name_part . ':' pin_rest end_item (rule 45)
		4500
		4501	':' shift, and go to state 353
		4502
		4503
		4504
		4505	state 279
		4506
		4507	name_part -> netname . (rule 46)
		4508
		4509	$default reduce using rule 46 (name_part)
		4510
		4511
		4512
		4513	state 280
		4514
		4515	apex_device_declaration -> TO AN . astring apex_speed_grade (rule 55)
		4516
		4517	QUOTED_STRING shift, and go to state 54
		4518	TXT_STRING shift, and go to state 55
		4519	NUM_STRING shift, and go to state 56
		4520
		4521	astring go to state 354
		4522
		4523
		4524
		4525	state 281
		4526
		4527	apex_info_line -> GND . ':' astring more_colons (rule 60)
		4528
		4529	':' shift, and go to state 355
		4530
		4531
		4532
		4533	state 282
		4534
		4535	apex_info_line -> GND_RES_IO . ':' astring more_colons (rule 61)
		4536
		4537	':' shift, and go to state 356
		4538
		4539
		4540
		4541	state 283
		4542
		4543	apex_info_line -> GND_RES_IN . ':' astring more_colons (rule 62)
		4544
		4545	':' shift, and go to state 357
		4546
		4547
		4548
		4549	state 284
		4550
		4551	apex_info_line -> VCC . ':' astring ':' NUM_STRING (rule 63)
		4552	apex_info_line -> VCC . ':' astring more_colons (rule 64)
		4553
		4554	':' shift, and go to state 358
		4555
		4556
		4557
		4558	state 285
		4559
		4560	apex_info_line -> TXT_STRING . ':' astring more_colons (rule 65)
		4561	apex_info_line -> TXT_STRING . ':' astring ':' PINDIR ':' astring ':' (rule 66)
		4562	apex_info_line -> TXT_STRING . '[' expr ']' ':' astring ':' PINDIR ':' astring ':' (rule 67)
		4563
		4564	':' shift, and go to state 359
		4565	'[' shift, and go to state 360
		4566
		4567
		4568
		4569	state 286
		4570
		4571	apex_chip_body -> apex_device_declaration apex_info_lines . (rule 54)
		4572	apex_info_lines -> apex_info_lines . apex_info_line (rule 58)
		4573
		4574	GND shift, and go to state 281
		4575	GND_RES_IO shift, and go to state 282
		4576	GND_RES_IN shift, and go to state 283
		4577	VCC shift, and go to state 284
		4578	TXT_STRING shift, and go to state 285
		4579
		4580	$default reduce using rule 54 (apex_chip_body)
		4581
		4582	apex_info_line go to state 361
		4583
		4584
		4585
		4586	state 287
		4587
		4588	apex_info_lines -> apex_info_line . (rule 59)
		4589
		4590	$default reduce using rule 59 (apex_info_lines)
		4591
		4592
		4593
		4594	state 288
		4595
		4596	alias_to_another_template -> ALIAS astring . end_item (rule 379)
		4597
		4598	';' shift, and go to state 240
		4599
		4600	end_item go to state 362
		4601
		4602
		4603
		4604	state 289
		4605
		4606	pin_declarations -> pin_declarations . pin_declaration (rule 42)
		4607	template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations . pin_equivalences END end_item (rule 371)
		4608
		4609	EQUIVALENT shift, and go to state 349
		4610	GND shift, and go to state 131
		4611	VCC shift, and go to state 132
		4612	QUOTED_STRING shift, and go to state 54
		4613	TXT_STRING shift, and go to state 55
		4614	NUM_STRING shift, and go to state 56
		4615
		4616	$default reduce using rule 37 (pin_equivalences)
		4617
		4618	astring go to state 133
		4619	pin_equivalences go to state 363
		4620	pin_declaration go to state 351
		4621	name_part go to state 278
		4622	pin_equivalence go to state 352
		4623	netname go to state 279
		4624
		4625
		4626
		4627	state 290
		4628
		4629	template_info_lines -> template_info_lines template_info_line . (rule 374)
		4630
		4631	$default reduce using rule 374 (template_info_lines)
		4632
		4633
		4634
		4635	state 291
		4636
		4637	colon_expr -> expr ':' . expr (rule 123)
		4638
		4639	TRUE shift, and go to state 27
		4640	FALSE shift, and go to state 28
		4641	TXT_STRING shift, and go to state 31
		4642	NUM_STRING shift, and go to state 32
		4643	'~' shift, and go to state 33
		4644	'(' shift, and go to state 34
		4645	'-' shift, and go to state 35
		4646
		4647	primary_expr go to state 41
		4648	mult_expr go to state 42
		4649	add_expr go to state 43
		4650	shift_expr go to state 44
		4651	relational_expr go to state 45
		4652	equality_expr go to state 46
		4653	and_expr go to state 47
		4654	exor_expr go to state 48
		4655	or_expr go to state 49
		4656	logand_expr go to state 50
		4657	logor_expr go to state 51
		4658	cond_expr go to state 52
		4659	expr go to state 364
		4660
		4661
		4662
		4663	state 292
		4664
		4665	components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines END end_item . (rule 300)
		4666
		4667	$default reduce using rule 300 (components_decl)
		4668
		4669
		4670
		4671	state 293
		4672
		4673	chip_name -> astring . (rule 306)
		4674
		4675	$default reduce using rule 306 (chip_name)
		4676
		4677
		4678
		4679	state 294
		4680
		4681	comp_defn_line -> chip_ident ':' chip_name . chip_type chip_value end_item (rule 304)
		4682
		4683	QUOTED_STRING shift, and go to state 54
		4684	TXT_STRING shift, and go to state 55
		4685	NUM_STRING shift, and go to state 56
		4686
		4687	astring go to state 365
		4688	chip_type go to state 366
		4689
		4690
		4691
		4692	state 295
		4693
		4694	conn_decl -> CONN conn_ident . conn_name last_route_status end_item nodelist END_CONN @17 end_item (rule 352)
		4695
		4696	QUOTED_STRING shift, and go to state 54
		4697	TXT_STRING shift, and go to state 55
		4698	NUM_STRING shift, and go to state 56
		4699
		4700	astring go to state 367
		4701	conn_name go to state 368
		4702
		4703
		4704
		4705	state 296
		4706
		4707	conn_ident -> netname . (rule 353)
		4708
		4709	$default reduce using rule 353 (conn_ident)
		4710
		4711
		4712
		4713	state 297
		4714
		4715	nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block END . end_item (rule 338)
		4716
		4717	';' shift, and go to state 240
		4718
		4719	end_item go to state 369
		4720
		4721
		4722
		4723	state 298
		4724
		4725	connection_block -> connection_block connection_block_item . (rule 339)
		4726
		4727	$default reduce using rule 339 (connection_block)
		4728
		4729
		4730
		4731	state 299
		4732
		4733	conn_decls -> conn_decls conn_decl . (rule 349)
		4734
		4735	$default reduce using rule 349 (conn_decls)
		4736
		4737
		4738
		4739	state 300
		4740
		4741	join_decl -> CONN astring astring . @15 end_item (rule 315)
		4742
		4743	$default reduce using rule 314 (@15)
		4744
		4745	@15 go to state 370
		4746
		4747
		4748
		4749	state 301
		4750
		4751	vhdl_concurrent_assignment -> astring SIG_ASSIGN . astring end_item (rule 210)
		4752
		4753	QUOTED_STRING shift, and go to state 54
		4754	TXT_STRING shift, and go to state 55
		4755	NUM_STRING shift, and go to state 56
		4756
		4757	astring go to state 371
		4758
		4759
		4760
		4761	state 302
		4762
		4763	joined_decl -> JOINED_NETS BEGIN_TOK join_decls END end_item . (rule 309)
		4764
		4765	$default reduce using rule 309 (joined_decl)
		4766
		4767
		4768
		4769	state 303
		4770
		4771	join_decl -> alias_part root_net '=' . '(' joined_nets ')' end_item (rule 313)
		4772
		4773	'(' shift, and go to state 372
		4774
		4775
		4776
		4777	state 304
		4778
		4779	rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls END end_item . (rule 327)
		4780
		4781	$default reduce using rule 327 (rename_pins_block)
		4782
		4783
		4784
		4785	state 305
		4786
		4787	rename_pin_decl -> rename_new_name '=' '(' . rename_pin_items ')' end_item (rule 330)
		4788
		4789	QUOTED_STRING shift, and go to state 54
		4790	TXT_STRING shift, and go to state 55
		4791	NUM_STRING shift, and go to state 56
		4792
		4793	QUOTED_STRING [reduce using rule 336 (rename_pin_item)]
		4794	TXT_STRING [reduce using rule 336 (rename_pin_item)]
		4795	NUM_STRING [reduce using rule 336 (rename_pin_item)]
		4796	$default reduce using rule 336 (rename_pin_item)
		4797
		4798	astring go to state 373
		4799	rename_pin_items go to state 374
		4800	rename_pin_item go to state 375
		4801
		4802
		4803
		4804	state 306
		4805
		4806	rename_new_name -> netname '(' bus_range . ')' (rule 332)
		4807
		4808	')' shift, and go to state 376
		4809
		4810
		4811
		4812	state 307
		4813
		4814	ahdl_port_list -> ahdl_port_list end_item ahdl_port_item . (rule 388)
		4815
		4816	$default reduce using rule 388 (ahdl_port_list)
		4817
		4818
		4819
		4820	state 308
		4821
		4822	pin_dir -> PINDIR . (rule 50)
		4823
		4824	$default reduce using rule 50 (pin_dir)
		4825
		4826
		4827
		4828	state 309
		4829
		4830	ahdl_port_item -> ahdl_name_list ':' pin_dir . (rule 391)
		4831
		4832	$default reduce using rule 391 (ahdl_port_item)
		4833
		4834
		4835
		4836	state 310
		4837
		4838	ahdl_name_list -> ahdl_name_list ',' ahdl_name_part . (rule 392)
		4839
		4840	$default reduce using rule 392 (ahdl_name_list)
		4841
		4842
		4843
		4844	state 311
		4845
		4846	verilog_port -> hdl_name_part . (rule 237)
		4847
		4848	$default reduce using rule 237 (verilog_port)
		4849
		4850
		4851
		4852	state 312
		4853
		4854	verilog_port_list -> '(' verilog_ports . ')' ';' @7 verilog_pindir_block (rule 232)
		4855	verilog_ports -> verilog_ports . ',' verilog_port (rule 234)
		4856
		4857	')' shift, and go to state 377
		4858	',' shift, and go to state 378
		4859
		4860
		4861
		4862	state 313
		4863
		4864	verilog_ports -> verilog_port . (rule 235)
		4865
		4866	$default reduce using rule 235 (verilog_ports)
		4867
		4868
		4869
		4870	state 314
		4871
		4872	hdl_name_part -> netname . (rule 157)
		4873
		4874	$default reduce using rule 157 (hdl_name_part)
		4875
		4876
		4877
		4878	state 315
		4879
		4880	verilog_pindir_decl -> pin_dir . @8 verilog_bus_expr hdl_signal_names ';' (rule 246)
		4881
		4882	$default reduce using rule 245 (@8)
		4883
		4884	@8 go to state 379
		4885
		4886
		4887
		4888	state 316
		4889
		4890	verilog_module_header -> MODULE hdl_compname_decl verilog_port_list verilog_pindir_block . (rule 228)
		4891	verilog_pindir_block -> verilog_pindir_block . verilog_pindir_decl (rule 242)
		4892
		4893	PINDIR shift, and go to state 308
		4894
		4895	$default reduce using rule 228 (verilog_module_header)
		4896
		4897	pin_dir go to state 315
		4898	verilog_pindir_decl go to state 380
		4899
		4900
		4901
		4902	state 317
		4903
		4904	verilog_pindir_block -> verilog_pindir_decl . (rule 243)
		4905
		4906	$default reduce using rule 243 (verilog_pindir_block)
		4907
		4908
		4909
		4910	state 318
		4911
		4912	verilog_module_instance -> astring astring . '(' verilog_port_map_list ')' ';' (rule 257)
		4913
		4914	'(' shift, and go to state 381
		4915
		4916
		4917
		4918	state 319
		4919
		4920	verilog_module_instances -> verilog_module_instances verilog_module_instance . (rule 254)
		4921
		4922	$default reduce using rule 254 (verilog_module_instances)
		4923
		4924
		4925
		4926	state 320
		4927
		4928	verilog_bus_expr -> '[' expr . ']' (rule 238)
		4929	verilog_bus_expr -> '[' expr . ':' expr ']' (rule 239)
		4930
		4931	':' shift, and go to state 382
		4932	']' shift, and go to state 383
		4933
		4934
		4935
		4936	state 321
		4937
		4938	hdl_signal_name -> astring . (rule 185)
		4939
		4940	$default reduce using rule 185 (hdl_signal_name)
		4941
		4942
		4943
		4944	state 322
		4945
		4946	hdl_signal_names -> hdl_signal_names . ',' hdl_signal_name (rule 183)
		4947	verilog_wires_decl -> verilog_wire_start verilog_bus_expr hdl_signal_names . verilog_wire_end (rule 250)
		4948
		4949	';' shift, and go to state 384
		4950	',' shift, and go to state 385
		4951
		4952	verilog_wire_end go to state 386
		4953
		4954
		4955
		4956	state 323
		4957
		4958	hdl_signal_names -> hdl_signal_name . (rule 184)
		4959
		4960	$default reduce using rule 184 (hdl_signal_names)
		4961
		4962
		4963
		4964	state 324
		4965
		4966	global_generic_decl -> GENERIC @9 generic_defn_lines END end_item . (rule 265)
		4967
		4968	$default reduce using rule 265 (global_generic_decl)
		4969
		4970
		4971
		4972	state 325
		4973
		4974	generic_defn_lines -> generic_defn_lines end_item generic_defn_text . (rule 268)
		4975
		4976	$default reduce using rule 268 (generic_defn_lines)
		4977
		4978
		4979
		4980	state 326
		4981
		4982	generic_defn_text -> generic_const_opt generic_defn_name_list ':' . generic_pindir_opt generic_defn_type (rule 275)
		4983
		4984	PINDIR shift, and go to state 387
		4985
		4986	$default reduce using rule 274 (generic_pindir_opt)
		4987
		4988	generic_pindir_opt go to state 388
		4989
		4990
		4991
		4992	state 327
		4993
		4994	generic_defn_name_list -> generic_defn_name_list ',' . generic_defn_name (rule 276)
		4995
		4996	QUOTED_STRING shift, and go to state 54
		4997	TXT_STRING shift, and go to state 55
		4998	NUM_STRING shift, and go to state 56
		4999
		5000	astring go to state 259
		5001	generic_defn_name go to state 389
		5002
		5003
		5004
		5005	state 328
		5006
		5007	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 . vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
		5008
		5009	GENERIC shift, and go to state 390
		5010
		5011	$default reduce using rule 145 (vhdl_generic_decl_opt)
		5012
		5013	vhdl_generic_decl_opt go to state 391
		5014	vhdl_generic_decl go to state 392
		5015
		5016
		5017
		5018	state 329
		5019
		5020	vhdl_architecture -> ARCHITECTURE astring OF astring . IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
		5021
		5022	IS shift, and go to state 393
		5023
		5024
		5025
		5026	state 330
		5027
		5028	vhdl_library_list -> vhdl_library_name ',' vhdl_library_list . (rule 212)
		5029
		5030	$default reduce using rule 212 (vhdl_library_list)
		5031
		5032
		5033
		5034	state 331
		5035
		5036	vhdl_lib_member_select -> ALL . (rule 220)
		5037
		5038	$default reduce using rule 220 (vhdl_lib_member_select)
		5039
		5040
		5041
		5042	state 332
		5043
		5044	vhdl_lib_member -> astring '.' astring . '.' vhdl_lib_member_select (rule 218)
		5045	vhdl_lib_member_select -> astring . (rule 221)
		5046
		5047	'.' shift, and go to state 394
		5048
		5049	$default reduce using rule 221 (vhdl_lib_member_select)
		5050
		5051
		5052
		5053	state 333
		5054
		5055	vhdl_lib_member -> astring '.' vhdl_lib_member_select . (rule 219)
		5056
		5057	$default reduce using rule 219 (vhdl_lib_member)
		5058
		5059
		5060
		5061	state 334
		5062
		5063	vhdl_lib_members -> vhdl_lib_member ',' vhdl_lib_members . (rule 216)
		5064
		5065	$default reduce using rule 216 (vhdl_lib_members)
		5066
		5067
		5068
		5069	state 335
		5070
		5071	vhdl_signal_decl -> SIGNAL . @5 hdl_signal_names ':' vhdl_type end_item (rule 182)
		5072
		5073	$default reduce using rule 181 (@5)
		5074
		5075	@5 go to state 395
		5076
		5077
		5078
		5079	state 336
		5080
		5081	vhdl_constant_decl -> CONSTANT . @4 generic_defn_text end_item (rule 180)
		5082
		5083	$default reduce using rule 179 (@4)
		5084
		5085	@4 go to state 396
		5086
		5087
		5088
		5089	state 337
		5090
		5091	vhdl_component_decl -> COMPONENT . hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item (rule 177)
		5092
		5093	TXT_STRING shift, and go to state 146
		5094
		5095	hdl_compname_decl go to state 397
		5096
		5097
		5098
		5099	state 338
		5100
		5101	vhdl_configuration_decl -> FOR . vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
		5102
		5103	ALL shift, and go to state 331
		5104	QUOTED_STRING shift, and go to state 54
		5105	TXT_STRING shift, and go to state 55
		5106	NUM_STRING shift, and go to state 56
		5107
		5108	astring go to state 398
		5109	vhdl_lib_member_select go to state 399
		5110
		5111
		5112
		5113	state 339
		5114
		5115	vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations . END astring end_item (rule 168)
		5116	vhdl_package_declarations -> vhdl_package_declarations . vhdl_package_decl_item (rule 170)
		5117
		5118	END shift, and go to state 400
		5119	SIGNAL shift, and go to state 335
		5120	CONSTANT shift, and go to state 336
		5121	COMPONENT shift, and go to state 337
		5122	FOR shift, and go to state 338
		5123
		5124	vhdl_package_decl_item go to state 401
		5125	vhdl_component_decl go to state 341
		5126	vhdl_constant_decl go to state 342
		5127	vhdl_signal_decl go to state 343
		5128	vhdl_configuration_decl go to state 344
		5129
		5130
		5131
		5132	state 340
		5133
		5134	vhdl_package_declarations -> vhdl_package_decl_item . (rule 171)
		5135
		5136	$default reduce using rule 171 (vhdl_package_declarations)
		5137
		5138
		5139
		5140	state 341
		5141
		5142	vhdl_package_decl_item -> vhdl_component_decl . (rule 173)
		5143
		5144	$default reduce using rule 173 (vhdl_package_decl_item)
		5145
		5146
		5147
		5148	state 342
		5149
		5150	vhdl_package_decl_item -> vhdl_constant_decl . (rule 174)
		5151
		5152	$default reduce using rule 174 (vhdl_package_decl_item)
		5153
		5154
		5155
		5156	state 343
		5157
		5158	vhdl_package_decl_item -> vhdl_signal_decl . (rule 175)
		5159
		5160	$default reduce using rule 175 (vhdl_package_decl_item)
		5161
		5162
		5163
		5164	state 344
		5165
		5166	vhdl_package_decl_item -> vhdl_configuration_decl . (rule 176)
		5167
		5168	$default reduce using rule 176 (vhdl_package_decl_item)
		5169
		5170
		5171
		5172	state 345
		5173
		5174	device_declaration -> DEVICE '=' astring . end_item (rule 34)
		5175
		5176	';' shift, and go to state 240
		5177
		5178	end_item go to state 402
		5179
		5180
		5181
		5182	state 346
		5183
		5184	route_flag_value -> NUM_STRING . (rule 41)
		5185
		5186	$default reduce using rule 41 (route_flag_value)
		5187
		5188
		5189
		5190	state 347
		5191
		5192	route_flags_info -> ROUTE_FLAGS '=' route_flag_value . end_item (rule 40)
		5193
		5194	';' shift, and go to state 240
		5195
		5196	end_item go to state 403
		5197
		5198
		5199
		5200	state 348
		5201
		5202	chip_generic_decl -> GENERIC @10 generic_defn_lines . END end_item (rule 267)
		5203	generic_defn_lines -> generic_defn_lines . end_item generic_defn_text (rule 268)
		5204
		5205	END shift, and go to state 404
		5206	';' shift, and go to state 240
		5207
		5208	end_item go to state 258
		5209
		5210
		5211
		5212	state 349
		5213
		5214	pin_equivalence -> EQUIVALENT . @1 '(' equivalent_pins ')' end_item (rule 127)
		5215
		5216	$default reduce using rule 126 (@1)
		5217
		5218	@1 go to state 405
		5219
		5220
		5221
		5222	state 350
		5223
		5224	flex_chip_body -> chip_info_lines pin_declarations pin_equivalences . END end_item (rule 25)
		5225
		5226	END shift, and go to state 406
		5227
		5228
		5229
		5230	state 351
		5231
		5232	pin_declarations -> pin_declarations pin_declaration . (rule 42)
		5233
		5234	$default reduce using rule 42 (pin_declarations)
		5235
		5236
		5237
		5238	state 352
		5239
		5240	pin_equivalences -> pin_equivalence . pin_equivalences (rule 35)
		5241	pin_equivalences -> pin_equivalence . (rule 36)
		5242
		5243	EQUIVALENT shift, and go to state 349
		5244
		5245	END reduce using rule 36 (pin_equivalences)
		5246	END [reduce using rule 37 (pin_equivalences)]
		5247	$default reduce using rule 36 (pin_equivalences)
		5248	pin_equivalences go to state 407
		5249	pin_equivalence go to state 352
		5250
		5251
		5252
		5253	state 353
		5254
		5255	pin_declaration -> name_part ':' . pin_rest end_item (rule 45)
		5256
		5257	LOCATION shift, and go to state 408
		5258	UNROUTED shift, and go to state 409
		5259	PINDIR shift, and go to state 308
		5260
		5261	pin_rest go to state 410
		5262	pin_dir go to state 411
		5263
		5264
		5265
		5266	state 354
		5267
		5268	apex_device_declaration -> TO AN astring . apex_speed_grade (rule 55)
		5269
		5270	'-' shift, and go to state 412
		5271
		5272	$default reduce using rule 57 (apex_speed_grade)
		5273
		5274	apex_speed_grade go to state 413
		5275
		5276
		5277
		5278	state 355
		5279
		5280	apex_info_line -> GND ':' . astring more_colons (rule 60)
		5281
		5282	QUOTED_STRING shift, and go to state 54
		5283	TXT_STRING shift, and go to state 55
		5284	NUM_STRING shift, and go to state 56
		5285
		5286	astring go to state 414
		5287
		5288
		5289
		5290	state 356
		5291
		5292	apex_info_line -> GND_RES_IO ':' . astring more_colons (rule 61)
		5293
		5294	QUOTED_STRING shift, and go to state 54
		5295	TXT_STRING shift, and go to state 55
		5296	NUM_STRING shift, and go to state 56
		5297
		5298	astring go to state 415
		5299
		5300
		5301
		5302	state 357
		5303
		5304	apex_info_line -> GND_RES_IN ':' . astring more_colons (rule 62)
		5305
		5306	QUOTED_STRING shift, and go to state 54
		5307	TXT_STRING shift, and go to state 55
		5308	NUM_STRING shift, and go to state 56
		5309
		5310	astring go to state 416
		5311
		5312
		5313
		5314	state 358
		5315
		5316	apex_info_line -> VCC ':' . astring ':' NUM_STRING (rule 63)
		5317	apex_info_line -> VCC ':' . astring more_colons (rule 64)
		5318
		5319	QUOTED_STRING shift, and go to state 54
		5320	TXT_STRING shift, and go to state 55
		5321	NUM_STRING shift, and go to state 56
		5322
		5323	astring go to state 417
		5324
		5325
		5326
		5327	state 359
		5328
		5329	apex_info_line -> TXT_STRING ':' . astring more_colons (rule 65)
		5330	apex_info_line -> TXT_STRING ':' . astring ':' PINDIR ':' astring ':' (rule 66)
		5331
		5332	QUOTED_STRING shift, and go to state 54
		5333	TXT_STRING shift, and go to state 55
		5334	NUM_STRING shift, and go to state 56
		5335
		5336	astring go to state 418
		5337
		5338
		5339
		5340	state 360
		5341
		5342	apex_info_line -> TXT_STRING '[' . expr ']' ':' astring ':' PINDIR ':' astring ':' (rule 67)
		5343
		5344	TRUE shift, and go to state 27
		5345	FALSE shift, and go to state 28
		5346	TXT_STRING shift, and go to state 31
		5347	NUM_STRING shift, and go to state 32
		5348	'~' shift, and go to state 33
		5349	'(' shift, and go to state 34
		5350	'-' shift, and go to state 35
		5351
		5352	primary_expr go to state 41
		5353	mult_expr go to state 42
		5354	add_expr go to state 43
		5355	shift_expr go to state 44
		5356	relational_expr go to state 45
		5357	equality_expr go to state 46
		5358	and_expr go to state 47
		5359	exor_expr go to state 48
		5360	or_expr go to state 49
		5361	logand_expr go to state 50
		5362	logor_expr go to state 51
		5363	cond_expr go to state 52
		5364	expr go to state 419
		5365
		5366
		5367
		5368	state 361
		5369
		5370	apex_info_lines -> apex_info_lines apex_info_line . (rule 58)
		5371
		5372	$default reduce using rule 58 (apex_info_lines)
		5373
		5374
		5375
		5376	state 362
		5377
		5378	alias_to_another_template -> ALIAS astring end_item . (rule 379)
		5379
		5380	$default reduce using rule 379 (alias_to_another_template)
		5381
		5382
		5383
		5384	state 363
		5385
		5386	template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences . END end_item (rule 371)
		5387
		5388	END shift, and go to state 420
		5389
		5390
		5391
		5392	state 364
		5393
		5394	colon_expr -> expr ':' expr . (rule 123)
		5395
		5396	$default reduce using rule 123 (colon_expr)
		5397
		5398
		5399
		5400	state 365
		5401
		5402	chip_type -> astring . (rule 307)
		5403
		5404	$default reduce using rule 307 (chip_type)
		5405
		5406
		5407
		5408	state 366
		5409
		5410	comp_defn_line -> chip_ident ':' chip_name chip_type . chip_value end_item (rule 304)
		5411
		5412	QUOTED_STRING shift, and go to state 54
		5413	TXT_STRING shift, and go to state 55
		5414	NUM_STRING shift, and go to state 56
		5415
		5416	astring go to state 421
		5417	chip_value go to state 422
		5418
		5419
		5420
		5421	state 367
		5422
		5423	conn_name -> astring . (rule 354)
		5424
		5425	$default reduce using rule 354 (conn_name)
		5426
		5427
		5428
		5429	state 368
		5430
		5431	conn_decl -> CONN conn_ident conn_name . last_route_status end_item nodelist END_CONN @17 end_item (rule 352)
		5432
		5433	QUOTED_STRING shift, and go to state 54
		5434	TXT_STRING shift, and go to state 55
		5435	NUM_STRING shift, and go to state 56
		5436
		5437	astring go to state 423
		5438	last_route_status go to state 424
		5439
		5440
		5441
		5442	state 369
		5443
		5444	nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block END end_item . (rule 338)
		5445
		5446	$default reduce using rule 338 (nets_decl)
		5447
		5448
		5449
		5450	state 370
		5451
		5452	join_decl -> CONN astring astring @15 . end_item (rule 315)
		5453
		5454	';' shift, and go to state 240
		5455
		5456	end_item go to state 425
		5457
		5458
		5459
		5460	state 371
		5461
		5462	vhdl_concurrent_assignment -> astring SIG_ASSIGN astring . end_item (rule 210)
		5463
		5464	';' shift, and go to state 240
		5465
		5466	end_item go to state 426
		5467
		5468
		5469
		5470	state 372
		5471
		5472	join_decl -> alias_part root_net '=' '(' . joined_nets ')' end_item (rule 313)
		5473
		5474	GND shift, and go to state 131
		5475	VCC shift, and go to state 132
		5476	QUOTED_STRING shift, and go to state 54
		5477	TXT_STRING shift, and go to state 55
		5478	NUM_STRING shift, and go to state 56
		5479
		5480	astring go to state 133
		5481	joined_nets go to state 427
		5482	joined_net go to state 428
		5483	single_net go to state 429
		5484	jumper_node go to state 430
		5485	netname go to state 431
		5486
		5487
		5488
		5489	state 373
		5490
		5491	rename_pin_item -> astring . '.' astring end_item (rule 335)
		5492
		5493	'.' shift, and go to state 432
		5494
		5495
		5496
		5497	state 374
		5498
		5499	rename_pin_decl -> rename_new_name '=' '(' rename_pin_items . ')' end_item (rule 330)
		5500	rename_pin_items -> rename_pin_items . rename_pin_item (rule 333)
		5501
		5502	QUOTED_STRING shift, and go to state 54
		5503	TXT_STRING shift, and go to state 55
		5504	NUM_STRING shift, and go to state 56
		5505	')' shift, and go to state 433
		5506
		5507	QUOTED_STRING [reduce using rule 336 (rename_pin_item)]
		5508	TXT_STRING [reduce using rule 336 (rename_pin_item)]
		5509	NUM_STRING [reduce using rule 336 (rename_pin_item)]
		5510	')' [reduce using rule 336 (rename_pin_item)]
		5511	$default reduce using rule 336 (rename_pin_item)
		5512
		5513	astring go to state 373
		5514	rename_pin_item go to state 434
		5515
		5516
		5517
		5518	state 375
		5519
		5520	rename_pin_items -> rename_pin_item . (rule 334)
		5521
		5522	$default reduce using rule 334 (rename_pin_items)
		5523
		5524
		5525
		5526	state 376
		5527
		5528	rename_new_name -> netname '(' bus_range ')' . (rule 332)
		5529
		5530	$default reduce using rule 332 (rename_new_name)
		5531
		5532
		5533
		5534	state 377
		5535
		5536	verilog_port_list -> '(' verilog_ports ')' . ';' @7 verilog_pindir_block (rule 232)
		5537
		5538	';' shift, and go to state 435
		5539
		5540
		5541
		5542	state 378
		5543
		5544	verilog_ports -> verilog_ports ',' . verilog_port (rule 234)
		5545
		5546	GND shift, and go to state 131
		5547	VCC shift, and go to state 132
		5548	QUOTED_STRING shift, and go to state 54
		5549	TXT_STRING shift, and go to state 55
		5550	NUM_STRING shift, and go to state 56
		5551
		5552	astring go to state 133
		5553	hdl_name_part go to state 311
		5554	verilog_port go to state 436
		5555	netname go to state 314
		5556
		5557
		5558
		5559	state 379
		5560
		5561	verilog_pindir_decl -> pin_dir @8 . verilog_bus_expr hdl_signal_names ';' (rule 246)
		5562
		5563	'[' shift, and go to state 255
		5564
		5565	$default reduce using rule 240 (verilog_bus_expr)
		5566
		5567	verilog_bus_expr go to state 437
		5568
		5569
		5570
		5571	state 380
		5572
		5573	verilog_pindir_block -> verilog_pindir_block verilog_pindir_decl . (rule 242)
		5574
		5575	$default reduce using rule 242 (verilog_pindir_block)
		5576
		5577
		5578
		5579	state 381
		5580
		5581	verilog_module_instance -> astring astring '(' . verilog_port_map_list ')' ';' (rule 257)
		5582
		5583	'.' shift, and go to state 438
		5584
		5585	$default reduce using rule 259 (verilog_port_map_list)
		5586
		5587	verilog_port_map_list go to state 439
		5588	verilog_port_maps go to state 440
		5589	verilog_port_map go to state 441
		5590
		5591
		5592
		5593	state 382
		5594
		5595	verilog_bus_expr -> '[' expr ':' . expr ']' (rule 239)
		5596
		5597	TRUE shift, and go to state 27
		5598	FALSE shift, and go to state 28
		5599	TXT_STRING shift, and go to state 31
		5600	NUM_STRING shift, and go to state 32
		5601	'~' shift, and go to state 33
		5602	'(' shift, and go to state 34
		5603	'-' shift, and go to state 35
		5604
		5605	primary_expr go to state 41
		5606	mult_expr go to state 42
		5607	add_expr go to state 43
		5608	shift_expr go to state 44
		5609	relational_expr go to state 45
		5610	equality_expr go to state 46
		5611	and_expr go to state 47
		5612	exor_expr go to state 48
		5613	or_expr go to state 49
		5614	logand_expr go to state 50
		5615	logor_expr go to state 51
		5616	cond_expr go to state 52
		5617	expr go to state 442
		5618
		5619
		5620
		5621	state 383
		5622
		5623	verilog_bus_expr -> '[' expr ']' . (rule 238)
		5624
		5625	$default reduce using rule 238 (verilog_bus_expr)
		5626
		5627
		5628
		5629	state 384
		5630
		5631	verilog_wire_end -> ';' . (rule 252)
		5632
		5633	$default reduce using rule 252 (verilog_wire_end)
		5634
		5635
		5636
		5637	state 385
		5638
		5639	hdl_signal_names -> hdl_signal_names ',' . hdl_signal_name (rule 183)
		5640
		5641	QUOTED_STRING shift, and go to state 54
		5642	TXT_STRING shift, and go to state 55
		5643	NUM_STRING shift, and go to state 56
		5644
		5645	astring go to state 321
		5646	hdl_signal_name go to state 443
		5647
		5648
		5649
		5650	state 386
		5651
		5652	verilog_wires_decl -> verilog_wire_start verilog_bus_expr hdl_signal_names verilog_wire_end . (rule 250)
		5653
		5654	$default reduce using rule 250 (verilog_wires_decl)
		5655
		5656
		5657
		5658	state 387
		5659
		5660	generic_pindir_opt -> PINDIR . (rule 273)
		5661
		5662	$default reduce using rule 273 (generic_pindir_opt)
		5663
		5664
		5665
		5666	state 388
		5667
		5668	generic_defn_text -> generic_const_opt generic_defn_name_list ':' generic_pindir_opt . generic_defn_type (rule 275)
		5669
		5670	DECLARATION shift, and go to state 444
		5671	INSTANCE shift, and go to state 445
		5672	BOOLEAN shift, and go to state 446
		5673	INTEGER shift, and go to state 447
		5674	ATTRIBUTE shift, and go to state 448
		5675	ENV_STRING shift, and go to state 449
		5676	STRING shift, and go to state 450
		5677
		5678	generic_defn_type go to state 451
		5679
		5680
		5681
		5682	state 389
		5683
		5684	generic_defn_name_list -> generic_defn_name_list ',' generic_defn_name . (rule 276)
		5685
		5686	$default reduce using rule 276 (generic_defn_name_list)
		5687
		5688
		5689
		5690	state 390
		5691
		5692	vhdl_generic_decl -> GENERIC . '(' @3 generic_defn_lines ')' end_item (rule 147)
		5693
		5694	'(' shift, and go to state 452
		5695
		5696
		5697
		5698	state 391
		5699
		5700	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt . vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
		5701
		5702	PORT shift, and go to state 453
		5703
		5704	$default reduce using rule 149 (vhdl_port_decl_opt)
		5705
		5706	vhdl_port_decl_opt go to state 454
		5707	vhdl_port_decl go to state 455
		5708
		5709
		5710
		5711	state 392
		5712
		5713	vhdl_generic_decl_opt -> vhdl_generic_decl . (rule 144)
		5714
		5715	$default reduce using rule 144 (vhdl_generic_decl_opt)
		5716
		5717
		5718
		5719	state 393
		5720
		5721	vhdl_architecture -> ARCHITECTURE astring OF astring IS . vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
		5722
		5723	SIGNAL shift, and go to state 335
		5724	CONSTANT shift, and go to state 336
		5725	COMPONENT shift, and go to state 337
		5726	FOR shift, and go to state 338
		5727
		5728	SIGNAL [reduce using rule 163 (vhdl_architecture_declarations)]
		5729	CONSTANT [reduce using rule 163 (vhdl_architecture_declarations)]
		5730	COMPONENT [reduce using rule 163 (vhdl_architecture_declarations)]
		5731	FOR [reduce using rule 163 (vhdl_architecture_declarations)]
		5732	$default reduce using rule 163 (vhdl_architecture_declarations)
		5733
		5734	vhdl_architecture_declarations go to state 456
		5735	vhdl_architecture_decl go to state 457
		5736	vhdl_component_decl go to state 458
		5737	vhdl_constant_decl go to state 459
		5738	vhdl_signal_decl go to state 460
		5739	vhdl_configuration_decl go to state 461
		5740
		5741
		5742
		5743	state 394
		5744
		5745	vhdl_lib_member -> astring '.' astring '.' . vhdl_lib_member_select (rule 218)
		5746
		5747	ALL shift, and go to state 331
		5748	QUOTED_STRING shift, and go to state 54
		5749	TXT_STRING shift, and go to state 55
		5750	NUM_STRING shift, and go to state 56
		5751
		5752	astring go to state 398
		5753	vhdl_lib_member_select go to state 462
		5754
		5755
		5756
		5757	state 395
		5758
		5759	vhdl_signal_decl -> SIGNAL @5 . hdl_signal_names ':' vhdl_type end_item (rule 182)
		5760
		5761	QUOTED_STRING shift, and go to state 54
		5762	TXT_STRING shift, and go to state 55
		5763	NUM_STRING shift, and go to state 56
		5764
		5765	astring go to state 321
		5766	hdl_signal_names go to state 463
		5767	hdl_signal_name go to state 323
		5768
		5769
		5770
		5771	state 396
		5772
		5773	vhdl_constant_decl -> CONSTANT @4 . generic_defn_text end_item (rule 180)
		5774
		5775	CONSTANT shift, and go to state 156
		5776
		5777	$default reduce using rule 272 (generic_const_opt)
		5778
		5779	generic_const_opt go to state 158
		5780	generic_defn_text go to state 464
		5781
		5782
		5783
		5784	state 397
		5785
		5786	vhdl_component_decl -> COMPONENT hdl_compname_decl . vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item (rule 177)
		5787
		5788	GENERIC shift, and go to state 390
		5789
		5790	$default reduce using rule 145 (vhdl_generic_decl_opt)
		5791
		5792	vhdl_generic_decl_opt go to state 465
		5793	vhdl_generic_decl go to state 392
		5794
		5795
		5796
		5797	state 398
		5798
		5799	vhdl_lib_member_select -> astring . (rule 221)
		5800
		5801	$default reduce using rule 221 (vhdl_lib_member_select)
		5802
		5803
		5804
		5805	state 399
		5806
		5807	vhdl_configuration_decl -> FOR vhdl_lib_member_select . ':' astring USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
		5808
		5809	':' shift, and go to state 466
		5810
		5811
		5812
		5813	state 400
		5814
		5815	vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END . astring end_item (rule 168)
		5816
		5817	QUOTED_STRING shift, and go to state 54
		5818	TXT_STRING shift, and go to state 55
		5819	NUM_STRING shift, and go to state 56
		5820
		5821	astring go to state 467
		5822
		5823
		5824
		5825	state 401
		5826
		5827	vhdl_package_declarations -> vhdl_package_declarations vhdl_package_decl_item . (rule 170)
		5828
		5829	$default reduce using rule 170 (vhdl_package_declarations)
		5830
		5831
		5832
		5833	state 402
		5834
		5835	device_declaration -> DEVICE '=' astring end_item . (rule 34)
		5836
		5837	$default reduce using rule 34 (device_declaration)
		5838
		5839
		5840
		5841	state 403
		5842
		5843	route_flags_info -> ROUTE_FLAGS '=' route_flag_value end_item . (rule 40)
		5844
		5845	$default reduce using rule 40 (route_flags_info)
		5846
		5847
		5848
		5849	state 404
		5850
		5851	chip_generic_decl -> GENERIC @10 generic_defn_lines END . end_item (rule 267)
		5852
		5853	';' shift, and go to state 240
		5854
		5855	end_item go to state 468
		5856
		5857
		5858
		5859	state 405
		5860
		5861	pin_equivalence -> EQUIVALENT @1 . '(' equivalent_pins ')' end_item (rule 127)
		5862
		5863	'(' shift, and go to state 469
		5864
		5865
		5866
		5867	state 406
		5868
		5869	flex_chip_body -> chip_info_lines pin_declarations pin_equivalences END . end_item (rule 25)
		5870
		5871	';' shift, and go to state 240
		5872
		5873	end_item go to state 470
		5874
		5875
		5876
		5877	state 407
		5878
		5879	pin_equivalences -> pin_equivalence pin_equivalences . (rule 35)
		5880
		5881	$default reduce using rule 35 (pin_equivalences)
		5882
		5883
		5884
		5885	state 408
		5886
		5887	pin_rest -> LOCATION . '=' astring (rule 49)
		5888
		5889	'=' shift, and go to state 471
		5890
		5891
		5892
		5893	state 409
		5894
		5895	pin_rest -> UNROUTED . (rule 48)
		5896
		5897	$default reduce using rule 48 (pin_rest)
		5898
		5899
		5900
		5901	state 410
		5902
		5903	pin_declaration -> name_part ':' pin_rest . end_item (rule 45)
		5904
		5905	';' shift, and go to state 240
		5906
		5907	end_item go to state 472
		5908
		5909
		5910
		5911	state 411
		5912
		5913	pin_rest -> pin_dir . pin_group '=' pin_ident vhdl_type_opt (rule 47)
		5914
		5915	'(' shift, and go to state 473
		5916
		5917	$default reduce using rule 52 (pin_group)
		5918
		5919	pin_group go to state 474
		5920
		5921
		5922
		5923	state 412
		5924
		5925	apex_speed_grade -> '-' . NUM_STRING (rule 56)
		5926
		5927	NUM_STRING shift, and go to state 475
		5928
		5929
		5930
		5931	state 413
		5932
		5933	apex_device_declaration -> TO AN astring apex_speed_grade . (rule 55)
		5934
		5935	$default reduce using rule 55 (apex_device_declaration)
		5936
		5937
		5938
		5939	state 414
		5940
		5941	apex_info_line -> GND ':' astring . more_colons (rule 60)
		5942
		5943	':' shift, and go to state 476
		5944
		5945	more_colons go to state 477
		5946
		5947
		5948
		5949	state 415
		5950
		5951	apex_info_line -> GND_RES_IO ':' astring . more_colons (rule 61)
		5952
		5953	':' shift, and go to state 476
		5954
		5955	more_colons go to state 478
		5956
		5957
		5958
		5959	state 416
		5960
		5961	apex_info_line -> GND_RES_IN ':' astring . more_colons (rule 62)
		5962
		5963	':' shift, and go to state 476
		5964
		5965	more_colons go to state 479
		5966
		5967
		5968
		5969	state 417
		5970
		5971	apex_info_line -> VCC ':' astring . ':' NUM_STRING (rule 63)
		5972	apex_info_line -> VCC ':' astring . more_colons (rule 64)
		5973
		5974	':' shift, and go to state 480
		5975
		5976	more_colons go to state 481
		5977
		5978
		5979
		5980	state 418
		5981
		5982	apex_info_line -> TXT_STRING ':' astring . more_colons (rule 65)
		5983	apex_info_line -> TXT_STRING ':' astring . ':' PINDIR ':' astring ':' (rule 66)
		5984
		5985	':' shift, and go to state 482
		5986
		5987	more_colons go to state 483
		5988
		5989
		5990
		5991	state 419
		5992
		5993	apex_info_line -> TXT_STRING '[' expr . ']' ':' astring ':' PINDIR ':' astring ':' (rule 67)
		5994
		5995	']' shift, and go to state 484
		5996
		5997
		5998
		5999	state 420
		6000
		6001	template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences END . end_item (rule 371)
		6002
		6003	';' shift, and go to state 240
		6004
		6005	end_item go to state 485
		6006
		6007
		6008
		6009	state 421
		6010
		6011	chip_value -> astring . (rule 308)
		6012
		6013	$default reduce using rule 308 (chip_value)
		6014
		6015
		6016
		6017	state 422
		6018
		6019	comp_defn_line -> chip_ident ':' chip_name chip_type chip_value . end_item (rule 304)
		6020
		6021	';' shift, and go to state 240
		6022
		6023	end_item go to state 486
		6024
		6025
		6026
		6027	state 423
		6028
		6029	last_route_status -> astring . (rule 355)
		6030
		6031	$default reduce using rule 355 (last_route_status)
		6032
		6033
		6034
		6035	state 424
		6036
		6037	conn_decl -> CONN conn_ident conn_name last_route_status . end_item nodelist END_CONN @17 end_item (rule 352)
		6038
		6039	';' shift, and go to state 240
		6040
		6041	end_item go to state 487
		6042
		6043
		6044
		6045	state 425
		6046
		6047	join_decl -> CONN astring astring @15 end_item . (rule 315)
		6048
		6049	$default reduce using rule 315 (join_decl)
		6050
		6051
		6052
		6053	state 426
		6054
		6055	vhdl_concurrent_assignment -> astring SIG_ASSIGN astring end_item . (rule 210)
		6056
		6057	$default reduce using rule 210 (vhdl_concurrent_assignment)
		6058
		6059
		6060
		6061	state 427
		6062
		6063	join_decl -> alias_part root_net '=' '(' joined_nets . ')' end_item (rule 313)
		6064	joined_nets -> joined_nets . joined_net (rule 321)
		6065
		6066	GND shift, and go to state 131
		6067	VCC shift, and go to state 132
		6068	QUOTED_STRING shift, and go to state 54
		6069	TXT_STRING shift, and go to state 55
		6070	NUM_STRING shift, and go to state 56
		6071	')' shift, and go to state 488
		6072
		6073	astring go to state 133
		6074	joined_net go to state 489
		6075	single_net go to state 429
		6076	jumper_node go to state 430
		6077	netname go to state 431
		6078
		6079
		6080
		6081	state 428
		6082
		6083	joined_nets -> joined_net . (rule 322)
		6084
		6085	$default reduce using rule 322 (joined_nets)
		6086
		6087
		6088
		6089	state 429
		6090
		6091	joined_net -> single_net . end_item (rule 323)
		6092
		6093	';' shift, and go to state 240
		6094
		6095	end_item go to state 490
		6096
		6097
		6098
		6099	state 430
		6100
		6101	joined_net -> jumper_node . end_item (rule 324)
		6102
		6103	';' shift, and go to state 240
		6104
		6105	end_item go to state 491
		6106
		6107
		6108
		6109	state 431
		6110
		6111	single_net -> netname . (rule 325)
		6112	jumper_node -> netname . '(' astring ')' (rule 326)
		6113
		6114	'(' shift, and go to state 492
		6115
		6116	$default reduce using rule 325 (single_net)
		6117
		6118
		6119
		6120	state 432
		6121
		6122	rename_pin_item -> astring '.' . astring end_item (rule 335)
		6123
		6124	QUOTED_STRING shift, and go to state 54
		6125	TXT_STRING shift, and go to state 55
		6126	NUM_STRING shift, and go to state 56
		6127
		6128	astring go to state 493
		6129
		6130
		6131
		6132	state 433
		6133
		6134	rename_pin_decl -> rename_new_name '=' '(' rename_pin_items ')' . end_item (rule 330)
		6135
		6136	';' shift, and go to state 240
		6137
		6138	end_item go to state 494
		6139
		6140
		6141
		6142	state 434
		6143
		6144	rename_pin_items -> rename_pin_items rename_pin_item . (rule 333)
		6145
		6146	$default reduce using rule 333 (rename_pin_items)
		6147
		6148
		6149
		6150	state 435
		6151
		6152	verilog_port_list -> '(' verilog_ports ')' ';' . @7 verilog_pindir_block (rule 232)
		6153
		6154	$default reduce using rule 231 (@7)
		6155
		6156	@7 go to state 495
		6157
		6158
		6159
		6160	state 436
		6161
		6162	verilog_ports -> verilog_ports ',' verilog_port . (rule 234)
		6163
		6164	$default reduce using rule 234 (verilog_ports)
		6165
		6166
		6167
		6168	state 437
		6169
		6170	verilog_pindir_decl -> pin_dir @8 verilog_bus_expr . hdl_signal_names ';' (rule 246)
		6171
		6172	QUOTED_STRING shift, and go to state 54
		6173	TXT_STRING shift, and go to state 55
		6174	NUM_STRING shift, and go to state 56
		6175
		6176	astring go to state 321
		6177	hdl_signal_names go to state 496
		6178	hdl_signal_name go to state 323
		6179
		6180
		6181
		6182	state 438
		6183
		6184	verilog_port_map -> '.' . astring '(' astring verilog_bus_expr ')' (rule 262)
		6185	verilog_port_map -> '.' . astring '(' ')' (rule 263)
		6186
		6187	QUOTED_STRING shift, and go to state 54
		6188	TXT_STRING shift, and go to state 55
		6189	NUM_STRING shift, and go to state 56
		6190
		6191	astring go to state 497
		6192
		6193
		6194
		6195	state 439
		6196
		6197	verilog_module_instance -> astring astring '(' verilog_port_map_list . ')' ';' (rule 257)
		6198
		6199	')' shift, and go to state 498
		6200
		6201
		6202
		6203	state 440
		6204
		6205	verilog_port_map_list -> verilog_port_maps . (rule 258)
		6206	verilog_port_maps -> verilog_port_maps . ',' verilog_port_map (rule 260)
		6207
		6208	',' shift, and go to state 499
		6209
		6210	$default reduce using rule 258 (verilog_port_map_list)
		6211
		6212
		6213
		6214	state 441
		6215
		6216	verilog_port_maps -> verilog_port_map . (rule 261)
		6217
		6218	$default reduce using rule 261 (verilog_port_maps)
		6219
		6220
		6221
		6222	state 442
		6223
		6224	verilog_bus_expr -> '[' expr ':' expr . ']' (rule 239)
		6225
		6226	']' shift, and go to state 500
		6227
		6228
		6229
		6230	state 443
		6231
		6232	hdl_signal_names -> hdl_signal_names ',' hdl_signal_name . (rule 183)
		6233
		6234	$default reduce using rule 183 (hdl_signal_names)
		6235
		6236
		6237
		6238	state 444
		6239
		6240	generic_defn_type -> DECLARATION . @11 assign_words (rule 283)
		6241
		6242	$default reduce using rule 282 (@11)
		6243
		6244	@11 go to state 501
		6245
		6246
		6247
		6248	state 445
		6249
		6250	generic_defn_type -> INSTANCE . @12 assign_words (rule 285)
		6251
		6252	$default reduce using rule 284 (@12)
		6253
		6254	@12 go to state 502
		6255
		6256
		6257
		6258	state 446
		6259
		6260	generic_defn_type -> BOOLEAN . opt_integer (rule 280)
		6261
		6262	ASSIGN shift, and go to state 503
		6263
		6264	$default reduce using rule 292 (opt_integer)
		6265
		6266	opt_integer go to state 504
		6267
		6268
		6269
		6270	state 447
		6271
		6272	generic_defn_type -> INTEGER . opt_integer (rule 279)
		6273	generic_defn_type -> INTEGER . RANGE opt_bus_range (rule 281)
		6274
		6275	ASSIGN shift, and go to state 503
		6276	RANGE shift, and go to state 505
		6277
		6278	$default reduce using rule 292 (opt_integer)
		6279
		6280	opt_integer go to state 506
		6281
		6282
		6283
		6284	state 448
		6285
		6286	generic_defn_type -> ATTRIBUTE . opt_integer (rule 290)
		6287
		6288	ASSIGN shift, and go to state 503
		6289
		6290	$default reduce using rule 292 (opt_integer)
		6291
		6292	opt_integer go to state 507
		6293
		6294
		6295
		6296	state 449
		6297
		6298	generic_defn_type -> ENV_STRING . @14 assign_words (rule 289)
		6299
		6300	$default reduce using rule 288 (@14)
		6301
		6302	@14 go to state 508
		6303
		6304
		6305
		6306	state 450
		6307
		6308	generic_defn_type -> STRING . @13 assign_words (rule 287)
		6309
		6310	$default reduce using rule 286 (@13)
		6311
		6312	@13 go to state 509
		6313
		6314
		6315
		6316	state 451
		6317
		6318	generic_defn_text -> generic_const_opt generic_defn_name_list ':' generic_pindir_opt generic_defn_type . (rule 275)
		6319
		6320	$default reduce using rule 275 (generic_defn_text)
		6321
		6322
		6323
		6324	state 452
		6325
		6326	vhdl_generic_decl -> GENERIC '(' . @3 generic_defn_lines ')' end_item (rule 147)
		6327
		6328	$default reduce using rule 146 (@3)
		6329
		6330	@3 go to state 510
		6331
		6332
		6333
		6334	state 453
		6335
		6336	vhdl_port_decl -> PORT . '(' vhdl_port_list ')' end_item (rule 150)
		6337
		6338	'(' shift, and go to state 511
		6339
		6340
		6341
		6342	state 454
		6343
		6344	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt . END TXT_STRING end_item (rule 142)
		6345
		6346	END shift, and go to state 512
		6347
		6348
		6349
		6350	state 455
		6351
		6352	vhdl_port_decl_opt -> vhdl_port_decl . (rule 148)
		6353
		6354	$default reduce using rule 148 (vhdl_port_decl_opt)
		6355
		6356
		6357
		6358	state 456
		6359
		6360	vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations . BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
		6361	vhdl_architecture_declarations -> vhdl_architecture_declarations . vhdl_architecture_decl (rule 161)
		6362
		6363	BEGIN_TOK shift, and go to state 513
		6364	SIGNAL shift, and go to state 335
		6365	CONSTANT shift, and go to state 336
		6366	COMPONENT shift, and go to state 337
		6367	FOR shift, and go to state 338
		6368
		6369	vhdl_architecture_decl go to state 514
		6370	vhdl_component_decl go to state 458
		6371	vhdl_constant_decl go to state 459
		6372	vhdl_signal_decl go to state 460
		6373	vhdl_configuration_decl go to state 461
		6374
		6375
		6376
		6377	state 457
		6378
		6379	vhdl_architecture_declarations -> vhdl_architecture_decl . (rule 162)
		6380
		6381	$default reduce using rule 162 (vhdl_architecture_declarations)
		6382
		6383
		6384
		6385	state 458
		6386
		6387	vhdl_architecture_decl -> vhdl_component_decl . (rule 164)
		6388
		6389	$default reduce using rule 164 (vhdl_architecture_decl)
		6390
		6391
		6392
		6393	state 459
		6394
		6395	vhdl_architecture_decl -> vhdl_constant_decl . (rule 165)
		6396
		6397	$default reduce using rule 165 (vhdl_architecture_decl)
		6398
		6399
		6400
		6401	state 460
		6402
		6403	vhdl_architecture_decl -> vhdl_signal_decl . (rule 166)
		6404
		6405	$default reduce using rule 166 (vhdl_architecture_decl)
		6406
		6407
		6408
		6409	state 461
		6410
		6411	vhdl_architecture_decl -> vhdl_configuration_decl . (rule 167)
		6412
		6413	$default reduce using rule 167 (vhdl_architecture_decl)
		6414
		6415
		6416
		6417	state 462
		6418
		6419	vhdl_lib_member -> astring '.' astring '.' vhdl_lib_member_select . (rule 218)
		6420
		6421	$default reduce using rule 218 (vhdl_lib_member)
		6422
		6423
		6424
		6425	state 463
		6426
		6427	vhdl_signal_decl -> SIGNAL @5 hdl_signal_names . ':' vhdl_type end_item (rule 182)
		6428	hdl_signal_names -> hdl_signal_names . ',' hdl_signal_name (rule 183)
		6429
		6430	':' shift, and go to state 515
		6431	',' shift, and go to state 385
		6432
		6433
		6434
		6435	state 464
		6436
		6437	vhdl_constant_decl -> CONSTANT @4 generic_defn_text . end_item (rule 180)
		6438
		6439	';' shift, and go to state 240
		6440
		6441	end_item go to state 516
		6442
		6443
		6444
		6445	state 465
		6446
		6447	vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt . vhdl_port_decl_opt END COMPONENT end_item (rule 177)
		6448
		6449	PORT shift, and go to state 453
		6450
		6451	$default reduce using rule 149 (vhdl_port_decl_opt)
		6452
		6453	vhdl_port_decl_opt go to state 517
		6454	vhdl_port_decl go to state 455
		6455
		6456
		6457
		6458	state 466
		6459
		6460	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' . astring USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
		6461
		6462	QUOTED_STRING shift, and go to state 54
		6463	TXT_STRING shift, and go to state 55
		6464	NUM_STRING shift, and go to state 56
		6465
		6466	astring go to state 518
		6467
		6468
		6469
		6470	state 467
		6471
		6472	vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END astring . end_item (rule 168)
		6473
		6474	';' shift, and go to state 240
		6475
		6476	end_item go to state 519
		6477
		6478
		6479
		6480	state 468
		6481
		6482	chip_generic_decl -> GENERIC @10 generic_defn_lines END end_item . (rule 267)
		6483
		6484	$default reduce using rule 267 (chip_generic_decl)
		6485
		6486
		6487
		6488	state 469
		6489
		6490	pin_equivalence -> EQUIVALENT @1 '(' . equivalent_pins ')' end_item (rule 127)
		6491
		6492	QUOTED_STRING shift, and go to state 54
		6493	TXT_STRING shift, and go to state 55
		6494	NUM_STRING shift, and go to state 56
		6495
		6496	$default reduce using rule 130 (equivalent_pins)
		6497
		6498	astring go to state 520
		6499	equivalent_pins go to state 521
		6500	equivalent_pin go to state 522
		6501
		6502
		6503
		6504	state 470
		6505
		6506	flex_chip_body -> chip_info_lines pin_declarations pin_equivalences END end_item . (rule 25)
		6507
		6508	$default reduce using rule 25 (flex_chip_body)
		6509
		6510
		6511
		6512	state 471
		6513
		6514	pin_rest -> LOCATION '=' . astring (rule 49)
		6515
		6516	QUOTED_STRING shift, and go to state 54
		6517	TXT_STRING shift, and go to state 55
		6518	NUM_STRING shift, and go to state 56
		6519
		6520	astring go to state 523
		6521
		6522
		6523
		6524	state 472
		6525
		6526	pin_declaration -> name_part ':' pin_rest end_item . (rule 45)
		6527
		6528	$default reduce using rule 45 (pin_declaration)
		6529
		6530
		6531
		6532	state 473
		6533
		6534	pin_group -> '(' . NUM_STRING ')' (rule 51)
		6535
		6536	NUM_STRING shift, and go to state 524
		6537
		6538
		6539
		6540	state 474
		6541
		6542	pin_rest -> pin_dir pin_group . '=' pin_ident vhdl_type_opt (rule 47)
		6543
		6544	'=' shift, and go to state 525
		6545
		6546
		6547
		6548	state 475
		6549
		6550	apex_speed_grade -> '-' NUM_STRING . (rule 56)
		6551
		6552	$default reduce using rule 56 (apex_speed_grade)
		6553
		6554
		6555
		6556	state 476
		6557
		6558	more_colons -> ':' . more_colons (rule 68)
		6559	more_colons -> ':' . (rule 69)
		6560
		6561	':' shift, and go to state 476
		6562
		6563	$default reduce using rule 69 (more_colons)
		6564
		6565	more_colons go to state 526
		6566
		6567
		6568
		6569	state 477
		6570
		6571	apex_info_line -> GND ':' astring more_colons . (rule 60)
		6572
		6573	$default reduce using rule 60 (apex_info_line)
		6574
		6575
		6576
		6577	state 478
		6578
		6579	apex_info_line -> GND_RES_IO ':' astring more_colons . (rule 61)
		6580
		6581	$default reduce using rule 61 (apex_info_line)
		6582
		6583
		6584
		6585	state 479
		6586
		6587	apex_info_line -> GND_RES_IN ':' astring more_colons . (rule 62)
		6588
		6589	$default reduce using rule 62 (apex_info_line)
		6590
		6591
		6592
		6593	state 480
		6594
		6595	apex_info_line -> VCC ':' astring ':' . NUM_STRING (rule 63)
		6596	more_colons -> ':' . more_colons (rule 68)
		6597	more_colons -> ':' . (rule 69)
		6598
		6599	NUM_STRING shift, and go to state 527
		6600	':' shift, and go to state 476
		6601
		6602	$default reduce using rule 69 (more_colons)
		6603
		6604	more_colons go to state 526
		6605
		6606
		6607
		6608	state 481
		6609
		6610	apex_info_line -> VCC ':' astring more_colons . (rule 64)
		6611
		6612	$default reduce using rule 64 (apex_info_line)
		6613
		6614
		6615
		6616	state 482
		6617
		6618	apex_info_line -> TXT_STRING ':' astring ':' . PINDIR ':' astring ':' (rule 66)
		6619	more_colons -> ':' . more_colons (rule 68)
		6620	more_colons -> ':' . (rule 69)
		6621
		6622	PINDIR shift, and go to state 528
		6623	':' shift, and go to state 476
		6624
		6625	$default reduce using rule 69 (more_colons)
		6626
		6627	more_colons go to state 526
		6628
		6629
		6630
		6631	state 483
		6632
		6633	apex_info_line -> TXT_STRING ':' astring more_colons . (rule 65)
		6634
		6635	$default reduce using rule 65 (apex_info_line)
		6636
		6637
		6638
		6639	state 484
		6640
		6641	apex_info_line -> TXT_STRING '[' expr ']' . ':' astring ':' PINDIR ':' astring ':' (rule 67)
		6642
		6643	':' shift, and go to state 529
		6644
		6645
		6646
		6647	state 485
		6648
		6649	template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences END end_item . (rule 371)
		6650
		6651	$default reduce using rule 371 (template_decl)
		6652
		6653
		6654
		6655	state 486
		6656
		6657	comp_defn_line -> chip_ident ':' chip_name chip_type chip_value end_item . (rule 304)
		6658
		6659	$default reduce using rule 304 (comp_defn_line)
		6660
		6661
		6662
		6663	state 487
		6664
		6665	conn_decl -> CONN conn_ident conn_name last_route_status end_item . nodelist END_CONN @17 end_item (rule 352)
		6666
		6667	QUOTED_STRING shift, and go to state 54
		6668	TXT_STRING shift, and go to state 55
		6669	NUM_STRING shift, and go to state 56
		6670
		6671	QUOTED_STRING [reduce using rule 358 (nodelist)]
		6672	TXT_STRING [reduce using rule 358 (nodelist)]
		6673	NUM_STRING [reduce using rule 358 (nodelist)]
		6674	$default reduce using rule 358 (nodelist)
		6675
		6676	astring go to state 530
		6677	nodelist go to state 531
		6678	net_node go to state 532
		6679	skt_id go to state 533
		6680
		6681
		6682
		6683	state 488
		6684
		6685	join_decl -> alias_part root_net '=' '(' joined_nets ')' . end_item (rule 313)
		6686
		6687	';' shift, and go to state 240
		6688
		6689	end_item go to state 534
		6690
		6691
		6692
		6693	state 489
		6694
		6695	joined_nets -> joined_nets joined_net . (rule 321)
		6696
		6697	$default reduce using rule 321 (joined_nets)
		6698
		6699
		6700
		6701	state 490
		6702
		6703	joined_net -> single_net end_item . (rule 323)
		6704
		6705	$default reduce using rule 323 (joined_net)
		6706
		6707
		6708
		6709	state 491
		6710
		6711	joined_net -> jumper_node end_item . (rule 324)
		6712
		6713	$default reduce using rule 324 (joined_net)
		6714
		6715
		6716
		6717	state 492
		6718
		6719	jumper_node -> netname '(' . astring ')' (rule 326)
		6720
		6721	QUOTED_STRING shift, and go to state 54
		6722	TXT_STRING shift, and go to state 55
		6723	NUM_STRING shift, and go to state 56
		6724
		6725	astring go to state 535
		6726
		6727
		6728
		6729	state 493
		6730
		6731	rename_pin_item -> astring '.' astring . end_item (rule 335)
		6732
		6733	';' shift, and go to state 240
		6734
		6735	end_item go to state 536
		6736
		6737
		6738
		6739	state 494
		6740
		6741	rename_pin_decl -> rename_new_name '=' '(' rename_pin_items ')' end_item . (rule 330)
		6742
		6743	$default reduce using rule 330 (rename_pin_decl)
		6744
		6745
		6746
		6747	state 495
		6748
		6749	verilog_port_list -> '(' verilog_ports ')' ';' @7 . verilog_pindir_block (rule 232)
		6750
		6751	PINDIR shift, and go to state 308
		6752
		6753	PINDIR [reduce using rule 244 (verilog_pindir_block)]
		6754	$default reduce using rule 244 (verilog_pindir_block)
		6755
		6756	pin_dir go to state 315
		6757	verilog_pindir_block go to state 537
		6758	verilog_pindir_decl go to state 317
		6759
		6760
		6761
		6762	state 496
		6763
		6764	hdl_signal_names -> hdl_signal_names . ',' hdl_signal_name (rule 183)
		6765	verilog_pindir_decl -> pin_dir @8 verilog_bus_expr hdl_signal_names . ';' (rule 246)
		6766
		6767	';' shift, and go to state 538
		6768	',' shift, and go to state 385
		6769
		6770
		6771
		6772	state 497
		6773
		6774	verilog_port_map -> '.' astring . '(' astring verilog_bus_expr ')' (rule 262)
		6775	verilog_port_map -> '.' astring . '(' ')' (rule 263)
		6776
		6777	'(' shift, and go to state 539
		6778
		6779
		6780
		6781	state 498
		6782
		6783	verilog_module_instance -> astring astring '(' verilog_port_map_list ')' . ';' (rule 257)
		6784
		6785	';' shift, and go to state 540
		6786
		6787
		6788
		6789	state 499
		6790
		6791	verilog_port_maps -> verilog_port_maps ',' . verilog_port_map (rule 260)
		6792
		6793	'.' shift, and go to state 438
		6794
		6795	verilog_port_map go to state 541
		6796
		6797
		6798
		6799	state 500
		6800
		6801	verilog_bus_expr -> '[' expr ':' expr ']' . (rule 239)
		6802
		6803	$default reduce using rule 239 (verilog_bus_expr)
		6804
		6805
		6806
		6807	state 501
		6808
		6809	generic_defn_type -> DECLARATION @11 . assign_words (rule 283)
		6810
		6811	ASSIGN shift, and go to state 542
		6812
		6813	$default reduce using rule 296 (assign_words)
		6814
		6815	assign_words go to state 543
		6816
		6817
		6818
		6819	state 502
		6820
		6821	generic_defn_type -> INSTANCE @12 . assign_words (rule 285)
		6822
		6823	ASSIGN shift, and go to state 542
		6824
		6825	$default reduce using rule 296 (assign_words)
		6826
		6827	assign_words go to state 544
		6828
		6829
		6830
		6831	state 503
		6832
		6833	opt_integer -> ASSIGN . expr (rule 291)
		6834
		6835	TRUE shift, and go to state 27
		6836	FALSE shift, and go to state 28
		6837	TXT_STRING shift, and go to state 31
		6838	NUM_STRING shift, and go to state 32
		6839	'~' shift, and go to state 33
		6840	'(' shift, and go to state 34
		6841	'-' shift, and go to state 35
		6842
		6843	primary_expr go to state 41
		6844	mult_expr go to state 42
		6845	add_expr go to state 43
		6846	shift_expr go to state 44
		6847	relational_expr go to state 45
		6848	equality_expr go to state 46
		6849	and_expr go to state 47
		6850	exor_expr go to state 48
		6851	or_expr go to state 49
		6852	logand_expr go to state 50
		6853	logor_expr go to state 51
		6854	cond_expr go to state 52
		6855	expr go to state 545
		6856
		6857
		6858
		6859	state 504
		6860
		6861	generic_defn_type -> BOOLEAN opt_integer . (rule 280)
		6862
		6863	$default reduce using rule 280 (generic_defn_type)
		6864
		6865
		6866
		6867	state 505
		6868
		6869	generic_defn_type -> INTEGER RANGE . opt_bus_range (rule 281)
		6870
		6871	ASSIGN shift, and go to state 546
		6872
		6873	$default reduce using rule 294 (opt_bus_range)
		6874
		6875	opt_bus_range go to state 547
		6876
		6877
		6878
		6879	state 506
		6880
		6881	generic_defn_type -> INTEGER opt_integer . (rule 279)
		6882
		6883	$default reduce using rule 279 (generic_defn_type)
		6884
		6885
		6886
		6887	state 507
		6888
		6889	generic_defn_type -> ATTRIBUTE opt_integer . (rule 290)
		6890
		6891	$default reduce using rule 290 (generic_defn_type)
		6892
		6893
		6894
		6895	state 508
		6896
		6897	generic_defn_type -> ENV_STRING @14 . assign_words (rule 289)
		6898
		6899	ASSIGN shift, and go to state 542
		6900
		6901	$default reduce using rule 296 (assign_words)
		6902
		6903	assign_words go to state 548
		6904
		6905
		6906
		6907	state 509
		6908
		6909	generic_defn_type -> STRING @13 . assign_words (rule 287)
		6910
		6911	ASSIGN shift, and go to state 542
		6912
		6913	$default reduce using rule 296 (assign_words)
		6914
		6915	assign_words go to state 549
		6916
		6917
		6918
		6919	state 510
		6920
		6921	vhdl_generic_decl -> GENERIC '(' @3 . generic_defn_lines ')' end_item (rule 147)
		6922
		6923	CONSTANT shift, and go to state 156
		6924
		6925	';' reduce using rule 270 (generic_defn_lines)
		6926	')' reduce using rule 270 (generic_defn_lines)
		6927	$default reduce using rule 272 (generic_const_opt)
		6928	generic_defn_lines go to state 550
		6929	generic_const_opt go to state 158
		6930	generic_defn_text go to state 159
		6931
		6932
		6933
		6934	state 511
		6935
		6936	vhdl_port_decl -> PORT '(' . vhdl_port_list ')' end_item (rule 150)
		6937
		6938	GND shift, and go to state 131
		6939	VCC shift, and go to state 132
		6940	QUOTED_STRING shift, and go to state 54
		6941	TXT_STRING shift, and go to state 55
		6942	NUM_STRING shift, and go to state 56
		6943
		6944	$default reduce using rule 153 (vhdl_port_list)
		6945
		6946	astring go to state 133
		6947	vhdl_port_list go to state 551
		6948	vhdl_port_item go to state 552
		6949	vhdl_name_list go to state 553
		6950	hdl_name_part go to state 554
		6951	netname go to state 314
		6952
		6953
		6954
		6955	state 512
		6956
		6957	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END . TXT_STRING end_item (rule 142)
		6958
		6959	TXT_STRING shift, and go to state 555
		6960
		6961
		6962
		6963	state 513
		6964
		6965	vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK . vhdl_architecture_body_items END astring end_item (rule 160)
		6966
		6967	QUOTED_STRING shift, and go to state 54
		6968	TXT_STRING shift, and go to state 556
		6969	NUM_STRING shift, and go to state 56
		6970
		6971	QUOTED_STRING [reduce using rule 189 (vhdl_architecture_body_items)]
		6972	TXT_STRING [reduce using rule 189 (vhdl_architecture_body_items)]
		6973	NUM_STRING [reduce using rule 189 (vhdl_architecture_body_items)]
		6974	$default reduce using rule 189 (vhdl_architecture_body_items)
		6975
		6976	astring go to state 230
		6977	vhdl_architecture_body_items go to state 557
		6978	vhdl_architecture_body_item go to state 558
		6979	vhdl_component_instance go to state 559
		6980	vhdl_inst_comp_binding go to state 560
		6981	vhdl_concurrent_assignment go to state 561
		6982
		6983
		6984
		6985	state 514
		6986
		6987	vhdl_architecture_declarations -> vhdl_architecture_declarations vhdl_architecture_decl . (rule 161)
		6988
		6989	$default reduce using rule 161 (vhdl_architecture_declarations)
		6990
		6991
		6992
		6993	state 515
		6994
		6995	vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' . vhdl_type end_item (rule 182)
		6996
		6997	BOOLEAN shift, and go to state 562
		6998	INTEGER shift, and go to state 563
		6999	NATURAL shift, and go to state 564
		7000	QUOTED_STRING shift, and go to state 54
		7001	TXT_STRING shift, and go to state 55
		7002	NUM_STRING shift, and go to state 56
		7003
		7004	astring go to state 565
		7005	vhdl_type go to state 566
		7006
		7007
		7008
		7009	state 516
		7010
		7011	vhdl_constant_decl -> CONSTANT @4 generic_defn_text end_item . (rule 180)
		7012
		7013	$default reduce using rule 180 (vhdl_constant_decl)
		7014
		7015
		7016
		7017	state 517
		7018
		7019	vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt . END COMPONENT end_item (rule 177)
		7020
		7021	END shift, and go to state 567
		7022
		7023
		7024
		7025	state 518
		7026
		7027	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring . USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
		7028
		7029	USE shift, and go to state 568
		7030
		7031
		7032
		7033	state 519
		7034
		7035	vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END astring end_item . (rule 168)
		7036
		7037	$default reduce using rule 168 (vhdl_package_decl)
		7038
		7039
		7040
		7041	state 520
		7042
		7043	equivalent_pin -> astring . (rule 131)
		7044
		7045	$default reduce using rule 131 (equivalent_pin)
		7046
		7047
		7048
		7049	state 521
		7050
		7051	pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins . ')' end_item (rule 127)
		7052
		7053	')' shift, and go to state 569
		7054
		7055
		7056
		7057	state 522
		7058
		7059	equivalent_pins -> equivalent_pin . end_item equivalent_pins (rule 128)
		7060	equivalent_pins -> equivalent_pin . (rule 129)
		7061
		7062	';' shift, and go to state 240
		7063
		7064	$default reduce using rule 129 (equivalent_pins)
		7065
		7066	end_item go to state 570
		7067
		7068
		7069
		7070	state 523
		7071
		7072	pin_rest -> LOCATION '=' astring . (rule 49)
		7073
		7074	$default reduce using rule 49 (pin_rest)
		7075
		7076
		7077
		7078	state 524
		7079
		7080	pin_group -> '(' NUM_STRING . ')' (rule 51)
		7081
		7082	')' shift, and go to state 571
		7083
		7084
		7085
		7086	state 525
		7087
		7088	pin_rest -> pin_dir pin_group '=' . pin_ident vhdl_type_opt (rule 47)
		7089
		7090	GND shift, and go to state 131
		7091	VCC shift, and go to state 132
		7092	QUOTED_STRING shift, and go to state 54
		7093	TXT_STRING shift, and go to state 55
		7094	NUM_STRING shift, and go to state 56
		7095
		7096	astring go to state 133
		7097	pin_ident go to state 572
		7098	netname go to state 573
		7099
		7100
		7101
		7102	state 526
		7103
		7104	more_colons -> ':' more_colons . (rule 68)
		7105
		7106	$default reduce using rule 68 (more_colons)
		7107
		7108
		7109
		7110	state 527
		7111
		7112	apex_info_line -> VCC ':' astring ':' NUM_STRING . (rule 63)
		7113
		7114	$default reduce using rule 63 (apex_info_line)
		7115
		7116
		7117
		7118	state 528
		7119
		7120	apex_info_line -> TXT_STRING ':' astring ':' PINDIR . ':' astring ':' (rule 66)
		7121
		7122	':' shift, and go to state 574
		7123
		7124
		7125
		7126	state 529
		7127
		7128	apex_info_line -> TXT_STRING '[' expr ']' ':' . astring ':' PINDIR ':' astring ':' (rule 67)
		7129
		7130	QUOTED_STRING shift, and go to state 54
		7131	TXT_STRING shift, and go to state 55
		7132	NUM_STRING shift, and go to state 56
		7133
		7134	astring go to state 575
		7135
		7136
		7137
		7138	state 530
		7139
		7140	skt_id -> astring . (rule 362)
		7141
		7142	$default reduce using rule 362 (skt_id)
		7143
		7144
		7145
		7146	state 531
		7147
		7148	conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist . END_CONN @17 end_item (rule 352)
		7149	nodelist -> nodelist . net_node (rule 356)
		7150
		7151	END_CONN shift, and go to state 576
		7152	QUOTED_STRING shift, and go to state 54
		7153	TXT_STRING shift, and go to state 55
		7154	NUM_STRING shift, and go to state 56
		7155
		7156	astring go to state 530
		7157	net_node go to state 577
		7158	skt_id go to state 533
		7159
		7160
		7161
		7162	state 532
		7163
		7164	nodelist -> net_node . (rule 357)
		7165
		7166	$default reduce using rule 357 (nodelist)
		7167
		7168
		7169
		7170	state 533
		7171
		7172	net_node -> skt_id . '(' node_id ')' fix_loc_part force_pin_dir node_group end_item (rule 359)
		7173
		7174	'(' shift, and go to state 578
		7175
		7176
		7177
		7178	state 534
		7179
		7180	join_decl -> alias_part root_net '=' '(' joined_nets ')' end_item . (rule 313)
		7181
		7182	$default reduce using rule 313 (join_decl)
		7183
		7184
		7185
		7186	state 535
		7187
		7188	jumper_node -> netname '(' astring . ')' (rule 326)
		7189
		7190	')' shift, and go to state 579
		7191
		7192
		7193
		7194	state 536
		7195
		7196	rename_pin_item -> astring '.' astring end_item . (rule 335)
		7197
		7198	$default reduce using rule 335 (rename_pin_item)
		7199
		7200
		7201
		7202	state 537
		7203
		7204	verilog_port_list -> '(' verilog_ports ')' ';' @7 verilog_pindir_block . (rule 232)
		7205	verilog_pindir_block -> verilog_pindir_block . verilog_pindir_decl (rule 242)
		7206
		7207	PINDIR shift, and go to state 308
		7208
		7209	PINDIR [reduce using rule 232 (verilog_port_list)]
		7210	$default reduce using rule 232 (verilog_port_list)
		7211
		7212	pin_dir go to state 315
		7213	verilog_pindir_decl go to state 380
		7214
		7215
		7216
		7217	state 538
		7218
		7219	verilog_pindir_decl -> pin_dir @8 verilog_bus_expr hdl_signal_names ';' . (rule 246)
		7220
		7221	$default reduce using rule 246 (verilog_pindir_decl)
		7222
		7223
		7224
		7225	state 539
		7226
		7227	verilog_port_map -> '.' astring '(' . astring verilog_bus_expr ')' (rule 262)
		7228	verilog_port_map -> '.' astring '(' . ')' (rule 263)
		7229
		7230	QUOTED_STRING shift, and go to state 54
		7231	TXT_STRING shift, and go to state 55
		7232	NUM_STRING shift, and go to state 56
		7233	')' shift, and go to state 580
		7234
		7235	astring go to state 581
		7236
		7237
		7238
		7239	state 540
		7240
		7241	verilog_module_instance -> astring astring '(' verilog_port_map_list ')' ';' . (rule 257)
		7242
		7243	$default reduce using rule 257 (verilog_module_instance)
		7244
		7245
		7246
		7247	state 541
		7248
		7249	verilog_port_maps -> verilog_port_maps ',' verilog_port_map . (rule 260)
		7250
		7251	$default reduce using rule 260 (verilog_port_maps)
		7252
		7253
		7254
		7255	state 542
		7256
		7257	assign_words -> ASSIGN . several_words (rule 295)
		7258
		7259	QUOTED_STRING shift, and go to state 54
		7260	TXT_STRING shift, and go to state 55
		7261	NUM_STRING shift, and go to state 56
		7262
		7263	astring go to state 582
		7264	several_words go to state 583
		7265	word go to state 584
		7266
		7267
		7268
		7269	state 543
		7270
		7271	generic_defn_type -> DECLARATION @11 assign_words . (rule 283)
		7272
		7273	$default reduce using rule 283 (generic_defn_type)
		7274
		7275
		7276
		7277	state 544
		7278
		7279	generic_defn_type -> INSTANCE @12 assign_words . (rule 285)
		7280
		7281	$default reduce using rule 285 (generic_defn_type)
		7282
		7283
		7284
		7285	state 545
		7286
		7287	opt_integer -> ASSIGN expr . (rule 291)
		7288
		7289	$default reduce using rule 291 (opt_integer)
		7290
		7291
		7292
		7293	state 546
		7294
		7295	opt_bus_range -> ASSIGN . bus_range (rule 293)
		7296
		7297	TRUE shift, and go to state 27
		7298	FALSE shift, and go to state 28
		7299	QUOTE shift, and go to state 29
		7300	QUOTED_STRING shift, and go to state 30
		7301	TXT_STRING shift, and go to state 31
		7302	NUM_STRING shift, and go to state 32
		7303	'~' shift, and go to state 33
		7304	'(' shift, and go to state 34
		7305	'-' shift, and go to state 35
		7306
		7307	bus_range go to state 585
		7308	expr1 go to state 39
		7309	simple_range_expr go to state 40
		7310	primary_expr go to state 41
		7311	mult_expr go to state 42
		7312	add_expr go to state 43
		7313	shift_expr go to state 44
		7314	relational_expr go to state 45
		7315	equality_expr go to state 46
		7316	and_expr go to state 47
		7317	exor_expr go to state 48
		7318	or_expr go to state 49
		7319	logand_expr go to state 50
		7320	logor_expr go to state 51
		7321	cond_expr go to state 52
		7322	expr go to state 53
		7323
		7324
		7325
		7326	state 547
		7327
		7328	generic_defn_type -> INTEGER RANGE opt_bus_range . (rule 281)
		7329
		7330	$default reduce using rule 281 (generic_defn_type)
		7331
		7332
		7333
		7334	state 548
		7335
		7336	generic_defn_type -> ENV_STRING @14 assign_words . (rule 289)
		7337
		7338	$default reduce using rule 289 (generic_defn_type)
		7339
		7340
		7341
		7342	state 549
		7343
		7344	generic_defn_type -> STRING @13 assign_words . (rule 287)
		7345
		7346	$default reduce using rule 287 (generic_defn_type)
		7347
		7348
		7349
		7350	state 550
		7351
		7352	vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines . ')' end_item (rule 147)
		7353	generic_defn_lines -> generic_defn_lines . end_item generic_defn_text (rule 268)
		7354
		7355	';' shift, and go to state 240
		7356	')' shift, and go to state 586
		7357
		7358	end_item go to state 258
		7359
		7360
		7361
		7362	state 551
		7363
		7364	vhdl_port_decl -> PORT '(' vhdl_port_list . ')' end_item (rule 150)
		7365	vhdl_port_list -> vhdl_port_list . end_item vhdl_port_item (rule 151)
		7366
		7367	';' shift, and go to state 240
		7368	')' shift, and go to state 587
		7369
		7370	end_item go to state 588
		7371
		7372
		7373
		7374	state 552
		7375
		7376	vhdl_port_list -> vhdl_port_item . (rule 152)
		7377
		7378	$default reduce using rule 152 (vhdl_port_list)
		7379
		7380
		7381
		7382	state 553
		7383
		7384	vhdl_port_item -> vhdl_name_list . ':' pin_dir vhdl_type vhdl_assign_opt (rule 154)
		7385	vhdl_name_list -> vhdl_name_list . ',' hdl_name_part (rule 155)
		7386
		7387	':' shift, and go to state 589
		7388	',' shift, and go to state 590
		7389
		7390
		7391
		7392	state 554
		7393
		7394	vhdl_name_list -> hdl_name_part . (rule 156)
		7395
		7396	$default reduce using rule 156 (vhdl_name_list)
		7397
		7398
		7399
		7400	state 555
		7401
		7402	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING . end_item (rule 142)
		7403
		7404	';' shift, and go to state 240
		7405
		7406	end_item go to state 591
		7407
		7408
		7409
		7410	state 556
		7411
		7412	astring -> TXT_STRING . (rule 20)
		7413	vhdl_inst_comp_binding -> TXT_STRING . ':' TXT_STRING (rule 193)
		7414
		7415	':' shift, and go to state 592
		7416
		7417	$default reduce using rule 20 (astring)
		7418
		7419
		7420
		7421	state 557
		7422
		7423	vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items . END astring end_item (rule 160)
		7424	vhdl_architecture_body_items -> vhdl_architecture_body_items . vhdl_architecture_body_item (rule 187)
		7425
		7426	END shift, and go to state 593
		7427	QUOTED_STRING shift, and go to state 54
		7428	TXT_STRING shift, and go to state 556
		7429	NUM_STRING shift, and go to state 56
		7430
		7431	astring go to state 230
		7432	vhdl_architecture_body_item go to state 594
		7433	vhdl_component_instance go to state 559
		7434	vhdl_inst_comp_binding go to state 560
		7435	vhdl_concurrent_assignment go to state 561
		7436
		7437
		7438
		7439	state 558
		7440
		7441	vhdl_architecture_body_items -> vhdl_architecture_body_item . (rule 188)
		7442
		7443	$default reduce using rule 188 (vhdl_architecture_body_items)
		7444
		7445
		7446
		7447	state 559
		7448
		7449	vhdl_architecture_body_item -> vhdl_component_instance . (rule 191)
		7450
		7451	$default reduce using rule 191 (vhdl_architecture_body_item)
		7452
		7453
		7454
		7455	state 560
		7456
		7457	vhdl_component_instance -> vhdl_inst_comp_binding . vhdl_inst_generic_map vhdl_inst_port_map end_item (rule 192)
		7458
		7459	GENERIC shift, and go to state 595
		7460
		7461	$default reduce using rule 196 (vhdl_inst_generic_map)
		7462
		7463	vhdl_inst_generic_map go to state 596
		7464
		7465
		7466
		7467	state 561
		7468
		7469	vhdl_architecture_body_item -> vhdl_concurrent_assignment . (rule 190)
		7470
		7471	$default reduce using rule 190 (vhdl_architecture_body_item)
		7472
		7473
		7474
		7475	state 562
		7476
		7477	vhdl_type -> BOOLEAN . vhdl_type_default_value_opt (rule 78)
		7478
		7479	ASSIGN shift, and go to state 597
		7480
		7481	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		7482	$default reduce using rule 80 (vhdl_type_default_value_opt)
		7483
		7484	vhdl_type_default_value_opt go to state 598
		7485
		7486
		7487
		7488	state 563
		7489
		7490	vhdl_type -> INTEGER . vhdl_type_default_value_opt (rule 74)
		7491	vhdl_type -> INTEGER . RANGE simple_range_expr vhdl_type_default_value_opt (rule 75)
		7492
		7493	ASSIGN shift, and go to state 597
		7494	RANGE shift, and go to state 599
		7495
		7496	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		7497	$default reduce using rule 80 (vhdl_type_default_value_opt)
		7498
		7499	vhdl_type_default_value_opt go to state 600
		7500
		7501
		7502
		7503	state 564
		7504
		7505	vhdl_type -> NATURAL . vhdl_type_default_value_opt (rule 76)
		7506	vhdl_type -> NATURAL . RANGE simple_range_expr vhdl_type_default_value_opt (rule 77)
		7507
		7508	ASSIGN shift, and go to state 597
		7509	RANGE shift, and go to state 601
		7510
		7511	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		7512	$default reduce using rule 80 (vhdl_type_default_value_opt)
		7513
		7514	vhdl_type_default_value_opt go to state 602
		7515
		7516
		7517
		7518	state 565
		7519
		7520	vhdl_type -> astring . vhdl_type_default_value_opt (rule 72)
		7521	vhdl_type -> astring . '(' bus_range ')' vhdl_type_default_value_opt (rule 73)
		7522
		7523	ASSIGN shift, and go to state 597
		7524	'(' shift, and go to state 603
		7525
		7526	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		7527	$default reduce using rule 80 (vhdl_type_default_value_opt)
		7528
		7529	vhdl_type_default_value_opt go to state 604
		7530
		7531
		7532
		7533	state 566
		7534
		7535	vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' vhdl_type . end_item (rule 182)
		7536
		7537	';' shift, and go to state 240
		7538
		7539	end_item go to state 605
		7540
		7541
		7542
		7543	state 567
		7544
		7545	vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END . COMPONENT end_item (rule 177)
		7546
		7547	COMPONENT shift, and go to state 606
		7548
		7549
		7550
		7551	state 568
		7552
		7553	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE . ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
		7554
		7555	ENTITY shift, and go to state 607
		7556
		7557
		7558
		7559	state 569
		7560
		7561	pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins ')' . end_item (rule 127)
		7562
		7563	';' shift, and go to state 240
		7564
		7565	end_item go to state 608
		7566
		7567
		7568
		7569	state 570
		7570
		7571	equivalent_pins -> equivalent_pin end_item . equivalent_pins (rule 128)
		7572
		7573	QUOTED_STRING shift, and go to state 54
		7574	TXT_STRING shift, and go to state 55
		7575	NUM_STRING shift, and go to state 56
		7576
		7577	$default reduce using rule 130 (equivalent_pins)
		7578
		7579	astring go to state 520
		7580	equivalent_pins go to state 609
		7581	equivalent_pin go to state 522
		7582
		7583
		7584
		7585	state 571
		7586
		7587	pin_group -> '(' NUM_STRING ')' . (rule 51)
		7588
		7589	$default reduce using rule 51 (pin_group)
		7590
		7591
		7592
		7593	state 572
		7594
		7595	pin_rest -> pin_dir pin_group '=' pin_ident . vhdl_type_opt (rule 47)
		7596
		7597	':' shift, and go to state 610
		7598
		7599	$default reduce using rule 71 (vhdl_type_opt)
		7600
		7601	vhdl_type_opt go to state 611
		7602
		7603
		7604
		7605	state 573
		7606
		7607	pin_ident -> netname . (rule 53)
		7608
		7609	$default reduce using rule 53 (pin_ident)
		7610
		7611
		7612
		7613	state 574
		7614
		7615	apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' . astring ':' (rule 66)
		7616
		7617	QUOTED_STRING shift, and go to state 54
		7618	TXT_STRING shift, and go to state 55
		7619	NUM_STRING shift, and go to state 56
		7620
		7621	astring go to state 612
		7622
		7623
		7624
		7625	state 575
		7626
		7627	apex_info_line -> TXT_STRING '[' expr ']' ':' astring . ':' PINDIR ':' astring ':' (rule 67)
		7628
		7629	':' shift, and go to state 613
		7630
		7631
		7632
		7633	state 576
		7634
		7635	conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN . @17 end_item (rule 352)
		7636
		7637	$default reduce using rule 351 (@17)
		7638
		7639	@17 go to state 614
		7640
		7641
		7642
		7643	state 577
		7644
		7645	nodelist -> nodelist net_node . (rule 356)
		7646
		7647	$default reduce using rule 356 (nodelist)
		7648
		7649
		7650
		7651	state 578
		7652
		7653	net_node -> skt_id '(' . node_id ')' fix_loc_part force_pin_dir node_group end_item (rule 359)
		7654
		7655	GND shift, and go to state 131
		7656	VCC shift, and go to state 132
		7657	QUOTED_STRING shift, and go to state 54
		7658	TXT_STRING shift, and go to state 55
		7659	NUM_STRING shift, and go to state 56
		7660
		7661	astring go to state 133
		7662	node_id go to state 615
		7663	netname go to state 616
		7664
		7665
		7666
		7667	state 579
		7668
		7669	jumper_node -> netname '(' astring ')' . (rule 326)
		7670
		7671	$default reduce using rule 326 (jumper_node)
		7672
		7673
		7674
		7675	state 580
		7676
		7677	verilog_port_map -> '.' astring '(' ')' . (rule 263)
		7678
		7679	$default reduce using rule 263 (verilog_port_map)
		7680
		7681
		7682
		7683	state 581
		7684
		7685	verilog_port_map -> '.' astring '(' astring . verilog_bus_expr ')' (rule 262)
		7686
		7687	'[' shift, and go to state 255
		7688
		7689	$default reduce using rule 240 (verilog_bus_expr)
		7690
		7691	verilog_bus_expr go to state 617
		7692
		7693
		7694
		7695	state 582
		7696
		7697	word -> astring . (rule 299)
		7698
		7699	$default reduce using rule 299 (word)
		7700
		7701
		7702
		7703	state 583
		7704
		7705	assign_words -> ASSIGN several_words . (rule 295)
		7706
		7707	$default reduce using rule 295 (assign_words)
		7708
		7709
		7710
		7711	state 584
		7712
		7713	several_words -> word . several_words (rule 297)
		7714	several_words -> word . (rule 298)
		7715
		7716	QUOTED_STRING shift, and go to state 54
		7717	TXT_STRING shift, and go to state 55
		7718	NUM_STRING shift, and go to state 56
		7719
		7720	$default reduce using rule 298 (several_words)
		7721
		7722	astring go to state 582
		7723	several_words go to state 618
		7724	word go to state 584
		7725
		7726
		7727
		7728	state 585
		7729
		7730	opt_bus_range -> ASSIGN bus_range . (rule 293)
		7731
		7732	$default reduce using rule 293 (opt_bus_range)
		7733
		7734
		7735
		7736	state 586
		7737
		7738	vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines ')' . end_item (rule 147)
		7739
		7740	';' shift, and go to state 240
		7741
		7742	end_item go to state 619
		7743
		7744
		7745
		7746	state 587
		7747
		7748	vhdl_port_decl -> PORT '(' vhdl_port_list ')' . end_item (rule 150)
		7749
		7750	';' shift, and go to state 240
		7751
		7752	end_item go to state 620
		7753
		7754
		7755
		7756	state 588
		7757
		7758	vhdl_port_list -> vhdl_port_list end_item . vhdl_port_item (rule 151)
		7759
		7760	GND shift, and go to state 131
		7761	VCC shift, and go to state 132
		7762	QUOTED_STRING shift, and go to state 54
		7763	TXT_STRING shift, and go to state 55
		7764	NUM_STRING shift, and go to state 56
		7765
		7766	astring go to state 133
		7767	vhdl_port_item go to state 621
		7768	vhdl_name_list go to state 553
		7769	hdl_name_part go to state 554
		7770	netname go to state 314
		7771
		7772
		7773
		7774	state 589
		7775
		7776	vhdl_port_item -> vhdl_name_list ':' . pin_dir vhdl_type vhdl_assign_opt (rule 154)
		7777
		7778	PINDIR shift, and go to state 308
		7779
		7780	pin_dir go to state 622
		7781
		7782
		7783
		7784	state 590
		7785
		7786	vhdl_name_list -> vhdl_name_list ',' . hdl_name_part (rule 155)
		7787
		7788	GND shift, and go to state 131
		7789	VCC shift, and go to state 132
		7790	QUOTED_STRING shift, and go to state 54
		7791	TXT_STRING shift, and go to state 55
		7792	NUM_STRING shift, and go to state 56
		7793
		7794	astring go to state 133
		7795	hdl_name_part go to state 623
		7796	netname go to state 314
		7797
		7798
		7799
		7800	state 591
		7801
		7802	vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item . (rule 142)
		7803
		7804	$default reduce using rule 142 (vhdl_chip_decl)
		7805
		7806
		7807
		7808	state 592
		7809
		7810	vhdl_inst_comp_binding -> TXT_STRING ':' . TXT_STRING (rule 193)
		7811
		7812	TXT_STRING shift, and go to state 624
		7813
		7814
		7815
		7816	state 593
		7817
		7818	vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END . astring end_item (rule 160)
		7819
		7820	QUOTED_STRING shift, and go to state 54
		7821	TXT_STRING shift, and go to state 55
		7822	NUM_STRING shift, and go to state 56
		7823
		7824	astring go to state 625
		7825
		7826
		7827
		7828	state 594
		7829
		7830	vhdl_architecture_body_items -> vhdl_architecture_body_items vhdl_architecture_body_item . (rule 187)
		7831
		7832	$default reduce using rule 187 (vhdl_architecture_body_items)
		7833
		7834
		7835
		7836	state 595
		7837
		7838	vhdl_inst_generic_map -> GENERIC . MAP @6 '(' vhdl_gen_map_list ')' (rule 195)
		7839
		7840	MAP shift, and go to state 626
		7841
		7842
		7843
		7844	state 596
		7845
		7846	vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map . vhdl_inst_port_map end_item (rule 192)
		7847
		7848	PORT shift, and go to state 627
		7849
		7850	$default reduce using rule 198 (vhdl_inst_port_map)
		7851
		7852	vhdl_inst_port_map go to state 628
		7853
		7854
		7855
		7856	state 597
		7857
		7858	vhdl_type_default_value_opt -> ASSIGN . bus_range (rule 79)
		7859
		7860	TRUE shift, and go to state 27
		7861	FALSE shift, and go to state 28
		7862	QUOTE shift, and go to state 29
		7863	QUOTED_STRING shift, and go to state 30
		7864	TXT_STRING shift, and go to state 31
		7865	NUM_STRING shift, and go to state 32
		7866	'~' shift, and go to state 33
		7867	'(' shift, and go to state 34
		7868	'-' shift, and go to state 35
		7869
		7870	bus_range go to state 629
		7871	expr1 go to state 39
		7872	simple_range_expr go to state 40
		7873	primary_expr go to state 41
		7874	mult_expr go to state 42
		7875	add_expr go to state 43
		7876	shift_expr go to state 44
		7877	relational_expr go to state 45
		7878	equality_expr go to state 46
		7879	and_expr go to state 47
		7880	exor_expr go to state 48
		7881	or_expr go to state 49
		7882	logand_expr go to state 50
		7883	logor_expr go to state 51
		7884	cond_expr go to state 52
		7885	expr go to state 53
		7886
		7887
		7888
		7889	state 598
		7890
		7891	vhdl_type -> BOOLEAN vhdl_type_default_value_opt . (rule 78)
		7892
		7893	$default reduce using rule 78 (vhdl_type)
		7894
		7895
		7896
		7897	state 599
		7898
		7899	vhdl_type -> INTEGER RANGE . simple_range_expr vhdl_type_default_value_opt (rule 75)
		7900
		7901	TRUE shift, and go to state 27
		7902	FALSE shift, and go to state 28
		7903	TXT_STRING shift, and go to state 31
		7904	NUM_STRING shift, and go to state 32
		7905	'~' shift, and go to state 33
		7906	'(' shift, and go to state 34
		7907	'-' shift, and go to state 35
		7908
		7909	simple_range_expr go to state 630
		7910	primary_expr go to state 41
		7911	mult_expr go to state 42
		7912	add_expr go to state 43
		7913	shift_expr go to state 44
		7914	relational_expr go to state 45
		7915	equality_expr go to state 46
		7916	and_expr go to state 47
		7917	exor_expr go to state 48
		7918	or_expr go to state 49
		7919	logand_expr go to state 50
		7920	logor_expr go to state 51
		7921	cond_expr go to state 52
		7922	expr go to state 631
		7923
		7924
		7925
		7926	state 600
		7927
		7928	vhdl_type -> INTEGER vhdl_type_default_value_opt . (rule 74)
		7929
		7930	$default reduce using rule 74 (vhdl_type)
		7931
		7932
		7933
		7934	state 601
		7935
		7936	vhdl_type -> NATURAL RANGE . simple_range_expr vhdl_type_default_value_opt (rule 77)
		7937
		7938	TRUE shift, and go to state 27
		7939	FALSE shift, and go to state 28
		7940	TXT_STRING shift, and go to state 31
		7941	NUM_STRING shift, and go to state 32
		7942	'~' shift, and go to state 33
		7943	'(' shift, and go to state 34
		7944	'-' shift, and go to state 35
		7945
		7946	simple_range_expr go to state 632
		7947	primary_expr go to state 41
		7948	mult_expr go to state 42
		7949	add_expr go to state 43
		7950	shift_expr go to state 44
		7951	relational_expr go to state 45
		7952	equality_expr go to state 46
		7953	and_expr go to state 47
		7954	exor_expr go to state 48
		7955	or_expr go to state 49
		7956	logand_expr go to state 50
		7957	logor_expr go to state 51
		7958	cond_expr go to state 52
		7959	expr go to state 631
		7960
		7961
		7962
		7963	state 602
		7964
		7965	vhdl_type -> NATURAL vhdl_type_default_value_opt . (rule 76)
		7966
		7967	$default reduce using rule 76 (vhdl_type)
		7968
		7969
		7970
		7971	state 603
		7972
		7973	vhdl_type -> astring '(' . bus_range ')' vhdl_type_default_value_opt (rule 73)
		7974
		7975	TRUE shift, and go to state 27
		7976	FALSE shift, and go to state 28
		7977	QUOTE shift, and go to state 29
		7978	QUOTED_STRING shift, and go to state 30
		7979	TXT_STRING shift, and go to state 31
		7980	NUM_STRING shift, and go to state 32
		7981	'~' shift, and go to state 33
		7982	'(' shift, and go to state 34
		7983	'-' shift, and go to state 35
		7984
		7985	bus_range go to state 633
		7986	expr1 go to state 39
		7987	simple_range_expr go to state 40
		7988	primary_expr go to state 41
		7989	mult_expr go to state 42
		7990	add_expr go to state 43
		7991	shift_expr go to state 44
		7992	relational_expr go to state 45
		7993	equality_expr go to state 46
		7994	and_expr go to state 47
		7995	exor_expr go to state 48
		7996	or_expr go to state 49
		7997	logand_expr go to state 50
		7998	logor_expr go to state 51
		7999	cond_expr go to state 52
		8000	expr go to state 53
		8001
		8002
		8003
		8004	state 604
		8005
		8006	vhdl_type -> astring vhdl_type_default_value_opt . (rule 72)
		8007
		8008	$default reduce using rule 72 (vhdl_type)
		8009
		8010
		8011
		8012	state 605
		8013
		8014	vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' vhdl_type end_item . (rule 182)
		8015
		8016	$default reduce using rule 182 (vhdl_signal_decl)
		8017
		8018
		8019
		8020	state 606
		8021
		8022	vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT . end_item (rule 177)
		8023
		8024	';' shift, and go to state 240
		8025
		8026	end_item go to state 634
		8027
		8028
		8029
		8030	state 607
		8031
		8032	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY . astring '.' astring '(' astring ')' ';' (rule 186)
		8033
		8034	QUOTED_STRING shift, and go to state 54
		8035	TXT_STRING shift, and go to state 55
		8036	NUM_STRING shift, and go to state 56
		8037
		8038	astring go to state 635
		8039
		8040
		8041
		8042	state 608
		8043
		8044	pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins ')' end_item . (rule 127)
		8045
		8046	$default reduce using rule 127 (pin_equivalence)
		8047
		8048
		8049
		8050	state 609
		8051
		8052	equivalent_pins -> equivalent_pin end_item equivalent_pins . (rule 128)
		8053
		8054	$default reduce using rule 128 (equivalent_pins)
		8055
		8056
		8057
		8058	state 610
		8059
		8060	vhdl_type_opt -> ':' . vhdl_type (rule 70)
		8061
		8062	BOOLEAN shift, and go to state 562
		8063	INTEGER shift, and go to state 563
		8064	NATURAL shift, and go to state 564
		8065	QUOTED_STRING shift, and go to state 54
		8066	TXT_STRING shift, and go to state 55
		8067	NUM_STRING shift, and go to state 56
		8068
		8069	astring go to state 565
		8070	vhdl_type go to state 636
		8071
		8072
		8073
		8074	state 611
		8075
		8076	pin_rest -> pin_dir pin_group '=' pin_ident vhdl_type_opt . (rule 47)
		8077
		8078	$default reduce using rule 47 (pin_rest)
		8079
		8080
		8081
		8082	state 612
		8083
		8084	apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' astring . ':' (rule 66)
		8085
		8086	':' shift, and go to state 637
		8087
		8088
		8089
		8090	state 613
		8091
		8092	apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' . PINDIR ':' astring ':' (rule 67)
		8093
		8094	PINDIR shift, and go to state 638
		8095
		8096
		8097
		8098	state 614
		8099
		8100	conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN @17 . end_item (rule 352)
		8101
		8102	';' shift, and go to state 240
		8103
		8104	end_item go to state 639
		8105
		8106
		8107
		8108	state 615
		8109
		8110	net_node -> skt_id '(' node_id . ')' fix_loc_part force_pin_dir node_group end_item (rule 359)
		8111
		8112	')' shift, and go to state 640
		8113
		8114
		8115
		8116	state 616
		8117
		8118	node_id -> netname . (rule 363)
		8119
		8120	$default reduce using rule 363 (node_id)
		8121
		8122
		8123
		8124	state 617
		8125
		8126	verilog_port_map -> '.' astring '(' astring verilog_bus_expr . ')' (rule 262)
		8127
		8128	')' shift, and go to state 641
		8129
		8130
		8131
		8132	state 618
		8133
		8134	several_words -> word several_words . (rule 297)
		8135
		8136	$default reduce using rule 297 (several_words)
		8137
		8138
		8139
		8140	state 619
		8141
		8142	vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines ')' end_item . (rule 147)
		8143
		8144	$default reduce using rule 147 (vhdl_generic_decl)
		8145
		8146
		8147
		8148	state 620
		8149
		8150	vhdl_port_decl -> PORT '(' vhdl_port_list ')' end_item . (rule 150)
		8151
		8152	$default reduce using rule 150 (vhdl_port_decl)
		8153
		8154
		8155
		8156	state 621
		8157
		8158	vhdl_port_list -> vhdl_port_list end_item vhdl_port_item . (rule 151)
		8159
		8160	$default reduce using rule 151 (vhdl_port_list)
		8161
		8162
		8163
		8164	state 622
		8165
		8166	vhdl_port_item -> vhdl_name_list ':' pin_dir . vhdl_type vhdl_assign_opt (rule 154)
		8167
		8168	BOOLEAN shift, and go to state 562
		8169	INTEGER shift, and go to state 563
		8170	NATURAL shift, and go to state 564
		8171	QUOTED_STRING shift, and go to state 54
		8172	TXT_STRING shift, and go to state 55
		8173	NUM_STRING shift, and go to state 56
		8174
		8175	astring go to state 565
		8176	vhdl_type go to state 642
		8177
		8178
		8179
		8180	state 623
		8181
		8182	vhdl_name_list -> vhdl_name_list ',' hdl_name_part . (rule 155)
		8183
		8184	$default reduce using rule 155 (vhdl_name_list)
		8185
		8186
		8187
		8188	state 624
		8189
		8190	vhdl_inst_comp_binding -> TXT_STRING ':' TXT_STRING . (rule 193)
		8191
		8192	$default reduce using rule 193 (vhdl_inst_comp_binding)
		8193
		8194
		8195
		8196	state 625
		8197
		8198	vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring . end_item (rule 160)
		8199
		8200	';' shift, and go to state 240
		8201
		8202	end_item go to state 643
		8203
		8204
		8205
		8206	state 626
		8207
		8208	vhdl_inst_generic_map -> GENERIC MAP . @6 '(' vhdl_gen_map_list ')' (rule 195)
		8209
		8210	$default reduce using rule 194 (@6)
		8211
		8212	@6 go to state 644
		8213
		8214
		8215
		8216	state 627
		8217
		8218	vhdl_inst_port_map -> PORT . MAP '(' vhdl_port_map_list ')' (rule 197)
		8219
		8220	MAP shift, and go to state 645
		8221
		8222
		8223
		8224	state 628
		8225
		8226	vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map vhdl_inst_port_map . end_item (rule 192)
		8227
		8228	';' shift, and go to state 240
		8229
		8230	end_item go to state 646
		8231
		8232
		8233
		8234	state 629
		8235
		8236	vhdl_type_default_value_opt -> ASSIGN bus_range . (rule 79)
		8237
		8238	$default reduce using rule 79 (vhdl_type_default_value_opt)
		8239
		8240
		8241
		8242	state 630
		8243
		8244	vhdl_type -> INTEGER RANGE simple_range_expr . vhdl_type_default_value_opt (rule 75)
		8245
		8246	ASSIGN shift, and go to state 597
		8247
		8248	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		8249	$default reduce using rule 80 (vhdl_type_default_value_opt)
		8250
		8251	vhdl_type_default_value_opt go to state 647
		8252
		8253
		8254
		8255	state 631
		8256
		8257	simple_range_expr -> expr . TO expr (rule 86)
		8258	simple_range_expr -> expr . DOWNTO expr (rule 87)
		8259
		8260	TO shift, and go to state 117
		8261	DOWNTO shift, and go to state 118
		8262
		8263
		8264
		8265	state 632
		8266
		8267	vhdl_type -> NATURAL RANGE simple_range_expr . vhdl_type_default_value_opt (rule 77)
		8268
		8269	ASSIGN shift, and go to state 597
		8270
		8271	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		8272	$default reduce using rule 80 (vhdl_type_default_value_opt)
		8273
		8274	vhdl_type_default_value_opt go to state 648
		8275
		8276
		8277
		8278	state 633
		8279
		8280	vhdl_type -> astring '(' bus_range . ')' vhdl_type_default_value_opt (rule 73)
		8281
		8282	')' shift, and go to state 649
		8283
		8284
		8285
		8286	state 634
		8287
		8288	vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item . (rule 177)
		8289
		8290	$default reduce using rule 177 (vhdl_component_decl)
		8291
		8292
		8293
		8294	state 635
		8295
		8296	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring . '.' astring '(' astring ')' ';' (rule 186)
		8297
		8298	'.' shift, and go to state 650
		8299
		8300
		8301
		8302	state 636
		8303
		8304	vhdl_type_opt -> ':' vhdl_type . (rule 70)
		8305
		8306	$default reduce using rule 70 (vhdl_type_opt)
		8307
		8308
		8309
		8310	state 637
		8311
		8312	apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' astring ':' . (rule 66)
		8313
		8314	$default reduce using rule 66 (apex_info_line)
		8315
		8316
		8317
		8318	state 638
		8319
		8320	apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR . ':' astring ':' (rule 67)
		8321
		8322	':' shift, and go to state 651
		8323
		8324
		8325
		8326	state 639
		8327
		8328	conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN @17 end_item . (rule 352)
		8329
		8330	$default reduce using rule 352 (conn_decl)
		8331
		8332
		8333
		8334	state 640
		8335
		8336	net_node -> skt_id '(' node_id ')' . fix_loc_part force_pin_dir node_group end_item (rule 359)
		8337
		8338	FIX_LOCATION shift, and go to state 652
		8339
		8340	$default reduce using rule 365 (fix_loc_part)
		8341
		8342	fix_loc_part go to state 653
		8343
		8344
		8345
		8346	state 641
		8347
		8348	verilog_port_map -> '.' astring '(' astring verilog_bus_expr ')' . (rule 262)
		8349
		8350	$default reduce using rule 262 (verilog_port_map)
		8351
		8352
		8353
		8354	state 642
		8355
		8356	vhdl_port_item -> vhdl_name_list ':' pin_dir vhdl_type . vhdl_assign_opt (rule 154)
		8357
		8358	ASSIGN shift, and go to state 654
		8359
		8360	$default reduce using rule 159 (vhdl_assign_opt)
		8361
		8362	vhdl_assign_opt go to state 655
		8363
		8364
		8365
		8366	state 643
		8367
		8368	vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item . (rule 160)
		8369
		8370	$default reduce using rule 160 (vhdl_architecture)
		8371
		8372
		8373
		8374	state 644
		8375
		8376	vhdl_inst_generic_map -> GENERIC MAP @6 . '(' vhdl_gen_map_list ')' (rule 195)
		8377
		8378	'(' shift, and go to state 656
		8379
		8380
		8381
		8382	state 645
		8383
		8384	vhdl_inst_port_map -> PORT MAP . '(' vhdl_port_map_list ')' (rule 197)
		8385
		8386	'(' shift, and go to state 657
		8387
		8388
		8389
		8390	state 646
		8391
		8392	vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map vhdl_inst_port_map end_item . (rule 192)
		8393
		8394	$default reduce using rule 192 (vhdl_component_instance)
		8395
		8396
		8397
		8398	state 647
		8399
		8400	vhdl_type -> INTEGER RANGE simple_range_expr vhdl_type_default_value_opt . (rule 75)
		8401
		8402	$default reduce using rule 75 (vhdl_type)
		8403
		8404
		8405
		8406	state 648
		8407
		8408	vhdl_type -> NATURAL RANGE simple_range_expr vhdl_type_default_value_opt . (rule 77)
		8409
		8410	$default reduce using rule 77 (vhdl_type)
		8411
		8412
		8413
		8414	state 649
		8415
		8416	vhdl_type -> astring '(' bus_range ')' . vhdl_type_default_value_opt (rule 73)
		8417
		8418	ASSIGN shift, and go to state 597
		8419
		8420	ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
		8421	$default reduce using rule 80 (vhdl_type_default_value_opt)
		8422
		8423	vhdl_type_default_value_opt go to state 658
		8424
		8425
		8426
		8427	state 650
		8428
		8429	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' . astring '(' astring ')' ';' (rule 186)
		8430
		8431	QUOTED_STRING shift, and go to state 54
		8432	TXT_STRING shift, and go to state 55
		8433	NUM_STRING shift, and go to state 56
		8434
		8435	astring go to state 659
		8436
		8437
		8438
		8439	state 651
		8440
		8441	apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' . astring ':' (rule 67)
		8442
		8443	QUOTED_STRING shift, and go to state 54
		8444	TXT_STRING shift, and go to state 55
		8445	NUM_STRING shift, and go to state 56
		8446
		8447	astring go to state 660
		8448
		8449
		8450
		8451	state 652
		8452
		8453	fix_loc_part -> FIX_LOCATION . (rule 364)
		8454
		8455	$default reduce using rule 364 (fix_loc_part)
		8456
		8457
		8458
		8459	state 653
		8460
		8461	net_node -> skt_id '(' node_id ')' fix_loc_part . force_pin_dir node_group end_item (rule 359)
		8462
		8463	PINDIR shift, and go to state 661
		8464
		8465	$default reduce using rule 361 (force_pin_dir)
		8466
		8467	force_pin_dir go to state 662
		8468
		8469
		8470
		8471	state 654
		8472
		8473	vhdl_assign_opt -> ASSIGN . expr (rule 158)
		8474
		8475	TRUE shift, and go to state 27
		8476	FALSE shift, and go to state 28
		8477	TXT_STRING shift, and go to state 31
		8478	NUM_STRING shift, and go to state 32
		8479	'~' shift, and go to state 33
		8480	'(' shift, and go to state 34
		8481	'-' shift, and go to state 35
		8482
		8483	primary_expr go to state 41
		8484	mult_expr go to state 42
		8485	add_expr go to state 43
		8486	shift_expr go to state 44
		8487	relational_expr go to state 45
		8488	equality_expr go to state 46
		8489	and_expr go to state 47
		8490	exor_expr go to state 48
		8491	or_expr go to state 49
		8492	logand_expr go to state 50
		8493	logor_expr go to state 51
		8494	cond_expr go to state 52
		8495	expr go to state 663
		8496
		8497
		8498
		8499	state 655
		8500
		8501	vhdl_port_item -> vhdl_name_list ':' pin_dir vhdl_type vhdl_assign_opt . (rule 154)
		8502
		8503	$default reduce using rule 154 (vhdl_port_item)
		8504
		8505
		8506
		8507	state 656
		8508
		8509	vhdl_inst_generic_map -> GENERIC MAP @6 '(' . vhdl_gen_map_list ')' (rule 195)
		8510
		8511	QUOTED_STRING shift, and go to state 54
		8512	TXT_STRING shift, and go to state 55
		8513	NUM_STRING shift, and go to state 56
		8514
		8515	astring go to state 664
		8516	vhdl_gen_map_list go to state 665
		8517	vhdl_gen_map go to state 666
		8518
		8519
		8520
		8521	state 657
		8522
		8523	vhdl_inst_port_map -> PORT MAP '(' . vhdl_port_map_list ')' (rule 197)
		8524
		8525	OPEN shift, and go to state 667
		8526	GND shift, and go to state 131
		8527	VCC shift, and go to state 132
		8528	QUOTED_STRING shift, and go to state 54
		8529	TXT_STRING shift, and go to state 55
		8530	NUM_STRING shift, and go to state 56
		8531
		8532	astring go to state 668
		8533	vhdl_port_map_list go to state 669
		8534	vhdl_port_map go to state 670
		8535	rename_new_name go to state 671
		8536	netname go to state 137
		8537
		8538
		8539
		8540	state 658
		8541
		8542	vhdl_type -> astring '(' bus_range ')' vhdl_type_default_value_opt . (rule 73)
		8543
		8544	$default reduce using rule 73 (vhdl_type)
		8545
		8546
		8547
		8548	state 659
		8549
		8550	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring . '(' astring ')' ';' (rule 186)
		8551
		8552	'(' shift, and go to state 672
		8553
		8554
		8555
		8556	state 660
		8557
		8558	apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' astring . ':' (rule 67)
		8559
		8560	':' shift, and go to state 673
		8561
		8562
		8563
		8564	state 661
		8565
		8566	force_pin_dir -> PINDIR . (rule 360)
		8567
		8568	$default reduce using rule 360 (force_pin_dir)
		8569
		8570
		8571
		8572	state 662
		8573
		8574	net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir . node_group end_item (rule 359)
		8575
		8576	'(' shift, and go to state 674
		8577
		8578	$default reduce using rule 367 (node_group)
		8579
		8580	node_group go to state 675
		8581
		8582
		8583
		8584	state 663
		8585
		8586	vhdl_assign_opt -> ASSIGN expr . (rule 158)
		8587
		8588	$default reduce using rule 158 (vhdl_assign_opt)
		8589
		8590
		8591
		8592	state 664
		8593
		8594	vhdl_gen_map -> astring . CONNECTED bus_range (rule 201)
		8595
		8596	CONNECTED shift, and go to state 676
		8597
		8598
		8599
		8600	state 665
		8601
		8602	vhdl_inst_generic_map -> GENERIC MAP @6 '(' vhdl_gen_map_list . ')' (rule 195)
		8603	vhdl_gen_map_list -> vhdl_gen_map_list . ',' vhdl_gen_map (rule 199)
		8604
		8605	')' shift, and go to state 677
		8606	',' shift, and go to state 678
		8607
		8608
		8609
		8610	state 666
		8611
		8612	vhdl_gen_map_list -> vhdl_gen_map . (rule 200)
		8613
		8614	$default reduce using rule 200 (vhdl_gen_map_list)
		8615
		8616
		8617
		8618	state 667
		8619
		8620	vhdl_port_map -> OPEN . (rule 207)
		8621
		8622	$default reduce using rule 207 (vhdl_port_map)
		8623
		8624
		8625
		8626	state 668
		8627
		8628	vhdl_port_map -> astring . vhdl_port_map_slice_opt CONNECTED rename_new_name (rule 204)
		8629	vhdl_port_map -> astring . vhdl_port_map_slice_opt CONNECTED OPEN (rule 205)
		8630	netname -> astring . (rule 370)
		8631
		8632	'(' shift, and go to state 679
		8633
		8634	CONNECTED reduce using rule 209 (vhdl_port_map_slice_opt)
		8635	'(' [reduce using rule 370 (netname)]
		8636	$default reduce using rule 370 (netname)
		8637	vhdl_port_map_slice_opt go to state 680
		8638
		8639
		8640
		8641	state 669
		8642
		8643	vhdl_inst_port_map -> PORT MAP '(' vhdl_port_map_list . ')' (rule 197)
		8644	vhdl_port_map_list -> vhdl_port_map_list . ',' vhdl_port_map (rule 202)
		8645
		8646	')' shift, and go to state 681
		8647	',' shift, and go to state 682
		8648
		8649
		8650
		8651	state 670
		8652
		8653	vhdl_port_map_list -> vhdl_port_map . (rule 203)
		8654
		8655	$default reduce using rule 203 (vhdl_port_map_list)
		8656
		8657
		8658
		8659	state 671
		8660
		8661	vhdl_port_map -> rename_new_name . vhdl_port_map_slice_opt (rule 206)
		8662
		8663	'(' shift, and go to state 679
		8664
		8665	$default reduce using rule 209 (vhdl_port_map_slice_opt)
		8666
		8667	vhdl_port_map_slice_opt go to state 683
		8668
		8669
		8670
		8671	state 672
		8672
		8673	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' . astring ')' ';' (rule 186)
		8674
		8675	QUOTED_STRING shift, and go to state 54
		8676	TXT_STRING shift, and go to state 55
		8677	NUM_STRING shift, and go to state 56
		8678
		8679	astring go to state 684
		8680
		8681
		8682
		8683	state 673
		8684
		8685	apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' astring ':' . (rule 67)
		8686
		8687	$default reduce using rule 67 (apex_info_line)
		8688
		8689
		8690
		8691	state 674
		8692
		8693	node_group -> '(' . NUM_STRING ')' (rule 366)
		8694
		8695	NUM_STRING shift, and go to state 685
		8696
		8697
		8698
		8699	state 675
		8700
		8701	net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir node_group . end_item (rule 359)
		8702
		8703	';' shift, and go to state 240
		8704
		8705	end_item go to state 686
		8706
		8707
		8708
		8709	state 676
		8710
		8711	vhdl_gen_map -> astring CONNECTED . bus_range (rule 201)
		8712
		8713	TRUE shift, and go to state 27
		8714	FALSE shift, and go to state 28
		8715	QUOTE shift, and go to state 29
		8716	QUOTED_STRING shift, and go to state 30
		8717	TXT_STRING shift, and go to state 31
		8718	NUM_STRING shift, and go to state 32
		8719	'~' shift, and go to state 33
		8720	'(' shift, and go to state 34
		8721	'-' shift, and go to state 35
		8722
		8723	bus_range go to state 687
		8724	expr1 go to state 39
		8725	simple_range_expr go to state 40
		8726	primary_expr go to state 41
		8727	mult_expr go to state 42
		8728	add_expr go to state 43
		8729	shift_expr go to state 44
		8730	relational_expr go to state 45
		8731	equality_expr go to state 46
		8732	and_expr go to state 47
		8733	exor_expr go to state 48
		8734	or_expr go to state 49
		8735	logand_expr go to state 50
		8736	logor_expr go to state 51
		8737	cond_expr go to state 52
		8738	expr go to state 53
		8739
		8740
		8741
		8742	state 677
		8743
		8744	vhdl_inst_generic_map -> GENERIC MAP @6 '(' vhdl_gen_map_list ')' . (rule 195)
		8745
		8746	$default reduce using rule 195 (vhdl_inst_generic_map)
		8747
		8748
		8749
		8750	state 678
		8751
		8752	vhdl_gen_map_list -> vhdl_gen_map_list ',' . vhdl_gen_map (rule 199)
		8753
		8754	QUOTED_STRING shift, and go to state 54
		8755	TXT_STRING shift, and go to state 55
		8756	NUM_STRING shift, and go to state 56
		8757
		8758	astring go to state 664
		8759	vhdl_gen_map go to state 688
		8760
		8761
		8762
		8763	state 679
		8764
		8765	vhdl_port_map_slice_opt -> '(' . bus_range ')' (rule 208)
		8766
		8767	TRUE shift, and go to state 27
		8768	FALSE shift, and go to state 28
		8769	QUOTE shift, and go to state 29
		8770	QUOTED_STRING shift, and go to state 30
		8771	TXT_STRING shift, and go to state 31
		8772	NUM_STRING shift, and go to state 32
		8773	'~' shift, and go to state 33
		8774	'(' shift, and go to state 34
		8775	'-' shift, and go to state 35
		8776
		8777	bus_range go to state 689
		8778	expr1 go to state 39
		8779	simple_range_expr go to state 40
		8780	primary_expr go to state 41
		8781	mult_expr go to state 42
		8782	add_expr go to state 43
		8783	shift_expr go to state 44
		8784	relational_expr go to state 45
		8785	equality_expr go to state 46
		8786	and_expr go to state 47
		8787	exor_expr go to state 48
		8788	or_expr go to state 49
		8789	logand_expr go to state 50
		8790	logor_expr go to state 51
		8791	cond_expr go to state 52
		8792	expr go to state 53
		8793
		8794
		8795
		8796	state 680
		8797
		8798	vhdl_port_map -> astring vhdl_port_map_slice_opt . CONNECTED rename_new_name (rule 204)
		8799	vhdl_port_map -> astring vhdl_port_map_slice_opt . CONNECTED OPEN (rule 205)
		8800
		8801	CONNECTED shift, and go to state 690
		8802
		8803
		8804
		8805	state 681
		8806
		8807	vhdl_inst_port_map -> PORT MAP '(' vhdl_port_map_list ')' . (rule 197)
		8808
		8809	$default reduce using rule 197 (vhdl_inst_port_map)
		8810
		8811
		8812
		8813	state 682
		8814
		8815	vhdl_port_map_list -> vhdl_port_map_list ',' . vhdl_port_map (rule 202)
		8816
		8817	OPEN shift, and go to state 667
		8818	GND shift, and go to state 131
		8819	VCC shift, and go to state 132
		8820	QUOTED_STRING shift, and go to state 54
		8821	TXT_STRING shift, and go to state 55
		8822	NUM_STRING shift, and go to state 56
		8823
		8824	astring go to state 668
		8825	vhdl_port_map go to state 691
		8826	rename_new_name go to state 671
		8827	netname go to state 137
		8828
		8829
		8830
		8831	state 683
		8832
		8833	vhdl_port_map -> rename_new_name vhdl_port_map_slice_opt . (rule 206)
		8834
		8835	$default reduce using rule 206 (vhdl_port_map)
		8836
		8837
		8838
		8839	state 684
		8840
		8841	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring . ')' ';' (rule 186)
		8842
		8843	')' shift, and go to state 692
		8844
		8845
		8846
		8847	state 685
		8848
		8849	node_group -> '(' NUM_STRING . ')' (rule 366)
		8850
		8851	')' shift, and go to state 693
		8852
		8853
		8854
		8855	state 686
		8856
		8857	net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir node_group end_item . (rule 359)
		8858
		8859	$default reduce using rule 359 (net_node)
		8860
		8861
		8862
		8863	state 687
		8864
		8865	vhdl_gen_map -> astring CONNECTED bus_range . (rule 201)
		8866
		8867	$default reduce using rule 201 (vhdl_gen_map)
		8868
		8869
		8870
		8871	state 688
		8872
		8873	vhdl_gen_map_list -> vhdl_gen_map_list ',' vhdl_gen_map . (rule 199)
		8874
		8875	$default reduce using rule 199 (vhdl_gen_map_list)
		8876
		8877
		8878
		8879	state 689
		8880
		8881	vhdl_port_map_slice_opt -> '(' bus_range . ')' (rule 208)
		8882
		8883	')' shift, and go to state 694
		8884
		8885
		8886
		8887	state 690
		8888
		8889	vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED . rename_new_name (rule 204)
		8890	vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED . OPEN (rule 205)
		8891
		8892	OPEN shift, and go to state 695
		8893	GND shift, and go to state 131
		8894	VCC shift, and go to state 132
		8895	QUOTED_STRING shift, and go to state 54
		8896	TXT_STRING shift, and go to state 55
		8897	NUM_STRING shift, and go to state 56
		8898
		8899	astring go to state 133
		8900	rename_new_name go to state 696
		8901	netname go to state 137
		8902
		8903
		8904
		8905	state 691
		8906
		8907	vhdl_port_map_list -> vhdl_port_map_list ',' vhdl_port_map . (rule 202)
		8908
		8909	$default reduce using rule 202 (vhdl_port_map_list)
		8910
		8911
		8912
		8913	state 692
		8914
		8915	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' . ';' (rule 186)
		8916
		8917	';' shift, and go to state 697
		8918
		8919
		8920
		8921	state 693
		8922
		8923	node_group -> '(' NUM_STRING ')' . (rule 366)
		8924
		8925	$default reduce using rule 366 (node_group)
		8926
		8927
		8928
		8929	state 694
		8930
		8931	vhdl_port_map_slice_opt -> '(' bus_range ')' . (rule 208)
		8932
		8933	$default reduce using rule 208 (vhdl_port_map_slice_opt)
		8934
		8935
		8936
		8937	state 695
		8938
		8939	vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED OPEN . (rule 205)
		8940
		8941	$default reduce using rule 205 (vhdl_port_map)
		8942
		8943
		8944
		8945	state 696
		8946
		8947	vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED rename_new_name . (rule 204)
		8948
		8949	$default reduce using rule 204 (vhdl_port_map)
		8950
		8951
		8952
		8953	state 697
		8954
		8955	vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' ';' . (rule 186)
		8956
		8957	$default reduce using rule 186 (vhdl_configuration_decl)
		8958
		8959
		8960
		8961	state 698
		8962
		8963	$ go to state 699
		8964
		8965
		8966
		8967	state 699
		8968
		8969	$ go to state 700
		8970
		8971
		8972
		8973	state 700
		8974
		8975	$default accept
		8976
		8977

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