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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3 | mjames | 1 | /* |
| 2 | * misc.c |
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| 3 | * |
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| 4 | * Created on: 21 Sep 2016 |
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| 5 | * Author: Mike |
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| 6 | */ |
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| 7 | |||
| 8 | |||
| 9 | void _init(void) |
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| 10 | { |
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| 11 | |||
| 12 | } |
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| 6 | mjames | 13 | |
| 14 | |||
| 15 | |||
| 16 | #if OLD_ENGINEBAY |
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| 17 | //----------------------------------------------------------- |
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| 18 | // This is the 10Hz timer |
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| 19 | |||
| 20 | void interrupt TimerISR1(void) { |
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| 21 | TimerFlag = 1; |
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| 22 | if (NoSerialInCTR < 5) { |
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| 23 | NoSerialInCTR++; |
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| 24 | if (NoSerialInCTR == 5) { |
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| 25 | NoSerialIn = 1; |
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| 26 | } |
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| 27 | } |
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| 28 | } |
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| 29 | //----------------------------------------------------------- |
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| 30 | |||
| 31 | |||
| 32 | volatile unsigned long RPM_Time[RPM_LIMIT]; |
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| 33 | volatile unsigned long RPM_Count; // incremented every reading |
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| 34 | |||
| 35 | void TimerISR0(void) { |
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| 36 | // check the listing |
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| 37 | asm volatile ("STMDB SP!, {r0-r4} "); |
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| 38 | // sort out the captures |
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| 39 | int stat = REG(TIMER0_IR); |
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| 40 | if (stat & (1 << 4)) //CR0 |
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| 41 | { |
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| 42 | RPM_Time[RPM_Count++] = REG(TIMER0_CR0); |
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| 43 | if (RPM_Count == RPM_LIMIT) { |
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| 44 | RPM_Count = 0; |
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| 45 | } |
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| 46 | } |
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| 47 | if (stat & (1 << 5)) //CR1 |
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| 48 | { |
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| 49 | // TDC_Time = REG(TIMER0_CR1); |
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| 50 | // TDC_Count++; |
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| 51 | } |
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| 52 | |||
| 53 | REG(TIMER0_IR) = stat; // clear the interrupts just handled. |
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| 54 | REG(VICVectAddr) = 0; // reset the VIC |
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| 55 | asm volatile ("LDMIA SP!, {r0-r4} "); |
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| 56 | asm volatile ("SUBS PC,lr,#4"); |
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| 57 | } |
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| 58 | |||
| 59 | //----------------------------------------------------------- |
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| 60 | // UART management |
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| 61 | // serial counter |
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| 62 | #define THRE (1<<6) |
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| 63 | #define RDR (1<<0) |
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| 64 | #define BUFFSIZ 256 |
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| 65 | |||
| 66 | volatile char txbuff[BUFFSIZ]; |
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| 67 | volatile int txptr = 0; |
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| 68 | volatile int txcnt = 0; |
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| 69 | |||
| 70 | volatile char rxbuff[BUFFSIZ]; |
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| 71 | volatile int rxptr = 0; |
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| 72 | volatile int rxcnt = 0; |
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| 73 | |||
| 74 | void Uart0ISR(void) __attribute__((naked)); |
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| 75 | void Uart0ISR(void) __attribute__((noinline)); |
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| 76 | void Uart0ISR(void) { |
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| 77 | asm volatile ("STMDB SP!, {r0-r3} "); |
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| 78 | int stat; |
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| 79 | while (!((stat = REG(UART0_IIR)) & 1)) { // LSbit is inactive |
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| 80 | switch (stat & 0x0E) { |
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| 81 | case 4: |
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| 82 | case 12: { |
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| 83 | char c = REG(UART0_RBR); |
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| 84 | |||
| 85 | NoSerialIn = NoSerialInCTR = 0; |
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| 86 | |||
| 87 | if (rxcnt < (BUFFSIZ - 1)) { |
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| 88 | rxbuff[(rxptr + rxcnt) % BUFFSIZ] = c; |
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| 89 | rxcnt++; |
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| 90 | } |
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| 91 | } |
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| 92 | break; |
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| 93 | case 2: { |
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| 94 | if (txcnt > 0) { |
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| 95 | REG(UART0_THR) = txbuff[txptr]; |
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| 96 | txcnt--; |
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| 97 | txptr++; |
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| 98 | txptr %= BUFFSIZ; |
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| 99 | } else { |
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| 100 | REG(UART0_IER) &= ~(1 << 1); // disable TX |
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| 101 | } |
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| 102 | } |
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| 103 | break; |
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| 104 | } |
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| 105 | } |
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| 106 | REG(VICVectAddr) = 0; // reset the VIC |
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| 107 | asm volatile ("LDMIA SP!, {r0-r3} "); |
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| 108 | asm volatile ("SUBS PC,lr,#4"); |
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| 109 | } |
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| 110 | |||
| 111 | int my_putchar(int c) { |
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| 112 | int rc = 0; |
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| 113 | { |
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| 114 | STI; |
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| 115 | if (!(REG(UART0_IER) & (1 << 1))) { |
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| 116 | REG(UART0_IER) |= (1 << 1); |
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| 117 | REG(UART0_THR) = c; |
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| 118 | rc=1; |
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| 119 | } else { |
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| 120 | |||
| 121 | if (txcnt < (BUFFSIZ - 1)) { |
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| 122 | txbuff[(txptr + txcnt) % BUFFSIZ] = c; |
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| 123 | txcnt++; |
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| 124 | rc = 1; |
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| 125 | } |
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| 126 | } |
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| 127 | CLI; |
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| 128 | } |
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| 129 | return rc; |
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| 130 | } |
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| 131 | |||
| 132 | int my_getchar(void) { |
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| 133 | |||
| 134 | int c = -1; |
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| 135 | STI; |
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| 136 | if (rxcnt) { |
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| 137 | c = rxbuff[rxptr]; |
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| 138 | rxcnt--; |
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| 139 | rxptr++; |
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| 140 | rxptr %= BUFFSIZ; |
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| 141 | } |
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| 142 | CLI; |
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| 143 | return c; |
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| 144 | } |
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| 145 | |||
| 146 | |||
| 147 | |||
| 148 | #endif |