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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_dma.c |
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4 | * @author MCD Application Team |
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5 | * @version V1.2.0 |
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6 | * @date 01-July-2016 |
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7 | * @brief DMA HAL module driver. |
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8 | * This file provides firmware functions to manage the following |
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9 | * functionalities of the Direct Memory Access (DMA) peripheral: |
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10 | * + Initialization and de-initialization functions |
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11 | * + IO operation functions |
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12 | * + Peripheral State and errors functions |
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13 | @verbatim |
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14 | ============================================================================== |
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15 | ##### How to use this driver ##### |
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16 | ============================================================================== |
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17 | [..] |
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18 | (#) Enable and configure the peripheral to be connected to the DMA Channel |
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19 | (except for internal SRAM / FLASH memories: no initialization is |
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20 | necessary). Please refer to the Reference manual for connection between peripherals |
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21 | and DMA requests. |
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22 | |||
23 | (#) For a given Channel, program the required configuration through the following parameters: |
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24 | Channel request, Transfer Direction, Source and Destination data formats, |
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25 | Circular or Normal mode, Channel Priority level, Source and Destination Increment mode |
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26 | using HAL_DMA_Init() function. |
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27 | |||
28 | (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error |
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29 | detection. |
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30 | |||
31 | (#) Use HAL_DMA_Abort() function to abort the current transfer |
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32 | |||
33 | -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
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34 | *** Polling mode IO operation *** |
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35 | ================================= |
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36 | [..] |
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37 | (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
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38 | address and destination address and the Length of data to be transferred |
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39 | (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
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40 | case a fixed Timeout can be configured by User depending from his application. |
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41 | |||
42 | *** Interrupt mode IO operation *** |
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43 | =================================== |
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44 | [..] |
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45 | (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
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46 | (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
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47 | (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
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48 | Source address and destination address and the Length of data to be transferred. |
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49 | In this case the DMA interrupt is configured |
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50 | (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
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51 | (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
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52 | add his own function by customization of function pointer XferCpltCallback and |
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53 | XferErrorCallback (i.e. a member of DMA handle structure). |
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54 | |||
55 | *** DMA HAL driver macros list *** |
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56 | ============================================= |
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57 | [..] |
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58 | Below the list of most used macros in DMA HAL driver. |
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59 | |||
60 | (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. |
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61 | (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. |
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62 | (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. |
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63 | (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. |
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64 | (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. |
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65 | (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. |
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66 | (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. |
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67 | |||
68 | [..] |
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69 | (@) You can refer to the DMA HAL driver header file for more useful macros |
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70 | |||
71 | @endverbatim |
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72 | ****************************************************************************** |
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73 | * @attention |
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74 | * |
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75 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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76 | * |
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77 | * Redistribution and use in source and binary forms, with or without modification, |
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78 | * are permitted provided that the following conditions are met: |
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79 | * 1. Redistributions of source code must retain the above copyright notice, |
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80 | * this list of conditions and the following disclaimer. |
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81 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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82 | * this list of conditions and the following disclaimer in the documentation |
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83 | * and/or other materials provided with the distribution. |
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84 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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85 | * may be used to endorse or promote products derived from this software |
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86 | * without specific prior written permission. |
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87 | * |
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88 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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89 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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90 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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91 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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92 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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93 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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94 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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95 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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96 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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97 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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98 | * |
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99 | ****************************************************************************** |
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100 | */ |
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101 | |||
102 | /* Includes ------------------------------------------------------------------*/ |
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103 | #include "stm32l1xx_hal.h" |
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104 | |||
105 | /** @addtogroup STM32L1xx_HAL_Driver |
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106 | * @{ |
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107 | */ |
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108 | |||
109 | /** @defgroup DMA DMA |
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110 | * @brief DMA HAL module driver |
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111 | * @{ |
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112 | */ |
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113 | |||
114 | #ifdef HAL_DMA_MODULE_ENABLED |
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115 | |||
116 | /* Private typedef -----------------------------------------------------------*/ |
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117 | /* Private define ------------------------------------------------------------*/ |
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118 | /* Private macro -------------------------------------------------------------*/ |
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119 | /* Private variables ---------------------------------------------------------*/ |
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120 | /* Private function prototypes -----------------------------------------------*/ |
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121 | /** @defgroup DMA_Private_Functions DMA Private Functions |
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122 | * @{ |
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123 | */ |
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124 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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125 | |||
126 | /** |
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127 | * @} |
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128 | */ |
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129 | |||
130 | /* Exported functions ---------------------------------------------------------*/ |
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131 | |||
132 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
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133 | * @{ |
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134 | */ |
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135 | |||
136 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
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137 | * @brief Initialization and de-initialization functions |
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138 | * |
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139 | @verbatim |
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140 | =============================================================================== |
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141 | ##### Initialization and de-initialization functions ##### |
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142 | =============================================================================== |
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143 | [..] |
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144 | This section provides functions allowing to initialize the DMA Channel source |
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145 | and destination addresses, incrementation and data sizes, transfer direction, |
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146 | circular/normal mode selection, memory-to-memory mode selection and Channel priority value. |
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147 | [..] |
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148 | The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
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149 | reference manual. |
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150 | |||
151 | @endverbatim |
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152 | * @{ |
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153 | */ |
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154 | |||
155 | /** |
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156 | * @brief Initialize the DMA according to the specified |
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157 | * parameters in the DMA_InitTypeDef and initialize the associated handle. |
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158 | * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
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159 | * the configuration information for the specified DMA Channel. |
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160 | * @retval HAL status |
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161 | */ |
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162 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
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163 | { |
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164 | uint32_t tmp = 0; |
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165 | |||
166 | /* Check the DMA handle allocation */ |
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167 | if(hdma == NULL) |
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168 | { |
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169 | return HAL_ERROR; |
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170 | } |
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171 | |||
172 | /* Check the parameters */ |
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173 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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174 | assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
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175 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
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176 | assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
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177 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
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178 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
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179 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
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180 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
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181 | |||
182 | #if defined (DMA2) |
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183 | /* calculation of the channel index */ |
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184 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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185 | { |
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186 | /* DMA1 */ |
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187 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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188 | hdma->DmaBaseAddress = DMA1; |
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189 | } |
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190 | else |
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191 | { |
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192 | /* DMA2 */ |
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193 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
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194 | hdma->DmaBaseAddress = DMA2; |
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195 | } |
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196 | #else |
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197 | /* calculation of the channel index */ |
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198 | /* DMA1 */ |
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199 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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200 | hdma->DmaBaseAddress = DMA1; |
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201 | #endif |
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202 | |||
203 | /* Change DMA peripheral state */ |
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204 | hdma->State = HAL_DMA_STATE_BUSY; |
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205 | |||
206 | /* Get the CR register value */ |
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207 | tmp = hdma->Instance->CCR; |
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208 | |||
209 | /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ |
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210 | tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ |
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211 | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ |
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212 | DMA_CCR_DIR)); |
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213 | |||
214 | /* Prepare the DMA Channel configuration */ |
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215 | tmp |= hdma->Init.Direction | |
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216 | hdma->Init.PeriphInc | hdma->Init.MemInc | |
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217 | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
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218 | hdma->Init.Mode | hdma->Init.Priority; |
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219 | |||
220 | /* Write to DMA Channel CR register */ |
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221 | hdma->Instance->CCR = tmp; |
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222 | |||
223 | /* Clean callbacks */ |
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224 | hdma->XferCpltCallback = NULL; |
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225 | hdma->XferHalfCpltCallback = NULL; |
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226 | hdma->XferErrorCallback = NULL; |
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227 | hdma->XferAbortCallback = NULL; |
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228 | |||
229 | /* Initialise the error code */ |
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230 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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231 | |||
232 | /* Initialize the DMA state*/ |
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233 | hdma->State = HAL_DMA_STATE_READY; |
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234 | |||
235 | /* Allocate lock resource and initialize it */ |
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236 | hdma->Lock = HAL_UNLOCKED; |
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237 | |||
238 | return HAL_OK; |
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239 | } |
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240 | |||
241 | /** |
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242 | * @brief DeInitialize the DMA peripheral. |
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243 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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244 | * the configuration information for the specified DMA Channel. |
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245 | * @retval HAL status |
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246 | */ |
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247 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
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248 | { |
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249 | /* Check the DMA handle allocation */ |
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250 | if (NULL == hdma ) |
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251 | { |
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252 | return HAL_ERROR; |
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253 | } |
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254 | |||
255 | /* Check the parameters */ |
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256 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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257 | |||
258 | /* Disable the selected DMA Channelx */ |
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259 | __HAL_DMA_DISABLE(hdma); |
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260 | |||
261 | #if defined (DMA2) |
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262 | /* calculation of the channel index */ |
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263 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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264 | { |
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265 | /* DMA1 */ |
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266 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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267 | hdma->DmaBaseAddress = DMA1; |
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268 | } |
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269 | else |
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270 | { |
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271 | /* DMA2 */ |
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272 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
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273 | hdma->DmaBaseAddress = DMA2; |
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274 | } |
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275 | #else |
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276 | /* calculation of the channel index */ |
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277 | /* DMA1 */ |
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278 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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279 | hdma->DmaBaseAddress = DMA1; |
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280 | #endif |
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281 | |||
282 | /* Reset DMA Channel control register */ |
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283 | hdma->Instance->CCR = 0; |
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284 | |||
285 | /* Reset DMA Channel Number of Data to Transfer register */ |
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286 | hdma->Instance->CNDTR = 0; |
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287 | |||
288 | /* Reset DMA Channel peripheral address register */ |
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289 | hdma->Instance->CPAR = 0; |
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290 | |||
291 | /* Reset DMA Channel memory address register */ |
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292 | hdma->Instance->CMAR = 0; |
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293 | |||
294 | /* Clear all flags */ |
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295 | hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); |
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296 | |||
297 | /* Initialise the error code */ |
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298 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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299 | |||
300 | /* Initialize the DMA state */ |
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301 | hdma->State = HAL_DMA_STATE_RESET; |
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302 | |||
303 | /* Release Lock */ |
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304 | __HAL_UNLOCK(hdma); |
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305 | |||
306 | return HAL_OK; |
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307 | } |
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308 | |||
309 | /** |
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310 | * @} |
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311 | */ |
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312 | |||
313 | /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions |
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314 | * @brief Input and Output operation functions |
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315 | * |
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316 | @verbatim |
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317 | =============================================================================== |
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318 | ##### IO operation functions ##### |
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319 | =============================================================================== |
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320 | [..] This section provides functions allowing to: |
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321 | (+) Configure the source, destination address and data length and Start DMA transfer |
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322 | (+) Configure the source, destination address and data length and |
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323 | Start DMA transfer with interrupt |
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324 | (+) Abort DMA transfer |
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325 | (+) Poll for transfer complete |
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326 | (+) Handle DMA interrupt request |
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327 | |||
328 | @endverbatim |
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329 | * @{ |
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330 | */ |
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331 | |||
332 | /** |
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333 | * @brief Start the DMA Transfer. |
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334 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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335 | * the configuration information for the specified DMA Channel. |
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336 | * @param SrcAddress: The source memory Buffer address |
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337 | * @param DstAddress: The destination memory Buffer address |
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338 | * @param DataLength: The length of data to be transferred from source to destination |
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339 | * @retval HAL status |
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340 | */ |
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341 | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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342 | { |
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343 | HAL_StatusTypeDef status = HAL_OK; |
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344 | |||
345 | /* Check the parameters */ |
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346 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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347 | |||
348 | /* Process locked */ |
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349 | __HAL_LOCK(hdma); |
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350 | |||
351 | if(HAL_DMA_STATE_READY == hdma->State) |
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352 | { |
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353 | /* Change DMA peripheral state */ |
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354 | hdma->State = HAL_DMA_STATE_BUSY; |
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355 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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356 | |||
357 | /* Disable the peripheral */ |
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358 | __HAL_DMA_DISABLE(hdma); |
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359 | |||
360 | /* Configure the source, destination address and the data length & clear flags*/ |
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361 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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362 | |||
363 | /* Enable the Peripheral */ |
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364 | __HAL_DMA_ENABLE(hdma); |
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365 | } |
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366 | else |
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367 | { |
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368 | /* Process Unlocked */ |
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369 | __HAL_UNLOCK(hdma); |
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370 | status = HAL_BUSY; |
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371 | } |
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372 | return status; |
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373 | } |
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374 | |||
375 | /** |
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376 | * @brief Start the DMA Transfer with interrupt enabled. |
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377 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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378 | * the configuration information for the specified DMA Channel. |
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379 | * @param SrcAddress: The source memory Buffer address |
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380 | * @param DstAddress: The destination memory Buffer address |
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381 | * @param DataLength: The length of data to be transferred from source to destination |
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382 | * @retval HAL status |
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383 | */ |
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384 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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385 | { |
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386 | HAL_StatusTypeDef status = HAL_OK; |
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387 | |||
388 | /* Check the parameters */ |
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389 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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390 | |||
391 | /* Process locked */ |
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392 | __HAL_LOCK(hdma); |
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393 | |||
394 | if(HAL_DMA_STATE_READY == hdma->State) |
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395 | { |
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396 | /* Change DMA peripheral state */ |
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397 | hdma->State = HAL_DMA_STATE_BUSY; |
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398 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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399 | |||
400 | /* Disable the peripheral */ |
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401 | __HAL_DMA_DISABLE(hdma); |
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402 | |||
403 | /* Configure the source, destination address and the data length & clear flags*/ |
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404 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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405 | |||
406 | /* Enable the transfer complete interrupt */ |
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407 | /* Enable the transfer Error interrupt */ |
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408 | if(NULL != hdma->XferHalfCpltCallback ) |
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409 | { |
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410 | /* Enable the Half transfer complete interrupt as well */ |
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411 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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412 | } |
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413 | else |
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414 | { |
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415 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
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416 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); |
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417 | } |
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418 | /* Enable the Peripheral */ |
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419 | __HAL_DMA_ENABLE(hdma); |
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420 | } |
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421 | else |
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422 | { |
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423 | /* Process Unlocked */ |
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424 | __HAL_UNLOCK(hdma); |
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425 | |||
426 | /* Remain BUSY */ |
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427 | status = HAL_BUSY; |
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428 | } |
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429 | return status; |
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430 | } |
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431 | |||
432 | /** |
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433 | * @brief Abort the DMA Transfer. |
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434 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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435 | * the configuration information for the specified DMA Channel. |
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436 | * @retval HAL status |
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437 | */ |
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438 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
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439 | { |
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440 | HAL_StatusTypeDef status = HAL_OK; |
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441 | |||
442 | /* Disable DMA IT */ |
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443 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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444 | |||
445 | /* Disable the channel */ |
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446 | __HAL_DMA_DISABLE(hdma); |
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447 | |||
448 | /* Clear all flags */ |
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449 | hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); |
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450 | |||
451 | /* Change the DMA state */ |
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452 | hdma->State = HAL_DMA_STATE_READY; |
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453 | |||
454 | /* Process Unlocked */ |
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455 | __HAL_UNLOCK(hdma); |
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456 | |||
457 | return status; |
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458 | } |
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459 | |||
460 | /** |
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461 | * @brief Aborts the DMA Transfer in Interrupt mode. |
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462 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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463 | * the configuration information for the specified DMA Stream. |
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464 | * @retval HAL status |
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465 | */ |
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466 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
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467 | { |
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468 | HAL_StatusTypeDef status = HAL_OK; |
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469 | |||
470 | if(HAL_DMA_STATE_BUSY != hdma->State) |
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471 | { |
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472 | /* no transfer ongoing */ |
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473 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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474 | |||
475 | status = HAL_ERROR; |
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476 | } |
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477 | else |
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478 | { |
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479 | /* Disable DMA IT */ |
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480 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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481 | |||
482 | /* Disable the channel */ |
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483 | __HAL_DMA_DISABLE(hdma); |
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484 | |||
485 | /* Clear all flags */ |
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486 | hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); |
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487 | |||
488 | /* Change the DMA state */ |
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489 | hdma->State = HAL_DMA_STATE_READY; |
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490 | |||
491 | /* Process Unlocked */ |
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492 | __HAL_UNLOCK(hdma); |
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493 | |||
494 | /* Call User Abort callback */ |
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495 | if(hdma->XferAbortCallback != NULL) |
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496 | { |
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497 | hdma->XferAbortCallback(hdma); |
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498 | } |
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499 | } |
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500 | return status; |
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501 | } |
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502 | |||
503 | /** |
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504 | * @brief Polling for transfer complete. |
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505 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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506 | * the configuration information for the specified DMA Channel. |
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507 | * @param CompleteLevel: Specifies the DMA level complete. |
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508 | * @param Timeout: Timeout duration. |
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509 | * @retval HAL status |
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510 | */ |
||
511 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
||
512 | { |
||
513 | uint32_t temp; |
||
514 | uint32_t tickstart = 0; |
||
515 | |||
516 | if(HAL_DMA_STATE_BUSY != hdma->State) |
||
517 | { |
||
518 | /* no transfer ongoing */ |
||
519 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
||
520 | __HAL_UNLOCK(hdma); |
||
521 | return HAL_ERROR; |
||
522 | } |
||
523 | |||
524 | /* Polling mode not supported in circular mode */ |
||
525 | if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) |
||
526 | { |
||
527 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; |
||
528 | return HAL_ERROR; |
||
529 | } |
||
530 | |||
531 | /* Get the level transfer complete flag */ |
||
532 | if (HAL_DMA_FULL_TRANSFER == CompleteLevel) |
||
533 | { |
||
534 | /* Transfer Complete flag */ |
||
535 | temp = DMA_FLAG_TC1 << hdma->ChannelIndex; |
||
536 | } |
||
537 | else |
||
538 | { |
||
539 | /* Half Transfer Complete flag */ |
||
540 | temp = DMA_FLAG_HT1 << hdma->ChannelIndex; |
||
541 | } |
||
542 | |||
543 | /* Get tick */ |
||
544 | tickstart = HAL_GetTick(); |
||
545 | |||
546 | while(RESET == (hdma->DmaBaseAddress->ISR & temp)) |
||
547 | { |
||
548 | if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) |
||
549 | { |
||
550 | /* When a DMA transfer error occurs */ |
||
551 | /* A hardware clear of its EN bits is performed */ |
||
552 | /* Clear all flags */ |
||
553 | hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); |
||
554 | |||
555 | /* Update error code */ |
||
556 | hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||
557 | |||
558 | /* Change the DMA state */ |
||
559 | hdma->State= HAL_DMA_STATE_READY; |
||
560 | |||
561 | /* Process Unlocked */ |
||
562 | __HAL_UNLOCK(hdma); |
||
563 | |||
564 | return HAL_ERROR; |
||
565 | } |
||
566 | /* Check for the Timeout */ |
||
567 | if(Timeout != HAL_MAX_DELAY) |
||
568 | { |
||
569 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
||
570 | { |
||
571 | /* Update error code */ |
||
572 | hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; |
||
573 | |||
574 | /* Change the DMA state */ |
||
575 | hdma->State = HAL_DMA_STATE_READY; |
||
576 | |||
577 | /* Process Unlocked */ |
||
578 | __HAL_UNLOCK(hdma); |
||
579 | |||
580 | return HAL_ERROR; |
||
581 | } |
||
582 | } |
||
583 | } |
||
584 | |||
585 | if(HAL_DMA_FULL_TRANSFER == CompleteLevel) |
||
586 | { |
||
587 | /* Clear the transfer complete flag */ |
||
588 | hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); |
||
589 | |||
590 | /* The selected Channelx EN bit is cleared (DMA is disabled and |
||
591 | all transfers are complete) */ |
||
592 | hdma->State = HAL_DMA_STATE_READY; |
||
593 | } |
||
594 | else |
||
595 | { |
||
596 | /* Clear the half transfer complete flag */ |
||
597 | hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); |
||
598 | } |
||
599 | |||
600 | /* Process unlocked */ |
||
601 | __HAL_UNLOCK(hdma); |
||
602 | |||
603 | return HAL_OK; |
||
604 | } |
||
605 | |||
606 | /** |
||
607 | * @brief Handle DMA interrupt request. |
||
608 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
609 | * the configuration information for the specified DMA Channel. |
||
610 | * @retval None |
||
611 | */ |
||
612 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
||
613 | { |
||
614 | uint32_t flag_it = hdma->DmaBaseAddress->ISR; |
||
615 | uint32_t source_it = hdma->Instance->CCR; |
||
616 | |||
617 | /* Half Transfer Complete Interrupt management ******************************/ |
||
618 | if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) |
||
619 | { |
||
620 | /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
||
621 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) |
||
622 | { |
||
623 | /* Disable the half transfer interrupt */ |
||
624 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||
625 | } |
||
626 | /* Clear the half transfer complete flag */ |
||
627 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); |
||
628 | |||
629 | /* DMA peripheral state is not updated in Half Transfer */ |
||
630 | /* but in Transfer Complete case */ |
||
631 | |||
632 | if(hdma->XferHalfCpltCallback != NULL) |
||
633 | { |
||
634 | /* Half transfer callback */ |
||
635 | hdma->XferHalfCpltCallback(hdma); |
||
636 | } |
||
637 | } |
||
638 | |||
639 | /* Transfer Complete Interrupt management ***********************************/ |
||
640 | else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) |
||
641 | { |
||
642 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) |
||
643 | { |
||
644 | /* Disable TE & TC */ |
||
645 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); |
||
646 | |||
647 | /* Change the DMA state */ |
||
648 | hdma->State = HAL_DMA_STATE_READY; |
||
649 | } |
||
650 | |||
651 | /* Clear the transfer complete flag */ |
||
652 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); |
||
653 | |||
654 | /* Process Unlocked */ |
||
655 | __HAL_UNLOCK(hdma); |
||
656 | |||
657 | if(hdma->XferCpltCallback != NULL) |
||
658 | { |
||
659 | /* Transfer complete callback */ |
||
660 | hdma->XferCpltCallback(hdma); |
||
661 | } |
||
662 | } |
||
663 | |||
664 | /* Transfer Error Interrupt management **************************************/ |
||
665 | else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) |
||
666 | { |
||
667 | /* When a DMA transfer error occurs */ |
||
668 | /* A hardware clear of its EN bits is performed */ |
||
669 | /* Disable ALL DMA IT */ |
||
670 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||
671 | |||
672 | /* Clear all flags */ |
||
673 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
674 | |||
675 | /* Update error code */ |
||
676 | hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||
677 | |||
678 | /* Change the DMA state */ |
||
679 | hdma->State = HAL_DMA_STATE_READY; |
||
680 | |||
681 | /* Process Unlocked */ |
||
682 | __HAL_UNLOCK(hdma); |
||
683 | |||
684 | if (hdma->XferErrorCallback != NULL) |
||
685 | { |
||
686 | /* Transfer error callback */ |
||
687 | hdma->XferErrorCallback(hdma); |
||
688 | } |
||
689 | } |
||
690 | return; |
||
691 | } |
||
692 | |||
693 | /** |
||
694 | * @brief Register callbacks |
||
695 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
696 | * the configuration information for the specified DMA Stream. |
||
697 | * @param CallbackID: User Callback identifer |
||
698 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
699 | * @param pCallback: pointer to private callbacsk function which has pointer to |
||
700 | * a DMA_HandleTypeDef structure as parameter. |
||
701 | * @retval HAL status |
||
702 | */ |
||
703 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) |
||
704 | { |
||
705 | HAL_StatusTypeDef status = HAL_OK; |
||
706 | |||
707 | /* Process locked */ |
||
708 | __HAL_LOCK(hdma); |
||
709 | |||
710 | if(HAL_DMA_STATE_READY == hdma->State) |
||
711 | { |
||
712 | switch (CallbackID) |
||
713 | { |
||
714 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
715 | hdma->XferCpltCallback = pCallback; |
||
716 | break; |
||
717 | |||
718 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
719 | hdma->XferHalfCpltCallback = pCallback; |
||
720 | break; |
||
721 | |||
722 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
723 | hdma->XferErrorCallback = pCallback; |
||
724 | break; |
||
725 | |||
726 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
727 | hdma->XferAbortCallback = pCallback; |
||
728 | break; |
||
729 | |||
730 | default: |
||
731 | status = HAL_ERROR; |
||
732 | break; |
||
733 | } |
||
734 | } |
||
735 | else |
||
736 | { |
||
737 | status = HAL_ERROR; |
||
738 | } |
||
739 | |||
740 | /* Release Lock */ |
||
741 | __HAL_UNLOCK(hdma); |
||
742 | |||
743 | return status; |
||
744 | } |
||
745 | |||
746 | /** |
||
747 | * @brief UnRegister callbacks |
||
748 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
749 | * the configuration information for the specified DMA Stream. |
||
750 | * @param CallbackID: User Callback identifer |
||
751 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
752 | * @retval HAL status |
||
753 | */ |
||
754 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
||
755 | { |
||
756 | HAL_StatusTypeDef status = HAL_OK; |
||
757 | |||
758 | /* Process locked */ |
||
759 | __HAL_LOCK(hdma); |
||
760 | |||
761 | if(HAL_DMA_STATE_READY == hdma->State) |
||
762 | { |
||
763 | switch (CallbackID) |
||
764 | { |
||
765 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
766 | hdma->XferCpltCallback = NULL; |
||
767 | break; |
||
768 | |||
769 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
770 | hdma->XferHalfCpltCallback = NULL; |
||
771 | break; |
||
772 | |||
773 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
774 | hdma->XferErrorCallback = NULL; |
||
775 | break; |
||
776 | |||
777 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
778 | hdma->XferAbortCallback = NULL; |
||
779 | break; |
||
780 | |||
781 | case HAL_DMA_XFER_ALL_CB_ID: |
||
782 | hdma->XferCpltCallback = NULL; |
||
783 | hdma->XferHalfCpltCallback = NULL; |
||
784 | hdma->XferErrorCallback = NULL; |
||
785 | hdma->XferAbortCallback = NULL; |
||
786 | break; |
||
787 | |||
788 | default: |
||
789 | status = HAL_ERROR; |
||
790 | break; |
||
791 | } |
||
792 | } |
||
793 | else |
||
794 | { |
||
795 | status = HAL_ERROR; |
||
796 | } |
||
797 | |||
798 | /* Release Lock */ |
||
799 | __HAL_UNLOCK(hdma); |
||
800 | |||
801 | return status; |
||
802 | } |
||
803 | |||
804 | /** |
||
805 | * @} |
||
806 | */ |
||
807 | |||
808 | |||
809 | |||
810 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions |
||
811 | * @brief Peripheral State and Errors functions |
||
812 | * |
||
813 | @verbatim |
||
814 | =============================================================================== |
||
815 | ##### Peripheral State and Errors functions ##### |
||
816 | =============================================================================== |
||
817 | [..] |
||
818 | This subsection provides functions allowing to |
||
819 | (+) Check the DMA state |
||
820 | (+) Get error code |
||
821 | |||
822 | @endverbatim |
||
823 | * @{ |
||
824 | */ |
||
825 | |||
826 | /** |
||
827 | * @brief Return the DMA hande state. |
||
828 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
829 | * the configuration information for the specified DMA Channel. |
||
830 | * @retval HAL state |
||
831 | */ |
||
832 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
||
833 | { |
||
834 | /* Return DMA handle state */ |
||
835 | return hdma->State; |
||
836 | } |
||
837 | |||
838 | /** |
||
839 | * @brief Return the DMA error code. |
||
840 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||
841 | * the configuration information for the specified DMA Channel. |
||
842 | * @retval DMA Error Code |
||
843 | */ |
||
844 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
||
845 | { |
||
846 | return hdma->ErrorCode; |
||
847 | } |
||
848 | |||
849 | /** |
||
850 | * @} |
||
851 | */ |
||
852 | |||
853 | /** |
||
854 | * @} |
||
855 | */ |
||
856 | |||
857 | /** @addtogroup DMA_Private_Functions |
||
858 | * @{ |
||
859 | */ |
||
860 | |||
861 | /** |
||
862 | * @brief Sets the DMA Transfer parameter. |
||
863 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
864 | * the configuration information for the specified DMA Channel. |
||
865 | * @param SrcAddress: The source memory Buffer address |
||
866 | * @param DstAddress: The destination memory Buffer address |
||
867 | * @param DataLength: The length of data to be transferred from source to destination |
||
868 | * @retval HAL status |
||
869 | */ |
||
870 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||
871 | { |
||
872 | /* Clear all flags */ |
||
873 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
874 | |||
875 | /* Configure DMA Channel data length */ |
||
876 | hdma->Instance->CNDTR = DataLength; |
||
877 | |||
878 | /* Peripheral to Memory */ |
||
879 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
||
880 | { |
||
881 | /* Configure DMA Channel destination address */ |
||
882 | hdma->Instance->CPAR = DstAddress; |
||
883 | |||
884 | /* Configure DMA Channel source address */ |
||
885 | hdma->Instance->CMAR = SrcAddress; |
||
886 | } |
||
887 | /* Memory to Peripheral */ |
||
888 | else |
||
889 | { |
||
890 | /* Configure DMA Channel source address */ |
||
891 | hdma->Instance->CPAR = SrcAddress; |
||
892 | |||
893 | /* Configure DMA Channel destination address */ |
||
894 | hdma->Instance->CMAR = DstAddress; |
||
895 | } |
||
896 | } |
||
897 | |||
898 | /** |
||
899 | * @} |
||
900 | */ |
||
901 | |||
902 | /** |
||
903 | * @} |
||
904 | */ |
||
905 | |||
906 | #endif /* HAL_DMA_MODULE_ENABLED */ |
||
907 | /** |
||
908 | * @} |
||
909 | */ |
||
910 | |||
911 | /** |
||
912 | * @} |
||
913 | */ |
||
914 | |||
915 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |