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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_adc_ex.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief This file provides firmware functions to manage the following |
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| 6 | * functionalities of the Analog to Digital Convertor (ADC) |
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| 7 | * peripheral: |
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| 8 | * + Operation functions |
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| 9 | * ++ Start, stop, get result of conversions of injected |
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| 10 | * group, using 2 possible modes: polling, interruption. |
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| 11 | * + Control functions |
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| 12 | * ++ Channels configuration on injected group |
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| 13 | * Other functions (generic functions) are available in file |
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| 14 | * "stm32l1xx_hal_adc.c". |
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| 15 | * |
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| 16 | @verbatim |
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| 17 | [..] |
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| 18 | (@) Sections "ADC peripheral features" and "How to use this driver" are |
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| 19 | available in file of generic functions "stm32l1xx_hal_adc.c". |
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| 20 | [..] |
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| 21 | @endverbatim |
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| 22 | ****************************************************************************** |
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| 23 | * @attention |
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| 24 | * |
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| 28 | mjames | 25 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| 26 | * All rights reserved.</center></h2> |
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| 2 | mjames | 27 | * |
| 28 | mjames | 28 | * This software component is licensed by ST under BSD 3-Clause license, |
| 29 | * the "License"; You may not use this file except in compliance with the |
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| 30 | * License. You may obtain a copy of the License at: |
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| 31 | * opensource.org/licenses/BSD-3-Clause |
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| 2 | mjames | 32 | * |
| 33 | ****************************************************************************** |
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| 34 | */ |
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| 35 | |||
| 36 | /* Includes ------------------------------------------------------------------*/ |
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| 37 | #include "stm32l1xx_hal.h" |
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| 38 | |||
| 39 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 40 | * @{ |
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| 41 | */ |
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| 42 | |||
| 43 | /** @defgroup ADCEx ADCEx |
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| 44 | * @brief ADC Extension HAL module driver |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | |||
| 48 | #ifdef HAL_ADC_MODULE_ENABLED |
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| 49 | |||
| 50 | /* Private typedef -----------------------------------------------------------*/ |
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| 51 | /* Private define ------------------------------------------------------------*/ |
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| 52 | /** @defgroup ADCEx_Private_Constants ADCEx Private Constants |
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| 53 | * @{ |
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| 54 | */ |
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| 55 | |||
| 56 | /* ADC conversion cycles (unit: ADC clock cycles) */ |
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| 57 | /* (selected sampling time + conversion time of 12 ADC clock cycles, with */ |
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| 58 | /* resolution 12 bits) */ |
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| 28 | mjames | 59 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ( 16U) |
| 60 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ( 21U) |
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| 61 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ( 28U) |
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| 62 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ( 36U) |
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| 63 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ( 60U) |
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| 64 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES (108U) |
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| 65 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES (204U) |
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| 66 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES (396U) |
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| 2 | mjames | 67 | |
| 68 | /* Delay for temperature sensor stabilization time. */ |
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| 69 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
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| 70 | /* Unit: us */ |
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| 28 | mjames | 71 | #define ADC_TEMPSENSOR_DELAY_US (10U) |
| 2 | mjames | 72 | |
| 73 | /** |
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| 74 | * @} |
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| 75 | */ |
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| 76 | |||
| 77 | /* Private macro -------------------------------------------------------------*/ |
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| 78 | /* Private variables ---------------------------------------------------------*/ |
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| 79 | /* Private function prototypes -----------------------------------------------*/ |
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| 80 | /* Private functions ---------------------------------------------------------*/ |
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| 81 | |||
| 82 | /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions |
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| 83 | * @{ |
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| 84 | */ |
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| 85 | |||
| 86 | /** @defgroup ADCEx_Exported_Functions_Group1 ADC Extended IO operation functions |
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| 87 | * @brief ADC Extended Input and Output operation functions |
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| 88 | * |
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| 89 | @verbatim |
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| 90 | =============================================================================== |
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| 91 | ##### IO operation functions ##### |
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| 92 | =============================================================================== |
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| 93 | [..] This section provides functions allowing to: |
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| 94 | (+) Start conversion of injected group. |
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| 95 | (+) Stop conversion of injected group. |
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| 96 | (+) Poll for conversion complete on injected group. |
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| 97 | (+) Get result of injected channel conversion. |
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| 98 | (+) Start conversion of injected group and enable interruptions. |
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| 99 | (+) Stop conversion of injected group and disable interruptions. |
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| 100 | |||
| 101 | @endverbatim |
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| 102 | * @{ |
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| 103 | */ |
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| 104 | |||
| 105 | /** |
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| 106 | * @brief Enables ADC, starts conversion of injected group. |
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| 107 | * Interruptions enabled in this function: None. |
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| 28 | mjames | 108 | * @param hadc ADC handle |
| 2 | mjames | 109 | * @retval HAL status |
| 110 | */ |
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| 111 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) |
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| 112 | { |
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| 113 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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| 114 | |||
| 115 | /* Check the parameters */ |
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| 116 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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| 117 | |||
| 118 | /* Process locked */ |
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| 119 | __HAL_LOCK(hadc); |
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| 120 | |||
| 121 | /* Enable the ADC peripheral */ |
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| 122 | tmp_hal_status = ADC_Enable(hadc); |
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| 123 | |||
| 124 | /* Start conversion if ADC is effectively enabled */ |
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| 125 | if (tmp_hal_status == HAL_OK) |
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| 126 | { |
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| 127 | /* Set ADC state */ |
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| 128 | /* - Clear state bitfield related to injected group conversion results */ |
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| 129 | /* - Set state bitfield related to injected operation */ |
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| 130 | ADC_STATE_CLR_SET(hadc->State, |
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| 131 | HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, |
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| 132 | HAL_ADC_STATE_INJ_BUSY); |
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| 133 | |||
| 134 | /* Check if a regular conversion is ongoing */ |
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| 135 | /* Note: On this device, there is no ADC error code fields related to */ |
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| 136 | /* conversions on group injected only. In case of conversion on */ |
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| 137 | /* going on group regular, no error code is reset. */ |
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| 138 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
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| 139 | { |
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| 140 | /* Reset ADC all error code fields */ |
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| 141 | ADC_CLEAR_ERRORCODE(hadc); |
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| 142 | } |
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| 143 | |||
| 144 | /* Process unlocked */ |
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| 145 | /* Unlock before starting ADC conversions: in case of potential */ |
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| 146 | /* interruption, to let the process to ADC IRQ Handler. */ |
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| 147 | __HAL_UNLOCK(hadc); |
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| 148 | |||
| 149 | /* Clear injected group conversion flag */ |
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| 150 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
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| 151 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); |
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| 152 | |||
| 153 | /* Enable conversion of injected group. */ |
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| 154 | /* If software start has been selected, conversion starts immediately. */ |
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| 155 | /* If external trigger has been selected, conversion will start at next */ |
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| 156 | /* trigger event. */ |
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| 157 | /* If automatic injected conversion is enabled, conversion will start */ |
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| 158 | /* after next regular group conversion. */ |
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| 159 | if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
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| 160 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
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| 161 | { |
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| 162 | /* Enable ADC software conversion for injected channels */ |
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| 163 | SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); |
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| 164 | } |
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| 165 | } |
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| 166 | |||
| 167 | /* Return function status */ |
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| 168 | return tmp_hal_status; |
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| 169 | } |
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| 170 | |||
| 171 | /** |
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| 172 | * @brief Stop conversion of injected channels. Disable ADC peripheral if |
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| 173 | * no regular conversion is on going. |
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| 174 | * @note If ADC must be disabled and if conversion is on going on |
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| 175 | * regular group, function HAL_ADC_Stop must be used to stop both |
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| 176 | * injected and regular groups, and disable the ADC. |
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| 177 | * @note If injected group mode auto-injection is enabled, |
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| 178 | * function HAL_ADC_Stop must be used. |
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| 179 | * @note In case of auto-injection mode, HAL_ADC_Stop must be used. |
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| 28 | mjames | 180 | * @param hadc ADC handle |
| 2 | mjames | 181 | * @retval None |
| 182 | */ |
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| 183 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) |
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| 184 | { |
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| 185 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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| 186 | |||
| 187 | /* Check the parameters */ |
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| 188 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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| 189 | |||
| 190 | /* Process locked */ |
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| 191 | __HAL_LOCK(hadc); |
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| 192 | |||
| 193 | /* Stop potential conversion and disable ADC peripheral */ |
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| 194 | /* Conditioned to: */ |
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| 195 | /* - No conversion on the other group (regular group) is intended to */ |
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| 196 | /* continue (injected and regular groups stop conversion and ADC disable */ |
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| 197 | /* are common) */ |
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| 198 | /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ |
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| 199 | if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && |
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| 200 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
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| 201 | { |
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| 202 | /* Stop potential conversion on going, on regular and injected groups */ |
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| 203 | /* Disable ADC peripheral */ |
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| 204 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
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| 205 | |||
| 206 | /* Check if ADC is effectively disabled */ |
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| 207 | if (tmp_hal_status == HAL_OK) |
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| 208 | { |
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| 209 | /* Set ADC state */ |
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| 210 | ADC_STATE_CLR_SET(hadc->State, |
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| 211 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
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| 212 | HAL_ADC_STATE_READY); |
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| 213 | } |
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| 214 | } |
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| 215 | else |
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| 216 | { |
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| 217 | /* Update ADC state machine to error */ |
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| 218 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
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| 219 | |||
| 220 | tmp_hal_status = HAL_ERROR; |
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| 221 | } |
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| 222 | |||
| 223 | /* Process unlocked */ |
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| 224 | __HAL_UNLOCK(hadc); |
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| 225 | |||
| 226 | /* Return function status */ |
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| 227 | return tmp_hal_status; |
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| 228 | } |
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| 229 | |||
| 230 | /** |
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| 231 | * @brief Wait for injected group conversion to be completed. |
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| 28 | mjames | 232 | * @param hadc ADC handle |
| 233 | * @param Timeout Timeout value in millisecond. |
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| 2 | mjames | 234 | * @retval HAL status |
| 235 | */ |
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| 236 | HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
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| 237 | { |
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| 238 | uint32_t tickstart; |
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| 239 | |||
| 240 | /* Variables for polling in case of scan mode enabled and polling for each */ |
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| 241 | /* conversion. */ |
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| 242 | /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU */ |
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| 243 | /* cycles to compensate number of CPU cycles for processing of variable */ |
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| 244 | /* "conversion_timeout_cpu_cycles_max" */ |
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| 245 | uint32_t conversion_timeout_cpu_cycles = 28; |
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| 246 | uint32_t conversion_timeout_cpu_cycles_max = 0; |
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| 247 | |||
| 248 | /* Check the parameters */ |
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| 249 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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| 250 | |||
| 251 | /* Get timeout */ |
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| 252 | tickstart = HAL_GetTick(); |
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| 253 | |||
| 254 | /* Polling for end of conversion: differentiation if single/sequence */ |
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| 255 | /* conversion. */ |
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| 256 | /* For injected group, flag JEOC is set only at the end of the sequence, */ |
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| 257 | /* not for each conversion within the sequence. */ |
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| 258 | /* If setting "EOCSelection" is set to poll for each single conversion, */ |
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| 259 | /* management of polling depends on setting of injected group sequencer: */ |
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| 260 | /* - If single conversion for injected group (scan mode disabled or */ |
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| 261 | /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ |
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| 262 | /* conversion completion. */ |
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| 263 | /* - If sequence conversion for injected group (scan mode enabled and */ |
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| 264 | /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ |
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| 265 | /* sequence. */ |
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| 266 | /* To poll for each conversion, the maximum conversion time is computed */ |
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| 267 | /* from ADC conversion time (selected sampling time + conversion time of */ |
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| 268 | /* 12 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ |
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| 269 | /* settings, conversion time range can vary from 8 to several thousands */ |
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| 270 | /* of CPU cycles). */ |
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| 271 | |||
| 272 | /* Note: On STM32L1, setting "EOCSelection" is related to regular group */ |
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| 273 | /* only, by hardware. For compatibility with other STM32 devices, */ |
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| 274 | /* this setting is related also to injected group by software. */ |
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| 275 | if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) || |
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| 276 | (hadc->Init.EOCSelection != ADC_EOC_SINGLE_CONV) ) |
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| 277 | { |
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| 278 | /* Wait until End of Conversion flag is raised */ |
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| 279 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) |
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| 280 | { |
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| 281 | /* Check if timeout is disabled (set to infinite wait) */ |
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| 282 | if(Timeout != HAL_MAX_DELAY) |
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| 283 | { |
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| 284 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
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| 285 | { |
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| 286 | /* Update ADC state machine to timeout */ |
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| 287 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
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| 288 | |||
| 289 | /* Process unlocked */ |
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| 290 | __HAL_UNLOCK(hadc); |
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| 291 | |||
| 292 | return HAL_TIMEOUT; |
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| 293 | } |
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| 294 | } |
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| 295 | } |
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| 296 | } |
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| 297 | else |
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| 298 | { |
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| 299 | /* Computation of CPU cycles corresponding to ADC conversion cycles. */ |
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| 300 | /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ |
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| 301 | /* channels. */ |
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| 302 | conversion_timeout_cpu_cycles_max = ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc); |
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| 303 | conversion_timeout_cpu_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc); |
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| 304 | |||
| 305 | /* Poll with maximum conversion time */ |
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| 306 | while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max) |
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| 307 | { |
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| 308 | /* Check if timeout is disabled (set to infinite wait) */ |
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| 309 | if(Timeout != HAL_MAX_DELAY) |
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| 310 | { |
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| 311 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
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| 312 | { |
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| 313 | /* Update ADC state machine to timeout */ |
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| 314 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
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| 315 | |||
| 316 | /* Process unlocked */ |
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| 317 | __HAL_UNLOCK(hadc); |
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| 318 | |||
| 319 | return HAL_TIMEOUT; |
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| 320 | } |
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| 321 | } |
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| 322 | conversion_timeout_cpu_cycles ++; |
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| 323 | } |
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| 324 | } |
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| 325 | |||
| 326 | /* Clear end of conversion flag of injected group if low power feature */ |
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| 327 | /* "Auto Wait" is disabled, to not interfere with this feature until data */ |
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| 328 | /* register is read using function HAL_ADCEx_InjectedGetValue(). */ |
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| 329 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
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| 330 | { |
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| 331 | /* Clear injected group conversion flag */ |
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| 332 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); |
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| 333 | } |
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| 334 | |||
| 335 | /* Update ADC state machine */ |
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| 336 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
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| 337 | |||
| 338 | /* Determine whether any further conversion upcoming on group injected */ |
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| 339 | /* by external trigger, continuous mode or scan sequence on going. */ |
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| 340 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
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| 341 | /* The test of scan sequence on going is done either with scan */ |
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| 342 | /* sequence disabled or with end of conversion flag set to */ |
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| 343 | /* of end of sequence. */ |
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| 344 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
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| 345 | (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || |
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| 346 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && |
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| 347 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
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| 348 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
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| 349 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
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| 350 | { |
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| 351 | /* Set ADC state */ |
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| 352 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
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| 353 | |||
| 354 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
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| 355 | { |
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| 356 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
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| 357 | } |
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| 358 | } |
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| 359 | |||
| 360 | /* Return ADC state */ |
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| 361 | return HAL_OK; |
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| 362 | } |
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| 363 | |||
| 364 | /** |
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| 365 | * @brief Enables ADC, starts conversion of injected group with interruption. |
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| 366 | * - JEOC (end of conversion of injected group) |
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| 367 | * Each of these interruptions has its dedicated callback function. |
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| 28 | mjames | 368 | * @param hadc ADC handle |
| 2 | mjames | 369 | * @retval HAL status. |
| 370 | */ |
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| 371 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) |
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| 372 | { |
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| 373 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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| 374 | |||
| 375 | /* Check the parameters */ |
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| 376 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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| 377 | |||
| 378 | /* Process locked */ |
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| 379 | __HAL_LOCK(hadc); |
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| 380 | |||
| 381 | /* Enable the ADC peripheral */ |
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| 382 | tmp_hal_status = ADC_Enable(hadc); |
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| 383 | |||
| 384 | /* Start conversion if ADC is effectively enabled */ |
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| 385 | if (tmp_hal_status == HAL_OK) |
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| 386 | { |
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| 387 | /* Set ADC state */ |
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| 388 | /* - Clear state bitfield related to injected group conversion results */ |
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| 389 | /* - Set state bitfield related to injected operation */ |
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| 390 | ADC_STATE_CLR_SET(hadc->State, |
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| 391 | HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, |
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| 392 | HAL_ADC_STATE_INJ_BUSY); |
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| 393 | |||
| 394 | /* Check if a regular conversion is ongoing */ |
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| 395 | /* Note: On this device, there is no ADC error code fields related to */ |
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| 396 | /* conversions on group injected only. In case of conversion on */ |
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| 397 | /* going on group regular, no error code is reset. */ |
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| 398 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
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| 399 | { |
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| 400 | /* Reset ADC all error code fields */ |
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| 401 | ADC_CLEAR_ERRORCODE(hadc); |
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| 402 | } |
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| 403 | |||
| 404 | /* Process unlocked */ |
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| 405 | /* Unlock before starting ADC conversions: in case of potential */ |
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| 406 | /* interruption, to let the process to ADC IRQ Handler. */ |
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| 407 | __HAL_UNLOCK(hadc); |
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| 408 | |||
| 409 | /* Clear injected group conversion flag */ |
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| 410 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
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| 411 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); |
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| 412 | |||
| 413 | /* Enable end of conversion interrupt for injected channels */ |
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| 414 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); |
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| 415 | |||
| 416 | /* Enable conversion of injected group. */ |
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| 417 | /* If software start has been selected, conversion starts immediately. */ |
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| 418 | /* If external trigger has been selected, conversion will start at next */ |
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| 419 | /* trigger event. */ |
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| 420 | /* If automatic injected conversion is enabled, conversion will start */ |
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| 421 | /* after next regular group conversion. */ |
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| 422 | if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
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| 423 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
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| 424 | { |
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| 425 | /* Enable ADC software conversion for injected channels */ |
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| 426 | SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); |
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| 427 | } |
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| 428 | } |
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| 429 | |||
| 430 | /* Return function status */ |
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| 431 | return tmp_hal_status; |
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| 432 | } |
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| 433 | |||
| 434 | /** |
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| 435 | * @brief Stop conversion of injected channels, disable interruption of |
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| 436 | * end-of-conversion. Disable ADC peripheral if no regular conversion |
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| 437 | * is on going. |
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| 438 | * @note If ADC must be disabled and if conversion is on going on |
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| 439 | * regular group, function HAL_ADC_Stop must be used to stop both |
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| 440 | * injected and regular groups, and disable the ADC. |
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| 441 | * @note If injected group mode auto-injection is enabled, |
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| 442 | * function HAL_ADC_Stop must be used. |
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| 28 | mjames | 443 | * @param hadc ADC handle |
| 2 | mjames | 444 | * @retval None |
| 445 | */ |
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| 446 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) |
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| 447 | { |
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| 448 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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| 449 | |||
| 450 | /* Check the parameters */ |
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| 451 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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| 452 | |||
| 453 | /* Process locked */ |
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| 454 | __HAL_LOCK(hadc); |
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| 455 | |||
| 456 | /* Stop potential conversion and disable ADC peripheral */ |
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| 457 | /* Conditioned to: */ |
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| 458 | /* - No conversion on the other group (regular group) is intended to */ |
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| 459 | /* continue (injected and regular groups stop conversion and ADC disable */ |
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| 460 | /* are common) */ |
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| 461 | /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ |
||
| 462 | if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && |
||
| 463 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
||
| 464 | { |
||
| 465 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 466 | /* Disable ADC peripheral */ |
||
| 467 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 468 | |||
| 469 | /* Check if ADC is effectively disabled */ |
||
| 470 | if (tmp_hal_status == HAL_OK) |
||
| 471 | { |
||
| 472 | /* Disable ADC end of conversion interrupt for injected channels */ |
||
| 473 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
||
| 474 | |||
| 475 | /* Set ADC state */ |
||
| 476 | ADC_STATE_CLR_SET(hadc->State, |
||
| 477 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 478 | HAL_ADC_STATE_READY); |
||
| 479 | } |
||
| 480 | } |
||
| 481 | else |
||
| 482 | { |
||
| 483 | /* Update ADC state machine to error */ |
||
| 484 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 485 | |||
| 486 | tmp_hal_status = HAL_ERROR; |
||
| 487 | } |
||
| 488 | |||
| 489 | /* Process unlocked */ |
||
| 490 | __HAL_UNLOCK(hadc); |
||
| 491 | |||
| 492 | /* Return function status */ |
||
| 493 | return tmp_hal_status; |
||
| 494 | } |
||
| 495 | |||
| 496 | /** |
||
| 497 | * @brief Get ADC injected group conversion result. |
||
| 498 | * @note Reading register JDRx automatically clears ADC flag JEOC |
||
| 499 | * (ADC group injected end of unitary conversion). |
||
| 500 | * @note This function does not clear ADC flag JEOS |
||
| 501 | * (ADC group injected end of sequence conversion) |
||
| 502 | * Occurrence of flag JEOS rising: |
||
| 503 | * - If sequencer is composed of 1 rank, flag JEOS is equivalent |
||
| 504 | * to flag JEOC. |
||
| 505 | * - If sequencer is composed of several ranks, during the scan |
||
| 506 | * sequence flag JEOC only is raised, at the end of the scan sequence |
||
| 507 | * both flags JEOC and EOS are raised. |
||
| 508 | * Flag JEOS must not be cleared by this function because |
||
| 509 | * it would not be compliant with low power features |
||
| 510 | * (feature low power auto-wait, not available on all STM32 families). |
||
| 511 | * To clear this flag, either use function: |
||
| 512 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
||
| 513 | * model polling: @ref HAL_ADCEx_InjectedPollForConversion() |
||
| 514 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). |
||
| 28 | mjames | 515 | * @param hadc ADC handle |
| 516 | * @param InjectedRank the converted ADC injected rank. |
||
| 2 | mjames | 517 | * This parameter can be one of the following values: |
| 518 | * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected |
||
| 519 | * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected |
||
| 520 | * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected |
||
| 521 | * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected |
||
| 522 | * @retval ADC group injected conversion data |
||
| 523 | */ |
||
| 524 | uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) |
||
| 525 | { |
||
| 526 | uint32_t tmp_jdr = 0; |
||
| 527 | |||
| 528 | /* Check the parameters */ |
||
| 529 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 530 | assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); |
||
| 531 | |||
| 532 | /* Get ADC converted value */ |
||
| 533 | switch(InjectedRank) |
||
| 534 | { |
||
| 535 | case ADC_INJECTED_RANK_4: |
||
| 536 | tmp_jdr = hadc->Instance->JDR4; |
||
| 537 | break; |
||
| 538 | case ADC_INJECTED_RANK_3: |
||
| 539 | tmp_jdr = hadc->Instance->JDR3; |
||
| 540 | break; |
||
| 541 | case ADC_INJECTED_RANK_2: |
||
| 542 | tmp_jdr = hadc->Instance->JDR2; |
||
| 543 | break; |
||
| 544 | case ADC_INJECTED_RANK_1: |
||
| 545 | default: |
||
| 546 | tmp_jdr = hadc->Instance->JDR1; |
||
| 547 | break; |
||
| 548 | } |
||
| 549 | |||
| 550 | /* Return ADC converted value */ |
||
| 551 | return tmp_jdr; |
||
| 552 | } |
||
| 553 | |||
| 554 | /** |
||
| 555 | * @brief Injected conversion complete callback in non blocking mode |
||
| 28 | mjames | 556 | * @param hadc ADC handle |
| 2 | mjames | 557 | * @retval None |
| 558 | */ |
||
| 559 | __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) |
||
| 560 | { |
||
| 561 | /* Prevent unused argument(s) compilation warning */ |
||
| 562 | UNUSED(hadc); |
||
| 563 | |||
| 564 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
| 565 | the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file |
||
| 566 | */ |
||
| 567 | } |
||
| 568 | |||
| 569 | /** |
||
| 570 | * @} |
||
| 571 | */ |
||
| 572 | |||
| 573 | /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions |
||
| 574 | * @brief ADC Extended Peripheral Control functions |
||
| 575 | * |
||
| 576 | @verbatim |
||
| 577 | =============================================================================== |
||
| 578 | ##### Peripheral Control functions ##### |
||
| 579 | =============================================================================== |
||
| 580 | [..] This section provides functions allowing to: |
||
| 581 | (+) Configure channels on injected group |
||
| 582 | |||
| 583 | @endverbatim |
||
| 584 | * @{ |
||
| 585 | */ |
||
| 586 | |||
| 587 | /** |
||
| 588 | * @brief Configures the ADC injected group and the selected channel to be |
||
| 589 | * linked to the injected group. |
||
| 590 | * @note Possibility to update parameters on the fly: |
||
| 591 | * This function initializes injected group, following calls to this |
||
| 592 | * function can be used to reconfigure some parameters of structure |
||
| 593 | * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. |
||
| 594 | * The setting of these parameters is conditioned to ADC state: |
||
| 595 | * this function must be called when ADC is not under conversion. |
||
| 28 | mjames | 596 | * @param hadc ADC handle |
| 597 | * @param sConfigInjected Structure of ADC injected group and ADC channel for |
||
| 2 | mjames | 598 | * injected group. |
| 599 | * @retval None |
||
| 600 | */ |
||
| 601 | HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) |
||
| 602 | { |
||
| 603 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 604 | __IO uint32_t wait_loop_index = 0; |
||
| 605 | |||
| 606 | /* Check the parameters */ |
||
| 607 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 608 | assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); |
||
| 609 | assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); |
||
| 610 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); |
||
| 611 | assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); |
||
| 612 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, sConfigInjected->InjectedOffset)); |
||
| 613 | |||
| 614 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
||
| 615 | { |
||
| 616 | assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); |
||
| 617 | assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); |
||
| 618 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); |
||
| 619 | } |
||
| 620 | |||
| 621 | if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) |
||
| 622 | { |
||
| 623 | assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); |
||
| 624 | } |
||
| 625 | |||
| 626 | /* Process locked */ |
||
| 627 | __HAL_LOCK(hadc); |
||
| 628 | |||
| 629 | /* Configuration of injected group sequencer: */ |
||
| 630 | /* - if scan mode is disabled, injected channels sequence length is set to */ |
||
| 631 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
||
| 632 | /* Parameter "InjectedNbrOfConversion" is discarded. */ |
||
| 633 | /* Note: Scan mode is present by hardware on this device and, if */ |
||
| 634 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
||
| 635 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
||
| 636 | /* - if scan mode is enabled, injected channels sequence length is set to */ |
||
| 637 | /* parameter ""InjectedNbrOfConversion". */ |
||
| 638 | if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) |
||
| 639 | { |
||
| 640 | if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) |
||
| 641 | { |
||
| 642 | /* Clear the old SQx bits for all injected ranks */ |
||
| 643 | MODIFY_REG(hadc->Instance->JSQR , |
||
| 644 | ADC_JSQR_JL | |
||
| 645 | ADC_JSQR_JSQ4 | |
||
| 646 | ADC_JSQR_JSQ3 | |
||
| 647 | ADC_JSQR_JSQ2 | |
||
| 648 | ADC_JSQR_JSQ1 , |
||
| 649 | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, |
||
| 650 | ADC_INJECTED_RANK_1, |
||
| 651 | 0x01) ); |
||
| 652 | } |
||
| 653 | /* If another injected rank than rank1 was intended to be set, and could */ |
||
| 654 | /* not due to ScanConvMode disabled, error is reported. */ |
||
| 655 | else |
||
| 656 | { |
||
| 657 | /* Update ADC state machine to error */ |
||
| 658 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 659 | |||
| 660 | tmp_hal_status = HAL_ERROR; |
||
| 661 | } |
||
| 662 | } |
||
| 663 | else |
||
| 664 | { |
||
| 665 | /* Since injected channels rank conv. order depends on total number of */ |
||
| 666 | /* injected conversions, selected rank must be below or equal to total */ |
||
| 667 | /* number of injected conversions to be updated. */ |
||
| 668 | if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) |
||
| 669 | { |
||
| 670 | /* Clear the old SQx bits for the selected rank */ |
||
| 671 | /* Set the SQx bits for the selected rank */ |
||
| 672 | MODIFY_REG(hadc->Instance->JSQR , |
||
| 673 | |||
| 674 | ADC_JSQR_JL | |
||
| 675 | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, |
||
| 676 | sConfigInjected->InjectedRank, |
||
| 677 | sConfigInjected->InjectedNbrOfConversion) , |
||
| 678 | |||
| 679 | ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | |
||
| 680 | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, |
||
| 681 | sConfigInjected->InjectedRank, |
||
| 682 | sConfigInjected->InjectedNbrOfConversion) ); |
||
| 683 | } |
||
| 684 | else |
||
| 685 | { |
||
| 686 | /* Clear the old SQx bits for the selected rank */ |
||
| 687 | MODIFY_REG(hadc->Instance->JSQR , |
||
| 688 | |||
| 689 | ADC_JSQR_JL | |
||
| 690 | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, |
||
| 691 | sConfigInjected->InjectedRank, |
||
| 692 | sConfigInjected->InjectedNbrOfConversion) , |
||
| 693 | |||
| 694 | 0x00000000 ); |
||
| 695 | } |
||
| 696 | } |
||
| 697 | |||
| 698 | /* Enable external trigger if trigger selection is different of software */ |
||
| 699 | /* start. */ |
||
| 700 | /* Note: This configuration keeps the hardware feature of parameter */ |
||
| 701 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
||
| 702 | /* software start. */ |
||
| 703 | |||
| 704 | if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) |
||
| 705 | { |
||
| 706 | MODIFY_REG(hadc->Instance->CR2 , |
||
| 707 | ADC_CR2_JEXTEN | |
||
| 708 | ADC_CR2_JEXTSEL , |
||
| 709 | sConfigInjected->ExternalTrigInjecConv | |
||
| 710 | sConfigInjected->ExternalTrigInjecConvEdge ); |
||
| 711 | } |
||
| 712 | else |
||
| 713 | { |
||
| 714 | MODIFY_REG(hadc->Instance->CR2, |
||
| 715 | ADC_CR2_JEXTEN | |
||
| 716 | ADC_CR2_JEXTSEL , |
||
| 717 | 0x00000000 ); |
||
| 718 | } |
||
| 719 | |||
| 720 | /* Configuration of injected group */ |
||
| 721 | /* Parameters update conditioned to ADC state: */ |
||
| 722 | /* Parameters that can be updated only when ADC is disabled: */ |
||
| 723 | /* - Automatic injected conversion */ |
||
| 724 | /* - Injected discontinuous mode */ |
||
| 725 | if ((ADC_IS_ENABLE(hadc) == RESET)) |
||
| 726 | { |
||
| 727 | hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO | |
||
| 728 | ADC_CR1_JDISCEN ); |
||
| 729 | |||
| 730 | /* Automatic injected conversion can be enabled if injected group */ |
||
| 731 | /* external triggers are disabled. */ |
||
| 732 | if (sConfigInjected->AutoInjectedConv == ENABLE) |
||
| 733 | { |
||
| 734 | if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) |
||
| 735 | { |
||
| 736 | SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); |
||
| 737 | } |
||
| 738 | else |
||
| 739 | { |
||
| 740 | /* Update ADC state machine to error */ |
||
| 741 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 742 | |||
| 743 | tmp_hal_status = HAL_ERROR; |
||
| 744 | } |
||
| 745 | } |
||
| 746 | |||
| 747 | /* Injected discontinuous can be enabled only if auto-injected mode is */ |
||
| 748 | /* disabled. */ |
||
| 749 | if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) |
||
| 750 | { |
||
| 751 | if (sConfigInjected->AutoInjectedConv == DISABLE) |
||
| 752 | { |
||
| 753 | SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); |
||
| 754 | } |
||
| 755 | else |
||
| 756 | { |
||
| 757 | /* Update ADC state machine to error */ |
||
| 758 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 759 | |||
| 760 | tmp_hal_status = HAL_ERROR; |
||
| 761 | } |
||
| 762 | } |
||
| 763 | } |
||
| 764 | |||
| 765 | /* Channel sampling time configuration */ |
||
| 766 | /* For InjectedChannels 0 to 9 */ |
||
| 767 | if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10) |
||
| 768 | { |
||
| 769 | MODIFY_REG(hadc->Instance->SMPR3, |
||
| 770 | ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel), |
||
| 771 | ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); |
||
| 772 | } |
||
| 773 | /* For InjectedChannels 10 to 19 */ |
||
| 774 | else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20) |
||
| 775 | { |
||
| 776 | MODIFY_REG(hadc->Instance->SMPR2, |
||
| 777 | ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel), |
||
| 778 | ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); |
||
| 779 | } |
||
| 780 | /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ |
||
| 781 | /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */ |
||
| 782 | else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX) |
||
| 783 | { |
||
| 784 | MODIFY_REG(hadc->Instance->SMPR1, |
||
| 785 | ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel), |
||
| 786 | ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); |
||
| 787 | } |
||
| 788 | /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */ |
||
| 789 | else |
||
| 790 | { |
||
| 791 | ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); |
||
| 792 | } |
||
| 793 | |||
| 794 | |||
| 795 | /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ |
||
| 796 | switch(sConfigInjected->InjectedRank) |
||
| 797 | { |
||
| 798 | case 1: |
||
| 799 | /* Set injected channel 1 offset */ |
||
| 800 | MODIFY_REG(hadc->Instance->JOFR1, |
||
| 801 | ADC_JOFR1_JOFFSET1, |
||
| 802 | sConfigInjected->InjectedOffset); |
||
| 803 | break; |
||
| 804 | case 2: |
||
| 805 | /* Set injected channel 2 offset */ |
||
| 806 | MODIFY_REG(hadc->Instance->JOFR2, |
||
| 807 | ADC_JOFR2_JOFFSET2, |
||
| 808 | sConfigInjected->InjectedOffset); |
||
| 809 | break; |
||
| 810 | case 3: |
||
| 811 | /* Set injected channel 3 offset */ |
||
| 812 | MODIFY_REG(hadc->Instance->JOFR3, |
||
| 813 | ADC_JOFR3_JOFFSET3, |
||
| 814 | sConfigInjected->InjectedOffset); |
||
| 815 | break; |
||
| 816 | case 4: |
||
| 817 | default: |
||
| 818 | MODIFY_REG(hadc->Instance->JOFR4, |
||
| 819 | ADC_JOFR4_JOFFSET4, |
||
| 820 | sConfigInjected->InjectedOffset); |
||
| 821 | break; |
||
| 822 | } |
||
| 823 | |||
| 824 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
||
| 825 | /* and VREFINT measurement path. */ |
||
| 826 | if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || |
||
| 827 | (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) |
||
| 828 | { |
||
| 829 | SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
||
| 830 | |||
| 831 | if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) |
||
| 832 | { |
||
| 833 | /* Delay for temperature sensor stabilization time */ |
||
| 834 | /* Compute number of CPU cycles to wait for */ |
||
| 835 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); |
||
| 836 | while(wait_loop_index != 0) |
||
| 837 | { |
||
| 838 | wait_loop_index--; |
||
| 839 | } |
||
| 840 | } |
||
| 841 | } |
||
| 842 | |||
| 843 | /* Process unlocked */ |
||
| 844 | __HAL_UNLOCK(hadc); |
||
| 845 | |||
| 846 | /* Return function status */ |
||
| 847 | return tmp_hal_status; |
||
| 848 | } |
||
| 849 | |||
| 850 | /** |
||
| 851 | * @} |
||
| 852 | */ |
||
| 853 | |||
| 854 | /** |
||
| 855 | * @} |
||
| 856 | */ |
||
| 857 | |||
| 858 | #endif /* HAL_ADC_MODULE_ENABLED */ |
||
| 859 | /** |
||
| 860 | * @} |
||
| 861 | */ |
||
| 862 | |||
| 863 | /** |
||
| 864 | * @} |
||
| 865 | */ |
||
| 866 | |||
| 867 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |