Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
||
| 3 | * @file stm32l1xx_hal_tim.h |
||
| 4 | * @author MCD Application Team |
||
| 5 | * @version V1.2.0 |
||
| 6 | * @date 01-July-2016 |
||
| 7 | * @brief Header file of TIM HAL module. |
||
| 8 | ****************************************************************************** |
||
| 9 | * @attention |
||
| 10 | * |
||
| 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||
| 12 | * |
||
| 13 | * Redistribution and use in source and binary forms, with or without modification, |
||
| 14 | * are permitted provided that the following conditions are met: |
||
| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
||
| 16 | * this list of conditions and the following disclaimer. |
||
| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
||
| 18 | * this list of conditions and the following disclaimer in the documentation |
||
| 19 | * and/or other materials provided with the distribution. |
||
| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
||
| 21 | * may be used to endorse or promote products derived from this software |
||
| 22 | * without specific prior written permission. |
||
| 23 | * |
||
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||
| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||
| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||
| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||
| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||
| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||
| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||
| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||
| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 34 | * |
||
| 35 | ****************************************************************************** |
||
| 36 | */ |
||
| 37 | |||
| 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
||
| 39 | #ifndef __STM32L1xx_HAL_TIM_H |
||
| 40 | #define __STM32L1xx_HAL_TIM_H |
||
| 41 | |||
| 42 | #ifdef __cplusplus |
||
| 43 | extern "C" { |
||
| 44 | #endif |
||
| 45 | |||
| 46 | /* Includes ------------------------------------------------------------------*/ |
||
| 47 | #include "stm32l1xx_hal_def.h" |
||
| 48 | |||
| 49 | /** @addtogroup STM32L1xx_HAL_Driver |
||
| 50 | * @{ |
||
| 51 | */ |
||
| 52 | |||
| 53 | /** @addtogroup TIM |
||
| 54 | * @{ |
||
| 55 | */ |
||
| 56 | |||
| 57 | /* Exported types ------------------------------------------------------------*/ |
||
| 58 | /** @defgroup TIM_Exported_Types TIM Exported Types |
||
| 59 | * @{ |
||
| 60 | */ |
||
| 61 | /** |
||
| 62 | * @brief TIM Time base Configuration Structure definition |
||
| 63 | */ |
||
| 64 | typedef struct |
||
| 65 | { |
||
| 66 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
||
| 67 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
||
| 68 | |||
| 69 | uint32_t CounterMode; /*!< Specifies the counter mode. |
||
| 70 | This parameter can be a value of @ref TIM_Counter_Mode */ |
||
| 71 | |||
| 72 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
||
| 73 | Auto-Reload Register at the next update event. |
||
| 74 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
||
| 75 | |||
| 76 | uint32_t ClockDivision; /*!< Specifies the clock division. |
||
| 77 | This parameter can be a value of @ref TIM_ClockDivision */ |
||
| 78 | |||
| 79 | } TIM_Base_InitTypeDef; |
||
| 80 | |||
| 81 | /** |
||
| 82 | * @brief TIM Output Compare Configuration Structure definition |
||
| 83 | */ |
||
| 84 | typedef struct |
||
| 85 | { |
||
| 86 | uint32_t OCMode; /*!< Specifies the TIM mode. |
||
| 87 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
||
| 88 | |||
| 89 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
||
| 90 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
||
| 91 | |||
| 92 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
||
| 93 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
||
| 94 | |||
| 95 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
||
| 96 | This parameter can be a value of @ref TIM_Output_Fast_State |
||
| 97 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
||
| 98 | |||
| 99 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
||
| 100 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */ |
||
| 101 | } TIM_OC_InitTypeDef; |
||
| 102 | |||
| 103 | /** |
||
| 104 | * @brief TIM One Pulse Mode Configuration Structure definition |
||
| 105 | */ |
||
| 106 | typedef struct |
||
| 107 | { |
||
| 108 | uint32_t OCMode; /*!< Specifies the TIM mode. |
||
| 109 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
||
| 110 | |||
| 111 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
||
| 112 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
||
| 113 | |||
| 114 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
||
| 115 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
||
| 116 | |||
| 117 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
||
| 118 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */ |
||
| 119 | |||
| 120 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
||
| 121 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
||
| 122 | |||
| 123 | uint32_t ICSelection; /*!< Specifies the input. |
||
| 124 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
||
| 125 | |||
| 126 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
||
| 127 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 128 | } TIM_OnePulse_InitTypeDef; |
||
| 129 | |||
| 130 | |||
| 131 | /** |
||
| 132 | * @brief TIM Input Capture Configuration Structure definition |
||
| 133 | */ |
||
| 134 | typedef struct |
||
| 135 | { |
||
| 136 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
||
| 137 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
||
| 138 | |||
| 139 | uint32_t ICSelection; /*!< Specifies the input. |
||
| 140 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
||
| 141 | |||
| 142 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
||
| 143 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
||
| 144 | |||
| 145 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
||
| 146 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 147 | } TIM_IC_InitTypeDef; |
||
| 148 | |||
| 149 | /** |
||
| 150 | * @brief TIM Encoder Configuration Structure definition |
||
| 151 | */ |
||
| 152 | typedef struct |
||
| 153 | { |
||
| 154 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
||
| 155 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
||
| 156 | |||
| 157 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
||
| 158 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
||
| 159 | |||
| 160 | uint32_t IC1Selection; /*!< Specifies the input. |
||
| 161 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
||
| 162 | |||
| 163 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
||
| 164 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
||
| 165 | |||
| 166 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
||
| 167 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 168 | |||
| 169 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
||
| 170 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
||
| 171 | |||
| 172 | uint32_t IC2Selection; /*!< Specifies the input. |
||
| 173 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
||
| 174 | |||
| 175 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
||
| 176 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
||
| 177 | |||
| 178 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
||
| 179 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 180 | } TIM_Encoder_InitTypeDef; |
||
| 181 | |||
| 182 | |||
| 183 | /** |
||
| 184 | * @brief TIM Clock Configuration Handle Structure definition |
||
| 185 | */ |
||
| 186 | typedef struct |
||
| 187 | { |
||
| 188 | uint32_t ClockSource; /*!< TIM clock sources |
||
| 189 | This parameter can be a value of @ref TIM_Clock_Source */ |
||
| 190 | uint32_t ClockPolarity; /*!< TIM clock polarity |
||
| 191 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
||
| 192 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
||
| 193 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
||
| 194 | uint32_t ClockFilter; /*!< TIM clock filter |
||
| 195 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 196 | }TIM_ClockConfigTypeDef; |
||
| 197 | |||
| 198 | /** |
||
| 199 | * @brief TIM Clear Input Configuration Handle Structure definition |
||
| 200 | */ |
||
| 201 | typedef struct |
||
| 202 | { |
||
| 203 | uint32_t ClearInputState; /*!< TIM clear Input state |
||
| 204 | This parameter can be ENABLE or DISABLE */ |
||
| 205 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
||
| 206 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
||
| 207 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
||
| 208 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
||
| 209 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
||
| 210 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
||
| 211 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
||
| 212 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 213 | }TIM_ClearInputConfigTypeDef; |
||
| 214 | |||
| 215 | /** |
||
| 216 | * @brief TIM Slave configuration Structure definition |
||
| 217 | */ |
||
| 218 | typedef struct { |
||
| 219 | uint32_t SlaveMode; /*!< Slave mode selection |
||
| 220 | This parameter can be a value of @ref TIM_Slave_Mode */ |
||
| 221 | uint32_t InputTrigger; /*!< Input Trigger source |
||
| 222 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
||
| 223 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
||
| 224 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
||
| 225 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
||
| 226 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
||
| 227 | uint32_t TriggerFilter; /*!< Input trigger filter |
||
| 228 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||
| 229 | |||
| 230 | }TIM_SlaveConfigTypeDef; |
||
| 231 | |||
| 232 | /** |
||
| 233 | * @brief HAL State structures definition |
||
| 234 | */ |
||
| 235 | typedef enum |
||
| 236 | { |
||
| 237 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
||
| 238 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
||
| 239 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
||
| 240 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
||
| 241 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
||
| 242 | }HAL_TIM_StateTypeDef; |
||
| 243 | |||
| 244 | /** |
||
| 245 | * @brief HAL Active channel structures definition |
||
| 246 | */ |
||
| 247 | typedef enum |
||
| 248 | { |
||
| 249 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
||
| 250 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
||
| 251 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
||
| 252 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
||
| 253 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
||
| 254 | }HAL_TIM_ActiveChannel; |
||
| 255 | |||
| 256 | /** |
||
| 257 | * @brief TIM Time Base Handle Structure definition |
||
| 258 | */ |
||
| 259 | typedef struct |
||
| 260 | { |
||
| 261 | TIM_TypeDef *Instance; /*!< Register base address */ |
||
| 262 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
||
| 263 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
||
| 264 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
||
| 265 | This array is accessed by a @ref TIM_DMA_Handle_index */ |
||
| 266 | HAL_LockTypeDef Lock; /*!< Locking object */ |
||
| 267 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
||
| 268 | }TIM_HandleTypeDef; |
||
| 269 | |||
| 270 | /** |
||
| 271 | * @} |
||
| 272 | */ |
||
| 273 | |||
| 274 | /* Exported constants --------------------------------------------------------*/ |
||
| 275 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
||
| 276 | * @{ |
||
| 277 | */ |
||
| 278 | |||
| 279 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
||
| 280 | * @{ |
||
| 281 | */ |
||
| 282 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ |
||
| 283 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
||
| 284 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
||
| 285 | /** |
||
| 286 | * @} |
||
| 287 | */ |
||
| 288 | |||
| 289 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
||
| 290 | * @{ |
||
| 291 | */ |
||
| 292 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
||
| 293 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ |
||
| 294 | /** |
||
| 295 | * @} |
||
| 296 | */ |
||
| 297 | |||
| 298 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
||
| 299 | * @{ |
||
| 300 | */ |
||
| 301 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ |
||
| 302 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
||
| 303 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
||
| 304 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
||
| 305 | /** |
||
| 306 | * @} |
||
| 307 | */ |
||
| 308 | |||
| 309 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
||
| 310 | * @{ |
||
| 311 | */ |
||
| 312 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) |
||
| 313 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
||
| 314 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
||
| 315 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
||
| 316 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
||
| 317 | /** |
||
| 318 | * @} |
||
| 319 | */ |
||
| 320 | |||
| 321 | /** @defgroup TIM_ClockDivision TIM ClockDivision |
||
| 322 | * @{ |
||
| 323 | */ |
||
| 324 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) |
||
| 325 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
||
| 326 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
||
| 327 | /** |
||
| 328 | * @} |
||
| 329 | */ |
||
| 330 | |||
| 331 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes |
||
| 332 | * @{ |
||
| 333 | */ |
||
| 334 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000) |
||
| 335 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
||
| 336 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
||
| 337 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
||
| 338 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
||
| 339 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
||
| 340 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
||
| 341 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
||
| 342 | /** |
||
| 343 | * @} |
||
| 344 | */ |
||
| 345 | |||
| 346 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
||
| 347 | * @{ |
||
| 348 | */ |
||
| 349 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) |
||
| 350 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
||
| 351 | /** |
||
| 352 | * @} |
||
| 353 | */ |
||
| 354 | |||
| 355 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
||
| 356 | * @{ |
||
| 357 | */ |
||
| 358 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) |
||
| 359 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
||
| 360 | /** |
||
| 361 | * @} |
||
| 362 | */ |
||
| 363 | |||
| 364 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
||
| 365 | * @{ |
||
| 366 | */ |
||
| 367 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
||
| 368 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) |
||
| 369 | /** |
||
| 370 | * @} |
||
| 371 | */ |
||
| 372 | |||
| 373 | /** @defgroup TIM_Channel TIM Channel |
||
| 374 | * @{ |
||
| 375 | */ |
||
| 376 | #define TIM_CHANNEL_1 ((uint32_t)0x0000) |
||
| 377 | #define TIM_CHANNEL_2 ((uint32_t)0x0004) |
||
| 378 | #define TIM_CHANNEL_3 ((uint32_t)0x0008) |
||
| 379 | #define TIM_CHANNEL_4 ((uint32_t)0x000C) |
||
| 380 | #define TIM_CHANNEL_ALL ((uint32_t)0x0018) |
||
| 381 | /** |
||
| 382 | * @} |
||
| 383 | */ |
||
| 384 | |||
| 385 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
||
| 386 | * @{ |
||
| 387 | */ |
||
| 388 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
||
| 389 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
||
| 390 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
||
| 391 | /** |
||
| 392 | * @} |
||
| 393 | */ |
||
| 394 | |||
| 395 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
||
| 396 | * @{ |
||
| 397 | */ |
||
| 398 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
||
| 399 | connected to IC1, IC2, IC3 or IC4, respectively */ |
||
| 400 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
||
| 401 | connected to IC2, IC1, IC4 or IC3, respectively */ |
||
| 402 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
||
| 403 | /** |
||
| 404 | * @} |
||
| 405 | */ |
||
| 406 | |||
| 407 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
||
| 408 | * @{ |
||
| 409 | */ |
||
| 410 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ |
||
| 411 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
||
| 412 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
||
| 413 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
||
| 414 | /** |
||
| 415 | * @} |
||
| 416 | */ |
||
| 417 | |||
| 418 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
||
| 419 | * @{ |
||
| 420 | */ |
||
| 421 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
||
| 422 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) |
||
| 423 | /** |
||
| 424 | * @} |
||
| 425 | */ |
||
| 426 | |||
| 427 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
||
| 428 | * @{ |
||
| 429 | */ |
||
| 430 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
||
| 431 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
||
| 432 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
||
| 433 | /** |
||
| 434 | * @} |
||
| 435 | */ |
||
| 436 | |||
| 437 | /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition |
||
| 438 | * @{ |
||
| 439 | */ |
||
| 440 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
||
| 441 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
||
| 442 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
||
| 443 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
||
| 444 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
||
| 445 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
||
| 446 | /** |
||
| 447 | * @} |
||
| 448 | */ |
||
| 449 | |||
| 450 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
||
| 451 | * @{ |
||
| 452 | */ |
||
| 453 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
||
| 454 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
||
| 455 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
||
| 456 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
||
| 457 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
||
| 458 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
||
| 459 | /** |
||
| 460 | * @} |
||
| 461 | */ |
||
| 462 | |||
| 463 | /** @defgroup TIM_Event_Source TIM Event Source |
||
| 464 | * @{ |
||
| 465 | */ |
||
| 466 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
||
| 467 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
||
| 468 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
||
| 469 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
||
| 470 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
||
| 471 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
||
| 472 | /** |
||
| 473 | * @} |
||
| 474 | */ |
||
| 475 | |||
| 476 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
||
| 477 | * @{ |
||
| 478 | */ |
||
| 479 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
||
| 480 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
||
| 481 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
||
| 482 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
||
| 483 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
||
| 484 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
||
| 485 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
||
| 486 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
||
| 487 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
||
| 488 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
||
| 489 | /** |
||
| 490 | * @} |
||
| 491 | */ |
||
| 492 | |||
| 493 | /** @defgroup TIM_Clock_Source TIM Clock Source |
||
| 494 | * @{ |
||
| 495 | */ |
||
| 496 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
||
| 497 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
||
| 498 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
||
| 499 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
||
| 500 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
||
| 501 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
||
| 502 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
||
| 503 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
||
| 504 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
||
| 505 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
||
| 506 | /** |
||
| 507 | * @} |
||
| 508 | */ |
||
| 509 | |||
| 510 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
||
| 511 | * @{ |
||
| 512 | */ |
||
| 513 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
||
| 514 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
||
| 515 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
||
| 516 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
||
| 517 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
||
| 518 | /** |
||
| 519 | * @} |
||
| 520 | */ |
||
| 521 | |||
| 522 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
||
| 523 | * @{ |
||
| 524 | */ |
||
| 525 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
||
| 526 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
||
| 527 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
||
| 528 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
||
| 529 | /** |
||
| 530 | * @} |
||
| 531 | */ |
||
| 532 | |||
| 533 | /** @defgroup TIM_ClearInput_Source TIM ClearInput Source |
||
| 534 | * @{ |
||
| 535 | */ |
||
| 536 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) |
||
| 537 | #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) |
||
| 538 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) |
||
| 539 | /** |
||
| 540 | * @} |
||
| 541 | */ |
||
| 542 | |||
| 543 | /** @defgroup TIM_ClearInput_Polarity TIM ClearInput Polarity |
||
| 544 | * @{ |
||
| 545 | */ |
||
| 546 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
||
| 547 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
||
| 548 | /** |
||
| 549 | * @} |
||
| 550 | */ |
||
| 551 | |||
| 552 | /** @defgroup TIM_ClearInput_Prescaler TIM ClearInput Prescaler |
||
| 553 | * @{ |
||
| 554 | */ |
||
| 555 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
||
| 556 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
||
| 557 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
||
| 558 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
||
| 559 | /** |
||
| 560 | * @} |
||
| 561 | */ |
||
| 562 | |||
| 563 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state |
||
| 564 | * @{ |
||
| 565 | */ |
||
| 566 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
||
| 567 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000) |
||
| 568 | /** |
||
| 569 | * @} |
||
| 570 | */ |
||
| 571 | |||
| 572 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state |
||
| 573 | * @{ |
||
| 574 | */ |
||
| 575 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
||
| 576 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000) |
||
| 577 | /** |
||
| 578 | * @} |
||
| 579 | */ |
||
| 580 | |||
| 581 | /** @defgroup TIM_Lock_level TIM Lock level |
||
| 582 | * @{ |
||
| 583 | */ |
||
| 584 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) |
||
| 585 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
||
| 586 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
||
| 587 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
||
| 588 | /** |
||
| 589 | * @} |
||
| 590 | */ |
||
| 591 | |||
| 592 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
||
| 593 | * @{ |
||
| 594 | */ |
||
| 595 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
||
| 596 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) |
||
| 597 | /** |
||
| 598 | * @} |
||
| 599 | */ |
||
| 600 | |||
| 601 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
||
| 602 | * @{ |
||
| 603 | */ |
||
| 604 | #define TIM_TRGO_RESET ((uint32_t)0x0000) |
||
| 605 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
||
| 606 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
||
| 607 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
||
| 608 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
||
| 609 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
||
| 610 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
||
| 611 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
||
| 612 | /** |
||
| 613 | * @} |
||
| 614 | */ |
||
| 615 | |||
| 616 | /** @defgroup TIM_Slave_Mode TIM Slave Mode |
||
| 617 | * @{ |
||
| 618 | */ |
||
| 619 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) |
||
| 620 | #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) |
||
| 621 | #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) |
||
| 622 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) |
||
| 623 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) |
||
| 624 | /** |
||
| 625 | * @} |
||
| 626 | */ |
||
| 627 | |||
| 628 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
||
| 629 | * @{ |
||
| 630 | */ |
||
| 631 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
||
| 632 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) |
||
| 633 | /** |
||
| 634 | * @} |
||
| 635 | */ |
||
| 636 | |||
| 637 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
||
| 638 | * @{ |
||
| 639 | */ |
||
| 640 | #define TIM_TS_ITR0 ((uint32_t)0x0000) |
||
| 641 | #define TIM_TS_ITR1 ((uint32_t)0x0010) |
||
| 642 | #define TIM_TS_ITR2 ((uint32_t)0x0020) |
||
| 643 | #define TIM_TS_ITR3 ((uint32_t)0x0030) |
||
| 644 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040) |
||
| 645 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050) |
||
| 646 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060) |
||
| 647 | #define TIM_TS_ETRF ((uint32_t)0x0070) |
||
| 648 | #define TIM_TS_NONE ((uint32_t)0xFFFF) |
||
| 649 | /** |
||
| 650 | * @} |
||
| 651 | */ |
||
| 652 | |||
| 653 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
||
| 654 | * @{ |
||
| 655 | */ |
||
| 656 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
||
| 657 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
||
| 658 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
||
| 659 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
||
| 660 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
||
| 661 | /** |
||
| 662 | * @} |
||
| 663 | */ |
||
| 664 | |||
| 665 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
||
| 666 | * @{ |
||
| 667 | */ |
||
| 668 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
||
| 669 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
||
| 670 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
||
| 671 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
||
| 672 | /** |
||
| 673 | * @} |
||
| 674 | */ |
||
| 675 | |||
| 676 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
||
| 677 | * @{ |
||
| 678 | */ |
||
| 679 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) |
||
| 680 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
||
| 681 | /** |
||
| 682 | * @} |
||
| 683 | */ |
||
| 684 | |||
| 685 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
||
| 686 | * @{ |
||
| 687 | */ |
||
| 688 | #define TIM_DMABASE_CR1 (0x00000000) |
||
| 689 | #define TIM_DMABASE_CR2 (0x00000001) |
||
| 690 | #define TIM_DMABASE_SMCR (0x00000002) |
||
| 691 | #define TIM_DMABASE_DIER (0x00000003) |
||
| 692 | #define TIM_DMABASE_SR (0x00000004) |
||
| 693 | #define TIM_DMABASE_EGR (0x00000005) |
||
| 694 | #define TIM_DMABASE_CCMR1 (0x00000006) |
||
| 695 | #define TIM_DMABASE_CCMR2 (0x00000007) |
||
| 696 | #define TIM_DMABASE_CCER (0x00000008) |
||
| 697 | #define TIM_DMABASE_CNT (0x00000009) |
||
| 698 | #define TIM_DMABASE_PSC (0x0000000A) |
||
| 699 | #define TIM_DMABASE_ARR (0x0000000B) |
||
| 700 | #define TIM_DMABASE_CCR1 (0x0000000D) |
||
| 701 | #define TIM_DMABASE_CCR2 (0x0000000E) |
||
| 702 | #define TIM_DMABASE_CCR3 (0x0000000F) |
||
| 703 | #define TIM_DMABASE_CCR4 (0x00000010) |
||
| 704 | #define TIM_DMABASE_DCR (0x00000012) |
||
| 705 | #define TIM_DMABASE_OR (0x00000013) |
||
| 706 | /** |
||
| 707 | * @} |
||
| 708 | */ |
||
| 709 | |||
| 710 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
||
| 711 | * @{ |
||
| 712 | */ |
||
| 713 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) |
||
| 714 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) |
||
| 715 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) |
||
| 716 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) |
||
| 717 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) |
||
| 718 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) |
||
| 719 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) |
||
| 720 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) |
||
| 721 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) |
||
| 722 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) |
||
| 723 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) |
||
| 724 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) |
||
| 725 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) |
||
| 726 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) |
||
| 727 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) |
||
| 728 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) |
||
| 729 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) |
||
| 730 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) |
||
| 731 | /** |
||
| 732 | * @} |
||
| 733 | */ |
||
| 734 | |||
| 735 | /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index |
||
| 736 | * @{ |
||
| 737 | */ |
||
| 738 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
||
| 739 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
||
| 740 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
||
| 741 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
||
| 742 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
||
| 743 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
||
| 744 | /** |
||
| 745 | * @} |
||
| 746 | */ |
||
| 747 | |||
| 748 | /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State |
||
| 749 | * @{ |
||
| 750 | */ |
||
| 751 | #define TIM_CCx_ENABLE ((uint32_t)0x0001) |
||
| 752 | #define TIM_CCx_DISABLE ((uint32_t)0x0000) |
||
| 753 | /** |
||
| 754 | * @} |
||
| 755 | */ |
||
| 756 | |||
| 757 | /** |
||
| 758 | * @} |
||
| 759 | */ |
||
| 760 | |||
| 761 | /* Private Constants -----------------------------------------------------------*/ |
||
| 762 | /** @defgroup TIM_Private_Constants TIM Private Constants |
||
| 763 | * @{ |
||
| 764 | */ |
||
| 765 | |||
| 766 | /* The counter of a timer instance is disabled only if all the CCx |
||
| 767 | channels have been disabled */ |
||
| 768 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
||
| 769 | /** |
||
| 770 | * @} |
||
| 771 | */ |
||
| 772 | |||
| 773 | /* Private Macros -----------------------------------------------------------*/ |
||
| 774 | /** @defgroup TIM_Private_Macros TIM Private Macros |
||
| 775 | * @{ |
||
| 776 | */ |
||
| 777 | |||
| 778 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
||
| 779 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
||
| 780 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
||
| 781 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
||
| 782 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
||
| 783 | |||
| 784 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
||
| 785 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
||
| 786 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
||
| 787 | |||
| 788 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
||
| 789 | ((MODE) == TIM_OCMODE_PWM2)) |
||
| 790 | |||
| 791 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
||
| 792 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
||
| 793 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
||
| 794 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
||
| 795 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
||
| 796 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
||
| 797 | |||
| 798 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
||
| 799 | ((STATE) == TIM_OCFAST_ENABLE)) |
||
| 800 | |||
| 801 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
||
| 802 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
||
| 803 | |||
| 804 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
||
| 805 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
||
| 806 | |||
| 807 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 808 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 809 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 810 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
||
| 811 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
||
| 812 | |||
| 813 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 814 | ((CHANNEL) == TIM_CHANNEL_2)) |
||
| 815 | |||
| 816 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ |
||
| 817 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ |
||
| 818 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) |
||
| 819 | |||
| 820 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
||
| 821 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
||
| 822 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
||
| 823 | |||
| 824 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
||
| 825 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
||
| 826 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
||
| 827 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
||
| 828 | |||
| 829 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
||
| 830 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
||
| 831 | |||
| 832 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
||
| 833 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
||
| 834 | ((MODE) == TIM_ENCODERMODE_TI12)) |
||
| 835 | |||
| 836 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
||
| 837 | |||
| 838 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
||
| 839 | |||
| 840 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
||
| 841 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
||
| 842 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
||
| 843 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
||
| 844 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
||
| 845 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
||
| 846 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
||
| 847 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
||
| 848 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
||
| 849 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
||
| 850 | |||
| 851 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
||
| 852 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
||
| 853 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
||
| 854 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
||
| 855 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
||
| 856 | |||
| 857 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
||
| 858 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
||
| 859 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
||
| 860 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
||
| 861 | |||
| 862 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
||
| 863 | |||
| 864 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ |
||
| 865 | ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ |
||
| 866 | ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) |
||
| 867 | |||
| 868 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
||
| 869 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
||
| 870 | |||
| 871 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
||
| 872 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
||
| 873 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
||
| 874 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
||
| 875 | |||
| 876 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
||
| 877 | |||
| 878 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
||
| 879 | ((STATE) == TIM_OSSR_DISABLE)) |
||
| 880 | |||
| 881 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
||
| 882 | ((STATE) == TIM_OSSI_DISABLE)) |
||
| 883 | |||
| 884 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
||
| 885 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
||
| 886 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
||
| 887 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
||
| 888 | |||
| 889 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
||
| 890 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
||
| 891 | |||
| 892 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
||
| 893 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
||
| 894 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
||
| 895 | ((SOURCE) == TIM_TRGO_OC1) || \ |
||
| 896 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
||
| 897 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
||
| 898 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
||
| 899 | ((SOURCE) == TIM_TRGO_OC4REF)) |
||
| 900 | |||
| 901 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
||
| 902 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
||
| 903 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
||
| 904 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
||
| 905 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
||
| 906 | |||
| 907 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
||
| 908 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
||
| 909 | |||
| 910 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
||
| 911 | ((SELECTION) == TIM_TS_ITR1) || \ |
||
| 912 | ((SELECTION) == TIM_TS_ITR2) || \ |
||
| 913 | ((SELECTION) == TIM_TS_ITR3) || \ |
||
| 914 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
||
| 915 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
||
| 916 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
||
| 917 | ((SELECTION) == TIM_TS_ETRF)) |
||
| 918 | |||
| 919 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
||
| 920 | ((SELECTION) == TIM_TS_ITR1) || \ |
||
| 921 | ((SELECTION) == TIM_TS_ITR2) || \ |
||
| 922 | ((SELECTION) == TIM_TS_ITR3) || \ |
||
| 923 | ((SELECTION) == TIM_TS_NONE)) |
||
| 924 | |||
| 925 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
||
| 926 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
||
| 927 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
||
| 928 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
||
| 929 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
||
| 930 | |||
| 931 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
||
| 932 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
||
| 933 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
||
| 934 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
||
| 935 | |||
| 936 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
||
| 937 | |||
| 938 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
||
| 939 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
||
| 940 | |||
| 941 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ |
||
| 942 | ((BASE) == TIM_DMABASE_CR2) || \ |
||
| 943 | ((BASE) == TIM_DMABASE_SMCR) || \ |
||
| 944 | ((BASE) == TIM_DMABASE_DIER) || \ |
||
| 945 | ((BASE) == TIM_DMABASE_SR) || \ |
||
| 946 | ((BASE) == TIM_DMABASE_EGR) || \ |
||
| 947 | ((BASE) == TIM_DMABASE_CCMR1) || \ |
||
| 948 | ((BASE) == TIM_DMABASE_CCMR2) || \ |
||
| 949 | ((BASE) == TIM_DMABASE_CCER) || \ |
||
| 950 | ((BASE) == TIM_DMABASE_CNT) || \ |
||
| 951 | ((BASE) == TIM_DMABASE_PSC) || \ |
||
| 952 | ((BASE) == TIM_DMABASE_ARR) || \ |
||
| 953 | ((BASE) == TIM_DMABASE_CCR1) || \ |
||
| 954 | ((BASE) == TIM_DMABASE_CCR2) || \ |
||
| 955 | ((BASE) == TIM_DMABASE_CCR3) || \ |
||
| 956 | ((BASE) == TIM_DMABASE_CCR4) || \ |
||
| 957 | ((BASE) == TIM_DMABASE_DCR) || \ |
||
| 958 | ((BASE) == TIM_DMABASE_OR)) |
||
| 959 | |||
| 960 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
||
| 961 | ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
||
| 962 | ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
||
| 963 | ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
||
| 964 | ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
||
| 965 | ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
||
| 966 | ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
||
| 967 | ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
||
| 968 | ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
||
| 969 | ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
||
| 970 | ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
||
| 971 | ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
||
| 972 | ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
||
| 973 | ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
||
| 974 | ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
||
| 975 | ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
||
| 976 | ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
||
| 977 | ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
||
| 978 | |||
| 979 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
||
| 980 | |||
| 981 | /** @brief Set TIM IC prescaler |
||
| 982 | * @param __HANDLE__: TIM handle |
||
| 983 | * @param __CHANNEL__: specifies TIM Channel |
||
| 984 | * @param __ICPSC__: specifies the prescaler value. |
||
| 985 | * @retval None |
||
| 986 | */ |
||
| 987 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
||
| 988 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
||
| 989 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
||
| 990 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
||
| 991 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
||
| 992 | |||
| 993 | /** @brief Reset TIM IC prescaler |
||
| 994 | * @param __HANDLE__: TIM handle |
||
| 995 | * @param __CHANNEL__: specifies TIM Channel |
||
| 996 | * @retval None |
||
| 997 | */ |
||
| 998 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
||
| 999 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
||
| 1000 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
||
| 1001 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
||
| 1002 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
||
| 1003 | |||
| 1004 | |||
| 1005 | /** @brief Set TIM IC polarity |
||
| 1006 | * @param __HANDLE__: TIM handle |
||
| 1007 | * @param __CHANNEL__: specifies TIM Channel |
||
| 1008 | * @param __POLARITY__: specifies TIM Channel Polarity |
||
| 1009 | * @retval None |
||
| 1010 | */ |
||
| 1011 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
||
| 1012 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
||
| 1013 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ |
||
| 1014 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ |
||
| 1015 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) |
||
| 1016 | |||
| 1017 | /** @brief Reset TIM IC polarity |
||
| 1018 | * @param __HANDLE__: TIM handle |
||
| 1019 | * @param __CHANNEL__: specifies TIM Channel |
||
| 1020 | * @retval None |
||
| 1021 | */ |
||
| 1022 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
||
| 1023 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
||
| 1024 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
||
| 1025 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
||
| 1026 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
||
| 1027 | |||
| 1028 | /** |
||
| 1029 | * @} |
||
| 1030 | */ |
||
| 1031 | |||
| 1032 | /* Private Functions --------------------------------------------------------*/ |
||
| 1033 | |||
| 1034 | /* Exported macros -----------------------------------------------------------*/ |
||
| 1035 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
||
| 1036 | * @{ |
||
| 1037 | */ |
||
| 1038 | |||
| 1039 | /** @brief Reset TIM handle state |
||
| 1040 | * @param __HANDLE__: TIM handle. |
||
| 1041 | * @retval None |
||
| 1042 | */ |
||
| 1043 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
||
| 1044 | |||
| 1045 | /** |
||
| 1046 | * @brief Enable the TIM peripheral. |
||
| 1047 | * @param __HANDLE__: TIM handle |
||
| 1048 | * @retval None |
||
| 1049 | */ |
||
| 1050 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
||
| 1051 | |||
| 1052 | /** |
||
| 1053 | * @brief Disable the TIM peripheral. |
||
| 1054 | * @param __HANDLE__: TIM handle |
||
| 1055 | * @retval None |
||
| 1056 | */ |
||
| 1057 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
||
| 1058 | do { \ |
||
| 1059 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
||
| 1060 | { \ |
||
| 1061 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
||
| 1062 | } \ |
||
| 1063 | } while(0) |
||
| 1064 | |||
| 1065 | /** |
||
| 1066 | * @brief Enables the specified TIM interrupt. |
||
| 1067 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1068 | * @param __INTERRUPT__: specifies the TIM interrupt source to enable. |
||
| 1069 | * This parameter can be one of the following values: |
||
| 1070 | * @arg TIM_IT_UPDATE: Update interrupt |
||
| 1071 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
||
| 1072 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
||
| 1073 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
||
| 1074 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
||
| 1075 | * @arg TIM_IT_COM: Commutation interrupt |
||
| 1076 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
||
| 1077 | * @retval None |
||
| 1078 | */ |
||
| 1079 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
||
| 1080 | |||
| 1081 | /** |
||
| 1082 | * @brief Disables the specified TIM interrupt. |
||
| 1083 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1084 | * @param __INTERRUPT__: specifies the TIM interrupt source to disable. |
||
| 1085 | * This parameter can be one of the following values: |
||
| 1086 | * @arg TIM_IT_UPDATE: Update interrupt |
||
| 1087 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
||
| 1088 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
||
| 1089 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
||
| 1090 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
||
| 1091 | * @arg TIM_IT_COM: Commutation interrupt |
||
| 1092 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
||
| 1093 | * @retval None |
||
| 1094 | */ |
||
| 1095 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
||
| 1096 | |||
| 1097 | /** |
||
| 1098 | * @brief Enables the specified DMA request. |
||
| 1099 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1100 | * @param __DMA__: specifies the TIM DMA request to enable. |
||
| 1101 | * This parameter can be one of the following values: |
||
| 1102 | * @arg TIM_DMA_UPDATE: Update DMA request |
||
| 1103 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
||
| 1104 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
||
| 1105 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
||
| 1106 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
||
| 1107 | * @arg TIM_DMA_COM: Commutation DMA request |
||
| 1108 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
||
| 1109 | * @retval None |
||
| 1110 | */ |
||
| 1111 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
||
| 1112 | |||
| 1113 | /** |
||
| 1114 | * @brief Disables the specified DMA request. |
||
| 1115 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1116 | * @param __DMA__: specifies the TIM DMA request to disable. |
||
| 1117 | * This parameter can be one of the following values: |
||
| 1118 | * @arg TIM_DMA_UPDATE: Update DMA request |
||
| 1119 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
||
| 1120 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
||
| 1121 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
||
| 1122 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
||
| 1123 | * @arg TIM_DMA_COM: Commutation DMA request |
||
| 1124 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
||
| 1125 | * @retval None |
||
| 1126 | */ |
||
| 1127 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
||
| 1128 | |||
| 1129 | /** |
||
| 1130 | * @brief Checks whether the specified TIM interrupt flag is set or not. |
||
| 1131 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1132 | * @param __FLAG__: specifies the TIM interrupt flag to check. |
||
| 1133 | * This parameter can be one of the following values: |
||
| 1134 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
||
| 1135 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
||
| 1136 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
||
| 1137 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
||
| 1138 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
||
| 1139 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
||
| 1140 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
||
| 1141 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
||
| 1142 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
||
| 1143 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
||
| 1144 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
||
| 1145 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
||
| 1146 | */ |
||
| 1147 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
||
| 1148 | |||
| 1149 | /** |
||
| 1150 | * @brief Clears the specified TIM interrupt flag. |
||
| 1151 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1152 | * @param __FLAG__: specifies the TIM interrupt flag to clear. |
||
| 1153 | * This parameter can be one of the following values: |
||
| 1154 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
||
| 1155 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
||
| 1156 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
||
| 1157 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
||
| 1158 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
||
| 1159 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
||
| 1160 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
||
| 1161 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
||
| 1162 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
||
| 1163 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
||
| 1164 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
||
| 1165 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
||
| 1166 | */ |
||
| 1167 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
||
| 1168 | |||
| 1169 | /** |
||
| 1170 | * @brief Checks whether the specified TIM interrupt has occurred or not. |
||
| 1171 | * @param __HANDLE__: TIM handle |
||
| 1172 | * @param __INTERRUPT__: specifies the TIM interrupt source to check. |
||
| 1173 | * @retval The state of TIM_IT (SET or RESET). |
||
| 1174 | */ |
||
| 1175 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||
| 1176 | |||
| 1177 | /** |
||
| 1178 | * @brief Clear the TIM interrupt pending bits |
||
| 1179 | * @param __HANDLE__: TIM handle |
||
| 1180 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
||
| 1181 | * @retval None |
||
| 1182 | */ |
||
| 1183 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
||
| 1184 | |||
| 1185 | /** |
||
| 1186 | * @brief Indicates whether or not the TIM Counter is used as downcounter |
||
| 1187 | * @param __HANDLE__: TIM handle. |
||
| 1188 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
||
| 1189 | * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder |
||
| 1190 | mode. |
||
| 1191 | */ |
||
| 1192 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
||
| 1193 | |||
| 1194 | /** |
||
| 1195 | * @brief Sets the TIM active prescaler register value on update event. |
||
| 1196 | * @param __HANDLE__: TIM handle. |
||
| 1197 | * @param __PRESC__: specifies the active prescaler register new value. |
||
| 1198 | * @retval None |
||
| 1199 | */ |
||
| 1200 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
||
| 1201 | |||
| 1202 | /** |
||
| 1203 | * @brief Sets the TIM Capture Compare Register value on runtime without |
||
| 1204 | * calling another time ConfigChannel function. |
||
| 1205 | * @param __HANDLE__: TIM handle. |
||
| 1206 | * @param __CHANNEL__ : TIM Channels to be configured. |
||
| 1207 | * This parameter can be one of the following values: |
||
| 1208 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
||
| 1209 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
||
| 1210 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
||
| 1211 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
||
| 1212 | * @param __COMPARE__: specifies the Capture Compare register new value. |
||
| 1213 | * @retval None |
||
| 1214 | */ |
||
| 1215 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
||
| 1216 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) |
||
| 1217 | |||
| 1218 | /** |
||
| 1219 | * @brief Gets the TIM Capture Compare Register value on runtime |
||
| 1220 | * @param __HANDLE__: TIM handle. |
||
| 1221 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
||
| 1222 | * This parameter can be one of the following values: |
||
| 1223 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
||
| 1224 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
||
| 1225 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
||
| 1226 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
||
| 1227 | * @retval None |
||
| 1228 | */ |
||
| 1229 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
||
| 1230 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) |
||
| 1231 | |||
| 1232 | /** |
||
| 1233 | * @brief Sets the TIM Counter Register value on runtime. |
||
| 1234 | * @param __HANDLE__: TIM handle. |
||
| 1235 | * @param __COUNTER__: specifies the Counter register new value. |
||
| 1236 | * @retval None |
||
| 1237 | */ |
||
| 1238 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
||
| 1239 | |||
| 1240 | /** |
||
| 1241 | * @brief Gets the TIM Counter Register value on runtime. |
||
| 1242 | * @param __HANDLE__: TIM handle. |
||
| 1243 | * @retval None |
||
| 1244 | */ |
||
| 1245 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ |
||
| 1246 | ((__HANDLE__)->Instance->CNT) |
||
| 1247 | |||
| 1248 | /** |
||
| 1249 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
||
| 1250 | * another time any Init function. |
||
| 1251 | * @param __HANDLE__: TIM handle. |
||
| 1252 | * @param __AUTORELOAD__: specifies the Counter register new value. |
||
| 1253 | * @retval None |
||
| 1254 | */ |
||
| 1255 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
||
| 1256 | do{ \ |
||
| 1257 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
||
| 1258 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
||
| 1259 | } while(0) |
||
| 1260 | |||
| 1261 | /** |
||
| 1262 | * @brief Gets the TIM Autoreload Register value on runtime |
||
| 1263 | * @param __HANDLE__: TIM handle. |
||
| 1264 | * @retval None |
||
| 1265 | */ |
||
| 1266 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ |
||
| 1267 | ((__HANDLE__)->Instance->ARR) |
||
| 1268 | |||
| 1269 | /** |
||
| 1270 | * @brief Sets the TIM Clock Division value on runtime without calling |
||
| 1271 | * another time any Init function. |
||
| 1272 | * @param __HANDLE__: TIM handle. |
||
| 1273 | * @param __CKD__: specifies the clock division value. |
||
| 1274 | * This parameter can be one of the following value: |
||
| 1275 | * @arg TIM_CLOCKDIVISION_DIV1 |
||
| 1276 | * @arg TIM_CLOCKDIVISION_DIV2 |
||
| 1277 | * @arg TIM_CLOCKDIVISION_DIV4 |
||
| 1278 | * @retval None |
||
| 1279 | */ |
||
| 1280 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
||
| 1281 | do{ \ |
||
| 1282 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
||
| 1283 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
||
| 1284 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
||
| 1285 | } while(0) |
||
| 1286 | |||
| 1287 | /** |
||
| 1288 | * @brief Gets the TIM Clock Division value on runtime |
||
| 1289 | * @param __HANDLE__: TIM handle. |
||
| 1290 | * @retval None |
||
| 1291 | */ |
||
| 1292 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ |
||
| 1293 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
||
| 1294 | |||
| 1295 | /** |
||
| 1296 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
||
| 1297 | * another time HAL_TIM_IC_ConfigChannel() function. |
||
| 1298 | * @param __HANDLE__: TIM handle. |
||
| 1299 | * @param __CHANNEL__ : TIM Channels to be configured. |
||
| 1300 | * This parameter can be one of the following values: |
||
| 1301 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
||
| 1302 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
||
| 1303 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
||
| 1304 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
||
| 1305 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
||
| 1306 | * This parameter can be one of the following values: |
||
| 1307 | * @arg TIM_ICPSC_DIV1: no prescaler |
||
| 1308 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
||
| 1309 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
||
| 1310 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
||
| 1311 | * @retval None |
||
| 1312 | */ |
||
| 1313 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
||
| 1314 | do{ \ |
||
| 1315 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
||
| 1316 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
||
| 1317 | } while(0) |
||
| 1318 | |||
| 1319 | /** |
||
| 1320 | * @brief Gets the TIM Input Capture prescaler on runtime |
||
| 1321 | * @param __HANDLE__: TIM handle. |
||
| 1322 | * @param __CHANNEL__ : TIM Channels to be configured. |
||
| 1323 | * This parameter can be one of the following values: |
||
| 1324 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
||
| 1325 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
||
| 1326 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
||
| 1327 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
||
| 1328 | * @retval None |
||
| 1329 | */ |
||
| 1330 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
||
| 1331 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
||
| 1332 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
||
| 1333 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
||
| 1334 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
||
| 1335 | |||
| 1336 | /** |
||
| 1337 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register |
||
| 1338 | * @param __HANDLE__: TIM handle. |
||
| 1339 | * @note When the USR bit of the TIMx_CR1 register is set, only counter |
||
| 1340 | * overflow/underflow generates an update interrupt or DMA request (if |
||
| 1341 | * enabled) |
||
| 1342 | * @retval None |
||
| 1343 | */ |
||
| 1344 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
||
| 1345 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
||
| 1346 | |||
| 1347 | /** |
||
| 1348 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register |
||
| 1349 | * @param __HANDLE__: TIM handle. |
||
| 1350 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the |
||
| 1351 | * following events generate an update interrupt or DMA request (if |
||
| 1352 | * enabled): |
||
| 1353 | * (+) Counter overflow/underflow |
||
| 1354 | * (+) Setting the UG bit |
||
| 1355 | * (+) Update generation through the slave mode controller |
||
| 1356 | * @retval None |
||
| 1357 | */ |
||
| 1358 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
||
| 1359 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
||
| 1360 | |||
| 1361 | /** |
||
| 1362 | * @brief Sets the TIM Capture x input polarity on runtime. |
||
| 1363 | * @param __HANDLE__: TIM handle. |
||
| 1364 | * @param __CHANNEL__: TIM Channels to be configured. |
||
| 1365 | * This parameter can be one of the following values: |
||
| 1366 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
||
| 1367 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
||
| 1368 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
||
| 1369 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
||
| 1370 | * @param __POLARITY__: Polarity for TIx source |
||
| 1371 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
||
| 1372 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
||
| 1373 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
||
| 1374 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
||
| 1375 | * @retval None |
||
| 1376 | */ |
||
| 1377 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
||
| 1378 | do{ \ |
||
| 1379 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
||
| 1380 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
||
| 1381 | }while(0) |
||
| 1382 | |||
| 1383 | /** |
||
| 1384 | * @} |
||
| 1385 | */ |
||
| 1386 | |||
| 1387 | /* Include TIM HAL Extension module */ |
||
| 1388 | #include "stm32l1xx_hal_tim_ex.h" |
||
| 1389 | |||
| 1390 | /* Exported functions --------------------------------------------------------*/ |
||
| 1391 | /** @addtogroup TIM_Exported_Functions |
||
| 1392 | * @{ |
||
| 1393 | */ |
||
| 1394 | |||
| 1395 | /** @addtogroup TIM_Exported_Functions_Group1 |
||
| 1396 | * @{ |
||
| 1397 | */ |
||
| 1398 | /* Time Base functions ********************************************************/ |
||
| 1399 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
||
| 1400 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
||
| 1401 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
||
| 1402 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1403 | /* Blocking mode: Polling */ |
||
| 1404 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
||
| 1405 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
||
| 1406 | /* Non-Blocking mode: Interrupt */ |
||
| 1407 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
||
| 1408 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
||
| 1409 | /* Non-Blocking mode: DMA */ |
||
| 1410 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
||
| 1411 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
||
| 1412 | /** |
||
| 1413 | * @} |
||
| 1414 | */ |
||
| 1415 | |||
| 1416 | /** @addtogroup TIM_Exported_Functions_Group2 |
||
| 1417 | * @{ |
||
| 1418 | */ |
||
| 1419 | /* Timer Output Compare functions **********************************************/ |
||
| 1420 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
||
| 1421 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
||
| 1422 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
||
| 1423 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1424 | /* Blocking mode: Polling */ |
||
| 1425 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1426 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1427 | /* Non-Blocking mode: Interrupt */ |
||
| 1428 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1429 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1430 | /* Non-Blocking mode: DMA */ |
||
| 1431 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||
| 1432 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1433 | |||
| 1434 | /** |
||
| 1435 | * @} |
||
| 1436 | */ |
||
| 1437 | |||
| 1438 | /** @addtogroup TIM_Exported_Functions_Group3 |
||
| 1439 | * @{ |
||
| 1440 | */ |
||
| 1441 | /* Timer PWM functions *********************************************************/ |
||
| 1442 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
||
| 1443 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
||
| 1444 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
||
| 1445 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1446 | /* Blocking mode: Polling */ |
||
| 1447 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1448 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1449 | /* Non-Blocking mode: Interrupt */ |
||
| 1450 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1451 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1452 | /* Non-Blocking mode: DMA */ |
||
| 1453 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||
| 1454 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1455 | /** |
||
| 1456 | * @} |
||
| 1457 | */ |
||
| 1458 | |||
| 1459 | /** @addtogroup TIM_Exported_Functions_Group4 |
||
| 1460 | * @{ |
||
| 1461 | */ |
||
| 1462 | /* Timer Input Capture functions ***********************************************/ |
||
| 1463 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
||
| 1464 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
||
| 1465 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
||
| 1466 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1467 | /* Blocking mode: Polling */ |
||
| 1468 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1469 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1470 | /* Non-Blocking mode: Interrupt */ |
||
| 1471 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1472 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1473 | /* Non-Blocking mode: DMA */ |
||
| 1474 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||
| 1475 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1476 | /** |
||
| 1477 | * @} |
||
| 1478 | */ |
||
| 1479 | |||
| 1480 | /** @addtogroup TIM_Exported_Functions_Group5 |
||
| 1481 | * @{ |
||
| 1482 | */ |
||
| 1483 | /* Timer One Pulse functions ***************************************************/ |
||
| 1484 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
||
| 1485 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
||
| 1486 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
||
| 1487 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1488 | /* Blocking mode: Polling */ |
||
| 1489 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1490 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1491 | /* Non-Blocking mode: Interrupt */ |
||
| 1492 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1493 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1494 | /** |
||
| 1495 | * @} |
||
| 1496 | */ |
||
| 1497 | |||
| 1498 | /** @addtogroup TIM_Exported_Functions_Group6 |
||
| 1499 | * @{ |
||
| 1500 | */ |
||
| 1501 | /* Timer Encoder functions *****************************************************/ |
||
| 1502 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
||
| 1503 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
||
| 1504 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
||
| 1505 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1506 | /* Blocking mode: Polling */ |
||
| 1507 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1508 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1509 | /* Non-Blocking mode: Interrupt */ |
||
| 1510 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1511 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1512 | /* Non-Blocking mode: DMA */ |
||
| 1513 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
||
| 1514 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1515 | |||
| 1516 | /** |
||
| 1517 | * @} |
||
| 1518 | */ |
||
| 1519 | |||
| 1520 | /** @addtogroup TIM_Exported_Functions_Group7 |
||
| 1521 | * @{ |
||
| 1522 | */ |
||
| 1523 | /* Interrupt Handler functions **********************************************/ |
||
| 1524 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
||
| 1525 | /** |
||
| 1526 | * @} |
||
| 1527 | */ |
||
| 1528 | |||
| 1529 | /** @addtogroup TIM_Exported_Functions_Group8 |
||
| 1530 | * @{ |
||
| 1531 | */ |
||
| 1532 | /* Control functions *********************************************************/ |
||
| 1533 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
||
| 1534 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
||
| 1535 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
||
| 1536 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
||
| 1537 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
||
| 1538 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
||
| 1539 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
||
| 1540 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
||
| 1541 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
||
| 1542 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
||
| 1543 | uint32_t *BurstBuffer, uint32_t BurstLength); |
||
| 1544 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
||
| 1545 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
||
| 1546 | uint32_t *BurstBuffer, uint32_t BurstLength); |
||
| 1547 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
||
| 1548 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
||
| 1549 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1550 | |||
| 1551 | /** |
||
| 1552 | * @} |
||
| 1553 | */ |
||
| 1554 | |||
| 1555 | /** @addtogroup TIM_Exported_Functions_Group9 |
||
| 1556 | * @{ |
||
| 1557 | */ |
||
| 1558 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
||
| 1559 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
||
| 1560 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
||
| 1561 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
||
| 1562 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
||
| 1563 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
||
| 1564 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
||
| 1565 | /** |
||
| 1566 | * @} |
||
| 1567 | */ |
||
| 1568 | |||
| 1569 | /** @addtogroup TIM_Exported_Functions_Group10 |
||
| 1570 | * @{ |
||
| 1571 | */ |
||
| 1572 | /* Peripheral State functions **************************************************/ |
||
| 1573 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
||
| 1574 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
||
| 1575 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
||
| 1576 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
||
| 1577 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
||
| 1578 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
||
| 1579 | |||
| 1580 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
||
| 1581 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
||
| 1582 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
||
| 1583 | |||
| 1584 | /** |
||
| 1585 | * @} |
||
| 1586 | */ |
||
| 1587 | |||
| 1588 | /** |
||
| 1589 | * @} |
||
| 1590 | */ |
||
| 1591 | |||
| 1592 | /** |
||
| 1593 | * @} |
||
| 1594 | */ |
||
| 1595 | |||
| 1596 | /** |
||
| 1597 | * @} |
||
| 1598 | */ |
||
| 1599 | |||
| 1600 | #ifdef __cplusplus |
||
| 1601 | } |
||
| 1602 | #endif |
||
| 1603 | |||
| 1604 | #endif /* __STM32L1xx_HAL_TIM_H */ |
||
| 1605 | |||
| 1606 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |