WebSVN – EngineBay2 – Blame – /trunk/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l1xx_hal_rcc.h
		4	* @author MCD Application Team
		5	* @brief Header file of RCC HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
28	mjames	9	* <h2><center>© Copyright(c) 2017 STMicroelectronics.
		10	* All rights reserved.</center></h2>
2	mjames	11	*
28	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
2	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32L1xx_HAL_RCC_H
		22	#define __STM32L1xx_HAL_RCC_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32l1xx_hal_def.h"
		30
		31	/** @addtogroup STM32L1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup RCC
		36	* @{
		37	*/
		38
		39	/** @addtogroup RCC_Private_Constants
		40	* @{
		41	*/
		42
		43	/** @defgroup RCC_Timeout RCC Timeout
		44	* @{
28	mjames	45	*/
		46
2	mjames	47	/* Disable Backup domain write protection state change timeout */
		48	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
		49	/* LSE state change timeout */
		50	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
		51	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
		52	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
28	mjames	53	#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
		54	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
		55	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
		56	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
2	mjames	57	/**
		58	* @}
		59	*/
28	mjames	60
2	mjames	61	/** @defgroup RCC_Register_Offset Register offsets
		62	* @{
		63	*/
		64	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
		65	#define RCC_CR_OFFSET 0x00
		66	#define RCC_CFGR_OFFSET 0x08
		67	#define RCC_CIR_OFFSET 0x0C
		68	#define RCC_CSR_OFFSET 0x34
		69	/**
		70	* @}
		71	*/
		72
		73	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
		74	* @brief RCC registers bit address in the alias region
		75	* @{
		76	*/
		77	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
		78	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
		79	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
		80	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
		81
		82	/* --- CR Register ---*/
		83	/* Alias word address of HSION bit */
28	mjames	84	#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
		85	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
2	mjames	86	/* Alias word address of MSION bit */
28	mjames	87	#define RCC_MSION_BIT_NUMBER RCC_CR_MSION_Pos
		88	#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
2	mjames	89	/* Alias word address of HSEON bit */
28	mjames	90	#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
		91	#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
2	mjames	92	/* Alias word address of CSSON bit */
28	mjames	93	#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
		94	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
2	mjames	95	/* Alias word address of PLLON bit */
28	mjames	96	#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
		97	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
2	mjames	98
		99	/* --- CSR Register ---*/
		100	/* Alias word address of LSION bit */
28	mjames	101	#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
		102	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
2	mjames	103
		104	/* Alias word address of RMVF bit */
28	mjames	105	#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
		106	#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
2	mjames	107
		108	/* Alias word address of LSEON bit */
28	mjames	109	#define RCC_LSEON_BIT_NUMBER RCC_CSR_LSEON_Pos
		110	#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
2	mjames	111
		112	/* Alias word address of LSEON bit */
28	mjames	113	#define RCC_LSEBYP_BIT_NUMBER RCC_CSR_LSEBYP_Pos
		114	#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
2	mjames	115
		116	/* Alias word address of RTCEN bit */
28	mjames	117	#define RCC_RTCEN_BIT_NUMBER RCC_CSR_RTCEN_Pos
		118	#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
2	mjames	119
		120	/* Alias word address of RTCRST bit */
28	mjames	121	#define RCC_RTCRST_BIT_NUMBER RCC_CSR_RTCRST_Pos
		122	#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
2	mjames	123
		124	/**
		125	* @}
		126	*/
28	mjames	127
2	mjames	128	/* CR register byte 2 (Bits[23:16]) base address */
28	mjames	129	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
2	mjames	130
		131	/* CIR register byte 1 (Bits[15:8]) base address */
28	mjames	132	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
2	mjames	133
		134	/* CIR register byte 2 (Bits[23:16]) base address */
28	mjames	135	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
2	mjames	136
		137	/* Defines used for Flags */
28	mjames	138	#define CR_REG_INDEX ((uint8_t)1U)
		139	#define CSR_REG_INDEX ((uint8_t)2U)
2	mjames	140
28	mjames	141	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
2	mjames	142
		143	/**
		144	* @}
		145	*/
		146
		147	/** @addtogroup RCC_Private_Macros
		148	* @{
		149	*/
		150	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
		151	((__SOURCE__) == RCC_PLLSOURCE_HSE))
		152	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
		153	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
		154	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
		155	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
		156	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
		157	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
		158	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
		159	((__HSE__) == RCC_HSE_BYPASS))
		160	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
		161	((__LSE__) == RCC_LSE_BYPASS))
		162	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
28	mjames	163	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
		164	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
2	mjames	165	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
		166	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
		167	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
		168	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
		169	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
		170	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
		171	((__RANGE__) == RCC_MSIRANGE_6))
		172	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
		173	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
		174
		175	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
		176	((__PLL__) == RCC_PLL_ON))
		177	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
		178	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
		179
		180	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
		181	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
		182	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
		183	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
		184	((__MUL__) == RCC_PLL_MUL48))
		185	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
		186	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
		187	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
		188	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
		189	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
		190	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
		191	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
		192	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
		193	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) \|\| \
		194	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
		195	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
		196	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
		197	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
		198	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
		199	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
		200	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
		201	((__HCLK__) == RCC_SYSCLK_DIV512))
		202	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
		203	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
		204	((__PCLK__) == RCC_HCLK_DIV16))
		205	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
		206	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
		207	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
28	mjames	208	((__DIV__) == RCC_MCODIV_16))
2	mjames	209	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
		210	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
		211	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
		212	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
		213	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
		214	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
		215	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
		216	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
		217	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
		218	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
		219	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
		220
		221	/**
		222	* @}
		223	*/
		224
		225	/* Exported types ------------------------------------------------------------*/
		226
		227	/** @defgroup RCC_Exported_Types RCC Exported Types
		228	* @{
		229	*/
		230
28	mjames	231	/**
		232	* @brief RCC PLL configuration structure definition
2	mjames	233	*/
		234	typedef struct
		235	{
		236	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
		237	This parameter can be a value of @ref RCC_PLL_Config */
		238
		239	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
28	mjames	240	This parameter must be a value of @ref RCC_PLL_Clock_Source */
2	mjames	241
		242	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
28	mjames	243	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
2	mjames	244
		245	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
28	mjames	246	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
2	mjames	247	} RCC_PLLInitTypeDef;
28	mjames	248
2	mjames	249	/**
28	mjames	250	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
2	mjames	251	*/
		252	typedef struct
		253	{
		254	uint32_t OscillatorType; /*!< The oscillators to be configured.
		255	This parameter can be a value of @ref RCC_Oscillator_Type */
		256
		257	uint32_t HSEState; /*!< The new state of the HSE.
		258	This parameter can be a value of @ref RCC_HSE_Config */
		259
		260	uint32_t LSEState; /*!< The new state of the LSE.
		261	This parameter can be a value of @ref RCC_LSE_Config */
		262
		263	uint32_t HSIState; /*!< The new state of the HSI.
		264	This parameter can be a value of @ref RCC_HSI_Config */
		265
		266	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
28	mjames	267	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
2	mjames	268
		269	uint32_t LSIState; /*!< The new state of the LSI.
		270	This parameter can be a value of @ref RCC_LSI_Config */
		271
		272	uint32_t MSIState; /*!< The new state of the MSI.
		273	This parameter can be a value of @ref RCC_MSI_Config */
		274
		275	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
28	mjames	276	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
2	mjames	277
		278	uint32_t MSIClockRange; /*!< The MSI frequency range.
		279	This parameter can be a value of @ref RCC_MSI_Clock_Range */
		280
28	mjames	281	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
2	mjames	282
		283	} RCC_OscInitTypeDef;
		284
		285	/**
28	mjames	286	* @brief RCC System, AHB and APB busses clock configuration structure definition
2	mjames	287	*/
		288	typedef struct
		289	{
		290	uint32_t ClockType; /*!< The clock to be configured.
		291	This parameter can be a value of @ref RCC_System_Clock_Type */
		292
		293	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
		294	This parameter can be a value of @ref RCC_System_Clock_Source */
		295
		296	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
		297	This parameter can be a value of @ref RCC_AHB_Clock_Source */
		298
		299	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
		300	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
		301
		302	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
		303	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
		304	} RCC_ClkInitTypeDef;
		305
		306	/**
		307	* @}
		308	*/
		309
		310	/* Exported constants --------------------------------------------------------*/
		311	/** @defgroup RCC_Exported_Constants RCC Exported Constants
		312	* @{
		313	*/
		314
		315	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
		316	* @{
		317	*/
		318
		319	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
		320	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
		321
		322	/**
		323	* @}
		324	*/
		325
		326	/** @defgroup RCC_Oscillator_Type Oscillator Type
		327	* @{
		328	*/
28	mjames	329	#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
		330	#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
		331	#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
		332	#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
		333	#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
		334	#define RCC_OSCILLATORTYPE_MSI (0x00000010U)
2	mjames	335	/**
		336	* @}
		337	*/
		338
		339	/** @defgroup RCC_HSE_Config HSE Config
		340	* @{
		341	*/
28	mjames	342	#define RCC_HSE_OFF (0x00000000U) /!< HSE clock deactivation /
		343	#define RCC_HSE_ON (0x00000001U) /!< HSE clock activation /
		344	#define RCC_HSE_BYPASS (0x00000005U) /!< External clock source for HSE clock /
2	mjames	345	/**
		346	* @}
		347	*/
		348
		349	/** @defgroup RCC_LSE_Config LSE Config
		350	* @{
		351	*/
28	mjames	352	#define RCC_LSE_OFF (0x00000000U) /!< LSE clock deactivation /
		353	#define RCC_LSE_ON (0x00000001U) /!< LSE clock activation /
		354	#define RCC_LSE_BYPASS (0x00000005U) /!< External clock source for LSE clock /
2	mjames	355
		356	/**
		357	* @}
		358	*/
		359
		360	/** @defgroup RCC_HSI_Config HSI Config
		361	* @{
		362	*/
28	mjames	363	#define RCC_HSI_OFF (0x00000000U) /!< HSI clock deactivation /
2	mjames	364	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
		365
28	mjames	366	#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
2	mjames	367
		368	/**
		369	* @}
		370	*/
		371
		372	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
		373	* @{
		374	*/
		375
		376	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
		377	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
		378	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
		379	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
		380	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
		381	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
		382	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
		383
		384	/**
		385	* @}
		386	*/
28	mjames	387
2	mjames	388	/** @defgroup RCC_LSI_Config LSI Config
		389	* @{
		390	*/
28	mjames	391	#define RCC_LSI_OFF (0x00000000U) /!< LSI clock deactivation /
2	mjames	392	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
		393
		394	/**
		395	* @}
		396	*/
		397
		398	/** @defgroup RCC_MSI_Config MSI Config
		399	* @{
		400	*/
28	mjames	401	#define RCC_MSI_OFF (0x00000000U)
		402	#define RCC_MSI_ON (0x00000001U)
2	mjames	403
28	mjames	404	#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */
2	mjames	405
		406	/**
		407	* @}
		408	*/
		409
		410	/** @defgroup RCC_PLL_Config PLL Config
		411	* @{
		412	*/
28	mjames	413	#define RCC_PLL_NONE (0x00000000U) /!< PLL is not configured /
		414	#define RCC_PLL_OFF (0x00000001U) /!< PLL deactivation /
		415	#define RCC_PLL_ON (0x00000002U) /!< PLL activation /
2	mjames	416
		417	/**
		418	* @}
		419	*/
		420
		421	/** @defgroup RCC_System_Clock_Type System Clock Type
		422	* @{
		423	*/
28	mjames	424	#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /!< SYSCLK to configure /
		425	#define RCC_CLOCKTYPE_HCLK (0x00000002U) /!< HCLK to configure /
		426	#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /!< PCLK1 to configure /
		427	#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /!< PCLK2 to configure /
2	mjames	428
		429	/**
		430	* @}
		431	*/
		432
		433	/** @defgroup RCC_System_Clock_Source System Clock Source
		434	* @{
		435	*/
		436	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selected as system clock /
		437	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
		438	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
		439	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
		440
		441	/**
		442	* @}
		443	*/
		444
		445	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
		446	* @{
		447	*/
		448	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
		449	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
		450	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
		451	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
		452
		453	/**
		454	* @}
		455	*/
		456
		457	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
		458	* @{
		459	*/
		460	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
		461	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
		462	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
		463	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
		464	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
		465	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
		466	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
		467	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
		468	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
		469
		470	/**
		471	* @}
		472	*/
28	mjames	473
2	mjames	474	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
		475	* @{
		476	*/
		477	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
		478	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
		479	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
		480	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
		481	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
		482
		483	/**
		484	* @}
		485	*/
		486
		487	/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
		488	* @{
		489	*/
28	mjames	490	#define RCC_RTC_HSE_DIV_2 0x00000000U /!< HSE is divided by 2 for RTC clock /
2	mjames	491	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
		492	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
		493	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
		494	/**
		495	* @}
		496	*/
		497
		498	/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
		499	* @{
		500	*/
28	mjames	501	#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /!< No clock /
2	mjames	502	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
		503	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
		504	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /!< HSE oscillator clock divided by X used as RTC clock /
		505	#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 2 used as RTC clock /
		506	#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 4 used as RTC clock /
		507	#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 8 used as RTC clock /
		508	#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 16 used as RTC clock /
		509	/**
		510	* @}
		511	*/
		512
		513	/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
		514	* @{
		515	*/
		516
		517	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
		518	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
		519	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
		520
		521	/**
		522	* @}
		523	*/
		524
		525	/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
		526	* @{
		527	*/
		528
		529	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
		530	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
		531	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
		532	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
		533	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
		534	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
		535	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
28	mjames	536	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
2	mjames	537	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
		538
		539	/**
		540	* @}
		541	*/
		542
		543	/** @defgroup RCC_MCO_Index MCO Index
		544	* @{
		545	*/
28	mjames	546	#define RCC_MCO1 (0x00000000U)
2	mjames	547	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
		548
		549	/**
		550	* @}
		551	*/
		552
		553	/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
		554	* @{
		555	*/
		556	#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
		557	#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
		558	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
		559	#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
		560	#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
		561
		562	/**
		563	* @}
		564	*/
		565
		566	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
		567	* @{
		568	*/
		569	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
		570	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
		571	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
		572	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
		573	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
		574	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
		575	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
		576	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
		577
		578	/**
		579	* @}
		580	*/
		581	/** @defgroup RCC_Interrupt Interrupts
		582	* @{
		583	*/
		584	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
		585	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
		586	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
		587	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
		588	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
		589	#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /!< MSI Ready Interrupt flag /
		590	#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /!< LSE Clock Security System Interrupt flag /
		591	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
		592	/**
		593	* @}
28	mjames	594	*/
		595
2	mjames	596	/** @defgroup RCC_Flag Flags
		597	* Elements values convention: XXXYYYYYb
		598	* - YYYYY : Flag position in the register
		599	* - XXX : Register index
		600	* - 001: CR register
		601	* - 010: CSR register
		602	* @{
		603	*/
		604	/* Flags in the CR register */
28	mjames	605	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSIRDY_Pos)) /!< Internal High Speed clock ready flag /
		606	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_MSIRDY_Pos)) /!< MSI clock ready flag /
		607	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSERDY_Pos)) /!< External High Speed clock ready flag /
		608	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_PLLRDY_Pos)) /!< PLL clock ready flag /
2	mjames	609
		610	/* Flags in the CSR register */
28	mjames	611	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LSIRDY_Pos)) /!< Internal Low Speed oscillator Ready /
		612	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LSECSSD_Pos)) /!< CSS on LSE failure Detection /
		613	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_OBLRSTF_Pos)) /!< Options bytes loading reset flag /
		614	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PINRSTF_Pos)) /!< PIN reset flag /
		615	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PORRSTF_Pos)) /!< POR/PDR reset flag /
		616	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_SFTRSTF_Pos)) /!< Software Reset flag /
		617	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_IWDGRSTF_Pos)) /!< Independent Watchdog reset flag /
		618	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_WWDGRSTF_Pos)) /!< Window watchdog reset flag /
		619	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LPWRRSTF_Pos)) /!< Low-Power reset flag /
		620	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LSERDY_Pos)) /!< External Low Speed oscillator Ready /
2	mjames	621
		622	/**
		623	* @}
		624	*/
		625
		626	/**
		627	* @}
		628	*/
		629
		630	/* Exported macro ------------------------------------------------------------*/
		631
		632	/** @defgroup RCC_Exported_Macros RCC Exported Macros
		633	* @{
		634	*/
		635
		636	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
		637	* @brief Enable or disable the AHB1 peripheral clock.
		638	* @note After reset, the peripheral clock (used for registers read/write access)
28	mjames	639	* is disabled and the application software has to enable this clock before
		640	* using it.
2	mjames	641	* @{
		642	*/
		643	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
		644	__IO uint32_t tmpreg; \
		645	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
		646	/* Delay after an RCC peripheral clock enabling */\
		647	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
		648	UNUSED(tmpreg); \
28	mjames	649	} while(0U)
2	mjames	650	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
		651	__IO uint32_t tmpreg; \
		652	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
		653	/* Delay after an RCC peripheral clock enabling */\
		654	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
		655	UNUSED(tmpreg); \
28	mjames	656	} while(0U)
2	mjames	657	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
		658	__IO uint32_t tmpreg; \
		659	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
		660	/* Delay after an RCC peripheral clock enabling */\
		661	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
		662	UNUSED(tmpreg); \
28	mjames	663	} while(0U)
2	mjames	664	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
		665	__IO uint32_t tmpreg; \
		666	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
		667	/* Delay after an RCC peripheral clock enabling */\
		668	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
		669	UNUSED(tmpreg); \
28	mjames	670	} while(0U)
2	mjames	671	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
		672	__IO uint32_t tmpreg; \
		673	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
		674	/* Delay after an RCC peripheral clock enabling */\
		675	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
		676	UNUSED(tmpreg); \
28	mjames	677	} while(0U)
2	mjames	678	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
		679	__IO uint32_t tmpreg; \
		680	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
		681	/* Delay after an RCC peripheral clock enabling */\
		682	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
		683	UNUSED(tmpreg); \
28	mjames	684	} while(0U)
2	mjames	685	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
		686	__IO uint32_t tmpreg; \
		687	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
		688	/* Delay after an RCC peripheral clock enabling */\
		689	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
		690	UNUSED(tmpreg); \
28	mjames	691	} while(0U)
2	mjames	692	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
		693	__IO uint32_t tmpreg; \
		694	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
		695	/* Delay after an RCC peripheral clock enabling */\
		696	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
		697	UNUSED(tmpreg); \
28	mjames	698	} while(0U)
2	mjames	699
		700	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
		701	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
		702	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
		703	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
		704	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
		705
		706	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
		707	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
		708	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
		709
		710	/**
		711	* @}
		712	*/
		713
		714	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
		715	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
		716	* @note After reset, the peripheral clock (used for registers read/write access)
28	mjames	717	* is disabled and the application software has to enable this clock before
		718	* using it.
		719	* @{
2	mjames	720	*/
		721	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
		722	__IO uint32_t tmpreg; \
		723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
		724	/* Delay after an RCC peripheral clock enabling */\
		725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
		726	UNUSED(tmpreg); \
28	mjames	727	} while(0U)
2	mjames	728	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
		729	__IO uint32_t tmpreg; \
		730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
		731	/* Delay after an RCC peripheral clock enabling */\
		732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
		733	UNUSED(tmpreg); \
28	mjames	734	} while(0U)
2	mjames	735	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
		736	__IO uint32_t tmpreg; \
		737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
		738	/* Delay after an RCC peripheral clock enabling */\
		739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
		740	UNUSED(tmpreg); \
28	mjames	741	} while(0U)
2	mjames	742	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
		743	__IO uint32_t tmpreg; \
		744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
		745	/* Delay after an RCC peripheral clock enabling */\
		746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
		747	UNUSED(tmpreg); \
28	mjames	748	} while(0U)
2	mjames	749	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
		750	__IO uint32_t tmpreg; \
		751	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
		752	/* Delay after an RCC peripheral clock enabling */\
		753	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
		754	UNUSED(tmpreg); \
28	mjames	755	} while(0U)
2	mjames	756	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
		757	__IO uint32_t tmpreg; \
		758	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
		759	/* Delay after an RCC peripheral clock enabling */\
		760	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
		761	UNUSED(tmpreg); \
28	mjames	762	} while(0U)
2	mjames	763	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
		764	__IO uint32_t tmpreg; \
		765	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
		766	/* Delay after an RCC peripheral clock enabling */\
		767	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
		768	UNUSED(tmpreg); \
28	mjames	769	} while(0U)
2	mjames	770	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
		771	__IO uint32_t tmpreg; \
		772	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
		773	/* Delay after an RCC peripheral clock enabling */\
		774	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
		775	UNUSED(tmpreg); \
28	mjames	776	} while(0U)
2	mjames	777	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
		778	__IO uint32_t tmpreg; \
		779	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
		780	/* Delay after an RCC peripheral clock enabling */\
		781	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
		782	UNUSED(tmpreg); \
28	mjames	783	} while(0U)
2	mjames	784	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
		785	__IO uint32_t tmpreg; \
		786	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
		787	/* Delay after an RCC peripheral clock enabling */\
		788	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
		789	UNUSED(tmpreg); \
28	mjames	790	} while(0U)
2	mjames	791	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
		792	__IO uint32_t tmpreg; \
		793	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
		794	/* Delay after an RCC peripheral clock enabling */\
		795	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
		796	UNUSED(tmpreg); \
28	mjames	797	} while(0U)
2	mjames	798	#define __HAL_RCC_USB_CLK_ENABLE() do { \
		799	__IO uint32_t tmpreg; \
		800	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
		801	/* Delay after an RCC peripheral clock enabling */\
		802	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
		803	UNUSED(tmpreg); \
28	mjames	804	} while(0U)
2	mjames	805	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
		806	__IO uint32_t tmpreg; \
		807	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
		808	/* Delay after an RCC peripheral clock enabling */\
		809	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
		810	UNUSED(tmpreg); \
28	mjames	811	} while(0U)
2	mjames	812	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
		813	__IO uint32_t tmpreg; \
		814	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
		815	/* Delay after an RCC peripheral clock enabling */\
		816	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
		817	UNUSED(tmpreg); \
28	mjames	818	} while(0U)
2	mjames	819	#define __HAL_RCC_COMP_CLK_ENABLE() do { \
		820	__IO uint32_t tmpreg; \
		821	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
		822	/* Delay after an RCC peripheral clock enabling */\
		823	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
		824	UNUSED(tmpreg); \
28	mjames	825	} while(0U)
2	mjames	826
		827
		828	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
		829	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
		830	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
		831	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
		832	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
		833	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
		834	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
		835	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
		836	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
		837	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
		838	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
		839	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
		840	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
		841	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
		842	#define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
		843
		844	/**
		845	* @}
		846	*/
		847
		848	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
		849	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
		850	* @note After reset, the peripheral clock (used for registers read/write access)
28	mjames	851	* is disabled and the application software has to enable this clock before
2	mjames	852	* using it.
		853	* @{
		854	*/
		855	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
		856	__IO uint32_t tmpreg; \
		857	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
		858	/* Delay after an RCC peripheral clock enabling */\
		859	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
		860	UNUSED(tmpreg); \
28	mjames	861	} while(0U)
2	mjames	862	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
		863	__IO uint32_t tmpreg; \
		864	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
		865	/* Delay after an RCC peripheral clock enabling */\
		866	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
		867	UNUSED(tmpreg); \
28	mjames	868	} while(0U)
2	mjames	869	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
		870	__IO uint32_t tmpreg; \
		871	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
		872	/* Delay after an RCC peripheral clock enabling */\
		873	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
		874	UNUSED(tmpreg); \
28	mjames	875	} while(0U)
2	mjames	876	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
		877	__IO uint32_t tmpreg; \
		878	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
		879	/* Delay after an RCC peripheral clock enabling */\
		880	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
		881	UNUSED(tmpreg); \
28	mjames	882	} while(0U)
2	mjames	883	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
		884	__IO uint32_t tmpreg; \
		885	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
		886	/* Delay after an RCC peripheral clock enabling */\
		887	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
		888	UNUSED(tmpreg); \
28	mjames	889	} while(0U)
2	mjames	890	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
		891	__IO uint32_t tmpreg; \
		892	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
		893	/* Delay after an RCC peripheral clock enabling */\
		894	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
		895	UNUSED(tmpreg); \
28	mjames	896	} while(0U)
2	mjames	897	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
		898	__IO uint32_t tmpreg; \
		899	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
		900	/* Delay after an RCC peripheral clock enabling */\
		901	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
		902	UNUSED(tmpreg); \
28	mjames	903	} while(0U)
2	mjames	904
		905	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
		906	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
		907	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
		908	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
		909	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
		910	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
		911	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
		912
		913	/**
		914	* @}
		915	*/
		916
		917	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
		918	* @brief Force or release AHB peripheral reset.
		919	* @{
28	mjames	920	*/
2	mjames	921	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
		922	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
		923	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
		924	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
		925	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
		926	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
		927
		928	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
		929	#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FLITFRST))
		930	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
		931
		932	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
		933	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
		934	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
		935	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
		936	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
		937	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
		938
		939	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
		940	#define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
		941	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
		942
		943	/**
		944	* @}
		945	*/
		946
		947	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
		948	* @brief Force or release APB1 peripheral reset.
28	mjames	949	* @{
2	mjames	950	*/
28	mjames	951	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
2	mjames	952	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
		953	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
		954	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
		955	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
		956	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
		957	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
		958	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
		959	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
		960	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
		961	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
		962	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
		963	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
		964	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
		965	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
		966	#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_COMPRST))
		967
28	mjames	968	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
2	mjames	969	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
		970	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
		971	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
		972	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
		973	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
		974	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
		975	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
		976	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
		977	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
		978	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
		979	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
		980	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
		981	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
		982	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
		983	#define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
		984
		985	/**
		986	* @}
		987	*/
		988
		989	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
		990	* @brief Force or release APB1 peripheral reset.
28	mjames	991	* @{
2	mjames	992	*/
28	mjames	993	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
2	mjames	994	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
		995	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
		996	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
		997	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
		998	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
		999	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
		1000	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
		1001
		1002	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
		1003	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
		1004	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
		1005	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
		1006	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
		1007	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
		1008	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
		1009	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
		1010
		1011	/**
		1012	* @}
		1013	*/
		1014
		1015	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
		1016	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
		1017	* power consumption.
		1018	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
		1019	* @note By default, all peripheral clocks are enabled during SLEEP mode.
		1020	* @{
		1021	*/
		1022	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOALPEN))
		1023	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOBLPEN))
		1024	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOCLPEN))
		1025	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIODLPEN))
		1026	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOHLPEN))
		1027
		1028	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_CRCLPEN))
		1029	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_FLITFLPEN))
		1030	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_DMA1LPEN))
		1031
		1032	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
		1033	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
		1034	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
		1035	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
		1036	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
		1037
		1038	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
		1039	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
		1040	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
		1041
		1042	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
		1043	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
		1044	* power consumption.
		1045	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
		1046	* @note By default, all peripheral clocks are enabled during SLEEP mode.
		1047	*/
		1048	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
		1049	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
		1050	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
		1051	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
		1052	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
		1053	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
		1054	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
		1055	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
		1056	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
		1057	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
		1058	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
		1059	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USBLPEN))
		1060	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
		1061	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
		1062	#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_COMPLPEN))
		1063
		1064	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
		1065	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
		1066	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
		1067	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
		1068	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
		1069	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
		1070	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
		1071	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
		1072	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
		1073	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
		1074	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
		1075	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
		1076	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
		1077	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
		1078	#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
		1079
		1080	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
		1081	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
		1082	* power consumption.
		1083	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
		1084	* @note By default, all peripheral clocks are enabled during SLEEP mode.
		1085	*/
		1086	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
		1087	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
		1088	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
		1089	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
		1090	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
		1091	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
		1092	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
		1093
		1094	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
		1095	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
		1096	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
		1097	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
		1098	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
		1099	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
		1100	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
		1101
		1102	/**
		1103	* @}
		1104	*/
		1105
		1106	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
		1107	* @brief Get the enable or disable status of the AHB peripheral clock.
		1108	* @note After reset, the peripheral clock (used for registers read/write access)
		1109	* is disabled and the application software has to enable this clock before
		1110	* using it.
		1111	* @{
		1112	*/
		1113
28	mjames	1114	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U)
		1115	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U)
		1116	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U)
		1117	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U)
		1118	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U)
		1119	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U)
		1120	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U)
		1121	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U)
		1122	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U)
		1123	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U)
		1124	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U)
		1125	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U)
		1126	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U)
		1127	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U)
		1128	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U)
		1129	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U)
2	mjames	1130
		1131	/**
		1132	* @}
		1133	*/
		1134
		1135	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
		1136	* @brief Get the enable or disable status of the APB1 peripheral clock.
		1137	* @note After reset, the peripheral clock (used for registers read/write access)
		1138	* is disabled and the application software has to enable this clock before
		1139	* using it.
		1140	* @{
		1141	*/
		1142
28	mjames	1143	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U)
		1144	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U)
		1145	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U)
		1146	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U)
		1147	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U)
		1148	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U)
		1149	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U)
		1150	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U)
		1151	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U)
		1152	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U)
		1153	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U)
		1154	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U)
		1155	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U)
		1156	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U)
		1157	#define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U)
		1158	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U)
		1159	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U)
		1160	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U)
		1161	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U)
		1162	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U)
		1163	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U)
		1164	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U)
		1165	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U)
		1166	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U)
		1167	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U)
		1168	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U)
		1169	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U)
		1170	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U)
		1171	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U)
		1172	#define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U)
2	mjames	1173
		1174	/**
		1175	* @}
		1176	*/
		1177
		1178	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
		1179	* @brief Get the enable or disable status of the APB2 peripheral clock.
		1180	* @note After reset, the peripheral clock (used for registers read/write access)
		1181	* is disabled and the application software has to enable this clock before
		1182	* using it.
		1183	* @{
		1184	*/
		1185
28	mjames	1186	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U)
		1187	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U)
		1188	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U)
		1189	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U)
		1190	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U)
		1191	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U)
		1192	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U)
		1193	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U)
		1194	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U)
		1195	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U)
		1196	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U)
		1197	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U)
		1198	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U)
		1199	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U)
		1200
2	mjames	1201	/**
		1202	* @}
		1203	*/
		1204
		1205	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status
		1206	* @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.
		1207	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
		1208	* power consumption.
		1209	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
		1210	* @note By default, all peripheral clocks are enabled during SLEEP mode.
		1211	* @{
		1212	*/
		1213
28	mjames	1214	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U)
		1215	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U)
		1216	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U)
		1217	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U)
		1218	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U)
		1219	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U)
		1220	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U)
		1221	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U)
		1222	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U)
		1223	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U)
		1224	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U)
		1225	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U)
		1226	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U)
		1227	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U)
		1228	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U)
		1229	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U)
2	mjames	1230
		1231	/**
		1232	* @}
		1233	*/
		1234
		1235	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
		1236	* @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
		1237	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
		1238	* power consumption.
		1239	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
		1240	* @note By default, all peripheral clocks are enabled during SLEEP mode.
		1241	* @{
		1242	*/
		1243
28	mjames	1244	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U)
		1245	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U)
		1246	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U)
		1247	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U)
		1248	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U)
		1249	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U)
		1250	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U)
		1251	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U)
		1252	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U)
		1253	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U)
		1254	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U)
		1255	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U)
		1256	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U)
		1257	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U)
		1258	#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U)
		1259	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U)
		1260	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U)
		1261	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U)
		1262	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U)
		1263	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U)
		1264	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U)
		1265	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U)
		1266	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U)
		1267	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U)
		1268	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U)
		1269	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U)
		1270	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U)
		1271	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U)
		1272	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U)
		1273	#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U)
2	mjames	1274
		1275	/**
		1276	* @}
		1277	*/
		1278
		1279	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
		1280	* @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
		1281	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
		1282	* power consumption.
		1283	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
		1284	* @note By default, all peripheral clocks are enabled during SLEEP mode.
		1285	* @{
		1286	*/
		1287
28	mjames	1288	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U)
		1289	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U)
		1290	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U)
		1291	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U)
		1292	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U)
		1293	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
		1294	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
		1295	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U)
		1296	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U)
		1297	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U)
		1298	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U)
		1299	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U)
		1300	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
		1301	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
2	mjames	1302
		1303	/**
		1304	* @}
		1305	*/
		1306
		1307	/** @defgroup RCC_HSI_Configuration HSI Configuration
28	mjames	1308	* @{
2	mjames	1309	*/
		1310
		1311	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
		1312	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
		1313	* @note HSI can not be stopped if it is used as system clock source. In this case,
28	mjames	1314	* you have to select another source of the system clock then stop the HSI.
2	mjames	1315	* @note After enabling the HSI, the application software should wait on HSIRDY
		1316	* flag to be set indicating that HSI clock is stable and can be used as
28	mjames	1317	* system clock source.
2	mjames	1318	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
28	mjames	1319	* clock cycles.
2	mjames	1320	*/
		1321	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
		1322	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
		1323
		1324	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
		1325	* @note The calibration is used to compensate for the variations in voltage
		1326	* and temperature that influence the frequency of the internal HSI RC.
		1327	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
		1328	* (default is RCC_HSICALIBRATION_DEFAULT).
		1329	* This parameter must be a number between 0 and 0x1F.
28	mjames	1330	*/
2	mjames	1331	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
28	mjames	1332	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
2	mjames	1333
		1334	/**
		1335	* @}
		1336	*/
		1337
		1338	/** @defgroup RCC_LSI_Configuration LSI Configuration
28	mjames	1339	* @{
2	mjames	1340	*/
		1341
		1342	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
28	mjames	1343	* @note After enabling the LSI, the application software should wait on
2	mjames	1344	* LSIRDY flag to be set indicating that LSI clock is stable and can
		1345	* be used to clock the IWDG and/or the RTC.
		1346	*/
		1347	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
		1348
		1349	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
28	mjames	1350	* @note LSI can not be disabled if the IWDG is running.
2	mjames	1351	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
28	mjames	1352	* clock cycles.
2	mjames	1353	*/
		1354	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
		1355
		1356	/**
		1357	* @}
		1358	*/
		1359
		1360	/** @defgroup RCC_HSE_Configuration HSE Configuration
28	mjames	1361	* @{
2	mjames	1362	*/
		1363
		1364	/**
		1365	* @brief Macro to configure the External High Speed oscillator (HSE).
		1366	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
		1367	* supported by this macro. User should request a transition to HSE Off
		1368	* first and then HSE On or HSE Bypass.
		1369	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
		1370	* software should wait on HSERDY flag to be set indicating that HSE clock
		1371	* is stable and can be used to clock the PLL and/or system clock.
		1372	* @note HSE state can not be changed if it is used directly or through the
		1373	* PLL as system clock. In this case, you have to select another source
		1374	* of the system clock then change the HSE state (ex. disable it).
		1375	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
		1376	* @note This function reset the CSSON bit, so if the clock security system(CSS)
		1377	* was previously enabled you have to enable it again after calling this
		1378	* function.
		1379	* @param __STATE__ specifies the new state of the HSE.
		1380	* This parameter can be one of the following values:
		1381	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
		1382	* 6 HSE oscillator clock cycles.
		1383	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
		1384	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
		1385	*/
		1386	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
		1387	do{ \
		1388	if ((__STATE__) == RCC_HSE_ON) \
		1389	{ \
		1390	SET_BIT(RCC->CR, RCC_CR_HSEON); \
		1391	} \
		1392	else if ((__STATE__) == RCC_HSE_OFF) \
		1393	{ \
		1394	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
		1395	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
		1396	} \
		1397	else if ((__STATE__) == RCC_HSE_BYPASS) \
		1398	{ \
		1399	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
		1400	SET_BIT(RCC->CR, RCC_CR_HSEON); \
		1401	} \
		1402	else \
		1403	{ \
		1404	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
		1405	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
		1406	} \
28	mjames	1407	}while(0U)
2	mjames	1408
		1409	/**
		1410	* @}
		1411	*/
		1412
		1413	/** @defgroup RCC_LSE_Configuration LSE Configuration
28	mjames	1414	* @{
2	mjames	1415	*/
		1416
		1417	/**
		1418	* @brief Macro to configure the External Low Speed oscillator (LSE).
28	mjames	1419	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
2	mjames	1420	* @note As the LSE is in the Backup domain and write access is denied to
28	mjames	1421	* this domain after reset, you have to enable write access using
2	mjames	1422	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
28	mjames	1423	* (to be done once after reset).
2	mjames	1424	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
		1425	* software should wait on LSERDY flag to be set indicating that LSE clock
		1426	* is stable and can be used to clock the RTC.
		1427	* @param __STATE__ specifies the new state of the LSE.
		1428	* This parameter can be one of the following values:
		1429	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
		1430	* 6 LSE oscillator clock cycles.
		1431	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
		1432	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
		1433	*/
		1434	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
		1435	do{ \
		1436	if ((__STATE__) == RCC_LSE_ON) \
		1437	{ \
		1438	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
		1439	} \
		1440	else if ((__STATE__) == RCC_LSE_OFF) \
		1441	{ \
		1442	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
		1443	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
		1444	} \
		1445	else if ((__STATE__) == RCC_LSE_BYPASS) \
		1446	{ \
		1447	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
		1448	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
		1449	} \
		1450	else \
		1451	{ \
		1452	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
		1453	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
		1454	} \
28	mjames	1455	}while(0U)
2	mjames	1456
		1457	/**
		1458	* @}
		1459	*/
		1460
		1461	/** @defgroup RCC_MSI_Configuration MSI Configuration
28	mjames	1462	* @{
2	mjames	1463	*/
		1464
		1465	/** @brief Macro to enable Internal Multi Speed oscillator (MSI).
		1466	* @note After enabling the MSI, the application software should wait on MSIRDY
		1467	* flag to be set indicating that MSI clock is stable and can be used as
28	mjames	1468	* system clock source.
2	mjames	1469	*/
		1470	#define __HAL_RCC_MSI_ENABLE() ((__IO uint32_t ) RCC_CR_MSION_BB = ENABLE)
28	mjames	1471
2	mjames	1472	/** @brief Macro to disable the Internal Multi Speed oscillator (MSI).
		1473	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
		1474	* It is used (enabled by hardware) as system clock source after startup
		1475	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
		1476	* of the HSE used directly or indirectly as system clock (if the Clock
28	mjames	1477	* Security System CSS is enabled).
2	mjames	1478	* @note MSI can not be stopped if it is used as system clock source. In this case,
28	mjames	1479	* you have to select another source of the system clock then stop the MSI.
2	mjames	1480	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
28	mjames	1481	* clock cycles.
2	mjames	1482	*/
		1483	#define __HAL_RCC_MSI_DISABLE() ((__IO uint32_t ) RCC_CR_MSION_BB = DISABLE)
		1484
		1485	/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
		1486	* @note The calibration is used to compensate for the variations in voltage
		1487	* and temperature that influence the frequency of the internal MSI RC.
		1488	* @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
		1489	* (default is RCC_MSICALIBRATION_DEFAULT).
		1490	* This parameter must be a number between 0 and 0xFF.
28	mjames	1491	*/
2	mjames	1492	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
28	mjames	1493	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
		1494
2	mjames	1495	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
28	mjames	1496	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
2	mjames	1497	* around 2.097 MHz. The MSI clock does not change after wake-up from
		1498	* STOP mode.
28	mjames	1499	* @note The MSI clock range can be modified on the fly.
2	mjames	1500	* @param _MSIRANGEVALUE_ specifies the MSI Clock range.
		1501	* This parameter must be one of the following values:
		1502	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
		1503	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
		1504	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
		1505	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
		1506	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
		1507	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
		1508	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
28	mjames	1509	*/
2	mjames	1510	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
		1511	RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
		1512
		1513	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
		1514	* @retval MSI clock range.
		1515	* This parameter must be one of the following values:
		1516	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
		1517	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
		1518	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
		1519	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
		1520	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
		1521	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
		1522	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
		1523	*/
		1524	#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
		1525
		1526	/**
		1527	* @}
		1528	*/
		1529
		1530	/** @defgroup RCC_PLL_Configuration PLL Configuration
28	mjames	1531	* @{
2	mjames	1532	*/
		1533
		1534	/** @brief Macro to enable the main PLL.
28	mjames	1535	* @note After enabling the main PLL, the application software should wait on
2	mjames	1536	* PLLRDY flag to be set indicating that PLL clock is stable and can
		1537	* be used as system clock source.
		1538	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
		1539	*/
		1540	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
		1541
		1542	/** @brief Macro to disable the main PLL.
		1543	* @note The main PLL can not be disabled if it is used as system clock source
		1544	*/
		1545	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
		1546
		1547	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
		1548	* @note This function must be used only when the main PLL is disabled.
28	mjames	1549	*
2	mjames	1550	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
		1551	* This parameter can be one of the following values:
		1552	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
		1553	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
		1554	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
		1555	* This parameter can be one of the following values:
		1556	* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
		1557	* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
		1558	* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
		1559	* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
		1560	* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
		1561	* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
		1562	* @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24
		1563	* @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32
		1564	* @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48
		1565	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
		1566	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
		1567	* in Range 3.
		1568	*
		1569	* @param __PLLDIV__ specifies the division factor for PLL VCO input clock
		1570	* This parameter can be one of the following values:
		1571	* @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
		1572	* @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
		1573	* @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
28	mjames	1574	*
2	mjames	1575	*/
		1576	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
		1577	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
		1578
		1579	/** @brief Get oscillator clock selected as PLL input clock
		1580	* @retval The clock source used for PLL entry. The returned value can be one
		1581	* of the following:
		1582	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
		1583	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
		1584	*/
		1585	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
		1586
		1587	/**
		1588	* @}
		1589	*/
		1590
		1591	/** @defgroup RCC_Get_Clock_source Get Clock source
28	mjames	1592	* @{
2	mjames	1593	*/
		1594
		1595	/**
		1596	* @brief Macro to configure the system clock source.
		1597	* @param __SYSCLKSOURCE__ specifies the system clock source.
		1598	* This parameter can be one of the following values:
		1599	* @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
		1600	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
		1601	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
		1602	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
		1603	*/
		1604	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
		1605	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
		1606
		1607	/** @brief Macro to get the clock source used as system clock.
		1608	* @retval The clock source used as system clock. The returned value can be one
		1609	* of the following:
		1610	* @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
		1611	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
		1612	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
		1613	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
		1614	*/
		1615	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
		1616
		1617	/**
		1618	* @}
		1619	*/
		1620
		1621	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
28	mjames	1622	* @{
		1623	*/
2	mjames	1624
		1625	/** @brief Macro to configure the MCO clock.
		1626	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
		1627	* This parameter can be one of the following values:
		1628	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
		1629	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
		1630	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
28	mjames	1631	* @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock
2	mjames	1632	* @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
		1633	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock
		1634	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock
		1635	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock
		1636	* @param __MCODIV__ specifies the MCO clock prescaler.
		1637	* This parameter can be one of the following values:
		1638	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
		1639	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
		1640	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
		1641	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
		1642	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
		1643	*/
		1644	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
		1645	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
		1646
		1647	/**
		1648	* @}
		1649	*/
		1650
		1651	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
28	mjames	1652	* @{
2	mjames	1653	*/
		1654
		1655	/** @brief Macro to configure the RTC clock (RTCCLK).
		1656	* @note As the RTC clock configuration bits are in the Backup domain and write
		1657	* access is denied to this domain after reset, you have to enable write
		1658	* access using the Power Backup Access macro before to configure
28	mjames	1659	* the RTC clock source (to be done once after reset).
		1660	* @note Once the RTC clock is configured it cannot be changed unless the
2	mjames	1661	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
		1662	* a Power On Reset (POR).
		1663	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
		1664	*
		1665	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
		1666	* This parameter can be one of the following values:
		1667	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
		1668	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
		1669	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
		1670	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
		1671	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
		1672	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
		1673	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
		1674	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
		1675	* work in STOP and STANDBY modes, and can be used as wakeup source.
		1676	* However, when the HSE clock is used as RTC clock source, the RTC
28	mjames	1677	* cannot be used in STOP and STANDBY modes.
2	mjames	1678	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
		1679	* RTC clock source).
		1680	*/
		1681	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
		1682	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
		1683	{ \
		1684	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
		1685	} \
28	mjames	1686	} while (0U)
2	mjames	1687
		1688	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
		1689	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
		1690	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
28	mjames	1691	} while (0U)
		1692
2	mjames	1693	/** @brief Macro to get the RTC clock source.
		1694	* @retval The clock source can be one of the following values:
		1695	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
		1696	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
		1697	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
		1698	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
		1699	*/
		1700	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
		1701
		1702	/**
		1703	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
		1704	*
		1705	* @retval Returned value can be one of the following values:
		1706	* @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock
		1707	* @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock
		1708	* @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock
		1709	* @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
		1710	*
		1711	*/
28	mjames	1712	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
2	mjames	1713
		1714	/** @brief Macro to enable the the RTC clock.
		1715	* @note These macros must be used only after the RTC clock source was selected.
		1716	*/
		1717	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_CSR_RTCEN_BB = ENABLE)
		1718
		1719	/** @brief Macro to disable the the RTC clock.
		1720	* @note These macros must be used only after the RTC clock source was selected.
		1721	*/
		1722	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_CSR_RTCEN_BB = DISABLE)
		1723
		1724	/** @brief Macro to force the Backup domain reset.
		1725	* @note This function resets the RTC peripheral (including the backup registers)
		1726	* and the RTC clock source selection in RCC_CSR register.
28	mjames	1727	* @note The BKPSRAM is not affected by this reset.
2	mjames	1728	*/
		1729	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_CSR_RTCRST_BB = ENABLE)
		1730
		1731	/** @brief Macros to release the Backup domain reset.
		1732	*/
		1733	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_CSR_RTCRST_BB = DISABLE)
		1734
		1735	/**
		1736	* @}
		1737	*/
		1738
		1739	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
		1740	* @brief macros to manage the specified RCC Flags and interrupts.
		1741	* @{
		1742	*/
		1743
		1744	/** @brief Enable RCC interrupt.
		1745	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
		1746	* This parameter can be any combination of the following values:
		1747	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
		1748	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
		1749	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
		1750	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
		1751	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
		1752	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
		1753	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
		1754	*/
		1755	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
		1756
		1757	/** @brief Disable RCC interrupt.
		1758	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
		1759	* This parameter can be any combination of the following values:
		1760	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
		1761	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
		1762	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
		1763	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
		1764	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
		1765	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
		1766	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
		1767	*/
		1768	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
		1769
		1770	/** @brief Clear the RCC's interrupt pending bits.
		1771	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
		1772	* This parameter can be any combination of the following values:
		1773	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
		1774	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
		1775	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
		1776	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
		1777	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
		1778	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
		1779	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
		1780	* @arg @ref RCC_IT_CSS Clock Security System interrupt
		1781	*/
		1782	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
		1783
		1784	/** @brief Check the RCC's interrupt has occurred or not.
		1785	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
		1786	* This parameter can be one of the following values:
		1787	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
		1788	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
		1789	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
		1790	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
		1791	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
		1792	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
		1793	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB devices)
		1794	* @arg @ref RCC_IT_CSS Clock Security System interrupt
		1795	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
		1796	*/
		1797	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
		1798
		1799	/** @brief Set RMVF bit to clear the reset flags.
		1800	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
		1801	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
		1802	*/
		1803	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
		1804
		1805	/** @brief Check RCC flag is set or not.
		1806	* @param __FLAG__ specifies the flag to check.
		1807	* This parameter can be one of the following values:
		1808	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
		1809	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.
		1810	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
		1811	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
		1812	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
		1813	* @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)
		1814	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
		1815	* @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
		1816	* @arg @ref RCC_FLAG_PINRST Pin reset.
		1817	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
		1818	* @arg @ref RCC_FLAG_SFTRST Software reset.
		1819	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
		1820	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
		1821	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
		1822	* @note (*) This bit is available in high and medium+ density devices only.
		1823	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1824	*/
28	mjames	1825	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
2	mjames	1826
		1827	/**
		1828	* @}
		1829	*/
		1830
		1831	/**
		1832	* @}
		1833	*/
		1834
		1835	/* Include RCC HAL Extension module */
		1836	#include "stm32l1xx_hal_rcc_ex.h"
		1837
		1838	/* Exported functions --------------------------------------------------------*/
		1839	/** @addtogroup RCC_Exported_Functions
		1840	* @{
		1841	*/
		1842
		1843	/** @addtogroup RCC_Exported_Functions_Group1
		1844	* @{
		1845	*/
		1846
		1847	/* Initialization and de-initialization functions ******************************/
28	mjames	1848	HAL_StatusTypeDef HAL_RCC_DeInit(void);
2	mjames	1849	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
		1850	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
		1851
		1852	/**
		1853	* @}
		1854	*/
		1855
		1856	/** @addtogroup RCC_Exported_Functions_Group2
		1857	* @{
		1858	*/
		1859
		1860	/* Peripheral Control functions ************************************************/
		1861	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
		1862	void HAL_RCC_EnableCSS(void);
28	mjames	1863	/* CSS NMI IRQ handler */
		1864	void HAL_RCC_NMI_IRQHandler(void);
		1865	/* User Callbacks in non blocking mode (IT mode) */
		1866	void HAL_RCC_CSSCallback(void);
2	mjames	1867	void HAL_RCC_DisableCSS(void);
		1868	uint32_t HAL_RCC_GetSysClockFreq(void);
		1869	uint32_t HAL_RCC_GetHCLKFreq(void);
		1870	uint32_t HAL_RCC_GetPCLK1Freq(void);
		1871	uint32_t HAL_RCC_GetPCLK2Freq(void);
		1872	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
		1873	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
		1874
		1875	/**
		1876	* @}
		1877	*/
		1878
		1879	/**
		1880	* @}
		1881	*/
		1882
		1883	/**
		1884	* @}
		1885	*/
		1886
		1887	/**
		1888	* @}
		1889	*/
28	mjames	1890
2	mjames	1891	#ifdef __cplusplus
		1892	}
		1893	#endif
		1894
		1895	#endif /* __STM32L1xx_HAL_RCC_H */
		1896
		1897	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
		1898

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(root)/trunk/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h – Rev 28