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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_adc_ex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V1.2.0 |
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| 6 | * @date 01-July-2016 |
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| 7 | * @brief Header file of ADC HAL Extension module. |
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| 8 | ****************************************************************************** |
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| 9 | * @attention |
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| 10 | * |
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| 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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| 12 | * |
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| 13 | * Redistribution and use in source and binary forms, with or without modification, |
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| 14 | * are permitted provided that the following conditions are met: |
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| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 16 | * this list of conditions and the following disclaimer. |
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 18 | * this list of conditions and the following disclaimer in the documentation |
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| 19 | * and/or other materials provided with the distribution. |
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 21 | * may be used to endorse or promote products derived from this software |
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| 22 | * without specific prior written permission. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | ****************************************************************************** |
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| 36 | */ |
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| 37 | |||
| 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 39 | #ifndef __STM32L1xx_HAL_ADC_EX_H |
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| 40 | #define __STM32L1xx_HAL_ADC_EX_H |
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| 41 | |||
| 42 | #ifdef __cplusplus |
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| 43 | extern "C" { |
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| 44 | #endif |
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| 45 | |||
| 46 | /* Includes ------------------------------------------------------------------*/ |
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| 47 | #include "stm32l1xx_hal_def.h" |
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| 48 | |||
| 49 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 50 | * @{ |
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| 51 | */ |
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| 52 | |||
| 53 | /** @addtogroup ADCEx |
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| 54 | * @{ |
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| 55 | */ |
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| 56 | |||
| 57 | /* Exported types ------------------------------------------------------------*/ |
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| 58 | /** @defgroup ADCEx_Exported_Types ADCEx Exported Types |
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| 59 | * @{ |
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| 60 | */ |
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| 61 | |||
| 62 | /** |
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| 63 | * @brief ADC Configuration injected Channel structure definition |
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| 64 | * @note Parameters of this structure are shared within 2 scopes: |
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| 65 | * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset |
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| 66 | * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, |
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| 67 | * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. |
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| 68 | * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. |
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| 69 | * ADC state can be either: |
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| 70 | * - For all parameters: ADC disabled |
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| 71 | * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. |
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| 72 | * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. |
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| 73 | */ |
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| 74 | typedef struct |
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| 75 | { |
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| 76 | uint32_t InjectedChannel; /*!< Selection of ADC channel to configure |
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| 77 | This parameter can be a value of @ref ADC_channels |
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| 78 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
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| 79 | uint32_t InjectedRank; /*!< Rank in the injected group sequencer |
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| 80 | This parameter must be a value of @ref ADCEx_injected_rank |
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| 81 | Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
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| 82 | uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. |
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| 83 | Unit: ADC clock cycles |
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| 84 | Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). |
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| 85 | This parameter can be a value of @ref ADC_sampling_times |
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| 86 | Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
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| 87 | If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
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| 88 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
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| 89 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
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| 90 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ |
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| 91 | uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). |
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| 92 | Offset value must be a positive number. |
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| 93 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
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| 94 | this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
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| 95 | uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. |
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| 96 | To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
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| 97 | This parameter must be a number between Min_Data = 1 and Max_Data = 4. |
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| 98 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 99 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 100 | uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
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| 101 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
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| 102 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
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| 103 | This parameter can be set to ENABLE or DISABLE. |
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| 104 | Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. |
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| 105 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 106 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 107 | uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one |
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| 108 | This parameter can be set to ENABLE or DISABLE. |
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| 109 | Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) |
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| 110 | Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) |
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| 111 | Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. |
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| 112 | To maintain JAUTO always enabled, DMA must be configured in circular mode. |
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| 113 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 114 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 115 | uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. |
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| 116 | If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. |
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| 117 | If set to external trigger source, triggering is on event rising edge. |
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| 118 | This parameter can be a value of @ref ADCEx_External_trigger_source_Injected |
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| 119 | Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). |
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| 120 | If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) |
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| 121 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 122 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 123 | uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. |
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| 124 | This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. |
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| 125 | If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. |
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| 126 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 127 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 128 | }ADC_InjectionConfTypeDef; |
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| 129 | /** |
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| 130 | * @} |
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| 131 | */ |
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| 132 | |||
| 133 | |||
| 134 | /* Exported constants --------------------------------------------------------*/ |
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| 135 | |||
| 136 | /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants |
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| 137 | * @{ |
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| 138 | */ |
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| 139 | |||
| 140 | /** @defgroup ADCEx_injected_rank ADCEx rank into injected group |
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| 141 | * @{ |
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| 142 | */ |
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| 143 | #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) |
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| 144 | #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) |
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| 145 | #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) |
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| 146 | #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) |
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| 147 | /** |
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| 148 | * @} |
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| 149 | */ |
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| 150 | |||
| 151 | /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group |
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| 152 | * @{ |
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| 153 | */ |
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| 154 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) |
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| 155 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) |
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| 156 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) |
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| 157 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) |
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| 158 | /** |
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| 159 | * @} |
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| 160 | */ |
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| 161 | |||
| 162 | /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected |
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| 163 | * @{ |
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| 164 | */ |
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| 165 | /* External triggers for injected groups of ADC1 */ |
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| 166 | #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 |
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| 167 | #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO |
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| 168 | #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 |
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| 169 | #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO |
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| 170 | #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 |
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| 171 | #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 |
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| 172 | #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 |
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| 173 | #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO |
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| 174 | #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 |
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| 175 | #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO |
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| 176 | #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 |
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| 177 | #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 |
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| 178 | #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010) |
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| 179 | /** |
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| 180 | * @} |
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| 181 | */ |
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| 182 | |||
| 183 | /** |
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| 184 | * @} |
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| 185 | */ |
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| 186 | |||
| 187 | |||
| 188 | /* Private constants ---------------------------------------------------------*/ |
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| 189 | |||
| 190 | /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants |
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| 191 | * @{ |
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| 192 | */ |
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| 193 | |||
| 194 | /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected |
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| 195 | * @{ |
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| 196 | */ |
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| 197 | |||
| 198 | /* List of external triggers of injected group for ADC1: */ |
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| 199 | /* (used internally by HAL driver. To not use into HAL structure parameters) */ |
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| 200 | #define ADC_EXTERNALTRIGINJEC_T9_CC1 ((uint32_t) 0x00000000) |
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| 201 | #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) |
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| 202 | #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) |
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| 203 | #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
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| 204 | #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) |
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| 205 | #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
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| 206 | #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) |
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| 207 | #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
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| 208 | #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) |
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| 209 | #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) |
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| 210 | #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) |
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| 211 | #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
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| 212 | /** |
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| 213 | * @} |
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| 214 | */ |
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| 215 | |||
| 216 | /** |
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| 217 | * @} |
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| 218 | */ |
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| 219 | |||
| 220 | |||
| 221 | /* Exported macro ------------------------------------------------------------*/ |
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| 222 | |||
| 223 | /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros |
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| 224 | * @{ |
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| 225 | */ |
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| 226 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
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| 227 | /* final user. */ |
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| 228 | |||
| 229 | /** |
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| 230 | * @brief Selection of channels bank. |
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| 231 | * Note: Banks availability depends on devices categories. |
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| 232 | * This macro is intended to change bank selection quickly on the fly, |
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| 233 | * without going through ADC init structure update and execution of function |
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| 234 | * 'HAL_ADC_Init()'. |
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| 235 | * @param __HANDLE__: ADC handle |
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| 236 | * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. |
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| 237 | * @retval None |
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| 238 | */ |
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| 239 | #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ |
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| 240 | MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) |
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| 241 | |||
| 242 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 243 | /** |
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| 244 | * @brief Configures the ADC channels speed. |
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| 245 | * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. |
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| 246 | * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is |
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| 247 | * in power down mode. |
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| 248 | * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is |
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| 249 | * in power down mode. |
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| 250 | * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in |
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| 251 | * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and |
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| 252 | * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. |
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| 253 | * (Note: OPAMP3 is available on STM32L1 Cat.4 only). |
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| 254 | * @param __CHANNEL__: ADC channel |
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| 255 | * This parameter can be one of the following values: |
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| 256 | * @arg ADC_CHANNEL_3: Channel 3 is selected. |
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| 257 | * @arg ADC_CHANNEL_8: Channel 8 is selected. |
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| 258 | * @arg ADC_CHANNEL_13: Channel 13 is selected. |
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| 259 | * @retval None |
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| 260 | */ |
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| 261 | #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ |
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| 262 | ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ |
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| 263 | )? \ |
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| 264 | (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ |
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| 265 | : \ |
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| 266 | ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ |
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| 267 | )? \ |
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| 268 | (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ |
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| 269 | : \ |
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| 270 | ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ |
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| 271 | )? \ |
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| 272 | (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ |
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| 273 | : \ |
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| 274 | (SET_BIT(COMP->CSR, 0x00000000)) \ |
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| 275 | ) \ |
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| 276 | ) \ |
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| 277 | ) |
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| 278 | |||
| 279 | #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ |
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| 280 | ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ |
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| 281 | )? \ |
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| 282 | (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ |
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| 283 | : \ |
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| 284 | ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ |
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| 285 | )? \ |
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| 286 | (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ |
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| 287 | : \ |
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| 288 | ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ |
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| 289 | )? \ |
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| 290 | (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ |
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| 291 | : \ |
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| 292 | (SET_BIT(COMP->CSR, 0x00000000)) \ |
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| 293 | ) \ |
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| 294 | ) \ |
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| 295 | ) |
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| 296 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 297 | |||
| 298 | /** |
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| 299 | * @} |
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| 300 | */ |
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| 301 | |||
| 302 | /* Private macro ------------------------------------------------------------*/ |
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| 303 | |||
| 304 | /** @defgroup ADCEx_Private_Macro ADCEx Private Macro |
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| 305 | * @{ |
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| 306 | */ |
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| 307 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
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| 308 | /* code of final user. */ |
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| 309 | |||
| 310 | /** |
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| 311 | * @brief Set ADC ranks available in register SQR1. |
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| 312 | * Register SQR1 bits availability depends on device category. |
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| 313 | * @param _NbrOfConversion_: Regular channel sequence length |
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| 314 | * @retval None |
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| 315 | */ |
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| 316 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 317 | #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
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| 318 | #else |
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| 319 | #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
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| 320 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 321 | |||
| 322 | /** |
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| 323 | * @brief Set the ADC's sample time for channel numbers between 30 and 31. |
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| 324 | * Register SMPR0 availability depends on device category. If register is not |
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| 325 | * available on the current device, this macro does nothing. |
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| 326 | * @retval None |
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| 327 | * @param _SAMPLETIME_: Sample time parameter. |
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| 328 | * @param _CHANNELNB_: Channel number. |
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| 329 | * @retval None |
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| 330 | */ |
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| 331 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 332 | #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ |
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| 333 | ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) |
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| 334 | #else |
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| 335 | #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ |
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| 336 | ((uint32_t)0x00000000) |
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| 337 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 338 | |||
| 339 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 340 | /** |
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| 341 | * @brief Set the ADC's sample time for channel numbers between 20 and 29. |
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| 342 | * @param _SAMPLETIME_: Sample time parameter. |
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| 343 | * @param _CHANNELNB_: Channel number. |
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| 344 | * @retval None |
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| 345 | */ |
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| 346 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
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| 347 | ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) |
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| 348 | #else |
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| 349 | /** |
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| 350 | * @brief Set the ADC's sample time for channel numbers between 20 and 26. |
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| 351 | * @param _SAMPLETIME_: Sample time parameter. |
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| 352 | * @param _CHANNELNB_: Channel number. |
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| 353 | * @retval None |
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| 354 | */ |
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| 355 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
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| 356 | ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) |
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| 357 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 358 | |||
| 359 | /** |
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| 360 | * @brief Defines the highest channel available in register SMPR1. Channels |
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| 361 | * availability depends on device category: |
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| 362 | * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 |
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| 363 | * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 |
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| 364 | * @param None |
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| 365 | * @retval None |
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| 366 | */ |
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| 367 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 368 | #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 |
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| 369 | #else |
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| 370 | #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 |
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| 371 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 372 | |||
| 373 | |||
| 374 | /** |
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| 375 | * @brief Define mask of configuration bits of ADC and regular group in |
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| 376 | * register CR2 (bits of ADC enable, conversion start and injected group are |
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| 377 | * excluded of this mask). |
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| 378 | * @retval None |
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| 379 | */ |
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| 380 | #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 381 | #define ADC_CR2_MASK_ADCINIT() \ |
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| 382 | (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) |
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| 383 | #else |
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| 384 | #define ADC_CR2_MASK_ADCINIT() \ |
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| 385 | (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) |
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| 386 | #endif |
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| 387 | |||
| 388 | |||
| 389 | /** |
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| 390 | * @brief Get the maximum ADC conversion cycles on all channels. |
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| 391 | * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) |
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| 392 | * Approximation of sampling time within 2 ranges, returns the highest value: |
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| 393 | * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} |
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| 394 | * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} |
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| 395 | * Unit: ADC clock cycles |
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| 396 | * @param __HANDLE__: ADC handle |
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| 397 | * @retval ADC conversion cycles on all channels |
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| 398 | */ |
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| 399 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 400 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
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| 401 | (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ |
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| 402 | (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
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| 403 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ |
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| 404 | (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ |
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| 405 | \ |
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| 406 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ |
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| 407 | ) |
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| 408 | #else |
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| 409 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
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| 410 | (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ |
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| 411 | (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
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| 412 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ |
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| 413 | \ |
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| 414 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ |
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| 415 | ) |
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| 416 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 417 | |||
| 418 | /** |
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| 419 | * @brief Get the ADC clock prescaler from ADC common control register |
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| 420 | * and convert it to its decimal number setting (refer to reference manual) |
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| 421 | * @retval None |
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| 422 | */ |
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| 423 | #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ |
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| 424 | ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) |
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| 425 | |||
| 426 | /** |
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| 427 | * @brief Clear register SMPR0. |
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| 428 | * Register SMPR0 availability depends on device category. If register is not |
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| 429 | * available on the current device, this macro performs no action. |
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| 430 | * @param __HANDLE__: ADC handle |
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| 431 | * @retval None |
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| 432 | */ |
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| 433 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 434 | #define ADC_SMPR1_CLEAR(__HANDLE__) \ |
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| 435 | CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \ |
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| 436 | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ |
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| 437 | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ |
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| 438 | ADC_SMPR1_SMP20 )) |
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| 439 | |||
| 440 | #define ADC_SMPR0_CLEAR(__HANDLE__) \ |
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| 441 | (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) |
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| 442 | #else |
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| 443 | #define ADC_SMPR1_CLEAR(__HANDLE__) \ |
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| 444 | CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ |
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| 445 | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ |
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| 446 | ADC_SMPR1_SMP20 )) |
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| 447 | |||
| 448 | #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP() |
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| 449 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 450 | |||
| 451 | /** |
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| 452 | * @brief Clear register CR2. |
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| 453 | * @param __HANDLE__: ADC handle |
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| 454 | * @retval None |
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| 455 | */ |
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| 456 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 457 | #define ADC_CR2_CLEAR(__HANDLE__) \ |
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| 458 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ |
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| 459 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ |
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| 460 | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ |
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| 461 | ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ |
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| 462 | ADC_CR2_CONT | ADC_CR2_ADON )) \ |
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| 463 | ) |
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| 464 | #else |
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| 465 | #define ADC_CR2_CLEAR(__HANDLE__) \ |
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| 466 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ |
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| 467 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ |
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| 468 | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ |
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| 469 | ADC_CR2_DMA | ADC_CR2_DELS | \ |
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| 470 | ADC_CR2_CONT | ADC_CR2_ADON )) \ |
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| 471 | ) |
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| 472 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 473 | |||
| 474 | /** |
||
| 475 | * @brief Set the sampling time of selected channel on register SMPR0 |
||
| 476 | * Register SMPR0 availability depends on device category. If register is not |
||
| 477 | * available on the current device, this macro performs no action. |
||
| 478 | * @param __HANDLE__: ADC handle |
||
| 479 | * @param _SAMPLETIME_: Sample time parameter. |
||
| 480 | * @param __CHANNEL__: Channel number. |
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| 481 | * @retval None |
||
| 482 | */ |
||
| 483 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 484 | #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ |
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| 485 | MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ |
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| 486 | ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ |
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| 487 | ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) |
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| 488 | #else |
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| 489 | #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() |
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| 490 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
||
| 491 | |||
| 492 | |||
| 493 | #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ |
||
| 494 | ((CHANNEL) == ADC_INJECTED_RANK_2) || \ |
||
| 495 | ((CHANNEL) == ADC_INJECTED_RANK_3) || \ |
||
| 496 | ((CHANNEL) == ADC_INJECTED_RANK_4) ) |
||
| 497 | |||
| 498 | #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ |
||
| 499 | ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ |
||
| 500 | ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ |
||
| 501 | ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) |
||
| 502 | |||
| 503 | #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ |
||
| 504 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
||
| 505 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ |
||
| 506 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ |
||
| 507 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ |
||
| 508 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ |
||
| 509 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ |
||
| 510 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ |
||
| 511 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ |
||
| 512 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ |
||
| 513 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ |
||
| 514 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ |
||
| 515 | ((REGTRIG) == ADC_SOFTWARE_START) ) |
||
| 516 | |||
| 517 | /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification |
||
| 518 | * @{ |
||
| 519 | */ |
||
| 520 | #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) |
||
| 521 | /** |
||
| 522 | * @} |
||
| 523 | */ |
||
| 524 | |||
| 525 | /** |
||
| 526 | * @} |
||
| 527 | */ |
||
| 528 | |||
| 529 | |||
| 530 | /* Exported functions --------------------------------------------------------*/ |
||
| 531 | /** @addtogroup ADCEx_Exported_Functions |
||
| 532 | * @{ |
||
| 533 | */ |
||
| 534 | |||
| 535 | /* IO operation functions *****************************************************/ |
||
| 536 | /** @addtogroup ADCEx_Exported_Functions_Group1 |
||
| 537 | * @{ |
||
| 538 | */ |
||
| 539 | |||
| 540 | /* Blocking mode: Polling */ |
||
| 541 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); |
||
| 542 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); |
||
| 543 | HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
||
| 544 | |||
| 545 | /* Non-blocking mode: Interruption */ |
||
| 546 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); |
||
| 547 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); |
||
| 548 | |||
| 549 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
||
| 550 | uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); |
||
| 551 | |||
| 552 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ |
||
| 553 | void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); |
||
| 554 | /** |
||
| 555 | * @} |
||
| 556 | */ |
||
| 557 | |||
| 558 | |||
| 559 | /* Peripheral Control functions ***********************************************/ |
||
| 560 | /** @addtogroup ADCEx_Exported_Functions_Group2 |
||
| 561 | * @{ |
||
| 562 | */ |
||
| 563 | |||
| 564 | HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); |
||
| 565 | /** |
||
| 566 | * @} |
||
| 567 | */ |
||
| 568 | |||
| 569 | |||
| 570 | /** |
||
| 571 | * @} |
||
| 572 | */ |
||
| 573 | |||
| 574 | |||
| 575 | /** |
||
| 576 | * @} |
||
| 577 | */ |
||
| 578 | |||
| 579 | /** |
||
| 580 | * @} |
||
| 581 | */ |
||
| 582 | |||
| 583 | #ifdef __cplusplus |
||
| 584 | } |
||
| 585 | #endif |
||
| 586 | |||
| 587 | #endif /* __STM32L1xx_HAL_ADC_EX_H */ |
||
| 588 | |||
| 589 | |||
| 590 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |