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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_utils.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief UTILS LL module driver. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | mjames | 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
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| 2 | mjames | 11 | * |
| 9 | mjames | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 2 | mjames | 16 | * |
| 17 | ****************************************************************************** |
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| 18 | */ |
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| 9 | mjames | 19 | |
| 2 | mjames | 20 | /* Includes ------------------------------------------------------------------*/ |
| 21 | #include "stm32f1xx_ll_rcc.h" |
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| 22 | #include "stm32f1xx_ll_utils.h" |
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| 23 | #include "stm32f1xx_ll_system.h" |
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| 24 | #ifdef USE_FULL_ASSERT |
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| 25 | #include "stm32_assert.h" |
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| 26 | #else |
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| 27 | #define assert_param(expr) ((void)0U) |
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| 28 | #endif |
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| 29 | |||
| 30 | /** @addtogroup STM32F1xx_LL_Driver |
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| 31 | * @{ |
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| 32 | */ |
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| 33 | |||
| 34 | /** @addtogroup UTILS_LL |
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| 35 | * @{ |
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| 36 | */ |
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| 37 | |||
| 38 | /* Private types -------------------------------------------------------------*/ |
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| 39 | /* Private variables ---------------------------------------------------------*/ |
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| 40 | /* Private constants ---------------------------------------------------------*/ |
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| 41 | /** @addtogroup UTILS_LL_Private_Constants |
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| 42 | * @{ |
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| 43 | */ |
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| 44 | |||
| 45 | /* Defines used for PLL range */ |
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| 46 | #define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */ |
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| 47 | |||
| 48 | /* Defines used for HSE range */ |
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| 49 | #define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */ |
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| 50 | #define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */ |
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| 51 | |||
| 52 | /* Defines used for FLASH latency according to HCLK Frequency */ |
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| 53 | #if defined(FLASH_ACR_LATENCY) |
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| 54 | #define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ |
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| 55 | #define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */ |
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| 56 | #else |
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| 9 | mjames | 57 | /*!< No Latency Configuration in this device */ |
| 2 | mjames | 58 | #endif |
| 59 | /** |
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| 60 | * @} |
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| 61 | */ |
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| 62 | /* Private macros ------------------------------------------------------------*/ |
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| 63 | /** @addtogroup UTILS_LL_Private_Macros |
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| 64 | * @{ |
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| 65 | */ |
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| 66 | #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ |
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| 67 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ |
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| 68 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ |
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| 69 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ |
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| 70 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ |
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| 71 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ |
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| 72 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ |
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| 73 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ |
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| 74 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) |
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| 75 | |||
| 76 | #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ |
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| 77 | || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ |
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| 78 | || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ |
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| 79 | || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ |
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| 80 | || ((__VALUE__) == LL_RCC_APB1_DIV_16)) |
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| 81 | |||
| 82 | #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ |
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| 83 | || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ |
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| 84 | || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ |
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| 85 | || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ |
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| 86 | || ((__VALUE__) == LL_RCC_APB2_DIV_16)) |
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| 87 | |||
| 88 | #if defined(RCC_CFGR_PLLMULL6_5) |
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| 89 | #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \ |
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| 90 | || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ |
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| 91 | || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ |
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| 92 | || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ |
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| 93 | || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ |
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| 94 | || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ |
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| 95 | || ((__VALUE__) == LL_RCC_PLL_MUL_6_5)) |
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| 96 | #else |
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| 97 | #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ |
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| 98 | || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ |
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| 99 | || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ |
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| 100 | || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ |
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| 101 | || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ |
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| 102 | || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ |
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| 103 | || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ |
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| 104 | || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ |
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| 105 | || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ |
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| 106 | || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ |
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| 107 | || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ |
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| 108 | || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ |
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| 109 | || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ |
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| 110 | || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ |
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| 111 | || ((__VALUE__) == LL_RCC_PLL_MUL_16)) |
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| 112 | #endif /* RCC_CFGR_PLLMULL6_5 */ |
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| 113 | |||
| 114 | #if defined(RCC_CFGR2_PREDIV1) |
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| 115 | #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ |
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| 116 | ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ |
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| 117 | ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ |
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| 118 | ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ |
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| 119 | ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ |
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| 120 | ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ |
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| 121 | ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ |
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| 122 | ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) |
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| 123 | #else |
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| 124 | #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2)) |
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| 125 | #endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ |
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| 126 | |||
| 127 | #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX) |
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| 128 | |||
| 129 | |||
| 130 | #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ |
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| 131 | || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) |
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| 132 | |||
| 133 | #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) |
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| 134 | /** |
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| 135 | * @} |
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| 136 | */ |
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| 137 | /* Private function prototypes -----------------------------------------------*/ |
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| 138 | /** @defgroup UTILS_LL_Private_Functions UTILS Private functions |
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| 139 | * @{ |
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| 140 | */ |
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| 141 | static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, |
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| 142 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); |
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| 143 | static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); |
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| 144 | static ErrorStatus UTILS_PLL_IsBusy(void); |
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| 145 | /** |
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| 146 | * @} |
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| 147 | */ |
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| 148 | |||
| 149 | /* Exported functions --------------------------------------------------------*/ |
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| 150 | /** @addtogroup UTILS_LL_Exported_Functions |
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| 151 | * @{ |
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| 152 | */ |
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| 153 | |||
| 154 | /** @addtogroup UTILS_LL_EF_DELAY |
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| 155 | * @{ |
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| 156 | */ |
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| 157 | |||
| 158 | /** |
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| 159 | * @brief This function configures the Cortex-M SysTick source to have 1ms time base. |
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| 160 | * @note When a RTOS is used, it is recommended to avoid changing the Systick |
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| 161 | * configuration by calling this function, for a delay use rather osDelay RTOS service. |
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| 162 | * @param HCLKFrequency HCLK frequency in Hz |
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| 163 | * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq |
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| 164 | * @retval None |
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| 165 | */ |
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| 166 | void LL_Init1msTick(uint32_t HCLKFrequency) |
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| 167 | { |
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| 168 | /* Use frequency provided in argument */ |
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| 169 | LL_InitTick(HCLKFrequency, 1000U); |
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| 170 | } |
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| 171 | |||
| 172 | /** |
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| 173 | * @brief This function provides accurate delay (in milliseconds) based |
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| 174 | * on SysTick counter flag |
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| 175 | * @note When a RTOS is used, it is recommended to avoid using blocking delay |
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| 176 | * and use rather osDelay service. |
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| 177 | * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which |
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| 178 | * will configure Systick to 1ms |
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| 179 | * @param Delay specifies the delay time length, in milliseconds. |
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| 180 | * @retval None |
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| 181 | */ |
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| 182 | void LL_mDelay(uint32_t Delay) |
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| 183 | { |
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| 184 | __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ |
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| 185 | /* Add this code to indicate that local variable is not used */ |
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| 186 | ((void)tmp); |
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| 187 | |||
| 188 | /* Add a period to guaranty minimum wait */ |
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| 189 | if (Delay < LL_MAX_DELAY) |
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| 190 | { |
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| 191 | Delay++; |
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| 192 | } |
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| 193 | |||
| 194 | while (Delay) |
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| 195 | { |
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| 196 | if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) |
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| 197 | { |
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| 198 | Delay--; |
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| 199 | } |
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| 200 | } |
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| 201 | } |
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| 202 | |||
| 203 | /** |
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| 204 | * @} |
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| 205 | */ |
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| 206 | |||
| 207 | /** @addtogroup UTILS_EF_SYSTEM |
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| 208 | * @brief System Configuration functions |
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| 209 | * |
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| 210 | @verbatim |
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| 211 | =============================================================================== |
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| 212 | ##### System Configuration functions ##### |
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| 213 | =============================================================================== |
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| 214 | [..] |
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| 215 | System, AHB and APB buses clocks configuration |
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| 216 | |||
| 217 | (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz. |
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| 218 | @endverbatim |
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| 219 | @internal |
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| 220 | Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: |
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| 221 | (++) +-----------------------------------------------+ |
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| 222 | (++) | Latency | SYSCLK clock frequency (MHz) | |
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| 223 | (++) |---------------|-------------------------------| |
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| 224 | (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | |
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| 225 | (++) |---------------|-------------------------------| |
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| 226 | (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | |
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| 227 | (++) |---------------|-------------------------------| |
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| 228 | (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | |
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| 229 | (++) +-----------------------------------------------+ |
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| 230 | @endinternal |
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| 231 | * @{ |
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| 232 | */ |
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| 233 | |||
| 234 | /** |
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| 235 | * @brief This function sets directly SystemCoreClock CMSIS variable. |
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| 236 | * @note Variable can be calculated also through SystemCoreClockUpdate function. |
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| 237 | * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) |
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| 238 | * @retval None |
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| 239 | */ |
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| 240 | void LL_SetSystemCoreClock(uint32_t HCLKFrequency) |
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| 241 | { |
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| 242 | /* HCLK clock frequency */ |
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| 243 | SystemCoreClock = HCLKFrequency; |
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| 244 | } |
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| 245 | |||
| 246 | /** |
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| 9 | mjames | 247 | * @brief Update number of Flash wait states in line with new frequency and current |
| 248 | voltage range. |
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| 249 | * @param Frequency SYSCLK frequency |
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| 250 | * @retval An ErrorStatus enumeration value: |
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| 251 | * - SUCCESS: Latency has been modified |
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| 252 | * - ERROR: Latency cannot be modified |
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| 253 | */ |
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| 254 | #if defined(FLASH_ACR_LATENCY) |
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| 255 | ErrorStatus LL_SetFlashLatency(uint32_t Frequency) |
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| 256 | { |
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| 257 | uint32_t timeout; |
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| 258 | uint32_t getlatency; |
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| 259 | uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ |
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| 260 | ErrorStatus status = SUCCESS; |
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| 261 | |||
| 262 | /* Frequency cannot be equal to 0 */ |
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| 263 | if (Frequency == 0U) |
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| 264 | { |
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| 265 | status = ERROR; |
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| 266 | } |
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| 267 | else |
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| 268 | { |
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| 269 | if (Frequency > UTILS_LATENCY2_FREQ) |
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| 270 | { |
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| 271 | /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */ |
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| 272 | latency = LL_FLASH_LATENCY_2; |
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| 273 | } |
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| 274 | else |
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| 275 | { |
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| 276 | if (Frequency > UTILS_LATENCY1_FREQ) |
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| 277 | { |
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| 278 | /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ |
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| 279 | latency = LL_FLASH_LATENCY_1; |
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| 280 | } |
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| 281 | else |
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| 282 | { |
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| 283 | /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ |
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| 284 | latency = LL_FLASH_LATENCY_0; |
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| 285 | } |
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| 286 | } |
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| 287 | |||
| 288 | if (status != ERROR) |
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| 289 | { |
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| 290 | LL_FLASH_SetLatency(latency); |
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| 291 | |||
| 292 | /* Check that the new number of wait states is taken into account to access the Flash |
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| 293 | memory by reading the FLASH_ACR register */ |
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| 294 | timeout = 2; |
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| 295 | do |
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| 296 | { |
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| 297 | /* Wait for Flash latency to be updated */ |
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| 298 | getlatency = LL_FLASH_GetLatency(); |
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| 299 | timeout--; |
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| 300 | } while ((getlatency != latency) && (timeout > 0)); |
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| 301 | |||
| 302 | if(getlatency != latency) |
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| 303 | { |
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| 304 | status = ERROR; |
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| 305 | } |
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| 306 | else |
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| 307 | { |
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| 308 | status = SUCCESS; |
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| 309 | } |
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| 310 | } |
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| 311 | } |
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| 312 | |||
| 313 | return status; |
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| 314 | } |
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| 315 | #endif /* FLASH_ACR_LATENCY */ |
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| 316 | |||
| 317 | /** |
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| 2 | mjames | 318 | * @brief This function configures system clock with HSI as clock source of the PLL |
| 319 | * @note The application need to ensure that PLL is disabled. |
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| 320 | * @note Function is based on the following formula: |
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| 321 | * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) |
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| 322 | * - PREDIV: Set to 2 for few devices |
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| 9 | mjames | 323 | * - PLLMUL: The application software must set correctly the PLL multiplication factor to |
| 2 | mjames | 324 | * not exceed 72MHz |
| 9 | mjames | 325 | * @note FLASH latency can be modified through this function. |
| 2 | mjames | 326 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| 327 | * the configuration information for the PLL. |
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| 328 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
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| 329 | * the configuration information for the BUS prescalers. |
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| 330 | * @retval An ErrorStatus enumeration value: |
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| 331 | * - SUCCESS: Max frequency configuration done |
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| 332 | * - ERROR: Max frequency configuration not done |
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| 333 | */ |
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| 334 | ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, |
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| 335 | LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
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| 336 | { |
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| 337 | ErrorStatus status = SUCCESS; |
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| 338 | uint32_t pllfreq = 0U; |
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| 339 | |||
| 340 | /* Check if one of the PLL is enabled */ |
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| 341 | if (UTILS_PLL_IsBusy() == SUCCESS) |
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| 342 | { |
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| 343 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
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| 344 | /* Check PREDIV value */ |
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| 345 | assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); |
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| 346 | #else |
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| 347 | /* Force PREDIV value to 2 */ |
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| 348 | UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; |
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| 349 | #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ |
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| 350 | /* Calculate the new PLL output frequency */ |
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| 351 | pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); |
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| 352 | |||
| 353 | /* Enable HSI if not enabled */ |
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| 354 | if (LL_RCC_HSI_IsReady() != 1U) |
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| 355 | { |
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| 356 | LL_RCC_HSI_Enable(); |
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| 357 | while (LL_RCC_HSI_IsReady() != 1U) |
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| 358 | { |
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| 359 | /* Wait for HSI ready */ |
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| 360 | } |
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| 361 | } |
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| 362 | |||
| 363 | /* Configure PLL */ |
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| 364 | LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); |
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| 365 | |||
| 366 | /* Enable PLL and switch system clock to PLL */ |
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| 367 | status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
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| 368 | } |
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| 369 | else |
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| 370 | { |
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| 371 | /* Current PLL configuration cannot be modified */ |
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| 372 | status = ERROR; |
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| 373 | } |
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| 374 | |||
| 375 | return status; |
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| 376 | } |
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| 377 | |||
| 378 | /** |
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| 379 | * @brief This function configures system clock with HSE as clock source of the PLL |
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| 380 | * @note The application need to ensure that PLL is disabled. |
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| 381 | * @note Function is based on the following formula: |
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| 382 | * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) |
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| 383 | * - PREDIV: Set to 2 for few devices |
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| 9 | mjames | 384 | * - PLLMUL: The application software must set correctly the PLL multiplication factor to |
| 2 | mjames | 385 | * not exceed @ref UTILS_PLL_OUTPUT_MAX |
| 9 | mjames | 386 | * @note FLASH latency can be modified through this function. |
| 2 | mjames | 387 | * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX |
| 388 | * @param HSEBypass This parameter can be one of the following values: |
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| 389 | * @arg @ref LL_UTILS_HSEBYPASS_ON |
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| 390 | * @arg @ref LL_UTILS_HSEBYPASS_OFF |
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| 391 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
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| 392 | * the configuration information for the PLL. |
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| 393 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
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| 394 | * the configuration information for the BUS prescalers. |
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| 395 | * @retval An ErrorStatus enumeration value: |
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| 396 | * - SUCCESS: Max frequency configuration done |
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| 397 | * - ERROR: Max frequency configuration not done |
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| 398 | */ |
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| 399 | ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, |
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| 400 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
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| 401 | { |
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| 402 | ErrorStatus status = SUCCESS; |
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| 403 | uint32_t pllfreq = 0U; |
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| 404 | |||
| 405 | /* Check the parameters */ |
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| 406 | assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); |
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| 407 | assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); |
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| 408 | |||
| 409 | /* Check if one of the PLL is enabled */ |
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| 410 | if (UTILS_PLL_IsBusy() == SUCCESS) |
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| 411 | { |
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| 412 | assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); |
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| 413 | |||
| 414 | /* Calculate the new PLL output frequency */ |
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| 415 | pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); |
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| 416 | |||
| 417 | /* Enable HSE if not enabled */ |
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| 418 | if (LL_RCC_HSE_IsReady() != 1U) |
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| 419 | { |
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| 420 | /* Check if need to enable HSE bypass feature or not */ |
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| 421 | if (HSEBypass == LL_UTILS_HSEBYPASS_ON) |
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| 422 | { |
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| 423 | LL_RCC_HSE_EnableBypass(); |
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| 424 | } |
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| 425 | else |
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| 426 | { |
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| 427 | LL_RCC_HSE_DisableBypass(); |
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| 428 | } |
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| 429 | |||
| 430 | /* Enable HSE */ |
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| 431 | LL_RCC_HSE_Enable(); |
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| 432 | while (LL_RCC_HSE_IsReady() != 1U) |
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| 433 | { |
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| 434 | /* Wait for HSE ready */ |
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| 435 | } |
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| 436 | } |
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| 437 | |||
| 9 | mjames | 438 | /* Configure PLL */ |
| 2 | mjames | 439 | LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); |
| 440 | |||
| 441 | /* Enable PLL and switch system clock to PLL */ |
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| 442 | status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
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| 443 | } |
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| 444 | else |
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| 445 | { |
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| 446 | /* Current PLL configuration cannot be modified */ |
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| 447 | status = ERROR; |
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| 448 | } |
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| 449 | |||
| 450 | return status; |
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| 451 | } |
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| 452 | |||
| 453 | /** |
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| 454 | * @} |
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| 455 | */ |
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| 456 | |||
| 457 | /** |
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| 458 | * @} |
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| 459 | */ |
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| 460 | |||
| 461 | /** @addtogroup UTILS_LL_Private_Functions |
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| 462 | * @{ |
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| 463 | */ |
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| 464 | /** |
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| 465 | * @brief Function to check that PLL can be modified |
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| 466 | * @param PLL_InputFrequency PLL input frequency (in Hz) |
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| 467 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
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| 468 | * the configuration information for the PLL. |
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| 469 | * @retval PLL output frequency (in Hz) |
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| 470 | */ |
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| 471 | static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) |
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| 472 | { |
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| 473 | uint32_t pllfreq = 0U; |
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| 474 | |||
| 475 | /* Check the parameters */ |
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| 476 | assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); |
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| 477 | |||
| 478 | /* Check different PLL parameters according to RM */ |
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| 479 | #if defined (RCC_CFGR2_PREDIV1) |
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| 480 | pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); |
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| 481 | #else |
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| 482 | pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul); |
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| 483 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
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| 484 | assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); |
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| 485 | |||
| 486 | return pllfreq; |
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| 487 | } |
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| 488 | |||
| 489 | /** |
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| 490 | * @brief Function to check that PLL can be modified |
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| 491 | * @retval An ErrorStatus enumeration value: |
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| 492 | * - SUCCESS: PLL modification can be done |
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| 493 | * - ERROR: PLL is busy |
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| 494 | */ |
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| 495 | static ErrorStatus UTILS_PLL_IsBusy(void) |
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| 496 | { |
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| 497 | ErrorStatus status = SUCCESS; |
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| 498 | |||
| 499 | /* Check if PLL is busy*/ |
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| 500 | if (LL_RCC_PLL_IsReady() != 0U) |
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| 501 | { |
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| 502 | /* PLL configuration cannot be modified */ |
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| 503 | status = ERROR; |
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| 504 | } |
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| 505 | #if defined(RCC_PLL2_SUPPORT) |
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| 506 | /* Check if PLL2 is busy*/ |
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| 507 | if (LL_RCC_PLL2_IsReady() != 0U) |
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| 508 | { |
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| 509 | /* PLL2 configuration cannot be modified */ |
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| 510 | status = ERROR; |
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| 511 | } |
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| 512 | #endif /* RCC_PLL2_SUPPORT */ |
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| 513 | |||
| 514 | #if defined(RCC_PLLI2S_SUPPORT) |
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| 515 | /* Check if PLLI2S is busy*/ |
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| 516 | if (LL_RCC_PLLI2S_IsReady() != 0U) |
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| 517 | { |
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| 518 | /* PLLI2S configuration cannot be modified */ |
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| 519 | status = ERROR; |
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| 520 | } |
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| 521 | #endif /* RCC_PLLI2S_SUPPORT */ |
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| 522 | |||
| 523 | return status; |
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| 524 | } |
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| 525 | |||
| 526 | /** |
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| 527 | * @brief Function to enable PLL and switch system clock to PLL |
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| 528 | * @param SYSCLK_Frequency SYSCLK frequency |
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| 529 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
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| 530 | * the configuration information for the BUS prescalers. |
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| 531 | * @retval An ErrorStatus enumeration value: |
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| 532 | * - SUCCESS: No problem to switch system to PLL |
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| 533 | * - ERROR: Problem to switch system to PLL |
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| 534 | */ |
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| 535 | static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
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| 536 | { |
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| 537 | ErrorStatus status = SUCCESS; |
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| 538 | #if defined(FLASH_ACR_LATENCY) |
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| 539 | uint32_t sysclk_frequency_current = 0U; |
||
| 540 | #endif /* FLASH_ACR_LATENCY */ |
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| 541 | |||
| 542 | assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); |
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| 543 | assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); |
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| 544 | assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); |
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| 545 | |||
| 546 | #if defined(FLASH_ACR_LATENCY) |
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| 547 | /* Calculate current SYSCLK frequency */ |
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| 548 | sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]); |
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| 549 | #endif /* FLASH_ACR_LATENCY */ |
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| 550 | |||
| 551 | /* Increasing the number of wait states because of higher CPU frequency */ |
||
| 552 | #if defined (FLASH_ACR_LATENCY) |
||
| 553 | if (sysclk_frequency_current < SYSCLK_Frequency) |
||
| 554 | { |
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| 555 | /* Set FLASH latency to highest latency */ |
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| 9 | mjames | 556 | status = LL_SetFlashLatency(SYSCLK_Frequency); |
| 2 | mjames | 557 | } |
| 558 | #endif /* FLASH_ACR_LATENCY */ |
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| 559 | |||
| 560 | /* Update system clock configuration */ |
||
| 561 | if (status == SUCCESS) |
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| 562 | { |
||
| 563 | #if defined(RCC_PLL2_SUPPORT) |
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| 9 | mjames | 564 | if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2) |
| 2 | mjames | 565 | { |
| 9 | mjames | 566 | /* Enable PLL2 */ |
| 567 | LL_RCC_PLL2_Enable(); |
||
| 568 | while (LL_RCC_PLL2_IsReady() != 1U) |
||
| 569 | { |
||
| 570 | /* Wait for PLL2 ready */ |
||
| 571 | } |
||
| 2 | mjames | 572 | } |
| 573 | #endif /* RCC_PLL2_SUPPORT */ |
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| 574 | /* Enable PLL */ |
||
| 575 | LL_RCC_PLL_Enable(); |
||
| 576 | while (LL_RCC_PLL_IsReady() != 1U) |
||
| 577 | { |
||
| 578 | /* Wait for PLL ready */ |
||
| 579 | } |
||
| 580 | |||
| 581 | /* Sysclk activation on the main PLL */ |
||
| 582 | LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); |
||
| 583 | LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); |
||
| 584 | while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) |
||
| 585 | { |
||
| 586 | /* Wait for system clock switch to PLL */ |
||
| 587 | } |
||
| 588 | |||
| 589 | /* Set APB1 & APB2 prescaler*/ |
||
| 590 | LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); |
||
| 591 | LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); |
||
| 592 | } |
||
| 593 | |||
| 594 | /* Decreasing the number of wait states because of lower CPU frequency */ |
||
| 595 | #if defined (FLASH_ACR_LATENCY) |
||
| 596 | if (sysclk_frequency_current > SYSCLK_Frequency) |
||
| 597 | { |
||
| 598 | /* Set FLASH latency to lowest latency */ |
||
| 9 | mjames | 599 | status = LL_SetFlashLatency(SYSCLK_Frequency); |
| 2 | mjames | 600 | } |
| 601 | #endif /* FLASH_ACR_LATENCY */ |
||
| 602 | |||
| 603 | /* Update SystemCoreClock variable */ |
||
| 604 | if (status == SUCCESS) |
||
| 605 | { |
||
| 606 | LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); |
||
| 607 | } |
||
| 608 | |||
| 609 | return status; |
||
| 610 | } |
||
| 611 | |||
| 612 | /** |
||
| 613 | * @} |
||
| 614 | */ |
||
| 615 | |||
| 616 | /** |
||
| 617 | * @} |
||
| 618 | */ |
||
| 619 | |||
| 620 | /** |
||
| 621 | * @} |
||
| 622 | */ |
||
| 623 | |||
| 624 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |