Subversion Repositories AFRtranscoder

Rev

Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
2 mjames 1 
/**
2 
  ******************************************************************************
3 
  * @file    stm32f1xx_ll_tim.c
4 
  * @author  MCD Application Team
5 
  * @brief   TIM LL module driver.
6 
  ******************************************************************************
7 
  * @attention
8 
  *
9 
  * Copyright (c) 2016 STMicroelectronics.
10 
  * All rights reserved.
11 
  *
12 
  * This software is licensed under terms that can be found in the LICENSE file
13 
  * in the root directory of this software component.
14 
  * If no LICENSE file comes with this software, it is provided AS-IS.
15 
  *
16 
  ******************************************************************************
17 
  */
18 
#if defined(USE_FULL_LL_DRIVER)
19 
 
20 
/* Includes ------------------------------------------------------------------*/
21 
#include "stm32f1xx_ll_tim.h"
22 
#include "stm32f1xx_ll_bus.h"
23 
 
24 
#ifdef  USE_FULL_ASSERT
25 
#include "stm32_assert.h"
26 
#else
27 
#define assert_param(expr) ((void)0U)
28 
#endif /* USE_FULL_ASSERT */
29 
 
30 
/** @addtogroup STM32F1xx_LL_Driver
31 
  * @{
32 
  */
33 
 
34 
#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
35 
 
36 
/** @addtogroup TIM_LL
37 
  * @{
38 
  */
39 
 
40 
/* Private types -------------------------------------------------------------*/
41 
/* Private variables ---------------------------------------------------------*/
42 
/* Private constants ---------------------------------------------------------*/
43 
/* Private macros ------------------------------------------------------------*/
44 
/** @addtogroup TIM_LL_Private_Macros
45 
  * @{
46 
  */
47 
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52 
 
53 
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56 
 
57 
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 
                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 
                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 
                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
65 
 
66 
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
67 
                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
68 
 
69 
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
70 
                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
71 
 
72 
#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
73 
                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
74 
 
75 
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
76 
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
77 
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
78 
 
79 
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
80 
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
81 
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
82 
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
83 
 
84 
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
85 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
86 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
87 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
88 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
89 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
90 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
91 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
92 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
93 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
94 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
95 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
96 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
97 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
98 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
99 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
100 
 
101 
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
102 
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
103 
 
104 
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
105 
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
106 
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
107 
 
108 
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
109 
                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
110 
 
111 
#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
112 
                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
113 
 
114 
#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
115 
                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
116 
 
117 
#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
118 
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
119 
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
120 
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
121 
 
122 
#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
123 
                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
124 
 
125 
#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
126 
                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
127 
 
128 
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
129 
                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
130 
/**
131 
  * @}
132 
  */
133 
 
134 
 
135 
/* Private function prototypes -----------------------------------------------*/
136 
/** @defgroup TIM_LL_Private_Functions TIM Private Functions
137 
  * @{
138 
  */
139 
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
140 
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
141 
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
144 
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
145 
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 
/**
148 
  * @}
149 
  */
150 
 
151 
/* Exported functions --------------------------------------------------------*/
152 
/** @addtogroup TIM_LL_Exported_Functions
153 
  * @{
154 
  */
155 
 
156 
/** @addtogroup TIM_LL_EF_Init
157 
  * @{
158 
  */
159 
 
160 
/**
161 
  * @brief  Set TIMx registers to their reset values.
162 
  * @param  TIMx Timer instance
163 
  * @retval An ErrorStatus enumeration value:
164 
  *          - SUCCESS: TIMx registers are de-initialized
165 
  *          - ERROR: invalid TIMx instance
166 
  */
167 
ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
168 
{
169 
  ErrorStatus result = SUCCESS;
170 
 
171 
  /* Check the parameters */
172 
  assert_param(IS_TIM_INSTANCE(TIMx));
173 
 
174 
  if (TIMx == TIM2)
175 
  {
176 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
177 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
178 
  }
179 
#if defined(TIM1)
180 
  else if (TIMx == TIM1)
181 
  {
182 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
183 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
184 
  }
185 
#endif /* TIM1 */
186 
#if defined(TIM3)
187 
  else if (TIMx == TIM3)
188 
  {
189 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
190 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
191 
  }
192 
#endif /* TIM3 */
193 
#if defined(TIM4)
194 
  else if (TIMx == TIM4)
195 
  {
196 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
197 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
198 
  }
199 
#endif /* TIM4 */
200 
#if defined(TIM5)
201 
  else if (TIMx == TIM5)
202 
  {
203 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
204 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
205 
  }
206 
#endif /* TIM5 */
207 
#if defined(TIM6)
208 
  else if (TIMx == TIM6)
209 
  {
210 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
211 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
212 
  }
213 
#endif /* TIM6 */
214 
#if defined (TIM7)
215 
  else if (TIMx == TIM7)
216 
  {
217 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
218 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
219 
  }
220 
#endif /* TIM7 */
221 
#if defined(TIM8)
222 
  else if (TIMx == TIM8)
223 
  {
224 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
225 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
226 
  }
227 
#endif /* TIM8 */
228 
#if defined(TIM9)
229 
  else if (TIMx == TIM9)
230 
  {
231 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
232 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
233 
  }
234 
#endif /* TIM9 */
235 
#if defined(TIM10)
236 
  else if (TIMx == TIM10)
237 
  {
238 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
239 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
240 
  }
241 
#endif /* TIM10 */
242 
#if defined(TIM11)
243 
  else if (TIMx == TIM11)
244 
  {
245 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
246 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
247 
  }
248 
#endif /* TIM11 */
249 
#if defined(TIM12)
250 
  else if (TIMx == TIM12)
251 
  {
252 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
253 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
254 
  }
255 
#endif /* TIM12 */
256 
#if defined(TIM13)
257 
  else if (TIMx == TIM13)
258 
  {
259 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
260 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
261 
  }
262 
#endif /* TIM13 */
263 
#if defined(TIM14)
264 
  else if (TIMx == TIM14)
265 
  {
266 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
267 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
268 
  }
269 
#endif /* TIM14 */
270 
#if defined(TIM15)
271 
  else if (TIMx == TIM15)
272 
  {
273 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
274 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
275 
  }
276 
#endif /* TIM15 */
277 
#if defined(TIM16)
278 
  else if (TIMx == TIM16)
279 
  {
280 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
281 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
282 
  }
283 
#endif /* TIM16 */
284 
#if defined(TIM17)
285 
  else if (TIMx == TIM17)
286 
  {
287 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
288 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
289 
  }
290 
#endif /* TIM17 */
291 
  else
292 
  {
293 
    result = ERROR;
294 
  }
295 
 
296 
  return result;
297 
}
298 
 
299 
/**
300 
  * @brief  Set the fields of the time base unit configuration data structure
301 
  *         to their default values.
302 
  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
303 
  * @retval None
304 
  */
305 
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
306 
{
307 
  /* Set the default configuration */
308 
  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
309 
  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
310 
  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
311 
  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
312 
  TIM_InitStruct->RepetitionCounter = 0x00000000U;
313 
}
314 
 
315 
/**
316 
  * @brief  Configure the TIMx time base unit.
317 
  * @param  TIMx Timer Instance
318 
  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
319 
  *         (TIMx time base unit configuration data structure)
320 
  * @retval An ErrorStatus enumeration value:
321 
  *          - SUCCESS: TIMx registers are de-initialized
322 
  *          - ERROR: not applicable
323 
  */
324 
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
325 
{
326 
  uint32_t tmpcr1;
327 
 
328 
  /* Check the parameters */
329 
  assert_param(IS_TIM_INSTANCE(TIMx));
330 
  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
331 
  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
332 
 
333 
  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
334 
 
335 
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
336 
  {
337 
    /* Select the Counter Mode */
338 
    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
339 
  }
340 
 
341 
  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
342 
  {
343 
    /* Set the clock division */
344 
    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
345 
  }
346 
 
347 
  /* Write to TIMx CR1 */
348 
  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
349 
 
350 
  /* Set the Autoreload value */
351 
  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
352 
 
353 
  /* Set the Prescaler value */
354 
  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
355 
 
356 
  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
357 
  {
358 
    /* Set the Repetition Counter value */
359 
    LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
360 
  }
361 
 
362 
  /* Generate an update event to reload the Prescaler
363 
     and the repetition counter value (if applicable) immediately */
364 
  LL_TIM_GenerateEvent_UPDATE(TIMx);
365 
 
366 
  return SUCCESS;
367 
}
368 
 
369 
/**
370 
  * @brief  Set the fields of the TIMx output channel configuration data
371 
  *         structure to their default values.
372 
  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
373 
  *         (the output channel configuration data structure)
374 
  * @retval None
375 
  */
376 
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
377 
{
378 
  /* Set the default configuration */
379 
  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
380 
  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
381 
  TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
382 
  TIM_OC_InitStruct->CompareValue = 0x00000000U;
383 
  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
384 
  TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
385 
  TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
386 
  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
387 
}
388 
 
389 
/**
390 
  * @brief  Configure the TIMx output channel.
391 
  * @param  TIMx Timer Instance
392 
  * @param  Channel This parameter can be one of the following values:
393 
  *         @arg @ref LL_TIM_CHANNEL_CH1
394 
  *         @arg @ref LL_TIM_CHANNEL_CH2
395 
  *         @arg @ref LL_TIM_CHANNEL_CH3
396 
  *         @arg @ref LL_TIM_CHANNEL_CH4
397 
  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
398 
  *         data structure)
399 
  * @retval An ErrorStatus enumeration value:
400 
  *          - SUCCESS: TIMx output channel is initialized
401 
  *          - ERROR: TIMx output channel is not initialized
402 
  */
403 
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
404 
{
405 
  ErrorStatus result = ERROR;
406 
 
407 
  switch (Channel)
408 
  {
409 
    case LL_TIM_CHANNEL_CH1:
410 
      result = OC1Config(TIMx, TIM_OC_InitStruct);
411 
      break;
412 
    case LL_TIM_CHANNEL_CH2:
413 
      result = OC2Config(TIMx, TIM_OC_InitStruct);
414 
      break;
415 
    case LL_TIM_CHANNEL_CH3:
416 
      result = OC3Config(TIMx, TIM_OC_InitStruct);
417 
      break;
418 
    case LL_TIM_CHANNEL_CH4:
419 
      result = OC4Config(TIMx, TIM_OC_InitStruct);
420 
      break;
421 
    default:
422 
      break;
423 
  }
424 
 
425 
  return result;
426 
}
427 
 
428 
/**
429 
  * @brief  Set the fields of the TIMx input channel configuration data
430 
  *         structure to their default values.
431 
  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
432 
  *         data structure)
433 
  * @retval None
434 
  */
435 
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
436 
{
437 
  /* Set the default configuration */
438 
  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
439 
  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
440 
  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
441 
  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
442 
}
443 
 
444 
/**
445 
  * @brief  Configure the TIMx input channel.
446 
  * @param  TIMx Timer Instance
447 
  * @param  Channel This parameter can be one of the following values:
448 
  *         @arg @ref LL_TIM_CHANNEL_CH1
449 
  *         @arg @ref LL_TIM_CHANNEL_CH2
450 
  *         @arg @ref LL_TIM_CHANNEL_CH3
451 
  *         @arg @ref LL_TIM_CHANNEL_CH4
452 
  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
453 
  *         structure)
454 
  * @retval An ErrorStatus enumeration value:
455 
  *          - SUCCESS: TIMx output channel is initialized
456 
  *          - ERROR: TIMx output channel is not initialized
457 
  */
458 
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
459 
{
460 
  ErrorStatus result = ERROR;
461 
 
462 
  switch (Channel)
463 
  {
464 
    case LL_TIM_CHANNEL_CH1:
465 
      result = IC1Config(TIMx, TIM_IC_InitStruct);
466 
      break;
467 
    case LL_TIM_CHANNEL_CH2:
468 
      result = IC2Config(TIMx, TIM_IC_InitStruct);
469 
      break;
470 
    case LL_TIM_CHANNEL_CH3:
471 
      result = IC3Config(TIMx, TIM_IC_InitStruct);
472 
      break;
473 
    case LL_TIM_CHANNEL_CH4:
474 
      result = IC4Config(TIMx, TIM_IC_InitStruct);
475 
      break;
476 
    default:
477 
      break;
478 
  }
479 
 
480 
  return result;
481 
}
482 
 
483 
/**
484 
  * @brief  Fills each TIM_EncoderInitStruct field with its default value
485 
  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
486 
  *         configuration data structure)
487 
  * @retval None
488 
  */
489 
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
490 
{
491 
  /* Set the default configuration */
492 
  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
493 
  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
494 
  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
495 
  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
496 
  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
497 
  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
498 
  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
499 
  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
500 
  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
501 
}
502 
 
503 
/**
504 
  * @brief  Configure the encoder interface of the timer instance.
505 
  * @param  TIMx Timer Instance
506 
  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
507 
  *         configuration data structure)
508 
  * @retval An ErrorStatus enumeration value:
509 
  *          - SUCCESS: TIMx registers are de-initialized
510 
  *          - ERROR: not applicable
511 
  */
512 
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
513 
{
514 
  uint32_t tmpccmr1;
515 
  uint32_t tmpccer;
516 
 
517 
  /* Check the parameters */
518 
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
519 
  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
520 
  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
521 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
522 
  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
523 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
524 
  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
525 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
526 
  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
527 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
528 
 
529 
  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
530 
  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
531 
 
532 
  /* Get the TIMx CCMR1 register value */
533 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
534 
 
535 
  /* Get the TIMx CCER register value */
536 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
537 
 
538 
  /* Configure TI1 */
539 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
540 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
541 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
542 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
543 
 
544 
  /* Configure TI2 */
545 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
546 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
547 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
548 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
549 
 
550 
  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
551 
  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
552 
  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
553 
  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
554 
  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
555 
 
556 
  /* Set encoder mode */
557 
  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
558 
 
559 
  /* Write to TIMx CCMR1 */
560 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
561 
 
562 
  /* Write to TIMx CCER */
563 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
564 
 
565 
  return SUCCESS;
566 
}
567 
 
568 
/**
569 
  * @brief  Set the fields of the TIMx Hall sensor interface configuration data
570 
  *         structure to their default values.
571 
  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
572 
  *         configuration data structure)
573 
  * @retval None
574 
  */
575 
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
576 
{
577 
  /* Set the default configuration */
578 
  TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
579 
  TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
580 
  TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
581 
  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
582 
}
583 
 
584 
/**
585 
  * @brief  Configure the Hall sensor interface of the timer instance.
586 
  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
587 
  *       to the TI1 input channel
588 
  * @note TIMx slave mode controller is configured in reset mode.
589 
          Selected internal trigger is TI1F_ED.
590 
  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
591 
  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
592 
  *       between 2 changes on the inputs. It gives information about motor speed.
593 
  * @note Channel 2 is configured in output PWM 2 mode.
594 
  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
595 
  * @note OC2REF is selected as trigger output on TRGO.
596 
  * @param  TIMx Timer Instance
597 
  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
598 
  *         interface configuration data structure)
599 
  * @retval An ErrorStatus enumeration value:
600 
  *          - SUCCESS: TIMx registers are de-initialized
601 
  *          - ERROR: not applicable
602 
  */
603 
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
604 
{
605 
  uint32_t tmpcr2;
606 
  uint32_t tmpccmr1;
607 
  uint32_t tmpccer;
608 
  uint32_t tmpsmcr;
609 
 
610 
  /* Check the parameters */
611 
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
612 
  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
613 
  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
614 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
615 
 
616 
  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
617 
  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
618 
 
619 
  /* Get the TIMx CR2 register value */
620 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
621 
 
622 
  /* Get the TIMx CCMR1 register value */
623 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
624 
 
625 
  /* Get the TIMx CCER register value */
626 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
627 
 
628 
  /* Get the TIMx SMCR register value */
629 
  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
630 
 
631 
  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
632 
  tmpcr2 |= TIM_CR2_TI1S;
633 
 
634 
  /* OC2REF signal is used as trigger output (TRGO) */
635 
  tmpcr2 |= LL_TIM_TRGO_OC2REF;
636 
 
637 
  /* Configure the slave mode controller */
638 
  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
639 
  tmpsmcr |= LL_TIM_TS_TI1F_ED;
640 
  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
641 
 
642 
  /* Configure input channel 1 */
643 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
644 
  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
645 
  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
646 
  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
647 
 
648 
  /* Configure input channel 2 */
649 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
650 
  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
651 
 
652 
  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
653 
  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
654 
  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
655 
  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
656 
 
657 
  /* Write to TIMx CR2 */
658 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
659 
 
660 
  /* Write to TIMx SMCR */
661 
  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
662 
 
663 
  /* Write to TIMx CCMR1 */
664 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
665 
 
666 
  /* Write to TIMx CCER */
667 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
668 
 
669 
  /* Write to TIMx CCR2 */
670 
  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
671 
 
672 
  return SUCCESS;
673 
}
674 
 
675 
/**
676 
  * @brief  Set the fields of the Break and Dead Time configuration data structure
677 
  *         to their default values.
678 
  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
679 
  *         data structure)
680 
  * @retval None
681 
  */
682 
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
683 
{
684 
  /* Set the default configuration */
685 
  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
686 
  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
687 
  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
688 
  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
689 
  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
690 
  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
691 
  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
692 
}
693 
 
694 
/**
695 
  * @brief  Configure the Break and Dead Time feature of the timer instance.
696 
  * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
697 
  *  depending on the LOCK configuration, it can be necessary to configure all of
698 
  *  them during the first write access to the TIMx_BDTR register.
699 
  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
700 
  *       a timer instance provides a break input.
701 
  * @param  TIMx Timer Instance
702 
  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
703 
  *         data structure)
704 
  * @retval An ErrorStatus enumeration value:
705 
  *          - SUCCESS: Break and Dead Time is initialized
706 
  *          - ERROR: not applicable
707 
  */
708 
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
709 
{
710 
  uint32_t tmpbdtr = 0;
711 
 
712 
  /* Check the parameters */
713 
  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
714 
  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
715 
  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
716 
  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
717 
  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
718 
  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
719 
  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
720 
 
721 
  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
722 
  the OSSI State, the dead time value and the Automatic Output Enable Bit */
723 
 
724 
  /* Set the BDTR bits */
725 
  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
726 
  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
727 
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
728 
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
729 
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
730 
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
731 
  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
732 
 
733 
  /* Set TIMx_BDTR */
734 
  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
735 
 
736 
  return SUCCESS;
737 
}
738 
/**
739 
  * @}
740 
  */
741 
 
742 
/**
743 
  * @}
744 
  */
745 
 
746 
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
747 
  *  @brief   Private functions
748 
  * @{
749 
  */
750 
/**
751 
  * @brief  Configure the TIMx output channel 1.
752 
  * @param  TIMx Timer Instance
753 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
754 
  * @retval An ErrorStatus enumeration value:
755 
  *          - SUCCESS: TIMx registers are de-initialized
756 
  *          - ERROR: not applicable
757 
  */
758 
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
759 
{
760 
  uint32_t tmpccmr1;
761 
  uint32_t tmpccer;
762 
  uint32_t tmpcr2;
763 
 
764 
  /* Check the parameters */
765 
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
766 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
767 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
768 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
769 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
770 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
771 
 
772 
  /* Disable the Channel 1: Reset the CC1E Bit */
773 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
774 
 
775 
  /* Get the TIMx CCER register value */
776 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
777 
 
778 
  /* Get the TIMx CR2 register value */
779 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
780 
 
781 
  /* Get the TIMx CCMR1 register value */
782 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
783 
 
784 
  /* Reset Capture/Compare selection Bits */
785 
  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
786 
 
787 
  /* Set the Output Compare Mode */
788 
  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
789 
 
790 
  /* Set the Output Compare Polarity */
791 
  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
792 
 
793 
  /* Set the Output State */
794 
  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
795 
 
796 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
797 
  {
798 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
799 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
800 
 
801 
    /* Set the complementary output Polarity */
802 
    MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
803 
 
804 
    /* Set the complementary output State */
805 
    MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
806 
 
807 
    /* Set the Output Idle state */
808 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
809 
 
810 
    /* Set the complementary output Idle state */
811 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
812 
  }
813 
 
814 
  /* Write to TIMx CR2 */
815 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
816 
 
817 
  /* Write to TIMx CCMR1 */
818 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
819 
 
820 
  /* Set the Capture Compare Register value */
821 
  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
822 
 
823 
  /* Write to TIMx CCER */
824 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
825 
 
826 
  return SUCCESS;
827 
}
828 
 
829 
/**
830 
  * @brief  Configure the TIMx output channel 2.
831 
  * @param  TIMx Timer Instance
832 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
833 
  * @retval An ErrorStatus enumeration value:
834 
  *          - SUCCESS: TIMx registers are de-initialized
835 
  *          - ERROR: not applicable
836 
  */
837 
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
838 
{
839 
  uint32_t tmpccmr1;
840 
  uint32_t tmpccer;
841 
  uint32_t tmpcr2;
842 
 
843 
  /* Check the parameters */
844 
  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
845 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
846 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
847 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
848 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
849 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
850 
 
851 
  /* Disable the Channel 2: Reset the CC2E Bit */
852 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
853 
 
854 
  /* Get the TIMx CCER register value */
855 
  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
856 
 
857 
  /* Get the TIMx CR2 register value */
858 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
859 
 
860 
  /* Get the TIMx CCMR1 register value */
861 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
862 
 
863 
  /* Reset Capture/Compare selection Bits */
864 
  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
865 
 
866 
  /* Select the Output Compare Mode */
867 
  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
868 
 
869 
  /* Set the Output Compare Polarity */
870 
  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
871 
 
872 
  /* Set the Output State */
873 
  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
874 
 
875 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
876 
  {
877 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
878 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
879 
 
880 
    /* Set the complementary output Polarity */
881 
    MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
882 
 
883 
    /* Set the complementary output State */
884 
    MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
885 
 
886 
    /* Set the Output Idle state */
887 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
888 
 
889 
    /* Set the complementary output Idle state */
890 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
891 
  }
892 
 
893 
  /* Write to TIMx CR2 */
894 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
895 
 
896 
  /* Write to TIMx CCMR1 */
897 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
898 
 
899 
  /* Set the Capture Compare Register value */
900 
  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
901 
 
902 
  /* Write to TIMx CCER */
903 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
904 
 
905 
  return SUCCESS;
906 
}
907 
 
908 
/**
909 
  * @brief  Configure the TIMx output channel 3.
910 
  * @param  TIMx Timer Instance
911 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
912 
  * @retval An ErrorStatus enumeration value:
913 
  *          - SUCCESS: TIMx registers are de-initialized
914 
  *          - ERROR: not applicable
915 
  */
916 
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
917 
{
918 
  uint32_t tmpccmr2;
919 
  uint32_t tmpccer;
920 
  uint32_t tmpcr2;
921 
 
922 
  /* Check the parameters */
923 
  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
924 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
925 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
926 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
927 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
928 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
929 
 
930 
  /* Disable the Channel 3: Reset the CC3E Bit */
931 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
932 
 
933 
  /* Get the TIMx CCER register value */
934 
  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
935 
 
936 
  /* Get the TIMx CR2 register value */
937 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
938 
 
939 
  /* Get the TIMx CCMR2 register value */
940 
  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
941 
 
942 
  /* Reset Capture/Compare selection Bits */
943 
  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
944 
 
945 
  /* Select the Output Compare Mode */
946 
  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
947 
 
948 
  /* Set the Output Compare Polarity */
949 
  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
950 
 
951 
  /* Set the Output State */
952 
  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
953 
 
954 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
955 
  {
956 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
957 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
958 
 
959 
    /* Set the complementary output Polarity */
960 
    MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
961 
 
962 
    /* Set the complementary output State */
963 
    MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
964 
 
965 
    /* Set the Output Idle state */
966 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
967 
 
968 
    /* Set the complementary output Idle state */
969 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
970 
  }
971 
 
972 
  /* Write to TIMx CR2 */
973 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
974 
 
975 
  /* Write to TIMx CCMR2 */
976 
  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
977 
 
978 
  /* Set the Capture Compare Register value */
979 
  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
980 
 
981 
  /* Write to TIMx CCER */
982 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
983 
 
984 
  return SUCCESS;
985 
}
986 
 
987 
/**
988 
  * @brief  Configure the TIMx output channel 4.
989 
  * @param  TIMx Timer Instance
990 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
991 
  * @retval An ErrorStatus enumeration value:
992 
  *          - SUCCESS: TIMx registers are de-initialized
993 
  *          - ERROR: not applicable
994 
  */
995 
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
996 
{
997 
  uint32_t tmpccmr2;
998 
  uint32_t tmpccer;
999 
  uint32_t tmpcr2;
1000 
 
1001 
  /* Check the parameters */
1002 
  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1003 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1004 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1005 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1006 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1007 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1008 
 
1009 
  /* Disable the Channel 4: Reset the CC4E Bit */
1010 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1011 
 
1012 
  /* Get the TIMx CCER register value */
1013 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1014 
 
1015 
  /* Get the TIMx CR2 register value */
1016 
  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1017 
 
1018 
  /* Get the TIMx CCMR2 register value */
1019 
  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1020 
 
1021 
  /* Reset Capture/Compare selection Bits */
1022 
  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1023 
 
1024 
  /* Select the Output Compare Mode */
1025 
  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1026 
 
1027 
  /* Set the Output Compare Polarity */
1028 
  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1029 
 
1030 
  /* Set the Output State */
1031 
  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1032 
 
1033 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
1034 
  {
1035 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1036 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1037 
 
1038 
    /* Set the Output Idle state */
1039 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1040 
  }
1041 
 
1042 
  /* Write to TIMx CR2 */
1043 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1044 
 
1045 
  /* Write to TIMx CCMR2 */
1046 
  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1047 
 
1048 
  /* Set the Capture Compare Register value */
1049 
  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1050 
 
1051 
  /* Write to TIMx CCER */
1052 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1053 
 
1054 
  return SUCCESS;
1055 
}
1056 
 
1057 
 
1058 
/**
1059 
  * @brief  Configure the TIMx input channel 1.
1060 
  * @param  TIMx Timer Instance
1061 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1062 
  * @retval An ErrorStatus enumeration value:
1063 
  *          - SUCCESS: TIMx registers are de-initialized
1064 
  *          - ERROR: not applicable
1065 
  */
1066 
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1067 
{
1068 
  /* Check the parameters */
1069 
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1070 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1071 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1072 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1073 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1074 
 
1075 
  /* Disable the Channel 1: Reset the CC1E Bit */
1076 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1077 
 
1078 
  /* Select the Input and set the filter and the prescaler value */
1079 
  MODIFY_REG(TIMx->CCMR1,
1080 
             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1081 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1082 
 
1083 
  /* Select the Polarity and set the CC1E Bit */
1084 
  MODIFY_REG(TIMx->CCER,
1085 
             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1086 
             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1087 
 
1088 
  return SUCCESS;
1089 
}
1090 
 
1091 
/**
1092 
  * @brief  Configure the TIMx input channel 2.
1093 
  * @param  TIMx Timer Instance
1094 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1095 
  * @retval An ErrorStatus enumeration value:
1096 
  *          - SUCCESS: TIMx registers are de-initialized
1097 
  *          - ERROR: not applicable
1098 
  */
1099 
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1100 
{
1101 
  /* Check the parameters */
1102 
  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1103 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1104 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1105 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1106 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1107 
 
1108 
  /* Disable the Channel 2: Reset the CC2E Bit */
1109 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1110 
 
1111 
  /* Select the Input and set the filter and the prescaler value */
1112 
  MODIFY_REG(TIMx->CCMR1,
1113 
             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1114 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1115 
 
1116 
  /* Select the Polarity and set the CC2E Bit */
1117 
  MODIFY_REG(TIMx->CCER,
1118 
             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1119 
             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1120 
 
1121 
  return SUCCESS;
1122 
}
1123 
 
1124 
/**
1125 
  * @brief  Configure the TIMx input channel 3.
1126 
  * @param  TIMx Timer Instance
1127 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1128 
  * @retval An ErrorStatus enumeration value:
1129 
  *          - SUCCESS: TIMx registers are de-initialized
1130 
  *          - ERROR: not applicable
1131 
  */
1132 
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1133 
{
1134 
  /* Check the parameters */
1135 
  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1136 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1137 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1138 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1139 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1140 
 
1141 
  /* Disable the Channel 3: Reset the CC3E Bit */
1142 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1143 
 
1144 
  /* Select the Input and set the filter and the prescaler value */
1145 
  MODIFY_REG(TIMx->CCMR2,
1146 
             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1147 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1148 
 
1149 
  /* Select the Polarity and set the CC3E Bit */
1150 
  MODIFY_REG(TIMx->CCER,
1151 
             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1152 
             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1153 
 
1154 
  return SUCCESS;
1155 
}
1156 
 
1157 
/**
1158 
  * @brief  Configure the TIMx input channel 4.
1159 
  * @param  TIMx Timer Instance
1160 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1161 
  * @retval An ErrorStatus enumeration value:
1162 
  *          - SUCCESS: TIMx registers are de-initialized
1163 
  *          - ERROR: not applicable
1164 
  */
1165 
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1166 
{
1167 
  /* Check the parameters */
1168 
  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1169 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1170 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1171 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1172 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1173 
 
1174 
  /* Disable the Channel 4: Reset the CC4E Bit */
1175 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1176 
 
1177 
  /* Select the Input and set the filter and the prescaler value */
1178 
  MODIFY_REG(TIMx->CCMR2,
1179 
             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1180 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1181 
 
1182 
  /* Select the Polarity and set the CC4E Bit */
1183 
  MODIFY_REG(TIMx->CCER,
1184 
             TIM_CCER_CC4P,
1185 
             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1186 
 
1187 
  return SUCCESS;
1188 
}
1189 
 
1190 
 
1191 
/**
1192 
  * @}
1193 
  */
1194 
 
1195 
/**
1196 
  * @}
1197 
  */
1198 
 
1199 
#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
1200 
 
1201 
/**
1202 
  * @}
1203 
  */
1204 
 
1205 
#endif /* USE_FULL_LL_DRIVER */
1206