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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_ll_sdmmc.c |
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4 | * @author MCD Application Team |
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5 | mjames | 5 | * @version V1.0.4 |
6 | * @date 29-April-2016 |
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2 | mjames | 7 | * @brief SDMMC Low Layer HAL module driver. |
8 | * |
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9 | * This file provides firmware functions to manage the following |
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10 | * functionalities of the SDMMC peripheral: |
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11 | * + Initialization/de-initialization functions |
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12 | * + I/O operation functions |
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13 | * + Peripheral Control functions |
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14 | * + Peripheral State functions |
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15 | * |
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16 | @verbatim |
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17 | ============================================================================== |
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18 | ##### SDMMC peripheral features ##### |
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19 | ============================================================================== |
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20 | [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 |
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21 | peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA |
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22 | devices. |
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23 | |||
24 | [..] The SDIO features include the following: |
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25 | (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support |
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26 | for three different databus modes: 1-bit (default), 4-bit and 8-bit |
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27 | (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) |
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28 | (+) Full compliance with SD Memory Card Specifications Version 2.0 |
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29 | (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two |
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30 | different data bus modes: 1-bit (default) and 4-bit |
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31 | (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol |
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32 | Rev1.1) |
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33 | (+) Data transfer up to 48 MHz for the 8 bit mode |
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34 | (+) Data and command output enable signals to control external bidirectional drivers. |
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35 | |||
36 | |||
37 | ##### How to use this driver ##### |
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38 | ============================================================================== |
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39 | [..] |
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40 | This driver is a considered as a driver of service for external devices drivers |
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41 | that interfaces with the SDIO peripheral. |
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42 | According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs |
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43 | is used in the device's driver to perform SDIO operations and functionalities. |
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44 | |||
45 | This driver is almost transparent for the final user, it is only used to implement other |
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46 | functionalities of the external device. |
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47 | |||
48 | [..] |
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49 | (+) The SDIO peripheral uses two clock signals: |
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50 | (++) SDIO adapter clock (SDIOCLK = HCLK) |
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51 | (++) AHB bus clock (HCLK/2) |
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52 | |||
53 | -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: |
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54 | Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) |
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55 | |||
56 | (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO |
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57 | peripheral. |
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58 | |||
59 | (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) |
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60 | function and disable it using the function SDIO_PowerState_OFF(SDIOx). |
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61 | |||
62 | (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. |
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63 | |||
64 | (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) |
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65 | and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. |
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66 | |||
67 | (+) When using the DMA mode |
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68 | (++) Configure the DMA in the MSP layer of the external device |
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69 | (++) Active the needed channel Request |
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70 | (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro |
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71 | __SDIO_DMA_DISABLE(). |
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72 | |||
73 | (+) To control the CPSM (Command Path State Machine) and send |
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74 | commands to the card use the SDIO_SendCommand(), |
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75 | SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has |
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76 | to fill the command structure (pointer to SDIO_CmdInitTypeDef) according |
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77 | to the selected command to be sent. |
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78 | The parameters that should be filled are: |
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79 | (++) Command Argument |
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80 | (++) Command Index |
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81 | (++) Command Response type |
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82 | (++) Command Wait |
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83 | (++) CPSM Status (Enable or Disable). |
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84 | |||
85 | -@@- To check if the command is well received, read the SDIO_CMDRESP |
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86 | register using the SDIO_GetCommandResponse(). |
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87 | The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the |
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88 | SDIO_GetResponse() function. |
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89 | |||
90 | (+) To control the DPSM (Data Path State Machine) and send/receive |
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91 | data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), |
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92 | SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. |
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93 | |||
94 | *** Read Operations *** |
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95 | ======================= |
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96 | [..] |
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97 | (#) First, user has to fill the data structure (pointer to |
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98 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
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99 | The parameters that should be filled are: |
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100 | (++) Data TimeOut |
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101 | (++) Data Length |
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102 | (++) Data Block size |
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103 | (++) Data Transfer direction: should be from card (To SDIO) |
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104 | (++) Data Transfer mode |
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105 | (++) DPSM Status (Enable or Disable) |
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106 | |||
107 | (#) Configure the SDIO resources to receive the data from the card |
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108 | according to selected transfer mode. |
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109 | |||
110 | (#) Send the selected Read command. |
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111 | |||
112 | (#) Use the SDIO flags/interrupts to check the transfer status. |
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113 | |||
114 | *** Write Operations *** |
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115 | ======================== |
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116 | [..] |
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117 | (#) First, user has to fill the data structure (pointer to |
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118 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
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119 | The parameters that should be filled are: |
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120 | (++) Data TimeOut |
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121 | (++) Data Length |
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122 | (++) Data Block size |
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123 | (++) Data Transfer direction: should be to card (To CARD) |
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124 | (++) Data Transfer mode |
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125 | (++) DPSM Status (Enable or Disable) |
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126 | |||
127 | (#) Configure the SDIO resources to send the data to the card according to |
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128 | selected transfer mode. |
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129 | |||
130 | (#) Send the selected Write command. |
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131 | |||
132 | (#) Use the SDIO flags/interrupts to check the transfer status. |
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133 | |||
134 | @endverbatim |
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135 | ****************************************************************************** |
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136 | * @attention |
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137 | * |
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5 | mjames | 138 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
2 | mjames | 139 | * |
140 | * Redistribution and use in source and binary forms, with or without modification, |
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141 | * are permitted provided that the following conditions are met: |
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142 | * 1. Redistributions of source code must retain the above copyright notice, |
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143 | * this list of conditions and the following disclaimer. |
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144 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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145 | * this list of conditions and the following disclaimer in the documentation |
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146 | * and/or other materials provided with the distribution. |
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147 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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148 | * may be used to endorse or promote products derived from this software |
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149 | * without specific prior written permission. |
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150 | * |
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151 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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152 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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153 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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154 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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155 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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156 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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157 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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158 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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159 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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160 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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161 | * |
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162 | ****************************************************************************** |
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163 | */ |
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164 | |||
165 | /* Includes ------------------------------------------------------------------*/ |
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166 | #include "stm32f1xx_hal.h" |
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167 | |||
168 | #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) |
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169 | |||
170 | #if defined(STM32F103xE) || defined(STM32F103xG) |
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171 | |||
172 | /** @addtogroup STM32F1xx_HAL_Driver |
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173 | * @{ |
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174 | */ |
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175 | |||
176 | /** @defgroup SDMMC_LL SDMMC Low Layer |
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177 | * @brief Low layer module for SD and MMC driver |
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178 | * @{ |
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179 | */ |
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180 | |||
181 | /* Private typedef -----------------------------------------------------------*/ |
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182 | /* Private define ------------------------------------------------------------*/ |
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183 | /* Private macro -------------------------------------------------------------*/ |
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184 | /* Private variables ---------------------------------------------------------*/ |
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185 | /* Private function prototypes -----------------------------------------------*/ |
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186 | /* Private functions ---------------------------------------------------------*/ |
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187 | |||
188 | /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions |
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189 | * @{ |
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190 | */ |
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191 | |||
192 | /** @defgroup HAL_SDMMC_LL_Group1 Initialization and de-initialization functions |
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193 | * @brief Initialization and Configuration functions |
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194 | * |
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195 | @verbatim |
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196 | =============================================================================== |
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197 | ##### Initialization/de-initialization functions ##### |
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198 | =============================================================================== |
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199 | [..] This section provides functions allowing to: |
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200 | |||
201 | @endverbatim |
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202 | * @{ |
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203 | */ |
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204 | |||
205 | /** |
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206 | * @brief Initializes the SDIO according to the specified |
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207 | * parameters in the SDIO_InitTypeDef and create the associated handle. |
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208 | * @param SDIOx: Pointer to SDIO register base |
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209 | * @param Init: SDIO initialization structure |
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210 | * @retval HAL status |
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211 | */ |
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212 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) |
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213 | { |
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214 | /* Check the parameters */ |
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215 | assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); |
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216 | assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); |
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217 | assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); |
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218 | assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); |
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219 | assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); |
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220 | assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); |
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221 | assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); |
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222 | |||
223 | /* Set SDIO configuration parameters */ |
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224 | /* Write to SDIO CLKCR */ |
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225 | MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ |
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226 | Init.ClockBypass |\ |
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227 | Init.ClockPowerSave |\ |
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228 | Init.BusWide |\ |
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229 | Init.HardwareFlowControl |\ |
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230 | Init.ClockDiv); |
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231 | |||
232 | return HAL_OK; |
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233 | } |
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234 | |||
235 | /** |
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236 | * @} |
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237 | */ |
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238 | |||
239 | /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions |
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240 | * @brief Data transfers functions |
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241 | * |
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242 | @verbatim |
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243 | =============================================================================== |
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244 | ##### IO operation functions ##### |
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245 | =============================================================================== |
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246 | [..] |
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247 | This subsection provides a set of functions allowing to manage the SDIO data |
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248 | transfers. |
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249 | |||
250 | @endverbatim |
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251 | * @{ |
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252 | */ |
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253 | |||
254 | /** |
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255 | * @brief Read data (word) from Rx FIFO in blocking mode (polling) |
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256 | * @param SDIOx: Pointer to SDIO register base |
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257 | * @retval HAL status |
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258 | */ |
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259 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) |
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260 | { |
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261 | /* Read data from Rx FIFO */ |
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262 | return (SDIOx->FIFO); |
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263 | } |
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264 | |||
265 | /** |
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266 | * @brief Write data (word) to Tx FIFO in blocking mode (polling) |
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267 | * @param SDIOx: Pointer to SDIO register base |
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268 | * @param pWriteData: pointer to data to write |
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269 | * @retval HAL status |
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270 | */ |
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271 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) |
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272 | { |
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273 | /* Write data to FIFO */ |
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274 | SDIOx->FIFO = *pWriteData; |
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275 | |||
276 | return HAL_OK; |
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277 | } |
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278 | |||
279 | /** |
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280 | * @} |
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281 | */ |
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282 | |||
283 | /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions |
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284 | * @brief management functions |
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285 | * |
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286 | @verbatim |
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287 | =============================================================================== |
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288 | ##### Peripheral Control functions ##### |
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289 | =============================================================================== |
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290 | [..] |
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291 | This subsection provides a set of functions allowing to control the SDIO data |
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292 | transfers. |
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293 | |||
294 | @endverbatim |
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295 | * @{ |
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296 | */ |
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297 | |||
298 | /** |
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299 | * @brief Set SDIO Power state to ON. |
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300 | * @param SDIOx: Pointer to SDIO register base |
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301 | * @retval HAL status |
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302 | */ |
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303 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) |
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304 | { |
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305 | /* Set power state to ON */ |
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306 | SDIOx->POWER = SDIO_POWER_PWRCTRL; |
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307 | |||
308 | return HAL_OK; |
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309 | } |
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310 | |||
311 | /** |
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312 | * @brief Set SDIO Power state to OFF. |
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313 | * @param SDIOx: Pointer to SDIO register base |
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314 | * @retval HAL status |
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315 | */ |
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316 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) |
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317 | { |
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318 | /* Set power state to OFF */ |
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319 | SDIOx->POWER = (uint32_t)0x00000000; |
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320 | |||
321 | return HAL_OK; |
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322 | } |
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323 | |||
324 | /** |
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325 | * @brief Get SDIO Power state. |
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326 | * @param SDIOx: Pointer to SDIO register base |
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327 | * @retval Power status of the controller. The returned value can be one of the |
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328 | * following values: |
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329 | * - 0x00: Power OFF |
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330 | * - 0x02: Power UP |
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331 | * - 0x03: Power ON |
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332 | */ |
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333 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) |
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334 | { |
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335 | return (SDIOx->POWER & SDIO_POWER_PWRCTRL); |
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336 | } |
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337 | |||
338 | /** |
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339 | * @brief Configure the SDIO command path according to the specified parameters in |
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340 | * SDIO_CmdInitTypeDef structure and send the command |
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341 | * @param SDIOx: Pointer to SDIO register base |
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342 | * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains |
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343 | * the configuration information for the SDIO command |
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344 | * @retval HAL status |
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345 | */ |
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346 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) |
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347 | { |
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348 | /* Check the parameters */ |
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349 | assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); |
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350 | assert_param(IS_SDIO_RESPONSE(Command->Response)); |
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351 | assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); |
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352 | assert_param(IS_SDIO_CPSM(Command->CPSM)); |
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353 | |||
354 | /* Set the SDIO Argument value */ |
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355 | SDIOx->ARG = Command->Argument; |
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356 | |||
357 | /* Set SDIO command parameters */ |
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358 | /* Write to SDIO CMD register */ |
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359 | MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, Command->CmdIndex |\ |
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360 | Command->Response |\ |
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361 | Command->WaitForInterrupt |\ |
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362 | Command->CPSM); |
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363 | |||
364 | return HAL_OK; |
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365 | } |
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366 | |||
367 | /** |
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368 | * @brief Return the command index of last command for which response received |
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369 | * @param SDIOx: Pointer to SDIO register base |
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370 | * @retval Command index of the last command response received |
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371 | */ |
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372 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) |
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373 | { |
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374 | return (uint8_t)(SDIOx->RESPCMD); |
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375 | } |
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376 | |||
377 | |||
378 | /** |
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379 | * @brief Return the response received from the card for the last command |
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380 | * @param SDIO_RESP: Specifies the SDIO response register. |
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381 | * This parameter can be one of the following values: |
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382 | * @arg SDIO_RESP1: Response Register 1 |
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383 | * @arg SDIO_RESP2: Response Register 2 |
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384 | * @arg SDIO_RESP3: Response Register 3 |
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385 | * @arg SDIO_RESP4: Response Register 4 |
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386 | * @retval The Corresponding response register value |
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387 | */ |
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388 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) |
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389 | { |
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390 | __IO uint32_t tmp = 0; |
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391 | |||
392 | /* Check the parameters */ |
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393 | assert_param(IS_SDIO_RESP(Response)); |
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394 | |||
395 | /* Get the response */ |
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396 | tmp = SDIO_RESP_ADDR + Response; |
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397 | |||
398 | return (*(__IO uint32_t *) tmp); |
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399 | } |
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400 | |||
401 | /** |
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402 | * @brief Configure the SDIO data path according to the specified |
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403 | * parameters in the SDIO_DataInitTypeDef. |
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404 | * @param SDIOx: Pointer to SDIO register base |
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405 | * @param Data : pointer to a SDIO_DataInitTypeDef structure |
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406 | * that contains the configuration information for the SDIO data. |
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407 | * @retval HAL status |
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408 | */ |
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409 | HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) |
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410 | { |
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411 | /* Check the parameters */ |
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412 | assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); |
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413 | assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); |
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414 | assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); |
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415 | assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); |
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416 | assert_param(IS_SDIO_DPSM(Data->DPSM)); |
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417 | |||
418 | /* Set the SDIO Data TimeOut value */ |
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419 | SDIOx->DTIMER = Data->DataTimeOut; |
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420 | |||
421 | /* Set the SDIO DataLength value */ |
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422 | SDIOx->DLEN = Data->DataLength; |
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423 | |||
424 | /* Set the SDIO data configuration parameters */ |
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425 | /* Write to SDIO DCTRL */ |
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426 | MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\ |
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427 | Data->TransferDir |\ |
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428 | Data->TransferMode |\ |
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429 | Data->DPSM); |
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430 | |||
431 | return HAL_OK; |
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432 | |||
433 | } |
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434 | |||
435 | /** |
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436 | * @brief Returns number of remaining data bytes to be transferred. |
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437 | * @param SDIOx: Pointer to SDIO register base |
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438 | * @retval Number of remaining data bytes to be transferred |
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439 | */ |
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440 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) |
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441 | { |
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442 | return (SDIOx->DCOUNT); |
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443 | } |
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444 | |||
445 | /** |
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446 | * @brief Get the FIFO data |
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447 | * @param SDIOx: Pointer to SDIO register base |
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448 | * @retval Data received |
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449 | */ |
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450 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) |
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451 | { |
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452 | return (SDIOx->FIFO); |
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453 | } |
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454 | |||
455 | |||
456 | /** |
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457 | * @brief Sets one of the two options of inserting read wait interval. |
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458 | * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. |
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459 | * This parameter can be: |
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460 | * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK |
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461 | * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 |
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462 | * @retval None |
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463 | */ |
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464 | HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) |
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465 | { |
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466 | /* Check the parameters */ |
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467 | assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); |
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468 | |||
469 | /* Set SDIO read wait mode */ |
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470 | MODIFY_REG(SDIO->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); |
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471 | |||
472 | return HAL_OK; |
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473 | } |
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474 | |||
475 | |||
476 | /** |
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477 | * @} |
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478 | */ |
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479 | |||
480 | /** |
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481 | * @} |
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482 | */ |
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483 | |||
484 | #endif /* STM32F103xE || STM32F103xG */ |
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485 | |||
486 | #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ |
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487 | |||
488 | /** |
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489 | * @} |
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490 | */ |
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491 | |||
492 | /** |
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493 | * @} |
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494 | */ |
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495 | |||
496 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |