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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_rcc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief RCC LL module driver. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file in |
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| 13 | * the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | ****************************************************************************** |
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| 16 | */ |
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| 17 | |||
| 18 | #if defined(USE_FULL_LL_DRIVER) |
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| 19 | |||
| 20 | /* Includes ------------------------------------------------------------------*/ |
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| 21 | #include "stm32f1xx_ll_rcc.h" |
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| 22 | #ifdef USE_FULL_ASSERT |
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| 23 | #include "stm32_assert.h" |
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| 24 | #else |
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| 25 | #define assert_param(expr) ((void)0U) |
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| 26 | #endif /* USE_FULL_ASSERT */ |
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| 27 | /** @addtogroup STM32F1xx_LL_Driver |
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| 28 | * @{ |
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| 29 | */ |
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| 30 | |||
| 31 | #if defined(RCC) |
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| 32 | |||
| 33 | /** @defgroup RCC_LL RCC |
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| 34 | * @{ |
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| 35 | */ |
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| 36 | |||
| 37 | /* Private types -------------------------------------------------------------*/ |
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| 38 | /* Private variables ---------------------------------------------------------*/ |
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| 39 | /* Private constants ---------------------------------------------------------*/ |
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| 40 | /* Private macros ------------------------------------------------------------*/ |
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| 41 | /** @addtogroup RCC_LL_Private_Macros |
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| 42 | * @{ |
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| 43 | */ |
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| 44 | #if defined(RCC_PLLI2S_SUPPORT) |
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| 45 | #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \ |
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| 46 | || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE)) |
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| 47 | #endif /* RCC_PLLI2S_SUPPORT */ |
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| 48 | |||
| 49 | #if defined(USB) || defined(USB_OTG_FS) |
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| 50 | #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) |
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| 51 | #endif /* USB */ |
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| 52 | |||
| 53 | #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) |
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| 54 | /** |
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| 55 | * @} |
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| 56 | */ |
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| 57 | |||
| 58 | /* Private function prototypes -----------------------------------------------*/ |
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| 59 | /** @defgroup RCC_LL_Private_Functions RCC Private functions |
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| 60 | * @{ |
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| 61 | */ |
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| 62 | uint32_t RCC_GetSystemClockFreq(void); |
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| 63 | uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); |
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| 64 | uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); |
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| 65 | uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); |
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| 66 | uint32_t RCC_PLL_GetFreqDomain_SYS(void); |
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| 67 | #if defined(RCC_PLLI2S_SUPPORT) |
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| 68 | uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); |
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| 69 | #endif /* RCC_PLLI2S_SUPPORT */ |
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| 70 | #if defined(RCC_PLL2_SUPPORT) |
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| 71 | uint32_t RCC_PLL2_GetFreqClockFreq(void); |
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| 72 | #endif /* RCC_PLL2_SUPPORT */ |
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| 73 | /** |
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| 74 | * @} |
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| 75 | */ |
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| 76 | |||
| 77 | /* Exported functions --------------------------------------------------------*/ |
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| 78 | /** @addtogroup RCC_LL_Exported_Functions |
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| 79 | * @{ |
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| 80 | */ |
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| 81 | |||
| 82 | /** @addtogroup RCC_LL_EF_Init |
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| 83 | * @{ |
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| 84 | */ |
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| 85 | |||
| 86 | /** |
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| 87 | * @brief Reset the RCC clock configuration to the default reset state. |
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| 88 | * @note The default reset state of the clock configuration is given below: |
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| 89 | * - HSI ON and used as system clock source |
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| 90 | * - HSE PLL, PLL2 & PLL3 are OFF |
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| 91 | * - AHB, APB1 and APB2 prescaler set to 1. |
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| 92 | * - CSS, MCO OFF |
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| 93 | * - All interrupts disabled |
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| 94 | * @note This function doesn't modify the configuration of the |
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| 95 | * - Peripheral clocks |
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| 96 | * - LSI, LSE and RTC clocks |
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| 97 | * @retval An ErrorStatus enumeration value: |
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| 98 | * - SUCCESS: RCC registers are de-initialized |
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| 99 | * - ERROR: not applicable |
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| 100 | */ |
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| 101 | ErrorStatus LL_RCC_DeInit(void) |
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| 102 | { |
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| 103 | /* Set HSION bit */ |
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| 104 | LL_RCC_HSI_Enable(); |
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| 105 | |||
| 106 | /* Wait for HSI READY bit */ |
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| 107 | while (LL_RCC_HSI_IsReady() != 1U) |
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| 108 | {} |
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| 109 | |||
| 110 | /* Configure HSI as system clock source */ |
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| 111 | LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); |
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| 112 | |||
| 113 | /* Wait till clock switch is ready */ |
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| 114 | while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) |
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| 115 | {} |
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| 116 | |||
| 117 | /* Reset PLLON bit */ |
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| 118 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
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| 119 | |||
| 120 | /* Wait for PLL READY bit to be reset */ |
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| 121 | while (LL_RCC_PLL_IsReady() != 0U) |
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| 122 | {} |
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| 123 | |||
| 124 | /* Reset CFGR register */ |
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| 125 | LL_RCC_WriteReg(CFGR, 0x00000000U); |
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| 126 | |||
| 127 | /* Reset HSEON, HSEBYP & CSSON bits */ |
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| 128 | CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP)); |
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| 129 | |||
| 130 | #if defined(RCC_CR_PLL2ON) |
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| 131 | /* Reset PLL2ON bit */ |
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| 132 | CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); |
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| 133 | #endif /* RCC_CR_PLL2ON */ |
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| 134 | |||
| 135 | #if defined(RCC_CR_PLL3ON) |
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| 136 | /* Reset PLL3ON bit */ |
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| 137 | CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); |
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| 138 | #endif /* RCC_CR_PLL3ON */ |
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| 139 | |||
| 140 | /* Set HSITRIM bits to the reset value */ |
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| 141 | LL_RCC_HSI_SetCalibTrimming(0x10U); |
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| 142 | |||
| 143 | #if defined(RCC_CFGR2_PREDIV1) |
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| 144 | /* Reset CFGR2 register */ |
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| 145 | LL_RCC_WriteReg(CFGR2, 0x00000000U); |
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| 146 | #endif /* RCC_CFGR2_PREDIV1 */ |
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| 147 | |||
| 148 | /* Disable all interrupts */ |
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| 149 | LL_RCC_WriteReg(CIR, 0x00000000U); |
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| 150 | |||
| 151 | /* Clear reset flags */ |
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| 152 | LL_RCC_ClearResetFlags(); |
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| 153 | |||
| 154 | return SUCCESS; |
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| 155 | } |
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| 156 | |||
| 157 | /** |
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| 158 | * @} |
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| 159 | */ |
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| 160 | |||
| 161 | /** @addtogroup RCC_LL_EF_Get_Freq |
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| 162 | * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
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| 163 | * and different peripheral clocks available on the device. |
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| 164 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) |
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| 165 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) |
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| 166 | * @note If SYSCLK source is PLL, function returns values based on |
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| 167 | * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. |
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| 168 | * @note (**) HSI_VALUE is a defined constant but the real value may vary |
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| 169 | * depending on the variations in voltage and temperature. |
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| 170 | * @note (***) HSE_VALUE is a defined constant, user has to ensure that |
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| 171 | * HSE_VALUE is same as the real frequency of the crystal used. |
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| 172 | * Otherwise, this function may have wrong result. |
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| 173 | * @note The result of this function could be incorrect when using fractional |
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| 174 | * value for HSE crystal. |
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| 175 | * @note This function can be used by the user application to compute the |
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| 176 | * baud-rate for the communication peripherals or configure other parameters. |
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| 177 | * @{ |
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| 178 | */ |
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| 179 | |||
| 180 | /** |
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| 181 | * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
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| 182 | * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function |
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| 183 | * must be called to update structure fields. Otherwise, any |
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| 184 | * configuration based on this function will be incorrect. |
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| 185 | * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies |
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| 186 | * @retval None |
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| 187 | */ |
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| 188 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) |
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| 189 | { |
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| 190 | /* Get SYSCLK frequency */ |
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| 191 | RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); |
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| 192 | |||
| 193 | /* HCLK clock frequency */ |
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| 194 | RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); |
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| 195 | |||
| 196 | /* PCLK1 clock frequency */ |
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| 197 | RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); |
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| 198 | |||
| 199 | /* PCLK2 clock frequency */ |
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| 200 | RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); |
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| 201 | } |
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| 202 | |||
| 203 | #if defined(RCC_CFGR2_I2S2SRC) |
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| 204 | /** |
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| 205 | * @brief Return I2Sx clock frequency |
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| 206 | * @param I2SxSource This parameter can be one of the following values: |
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| 207 | * @arg @ref LL_RCC_I2S2_CLKSOURCE |
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| 208 | * @arg @ref LL_RCC_I2S3_CLKSOURCE |
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| 209 | * @retval I2S clock frequency (in Hz) |
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| 210 | */ |
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| 211 | uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) |
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| 212 | { |
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| 213 | uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
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| 214 | |||
| 215 | /* Check parameter */ |
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| 216 | assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); |
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| 217 | |||
| 218 | /* I2S1CLK clock frequency */ |
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| 219 | switch (LL_RCC_GetI2SClockSource(I2SxSource)) |
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| 220 | { |
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| 221 | case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */ |
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| 222 | case LL_RCC_I2S3_CLKSOURCE_SYSCLK: |
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| 223 | i2s_frequency = RCC_GetSystemClockFreq(); |
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| 224 | break; |
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| 225 | |||
| 226 | case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */ |
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| 227 | case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO: |
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| 228 | default: |
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| 229 | i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U; |
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| 230 | break; |
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| 231 | } |
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| 232 | |||
| 233 | return i2s_frequency; |
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| 234 | } |
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| 235 | #endif /* RCC_CFGR2_I2S2SRC */ |
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| 236 | |||
| 237 | #if defined(USB) || defined(USB_OTG_FS) |
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| 238 | /** |
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| 239 | * @brief Return USBx clock frequency |
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| 240 | * @param USBxSource This parameter can be one of the following values: |
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| 241 | * @arg @ref LL_RCC_USB_CLKSOURCE |
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| 242 | * @retval USB clock frequency (in Hz) |
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| 243 | * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready |
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| 244 | */ |
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| 245 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) |
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| 246 | { |
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| 247 | uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
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| 248 | |||
| 249 | /* Check parameter */ |
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| 250 | assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); |
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| 251 | |||
| 252 | /* USBCLK clock frequency */ |
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| 253 | switch (LL_RCC_GetUSBClockSource(USBxSource)) |
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| 254 | { |
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| 255 | #if defined(RCC_CFGR_USBPRE) |
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| 256 | case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ |
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| 257 | if (LL_RCC_PLL_IsReady()) |
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| 258 | { |
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| 259 | usb_frequency = RCC_PLL_GetFreqDomain_SYS(); |
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| 260 | } |
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| 261 | break; |
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| 262 | |||
| 263 | case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */ |
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| 264 | default: |
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| 265 | if (LL_RCC_PLL_IsReady()) |
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| 266 | { |
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| 267 | usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U; |
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| 268 | } |
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| 269 | break; |
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| 270 | #endif /* RCC_CFGR_USBPRE */ |
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| 271 | #if defined(RCC_CFGR_OTGFSPRE) |
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| 272 | /* USBCLK = PLLVCO/2 |
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| 273 | = (2 x PLLCLK) / 2 |
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| 274 | = PLLCLK */ |
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| 275 | case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */ |
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| 276 | if (LL_RCC_PLL_IsReady()) |
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| 277 | { |
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| 278 | usb_frequency = RCC_PLL_GetFreqDomain_SYS(); |
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| 279 | } |
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| 280 | break; |
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| 281 | |||
| 282 | /* USBCLK = PLLVCO/3 |
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| 283 | = (2 x PLLCLK) / 3 */ |
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| 284 | case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */ |
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| 285 | default: |
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| 286 | if (LL_RCC_PLL_IsReady()) |
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| 287 | { |
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| 288 | usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U; |
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| 289 | } |
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| 290 | break; |
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| 291 | #endif /* RCC_CFGR_OTGFSPRE */ |
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| 292 | } |
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| 293 | |||
| 294 | return usb_frequency; |
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| 295 | } |
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| 296 | #endif /* USB */ |
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| 297 | |||
| 298 | /** |
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| 299 | * @brief Return ADCx clock frequency |
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| 300 | * @param ADCxSource This parameter can be one of the following values: |
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| 301 | * @arg @ref LL_RCC_ADC_CLKSOURCE |
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| 302 | * @retval ADC clock frequency (in Hz) |
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| 303 | */ |
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| 304 | uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) |
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| 305 | { |
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| 306 | uint32_t adc_prescaler = 0U; |
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| 307 | uint32_t adc_frequency = 0U; |
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| 308 | |||
| 309 | /* Check parameter */ |
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| 310 | assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); |
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| 311 | |||
| 312 | /* Get ADC prescaler */ |
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| 313 | adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource); |
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| 314 | |||
| 315 | /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */ |
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| 316 | adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) |
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| 317 | / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U); |
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| 318 | |||
| 319 | return adc_frequency; |
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| 320 | } |
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| 321 | |||
| 322 | /** |
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| 323 | * @} |
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| 324 | */ |
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| 325 | |||
| 326 | /** |
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| 327 | * @} |
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| 328 | */ |
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| 329 | |||
| 330 | /** @addtogroup RCC_LL_Private_Functions |
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| 331 | * @{ |
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| 332 | */ |
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| 333 | |||
| 334 | /** |
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| 335 | * @brief Return SYSTEM clock frequency |
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| 336 | * @retval SYSTEM clock frequency (in Hz) |
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| 337 | */ |
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| 338 | uint32_t RCC_GetSystemClockFreq(void) |
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| 339 | { |
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| 340 | uint32_t frequency = 0U; |
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| 341 | |||
| 342 | /* Get SYSCLK source -------------------------------------------------------*/ |
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| 343 | switch (LL_RCC_GetSysClkSource()) |
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| 344 | { |
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| 345 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ |
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| 346 | frequency = HSI_VALUE; |
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| 347 | break; |
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| 348 | |||
| 349 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ |
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| 350 | frequency = HSE_VALUE; |
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| 351 | break; |
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| 352 | |||
| 353 | case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ |
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| 354 | frequency = RCC_PLL_GetFreqDomain_SYS(); |
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| 355 | break; |
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| 356 | |||
| 357 | default: |
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| 358 | frequency = HSI_VALUE; |
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| 359 | break; |
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| 360 | } |
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| 361 | |||
| 362 | return frequency; |
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| 363 | } |
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| 364 | |||
| 365 | /** |
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| 366 | * @brief Return HCLK clock frequency |
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| 367 | * @param SYSCLK_Frequency SYSCLK clock frequency |
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| 368 | * @retval HCLK clock frequency (in Hz) |
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| 369 | */ |
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| 370 | uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) |
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| 371 | { |
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| 372 | /* HCLK clock frequency */ |
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| 373 | return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); |
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| 374 | } |
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| 375 | |||
| 376 | /** |
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| 377 | * @brief Return PCLK1 clock frequency |
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| 378 | * @param HCLK_Frequency HCLK clock frequency |
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| 379 | * @retval PCLK1 clock frequency (in Hz) |
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| 380 | */ |
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| 381 | uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) |
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| 382 | { |
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| 383 | /* PCLK1 clock frequency */ |
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| 384 | return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); |
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| 385 | } |
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| 386 | |||
| 387 | /** |
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| 388 | * @brief Return PCLK2 clock frequency |
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| 389 | * @param HCLK_Frequency HCLK clock frequency |
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| 390 | * @retval PCLK2 clock frequency (in Hz) |
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| 391 | */ |
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| 392 | uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) |
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| 393 | { |
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| 394 | /* PCLK2 clock frequency */ |
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| 395 | return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); |
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| 396 | } |
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| 397 | |||
| 398 | /** |
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| 399 | * @brief Return PLL clock frequency used for system domain |
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| 400 | * @retval PLL clock frequency (in Hz) |
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| 401 | */ |
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| 402 | uint32_t RCC_PLL_GetFreqDomain_SYS(void) |
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| 403 | { |
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| 404 | uint32_t pllinputfreq = 0U, pllsource = 0U; |
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| 405 | |||
| 406 | /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */ |
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| 407 | |||
| 408 | /* Get PLL source */ |
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| 409 | pllsource = LL_RCC_PLL_GetMainSource(); |
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| 410 | |||
| 411 | switch (pllsource) |
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| 412 | { |
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| 413 | case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ |
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| 414 | pllinputfreq = HSI_VALUE / 2U; |
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| 415 | break; |
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| 416 | |||
| 417 | case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ |
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| 418 | pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U); |
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| 419 | break; |
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| 420 | |||
| 421 | #if defined(RCC_PLL2_SUPPORT) |
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| 422 | case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */ |
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| 423 | pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U); |
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| 424 | break; |
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| 425 | #endif /* RCC_PLL2_SUPPORT */ |
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| 426 | |||
| 427 | default: |
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| 428 | pllinputfreq = HSI_VALUE / 2U; |
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| 429 | break; |
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| 430 | } |
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| 431 | return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator()); |
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| 432 | } |
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| 433 | |||
| 434 | #if defined(RCC_PLL2_SUPPORT) |
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| 435 | /** |
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| 436 | * @brief Return PLL clock frequency used for system domain |
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| 437 | * @retval PLL clock frequency (in Hz) |
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| 438 | */ |
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| 439 | uint32_t RCC_PLL2_GetFreqClockFreq(void) |
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| 440 | { |
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| 441 | return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2()); |
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| 442 | } |
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| 443 | #endif /* RCC_PLL2_SUPPORT */ |
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| 444 | |||
| 445 | #if defined(RCC_PLLI2S_SUPPORT) |
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| 446 | /** |
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| 447 | * @brief Return PLL clock frequency used for system domain |
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| 448 | * @retval PLL clock frequency (in Hz) |
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| 449 | */ |
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| 450 | uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) |
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| 451 | { |
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| 452 | return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2()); |
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| 453 | } |
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| 454 | #endif /* RCC_PLLI2S_SUPPORT */ |
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| 455 | |||
| 456 | /** |
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| 457 | * @} |
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| 458 | */ |
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| 459 | |||
| 460 | /** |
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| 461 | * @} |
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| 462 | */ |
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| 463 | |||
| 464 | #endif /* defined(RCC) */ |
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| 465 | |||
| 466 | /** |
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| 467 | * @} |
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| 468 | */ |
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| 469 | |||
| 470 | #endif /* USE_FULL_LL_DRIVER */ |
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| 471 |