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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_dma.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief DMA LL module driver. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file in |
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| 13 | * the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | */ |
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| 18 | |||
| 19 | #if defined(USE_FULL_LL_DRIVER) |
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| 20 | |||
| 21 | /* Includes ------------------------------------------------------------------*/ |
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| 22 | #include "stm32f1xx_ll_dma.h" |
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| 23 | #include "stm32f1xx_ll_bus.h" |
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| 24 | #ifdef USE_FULL_ASSERT |
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| 25 | #include "stm32_assert.h" |
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| 26 | #else |
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| 27 | #define assert_param(expr) ((void)0U) |
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| 28 | #endif |
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| 29 | |||
| 30 | /** @addtogroup STM32F1xx_LL_Driver |
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| 31 | * @{ |
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| 32 | */ |
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| 33 | |||
| 34 | #if defined (DMA1) || defined (DMA2) |
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| 35 | |||
| 36 | /** @defgroup DMA_LL DMA |
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| 37 | * @{ |
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| 38 | */ |
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| 39 | |||
| 40 | /* Private types -------------------------------------------------------------*/ |
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| 41 | /* Private variables ---------------------------------------------------------*/ |
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| 42 | /* Private constants ---------------------------------------------------------*/ |
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| 43 | /* Private macros ------------------------------------------------------------*/ |
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| 44 | /** @addtogroup DMA_LL_Private_Macros |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ |
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| 48 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ |
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| 49 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) |
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| 50 | |||
| 51 | #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ |
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| 52 | ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) |
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| 53 | |||
| 54 | #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ |
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| 55 | ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) |
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| 56 | |||
| 57 | #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ |
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| 58 | ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) |
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| 59 | |||
| 60 | #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ |
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| 61 | ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ |
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| 62 | ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) |
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| 63 | |||
| 64 | #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ |
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| 65 | ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ |
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| 66 | ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) |
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| 67 | |||
| 68 | #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) |
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| 69 | |||
| 70 | #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ |
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| 71 | ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ |
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| 72 | ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ |
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| 73 | ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) |
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| 74 | |||
| 75 | #if defined (DMA2) |
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| 76 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
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| 77 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 78 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 79 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 80 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 81 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
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| 82 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
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| 83 | ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ |
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| 84 | (((INSTANCE) == DMA2) && \ |
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| 85 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 86 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 87 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 88 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 89 | ((CHANNEL) == LL_DMA_CHANNEL_5)))) |
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| 90 | #else |
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| 91 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
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| 92 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 93 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 94 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 95 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 96 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
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| 97 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
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| 98 | ((CHANNEL) == LL_DMA_CHANNEL_7)))) |
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| 99 | #endif |
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| 100 | /** |
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| 101 | * @} |
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| 102 | */ |
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| 103 | |||
| 104 | /* Private function prototypes -----------------------------------------------*/ |
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| 105 | /* Exported functions --------------------------------------------------------*/ |
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| 106 | /** @addtogroup DMA_LL_Exported_Functions |
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| 107 | * @{ |
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| 108 | */ |
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| 109 | |||
| 110 | /** @addtogroup DMA_LL_EF_Init |
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| 111 | * @{ |
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| 112 | */ |
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| 113 | |||
| 114 | /** |
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| 115 | * @brief De-initialize the DMA registers to their default reset values. |
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| 116 | * @param DMAx DMAx Instance |
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| 117 | * @param Channel This parameter can be one of the following values: |
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| 118 | * @arg @ref LL_DMA_CHANNEL_1 |
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| 119 | * @arg @ref LL_DMA_CHANNEL_2 |
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| 120 | * @arg @ref LL_DMA_CHANNEL_3 |
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| 121 | * @arg @ref LL_DMA_CHANNEL_4 |
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| 122 | * @arg @ref LL_DMA_CHANNEL_5 |
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| 123 | * @arg @ref LL_DMA_CHANNEL_6 |
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| 124 | * @arg @ref LL_DMA_CHANNEL_7 |
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| 125 | * @retval An ErrorStatus enumeration value: |
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| 126 | * - SUCCESS: DMA registers are de-initialized |
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| 127 | * - ERROR: DMA registers are not de-initialized |
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| 128 | */ |
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| 129 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) |
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| 130 | { |
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| 131 | DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; |
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| 132 | ErrorStatus status = SUCCESS; |
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| 133 | |||
| 134 | /* Check the DMA Instance DMAx and Channel parameters*/ |
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| 135 | assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); |
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| 136 | |||
| 137 | tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); |
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| 138 | |||
| 139 | /* Disable the selected DMAx_Channely */ |
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| 140 | CLEAR_BIT(tmp->CCR, DMA_CCR_EN); |
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| 141 | |||
| 142 | /* Reset DMAx_Channely control register */ |
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| 143 | LL_DMA_WriteReg(tmp, CCR, 0U); |
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| 144 | |||
| 145 | /* Reset DMAx_Channely remaining bytes register */ |
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| 146 | LL_DMA_WriteReg(tmp, CNDTR, 0U); |
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| 147 | |||
| 148 | /* Reset DMAx_Channely peripheral address register */ |
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| 149 | LL_DMA_WriteReg(tmp, CPAR, 0U); |
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| 150 | |||
| 151 | /* Reset DMAx_Channely memory address register */ |
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| 152 | LL_DMA_WriteReg(tmp, CMAR, 0U); |
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| 153 | |||
| 154 | if (Channel == LL_DMA_CHANNEL_1) |
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| 155 | { |
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| 156 | /* Reset interrupt pending bits for DMAx Channel1 */ |
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| 157 | LL_DMA_ClearFlag_GI1(DMAx); |
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| 158 | } |
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| 159 | else if (Channel == LL_DMA_CHANNEL_2) |
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| 160 | { |
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| 161 | /* Reset interrupt pending bits for DMAx Channel2 */ |
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| 162 | LL_DMA_ClearFlag_GI2(DMAx); |
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| 163 | } |
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| 164 | else if (Channel == LL_DMA_CHANNEL_3) |
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| 165 | { |
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| 166 | /* Reset interrupt pending bits for DMAx Channel3 */ |
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| 167 | LL_DMA_ClearFlag_GI3(DMAx); |
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| 168 | } |
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| 169 | else if (Channel == LL_DMA_CHANNEL_4) |
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| 170 | { |
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| 171 | /* Reset interrupt pending bits for DMAx Channel4 */ |
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| 172 | LL_DMA_ClearFlag_GI4(DMAx); |
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| 173 | } |
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| 174 | else if (Channel == LL_DMA_CHANNEL_5) |
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| 175 | { |
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| 176 | /* Reset interrupt pending bits for DMAx Channel5 */ |
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| 177 | LL_DMA_ClearFlag_GI5(DMAx); |
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| 178 | } |
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| 179 | |||
| 180 | else if (Channel == LL_DMA_CHANNEL_6) |
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| 181 | { |
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| 182 | /* Reset interrupt pending bits for DMAx Channel6 */ |
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| 183 | LL_DMA_ClearFlag_GI6(DMAx); |
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| 184 | } |
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| 185 | else if (Channel == LL_DMA_CHANNEL_7) |
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| 186 | { |
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| 187 | /* Reset interrupt pending bits for DMAx Channel7 */ |
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| 188 | LL_DMA_ClearFlag_GI7(DMAx); |
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| 189 | } |
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| 190 | else |
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| 191 | { |
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| 192 | status = ERROR; |
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| 193 | } |
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| 194 | |||
| 195 | return status; |
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| 196 | } |
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| 197 | |||
| 198 | /** |
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| 199 | * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. |
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| 200 | * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : |
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| 201 | * @arg @ref __LL_DMA_GET_INSTANCE |
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| 202 | * @arg @ref __LL_DMA_GET_CHANNEL |
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| 203 | * @param DMAx DMAx Instance |
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| 204 | * @param Channel This parameter can be one of the following values: |
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| 205 | * @arg @ref LL_DMA_CHANNEL_1 |
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| 206 | * @arg @ref LL_DMA_CHANNEL_2 |
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| 207 | * @arg @ref LL_DMA_CHANNEL_3 |
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| 208 | * @arg @ref LL_DMA_CHANNEL_4 |
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| 209 | * @arg @ref LL_DMA_CHANNEL_5 |
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| 210 | * @arg @ref LL_DMA_CHANNEL_6 |
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| 211 | * @arg @ref LL_DMA_CHANNEL_7 |
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| 212 | * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. |
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| 213 | * @retval An ErrorStatus enumeration value: |
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| 214 | * - SUCCESS: DMA registers are initialized |
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| 215 | * - ERROR: Not applicable |
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| 216 | */ |
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| 217 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) |
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| 218 | { |
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| 219 | /* Check the DMA Instance DMAx and Channel parameters*/ |
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| 220 | assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); |
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| 221 | |||
| 222 | /* Check the DMA parameters from DMA_InitStruct */ |
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| 223 | assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); |
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| 224 | assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); |
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| 225 | assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); |
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| 226 | assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); |
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| 227 | assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); |
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| 228 | assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); |
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| 229 | assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); |
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| 230 | assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); |
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| 231 | |||
| 232 | /*---------------------------- DMAx CCR Configuration ------------------------ |
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| 233 | * Configure DMAx_Channely: data transfer direction, data transfer mode, |
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| 234 | * peripheral and memory increment mode, |
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| 235 | * data size alignment and priority level with parameters : |
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| 236 | * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits |
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| 237 | * - Mode: DMA_CCR_CIRC bit |
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| 238 | * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit |
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| 239 | * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit |
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| 240 | * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits |
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| 241 | * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits |
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| 242 | * - Priority: DMA_CCR_PL[1:0] bits |
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| 243 | */ |
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| 244 | LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ |
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| 245 | DMA_InitStruct->Mode | \ |
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| 246 | DMA_InitStruct->PeriphOrM2MSrcIncMode | \ |
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| 247 | DMA_InitStruct->MemoryOrM2MDstIncMode | \ |
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| 248 | DMA_InitStruct->PeriphOrM2MSrcDataSize | \ |
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| 249 | DMA_InitStruct->MemoryOrM2MDstDataSize | \ |
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| 250 | DMA_InitStruct->Priority); |
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| 251 | |||
| 252 | /*-------------------------- DMAx CMAR Configuration ------------------------- |
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| 253 | * Configure the memory or destination base address with parameter : |
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| 254 | * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits |
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| 255 | */ |
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| 256 | LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); |
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| 257 | |||
| 258 | /*-------------------------- DMAx CPAR Configuration ------------------------- |
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| 259 | * Configure the peripheral or source base address with parameter : |
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| 260 | * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits |
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| 261 | */ |
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| 262 | LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); |
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| 263 | |||
| 264 | /*--------------------------- DMAx CNDTR Configuration ----------------------- |
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| 265 | * Configure the peripheral base address with parameter : |
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| 266 | * - NbData: DMA_CNDTR_NDT[15:0] bits |
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| 267 | */ |
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| 268 | LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); |
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| 269 | |||
| 270 | return SUCCESS; |
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| 271 | } |
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| 272 | |||
| 273 | /** |
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| 274 | * @brief Set each @ref LL_DMA_InitTypeDef field to default value. |
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| 275 | * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. |
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| 276 | * @retval None |
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| 277 | */ |
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| 278 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) |
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| 279 | { |
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| 280 | /* Set DMA_InitStruct fields to default values */ |
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| 281 | DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; |
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| 282 | DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; |
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| 283 | DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
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| 284 | DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; |
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| 285 | DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
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| 286 | DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; |
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| 287 | DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
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| 288 | DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
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| 289 | DMA_InitStruct->NbData = 0x00000000U; |
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| 290 | DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; |
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| 291 | } |
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| 292 | |||
| 293 | /** |
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| 294 | * @} |
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| 295 | */ |
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| 296 | |||
| 297 | /** |
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| 298 | * @} |
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| 299 | */ |
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| 300 | |||
| 301 | /** |
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| 302 | * @} |
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| 303 | */ |
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| 304 | |||
| 305 | #endif /* DMA1 || DMA2 */ |
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| 306 | |||
| 307 | /** |
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| 308 | * @} |
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| 309 | */ |
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| 310 | |||
| 311 | #endif /* USE_FULL_LL_DRIVER */ |
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| 312 |