WebSVN – canSerial – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_dma.c
		4	* @author MCD Application Team
		5	* @brief DMA LL module driver.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	#if defined(USE_FULL_LL_DRIVER)
		21
		22	/* Includes ------------------------------------------------------------------*/
		23	#include "stm32f1xx_ll_dma.h"
		24	#include "stm32f1xx_ll_bus.h"
		25	#ifdef USE_FULL_ASSERT
		26	#include "stm32_assert.h"
		27	#else
		28	#define assert_param(expr) ((void)0U)
		29	#endif
		30
		31	/** @addtogroup STM32F1xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (DMA1) \|\| defined (DMA2)
		36
		37	/** @defgroup DMA_LL DMA
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/* Private constants ---------------------------------------------------------*/
		44	/* Private macros ------------------------------------------------------------*/
		45	/** @addtogroup DMA_LL_Private_Macros
		46	* @{
		47	*/
		48	#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) \|\| \
		49	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) \|\| \
		50	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
		51
		52	#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) \|\| \
		53	((__VALUE__) == LL_DMA_MODE_CIRCULAR))
		54
		55	#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) \|\| \
		56	((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
		57
		58	#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) \|\| \
		59	((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
		60
		61	#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) \|\| \
		62	((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) \|\| \
		63	((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
		64
		65	#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) \|\| \
		66	((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) \|\| \
		67	((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
		68
		69	#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
		70
		71	#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) \|\| \
		72	((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) \|\| \
		73	((__VALUE__) == LL_DMA_PRIORITY_HIGH) \|\| \
		74	((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
		75
		76	#if defined (DMA2)
		77	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		78	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		79	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		80	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		81	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		82	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		83	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		84	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
		85	(((INSTANCE) == DMA2) && \
		86	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		87	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		88	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		89	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		90	((CHANNEL) == LL_DMA_CHANNEL_5))))
		91	#else
		92	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		93	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		94	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		95	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		96	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		97	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		98	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		99	((CHANNEL) == LL_DMA_CHANNEL_7))))
		100	#endif
		101	/**
		102	* @}
		103	*/
		104
		105	/* Private function prototypes -----------------------------------------------*/
		106	/* Exported functions --------------------------------------------------------*/
		107	/** @addtogroup DMA_LL_Exported_Functions
		108	* @{
		109	*/
		110
		111	/** @addtogroup DMA_LL_EF_Init
		112	* @{
		113	*/
		114
		115	/**
		116	* @brief De-initialize the DMA registers to their default reset values.
		117	* @param DMAx DMAx Instance
		118	* @param Channel This parameter can be one of the following values:
		119	* @arg @ref LL_DMA_CHANNEL_1
		120	* @arg @ref LL_DMA_CHANNEL_2
		121	* @arg @ref LL_DMA_CHANNEL_3
		122	* @arg @ref LL_DMA_CHANNEL_4
		123	* @arg @ref LL_DMA_CHANNEL_5
		124	* @arg @ref LL_DMA_CHANNEL_6
		125	* @arg @ref LL_DMA_CHANNEL_7
		126	* @retval An ErrorStatus enumeration value:
		127	* - SUCCESS: DMA registers are de-initialized
		128	* - ERROR: DMA registers are not de-initialized
		129	*/
		130	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
		131	{
		132	DMA_Channel_TypeDef tmp = (DMA_Channel_TypeDef )DMA1_Channel1;
		133	ErrorStatus status = SUCCESS;
		134
		135	/* Check the DMA Instance DMAx and Channel parameters*/
		136	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
		137
		138	tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
		139
		140	/* Disable the selected DMAx_Channely */
		141	CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
		142
		143	/* Reset DMAx_Channely control register */
		144	LL_DMA_WriteReg(tmp, CCR, 0U);
		145
		146	/* Reset DMAx_Channely remaining bytes register */
		147	LL_DMA_WriteReg(tmp, CNDTR, 0U);
		148
		149	/* Reset DMAx_Channely peripheral address register */
		150	LL_DMA_WriteReg(tmp, CPAR, 0U);
		151
		152	/* Reset DMAx_Channely memory address register */
		153	LL_DMA_WriteReg(tmp, CMAR, 0U);
		154
		155	if (Channel == LL_DMA_CHANNEL_1)
		156	{
		157	/* Reset interrupt pending bits for DMAx Channel1 */
		158	LL_DMA_ClearFlag_GI1(DMAx);
		159	}
		160	else if (Channel == LL_DMA_CHANNEL_2)
		161	{
		162	/* Reset interrupt pending bits for DMAx Channel2 */
		163	LL_DMA_ClearFlag_GI2(DMAx);
		164	}
		165	else if (Channel == LL_DMA_CHANNEL_3)
		166	{
		167	/* Reset interrupt pending bits for DMAx Channel3 */
		168	LL_DMA_ClearFlag_GI3(DMAx);
		169	}
		170	else if (Channel == LL_DMA_CHANNEL_4)
		171	{
		172	/* Reset interrupt pending bits for DMAx Channel4 */
		173	LL_DMA_ClearFlag_GI4(DMAx);
		174	}
		175	else if (Channel == LL_DMA_CHANNEL_5)
		176	{
		177	/* Reset interrupt pending bits for DMAx Channel5 */
		178	LL_DMA_ClearFlag_GI5(DMAx);
		179	}
		180
		181	else if (Channel == LL_DMA_CHANNEL_6)
		182	{
		183	/* Reset interrupt pending bits for DMAx Channel6 */
		184	LL_DMA_ClearFlag_GI6(DMAx);
		185	}
		186	else if (Channel == LL_DMA_CHANNEL_7)
		187	{
		188	/* Reset interrupt pending bits for DMAx Channel7 */
		189	LL_DMA_ClearFlag_GI7(DMAx);
		190	}
		191	else
		192	{
		193	status = ERROR;
		194	}
		195
		196	return status;
		197	}
		198
		199	/**
		200	* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
		201	* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
		202	* @arg @ref __LL_DMA_GET_INSTANCE
		203	* @arg @ref __LL_DMA_GET_CHANNEL
		204	* @param DMAx DMAx Instance
		205	* @param Channel This parameter can be one of the following values:
		206	* @arg @ref LL_DMA_CHANNEL_1
		207	* @arg @ref LL_DMA_CHANNEL_2
		208	* @arg @ref LL_DMA_CHANNEL_3
		209	* @arg @ref LL_DMA_CHANNEL_4
		210	* @arg @ref LL_DMA_CHANNEL_5
		211	* @arg @ref LL_DMA_CHANNEL_6
		212	* @arg @ref LL_DMA_CHANNEL_7
		213	* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
		214	* @retval An ErrorStatus enumeration value:
		215	* - SUCCESS: DMA registers are initialized
		216	* - ERROR: Not applicable
		217	*/
		218	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct)
		219	{
		220	/* Check the DMA Instance DMAx and Channel parameters*/
		221	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
		222
		223	/* Check the DMA parameters from DMA_InitStruct */
		224	assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
		225	assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
		226	assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
		227	assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
		228	assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
		229	assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
		230	assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
		231	assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
		232
		233	/*---------------------------- DMAx CCR Configuration ------------------------
		234	* Configure DMAx_Channely: data transfer direction, data transfer mode,
		235	* peripheral and memory increment mode,
		236	* data size alignment and priority level with parameters :
		237	* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
		238	* - Mode: DMA_CCR_CIRC bit
		239	* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
		240	* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
		241	* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
		242	* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
		243	* - Priority: DMA_CCR_PL[1:0] bits
		244	*/
		245	LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction \| \
		246	DMA_InitStruct->Mode \| \
		247	DMA_InitStruct->PeriphOrM2MSrcIncMode \| \
		248	DMA_InitStruct->MemoryOrM2MDstIncMode \| \
		249	DMA_InitStruct->PeriphOrM2MSrcDataSize \| \
		250	DMA_InitStruct->MemoryOrM2MDstDataSize \| \
		251	DMA_InitStruct->Priority);
		252
		253	/*-------------------------- DMAx CMAR Configuration -------------------------
		254	* Configure the memory or destination base address with parameter :
		255	* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
		256	*/
		257	LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
		258
		259	/*-------------------------- DMAx CPAR Configuration -------------------------
		260	* Configure the peripheral or source base address with parameter :
		261	* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
		262	*/
		263	LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
		264
		265	/*--------------------------- DMAx CNDTR Configuration -----------------------
		266	* Configure the peripheral base address with parameter :
		267	* - NbData: DMA_CNDTR_NDT[15:0] bits
		268	*/
		269	LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
		270
		271	return SUCCESS;
		272	}
		273
		274	/**
		275	* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
		276	* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
		277	* @retval None
		278	*/
		279	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
		280	{
		281	/* Set DMA_InitStruct fields to default values */
		282	DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
		283	DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
		284	DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
		285	DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
		286	DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
		287	DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
		288	DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
		289	DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
		290	DMA_InitStruct->NbData = 0x00000000U;
		291	DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
		292	}
		293
		294	/**
		295	* @}
		296	*/
		297
		298	/**
		299	* @}
		300	*/
		301
		302	/**
		303	* @}
		304	*/
		305
		306	#endif /* DMA1 \|\| DMA2 */
		307
		308	/**
		309	* @}
		310	*/
		311
		312	#endif /* USE_FULL_LL_DRIVER */
		313
		314	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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