WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_dma.c
		4	* @author MCD Application Team
		5	* @brief DMA LL module driver.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35	#if defined(USE_FULL_LL_DRIVER)
		36
		37	/* Includes ------------------------------------------------------------------*/
		38	#include "stm32f1xx_ll_dma.h"
		39	#include "stm32f1xx_ll_bus.h"
		40	#ifdef USE_FULL_ASSERT
		41	#include "stm32_assert.h"
		42	#else
		43	#define assert_param(expr) ((void)0U)
		44	#endif
		45
		46	/** @addtogroup STM32F1xx_LL_Driver
		47	* @{
		48	*/
		49
		50	#if defined (DMA1) \|\| defined (DMA2)
		51
		52	/** @defgroup DMA_LL DMA
		53	* @{
		54	*/
		55
		56	/* Private types -------------------------------------------------------------*/
		57	/* Private variables ---------------------------------------------------------*/
		58	/* Private constants ---------------------------------------------------------*/
		59	/* Private macros ------------------------------------------------------------*/
		60	/** @addtogroup DMA_LL_Private_Macros
		61	* @{
		62	*/
		63	#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) \|\| \
		64	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) \|\| \
		65	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
		66
		67	#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) \|\| \
		68	((__VALUE__) == LL_DMA_MODE_CIRCULAR))
		69
		70	#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) \|\| \
		71	((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
		72
		73	#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) \|\| \
		74	((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
		75
		76	#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) \|\| \
		77	((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) \|\| \
		78	((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
		79
		80	#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) \|\| \
		81	((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) \|\| \
		82	((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
		83
		84	#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
		85
		86	#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) \|\| \
		87	((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) \|\| \
		88	((__VALUE__) == LL_DMA_PRIORITY_HIGH) \|\| \
		89	((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
		90
		91	#if defined (DMA2)
		92	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		93	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		94	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		95	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		96	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		97	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		98	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		99	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
		100	(((INSTANCE) == DMA2) && \
		101	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		102	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		103	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		104	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		105	((CHANNEL) == LL_DMA_CHANNEL_5))))
		106	#else
		107	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		108	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		109	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		110	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		111	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		112	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		113	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		114	((CHANNEL) == LL_DMA_CHANNEL_7))))
		115	#endif
		116	/**
		117	* @}
		118	*/
		119
		120	/* Private function prototypes -----------------------------------------------*/
		121	/* Exported functions --------------------------------------------------------*/
		122	/** @addtogroup DMA_LL_Exported_Functions
		123	* @{
		124	*/
		125
		126	/** @addtogroup DMA_LL_EF_Init
		127	* @{
		128	*/
		129
		130	/**
		131	* @brief De-initialize the DMA registers to their default reset values.
		132	* @param DMAx DMAx Instance
		133	* @param Channel This parameter can be one of the following values:
		134	* @arg @ref LL_DMA_CHANNEL_1
		135	* @arg @ref LL_DMA_CHANNEL_2
		136	* @arg @ref LL_DMA_CHANNEL_3
		137	* @arg @ref LL_DMA_CHANNEL_4
		138	* @arg @ref LL_DMA_CHANNEL_5
		139	* @arg @ref LL_DMA_CHANNEL_6
		140	* @arg @ref LL_DMA_CHANNEL_7
		141	* @retval An ErrorStatus enumeration value:
		142	* - SUCCESS: DMA registers are de-initialized
		143	* - ERROR: DMA registers are not de-initialized
		144	*/
		145	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
		146	{
		147	DMA_Channel_TypeDef tmp = (DMA_Channel_TypeDef )DMA1_Channel1;
		148	ErrorStatus status = SUCCESS;
		149
		150	/* Check the DMA Instance DMAx and Channel parameters*/
		151	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
		152
		153	tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
		154
		155	/* Disable the selected DMAx_Channely */
		156	CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
		157
		158	/* Reset DMAx_Channely control register */
		159	LL_DMA_WriteReg(tmp, CCR, 0U);
		160
		161	/* Reset DMAx_Channely remaining bytes register */
		162	LL_DMA_WriteReg(tmp, CNDTR, 0U);
		163
		164	/* Reset DMAx_Channely peripheral address register */
		165	LL_DMA_WriteReg(tmp, CPAR, 0U);
		166
		167	/* Reset DMAx_Channely memory address register */
		168	LL_DMA_WriteReg(tmp, CMAR, 0U);
		169
		170	if (Channel == LL_DMA_CHANNEL_1)
		171	{
		172	/* Reset interrupt pending bits for DMAx Channel1 */
		173	LL_DMA_ClearFlag_GI1(DMAx);
		174	}
		175	else if (Channel == LL_DMA_CHANNEL_2)
		176	{
		177	/* Reset interrupt pending bits for DMAx Channel2 */
		178	LL_DMA_ClearFlag_GI2(DMAx);
		179	}
		180	else if (Channel == LL_DMA_CHANNEL_3)
		181	{
		182	/* Reset interrupt pending bits for DMAx Channel3 */
		183	LL_DMA_ClearFlag_GI3(DMAx);
		184	}
		185	else if (Channel == LL_DMA_CHANNEL_4)
		186	{
		187	/* Reset interrupt pending bits for DMAx Channel4 */
		188	LL_DMA_ClearFlag_GI4(DMAx);
		189	}
		190	else if (Channel == LL_DMA_CHANNEL_5)
		191	{
		192	/* Reset interrupt pending bits for DMAx Channel5 */
		193	LL_DMA_ClearFlag_GI5(DMAx);
		194	}
		195
		196	else if (Channel == LL_DMA_CHANNEL_6)
		197	{
		198	/* Reset interrupt pending bits for DMAx Channel6 */
		199	LL_DMA_ClearFlag_GI6(DMAx);
		200	}
		201	else if (Channel == LL_DMA_CHANNEL_7)
		202	{
		203	/* Reset interrupt pending bits for DMAx Channel7 */
		204	LL_DMA_ClearFlag_GI7(DMAx);
		205	}
		206	else
		207	{
		208	status = ERROR;
		209	}
		210
		211	return status;
		212	}
		213
		214	/**
		215	* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
		216	* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
		217	* @arg @ref __LL_DMA_GET_INSTANCE
		218	* @arg @ref __LL_DMA_GET_CHANNEL
		219	* @param DMAx DMAx Instance
		220	* @param Channel This parameter can be one of the following values:
		221	* @arg @ref LL_DMA_CHANNEL_1
		222	* @arg @ref LL_DMA_CHANNEL_2
		223	* @arg @ref LL_DMA_CHANNEL_3
		224	* @arg @ref LL_DMA_CHANNEL_4
		225	* @arg @ref LL_DMA_CHANNEL_5
		226	* @arg @ref LL_DMA_CHANNEL_6
		227	* @arg @ref LL_DMA_CHANNEL_7
		228	* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
		229	* @retval An ErrorStatus enumeration value:
		230	* - SUCCESS: DMA registers are initialized
		231	* - ERROR: Not applicable
		232	*/
		233	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct)
		234	{
		235	/* Check the DMA Instance DMAx and Channel parameters*/
		236	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
		237
		238	/* Check the DMA parameters from DMA_InitStruct */
		239	assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
		240	assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
		241	assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
		242	assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
		243	assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
		244	assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
		245	assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
		246	assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
		247
		248	/*---------------------------- DMAx CCR Configuration ------------------------
		249	* Configure DMAx_Channely: data transfer direction, data transfer mode,
		250	* peripheral and memory increment mode,
		251	* data size alignment and priority level with parameters :
		252	* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
		253	* - Mode: DMA_CCR_CIRC bit
		254	* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
		255	* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
		256	* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
		257	* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
		258	* - Priority: DMA_CCR_PL[1:0] bits
		259	*/
		260	LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction \| \
		261	DMA_InitStruct->Mode \| \
		262	DMA_InitStruct->PeriphOrM2MSrcIncMode \| \
		263	DMA_InitStruct->MemoryOrM2MDstIncMode \| \
		264	DMA_InitStruct->PeriphOrM2MSrcDataSize \| \
		265	DMA_InitStruct->MemoryOrM2MDstDataSize \| \
		266	DMA_InitStruct->Priority);
		267
		268	/*-------------------------- DMAx CMAR Configuration -------------------------
		269	* Configure the memory or destination base address with parameter :
		270	* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
		271	*/
		272	LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
		273
		274	/*-------------------------- DMAx CPAR Configuration -------------------------
		275	* Configure the peripheral or source base address with parameter :
		276	* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
		277	*/
		278	LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
		279
		280	/*--------------------------- DMAx CNDTR Configuration -----------------------
		281	* Configure the peripheral base address with parameter :
		282	* - NbData: DMA_CNDTR_NDT[15:0] bits
		283	*/
		284	LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
		285
		286	return SUCCESS;
		287	}
		288
		289	/**
		290	* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
		291	* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
		292	* @retval None
		293	*/
		294	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
		295	{
		296	/* Set DMA_InitStruct fields to default values */
		297	DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
		298	DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
		299	DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
		300	DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
		301	DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
		302	DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
		303	DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
		304	DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
		305	DMA_InitStruct->NbData = 0x00000000U;
		306	DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
		307	}
		308
		309	/**
		310	* @}
		311	*/
		312
		313	/**
		314	* @}
		315	*/
		316
		317	/**
		318	* @}
		319	*/
		320
		321	#endif /* DMA1 \|\| DMA2 */
		322
		323	/**
		324	* @}
		325	*/
		326
		327	#endif /* USE_FULL_LL_DRIVER */
		328
		329	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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