WebSVN – dashGPS – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_adc.c
		4	* @author MCD Application Team
		5	* @brief ADC LL module driver
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	#if defined(USE_FULL_LL_DRIVER)
		21
		22	/* Includes ------------------------------------------------------------------*/
		23	#include "stm32f1xx_ll_adc.h"
		24	#include "stm32f1xx_ll_bus.h"
		25
		26	#ifdef USE_FULL_ASSERT
		27	#include "stm32_assert.h"
		28	#else
		29	#define assert_param(expr) ((void)0U)
		30	#endif
		31
		32	/** @addtogroup STM32F1xx_LL_Driver
		33	* @{
		34	*/
		35
		36	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
		37
		38	/** @addtogroup ADC_LL ADC
		39	* @{
		40	*/
		41
		42	/* Private types -------------------------------------------------------------*/
		43	/* Private variables ---------------------------------------------------------*/
		44	/* Private constants ---------------------------------------------------------*/
		45	/* Private macros ------------------------------------------------------------*/
		46
		47	/** @addtogroup ADC_LL_Private_Macros
		48	* @{
		49	*/
		50
		51	/* Check of parameters for configuration of ADC hierarchical scope: */
		52	/* common to several ADC instances. */
		53	/* Check of parameters for configuration of ADC hierarchical scope: */
		54	/* ADC instance. */
		55	#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
		56	( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
		57	\|\| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
		58	)
		59
		60	#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
		61	( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
		62	\|\| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
		63	)
		64
		65	#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
		66	( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
		67	\|\| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
		68	)
		69
		70	/* Check of parameters for configuration of ADC hierarchical scope: */
		71	/* ADC group regular */
		72	#if defined(ADC3)
		73	#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
		74	((((__ADC_INSTANCE__) == ADC1) \|\| ((__ADC_INSTANCE__) == ADC2)) \
		75	? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
		76	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
		77	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
		78	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
		79	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
		80	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
		81	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
		82	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
		83	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
		84	) \
		85	: \
		86	( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
		87	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
		88	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
		89	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
		90	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
		91	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \
		92	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
		93	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
		94	) \
		95	)
		96	#else
		97	#if defined (STM32F101xE) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
		98	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
		99	( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
		100	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
		101	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
		102	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
		103	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
		104	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
		105	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
		106	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
		107	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
		108	)
		109	#else
		110	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
		111	( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
		112	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
		113	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
		114	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
		115	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
		116	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
		117	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
		118	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
		119	)
		120	#endif
		121	#endif
		122	#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
		123	( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
		124	\|\| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
		125	)
		126
		127	#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
		128	( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
		129	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
		130	)
		131
		132	#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
		133	( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
		134	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
		135	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
		136	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
		137	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
		138	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
		139	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
		140	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
		141	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
		142	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
		143	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
		144	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
		145	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
		146	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
		147	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
		148	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
		149	)
		150
		151	#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
		152	( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
		153	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
		154	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
		155	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
		156	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
		157	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
		158	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
		159	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
		160	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
		161	)
		162
		163	/* Check of parameters for configuration of ADC hierarchical scope: */
		164	/* ADC group injected */
		165	#if defined(ADC3)
		166	#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
		167	((((__ADC_INSTANCE__) == ADC1) \|\| ((__ADC_INSTANCE__) == ADC2)) \
		168	? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
		169	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
		170	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
		171	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
		172	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
		173	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
		174	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
		175	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
		176	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
		177	) \
		178	: \
		179	( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
		180	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
		181	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
		182	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
		183	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
		184	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \
		185	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
		186	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
		187	) \
		188	)
		189	#else
		190	#if defined (STM32F101xE) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
		191	#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
		192	( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
		193	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
		194	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
		195	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
		196	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
		197	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
		198	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
		199	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
		200	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
		201	)
		202	#else
		203	#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
		204	( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
		205	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
		206	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
		207	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
		208	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
		209	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
		210	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
		211	\|\| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
		212	)
		213	#endif
		214	#endif
		215	#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
		216	( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
		217	\|\| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
		218	)
		219
		220	#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
		221	( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
		222	\|\| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
		223	\|\| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
		224	\|\| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
		225	)
		226
		227	#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
		228	( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
		229	\|\| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
		230	)
		231
		232	#if defined(ADC_MULTIMODE_SUPPORT)
		233	/* Check of parameters for configuration of ADC hierarchical scope: */
		234	/* multimode. */
		235	#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
		236	( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
		237	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
		238	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \
		239	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \
		240	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
		241	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
		242	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
		243	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
		244	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \
		245	\|\| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \
		246	)
		247
		248	#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
		249	( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
		250	\|\| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
		251	\|\| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
		252	)
		253
		254	#endif /* ADC_MULTIMODE_SUPPORT */
		255	/**
		256	* @}
		257	*/
		258
		259
		260	/* Private function prototypes -----------------------------------------------*/
		261
		262	/* Exported functions --------------------------------------------------------*/
		263	/** @addtogroup ADC_LL_Exported_Functions
		264	* @{
		265	*/
		266
		267	/** @addtogroup ADC_LL_EF_Init
		268	* @{
		269	*/
		270
		271	/**
		272	* @brief De-initialize registers of all ADC instances belonging to
		273	* the same ADC common instance to their default reset values.
		274	* @param ADCxy_COMMON ADC common instance
		275	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		276	* @retval An ErrorStatus enumeration value:
		277	* - SUCCESS: ADC common registers are de-initialized
		278	* - ERROR: not applicable
		279	*/
		280	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
		281	{
		282	/* Check the parameters */
		283	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
		284
		285	/* Force reset of ADC clock (core clock) */
		286	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
		287
		288	/* Release reset of ADC clock (core clock) */
		289	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
		290
		291	return SUCCESS;
		292	}
		293
		294	/**
		295	* @brief Initialize some features of ADC common parameters
		296	* (all ADC instances belonging to the same ADC common instance)
		297	* and multimode (for devices with several ADC instances available).
		298	* @note The setting of ADC common parameters is conditioned to
		299	* ADC instances state:
		300	* All ADC instances belonging to the same ADC common instance
		301	* must be disabled.
		302	* @param ADCxy_COMMON ADC common instance
		303	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		304	* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
		305	* @retval An ErrorStatus enumeration value:
		306	* - SUCCESS: ADC common registers are initialized
		307	* - ERROR: ADC common registers are not initialized
		308	*/
		309	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct)
		310	{
		311	ErrorStatus status = SUCCESS;
		312
		313	/* Check the parameters */
		314	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
		315	#if defined(ADC_MULTIMODE_SUPPORT)
		316	assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
		317	#endif /* ADC_MULTIMODE_SUPPORT */
		318
		319	/* Note: Hardware constraint (refer to description of functions */
		320	/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
		321	/* On this STM32 serie, setting of these features is conditioned to */
		322	/* ADC state: */
		323	/* All ADC instances of the ADC common group must be disabled. */
		324	if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
		325	{
		326	/* Configuration of ADC hierarchical scope: */
		327	/* - common to several ADC */
		328	/* (all ADC instances belonging to the same ADC common instance) */
		329	/* - multimode (if several ADC instances available on the */
		330	/* selected device) */
		331	/* - Set ADC multimode configuration */
		332	/* - Set ADC multimode DMA transfer */
		333	/* - Set ADC multimode: delay between 2 sampling phases */
		334	#if defined(ADC_MULTIMODE_SUPPORT)
		335	if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
		336	{
		337	MODIFY_REG(ADCxy_COMMON->CR1,
		338	ADC_CR1_DUALMOD,
		339	ADC_CommonInitStruct->Multimode
		340	);
		341	}
		342	else
		343	{
		344	MODIFY_REG(ADCxy_COMMON->CR1,
		345	ADC_CR1_DUALMOD,
		346	LL_ADC_MULTI_INDEPENDENT
		347	);
		348	}
		349	#endif
		350	}
		351	else
		352	{
		353	/* Initialization error: One or several ADC instances belonging to */
		354	/* the same ADC common instance are not disabled. */
		355	status = ERROR;
		356	}
		357
		358	return status;
		359	}
		360
		361	/**
		362	* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
		363	* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
		364	* whose fields will be set to default values.
		365	* @retval None
		366	*/
		367	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
		368	{
		369	/* Set ADC_CommonInitStruct fields to default values */
		370	/* Set fields of ADC common */
		371	/* (all ADC instances belonging to the same ADC common instance) */
		372
		373	#if defined(ADC_MULTIMODE_SUPPORT)
		374	/* Set fields of ADC multimode */
		375	ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
		376	#endif /* ADC_MULTIMODE_SUPPORT */
		377	}
		378
		379	/**
		380	* @brief De-initialize registers of the selected ADC instance
		381	* to their default reset values.
		382	* @note To reset all ADC instances quickly (perform a hard reset),
		383	* use function @ref LL_ADC_CommonDeInit().
		384	* @param ADCx ADC instance
		385	* @retval An ErrorStatus enumeration value:
		386	* - SUCCESS: ADC registers are de-initialized
		387	* - ERROR: ADC registers are not de-initialized
		388	*/
		389	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
		390	{
		391	ErrorStatus status = SUCCESS;
		392
		393	/* Check the parameters */
		394	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		395
		396	/* Disable ADC instance if not already disabled. */
		397	if(LL_ADC_IsEnabled(ADCx) == 1U)
		398	{
		399	/* Set ADC group regular trigger source to SW start to ensure to not */
		400	/* have an external trigger event occurring during the conversion stop */
		401	/* ADC disable process. */
		402	LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
		403
		404	/* Set ADC group injected trigger source to SW start to ensure to not */
		405	/* have an external trigger event occurring during the conversion stop */
		406	/* ADC disable process. */
		407	LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
		408
		409	/* Disable the ADC instance */
		410	LL_ADC_Disable(ADCx);
		411	}
		412
		413	/* Check whether ADC state is compliant with expected state */
		414	/* (hardware requirements of bits state to reset registers below) */
		415	if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
		416	{
		417	/* ========== Reset ADC registers ========== */
		418	/* Reset register SR */
		419	CLEAR_BIT(ADCx->SR,
		420	( LL_ADC_FLAG_STRT
		421	\| LL_ADC_FLAG_JSTRT
		422	\| LL_ADC_FLAG_EOS
		423	\| LL_ADC_FLAG_JEOS
		424	\| LL_ADC_FLAG_AWD1 )
		425	);
		426
		427	/* Reset register CR1 */
		428	#if defined (STM32F103x6) \|\| defined (STM32F103xB) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG)
		429
		430	CLEAR_BIT(ADCx->CR1,
		431	( ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_DUALMOD
		432	\| ADC_CR1_DISCNUM \| ADC_CR1_JDISCEN \| ADC_CR1_DISCEN
		433	\| ADC_CR1_JAUTO \| ADC_CR1_AWDSGL \| ADC_CR1_SCAN
		434	\| ADC_CR1_JEOCIE \| ADC_CR1_AWDIE \| ADC_CR1_EOCIE
		435	\| ADC_CR1_AWDCH )
		436	);
		437	#else
		438
		439	CLEAR_BIT(ADCx->CR1,
		440	( ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_DISCNUM
		441	\| ADC_CR1_JDISCEN \| ADC_CR1_DISCEN \| ADC_CR1_JAUTO
		442	\| ADC_CR1_AWDSGL \| ADC_CR1_SCAN \| ADC_CR1_JEOCIE
		443	\| ADC_CR1_AWDIE \| ADC_CR1_EOCIE \| ADC_CR1_AWDCH )
		444	);
		445	#endif
		446
		447	/* Reset register CR2 */
		448	CLEAR_BIT(ADCx->CR2,
		449	( ADC_CR2_TSVREFE
		450	\| ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG \| ADC_CR2_EXTSEL
		451	\| ADC_CR2_JSWSTART \| ADC_CR2_JEXTTRIG \| ADC_CR2_JEXTSEL
		452	\| ADC_CR2_ALIGN \| ADC_CR2_DMA
		453	\| ADC_CR2_RSTCAL \| ADC_CR2_CAL
		454	\| ADC_CR2_CONT \| ADC_CR2_ADON )
		455	);
		456
		457	/* Reset register SMPR1 */
		458	CLEAR_BIT(ADCx->SMPR1,
		459	( ADC_SMPR1_SMP17 \| ADC_SMPR1_SMP16
		460	\| ADC_SMPR1_SMP15 \| ADC_SMPR1_SMP14 \| ADC_SMPR1_SMP13
		461	\| ADC_SMPR1_SMP12 \| ADC_SMPR1_SMP11 \| ADC_SMPR1_SMP10)
		462	);
		463
		464	/* Reset register SMPR2 */
		465	CLEAR_BIT(ADCx->SMPR2,
		466	( ADC_SMPR2_SMP9
		467	\| ADC_SMPR2_SMP8 \| ADC_SMPR2_SMP7 \| ADC_SMPR2_SMP6
		468	\| ADC_SMPR2_SMP5 \| ADC_SMPR2_SMP4 \| ADC_SMPR2_SMP3
		469	\| ADC_SMPR2_SMP2 \| ADC_SMPR2_SMP1 \| ADC_SMPR2_SMP0)
		470	);
		471
		472	/* Reset register JOFR1 */
		473	CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
		474	/* Reset register JOFR2 */
		475	CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
		476	/* Reset register JOFR3 */
		477	CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
		478	/* Reset register JOFR4 */
		479	CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
		480
		481	/* Reset register HTR */
		482	SET_BIT(ADCx->HTR, ADC_HTR_HT);
		483	/* Reset register LTR */
		484	CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
		485
		486	/* Reset register SQR1 */
		487	CLEAR_BIT(ADCx->SQR1,
		488	( ADC_SQR1_L
		489	\| ADC_SQR1_SQ16
		490	\| ADC_SQR1_SQ15 \| ADC_SQR1_SQ14 \| ADC_SQR1_SQ13)
		491	);
		492
		493	/* Reset register SQR2 */
		494	CLEAR_BIT(ADCx->SQR2,
		495	( ADC_SQR2_SQ12 \| ADC_SQR2_SQ11 \| ADC_SQR2_SQ10
		496	\| ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7)
		497	);
		498
		499
		500	/* Reset register JSQR */
		501	CLEAR_BIT(ADCx->JSQR,
		502	( ADC_JSQR_JL
		503	\| ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3
		504	\| ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 )
		505	);
		506
		507	/* Reset register DR */
		508	/* bits in access mode read only, no direct reset applicable */
		509
		510	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
		511	/* bits in access mode read only, no direct reset applicable */
		512
		513	}
		514
		515	return status;
		516	}
		517
		518	/**
		519	* @brief Initialize some features of ADC instance.
		520	* @note These parameters have an impact on ADC scope: ADC instance.
		521	* Affects both group regular and group injected (availability
		522	* of ADC group injected depends on STM32 families).
		523	* Refer to corresponding unitary functions into
		524	* @ref ADC_LL_EF_Configuration_ADC_Instance .
		525	* @note The setting of these parameters by function @ref LL_ADC_Init()
		526	* is conditioned to ADC state:
		527	* ADC instance must be disabled.
		528	* This condition is applied to all ADC features, for efficiency
		529	* and compatibility over all STM32 families. However, the different
		530	* features can be set under different ADC state conditions
		531	* (setting possible with ADC enabled without conversion on going,
		532	* ADC enabled with conversion on going, ...)
		533	* Each feature can be updated afterwards with a unitary function
		534	* and potentially with ADC in a different state than disabled,
		535	* refer to description of each function for setting
		536	* conditioned to ADC state.
		537	* @note After using this function, some other features must be configured
		538	* using LL unitary functions.
		539	* The minimum configuration remaining to be done is:
		540	* - Set ADC group regular or group injected sequencer:
		541	* map channel on the selected sequencer rank.
		542	* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
		543	* - Set ADC channel sampling time
		544	* Refer to function LL_ADC_SetChannelSamplingTime();
		545	* @param ADCx ADC instance
		546	* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
		547	* @retval An ErrorStatus enumeration value:
		548	* - SUCCESS: ADC registers are initialized
		549	* - ERROR: ADC registers are not initialized
		550	*/
		551	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct)
		552	{
		553	ErrorStatus status = SUCCESS;
		554
		555	/* Check the parameters */
		556	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		557
		558	assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
		559	assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
		560
		561	/* Note: Hardware constraint (refer to description of this function): */
		562	/* ADC instance must be disabled. */
		563	if(LL_ADC_IsEnabled(ADCx) == 0U)
		564	{
		565	/* Configuration of ADC hierarchical scope: */
		566	/* - ADC instance */
		567	/* - Set ADC conversion data alignment */
		568	MODIFY_REG(ADCx->CR1,
		569	ADC_CR1_SCAN
		570	,
		571	ADC_InitStruct->SequencersScanMode
		572	);
		573
		574	MODIFY_REG(ADCx->CR2,
		575	ADC_CR2_ALIGN
		576	,
		577	ADC_InitStruct->DataAlignment
		578	);
		579
		580	}
		581	else
		582	{
		583	/* Initialization error: ADC instance is not disabled. */
		584	status = ERROR;
		585	}
		586	return status;
		587	}
		588
		589	/**
		590	* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
		591	* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
		592	* whose fields will be set to default values.
		593	* @retval None
		594	*/
		595	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
		596	{
		597	/* Set ADC_InitStruct fields to default values */
		598	/* Set fields of ADC instance */
		599	ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
		600
		601	/* Enable scan mode to have a generic behavior with ADC of other */
		602	/* STM32 families, without this setting available: */
		603	/* ADC group regular sequencer and ADC group injected sequencer depend */
		604	/* only of their own configuration. */
		605	ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
		606
		607	}
		608
		609	/**
		610	* @brief Initialize some features of ADC group regular.
		611	* @note These parameters have an impact on ADC scope: ADC group regular.
		612	* Refer to corresponding unitary functions into
		613	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
		614	* (functions with prefix "REG").
		615	* @note The setting of these parameters by function @ref LL_ADC_Init()
		616	* is conditioned to ADC state:
		617	* ADC instance must be disabled.
		618	* This condition is applied to all ADC features, for efficiency
		619	* and compatibility over all STM32 families. However, the different
		620	* features can be set under different ADC state conditions
		621	* (setting possible with ADC enabled without conversion on going,
		622	* ADC enabled with conversion on going, ...)
		623	* Each feature can be updated afterwards with a unitary function
		624	* and potentially with ADC in a different state than disabled,
		625	* refer to description of each function for setting
		626	* conditioned to ADC state.
		627	* @note After using this function, other features must be configured
		628	* using LL unitary functions.
		629	* The minimum configuration remaining to be done is:
		630	* - Set ADC group regular or group injected sequencer:
		631	* map channel on the selected sequencer rank.
		632	* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
		633	* - Set ADC channel sampling time
		634	* Refer to function LL_ADC_SetChannelSamplingTime();
		635	* @param ADCx ADC instance
		636	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
		637	* @retval An ErrorStatus enumeration value:
		638	* - SUCCESS: ADC registers are initialized
		639	* - ERROR: ADC registers are not initialized
		640	*/
		641	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct)
		642	{
		643	ErrorStatus status = SUCCESS;
		644
		645	/* Check the parameters */
		646	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		647	#if defined(ADC3)
		648	assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
		649	#else
		650	assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
		651	#endif
		652	assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
		653	if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
		654	{
		655	assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
		656	}
		657	assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
		658	assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
		659
		660	/* Note: Hardware constraint (refer to description of this function): */
		661	/* ADC instance must be disabled. */
		662	if(LL_ADC_IsEnabled(ADCx) == 0U)
		663	{
		664	/* Configuration of ADC hierarchical scope: */
		665	/* - ADC group regular */
		666	/* - Set ADC group regular trigger source */
		667	/* - Set ADC group regular sequencer length */
		668	/* - Set ADC group regular sequencer discontinuous mode */
		669	/* - Set ADC group regular continuous mode */
		670	/* - Set ADC group regular conversion data transfer: no transfer or */
		671	/* transfer by DMA, and DMA requests mode */
		672	/* Note: On this STM32 serie, ADC trigger edge is set when starting */
		673	/* ADC conversion. */
		674	/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
		675	if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
		676	{
		677	MODIFY_REG(ADCx->CR1,
		678	ADC_CR1_DISCEN
		679	\| ADC_CR1_DISCNUM
		680	,
		681	ADC_REG_InitStruct->SequencerLength
		682	\| ADC_REG_InitStruct->SequencerDiscont
		683	);
		684	}
		685	else
		686	{
		687	MODIFY_REG(ADCx->CR1,
		688	ADC_CR1_DISCEN
		689	\| ADC_CR1_DISCNUM
		690	,
		691	ADC_REG_InitStruct->SequencerLength
		692	\| LL_ADC_REG_SEQ_DISCONT_DISABLE
		693	);
		694	}
		695
		696	MODIFY_REG(ADCx->CR2,
		697	ADC_CR2_EXTSEL
		698	\| ADC_CR2_CONT
		699	\| ADC_CR2_DMA
		700	,
		701	ADC_REG_InitStruct->TriggerSource
		702	\| ADC_REG_InitStruct->ContinuousMode
		703	\| ADC_REG_InitStruct->DMATransfer
		704	);
		705
		706	/* Set ADC group regular sequencer length and scan direction */
		707	/* Note: Hardware constraint (refer to description of this function): */
		708	/* Note: If ADC instance feature scan mode is disabled */
		709	/* (refer to ADC instance initialization structure */
		710	/* parameter @ref SequencersScanMode */
		711	/* or function @ref LL_ADC_SetSequencersScanMode() ), */
		712	/* this parameter is discarded. */
		713	LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
		714	}
		715	else
		716	{
		717	/* Initialization error: ADC instance is not disabled. */
		718	status = ERROR;
		719	}
		720	return status;
		721	}
		722
		723	/**
		724	* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
		725	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
		726	* whose fields will be set to default values.
		727	* @retval None
		728	*/
		729	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
		730	{
		731	/* Set ADC_REG_InitStruct fields to default values */
		732	/* Set fields of ADC group regular */
		733	/* Note: On this STM32 serie, ADC trigger edge is set when starting */
		734	/* ADC conversion. */
		735	/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
		736	ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
		737	ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
		738	ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
		739	ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
		740	ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
		741	}
		742
		743	/**
		744	* @brief Initialize some features of ADC group injected.
		745	* @note These parameters have an impact on ADC scope: ADC group injected.
		746	* Refer to corresponding unitary functions into
		747	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
		748	* (functions with prefix "INJ").
		749	* @note The setting of these parameters by function @ref LL_ADC_Init()
		750	* is conditioned to ADC state:
		751	* ADC instance must be disabled.
		752	* This condition is applied to all ADC features, for efficiency
		753	* and compatibility over all STM32 families. However, the different
		754	* features can be set under different ADC state conditions
		755	* (setting possible with ADC enabled without conversion on going,
		756	* ADC enabled with conversion on going, ...)
		757	* Each feature can be updated afterwards with a unitary function
		758	* and potentially with ADC in a different state than disabled,
		759	* refer to description of each function for setting
		760	* conditioned to ADC state.
		761	* @note After using this function, other features must be configured
		762	* using LL unitary functions.
		763	* The minimum configuration remaining to be done is:
		764	* - Set ADC group injected sequencer:
		765	* map channel on the selected sequencer rank.
		766	* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
		767	* - Set ADC channel sampling time
		768	* Refer to function LL_ADC_SetChannelSamplingTime();
		769	* @param ADCx ADC instance
		770	* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
		771	* @retval An ErrorStatus enumeration value:
		772	* - SUCCESS: ADC registers are initialized
		773	* - ERROR: ADC registers are not initialized
		774	*/
		775	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct)
		776	{
		777	ErrorStatus status = SUCCESS;
		778
		779	/* Check the parameters */
		780	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		781	#if defined(ADC3)
		782	assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
		783	#else
		784	assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
		785	#endif
		786	assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
		787	if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
		788	{
		789	assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
		790	}
		791	assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
		792
		793	/* Note: Hardware constraint (refer to description of this function): */
		794	/* ADC instance must be disabled. */
		795	if(LL_ADC_IsEnabled(ADCx) == 0U)
		796	{
		797	/* Configuration of ADC hierarchical scope: */
		798	/* - ADC group injected */
		799	/* - Set ADC group injected trigger source */
		800	/* - Set ADC group injected sequencer length */
		801	/* - Set ADC group injected sequencer discontinuous mode */
		802	/* - Set ADC group injected conversion trigger: independent or */
		803	/* from ADC group regular */
		804	/* Note: On this STM32 serie, ADC trigger edge is set when starting */
		805	/* ADC conversion. */
		806	/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
		807	if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
		808	{
		809	MODIFY_REG(ADCx->CR1,
		810	ADC_CR1_JDISCEN
		811	\| ADC_CR1_JAUTO
		812	,
		813	ADC_INJ_InitStruct->SequencerDiscont
		814	\| ADC_INJ_InitStruct->TrigAuto
		815	);
		816	}
		817	else
		818	{
		819	MODIFY_REG(ADCx->CR1,
		820	ADC_CR1_JDISCEN
		821	\| ADC_CR1_JAUTO
		822	,
		823	LL_ADC_REG_SEQ_DISCONT_DISABLE
		824	\| ADC_INJ_InitStruct->TrigAuto
		825	);
		826	}
		827
		828	MODIFY_REG(ADCx->CR2,
		829	ADC_CR2_JEXTSEL
		830	,
		831	ADC_INJ_InitStruct->TriggerSource
		832	);
		833
		834	/* Note: Hardware constraint (refer to description of this function): */
		835	/* Note: If ADC instance feature scan mode is disabled */
		836	/* (refer to ADC instance initialization structure */
		837	/* parameter @ref SequencersScanMode */
		838	/* or function @ref LL_ADC_SetSequencersScanMode() ), */
		839	/* this parameter is discarded. */
		840	LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
		841	}
		842	else
		843	{
		844	/* Initialization error: ADC instance is not disabled. */
		845	status = ERROR;
		846	}
		847	return status;
		848	}
		849
		850	/**
		851	* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
		852	* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
		853	* whose fields will be set to default values.
		854	* @retval None
		855	*/
		856	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
		857	{
		858	/* Set ADC_INJ_InitStruct fields to default values */
		859	/* Set fields of ADC group injected */
		860	ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
		861	ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
		862	ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
		863	ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
		864	}
		865
		866	/**
		867	* @}
		868	*/
		869
		870	/**
		871	* @}
		872	*/
		873
		874	/**
		875	* @}
		876	*/
		877
		878	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
		879
		880	/**
		881	* @}
		882	*/
		883
		884	#endif /* USE_FULL_LL_DRIVER */
		885
		886	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c – Rev 2