WebSVN – dashGPS – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_tim.c
		4	* @author MCD Application Team
		5	* @brief TIM HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Timer (TIM) peripheral:
		8	* + TIM Time Base Initialization
		9	* + TIM Time Base Start
		10	* + TIM Time Base Start Interruption
		11	* + TIM Time Base Start DMA
		12	* + TIM Output Compare/PWM Initialization
		13	* + TIM Output Compare/PWM Channel Configuration
		14	* + TIM Output Compare/PWM Start
		15	* + TIM Output Compare/PWM Start Interruption
		16	* + TIM Output Compare/PWM Start DMA
		17	* + TIM Input Capture Initialization
		18	* + TIM Input Capture Channel Configuration
		19	* + TIM Input Capture Start
		20	* + TIM Input Capture Start Interruption
		21	* + TIM Input Capture Start DMA
		22	* + TIM One Pulse Initialization
		23	* + TIM One Pulse Channel Configuration
		24	* + TIM One Pulse Start
		25	* + TIM Encoder Interface Initialization
		26	* + TIM Encoder Interface Start
		27	* + TIM Encoder Interface Start Interruption
		28	* + TIM Encoder Interface Start DMA
		29	* + Commutation Event configuration with Interruption and DMA
		30	* + TIM OCRef clear configuration
		31	* + TIM External Clock configuration
		32	@verbatim
		33	==============================================================================
		34	##### TIMER Generic features #####
		35	==============================================================================
		36	[..] The Timer features include:
		37	(#) 16-bit up, down, up/down auto-reload counter.
		38	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
		39	counter clock frequency either by any factor between 1 and 65536.
		40	(#) Up to 4 independent channels for:
		41	(++) Input Capture
		42	(++) Output Compare
		43	(++) PWM generation (Edge and Center-aligned Mode)
		44	(++) One-pulse mode output
		45	(#) Synchronization circuit to control the timer with external signals and to interconnect
		46	several timers together.
		47	(#) Supports incremental encoder for positioning purposes
		48
		49	##### How to use this driver #####
		50	==============================================================================
		51	[..]
		52	(#) Initialize the TIM low level resources by implementing the following functions
		53	depending on the selected feature:
		54	(++) Time Base : HAL_TIM_Base_MspInit()
		55	(++) Input Capture : HAL_TIM_IC_MspInit()
		56	(++) Output Compare : HAL_TIM_OC_MspInit()
		57	(++) PWM generation : HAL_TIM_PWM_MspInit()
		58	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
		59	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
		60
		61	(#) Initialize the TIM low level resources :
		62	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
		63	(##) TIM pins configuration
		64	(+++) Enable the clock for the TIM GPIOs using the following function:
		65	__HAL_RCC_GPIOx_CLK_ENABLE();
		66	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
		67
		68	(#) The external Clock can be configured, if needed (the default clock is the
		69	internal clock from the APBx), using the following function:
		70	HAL_TIM_ConfigClockSource, the clock configuration should be done before
		71	any start function.
		72
		73	(#) Configure the TIM in the desired functioning mode using one of the
		74	Initialization function of this driver:
		75	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
		76	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
		77	Output Compare signal.
		78	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
		79	PWM signal.
		80	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
		81	external signal.
		82	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
		83	in One Pulse Mode.
		84	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
		85
		86	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
		87	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
		88	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
		89	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
		90	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
		91	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
		92	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
		93
		94	(#) The DMA Burst is managed with the two following functions:
		95	HAL_TIM_DMABurst_WriteStart()
		96	HAL_TIM_DMABurst_ReadStart()
		97
		98	* Callback registration *
		99	=============================================
		100
		101	[..]
		102	The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
		103	allows the user to configure dynamically the driver callbacks.
		104
		105	[..]
		106	Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
		107	@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
		108	the Callback ID and a pointer to the user callback function.
		109
		110	[..]
		111	Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
		112	weak function.
		113	@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
		114	and the Callback ID.
		115
		116	[..]
		117	These functions allow to register/unregister following callbacks:
		118	(+) Base_MspInitCallback : TIM Base Msp Init Callback.
		119	(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
		120	(+) IC_MspInitCallback : TIM IC Msp Init Callback.
		121	(+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
		122	(+) OC_MspInitCallback : TIM OC Msp Init Callback.
		123	(+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
		124	(+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
		125	(+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
		126	(+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
		127	(+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
		128	(+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
		129	(+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
		130	(+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
		131	(+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
		132	(+) PeriodElapsedCallback : TIM Period Elapsed Callback.
		133	(+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
		134	(+) TriggerCallback : TIM Trigger Callback.
		135	(+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
		136	(+) IC_CaptureCallback : TIM Input Capture Callback.
		137	(+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
		138	(+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
		139	(+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
		140	(+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
		141	(+) ErrorCallback : TIM Error Callback.
		142	(+) CommutationCallback : TIM Commutation Callback.
		143	(+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
		144	(+) BreakCallback : TIM Break Callback.
		145
		146	[..]
		147	By default, after the Init and when the state is HAL_TIM_STATE_RESET
		148	all interrupt callbacks are set to the corresponding weak functions:
		149	examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
		150
		151	[..]
		152	Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
		153	functionalities in the Init / DeInit only when these callbacks are null
		154	(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
		155	keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
		156
		157	[..]
		158	Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
		159	Exception done MspInit / MspDeInit that can be registered / unregistered
		160	in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
		161	thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
		162	In that case first register the MspInit/MspDeInit user callbacks
		163	using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
		164
		165	[..]
		166	When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
		167	not defined, the callback registration feature is not available and all callbacks
		168	are set to the corresponding weak functions.
		169
		170	@endverbatim
		171	******************************************************************************
		172	* @attention
		173	*
		174	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		175	* All rights reserved.</center></h2>
		176	*
		177	* This software component is licensed by ST under BSD 3-Clause license,
		178	* the "License"; You may not use this file except in compliance with the
		179	* License. You may obtain a copy of the License at:
		180	* opensource.org/licenses/BSD-3-Clause
		181	*
		182	******************************************************************************
		183	*/
		184
		185	/* Includes ------------------------------------------------------------------*/
		186	#include "stm32f1xx_hal.h"
		187
		188	/** @addtogroup STM32F1xx_HAL_Driver
		189	* @{
		190	*/
		191
		192	/** @defgroup TIM TIM
		193	* @brief TIM HAL module driver
		194	* @{
		195	*/
		196
		197	#ifdef HAL_TIM_MODULE_ENABLED
		198
		199	/* Private typedef -----------------------------------------------------------*/
		200	/* Private define ------------------------------------------------------------*/
		201	/* Private macro -------------------------------------------------------------*/
		202	/* Private variables ---------------------------------------------------------*/
		203	/* Private function prototypes -----------------------------------------------*/
		204	/** @addtogroup TIM_Private_Functions
		205	* @{
		206	*/
		207	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		208	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		209	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		210	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
		211	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		212	uint32_t TIM_ICFilter);
		213	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
		214	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		215	uint32_t TIM_ICFilter);
		216	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		217	uint32_t TIM_ICFilter);
		218	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
		219	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
		220	static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
		221	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
		222	static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
		223	static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
		224	TIM_SlaveConfigTypeDef *sSlaveConfig);
		225	/**
		226	* @}
		227	*/
		228	/* Exported functions --------------------------------------------------------*/
		229
		230	/** @defgroup TIM_Exported_Functions TIM Exported Functions
		231	* @{
		232	*/
		233
		234	/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
		235	* @brief Time Base functions
		236	*
		237	@verbatim
		238	==============================================================================
		239	##### Time Base functions #####
		240	==============================================================================
		241	[..]
		242	This section provides functions allowing to:
		243	(+) Initialize and configure the TIM base.
		244	(+) De-initialize the TIM base.
		245	(+) Start the Time Base.
		246	(+) Stop the Time Base.
		247	(+) Start the Time Base and enable interrupt.
		248	(+) Stop the Time Base and disable interrupt.
		249	(+) Start the Time Base and enable DMA transfer.
		250	(+) Stop the Time Base and disable DMA transfer.
		251
		252	@endverbatim
		253	* @{
		254	*/
		255	/**
		256	* @brief Initializes the TIM Time base Unit according to the specified
		257	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
		258	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		259	* requires a timer reset to avoid unexpected direction
		260	* due to DIR bit readonly in center aligned mode.
		261	* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
		262	* @param htim TIM Base handle
		263	* @retval HAL status
		264	*/
		265	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
		266	{
		267	/* Check the TIM handle allocation */
		268	if (htim == NULL)
		269	{
		270	return HAL_ERROR;
		271	}
		272
		273	/* Check the parameters */
		274	assert_param(IS_TIM_INSTANCE(htim->Instance));
		275	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		276	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		277	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		278
		279	if (htim->State == HAL_TIM_STATE_RESET)
		280	{
		281	/* Allocate lock resource and initialize it */
		282	htim->Lock = HAL_UNLOCKED;
		283
		284	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		285	/* Reset interrupt callbacks to legacy weak callbacks */
		286	TIM_ResetCallback(htim);
		287
		288	if (htim->Base_MspInitCallback == NULL)
		289	{
		290	htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
		291	}
		292	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		293	htim->Base_MspInitCallback(htim);
		294	#else
		295	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		296	HAL_TIM_Base_MspInit(htim);
		297	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		298	}
		299
		300	/* Set the TIM state */
		301	htim->State = HAL_TIM_STATE_BUSY;
		302
		303	/* Set the Time Base configuration */
		304	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		305
		306	/* Initialize the TIM state*/
		307	htim->State = HAL_TIM_STATE_READY;
		308
		309	return HAL_OK;
		310	}
		311
		312	/**
		313	* @brief DeInitializes the TIM Base peripheral
		314	* @param htim TIM Base handle
		315	* @retval HAL status
		316	*/
		317	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
		318	{
		319	/* Check the parameters */
		320	assert_param(IS_TIM_INSTANCE(htim->Instance));
		321
		322	htim->State = HAL_TIM_STATE_BUSY;
		323
		324	/* Disable the TIM Peripheral Clock */
		325	__HAL_TIM_DISABLE(htim);
		326
		327	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		328	if (htim->Base_MspDeInitCallback == NULL)
		329	{
		330	htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
		331	}
		332	/* DeInit the low level hardware */
		333	htim->Base_MspDeInitCallback(htim);
		334	#else
		335	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		336	HAL_TIM_Base_MspDeInit(htim);
		337	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		338
		339	/* Change TIM state */
		340	htim->State = HAL_TIM_STATE_RESET;
		341
		342	/* Release Lock */
		343	__HAL_UNLOCK(htim);
		344
		345	return HAL_OK;
		346	}
		347
		348	/**
		349	* @brief Initializes the TIM Base MSP.
		350	* @param htim TIM Base handle
		351	* @retval None
		352	*/
		353	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
		354	{
		355	/* Prevent unused argument(s) compilation warning */
		356	UNUSED(htim);
		357
		358	/* NOTE : This function should not be modified, when the callback is needed,
		359	the HAL_TIM_Base_MspInit could be implemented in the user file
		360	*/
		361	}
		362
		363	/**
		364	* @brief DeInitializes TIM Base MSP.
		365	* @param htim TIM Base handle
		366	* @retval None
		367	*/
		368	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
		369	{
		370	/* Prevent unused argument(s) compilation warning */
		371	UNUSED(htim);
		372
		373	/* NOTE : This function should not be modified, when the callback is needed,
		374	the HAL_TIM_Base_MspDeInit could be implemented in the user file
		375	*/
		376	}
		377
		378
		379	/**
		380	* @brief Starts the TIM Base generation.
		381	* @param htim TIM Base handle
		382	* @retval HAL status
		383	*/
		384	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
		385	{
		386	uint32_t tmpsmcr;
		387
		388	/* Check the parameters */
		389	assert_param(IS_TIM_INSTANCE(htim->Instance));
		390
		391	/* Set the TIM state */
		392	htim->State = HAL_TIM_STATE_BUSY;
		393
		394	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		395	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		396	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		397	{
		398	__HAL_TIM_ENABLE(htim);
		399	}
		400
		401	/* Change the TIM state*/
		402	htim->State = HAL_TIM_STATE_READY;
		403
		404	/* Return function status */
		405	return HAL_OK;
		406	}
		407
		408	/**
		409	* @brief Stops the TIM Base generation.
		410	* @param htim TIM Base handle
		411	* @retval HAL status
		412	*/
		413	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
		414	{
		415	/* Check the parameters */
		416	assert_param(IS_TIM_INSTANCE(htim->Instance));
		417
		418	/* Set the TIM state */
		419	htim->State = HAL_TIM_STATE_BUSY;
		420
		421	/* Disable the Peripheral */
		422	__HAL_TIM_DISABLE(htim);
		423
		424	/* Change the TIM state*/
		425	htim->State = HAL_TIM_STATE_READY;
		426
		427	/* Return function status */
		428	return HAL_OK;
		429	}
		430
		431	/**
		432	* @brief Starts the TIM Base generation in interrupt mode.
		433	* @param htim TIM Base handle
		434	* @retval HAL status
		435	*/
		436	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
		437	{
		438	uint32_t tmpsmcr;
		439
		440	/* Check the parameters */
		441	assert_param(IS_TIM_INSTANCE(htim->Instance));
		442
		443	/* Enable the TIM Update interrupt */
		444	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
		445
		446	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		447	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		448	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		449	{
		450	__HAL_TIM_ENABLE(htim);
		451	}
		452
		453	/* Return function status */
		454	return HAL_OK;
		455	}
		456
		457	/**
		458	* @brief Stops the TIM Base generation in interrupt mode.
		459	* @param htim TIM Base handle
		460	* @retval HAL status
		461	*/
		462	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
		463	{
		464	/* Check the parameters */
		465	assert_param(IS_TIM_INSTANCE(htim->Instance));
		466	/* Disable the TIM Update interrupt */
		467	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
		468
		469	/* Disable the Peripheral */
		470	__HAL_TIM_DISABLE(htim);
		471
		472	/* Return function status */
		473	return HAL_OK;
		474	}
		475
		476	/**
		477	* @brief Starts the TIM Base generation in DMA mode.
		478	* @param htim TIM Base handle
		479	* @param pData The source Buffer address.
		480	* @param Length The length of data to be transferred from memory to peripheral.
		481	* @retval HAL status
		482	*/
		483	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
		484	{
		485	uint32_t tmpsmcr;
		486
		487	/* Check the parameters */
		488	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
		489
		490	if (htim->State == HAL_TIM_STATE_BUSY)
		491	{
		492	return HAL_BUSY;
		493	}
		494	else if (htim->State == HAL_TIM_STATE_READY)
		495	{
		496	if ((pData == NULL) && (Length > 0U))
		497	{
		498	return HAL_ERROR;
		499	}
		500	else
		501	{
		502	htim->State = HAL_TIM_STATE_BUSY;
		503	}
		504	}
		505	else
		506	{
		507	/* nothing to do */
		508	}
		509
		510	/* Set the DMA Period elapsed callbacks */
		511	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		512	htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
		513
		514	/* Set the DMA error callback */
		515	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		516
		517	/* Enable the DMA channel */
		518	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
		519	{
		520	return HAL_ERROR;
		521	}
		522
		523	/* Enable the TIM Update DMA request */
		524	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
		525
		526	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		527	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		528	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		529	{
		530	__HAL_TIM_ENABLE(htim);
		531	}
		532
		533	/* Return function status */
		534	return HAL_OK;
		535	}
		536
		537	/**
		538	* @brief Stops the TIM Base generation in DMA mode.
		539	* @param htim TIM Base handle
		540	* @retval HAL status
		541	*/
		542	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
		543	{
		544	/* Check the parameters */
		545	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
		546
		547	/* Disable the TIM Update DMA request */
		548	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
		549
		550	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
		551
		552	/* Disable the Peripheral */
		553	__HAL_TIM_DISABLE(htim);
		554
		555	/* Change the htim state */
		556	htim->State = HAL_TIM_STATE_READY;
		557
		558	/* Return function status */
		559	return HAL_OK;
		560	}
		561
		562	/**
		563	* @}
		564	*/
		565
		566	/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		567	* @brief TIM Output Compare functions
		568	*
		569	@verbatim
		570	==============================================================================
		571	##### TIM Output Compare functions #####
		572	==============================================================================
		573	[..]
		574	This section provides functions allowing to:
		575	(+) Initialize and configure the TIM Output Compare.
		576	(+) De-initialize the TIM Output Compare.
		577	(+) Start the TIM Output Compare.
		578	(+) Stop the TIM Output Compare.
		579	(+) Start the TIM Output Compare and enable interrupt.
		580	(+) Stop the TIM Output Compare and disable interrupt.
		581	(+) Start the TIM Output Compare and enable DMA transfer.
		582	(+) Stop the TIM Output Compare and disable DMA transfer.
		583
		584	@endverbatim
		585	* @{
		586	*/
		587	/**
		588	* @brief Initializes the TIM Output Compare according to the specified
		589	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		590	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		591	* requires a timer reset to avoid unexpected direction
		592	* due to DIR bit readonly in center aligned mode.
		593	* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
		594	* @param htim TIM Output Compare handle
		595	* @retval HAL status
		596	*/
		597	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
		598	{
		599	/* Check the TIM handle allocation */
		600	if (htim == NULL)
		601	{
		602	return HAL_ERROR;
		603	}
		604
		605	/* Check the parameters */
		606	assert_param(IS_TIM_INSTANCE(htim->Instance));
		607	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		608	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		609	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		610
		611	if (htim->State == HAL_TIM_STATE_RESET)
		612	{
		613	/* Allocate lock resource and initialize it */
		614	htim->Lock = HAL_UNLOCKED;
		615
		616	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		617	/* Reset interrupt callbacks to legacy weak callbacks */
		618	TIM_ResetCallback(htim);
		619
		620	if (htim->OC_MspInitCallback == NULL)
		621	{
		622	htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
		623	}
		624	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		625	htim->OC_MspInitCallback(htim);
		626	#else
		627	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		628	HAL_TIM_OC_MspInit(htim);
		629	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		630	}
		631
		632	/* Set the TIM state */
		633	htim->State = HAL_TIM_STATE_BUSY;
		634
		635	/* Init the base time for the Output Compare */
		636	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		637
		638	/* Initialize the TIM state*/
		639	htim->State = HAL_TIM_STATE_READY;
		640
		641	return HAL_OK;
		642	}
		643
		644	/**
		645	* @brief DeInitializes the TIM peripheral
		646	* @param htim TIM Output Compare handle
		647	* @retval HAL status
		648	*/
		649	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
		650	{
		651	/* Check the parameters */
		652	assert_param(IS_TIM_INSTANCE(htim->Instance));
		653
		654	htim->State = HAL_TIM_STATE_BUSY;
		655
		656	/* Disable the TIM Peripheral Clock */
		657	__HAL_TIM_DISABLE(htim);
		658
		659	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		660	if (htim->OC_MspDeInitCallback == NULL)
		661	{
		662	htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
		663	}
		664	/* DeInit the low level hardware */
		665	htim->OC_MspDeInitCallback(htim);
		666	#else
		667	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		668	HAL_TIM_OC_MspDeInit(htim);
		669	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		670
		671	/* Change TIM state */
		672	htim->State = HAL_TIM_STATE_RESET;
		673
		674	/* Release Lock */
		675	__HAL_UNLOCK(htim);
		676
		677	return HAL_OK;
		678	}
		679
		680	/**
		681	* @brief Initializes the TIM Output Compare MSP.
		682	* @param htim TIM Output Compare handle
		683	* @retval None
		684	*/
		685	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
		686	{
		687	/* Prevent unused argument(s) compilation warning */
		688	UNUSED(htim);
		689
		690	/* NOTE : This function should not be modified, when the callback is needed,
		691	the HAL_TIM_OC_MspInit could be implemented in the user file
		692	*/
		693	}
		694
		695	/**
		696	* @brief DeInitializes TIM Output Compare MSP.
		697	* @param htim TIM Output Compare handle
		698	* @retval None
		699	*/
		700	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
		701	{
		702	/* Prevent unused argument(s) compilation warning */
		703	UNUSED(htim);
		704
		705	/* NOTE : This function should not be modified, when the callback is needed,
		706	the HAL_TIM_OC_MspDeInit could be implemented in the user file
		707	*/
		708	}
		709
		710	/**
		711	* @brief Starts the TIM Output Compare signal generation.
		712	* @param htim TIM Output Compare handle
		713	* @param Channel TIM Channel to be enabled
		714	* This parameter can be one of the following values:
		715	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		716	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		717	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		718	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		719	* @retval HAL status
		720	*/
		721	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		722	{
		723	uint32_t tmpsmcr;
		724
		725	/* Check the parameters */
		726	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		727
		728	/* Enable the Output compare channel */
		729	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		730
		731	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		732	{
		733	/* Enable the main output */
		734	__HAL_TIM_MOE_ENABLE(htim);
		735	}
		736
		737	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		738	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		739	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		740	{
		741	__HAL_TIM_ENABLE(htim);
		742	}
		743
		744	/* Return function status */
		745	return HAL_OK;
		746	}
		747
		748	/**
		749	* @brief Stops the TIM Output Compare signal generation.
		750	* @param htim TIM Output Compare handle
		751	* @param Channel TIM Channel to be disabled
		752	* This parameter can be one of the following values:
		753	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		754	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		755	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		756	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		757	* @retval HAL status
		758	*/
		759	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		760	{
		761	/* Check the parameters */
		762	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		763
		764	/* Disable the Output compare channel */
		765	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		766
		767	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		768	{
		769	/* Disable the Main Output */
		770	__HAL_TIM_MOE_DISABLE(htim);
		771	}
		772
		773	/* Disable the Peripheral */
		774	__HAL_TIM_DISABLE(htim);
		775
		776	/* Return function status */
		777	return HAL_OK;
		778	}
		779
		780	/**
		781	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
		782	* @param htim TIM Output Compare handle
		783	* @param Channel TIM Channel to be enabled
		784	* This parameter can be one of the following values:
		785	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		786	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		787	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		788	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		789	* @retval HAL status
		790	*/
		791	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		792	{
		793	uint32_t tmpsmcr;
		794
		795	/* Check the parameters */
		796	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		797
		798	switch (Channel)
		799	{
		800	case TIM_CHANNEL_1:
		801	{
		802	/* Enable the TIM Capture/Compare 1 interrupt */
		803	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		804	break;
		805	}
		806
		807	case TIM_CHANNEL_2:
		808	{
		809	/* Enable the TIM Capture/Compare 2 interrupt */
		810	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		811	break;
		812	}
		813
		814	case TIM_CHANNEL_3:
		815	{
		816	/* Enable the TIM Capture/Compare 3 interrupt */
		817	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		818	break;
		819	}
		820
		821	case TIM_CHANNEL_4:
		822	{
		823	/* Enable the TIM Capture/Compare 4 interrupt */
		824	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		825	break;
		826	}
		827
		828	default:
		829	break;
		830	}
		831
		832	/* Enable the Output compare channel */
		833	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		834
		835	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		836	{
		837	/* Enable the main output */
		838	__HAL_TIM_MOE_ENABLE(htim);
		839	}
		840
		841	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		842	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		843	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		844	{
		845	__HAL_TIM_ENABLE(htim);
		846	}
		847
		848	/* Return function status */
		849	return HAL_OK;
		850	}
		851
		852	/**
		853	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
		854	* @param htim TIM Output Compare handle
		855	* @param Channel TIM Channel to be disabled
		856	* This parameter can be one of the following values:
		857	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		858	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		859	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		860	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		861	* @retval HAL status
		862	*/
		863	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		864	{
		865	/* Check the parameters */
		866	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		867
		868	switch (Channel)
		869	{
		870	case TIM_CHANNEL_1:
		871	{
		872	/* Disable the TIM Capture/Compare 1 interrupt */
		873	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		874	break;
		875	}
		876
		877	case TIM_CHANNEL_2:
		878	{
		879	/* Disable the TIM Capture/Compare 2 interrupt */
		880	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		881	break;
		882	}
		883
		884	case TIM_CHANNEL_3:
		885	{
		886	/* Disable the TIM Capture/Compare 3 interrupt */
		887	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		888	break;
		889	}
		890
		891	case TIM_CHANNEL_4:
		892	{
		893	/* Disable the TIM Capture/Compare 4 interrupt */
		894	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		895	break;
		896	}
		897
		898	default:
		899	break;
		900	}
		901
		902	/* Disable the Output compare channel */
		903	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		904
		905	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		906	{
		907	/* Disable the Main Output */
		908	__HAL_TIM_MOE_DISABLE(htim);
		909	}
		910
		911	/* Disable the Peripheral */
		912	__HAL_TIM_DISABLE(htim);
		913
		914	/* Return function status */
		915	return HAL_OK;
		916	}
		917
		918	/**
		919	* @brief Starts the TIM Output Compare signal generation in DMA mode.
		920	* @param htim TIM Output Compare handle
		921	* @param Channel TIM Channel to be enabled
		922	* This parameter can be one of the following values:
		923	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		924	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		925	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		926	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		927	* @param pData The source Buffer address.
		928	* @param Length The length of data to be transferred from memory to TIM peripheral
		929	* @retval HAL status
		930	*/
		931	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		932	{
		933	uint32_t tmpsmcr;
		934
		935	/* Check the parameters */
		936	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		937
		938	if (htim->State == HAL_TIM_STATE_BUSY)
		939	{
		940	return HAL_BUSY;
		941	}
		942	else if (htim->State == HAL_TIM_STATE_READY)
		943	{
		944	if ((pData == NULL) && (Length > 0U))
		945	{
		946	return HAL_ERROR;
		947	}
		948	else
		949	{
		950	htim->State = HAL_TIM_STATE_BUSY;
		951	}
		952	}
		953	else
		954	{
		955	/* nothing to do */
		956	}
		957
		958	switch (Channel)
		959	{
		960	case TIM_CHANNEL_1:
		961	{
		962	/* Set the DMA compare callbacks */
		963	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		964	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		965
		966	/* Set the DMA error callback */
		967	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		968
		969	/* Enable the DMA channel */
		970	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
		971	{
		972	return HAL_ERROR;
		973	}
		974
		975	/* Enable the TIM Capture/Compare 1 DMA request */
		976	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		977	break;
		978	}
		979
		980	case TIM_CHANNEL_2:
		981	{
		982	/* Set the DMA compare callbacks */
		983	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		984	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		985
		986	/* Set the DMA error callback */
		987	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		988
		989	/* Enable the DMA channel */
		990	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
		991	{
		992	return HAL_ERROR;
		993	}
		994
		995	/* Enable the TIM Capture/Compare 2 DMA request */
		996	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		997	break;
		998	}
		999
		1000	case TIM_CHANNEL_3:
		1001	{
		1002	/* Set the DMA compare callbacks */
		1003	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1004	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1005
		1006	/* Set the DMA error callback */
		1007	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		1008
		1009	/* Enable the DMA channel */
		1010	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
		1011	{
		1012	return HAL_ERROR;
		1013	}
		1014	/* Enable the TIM Capture/Compare 3 DMA request */
		1015	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		1016	break;
		1017	}
		1018
		1019	case TIM_CHANNEL_4:
		1020	{
		1021	/* Set the DMA compare callbacks */
		1022	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1023	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1024
		1025	/* Set the DMA error callback */
		1026	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		1027
		1028	/* Enable the DMA channel */
		1029	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
		1030	{
		1031	return HAL_ERROR;
		1032	}
		1033	/* Enable the TIM Capture/Compare 4 DMA request */
		1034	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		1035	break;
		1036	}
		1037
		1038	default:
		1039	break;
		1040	}
		1041
		1042	/* Enable the Output compare channel */
		1043	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1044
		1045	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1046	{
		1047	/* Enable the main output */
		1048	__HAL_TIM_MOE_ENABLE(htim);
		1049	}
		1050
		1051	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1052	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1053	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1054	{
		1055	__HAL_TIM_ENABLE(htim);
		1056	}
		1057
		1058	/* Return function status */
		1059	return HAL_OK;
		1060	}
		1061
		1062	/**
		1063	* @brief Stops the TIM Output Compare signal generation in DMA mode.
		1064	* @param htim TIM Output Compare handle
		1065	* @param Channel TIM Channel to be disabled
		1066	* This parameter can be one of the following values:
		1067	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1068	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1069	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1070	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1071	* @retval HAL status
		1072	*/
		1073	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		1074	{
		1075	/* Check the parameters */
		1076	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1077
		1078	switch (Channel)
		1079	{
		1080	case TIM_CHANNEL_1:
		1081	{
		1082	/* Disable the TIM Capture/Compare 1 DMA request */
		1083	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		1084	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		1085	break;
		1086	}
		1087
		1088	case TIM_CHANNEL_2:
		1089	{
		1090	/* Disable the TIM Capture/Compare 2 DMA request */
		1091	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		1092	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		1093	break;
		1094	}
		1095
		1096	case TIM_CHANNEL_3:
		1097	{
		1098	/* Disable the TIM Capture/Compare 3 DMA request */
		1099	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		1100	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		1101	break;
		1102	}
		1103
		1104	case TIM_CHANNEL_4:
		1105	{
		1106	/* Disable the TIM Capture/Compare 4 interrupt */
		1107	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		1108	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		1109	break;
		1110	}
		1111
		1112	default:
		1113	break;
		1114	}
		1115
		1116	/* Disable the Output compare channel */
		1117	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1118
		1119	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1120	{
		1121	/* Disable the Main Output */
		1122	__HAL_TIM_MOE_DISABLE(htim);
		1123	}
		1124
		1125	/* Disable the Peripheral */
		1126	__HAL_TIM_DISABLE(htim);
		1127
		1128	/* Change the htim state */
		1129	htim->State = HAL_TIM_STATE_READY;
		1130
		1131	/* Return function status */
		1132	return HAL_OK;
		1133	}
		1134
		1135	/**
		1136	* @}
		1137	*/
		1138
		1139	/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
		1140	* @brief TIM PWM functions
		1141	*
		1142	@verbatim
		1143	==============================================================================
		1144	##### TIM PWM functions #####
		1145	==============================================================================
		1146	[..]
		1147	This section provides functions allowing to:
		1148	(+) Initialize and configure the TIM PWM.
		1149	(+) De-initialize the TIM PWM.
		1150	(+) Start the TIM PWM.
		1151	(+) Stop the TIM PWM.
		1152	(+) Start the TIM PWM and enable interrupt.
		1153	(+) Stop the TIM PWM and disable interrupt.
		1154	(+) Start the TIM PWM and enable DMA transfer.
		1155	(+) Stop the TIM PWM and disable DMA transfer.
		1156
		1157	@endverbatim
		1158	* @{
		1159	*/
		1160	/**
		1161	* @brief Initializes the TIM PWM Time Base according to the specified
		1162	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		1163	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1164	* requires a timer reset to avoid unexpected direction
		1165	* due to DIR bit readonly in center aligned mode.
		1166	* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
		1167	* @param htim TIM PWM handle
		1168	* @retval HAL status
		1169	*/
		1170	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
		1171	{
		1172	/* Check the TIM handle allocation */
		1173	if (htim == NULL)
		1174	{
		1175	return HAL_ERROR;
		1176	}
		1177
		1178	/* Check the parameters */
		1179	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1180	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		1181	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		1182	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		1183
		1184	if (htim->State == HAL_TIM_STATE_RESET)
		1185	{
		1186	/* Allocate lock resource and initialize it */
		1187	htim->Lock = HAL_UNLOCKED;
		1188
		1189	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1190	/* Reset interrupt callbacks to legacy weak callbacks */
		1191	TIM_ResetCallback(htim);
		1192
		1193	if (htim->PWM_MspInitCallback == NULL)
		1194	{
		1195	htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
		1196	}
		1197	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		1198	htim->PWM_MspInitCallback(htim);
		1199	#else
		1200	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		1201	HAL_TIM_PWM_MspInit(htim);
		1202	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1203	}
		1204
		1205	/* Set the TIM state */
		1206	htim->State = HAL_TIM_STATE_BUSY;
		1207
		1208	/* Init the base time for the PWM */
		1209	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1210
		1211	/* Initialize the TIM state*/
		1212	htim->State = HAL_TIM_STATE_READY;
		1213
		1214	return HAL_OK;
		1215	}
		1216
		1217	/**
		1218	* @brief DeInitializes the TIM peripheral
		1219	* @param htim TIM PWM handle
		1220	* @retval HAL status
		1221	*/
		1222	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
		1223	{
		1224	/* Check the parameters */
		1225	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1226
		1227	htim->State = HAL_TIM_STATE_BUSY;
		1228
		1229	/* Disable the TIM Peripheral Clock */
		1230	__HAL_TIM_DISABLE(htim);
		1231
		1232	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1233	if (htim->PWM_MspDeInitCallback == NULL)
		1234	{
		1235	htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
		1236	}
		1237	/* DeInit the low level hardware */
		1238	htim->PWM_MspDeInitCallback(htim);
		1239	#else
		1240	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		1241	HAL_TIM_PWM_MspDeInit(htim);
		1242	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1243
		1244	/* Change TIM state */
		1245	htim->State = HAL_TIM_STATE_RESET;
		1246
		1247	/* Release Lock */
		1248	__HAL_UNLOCK(htim);
		1249
		1250	return HAL_OK;
		1251	}
		1252
		1253	/**
		1254	* @brief Initializes the TIM PWM MSP.
		1255	* @param htim TIM PWM handle
		1256	* @retval None
		1257	*/
		1258	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
		1259	{
		1260	/* Prevent unused argument(s) compilation warning */
		1261	UNUSED(htim);
		1262
		1263	/* NOTE : This function should not be modified, when the callback is needed,
		1264	the HAL_TIM_PWM_MspInit could be implemented in the user file
		1265	*/
		1266	}
		1267
		1268	/**
		1269	* @brief DeInitializes TIM PWM MSP.
		1270	* @param htim TIM PWM handle
		1271	* @retval None
		1272	*/
		1273	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
		1274	{
		1275	/* Prevent unused argument(s) compilation warning */
		1276	UNUSED(htim);
		1277
		1278	/* NOTE : This function should not be modified, when the callback is needed,
		1279	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
		1280	*/
		1281	}
		1282
		1283	/**
		1284	* @brief Starts the PWM signal generation.
		1285	* @param htim TIM handle
		1286	* @param Channel TIM Channels to be enabled
		1287	* This parameter can be one of the following values:
		1288	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1289	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1290	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1291	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1292	* @retval HAL status
		1293	*/
		1294	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		1295	{
		1296	uint32_t tmpsmcr;
		1297
		1298	/* Check the parameters */
		1299	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1300
		1301	/* Enable the Capture compare channel */
		1302	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1303
		1304	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1305	{
		1306	/* Enable the main output */
		1307	__HAL_TIM_MOE_ENABLE(htim);
		1308	}
		1309
		1310	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1311	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1312	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1313	{
		1314	__HAL_TIM_ENABLE(htim);
		1315	}
		1316
		1317	/* Return function status */
		1318	return HAL_OK;
		1319	}
		1320
		1321	/**
		1322	* @brief Stops the PWM signal generation.
		1323	* @param htim TIM PWM handle
		1324	* @param Channel TIM Channels to be disabled
		1325	* This parameter can be one of the following values:
		1326	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1327	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1328	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1329	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1330	* @retval HAL status
		1331	*/
		1332	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		1333	{
		1334	/* Check the parameters */
		1335	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1336
		1337	/* Disable the Capture compare channel */
		1338	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1339
		1340	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1341	{
		1342	/* Disable the Main Output */
		1343	__HAL_TIM_MOE_DISABLE(htim);
		1344	}
		1345
		1346	/* Disable the Peripheral */
		1347	__HAL_TIM_DISABLE(htim);
		1348
		1349	/* Change the htim state */
		1350	htim->State = HAL_TIM_STATE_READY;
		1351
		1352	/* Return function status */
		1353	return HAL_OK;
		1354	}
		1355
		1356	/**
		1357	* @brief Starts the PWM signal generation in interrupt mode.
		1358	* @param htim TIM PWM handle
		1359	* @param Channel TIM Channel to be enabled
		1360	* This parameter can be one of the following values:
		1361	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1362	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1363	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1364	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1365	* @retval HAL status
		1366	*/
		1367	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1368	{
		1369	uint32_t tmpsmcr;
		1370	/* Check the parameters */
		1371	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1372
		1373	switch (Channel)
		1374	{
		1375	case TIM_CHANNEL_1:
		1376	{
		1377	/* Enable the TIM Capture/Compare 1 interrupt */
		1378	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		1379	break;
		1380	}
		1381
		1382	case TIM_CHANNEL_2:
		1383	{
		1384	/* Enable the TIM Capture/Compare 2 interrupt */
		1385	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		1386	break;
		1387	}
		1388
		1389	case TIM_CHANNEL_3:
		1390	{
		1391	/* Enable the TIM Capture/Compare 3 interrupt */
		1392	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		1393	break;
		1394	}
		1395
		1396	case TIM_CHANNEL_4:
		1397	{
		1398	/* Enable the TIM Capture/Compare 4 interrupt */
		1399	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		1400	break;
		1401	}
		1402
		1403	default:
		1404	break;
		1405	}
		1406
		1407	/* Enable the Capture compare channel */
		1408	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1409
		1410	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1411	{
		1412	/* Enable the main output */
		1413	__HAL_TIM_MOE_ENABLE(htim);
		1414	}
		1415
		1416	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1417	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1418	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1419	{
		1420	__HAL_TIM_ENABLE(htim);
		1421	}
		1422
		1423	/* Return function status */
		1424	return HAL_OK;
		1425	}
		1426
		1427	/**
		1428	* @brief Stops the PWM signal generation in interrupt mode.
		1429	* @param htim TIM PWM handle
		1430	* @param Channel TIM Channels to be disabled
		1431	* This parameter can be one of the following values:
		1432	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1433	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1434	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1435	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1436	* @retval HAL status
		1437	*/
		1438	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1439	{
		1440	/* Check the parameters */
		1441	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1442
		1443	switch (Channel)
		1444	{
		1445	case TIM_CHANNEL_1:
		1446	{
		1447	/* Disable the TIM Capture/Compare 1 interrupt */
		1448	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		1449	break;
		1450	}
		1451
		1452	case TIM_CHANNEL_2:
		1453	{
		1454	/* Disable the TIM Capture/Compare 2 interrupt */
		1455	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		1456	break;
		1457	}
		1458
		1459	case TIM_CHANNEL_3:
		1460	{
		1461	/* Disable the TIM Capture/Compare 3 interrupt */
		1462	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		1463	break;
		1464	}
		1465
		1466	case TIM_CHANNEL_4:
		1467	{
		1468	/* Disable the TIM Capture/Compare 4 interrupt */
		1469	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		1470	break;
		1471	}
		1472
		1473	default:
		1474	break;
		1475	}
		1476
		1477	/* Disable the Capture compare channel */
		1478	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1479
		1480	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1481	{
		1482	/* Disable the Main Output */
		1483	__HAL_TIM_MOE_DISABLE(htim);
		1484	}
		1485
		1486	/* Disable the Peripheral */
		1487	__HAL_TIM_DISABLE(htim);
		1488
		1489	/* Return function status */
		1490	return HAL_OK;
		1491	}
		1492
		1493	/**
		1494	* @brief Starts the TIM PWM signal generation in DMA mode.
		1495	* @param htim TIM PWM handle
		1496	* @param Channel TIM Channels to be enabled
		1497	* This parameter can be one of the following values:
		1498	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1499	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1500	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1501	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1502	* @param pData The source Buffer address.
		1503	* @param Length The length of data to be transferred from memory to TIM peripheral
		1504	* @retval HAL status
		1505	*/
		1506	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		1507	{
		1508	uint32_t tmpsmcr;
		1509
		1510	/* Check the parameters */
		1511	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1512
		1513	if (htim->State == HAL_TIM_STATE_BUSY)
		1514	{
		1515	return HAL_BUSY;
		1516	}
		1517	else if (htim->State == HAL_TIM_STATE_READY)
		1518	{
		1519	if ((pData == NULL) && (Length > 0U))
		1520	{
		1521	return HAL_ERROR;
		1522	}
		1523	else
		1524	{
		1525	htim->State = HAL_TIM_STATE_BUSY;
		1526	}
		1527	}
		1528	else
		1529	{
		1530	/* nothing to do */
		1531	}
		1532
		1533	switch (Channel)
		1534	{
		1535	case TIM_CHANNEL_1:
		1536	{
		1537	/* Set the DMA compare callbacks */
		1538	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1539	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1540
		1541	/* Set the DMA error callback */
		1542	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		1543
		1544	/* Enable the DMA channel */
		1545	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
		1546	{
		1547	return HAL_ERROR;
		1548	}
		1549
		1550	/* Enable the TIM Capture/Compare 1 DMA request */
		1551	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		1552	break;
		1553	}
		1554
		1555	case TIM_CHANNEL_2:
		1556	{
		1557	/* Set the DMA compare callbacks */
		1558	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1559	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1560
		1561	/* Set the DMA error callback */
		1562	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		1563
		1564	/* Enable the DMA channel */
		1565	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
		1566	{
		1567	return HAL_ERROR;
		1568	}
		1569	/* Enable the TIM Capture/Compare 2 DMA request */
		1570	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		1571	break;
		1572	}
		1573
		1574	case TIM_CHANNEL_3:
		1575	{
		1576	/* Set the DMA compare callbacks */
		1577	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1578	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1579
		1580	/* Set the DMA error callback */
		1581	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		1582
		1583	/* Enable the DMA channel */
		1584	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
		1585	{
		1586	return HAL_ERROR;
		1587	}
		1588	/* Enable the TIM Output Capture/Compare 3 request */
		1589	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		1590	break;
		1591	}
		1592
		1593	case TIM_CHANNEL_4:
		1594	{
		1595	/* Set the DMA compare callbacks */
		1596	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1597	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1598
		1599	/* Set the DMA error callback */
		1600	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		1601
		1602	/* Enable the DMA channel */
		1603	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
		1604	{
		1605	return HAL_ERROR;
		1606	}
		1607	/* Enable the TIM Capture/Compare 4 DMA request */
		1608	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		1609	break;
		1610	}
		1611
		1612	default:
		1613	break;
		1614	}
		1615
		1616	/* Enable the Capture compare channel */
		1617	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1618
		1619	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1620	{
		1621	/* Enable the main output */
		1622	__HAL_TIM_MOE_ENABLE(htim);
		1623	}
		1624
		1625	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1626	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1627	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1628	{
		1629	__HAL_TIM_ENABLE(htim);
		1630	}
		1631
		1632	/* Return function status */
		1633	return HAL_OK;
		1634	}
		1635
		1636	/**
		1637	* @brief Stops the TIM PWM signal generation in DMA mode.
		1638	* @param htim TIM PWM handle
		1639	* @param Channel TIM Channels to be disabled
		1640	* This parameter can be one of the following values:
		1641	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1642	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1643	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1644	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1645	* @retval HAL status
		1646	*/
		1647	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		1648	{
		1649	/* Check the parameters */
		1650	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1651
		1652	switch (Channel)
		1653	{
		1654	case TIM_CHANNEL_1:
		1655	{
		1656	/* Disable the TIM Capture/Compare 1 DMA request */
		1657	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		1658	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		1659	break;
		1660	}
		1661
		1662	case TIM_CHANNEL_2:
		1663	{
		1664	/* Disable the TIM Capture/Compare 2 DMA request */
		1665	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		1666	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		1667	break;
		1668	}
		1669
		1670	case TIM_CHANNEL_3:
		1671	{
		1672	/* Disable the TIM Capture/Compare 3 DMA request */
		1673	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		1674	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		1675	break;
		1676	}
		1677
		1678	case TIM_CHANNEL_4:
		1679	{
		1680	/* Disable the TIM Capture/Compare 4 interrupt */
		1681	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		1682	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		1683	break;
		1684	}
		1685
		1686	default:
		1687	break;
		1688	}
		1689
		1690	/* Disable the Capture compare channel */
		1691	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1692
		1693	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1694	{
		1695	/* Disable the Main Output */
		1696	__HAL_TIM_MOE_DISABLE(htim);
		1697	}
		1698
		1699	/* Disable the Peripheral */
		1700	__HAL_TIM_DISABLE(htim);
		1701
		1702	/* Change the htim state */
		1703	htim->State = HAL_TIM_STATE_READY;
		1704
		1705	/* Return function status */
		1706	return HAL_OK;
		1707	}
		1708
		1709	/**
		1710	* @}
		1711	*/
		1712
		1713	/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1714	* @brief TIM Input Capture functions
		1715	*
		1716	@verbatim
		1717	==============================================================================
		1718	##### TIM Input Capture functions #####
		1719	==============================================================================
		1720	[..]
		1721	This section provides functions allowing to:
		1722	(+) Initialize and configure the TIM Input Capture.
		1723	(+) De-initialize the TIM Input Capture.
		1724	(+) Start the TIM Input Capture.
		1725	(+) Stop the TIM Input Capture.
		1726	(+) Start the TIM Input Capture and enable interrupt.
		1727	(+) Stop the TIM Input Capture and disable interrupt.
		1728	(+) Start the TIM Input Capture and enable DMA transfer.
		1729	(+) Stop the TIM Input Capture and disable DMA transfer.
		1730
		1731	@endverbatim
		1732	* @{
		1733	*/
		1734	/**
		1735	* @brief Initializes the TIM Input Capture Time base according to the specified
		1736	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		1737	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1738	* requires a timer reset to avoid unexpected direction
		1739	* due to DIR bit readonly in center aligned mode.
		1740	* Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
		1741	* @param htim TIM Input Capture handle
		1742	* @retval HAL status
		1743	*/
		1744	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
		1745	{
		1746	/* Check the TIM handle allocation */
		1747	if (htim == NULL)
		1748	{
		1749	return HAL_ERROR;
		1750	}
		1751
		1752	/* Check the parameters */
		1753	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1754	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		1755	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		1756	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		1757
		1758	if (htim->State == HAL_TIM_STATE_RESET)
		1759	{
		1760	/* Allocate lock resource and initialize it */
		1761	htim->Lock = HAL_UNLOCKED;
		1762
		1763	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1764	/* Reset interrupt callbacks to legacy weak callbacks */
		1765	TIM_ResetCallback(htim);
		1766
		1767	if (htim->IC_MspInitCallback == NULL)
		1768	{
		1769	htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
		1770	}
		1771	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		1772	htim->IC_MspInitCallback(htim);
		1773	#else
		1774	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		1775	HAL_TIM_IC_MspInit(htim);
		1776	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1777	}
		1778
		1779	/* Set the TIM state */
		1780	htim->State = HAL_TIM_STATE_BUSY;
		1781
		1782	/* Init the base time for the input capture */
		1783	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1784
		1785	/* Initialize the TIM state*/
		1786	htim->State = HAL_TIM_STATE_READY;
		1787
		1788	return HAL_OK;
		1789	}
		1790
		1791	/**
		1792	* @brief DeInitializes the TIM peripheral
		1793	* @param htim TIM Input Capture handle
		1794	* @retval HAL status
		1795	*/
		1796	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
		1797	{
		1798	/* Check the parameters */
		1799	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1800
		1801	htim->State = HAL_TIM_STATE_BUSY;
		1802
		1803	/* Disable the TIM Peripheral Clock */
		1804	__HAL_TIM_DISABLE(htim);
		1805
		1806	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1807	if (htim->IC_MspDeInitCallback == NULL)
		1808	{
		1809	htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
		1810	}
		1811	/* DeInit the low level hardware */
		1812	htim->IC_MspDeInitCallback(htim);
		1813	#else
		1814	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		1815	HAL_TIM_IC_MspDeInit(htim);
		1816	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1817
		1818	/* Change TIM state */
		1819	htim->State = HAL_TIM_STATE_RESET;
		1820
		1821	/* Release Lock */
		1822	__HAL_UNLOCK(htim);
		1823
		1824	return HAL_OK;
		1825	}
		1826
		1827	/**
		1828	* @brief Initializes the TIM Input Capture MSP.
		1829	* @param htim TIM Input Capture handle
		1830	* @retval None
		1831	*/
		1832	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
		1833	{
		1834	/* Prevent unused argument(s) compilation warning */
		1835	UNUSED(htim);
		1836
		1837	/* NOTE : This function should not be modified, when the callback is needed,
		1838	the HAL_TIM_IC_MspInit could be implemented in the user file
		1839	*/
		1840	}
		1841
		1842	/**
		1843	* @brief DeInitializes TIM Input Capture MSP.
		1844	* @param htim TIM handle
		1845	* @retval None
		1846	*/
		1847	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
		1848	{
		1849	/* Prevent unused argument(s) compilation warning */
		1850	UNUSED(htim);
		1851
		1852	/* NOTE : This function should not be modified, when the callback is needed,
		1853	the HAL_TIM_IC_MspDeInit could be implemented in the user file
		1854	*/
		1855	}
		1856
		1857	/**
		1858	* @brief Starts the TIM Input Capture measurement.
		1859	* @param htim TIM Input Capture handle
		1860	* @param Channel TIM Channels to be enabled
		1861	* This parameter can be one of the following values:
		1862	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1863	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1864	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1865	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1866	* @retval HAL status
		1867	*/
		1868	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		1869	{
		1870	uint32_t tmpsmcr;
		1871
		1872	/* Check the parameters */
		1873	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1874
		1875	/* Enable the Input Capture channel */
		1876	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1877
		1878	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1879	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1880	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1881	{
		1882	__HAL_TIM_ENABLE(htim);
		1883	}
		1884
		1885	/* Return function status */
		1886	return HAL_OK;
		1887	}
		1888
		1889	/**
		1890	* @brief Stops the TIM Input Capture measurement.
		1891	* @param htim TIM Input Capture handle
		1892	* @param Channel TIM Channels to be disabled
		1893	* This parameter can be one of the following values:
		1894	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1895	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1896	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1897	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1898	* @retval HAL status
		1899	*/
		1900	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		1901	{
		1902	/* Check the parameters */
		1903	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1904
		1905	/* Disable the Input Capture channel */
		1906	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1907
		1908	/* Disable the Peripheral */
		1909	__HAL_TIM_DISABLE(htim);
		1910
		1911	/* Return function status */
		1912	return HAL_OK;
		1913	}
		1914
		1915	/**
		1916	* @brief Starts the TIM Input Capture measurement in interrupt mode.
		1917	* @param htim TIM Input Capture handle
		1918	* @param Channel TIM Channels to be enabled
		1919	* This parameter can be one of the following values:
		1920	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1921	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1922	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1923	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1924	* @retval HAL status
		1925	*/
		1926	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1927	{
		1928	uint32_t tmpsmcr;
		1929
		1930	/* Check the parameters */
		1931	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1932
		1933	switch (Channel)
		1934	{
		1935	case TIM_CHANNEL_1:
		1936	{
		1937	/* Enable the TIM Capture/Compare 1 interrupt */
		1938	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		1939	break;
		1940	}
		1941
		1942	case TIM_CHANNEL_2:
		1943	{
		1944	/* Enable the TIM Capture/Compare 2 interrupt */
		1945	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		1946	break;
		1947	}
		1948
		1949	case TIM_CHANNEL_3:
		1950	{
		1951	/* Enable the TIM Capture/Compare 3 interrupt */
		1952	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		1953	break;
		1954	}
		1955
		1956	case TIM_CHANNEL_4:
		1957	{
		1958	/* Enable the TIM Capture/Compare 4 interrupt */
		1959	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		1960	break;
		1961	}
		1962
		1963	default:
		1964	break;
		1965	}
		1966	/* Enable the Input Capture channel */
		1967	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1968
		1969	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1970	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1971	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1972	{
		1973	__HAL_TIM_ENABLE(htim);
		1974	}
		1975
		1976	/* Return function status */
		1977	return HAL_OK;
		1978	}
		1979
		1980	/**
		1981	* @brief Stops the TIM Input Capture measurement in interrupt mode.
		1982	* @param htim TIM Input Capture handle
		1983	* @param Channel TIM Channels to be disabled
		1984	* This parameter can be one of the following values:
		1985	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1986	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1987	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1988	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1989	* @retval HAL status
		1990	*/
		1991	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1992	{
		1993	/* Check the parameters */
		1994	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1995
		1996	switch (Channel)
		1997	{
		1998	case TIM_CHANNEL_1:
		1999	{
		2000	/* Disable the TIM Capture/Compare 1 interrupt */
		2001	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2002	break;
		2003	}
		2004
		2005	case TIM_CHANNEL_2:
		2006	{
		2007	/* Disable the TIM Capture/Compare 2 interrupt */
		2008	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2009	break;
		2010	}
		2011
		2012	case TIM_CHANNEL_3:
		2013	{
		2014	/* Disable the TIM Capture/Compare 3 interrupt */
		2015	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		2016	break;
		2017	}
		2018
		2019	case TIM_CHANNEL_4:
		2020	{
		2021	/* Disable the TIM Capture/Compare 4 interrupt */
		2022	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		2023	break;
		2024	}
		2025
		2026	default:
		2027	break;
		2028	}
		2029
		2030	/* Disable the Input Capture channel */
		2031	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		2032
		2033	/* Disable the Peripheral */
		2034	__HAL_TIM_DISABLE(htim);
		2035
		2036	/* Return function status */
		2037	return HAL_OK;
		2038	}
		2039
		2040	/**
		2041	* @brief Starts the TIM Input Capture measurement in DMA mode.
		2042	* @param htim TIM Input Capture handle
		2043	* @param Channel TIM Channels to be enabled
		2044	* This parameter can be one of the following values:
		2045	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2046	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2047	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		2048	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		2049	* @param pData The destination Buffer address.
		2050	* @param Length The length of data to be transferred from TIM peripheral to memory.
		2051	* @retval HAL status
		2052	*/
		2053	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		2054	{
		2055	uint32_t tmpsmcr;
		2056
		2057	/* Check the parameters */
		2058	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		2059	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2060
		2061	if (htim->State == HAL_TIM_STATE_BUSY)
		2062	{
		2063	return HAL_BUSY;
		2064	}
		2065	else if (htim->State == HAL_TIM_STATE_READY)
		2066	{
		2067	if ((pData == NULL) && (Length > 0U))
		2068	{
		2069	return HAL_ERROR;
		2070	}
		2071	else
		2072	{
		2073	htim->State = HAL_TIM_STATE_BUSY;
		2074	}
		2075	}
		2076	else
		2077	{
		2078	/* nothing to do */
		2079	}
		2080
		2081	switch (Channel)
		2082	{
		2083	case TIM_CHANNEL_1:
		2084	{
		2085	/* Set the DMA capture callbacks */
		2086	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		2087	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2088
		2089	/* Set the DMA error callback */
		2090	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		2091
		2092	/* Enable the DMA channel */
		2093	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
		2094	{
		2095	return HAL_ERROR;
		2096	}
		2097	/* Enable the TIM Capture/Compare 1 DMA request */
		2098	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		2099	break;
		2100	}
		2101
		2102	case TIM_CHANNEL_2:
		2103	{
		2104	/* Set the DMA capture callbacks */
		2105	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		2106	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2107
		2108	/* Set the DMA error callback */
		2109	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		2110
		2111	/* Enable the DMA channel */
		2112	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
		2113	{
		2114	return HAL_ERROR;
		2115	}
		2116	/* Enable the TIM Capture/Compare 2 DMA request */
		2117	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		2118	break;
		2119	}
		2120
		2121	case TIM_CHANNEL_3:
		2122	{
		2123	/* Set the DMA capture callbacks */
		2124	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
		2125	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2126
		2127	/* Set the DMA error callback */
		2128	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		2129
		2130	/* Enable the DMA channel */
		2131	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
		2132	{
		2133	return HAL_ERROR;
		2134	}
		2135	/* Enable the TIM Capture/Compare 3 DMA request */
		2136	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		2137	break;
		2138	}
		2139
		2140	case TIM_CHANNEL_4:
		2141	{
		2142	/* Set the DMA capture callbacks */
		2143	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
		2144	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2145
		2146	/* Set the DMA error callback */
		2147	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		2148
		2149	/* Enable the DMA channel */
		2150	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
		2151	{
		2152	return HAL_ERROR;
		2153	}
		2154	/* Enable the TIM Capture/Compare 4 DMA request */
		2155	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		2156	break;
		2157	}
		2158
		2159	default:
		2160	break;
		2161	}
		2162
		2163	/* Enable the Input Capture channel */
		2164	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		2165
		2166	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		2167	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		2168	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		2169	{
		2170	__HAL_TIM_ENABLE(htim);
		2171	}
		2172
		2173	/* Return function status */
		2174	return HAL_OK;
		2175	}
		2176
		2177	/**
		2178	* @brief Stops the TIM Input Capture measurement in DMA mode.
		2179	* @param htim TIM Input Capture handle
		2180	* @param Channel TIM Channels to be disabled
		2181	* This parameter can be one of the following values:
		2182	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2183	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2184	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		2185	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		2186	* @retval HAL status
		2187	*/
		2188	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		2189	{
		2190	/* Check the parameters */
		2191	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		2192	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2193
		2194	switch (Channel)
		2195	{
		2196	case TIM_CHANNEL_1:
		2197	{
		2198	/* Disable the TIM Capture/Compare 1 DMA request */
		2199	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		2200	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		2201	break;
		2202	}
		2203
		2204	case TIM_CHANNEL_2:
		2205	{
		2206	/* Disable the TIM Capture/Compare 2 DMA request */
		2207	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		2208	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		2209	break;
		2210	}
		2211
		2212	case TIM_CHANNEL_3:
		2213	{
		2214	/* Disable the TIM Capture/Compare 3 DMA request */
		2215	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		2216	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		2217	break;
		2218	}
		2219
		2220	case TIM_CHANNEL_4:
		2221	{
		2222	/* Disable the TIM Capture/Compare 4 DMA request */
		2223	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		2224	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		2225	break;
		2226	}
		2227
		2228	default:
		2229	break;
		2230	}
		2231
		2232	/* Disable the Input Capture channel */
		2233	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		2234
		2235	/* Disable the Peripheral */
		2236	__HAL_TIM_DISABLE(htim);
		2237
		2238	/* Change the htim state */
		2239	htim->State = HAL_TIM_STATE_READY;
		2240
		2241	/* Return function status */
		2242	return HAL_OK;
		2243	}
		2244	/**
		2245	* @}
		2246	*/
		2247
		2248	/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		2249	* @brief TIM One Pulse functions
		2250	*
		2251	@verbatim
		2252	==============================================================================
		2253	##### TIM One Pulse functions #####
		2254	==============================================================================
		2255	[..]
		2256	This section provides functions allowing to:
		2257	(+) Initialize and configure the TIM One Pulse.
		2258	(+) De-initialize the TIM One Pulse.
		2259	(+) Start the TIM One Pulse.
		2260	(+) Stop the TIM One Pulse.
		2261	(+) Start the TIM One Pulse and enable interrupt.
		2262	(+) Stop the TIM One Pulse and disable interrupt.
		2263	(+) Start the TIM One Pulse and enable DMA transfer.
		2264	(+) Stop the TIM One Pulse and disable DMA transfer.
		2265
		2266	@endverbatim
		2267	* @{
		2268	*/
		2269	/**
		2270	* @brief Initializes the TIM One Pulse Time Base according to the specified
		2271	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		2272	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		2273	* requires a timer reset to avoid unexpected direction
		2274	* due to DIR bit readonly in center aligned mode.
		2275	* Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
		2276	* @param htim TIM One Pulse handle
		2277	* @param OnePulseMode Select the One pulse mode.
		2278	* This parameter can be one of the following values:
		2279	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
		2280	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
		2281	* @retval HAL status
		2282	*/
		2283	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
		2284	{
		2285	/* Check the TIM handle allocation */
		2286	if (htim == NULL)
		2287	{
		2288	return HAL_ERROR;
		2289	}
		2290
		2291	/* Check the parameters */
		2292	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2293	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		2294	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		2295	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
		2296	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		2297
		2298	if (htim->State == HAL_TIM_STATE_RESET)
		2299	{
		2300	/* Allocate lock resource and initialize it */
		2301	htim->Lock = HAL_UNLOCKED;
		2302
		2303	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2304	/* Reset interrupt callbacks to legacy weak callbacks */
		2305	TIM_ResetCallback(htim);
		2306
		2307	if (htim->OnePulse_MspInitCallback == NULL)
		2308	{
		2309	htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
		2310	}
		2311	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		2312	htim->OnePulse_MspInitCallback(htim);
		2313	#else
		2314	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		2315	HAL_TIM_OnePulse_MspInit(htim);
		2316	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2317	}
		2318
		2319	/* Set the TIM state */
		2320	htim->State = HAL_TIM_STATE_BUSY;
		2321
		2322	/* Configure the Time base in the One Pulse Mode */
		2323	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		2324
		2325	/* Reset the OPM Bit */
		2326	htim->Instance->CR1 &= ~TIM_CR1_OPM;
		2327
		2328	/* Configure the OPM Mode */
		2329	htim->Instance->CR1 \|= OnePulseMode;
		2330
		2331	/* Initialize the TIM state*/
		2332	htim->State = HAL_TIM_STATE_READY;
		2333
		2334	return HAL_OK;
		2335	}
		2336
		2337	/**
		2338	* @brief DeInitializes the TIM One Pulse
		2339	* @param htim TIM One Pulse handle
		2340	* @retval HAL status
		2341	*/
		2342	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
		2343	{
		2344	/* Check the parameters */
		2345	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2346
		2347	htim->State = HAL_TIM_STATE_BUSY;
		2348
		2349	/* Disable the TIM Peripheral Clock */
		2350	__HAL_TIM_DISABLE(htim);
		2351
		2352	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2353	if (htim->OnePulse_MspDeInitCallback == NULL)
		2354	{
		2355	htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
		2356	}
		2357	/* DeInit the low level hardware */
		2358	htim->OnePulse_MspDeInitCallback(htim);
		2359	#else
		2360	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		2361	HAL_TIM_OnePulse_MspDeInit(htim);
		2362	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2363
		2364	/* Change TIM state */
		2365	htim->State = HAL_TIM_STATE_RESET;
		2366
		2367	/* Release Lock */
		2368	__HAL_UNLOCK(htim);
		2369
		2370	return HAL_OK;
		2371	}
		2372
		2373	/**
		2374	* @brief Initializes the TIM One Pulse MSP.
		2375	* @param htim TIM One Pulse handle
		2376	* @retval None
		2377	*/
		2378	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
		2379	{
		2380	/* Prevent unused argument(s) compilation warning */
		2381	UNUSED(htim);
		2382
		2383	/* NOTE : This function should not be modified, when the callback is needed,
		2384	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
		2385	*/
		2386	}
		2387
		2388	/**
		2389	* @brief DeInitializes TIM One Pulse MSP.
		2390	* @param htim TIM One Pulse handle
		2391	* @retval None
		2392	*/
		2393	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
		2394	{
		2395	/* Prevent unused argument(s) compilation warning */
		2396	UNUSED(htim);
		2397
		2398	/* NOTE : This function should not be modified, when the callback is needed,
		2399	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
		2400	*/
		2401	}
		2402
		2403	/**
		2404	* @brief Starts the TIM One Pulse signal generation.
		2405	* @param htim TIM One Pulse handle
		2406	* @param OutputChannel TIM Channels to be enabled
		2407	* This parameter can be one of the following values:
		2408	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2409	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2410	* @retval HAL status
		2411	*/
		2412	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2413	{
		2414	/* Prevent unused argument(s) compilation warning */
		2415	UNUSED(OutputChannel);
		2416
		2417	/* Enable the Capture compare and the Input Capture channels
		2418	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2419	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2420	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2421	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
		2422
		2423	No need to enable the counter, it's enabled automatically by hardware
		2424	(the counter starts in response to a stimulus and generate a pulse */
		2425
		2426	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2427	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2428
		2429	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2430	{
		2431	/* Enable the main output */
		2432	__HAL_TIM_MOE_ENABLE(htim);
		2433	}
		2434
		2435	/* Return function status */
		2436	return HAL_OK;
		2437	}
		2438
		2439	/**
		2440	* @brief Stops the TIM One Pulse signal generation.
		2441	* @param htim TIM One Pulse handle
		2442	* @param OutputChannel TIM Channels to be disable
		2443	* This parameter can be one of the following values:
		2444	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2445	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2446	* @retval HAL status
		2447	*/
		2448	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2449	{
		2450	/* Prevent unused argument(s) compilation warning */
		2451	UNUSED(OutputChannel);
		2452
		2453	/* Disable the Capture compare and the Input Capture channels
		2454	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2455	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2456	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2457	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
		2458
		2459	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2460	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2461
		2462	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2463	{
		2464	/* Disable the Main Output */
		2465	__HAL_TIM_MOE_DISABLE(htim);
		2466	}
		2467
		2468	/* Disable the Peripheral */
		2469	__HAL_TIM_DISABLE(htim);
		2470
		2471	/* Return function status */
		2472	return HAL_OK;
		2473	}
		2474
		2475	/**
		2476	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
		2477	* @param htim TIM One Pulse handle
		2478	* @param OutputChannel TIM Channels to be enabled
		2479	* This parameter can be one of the following values:
		2480	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2481	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2482	* @retval HAL status
		2483	*/
		2484	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2485	{
		2486	/* Prevent unused argument(s) compilation warning */
		2487	UNUSED(OutputChannel);
		2488
		2489	/* Enable the Capture compare and the Input Capture channels
		2490	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2491	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2492	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2493	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
		2494
		2495	No need to enable the counter, it's enabled automatically by hardware
		2496	(the counter starts in response to a stimulus and generate a pulse */
		2497
		2498	/* Enable the TIM Capture/Compare 1 interrupt */
		2499	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2500
		2501	/* Enable the TIM Capture/Compare 2 interrupt */
		2502	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2503
		2504	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2505	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2506
		2507	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2508	{
		2509	/* Enable the main output */
		2510	__HAL_TIM_MOE_ENABLE(htim);
		2511	}
		2512
		2513	/* Return function status */
		2514	return HAL_OK;
		2515	}
		2516
		2517	/**
		2518	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
		2519	* @param htim TIM One Pulse handle
		2520	* @param OutputChannel TIM Channels to be enabled
		2521	* This parameter can be one of the following values:
		2522	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2523	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2524	* @retval HAL status
		2525	*/
		2526	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2527	{
		2528	/* Prevent unused argument(s) compilation warning */
		2529	UNUSED(OutputChannel);
		2530
		2531	/* Disable the TIM Capture/Compare 1 interrupt */
		2532	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2533
		2534	/* Disable the TIM Capture/Compare 2 interrupt */
		2535	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2536
		2537	/* Disable the Capture compare and the Input Capture channels
		2538	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2539	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2540	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2541	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
		2542	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2543	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2544
		2545	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2546	{
		2547	/* Disable the Main Output */
		2548	__HAL_TIM_MOE_DISABLE(htim);
		2549	}
		2550
		2551	/* Disable the Peripheral */
		2552	__HAL_TIM_DISABLE(htim);
		2553
		2554	/* Return function status */
		2555	return HAL_OK;
		2556	}
		2557
		2558	/**
		2559	* @}
		2560	*/
		2561
		2562	/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
		2563	* @brief TIM Encoder functions
		2564	*
		2565	@verbatim
		2566	==============================================================================
		2567	##### TIM Encoder functions #####
		2568	==============================================================================
		2569	[..]
		2570	This section provides functions allowing to:
		2571	(+) Initialize and configure the TIM Encoder.
		2572	(+) De-initialize the TIM Encoder.
		2573	(+) Start the TIM Encoder.
		2574	(+) Stop the TIM Encoder.
		2575	(+) Start the TIM Encoder and enable interrupt.
		2576	(+) Stop the TIM Encoder and disable interrupt.
		2577	(+) Start the TIM Encoder and enable DMA transfer.
		2578	(+) Stop the TIM Encoder and disable DMA transfer.
		2579
		2580	@endverbatim
		2581	* @{
		2582	*/
		2583	/**
		2584	* @brief Initializes the TIM Encoder Interface and initialize the associated handle.
		2585	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		2586	* requires a timer reset to avoid unexpected direction
		2587	* due to DIR bit readonly in center aligned mode.
		2588	* Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
		2589	* @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
		2590	* Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
		2591	* using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
		2592	* @param htim TIM Encoder Interface handle
		2593	* @param sConfig TIM Encoder Interface configuration structure
		2594	* @retval HAL status
		2595	*/
		2596	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
		2597	{
		2598	uint32_t tmpsmcr;
		2599	uint32_t tmpccmr1;
		2600	uint32_t tmpccer;
		2601
		2602	/* Check the TIM handle allocation */
		2603	if (htim == NULL)
		2604	{
		2605	return HAL_ERROR;
		2606	}
		2607
		2608	/* Check the parameters */
		2609	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		2610	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		2611	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		2612	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2613	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
		2614	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
		2615	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
		2616	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
		2617	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
		2618	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
		2619	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
		2620	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
		2621	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
		2622
		2623	if (htim->State == HAL_TIM_STATE_RESET)
		2624	{
		2625	/* Allocate lock resource and initialize it */
		2626	htim->Lock = HAL_UNLOCKED;
		2627
		2628	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2629	/* Reset interrupt callbacks to legacy weak callbacks */
		2630	TIM_ResetCallback(htim);
		2631
		2632	if (htim->Encoder_MspInitCallback == NULL)
		2633	{
		2634	htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
		2635	}
		2636	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		2637	htim->Encoder_MspInitCallback(htim);
		2638	#else
		2639	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		2640	HAL_TIM_Encoder_MspInit(htim);
		2641	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2642	}
		2643
		2644	/* Set the TIM state */
		2645	htim->State = HAL_TIM_STATE_BUSY;
		2646
		2647	/* Reset the SMS and ECE bits */
		2648	htim->Instance->SMCR &= ~(TIM_SMCR_SMS \| TIM_SMCR_ECE);
		2649
		2650	/* Configure the Time base in the Encoder Mode */
		2651	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		2652
		2653	/* Get the TIMx SMCR register value */
		2654	tmpsmcr = htim->Instance->SMCR;
		2655
		2656	/* Get the TIMx CCMR1 register value */
		2657	tmpccmr1 = htim->Instance->CCMR1;
		2658
		2659	/* Get the TIMx CCER register value */
		2660	tmpccer = htim->Instance->CCER;
		2661
		2662	/* Set the encoder Mode */
		2663	tmpsmcr \|= sConfig->EncoderMode;
		2664
		2665	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
		2666	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
		2667	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
		2668
		2669	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
		2670	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
		2671	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
		2672	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
		2673	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
		2674
		2675	/* Set the TI1 and the TI2 Polarities */
		2676	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
		2677	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
		2678
		2679	/* Write to TIMx SMCR */
		2680	htim->Instance->SMCR = tmpsmcr;
		2681
		2682	/* Write to TIMx CCMR1 */
		2683	htim->Instance->CCMR1 = tmpccmr1;
		2684
		2685	/* Write to TIMx CCER */
		2686	htim->Instance->CCER = tmpccer;
		2687
		2688	/* Initialize the TIM state*/
		2689	htim->State = HAL_TIM_STATE_READY;
		2690
		2691	return HAL_OK;
		2692	}
		2693
		2694
		2695	/**
		2696	* @brief DeInitializes the TIM Encoder interface
		2697	* @param htim TIM Encoder Interface handle
		2698	* @retval HAL status
		2699	*/
		2700	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
		2701	{
		2702	/* Check the parameters */
		2703	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2704
		2705	htim->State = HAL_TIM_STATE_BUSY;
		2706
		2707	/* Disable the TIM Peripheral Clock */
		2708	__HAL_TIM_DISABLE(htim);
		2709
		2710	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2711	if (htim->Encoder_MspDeInitCallback == NULL)
		2712	{
		2713	htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
		2714	}
		2715	/* DeInit the low level hardware */
		2716	htim->Encoder_MspDeInitCallback(htim);
		2717	#else
		2718	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		2719	HAL_TIM_Encoder_MspDeInit(htim);
		2720	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2721
		2722	/* Change TIM state */
		2723	htim->State = HAL_TIM_STATE_RESET;
		2724
		2725	/* Release Lock */
		2726	__HAL_UNLOCK(htim);
		2727
		2728	return HAL_OK;
		2729	}
		2730
		2731	/**
		2732	* @brief Initializes the TIM Encoder Interface MSP.
		2733	* @param htim TIM Encoder Interface handle
		2734	* @retval None
		2735	*/
		2736	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
		2737	{
		2738	/* Prevent unused argument(s) compilation warning */
		2739	UNUSED(htim);
		2740
		2741	/* NOTE : This function should not be modified, when the callback is needed,
		2742	the HAL_TIM_Encoder_MspInit could be implemented in the user file
		2743	*/
		2744	}
		2745
		2746	/**
		2747	* @brief DeInitializes TIM Encoder Interface MSP.
		2748	* @param htim TIM Encoder Interface handle
		2749	* @retval None
		2750	*/
		2751	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
		2752	{
		2753	/* Prevent unused argument(s) compilation warning */
		2754	UNUSED(htim);
		2755
		2756	/* NOTE : This function should not be modified, when the callback is needed,
		2757	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
		2758	*/
		2759	}
		2760
		2761	/**
		2762	* @brief Starts the TIM Encoder Interface.
		2763	* @param htim TIM Encoder Interface handle
		2764	* @param Channel TIM Channels to be enabled
		2765	* This parameter can be one of the following values:
		2766	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2767	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2768	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2769	* @retval HAL status
		2770	*/
		2771	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		2772	{
		2773	/* Check the parameters */
		2774	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2775
		2776	/* Enable the encoder interface channels */
		2777	switch (Channel)
		2778	{
		2779	case TIM_CHANNEL_1:
		2780	{
		2781	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2782	break;
		2783	}
		2784
		2785	case TIM_CHANNEL_2:
		2786	{
		2787	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2788	break;
		2789	}
		2790
		2791	default :
		2792	{
		2793	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2794	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2795	break;
		2796	}
		2797	}
		2798	/* Enable the Peripheral */
		2799	__HAL_TIM_ENABLE(htim);
		2800
		2801	/* Return function status */
		2802	return HAL_OK;
		2803	}
		2804
		2805	/**
		2806	* @brief Stops the TIM Encoder Interface.
		2807	* @param htim TIM Encoder Interface handle
		2808	* @param Channel TIM Channels to be disabled
		2809	* This parameter can be one of the following values:
		2810	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2811	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2812	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2813	* @retval HAL status
		2814	*/
		2815	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		2816	{
		2817	/* Check the parameters */
		2818	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2819
		2820	/* Disable the Input Capture channels 1 and 2
		2821	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2822	switch (Channel)
		2823	{
		2824	case TIM_CHANNEL_1:
		2825	{
		2826	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2827	break;
		2828	}
		2829
		2830	case TIM_CHANNEL_2:
		2831	{
		2832	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2833	break;
		2834	}
		2835
		2836	default :
		2837	{
		2838	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2839	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2840	break;
		2841	}
		2842	}
		2843
		2844	/* Disable the Peripheral */
		2845	__HAL_TIM_DISABLE(htim);
		2846
		2847	/* Return function status */
		2848	return HAL_OK;
		2849	}
		2850
		2851	/**
		2852	* @brief Starts the TIM Encoder Interface in interrupt mode.
		2853	* @param htim TIM Encoder Interface handle
		2854	* @param Channel TIM Channels to be enabled
		2855	* This parameter can be one of the following values:
		2856	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2857	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2858	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2859	* @retval HAL status
		2860	*/
		2861	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		2862	{
		2863	/* Check the parameters */
		2864	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2865
		2866	/* Enable the encoder interface channels */
		2867	/* Enable the capture compare Interrupts 1 and/or 2 */
		2868	switch (Channel)
		2869	{
		2870	case TIM_CHANNEL_1:
		2871	{
		2872	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2873	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2874	break;
		2875	}
		2876
		2877	case TIM_CHANNEL_2:
		2878	{
		2879	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2880	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2881	break;
		2882	}
		2883
		2884	default :
		2885	{
		2886	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2887	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2888	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2889	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2890	break;
		2891	}
		2892	}
		2893
		2894	/* Enable the Peripheral */
		2895	__HAL_TIM_ENABLE(htim);
		2896
		2897	/* Return function status */
		2898	return HAL_OK;
		2899	}
		2900
		2901	/**
		2902	* @brief Stops the TIM Encoder Interface in interrupt mode.
		2903	* @param htim TIM Encoder Interface handle
		2904	* @param Channel TIM Channels to be disabled
		2905	* This parameter can be one of the following values:
		2906	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2907	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2908	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2909	* @retval HAL status
		2910	*/
		2911	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		2912	{
		2913	/* Check the parameters */
		2914	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2915
		2916	/* Disable the Input Capture channels 1 and 2
		2917	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2918	if (Channel == TIM_CHANNEL_1)
		2919	{
		2920	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2921
		2922	/* Disable the capture compare Interrupts 1 */
		2923	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2924	}
		2925	else if (Channel == TIM_CHANNEL_2)
		2926	{
		2927	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2928
		2929	/* Disable the capture compare Interrupts 2 */
		2930	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2931	}
		2932	else
		2933	{
		2934	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2935	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2936
		2937	/* Disable the capture compare Interrupts 1 and 2 */
		2938	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2939	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2940	}
		2941
		2942	/* Disable the Peripheral */
		2943	__HAL_TIM_DISABLE(htim);
		2944
		2945	/* Change the htim state */
		2946	htim->State = HAL_TIM_STATE_READY;
		2947
		2948	/* Return function status */
		2949	return HAL_OK;
		2950	}
		2951
		2952	/**
		2953	* @brief Starts the TIM Encoder Interface in DMA mode.
		2954	* @param htim TIM Encoder Interface handle
		2955	* @param Channel TIM Channels to be enabled
		2956	* This parameter can be one of the following values:
		2957	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2958	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2959	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2960	* @param pData1 The destination Buffer address for IC1.
		2961	* @param pData2 The destination Buffer address for IC2.
		2962	* @param Length The length of data to be transferred from TIM peripheral to memory.
		2963	* @retval HAL status
		2964	*/
		2965	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		2966	uint32_t *pData2, uint16_t Length)
		2967	{
		2968	/* Check the parameters */
		2969	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2970
		2971	if (htim->State == HAL_TIM_STATE_BUSY)
		2972	{
		2973	return HAL_BUSY;
		2974	}
		2975	else if (htim->State == HAL_TIM_STATE_READY)
		2976	{
		2977	if ((((pData1 == NULL) \|\| (pData2 == NULL))) && (Length > 0U))
		2978	{
		2979	return HAL_ERROR;
		2980	}
		2981	else
		2982	{
		2983	htim->State = HAL_TIM_STATE_BUSY;
		2984	}
		2985	}
		2986	else
		2987	{
		2988	/* nothing to do */
		2989	}
		2990
		2991	switch (Channel)
		2992	{
		2993	case TIM_CHANNEL_1:
		2994	{
		2995	/* Set the DMA capture callbacks */
		2996	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		2997	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2998
		2999	/* Set the DMA error callback */
		3000	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3001
		3002	/* Enable the DMA channel */
		3003	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
		3004	{
		3005	return HAL_ERROR;
		3006	}
		3007	/* Enable the TIM Input Capture DMA request */
		3008	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		3009
		3010	/* Enable the Peripheral */
		3011	__HAL_TIM_ENABLE(htim);
		3012
		3013	/* Enable the Capture compare channel */
		3014	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		3015	break;
		3016	}
		3017
		3018	case TIM_CHANNEL_2:
		3019	{
		3020	/* Set the DMA capture callbacks */
		3021	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		3022	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		3023
		3024	/* Set the DMA error callback */
		3025	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
		3026	/* Enable the DMA channel */
		3027	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
		3028	{
		3029	return HAL_ERROR;
		3030	}
		3031	/* Enable the TIM Input Capture DMA request */
		3032	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		3033
		3034	/* Enable the Peripheral */
		3035	__HAL_TIM_ENABLE(htim);
		3036
		3037	/* Enable the Capture compare channel */
		3038	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		3039	break;
		3040	}
		3041
		3042	case TIM_CHANNEL_ALL:
		3043	{
		3044	/* Set the DMA capture callbacks */
		3045	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		3046	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		3047
		3048	/* Set the DMA error callback */
		3049	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3050
		3051	/* Enable the DMA channel */
		3052	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
		3053	{
		3054	return HAL_ERROR;
		3055	}
		3056
		3057	/* Set the DMA capture callbacks */
		3058	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		3059	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		3060
		3061	/* Set the DMA error callback */
		3062	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		3063
		3064	/* Enable the DMA channel */
		3065	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
		3066	{
		3067	return HAL_ERROR;
		3068	}
		3069	/* Enable the Peripheral */
		3070	__HAL_TIM_ENABLE(htim);
		3071
		3072	/* Enable the Capture compare channel */
		3073	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		3074	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		3075
		3076	/* Enable the TIM Input Capture DMA request */
		3077	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		3078	/* Enable the TIM Input Capture DMA request */
		3079	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		3080	break;
		3081	}
		3082
		3083	default:
		3084	break;
		3085	}
		3086	/* Return function status */
		3087	return HAL_OK;
		3088	}
		3089
		3090	/**
		3091	* @brief Stops the TIM Encoder Interface in DMA mode.
		3092	* @param htim TIM Encoder Interface handle
		3093	* @param Channel TIM Channels to be enabled
		3094	* This parameter can be one of the following values:
		3095	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3096	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3097	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		3098	* @retval HAL status
		3099	*/
		3100	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		3101	{
		3102	/* Check the parameters */
		3103	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		3104
		3105	/* Disable the Input Capture channels 1 and 2
		3106	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		3107	if (Channel == TIM_CHANNEL_1)
		3108	{
		3109	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		3110
		3111	/* Disable the capture compare DMA Request 1 */
		3112	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		3113	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		3114	}
		3115	else if (Channel == TIM_CHANNEL_2)
		3116	{
		3117	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		3118
		3119	/* Disable the capture compare DMA Request 2 */
		3120	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		3121	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		3122	}
		3123	else
		3124	{
		3125	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		3126	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		3127
		3128	/* Disable the capture compare DMA Request 1 and 2 */
		3129	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		3130	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		3131	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		3132	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		3133	}
		3134
		3135	/* Disable the Peripheral */
		3136	__HAL_TIM_DISABLE(htim);
		3137
		3138	/* Change the htim state */
		3139	htim->State = HAL_TIM_STATE_READY;
		3140
		3141	/* Return function status */
		3142	return HAL_OK;
		3143	}
		3144
		3145	/**
		3146	* @}
		3147	*/
		3148	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		3149	* @brief TIM IRQ handler management
		3150	*
		3151	@verbatim
		3152	==============================================================================
		3153	##### IRQ handler management #####
		3154	==============================================================================
		3155	[..]
		3156	This section provides Timer IRQ handler function.
		3157
		3158	@endverbatim
		3159	* @{
		3160	*/
		3161	/**
		3162	* @brief This function handles TIM interrupts requests.
		3163	* @param htim TIM handle
		3164	* @retval None
		3165	*/
		3166	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
		3167	{
		3168	/* Capture compare 1 event */
		3169	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
		3170	{
		3171	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
		3172	{
		3173	{
		3174	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
		3175	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		3176
		3177	/* Input capture event */
		3178	if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
		3179	{
		3180	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3181	htim->IC_CaptureCallback(htim);
		3182	#else
		3183	HAL_TIM_IC_CaptureCallback(htim);
		3184	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3185	}
		3186	/* Output compare event */
		3187	else
		3188	{
		3189	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3190	htim->OC_DelayElapsedCallback(htim);
		3191	htim->PWM_PulseFinishedCallback(htim);
		3192	#else
		3193	HAL_TIM_OC_DelayElapsedCallback(htim);
		3194	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3195	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3196	}
		3197	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3198	}
		3199	}
		3200	}
		3201	/* Capture compare 2 event */
		3202	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
		3203	{
		3204	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
		3205	{
		3206	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
		3207	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		3208	/* Input capture event */
		3209	if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
		3210	{
		3211	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3212	htim->IC_CaptureCallback(htim);
		3213	#else
		3214	HAL_TIM_IC_CaptureCallback(htim);
		3215	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3216	}
		3217	/* Output compare event */
		3218	else
		3219	{
		3220	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3221	htim->OC_DelayElapsedCallback(htim);
		3222	htim->PWM_PulseFinishedCallback(htim);
		3223	#else
		3224	HAL_TIM_OC_DelayElapsedCallback(htim);
		3225	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3226	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3227	}
		3228	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3229	}
		3230	}
		3231	/* Capture compare 3 event */
		3232	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
		3233	{
		3234	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
		3235	{
		3236	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
		3237	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		3238	/* Input capture event */
		3239	if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
		3240	{
		3241	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3242	htim->IC_CaptureCallback(htim);
		3243	#else
		3244	HAL_TIM_IC_CaptureCallback(htim);
		3245	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3246	}
		3247	/* Output compare event */
		3248	else
		3249	{
		3250	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3251	htim->OC_DelayElapsedCallback(htim);
		3252	htim->PWM_PulseFinishedCallback(htim);
		3253	#else
		3254	HAL_TIM_OC_DelayElapsedCallback(htim);
		3255	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3256	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3257	}
		3258	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3259	}
		3260	}
		3261	/* Capture compare 4 event */
		3262	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
		3263	{
		3264	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
		3265	{
		3266	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
		3267	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		3268	/* Input capture event */
		3269	if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
		3270	{
		3271	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3272	htim->IC_CaptureCallback(htim);
		3273	#else
		3274	HAL_TIM_IC_CaptureCallback(htim);
		3275	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3276	}
		3277	/* Output compare event */
		3278	else
		3279	{
		3280	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3281	htim->OC_DelayElapsedCallback(htim);
		3282	htim->PWM_PulseFinishedCallback(htim);
		3283	#else
		3284	HAL_TIM_OC_DelayElapsedCallback(htim);
		3285	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3286	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3287	}
		3288	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3289	}
		3290	}
		3291	/* TIM Update event */
		3292	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
		3293	{
		3294	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
		3295	{
		3296	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
		3297	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3298	htim->PeriodElapsedCallback(htim);
		3299	#else
		3300	HAL_TIM_PeriodElapsedCallback(htim);
		3301	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3302	}
		3303	}
		3304	/* TIM Break input event */
		3305	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
		3306	{
		3307	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
		3308	{
		3309	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
		3310	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3311	htim->BreakCallback(htim);
		3312	#else
		3313	HAL_TIMEx_BreakCallback(htim);
		3314	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3315	}
		3316	}
		3317	/* TIM Trigger detection event */
		3318	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
		3319	{
		3320	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
		3321	{
		3322	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
		3323	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3324	htim->TriggerCallback(htim);
		3325	#else
		3326	HAL_TIM_TriggerCallback(htim);
		3327	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3328	}
		3329	}
		3330	/* TIM commutation event */
		3331	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
		3332	{
		3333	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
		3334	{
		3335	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
		3336	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3337	htim->CommutationCallback(htim);
		3338	#else
		3339	HAL_TIMEx_CommutCallback(htim);
		3340	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3341	}
		3342	}
		3343	}
		3344
		3345	/**
		3346	* @}
		3347	*/
		3348
		3349	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		3350	* @brief TIM Peripheral Control functions
		3351	*
		3352	@verbatim
		3353	==============================================================================
		3354	##### Peripheral Control functions #####
		3355	==============================================================================
		3356	[..]
		3357	This section provides functions allowing to:
		3358	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
		3359	(+) Configure External Clock source.
		3360	(+) Configure Complementary channels, break features and dead time.
		3361	(+) Configure Master and the Slave synchronization.
		3362	(+) Configure the DMA Burst Mode.
		3363
		3364	@endverbatim
		3365	* @{
		3366	*/
		3367
		3368	/**
		3369	* @brief Initializes the TIM Output Compare Channels according to the specified
		3370	* parameters in the TIM_OC_InitTypeDef.
		3371	* @param htim TIM Output Compare handle
		3372	* @param sConfig TIM Output Compare configuration structure
		3373	* @param Channel TIM Channels to configure
		3374	* This parameter can be one of the following values:
		3375	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3376	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3377	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3378	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3379	* @retval HAL status
		3380	*/
		3381	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
		3382	TIM_OC_InitTypeDef *sConfig,
		3383	uint32_t Channel)
		3384	{
		3385	/* Check the parameters */
		3386	assert_param(IS_TIM_CHANNELS(Channel));
		3387	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
		3388	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
		3389
		3390	/* Process Locked */
		3391	__HAL_LOCK(htim);
		3392
		3393	htim->State = HAL_TIM_STATE_BUSY;
		3394
		3395	switch (Channel)
		3396	{
		3397	case TIM_CHANNEL_1:
		3398	{
		3399	/* Check the parameters */
		3400	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3401
		3402	/* Configure the TIM Channel 1 in Output Compare */
		3403	TIM_OC1_SetConfig(htim->Instance, sConfig);
		3404	break;
		3405	}
		3406
		3407	case TIM_CHANNEL_2:
		3408	{
		3409	/* Check the parameters */
		3410	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3411
		3412	/* Configure the TIM Channel 2 in Output Compare */
		3413	TIM_OC2_SetConfig(htim->Instance, sConfig);
		3414	break;
		3415	}
		3416
		3417	case TIM_CHANNEL_3:
		3418	{
		3419	/* Check the parameters */
		3420	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3421
		3422	/* Configure the TIM Channel 3 in Output Compare */
		3423	TIM_OC3_SetConfig(htim->Instance, sConfig);
		3424	break;
		3425	}
		3426
		3427	case TIM_CHANNEL_4:
		3428	{
		3429	/* Check the parameters */
		3430	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3431
		3432	/* Configure the TIM Channel 4 in Output Compare */
		3433	TIM_OC4_SetConfig(htim->Instance, sConfig);
		3434	break;
		3435	}
		3436
		3437	default:
		3438	break;
		3439	}
		3440
		3441	htim->State = HAL_TIM_STATE_READY;
		3442
		3443	__HAL_UNLOCK(htim);
		3444
		3445	return HAL_OK;
		3446	}
		3447
		3448	/**
		3449	* @brief Initializes the TIM Input Capture Channels according to the specified
		3450	* parameters in the TIM_IC_InitTypeDef.
		3451	* @param htim TIM IC handle
		3452	* @param sConfig TIM Input Capture configuration structure
		3453	* @param Channel TIM Channel to configure
		3454	* This parameter can be one of the following values:
		3455	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3456	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3457	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3458	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3459	* @retval HAL status
		3460	*/
		3461	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
		3462	{
		3463	/* Check the parameters */
		3464	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3465	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
		3466	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
		3467	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
		3468	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
		3469
		3470	/* Process Locked */
		3471	__HAL_LOCK(htim);
		3472
		3473	htim->State = HAL_TIM_STATE_BUSY;
		3474
		3475	if (Channel == TIM_CHANNEL_1)
		3476	{
		3477	/* TI1 Configuration */
		3478	TIM_TI1_SetConfig(htim->Instance,
		3479	sConfig->ICPolarity,
		3480	sConfig->ICSelection,
		3481	sConfig->ICFilter);
		3482
		3483	/* Reset the IC1PSC Bits */
		3484	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
		3485
		3486	/* Set the IC1PSC value */
		3487	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
		3488	}
		3489	else if (Channel == TIM_CHANNEL_2)
		3490	{
		3491	/* TI2 Configuration */
		3492	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3493
		3494	TIM_TI2_SetConfig(htim->Instance,
		3495	sConfig->ICPolarity,
		3496	sConfig->ICSelection,
		3497	sConfig->ICFilter);
		3498
		3499	/* Reset the IC2PSC Bits */
		3500	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
		3501
		3502	/* Set the IC2PSC value */
		3503	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
		3504	}
		3505	else if (Channel == TIM_CHANNEL_3)
		3506	{
		3507	/* TI3 Configuration */
		3508	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3509
		3510	TIM_TI3_SetConfig(htim->Instance,
		3511	sConfig->ICPolarity,
		3512	sConfig->ICSelection,
		3513	sConfig->ICFilter);
		3514
		3515	/* Reset the IC3PSC Bits */
		3516	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
		3517
		3518	/* Set the IC3PSC value */
		3519	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
		3520	}
		3521	else
		3522	{
		3523	/* TI4 Configuration */
		3524	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3525
		3526	TIM_TI4_SetConfig(htim->Instance,
		3527	sConfig->ICPolarity,
		3528	sConfig->ICSelection,
		3529	sConfig->ICFilter);
		3530
		3531	/* Reset the IC4PSC Bits */
		3532	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
		3533
		3534	/* Set the IC4PSC value */
		3535	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
		3536	}
		3537
		3538	htim->State = HAL_TIM_STATE_READY;
		3539
		3540	__HAL_UNLOCK(htim);
		3541
		3542	return HAL_OK;
		3543	}
		3544
		3545	/**
		3546	* @brief Initializes the TIM PWM channels according to the specified
		3547	* parameters in the TIM_OC_InitTypeDef.
		3548	* @param htim TIM PWM handle
		3549	* @param sConfig TIM PWM configuration structure
		3550	* @param Channel TIM Channels to be configured
		3551	* This parameter can be one of the following values:
		3552	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3553	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3554	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3555	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3556	* @retval HAL status
		3557	*/
		3558	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
		3559	TIM_OC_InitTypeDef *sConfig,
		3560	uint32_t Channel)
		3561	{
		3562	/* Check the parameters */
		3563	assert_param(IS_TIM_CHANNELS(Channel));
		3564	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
		3565	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
		3566	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
		3567
		3568	/* Process Locked */
		3569	__HAL_LOCK(htim);
		3570
		3571	htim->State = HAL_TIM_STATE_BUSY;
		3572
		3573	switch (Channel)
		3574	{
		3575	case TIM_CHANNEL_1:
		3576	{
		3577	/* Check the parameters */
		3578	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3579
		3580	/* Configure the Channel 1 in PWM mode */
		3581	TIM_OC1_SetConfig(htim->Instance, sConfig);
		3582
		3583	/* Set the Preload enable bit for channel1 */
		3584	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
		3585
		3586	/* Configure the Output Fast mode */
		3587	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
		3588	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
		3589	break;
		3590	}
		3591
		3592	case TIM_CHANNEL_2:
		3593	{
		3594	/* Check the parameters */
		3595	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3596
		3597	/* Configure the Channel 2 in PWM mode */
		3598	TIM_OC2_SetConfig(htim->Instance, sConfig);
		3599
		3600	/* Set the Preload enable bit for channel2 */
		3601	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
		3602
		3603	/* Configure the Output Fast mode */
		3604	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
		3605	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8U;
		3606	break;
		3607	}
		3608
		3609	case TIM_CHANNEL_3:
		3610	{
		3611	/* Check the parameters */
		3612	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3613
		3614	/* Configure the Channel 3 in PWM mode */
		3615	TIM_OC3_SetConfig(htim->Instance, sConfig);
		3616
		3617	/* Set the Preload enable bit for channel3 */
		3618	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
		3619
		3620	/* Configure the Output Fast mode */
		3621	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
		3622	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
		3623	break;
		3624	}
		3625
		3626	case TIM_CHANNEL_4:
		3627	{
		3628	/* Check the parameters */
		3629	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3630
		3631	/* Configure the Channel 4 in PWM mode */
		3632	TIM_OC4_SetConfig(htim->Instance, sConfig);
		3633
		3634	/* Set the Preload enable bit for channel4 */
		3635	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
		3636
		3637	/* Configure the Output Fast mode */
		3638	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
		3639	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8U;
		3640	break;
		3641	}
		3642
		3643	default:
		3644	break;
		3645	}
		3646
		3647	htim->State = HAL_TIM_STATE_READY;
		3648
		3649	__HAL_UNLOCK(htim);
		3650
		3651	return HAL_OK;
		3652	}
		3653
		3654	/**
		3655	* @brief Initializes the TIM One Pulse Channels according to the specified
		3656	* parameters in the TIM_OnePulse_InitTypeDef.
		3657	* @param htim TIM One Pulse handle
		3658	* @param sConfig TIM One Pulse configuration structure
		3659	* @param OutputChannel TIM output channel to configure
		3660	* This parameter can be one of the following values:
		3661	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3662	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3663	* @param InputChannel TIM input Channel to configure
		3664	* This parameter can be one of the following values:
		3665	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3666	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3667	* @note To output a waveform with a minimum delay user can enable the fast
		3668	* mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
		3669	* output is forced in response to the edge detection on TIx input,
		3670	* without taking in account the comparison.
		3671	* @retval HAL status
		3672	*/
		3673	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		3674	uint32_t OutputChannel, uint32_t InputChannel)
		3675	{
		3676	TIM_OC_InitTypeDef temp1;
		3677
		3678	/* Check the parameters */
		3679	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
		3680	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
		3681
		3682	if (OutputChannel != InputChannel)
		3683	{
		3684	/* Process Locked */
		3685	__HAL_LOCK(htim);
		3686
		3687	htim->State = HAL_TIM_STATE_BUSY;
		3688
		3689	/* Extract the Output compare configuration from sConfig structure */
		3690	temp1.OCMode = sConfig->OCMode;
		3691	temp1.Pulse = sConfig->Pulse;
		3692	temp1.OCPolarity = sConfig->OCPolarity;
		3693	temp1.OCNPolarity = sConfig->OCNPolarity;
		3694	temp1.OCIdleState = sConfig->OCIdleState;
		3695	temp1.OCNIdleState = sConfig->OCNIdleState;
		3696
		3697	switch (OutputChannel)
		3698	{
		3699	case TIM_CHANNEL_1:
		3700	{
		3701	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3702
		3703	TIM_OC1_SetConfig(htim->Instance, &temp1);
		3704	break;
		3705	}
		3706	case TIM_CHANNEL_2:
		3707	{
		3708	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3709
		3710	TIM_OC2_SetConfig(htim->Instance, &temp1);
		3711	break;
		3712	}
		3713	default:
		3714	break;
		3715	}
		3716
		3717	switch (InputChannel)
		3718	{
		3719	case TIM_CHANNEL_1:
		3720	{
		3721	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3722
		3723	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
		3724	sConfig->ICSelection, sConfig->ICFilter);
		3725
		3726	/* Reset the IC1PSC Bits */
		3727	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
		3728
		3729	/* Select the Trigger source */
		3730	htim->Instance->SMCR &= ~TIM_SMCR_TS;
		3731	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
		3732
		3733	/* Select the Slave Mode */
		3734	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3735	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
		3736	break;
		3737	}
		3738	case TIM_CHANNEL_2:
		3739	{
		3740	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3741
		3742	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
		3743	sConfig->ICSelection, sConfig->ICFilter);
		3744
		3745	/* Reset the IC2PSC Bits */
		3746	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
		3747
		3748	/* Select the Trigger source */
		3749	htim->Instance->SMCR &= ~TIM_SMCR_TS;
		3750	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
		3751
		3752	/* Select the Slave Mode */
		3753	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3754	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
		3755	break;
		3756	}
		3757
		3758	default:
		3759	break;
		3760	}
		3761
		3762	htim->State = HAL_TIM_STATE_READY;
		3763
		3764	__HAL_UNLOCK(htim);
		3765
		3766	return HAL_OK;
		3767	}
		3768	else
		3769	{
		3770	return HAL_ERROR;
		3771	}
		3772	}
		3773
		3774	/**
		3775	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
		3776	* @param htim TIM handle
		3777	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
		3778	* This parameter can be one of the following values:
		3779	* @arg TIM_DMABASE_CR1
		3780	* @arg TIM_DMABASE_CR2
		3781	* @arg TIM_DMABASE_SMCR
		3782	* @arg TIM_DMABASE_DIER
		3783	* @arg TIM_DMABASE_SR
		3784	* @arg TIM_DMABASE_EGR
		3785	* @arg TIM_DMABASE_CCMR1
		3786	* @arg TIM_DMABASE_CCMR2
		3787	* @arg TIM_DMABASE_CCER
		3788	* @arg TIM_DMABASE_CNT
		3789	* @arg TIM_DMABASE_PSC
		3790	* @arg TIM_DMABASE_ARR
		3791	* @arg TIM_DMABASE_RCR
		3792	* @arg TIM_DMABASE_CCR1
		3793	* @arg TIM_DMABASE_CCR2
		3794	* @arg TIM_DMABASE_CCR3
		3795	* @arg TIM_DMABASE_CCR4
		3796	* @arg TIM_DMABASE_BDTR
		3797	* @param BurstRequestSrc TIM DMA Request sources
		3798	* This parameter can be one of the following values:
		3799	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		3800	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		3801	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		3802	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		3803	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		3804	* @arg TIM_DMA_COM: TIM Commutation DMA source
		3805	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		3806	* @param BurstBuffer The Buffer address.
		3807	* @param BurstLength DMA Burst length. This parameter can be one value
		3808	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		3809	* @note This function should be used only when BurstLength is equal to DMA data transfer length.
		3810	* @retval HAL status
		3811	*/
		3812	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
		3813	uint32_t *BurstBuffer, uint32_t BurstLength)
		3814	{
		3815	/* Check the parameters */
		3816	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
		3817	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
		3818	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3819	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
		3820
		3821	if (htim->State == HAL_TIM_STATE_BUSY)
		3822	{
		3823	return HAL_BUSY;
		3824	}
		3825	else if (htim->State == HAL_TIM_STATE_READY)
		3826	{
		3827	if ((BurstBuffer == NULL) && (BurstLength > 0U))
		3828	{
		3829	return HAL_ERROR;
		3830	}
		3831	else
		3832	{
		3833	htim->State = HAL_TIM_STATE_BUSY;
		3834	}
		3835	}
		3836	else
		3837	{
		3838	/* nothing to do */
		3839	}
		3840	switch (BurstRequestSrc)
		3841	{
		3842	case TIM_DMA_UPDATE:
		3843	{
		3844	/* Set the DMA Period elapsed callbacks */
		3845	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		3846	htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
		3847
		3848	/* Set the DMA error callback */
		3849	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		3850
		3851	/* Enable the DMA channel */
		3852	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3853	{
		3854	return HAL_ERROR;
		3855	}
		3856	break;
		3857	}
		3858	case TIM_DMA_CC1:
		3859	{
		3860	/* Set the DMA compare callbacks */
		3861	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3862	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3863
		3864	/* Set the DMA error callback */
		3865	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3866
		3867	/* Enable the DMA channel */
		3868	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
		3869	(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3870	{
		3871	return HAL_ERROR;
		3872	}
		3873	break;
		3874	}
		3875	case TIM_DMA_CC2:
		3876	{
		3877	/* Set the DMA compare callbacks */
		3878	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3879	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3880
		3881	/* Set the DMA error callback */
		3882	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		3883
		3884	/* Enable the DMA channel */
		3885	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
		3886	(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3887	{
		3888	return HAL_ERROR;
		3889	}
		3890	break;
		3891	}
		3892	case TIM_DMA_CC3:
		3893	{
		3894	/* Set the DMA compare callbacks */
		3895	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3896	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3897
		3898	/* Set the DMA error callback */
		3899	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		3900
		3901	/* Enable the DMA channel */
		3902	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
		3903	(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3904	{
		3905	return HAL_ERROR;
		3906	}
		3907	break;
		3908	}
		3909	case TIM_DMA_CC4:
		3910	{
		3911	/* Set the DMA compare callbacks */
		3912	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3913	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3914
		3915	/* Set the DMA error callback */
		3916	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		3917
		3918	/* Enable the DMA channel */
		3919	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
		3920	(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3921	{
		3922	return HAL_ERROR;
		3923	}
		3924	break;
		3925	}
		3926	case TIM_DMA_COM:
		3927	{
		3928	/* Set the DMA commutation callbacks */
		3929	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
		3930	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
		3931
		3932	/* Set the DMA error callback */
		3933	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
		3934
		3935	/* Enable the DMA channel */
		3936	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
		3937	(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3938	{
		3939	return HAL_ERROR;
		3940	}
		3941	break;
		3942	}
		3943	case TIM_DMA_TRIGGER:
		3944	{
		3945	/* Set the DMA trigger callbacks */
		3946	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
		3947	htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
		3948
		3949	/* Set the DMA error callback */
		3950	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
		3951
		3952	/* Enable the DMA channel */
		3953	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
		3954	(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		3955	{
		3956	return HAL_ERROR;
		3957	}
		3958	break;
		3959	}
		3960	default:
		3961	break;
		3962	}
		3963	/* configure the DMA Burst Mode */
		3964	htim->Instance->DCR = (BurstBaseAddress \| BurstLength);
		3965
		3966	/* Enable the TIM DMA Request */
		3967	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
		3968
		3969	htim->State = HAL_TIM_STATE_READY;
		3970
		3971	/* Return function status */
		3972	return HAL_OK;
		3973	}
		3974
		3975	/**
		3976	* @brief Stops the TIM DMA Burst mode
		3977	* @param htim TIM handle
		3978	* @param BurstRequestSrc TIM DMA Request sources to disable
		3979	* @retval HAL status
		3980	*/
		3981	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
		3982	{
		3983	HAL_StatusTypeDef status = HAL_OK;
		3984	/* Check the parameters */
		3985	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3986
		3987	/* Abort the DMA transfer (at least disable the DMA channel) */
		3988	switch (BurstRequestSrc)
		3989	{
		3990	case TIM_DMA_UPDATE:
		3991	{
		3992	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
		3993	break;
		3994	}
		3995	case TIM_DMA_CC1:
		3996	{
		3997	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		3998	break;
		3999	}
		4000	case TIM_DMA_CC2:
		4001	{
		4002	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		4003	break;
		4004	}
		4005	case TIM_DMA_CC3:
		4006	{
		4007	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		4008	break;
		4009	}
		4010	case TIM_DMA_CC4:
		4011	{
		4012	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		4013	break;
		4014	}
		4015	case TIM_DMA_COM:
		4016	{
		4017	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
		4018	break;
		4019	}
		4020	case TIM_DMA_TRIGGER:
		4021	{
		4022	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
		4023	break;
		4024	}
		4025	default:
		4026	break;
		4027	}
		4028
		4029	if (HAL_OK == status)
		4030	{
		4031	/* Disable the TIM Update DMA request */
		4032	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
		4033	}
		4034
		4035	/* Return function status */
		4036	return status;
		4037	}
		4038
		4039	/**
		4040	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
		4041	* @param htim TIM handle
		4042	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
		4043	* This parameter can be one of the following values:
		4044	* @arg TIM_DMABASE_CR1
		4045	* @arg TIM_DMABASE_CR2
		4046	* @arg TIM_DMABASE_SMCR
		4047	* @arg TIM_DMABASE_DIER
		4048	* @arg TIM_DMABASE_SR
		4049	* @arg TIM_DMABASE_EGR
		4050	* @arg TIM_DMABASE_CCMR1
		4051	* @arg TIM_DMABASE_CCMR2
		4052	* @arg TIM_DMABASE_CCER
		4053	* @arg TIM_DMABASE_CNT
		4054	* @arg TIM_DMABASE_PSC
		4055	* @arg TIM_DMABASE_ARR
		4056	* @arg TIM_DMABASE_RCR
		4057	* @arg TIM_DMABASE_CCR1
		4058	* @arg TIM_DMABASE_CCR2
		4059	* @arg TIM_DMABASE_CCR3
		4060	* @arg TIM_DMABASE_CCR4
		4061	* @arg TIM_DMABASE_BDTR
		4062	* @param BurstRequestSrc TIM DMA Request sources
		4063	* This parameter can be one of the following values:
		4064	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		4065	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		4066	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		4067	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		4068	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		4069	* @arg TIM_DMA_COM: TIM Commutation DMA source
		4070	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		4071	* @param BurstBuffer The Buffer address.
		4072	* @param BurstLength DMA Burst length. This parameter can be one value
		4073	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		4074	* @note This function should be used only when BurstLength is equal to DMA data transfer length.
		4075	* @retval HAL status
		4076	*/
		4077	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		4078	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
		4079	{
		4080	/* Check the parameters */
		4081	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
		4082	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
		4083	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		4084	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
		4085
		4086	if (htim->State == HAL_TIM_STATE_BUSY)
		4087	{
		4088	return HAL_BUSY;
		4089	}
		4090	else if (htim->State == HAL_TIM_STATE_READY)
		4091	{
		4092	if ((BurstBuffer == NULL) && (BurstLength > 0U))
		4093	{
		4094	return HAL_ERROR;
		4095	}
		4096	else
		4097	{
		4098	htim->State = HAL_TIM_STATE_BUSY;
		4099	}
		4100	}
		4101	else
		4102	{
		4103	/* nothing to do */
		4104	}
		4105	switch (BurstRequestSrc)
		4106	{
		4107	case TIM_DMA_UPDATE:
		4108	{
		4109	/* Set the DMA Period elapsed callbacks */
		4110	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		4111	htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
		4112
		4113	/* Set the DMA error callback */
		4114	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		4115
		4116	/* Enable the DMA channel */
		4117	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4118	{
		4119	return HAL_ERROR;
		4120	}
		4121	break;
		4122	}
		4123	case TIM_DMA_CC1:
		4124	{
		4125	/* Set the DMA capture callbacks */
		4126	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		4127	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4128
		4129	/* Set the DMA error callback */
		4130	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		4131
		4132	/* Enable the DMA channel */
		4133	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4134	{
		4135	return HAL_ERROR;
		4136	}
		4137	break;
		4138	}
		4139	case TIM_DMA_CC2:
		4140	{
		4141	/* Set the DMA capture/compare callbacks */
		4142	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		4143	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4144
		4145	/* Set the DMA error callback */
		4146	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		4147
		4148	/* Enable the DMA channel */
		4149	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4150	{
		4151	return HAL_ERROR;
		4152	}
		4153	break;
		4154	}
		4155	case TIM_DMA_CC3:
		4156	{
		4157	/* Set the DMA capture callbacks */
		4158	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
		4159	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4160
		4161	/* Set the DMA error callback */
		4162	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		4163
		4164	/* Enable the DMA channel */
		4165	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4166	{
		4167	return HAL_ERROR;
		4168	}
		4169	break;
		4170	}
		4171	case TIM_DMA_CC4:
		4172	{
		4173	/* Set the DMA capture callbacks */
		4174	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
		4175	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4176
		4177	/* Set the DMA error callback */
		4178	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		4179
		4180	/* Enable the DMA channel */
		4181	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4182	{
		4183	return HAL_ERROR;
		4184	}
		4185	break;
		4186	}
		4187	case TIM_DMA_COM:
		4188	{
		4189	/* Set the DMA commutation callbacks */
		4190	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
		4191	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
		4192
		4193	/* Set the DMA error callback */
		4194	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
		4195
		4196	/* Enable the DMA channel */
		4197	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4198	{
		4199	return HAL_ERROR;
		4200	}
		4201	break;
		4202	}
		4203	case TIM_DMA_TRIGGER:
		4204	{
		4205	/* Set the DMA trigger callbacks */
		4206	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
		4207	htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
		4208
		4209	/* Set the DMA error callback */
		4210	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
		4211
		4212	/* Enable the DMA channel */
		4213	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
		4214	{
		4215	return HAL_ERROR;
		4216	}
		4217	break;
		4218	}
		4219	default:
		4220	break;
		4221	}
		4222
		4223	/* configure the DMA Burst Mode */
		4224	htim->Instance->DCR = (BurstBaseAddress \| BurstLength);
		4225
		4226	/* Enable the TIM DMA Request */
		4227	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
		4228
		4229	htim->State = HAL_TIM_STATE_READY;
		4230
		4231	/* Return function status */
		4232	return HAL_OK;
		4233	}
		4234
		4235	/**
		4236	* @brief Stop the DMA burst reading
		4237	* @param htim TIM handle
		4238	* @param BurstRequestSrc TIM DMA Request sources to disable.
		4239	* @retval HAL status
		4240	*/
		4241	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
		4242	{
		4243	HAL_StatusTypeDef status = HAL_OK;
		4244	/* Check the parameters */
		4245	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		4246
		4247	/* Abort the DMA transfer (at least disable the DMA channel) */
		4248	switch (BurstRequestSrc)
		4249	{
		4250	case TIM_DMA_UPDATE:
		4251	{
		4252	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
		4253	break;
		4254	}
		4255	case TIM_DMA_CC1:
		4256	{
		4257	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		4258	break;
		4259	}
		4260	case TIM_DMA_CC2:
		4261	{
		4262	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		4263	break;
		4264	}
		4265	case TIM_DMA_CC3:
		4266	{
		4267	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		4268	break;
		4269	}
		4270	case TIM_DMA_CC4:
		4271	{
		4272	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		4273	break;
		4274	}
		4275	case TIM_DMA_COM:
		4276	{
		4277	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
		4278	break;
		4279	}
		4280	case TIM_DMA_TRIGGER:
		4281	{
		4282	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
		4283	break;
		4284	}
		4285	default:
		4286	break;
		4287	}
		4288
		4289	if (HAL_OK == status)
		4290	{
		4291	/* Disable the TIM Update DMA request */
		4292	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
		4293	}
		4294
		4295	/* Return function status */
		4296	return status;
		4297	}
		4298
		4299	/**
		4300	* @brief Generate a software event
		4301	* @param htim TIM handle
		4302	* @param EventSource specifies the event source.
		4303	* This parameter can be one of the following values:
		4304	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
		4305	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
		4306	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
		4307	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
		4308	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
		4309	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
		4310	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
		4311	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
		4312	* @note Basic timers can only generate an update event.
		4313	* @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
		4314	* @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
		4315	* supporting a break input.
		4316	* @retval HAL status
		4317	*/
		4318
		4319	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
		4320	{
		4321	/* Check the parameters */
		4322	assert_param(IS_TIM_INSTANCE(htim->Instance));
		4323	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
		4324
		4325	/* Process Locked */
		4326	__HAL_LOCK(htim);
		4327
		4328	/* Change the TIM state */
		4329	htim->State = HAL_TIM_STATE_BUSY;
		4330
		4331	/* Set the event sources */
		4332	htim->Instance->EGR = EventSource;
		4333
		4334	/* Change the TIM state */
		4335	htim->State = HAL_TIM_STATE_READY;
		4336
		4337	__HAL_UNLOCK(htim);
		4338
		4339	/* Return function status */
		4340	return HAL_OK;
		4341	}
		4342
		4343	/**
		4344	* @brief Configures the OCRef clear feature
		4345	* @param htim TIM handle
		4346	* @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
		4347	* contains the OCREF clear feature and parameters for the TIM peripheral.
		4348	* @param Channel specifies the TIM Channel
		4349	* This parameter can be one of the following values:
		4350	* @arg TIM_CHANNEL_1: TIM Channel 1
		4351	* @arg TIM_CHANNEL_2: TIM Channel 2
		4352	* @arg TIM_CHANNEL_3: TIM Channel 3
		4353	* @arg TIM_CHANNEL_4: TIM Channel 4
		4354	* @retval HAL status
		4355	*/
		4356	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
		4357	TIM_ClearInputConfigTypeDef *sClearInputConfig,
		4358	uint32_t Channel)
		4359	{
		4360	/* Check the parameters */
		4361	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
		4362	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
		4363
		4364	/* Process Locked */
		4365	__HAL_LOCK(htim);
		4366
		4367	htim->State = HAL_TIM_STATE_BUSY;
		4368
		4369	switch (sClearInputConfig->ClearInputSource)
		4370	{
		4371	case TIM_CLEARINPUTSOURCE_NONE:
		4372	{
		4373	/* Clear the OCREF clear selection bit and the the ETR Bits */
		4374	CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP));
		4375	break;
		4376	}
		4377
		4378	case TIM_CLEARINPUTSOURCE_ETR:
		4379	{
		4380	/* Check the parameters */
		4381	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
		4382	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
		4383	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
		4384
		4385	/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
		4386	if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
		4387	{
		4388	htim->State = HAL_TIM_STATE_READY;
		4389	__HAL_UNLOCK(htim);
		4390	return HAL_ERROR;
		4391	}
		4392
		4393	TIM_ETR_SetConfig(htim->Instance,
		4394	sClearInputConfig->ClearInputPrescaler,
		4395	sClearInputConfig->ClearInputPolarity,
		4396	sClearInputConfig->ClearInputFilter);
		4397	break;
		4398	}
		4399
		4400	default:
		4401	break;
		4402	}
		4403
		4404	switch (Channel)
		4405	{
		4406	case TIM_CHANNEL_1:
		4407	{
		4408	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4409	{
		4410	/* Enable the OCREF clear feature for Channel 1 */
		4411	SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
		4412	}
		4413	else
		4414	{
		4415	/* Disable the OCREF clear feature for Channel 1 */
		4416	CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
		4417	}
		4418	break;
		4419	}
		4420	case TIM_CHANNEL_2:
		4421	{
		4422	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4423	{
		4424	/* Enable the OCREF clear feature for Channel 2 */
		4425	SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
		4426	}
		4427	else
		4428	{
		4429	/* Disable the OCREF clear feature for Channel 2 */
		4430	CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
		4431	}
		4432	break;
		4433	}
		4434	case TIM_CHANNEL_3:
		4435	{
		4436	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4437	{
		4438	/* Enable the OCREF clear feature for Channel 3 */
		4439	SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
		4440	}
		4441	else
		4442	{
		4443	/* Disable the OCREF clear feature for Channel 3 */
		4444	CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
		4445	}
		4446	break;
		4447	}
		4448	case TIM_CHANNEL_4:
		4449	{
		4450	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4451	{
		4452	/* Enable the OCREF clear feature for Channel 4 */
		4453	SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
		4454	}
		4455	else
		4456	{
		4457	/* Disable the OCREF clear feature for Channel 4 */
		4458	CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
		4459	}
		4460	break;
		4461	}
		4462	default:
		4463	break;
		4464	}
		4465
		4466	htim->State = HAL_TIM_STATE_READY;
		4467
		4468	__HAL_UNLOCK(htim);
		4469
		4470	return HAL_OK;
		4471	}
		4472
		4473	/**
		4474	* @brief Configures the clock source to be used
		4475	* @param htim TIM handle
		4476	* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
		4477	* contains the clock source information for the TIM peripheral.
		4478	* @retval HAL status
		4479	*/
		4480	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
		4481	{
		4482	uint32_t tmpsmcr;
		4483
		4484	/* Process Locked */
		4485	__HAL_LOCK(htim);
		4486
		4487	htim->State = HAL_TIM_STATE_BUSY;
		4488
		4489	/* Check the parameters */
		4490	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
		4491
		4492	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
		4493	tmpsmcr = htim->Instance->SMCR;
		4494	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
		4495	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		4496	htim->Instance->SMCR = tmpsmcr;
		4497
		4498	switch (sClockSourceConfig->ClockSource)
		4499	{
		4500	case TIM_CLOCKSOURCE_INTERNAL:
		4501	{
		4502	assert_param(IS_TIM_INSTANCE(htim->Instance));
		4503	break;
		4504	}
		4505
		4506	case TIM_CLOCKSOURCE_ETRMODE1:
		4507	{
		4508	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
		4509	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
		4510
		4511	/* Check ETR input conditioning related parameters */
		4512	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
		4513	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4514	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4515
		4516	/* Configure the ETR Clock source */
		4517	TIM_ETR_SetConfig(htim->Instance,
		4518	sClockSourceConfig->ClockPrescaler,
		4519	sClockSourceConfig->ClockPolarity,
		4520	sClockSourceConfig->ClockFilter);
		4521
		4522	/* Select the External clock mode1 and the ETRF trigger */
		4523	tmpsmcr = htim->Instance->SMCR;
		4524	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
		4525	/* Write to TIMx SMCR */
		4526	htim->Instance->SMCR = tmpsmcr;
		4527	break;
		4528	}
		4529
		4530	case TIM_CLOCKSOURCE_ETRMODE2:
		4531	{
		4532	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
		4533	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
		4534
		4535	/* Check ETR input conditioning related parameters */
		4536	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
		4537	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4538	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4539
		4540	/* Configure the ETR Clock source */
		4541	TIM_ETR_SetConfig(htim->Instance,
		4542	sClockSourceConfig->ClockPrescaler,
		4543	sClockSourceConfig->ClockPolarity,
		4544	sClockSourceConfig->ClockFilter);
		4545	/* Enable the External clock mode2 */
		4546	htim->Instance->SMCR \|= TIM_SMCR_ECE;
		4547	break;
		4548	}
		4549
		4550	case TIM_CLOCKSOURCE_TI1:
		4551	{
		4552	/* Check whether or not the timer instance supports external clock mode 1 */
		4553	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		4554
		4555	/* Check TI1 input conditioning related parameters */
		4556	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4557	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4558
		4559	TIM_TI1_ConfigInputStage(htim->Instance,
		4560	sClockSourceConfig->ClockPolarity,
		4561	sClockSourceConfig->ClockFilter);
		4562	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
		4563	break;
		4564	}
		4565
		4566	case TIM_CLOCKSOURCE_TI2:
		4567	{
		4568	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
		4569	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		4570
		4571	/* Check TI2 input conditioning related parameters */
		4572	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4573	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4574
		4575	TIM_TI2_ConfigInputStage(htim->Instance,
		4576	sClockSourceConfig->ClockPolarity,
		4577	sClockSourceConfig->ClockFilter);
		4578	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
		4579	break;
		4580	}
		4581
		4582	case TIM_CLOCKSOURCE_TI1ED:
		4583	{
		4584	/* Check whether or not the timer instance supports external clock mode 1 */
		4585	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		4586
		4587	/* Check TI1 input conditioning related parameters */
		4588	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4589	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4590
		4591	TIM_TI1_ConfigInputStage(htim->Instance,
		4592	sClockSourceConfig->ClockPolarity,
		4593	sClockSourceConfig->ClockFilter);
		4594	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
		4595	break;
		4596	}
		4597
		4598	case TIM_CLOCKSOURCE_ITR0:
		4599	case TIM_CLOCKSOURCE_ITR1:
		4600	case TIM_CLOCKSOURCE_ITR2:
		4601	case TIM_CLOCKSOURCE_ITR3:
		4602	{
		4603	/* Check whether or not the timer instance supports internal trigger input */
		4604	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
		4605
		4606	TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
		4607	break;
		4608	}
		4609
		4610	default:
		4611	break;
		4612	}
		4613	htim->State = HAL_TIM_STATE_READY;
		4614
		4615	__HAL_UNLOCK(htim);
		4616
		4617	return HAL_OK;
		4618	}
		4619
		4620	/**
		4621	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
		4622	* or a XOR combination between CH1_input, CH2_input & CH3_input
		4623	* @param htim TIM handle.
		4624	* @param TI1_Selection Indicate whether or not channel 1 is connected to the
		4625	* output of a XOR gate.
		4626	* This parameter can be one of the following values:
		4627	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
		4628	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
		4629	* pins are connected to the TI1 input (XOR combination)
		4630	* @retval HAL status
		4631	*/
		4632	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
		4633	{
		4634	uint32_t tmpcr2;
		4635
		4636	/* Check the parameters */
		4637	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
		4638	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
		4639
		4640	/* Get the TIMx CR2 register value */
		4641	tmpcr2 = htim->Instance->CR2;
		4642
		4643	/* Reset the TI1 selection */
		4644	tmpcr2 &= ~TIM_CR2_TI1S;
		4645
		4646	/* Set the TI1 selection */
		4647	tmpcr2 \|= TI1_Selection;
		4648
		4649	/* Write to TIMxCR2 */
		4650	htim->Instance->CR2 = tmpcr2;
		4651
		4652	return HAL_OK;
		4653	}
		4654
		4655	/**
		4656	* @brief Configures the TIM in Slave mode
		4657	* @param htim TIM handle.
		4658	* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
		4659	* contains the selected trigger (internal trigger input, filtered
		4660	* timer input or external trigger input) and the Slave mode
		4661	* (Disable, Reset, Gated, Trigger, External clock mode 1).
		4662	* @retval HAL status
		4663	*/
		4664	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
		4665	{
		4666	/* Check the parameters */
		4667	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
		4668	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
		4669	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
		4670
		4671	__HAL_LOCK(htim);
		4672
		4673	htim->State = HAL_TIM_STATE_BUSY;
		4674
		4675	if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
		4676	{
		4677	htim->State = HAL_TIM_STATE_READY;
		4678	__HAL_UNLOCK(htim);
		4679	return HAL_ERROR;
		4680	}
		4681
		4682	/* Disable Trigger Interrupt */
		4683	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
		4684
		4685	/* Disable Trigger DMA request */
		4686	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
		4687
		4688	htim->State = HAL_TIM_STATE_READY;
		4689
		4690	__HAL_UNLOCK(htim);
		4691
		4692	return HAL_OK;
		4693	}
		4694
		4695	/**
		4696	* @brief Configures the TIM in Slave mode in interrupt mode
		4697	* @param htim TIM handle.
		4698	* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
		4699	* contains the selected trigger (internal trigger input, filtered
		4700	* timer input or external trigger input) and the Slave mode
		4701	* (Disable, Reset, Gated, Trigger, External clock mode 1).
		4702	* @retval HAL status
		4703	*/
		4704	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
		4705	TIM_SlaveConfigTypeDef *sSlaveConfig)
		4706	{
		4707	/* Check the parameters */
		4708	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
		4709	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
		4710	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
		4711
		4712	__HAL_LOCK(htim);
		4713
		4714	htim->State = HAL_TIM_STATE_BUSY;
		4715
		4716	if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
		4717	{
		4718	htim->State = HAL_TIM_STATE_READY;
		4719	__HAL_UNLOCK(htim);
		4720	return HAL_ERROR;
		4721	}
		4722
		4723	/* Enable Trigger Interrupt */
		4724	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
		4725
		4726	/* Disable Trigger DMA request */
		4727	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
		4728
		4729	htim->State = HAL_TIM_STATE_READY;
		4730
		4731	__HAL_UNLOCK(htim);
		4732
		4733	return HAL_OK;
		4734	}
		4735
		4736	/**
		4737	* @brief Read the captured value from Capture Compare unit
		4738	* @param htim TIM handle.
		4739	* @param Channel TIM Channels to be enabled
		4740	* This parameter can be one of the following values:
		4741	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		4742	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		4743	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		4744	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		4745	* @retval Captured value
		4746	*/
		4747	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
		4748	{
		4749	uint32_t tmpreg = 0U;
		4750
		4751	switch (Channel)
		4752	{
		4753	case TIM_CHANNEL_1:
		4754	{
		4755	/* Check the parameters */
		4756	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		4757
		4758	/* Return the capture 1 value */
		4759	tmpreg = htim->Instance->CCR1;
		4760
		4761	break;
		4762	}
		4763	case TIM_CHANNEL_2:
		4764	{
		4765	/* Check the parameters */
		4766	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4767
		4768	/* Return the capture 2 value */
		4769	tmpreg = htim->Instance->CCR2;
		4770
		4771	break;
		4772	}
		4773
		4774	case TIM_CHANNEL_3:
		4775	{
		4776	/* Check the parameters */
		4777	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		4778
		4779	/* Return the capture 3 value */
		4780	tmpreg = htim->Instance->CCR3;
		4781
		4782	break;
		4783	}
		4784
		4785	case TIM_CHANNEL_4:
		4786	{
		4787	/* Check the parameters */
		4788	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		4789
		4790	/* Return the capture 4 value */
		4791	tmpreg = htim->Instance->CCR4;
		4792
		4793	break;
		4794	}
		4795
		4796	default:
		4797	break;
		4798	}
		4799
		4800	return tmpreg;
		4801	}
		4802
		4803	/**
		4804	* @}
		4805	*/
		4806
		4807	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		4808	* @brief TIM Callbacks functions
		4809	*
		4810	@verbatim
		4811	==============================================================================
		4812	##### TIM Callbacks functions #####
		4813	==============================================================================
		4814	[..]
		4815	This section provides TIM callback functions:
		4816	(+) TIM Period elapsed callback
		4817	(+) TIM Output Compare callback
		4818	(+) TIM Input capture callback
		4819	(+) TIM Trigger callback
		4820	(+) TIM Error callback
		4821
		4822	@endverbatim
		4823	* @{
		4824	*/
		4825
		4826	/**
		4827	* @brief Period elapsed callback in non-blocking mode
		4828	* @param htim TIM handle
		4829	* @retval None
		4830	*/
		4831	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
		4832	{
		4833	/* Prevent unused argument(s) compilation warning */
		4834	UNUSED(htim);
		4835
		4836	/* NOTE : This function should not be modified, when the callback is needed,
		4837	the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
		4838	*/
		4839	}
		4840
		4841	/**
		4842	* @brief Period elapsed half complete callback in non-blocking mode
		4843	* @param htim TIM handle
		4844	* @retval None
		4845	*/
		4846	__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
		4847	{
		4848	/* Prevent unused argument(s) compilation warning */
		4849	UNUSED(htim);
		4850
		4851	/* NOTE : This function should not be modified, when the callback is needed,
		4852	the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
		4853	*/
		4854	}
		4855
		4856	/**
		4857	* @brief Output Compare callback in non-blocking mode
		4858	* @param htim TIM OC handle
		4859	* @retval None
		4860	*/
		4861	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
		4862	{
		4863	/* Prevent unused argument(s) compilation warning */
		4864	UNUSED(htim);
		4865
		4866	/* NOTE : This function should not be modified, when the callback is needed,
		4867	the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
		4868	*/
		4869	}
		4870
		4871	/**
		4872	* @brief Input Capture callback in non-blocking mode
		4873	* @param htim TIM IC handle
		4874	* @retval None
		4875	*/
		4876	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
		4877	{
		4878	/* Prevent unused argument(s) compilation warning */
		4879	UNUSED(htim);
		4880
		4881	/* NOTE : This function should not be modified, when the callback is needed,
		4882	the HAL_TIM_IC_CaptureCallback could be implemented in the user file
		4883	*/
		4884	}
		4885
		4886	/**
		4887	* @brief Input Capture half complete callback in non-blocking mode
		4888	* @param htim TIM IC handle
		4889	* @retval None
		4890	*/
		4891	__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
		4892	{
		4893	/* Prevent unused argument(s) compilation warning */
		4894	UNUSED(htim);
		4895
		4896	/* NOTE : This function should not be modified, when the callback is needed,
		4897	the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
		4898	*/
		4899	}
		4900
		4901	/**
		4902	* @brief PWM Pulse finished callback in non-blocking mode
		4903	* @param htim TIM handle
		4904	* @retval None
		4905	*/
		4906	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
		4907	{
		4908	/* Prevent unused argument(s) compilation warning */
		4909	UNUSED(htim);
		4910
		4911	/* NOTE : This function should not be modified, when the callback is needed,
		4912	the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
		4913	*/
		4914	}
		4915
		4916	/**
		4917	* @brief PWM Pulse finished half complete callback in non-blocking mode
		4918	* @param htim TIM handle
		4919	* @retval None
		4920	*/
		4921	__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
		4922	{
		4923	/* Prevent unused argument(s) compilation warning */
		4924	UNUSED(htim);
		4925
		4926	/* NOTE : This function should not be modified, when the callback is needed,
		4927	the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
		4928	*/
		4929	}
		4930
		4931	/**
		4932	* @brief Hall Trigger detection callback in non-blocking mode
		4933	* @param htim TIM handle
		4934	* @retval None
		4935	*/
		4936	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
		4937	{
		4938	/* Prevent unused argument(s) compilation warning */
		4939	UNUSED(htim);
		4940
		4941	/* NOTE : This function should not be modified, when the callback is needed,
		4942	the HAL_TIM_TriggerCallback could be implemented in the user file
		4943	*/
		4944	}
		4945
		4946	/**
		4947	* @brief Hall Trigger detection half complete callback in non-blocking mode
		4948	* @param htim TIM handle
		4949	* @retval None
		4950	*/
		4951	__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
		4952	{
		4953	/* Prevent unused argument(s) compilation warning */
		4954	UNUSED(htim);
		4955
		4956	/* NOTE : This function should not be modified, when the callback is needed,
		4957	the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
		4958	*/
		4959	}
		4960
		4961	/**
		4962	* @brief Timer error callback in non-blocking mode
		4963	* @param htim TIM handle
		4964	* @retval None
		4965	*/
		4966	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
		4967	{
		4968	/* Prevent unused argument(s) compilation warning */
		4969	UNUSED(htim);
		4970
		4971	/* NOTE : This function should not be modified, when the callback is needed,
		4972	the HAL_TIM_ErrorCallback could be implemented in the user file
		4973	*/
		4974	}
		4975
		4976	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		4977	/**
		4978	* @brief Register a User TIM callback to be used instead of the weak predefined callback
		4979	* @param htim tim handle
		4980	* @param CallbackID ID of the callback to be registered
		4981	* This parameter can be one of the following values:
		4982	* @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
		4983	* @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
		4984	* @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
		4985	* @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
		4986	* @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
		4987	* @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
		4988	* @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
		4989	* @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
		4990	* @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
		4991	* @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
		4992	* @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
		4993	* @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
		4994	* @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
		4995	* @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
		4996	* @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
		4997	* @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
		4998	* @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
		4999	* @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
		5000	* @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
		5001	* @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
		5002	* @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
		5003	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
		5004	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
		5005	* @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
		5006	* @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
		5007	* @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
		5008	* @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
		5009	* @param pCallback pointer to the callback function
		5010	* @retval status
		5011	*/
		5012	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		5013	pTIM_CallbackTypeDef pCallback)
		5014	{
		5015	HAL_StatusTypeDef status = HAL_OK;
		5016
		5017	if (pCallback == NULL)
		5018	{
		5019	return HAL_ERROR;
		5020	}
		5021	/* Process locked */
		5022	__HAL_LOCK(htim);
		5023
		5024	if (htim->State == HAL_TIM_STATE_READY)
		5025	{
		5026	switch (CallbackID)
		5027	{
		5028	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5029	htim->Base_MspInitCallback = pCallback;
		5030	break;
		5031
		5032	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5033	htim->Base_MspDeInitCallback = pCallback;
		5034	break;
		5035
		5036	case HAL_TIM_IC_MSPINIT_CB_ID :
		5037	htim->IC_MspInitCallback = pCallback;
		5038	break;
		5039
		5040	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5041	htim->IC_MspDeInitCallback = pCallback;
		5042	break;
		5043
		5044	case HAL_TIM_OC_MSPINIT_CB_ID :
		5045	htim->OC_MspInitCallback = pCallback;
		5046	break;
		5047
		5048	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5049	htim->OC_MspDeInitCallback = pCallback;
		5050	break;
		5051
		5052	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5053	htim->PWM_MspInitCallback = pCallback;
		5054	break;
		5055
		5056	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5057	htim->PWM_MspDeInitCallback = pCallback;
		5058	break;
		5059
		5060	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5061	htim->OnePulse_MspInitCallback = pCallback;
		5062	break;
		5063
		5064	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5065	htim->OnePulse_MspDeInitCallback = pCallback;
		5066	break;
		5067
		5068	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5069	htim->Encoder_MspInitCallback = pCallback;
		5070	break;
		5071
		5072	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5073	htim->Encoder_MspDeInitCallback = pCallback;
		5074	break;
		5075
		5076	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5077	htim->HallSensor_MspInitCallback = pCallback;
		5078	break;
		5079
		5080	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5081	htim->HallSensor_MspDeInitCallback = pCallback;
		5082	break;
		5083
		5084	case HAL_TIM_PERIOD_ELAPSED_CB_ID :
		5085	htim->PeriodElapsedCallback = pCallback;
		5086	break;
		5087
		5088	case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
		5089	htim->PeriodElapsedHalfCpltCallback = pCallback;
		5090	break;
		5091
		5092	case HAL_TIM_TRIGGER_CB_ID :
		5093	htim->TriggerCallback = pCallback;
		5094	break;
		5095
		5096	case HAL_TIM_TRIGGER_HALF_CB_ID :
		5097	htim->TriggerHalfCpltCallback = pCallback;
		5098	break;
		5099
		5100	case HAL_TIM_IC_CAPTURE_CB_ID :
		5101	htim->IC_CaptureCallback = pCallback;
		5102	break;
		5103
		5104	case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
		5105	htim->IC_CaptureHalfCpltCallback = pCallback;
		5106	break;
		5107
		5108	case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
		5109	htim->OC_DelayElapsedCallback = pCallback;
		5110	break;
		5111
		5112	case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
		5113	htim->PWM_PulseFinishedCallback = pCallback;
		5114	break;
		5115
		5116	case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
		5117	htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
		5118	break;
		5119
		5120	case HAL_TIM_ERROR_CB_ID :
		5121	htim->ErrorCallback = pCallback;
		5122	break;
		5123
		5124	case HAL_TIM_COMMUTATION_CB_ID :
		5125	htim->CommutationCallback = pCallback;
		5126	break;
		5127
		5128	case HAL_TIM_COMMUTATION_HALF_CB_ID :
		5129	htim->CommutationHalfCpltCallback = pCallback;
		5130	break;
		5131
		5132	case HAL_TIM_BREAK_CB_ID :
		5133	htim->BreakCallback = pCallback;
		5134	break;
		5135
		5136	default :
		5137	/* Return error status */
		5138	status = HAL_ERROR;
		5139	break;
		5140	}
		5141	}
		5142	else if (htim->State == HAL_TIM_STATE_RESET)
		5143	{
		5144	switch (CallbackID)
		5145	{
		5146	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5147	htim->Base_MspInitCallback = pCallback;
		5148	break;
		5149
		5150	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5151	htim->Base_MspDeInitCallback = pCallback;
		5152	break;
		5153
		5154	case HAL_TIM_IC_MSPINIT_CB_ID :
		5155	htim->IC_MspInitCallback = pCallback;
		5156	break;
		5157
		5158	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5159	htim->IC_MspDeInitCallback = pCallback;
		5160	break;
		5161
		5162	case HAL_TIM_OC_MSPINIT_CB_ID :
		5163	htim->OC_MspInitCallback = pCallback;
		5164	break;
		5165
		5166	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5167	htim->OC_MspDeInitCallback = pCallback;
		5168	break;
		5169
		5170	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5171	htim->PWM_MspInitCallback = pCallback;
		5172	break;
		5173
		5174	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5175	htim->PWM_MspDeInitCallback = pCallback;
		5176	break;
		5177
		5178	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5179	htim->OnePulse_MspInitCallback = pCallback;
		5180	break;
		5181
		5182	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5183	htim->OnePulse_MspDeInitCallback = pCallback;
		5184	break;
		5185
		5186	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5187	htim->Encoder_MspInitCallback = pCallback;
		5188	break;
		5189
		5190	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5191	htim->Encoder_MspDeInitCallback = pCallback;
		5192	break;
		5193
		5194	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5195	htim->HallSensor_MspInitCallback = pCallback;
		5196	break;
		5197
		5198	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5199	htim->HallSensor_MspDeInitCallback = pCallback;
		5200	break;
		5201
		5202	default :
		5203	/* Return error status */
		5204	status = HAL_ERROR;
		5205	break;
		5206	}
		5207	}
		5208	else
		5209	{
		5210	/* Return error status */
		5211	status = HAL_ERROR;
		5212	}
		5213
		5214	/* Release Lock */
		5215	__HAL_UNLOCK(htim);
		5216
		5217	return status;
		5218	}
		5219
		5220	/**
		5221	* @brief Unregister a TIM callback
		5222	* TIM callback is redirected to the weak predefined callback
		5223	* @param htim tim handle
		5224	* @param CallbackID ID of the callback to be unregistered
		5225	* This parameter can be one of the following values:
		5226	* @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
		5227	* @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
		5228	* @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
		5229	* @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
		5230	* @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
		5231	* @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
		5232	* @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
		5233	* @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
		5234	* @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
		5235	* @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
		5236	* @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
		5237	* @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
		5238	* @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
		5239	* @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
		5240	* @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
		5241	* @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
		5242	* @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
		5243	* @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
		5244	* @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
		5245	* @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
		5246	* @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
		5247	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
		5248	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
		5249	* @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
		5250	* @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
		5251	* @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
		5252	* @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
		5253	* @retval status
		5254	*/
		5255	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
		5256	{
		5257	HAL_StatusTypeDef status = HAL_OK;
		5258
		5259	/* Process locked */
		5260	__HAL_LOCK(htim);
		5261
		5262	if (htim->State == HAL_TIM_STATE_READY)
		5263	{
		5264	switch (CallbackID)
		5265	{
		5266	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5267	htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
		5268	break;
		5269
		5270	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5271	htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
		5272	break;
		5273
		5274	case HAL_TIM_IC_MSPINIT_CB_ID :
		5275	htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
		5276	break;
		5277
		5278	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5279	htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
		5280	break;
		5281
		5282	case HAL_TIM_OC_MSPINIT_CB_ID :
		5283	htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
		5284	break;
		5285
		5286	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5287	htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
		5288	break;
		5289
		5290	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5291	htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
		5292	break;
		5293
		5294	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5295	htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
		5296	break;
		5297
		5298	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5299	htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
		5300	break;
		5301
		5302	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5303	htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
		5304	break;
		5305
		5306	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5307	htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
		5308	break;
		5309
		5310	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5311	htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
		5312	break;
		5313
		5314	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5315	htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
		5316	break;
		5317
		5318	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5319	htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
		5320	break;
		5321
		5322	case HAL_TIM_PERIOD_ELAPSED_CB_ID :
		5323	htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
		5324	break;
		5325
		5326	case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
		5327	htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
		5328	break;
		5329
		5330	case HAL_TIM_TRIGGER_CB_ID :
		5331	htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
		5332	break;
		5333
		5334	case HAL_TIM_TRIGGER_HALF_CB_ID :
		5335	htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
		5336	break;
		5337
		5338	case HAL_TIM_IC_CAPTURE_CB_ID :
		5339	htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
		5340	break;
		5341
		5342	case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
		5343	htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
		5344	break;
		5345
		5346	case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
		5347	htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
		5348	break;
		5349
		5350	case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
		5351	htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
		5352	break;
		5353
		5354	case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
		5355	htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
		5356	break;
		5357
		5358	case HAL_TIM_ERROR_CB_ID :
		5359	htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
		5360	break;
		5361
		5362	case HAL_TIM_COMMUTATION_CB_ID :
		5363	htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
		5364	break;
		5365
		5366	case HAL_TIM_COMMUTATION_HALF_CB_ID :
		5367	htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
		5368	break;
		5369
		5370	case HAL_TIM_BREAK_CB_ID :
		5371	htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
		5372	break;
		5373
		5374	default :
		5375	/* Return error status */
		5376	status = HAL_ERROR;
		5377	break;
		5378	}
		5379	}
		5380	else if (htim->State == HAL_TIM_STATE_RESET)
		5381	{
		5382	switch (CallbackID)
		5383	{
		5384	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5385	htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
		5386	break;
		5387
		5388	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5389	htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
		5390	break;
		5391
		5392	case HAL_TIM_IC_MSPINIT_CB_ID :
		5393	htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
		5394	break;
		5395
		5396	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5397	htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
		5398	break;
		5399
		5400	case HAL_TIM_OC_MSPINIT_CB_ID :
		5401	htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
		5402	break;
		5403
		5404	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5405	htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
		5406	break;
		5407
		5408	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5409	htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
		5410	break;
		5411
		5412	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5413	htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
		5414	break;
		5415
		5416	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5417	htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
		5418	break;
		5419
		5420	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5421	htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
		5422	break;
		5423
		5424	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5425	htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
		5426	break;
		5427
		5428	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5429	htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
		5430	break;
		5431
		5432	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5433	htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
		5434	break;
		5435
		5436	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5437	htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
		5438	break;
		5439
		5440	default :
		5441	/* Return error status */
		5442	status = HAL_ERROR;
		5443	break;
		5444	}
		5445	}
		5446	else
		5447	{
		5448	/* Return error status */
		5449	status = HAL_ERROR;
		5450	}
		5451
		5452	/* Release Lock */
		5453	__HAL_UNLOCK(htim);
		5454
		5455	return status;
		5456	}
		5457	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5458
		5459	/**
		5460	* @}
		5461	*/
		5462
		5463	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		5464	* @brief TIM Peripheral State functions
		5465	*
		5466	@verbatim
		5467	==============================================================================
		5468	##### Peripheral State functions #####
		5469	==============================================================================
		5470	[..]
		5471	This subsection permits to get in run-time the status of the peripheral
		5472	and the data flow.
		5473
		5474	@endverbatim
		5475	* @{
		5476	*/
		5477
		5478	/**
		5479	* @brief Return the TIM Base handle state.
		5480	* @param htim TIM Base handle
		5481	* @retval HAL state
		5482	*/
		5483	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
		5484	{
		5485	return htim->State;
		5486	}
		5487
		5488	/**
		5489	* @brief Return the TIM OC handle state.
		5490	* @param htim TIM Output Compare handle
		5491	* @retval HAL state
		5492	*/
		5493	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
		5494	{
		5495	return htim->State;
		5496	}
		5497
		5498	/**
		5499	* @brief Return the TIM PWM handle state.
		5500	* @param htim TIM handle
		5501	* @retval HAL state
		5502	*/
		5503	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
		5504	{
		5505	return htim->State;
		5506	}
		5507
		5508	/**
		5509	* @brief Return the TIM Input Capture handle state.
		5510	* @param htim TIM IC handle
		5511	* @retval HAL state
		5512	*/
		5513	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
		5514	{
		5515	return htim->State;
		5516	}
		5517
		5518	/**
		5519	* @brief Return the TIM One Pulse Mode handle state.
		5520	* @param htim TIM OPM handle
		5521	* @retval HAL state
		5522	*/
		5523	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
		5524	{
		5525	return htim->State;
		5526	}
		5527
		5528	/**
		5529	* @brief Return the TIM Encoder Mode handle state.
		5530	* @param htim TIM Encoder Interface handle
		5531	* @retval HAL state
		5532	*/
		5533	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
		5534	{
		5535	return htim->State;
		5536	}
		5537
		5538	/**
		5539	* @}
		5540	*/
		5541
		5542	/**
		5543	* @}
		5544	*/
		5545
		5546	/** @defgroup TIM_Private_Functions TIM Private Functions
		5547	* @{
		5548	*/
		5549
		5550	/**
		5551	* @brief TIM DMA error callback
		5552	* @param hdma pointer to DMA handle.
		5553	* @retval None
		5554	*/
		5555	void TIM_DMAError(DMA_HandleTypeDef *hdma)
		5556	{
		5557	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5558
		5559	htim->State = HAL_TIM_STATE_READY;
		5560
		5561	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5562	htim->ErrorCallback(htim);
		5563	#else
		5564	HAL_TIM_ErrorCallback(htim);
		5565	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5566	}
		5567
		5568	/**
		5569	* @brief TIM DMA Delay Pulse complete callback.
		5570	* @param hdma pointer to DMA handle.
		5571	* @retval None
		5572	*/
		5573	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
		5574	{
		5575	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5576
		5577	htim->State = HAL_TIM_STATE_READY;
		5578
		5579	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5580	{
		5581	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5582	}
		5583	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5584	{
		5585	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5586	}
		5587	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5588	{
		5589	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5590	}
		5591	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5592	{
		5593	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5594	}
		5595	else
		5596	{
		5597	/* nothing to do */
		5598	}
		5599
		5600	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5601	htim->PWM_PulseFinishedCallback(htim);
		5602	#else
		5603	HAL_TIM_PWM_PulseFinishedCallback(htim);
		5604	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5605
		5606	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5607	}
		5608
		5609	/**
		5610	* @brief TIM DMA Delay Pulse half complete callback.
		5611	* @param hdma pointer to DMA handle.
		5612	* @retval None
		5613	*/
		5614	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
		5615	{
		5616	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5617
		5618	htim->State = HAL_TIM_STATE_READY;
		5619
		5620	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5621	{
		5622	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5623	}
		5624	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5625	{
		5626	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5627	}
		5628	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5629	{
		5630	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5631	}
		5632	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5633	{
		5634	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5635	}
		5636	else
		5637	{
		5638	/* nothing to do */
		5639	}
		5640
		5641	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5642	htim->PWM_PulseFinishedHalfCpltCallback(htim);
		5643	#else
		5644	HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
		5645	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5646
		5647	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5648	}
		5649
		5650	/**
		5651	* @brief TIM DMA Capture complete callback.
		5652	* @param hdma pointer to DMA handle.
		5653	* @retval None
		5654	*/
		5655	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
		5656	{
		5657	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5658
		5659	htim->State = HAL_TIM_STATE_READY;
		5660
		5661	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5662	{
		5663	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5664	}
		5665	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5666	{
		5667	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5668	}
		5669	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5670	{
		5671	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5672	}
		5673	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5674	{
		5675	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5676	}
		5677	else
		5678	{
		5679	/* nothing to do */
		5680	}
		5681
		5682	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5683	htim->IC_CaptureCallback(htim);
		5684	#else
		5685	HAL_TIM_IC_CaptureCallback(htim);
		5686	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5687
		5688	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5689	}
		5690
		5691	/**
		5692	* @brief TIM DMA Capture half complete callback.
		5693	* @param hdma pointer to DMA handle.
		5694	* @retval None
		5695	*/
		5696	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
		5697	{
		5698	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5699
		5700	htim->State = HAL_TIM_STATE_READY;
		5701
		5702	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5703	{
		5704	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5705	}
		5706	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5707	{
		5708	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5709	}
		5710	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5711	{
		5712	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5713	}
		5714	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5715	{
		5716	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5717	}
		5718	else
		5719	{
		5720	/* nothing to do */
		5721	}
		5722
		5723	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5724	htim->IC_CaptureHalfCpltCallback(htim);
		5725	#else
		5726	HAL_TIM_IC_CaptureHalfCpltCallback(htim);
		5727	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5728
		5729	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5730	}
		5731
		5732	/**
		5733	* @brief TIM DMA Period Elapse complete callback.
		5734	* @param hdma pointer to DMA handle.
		5735	* @retval None
		5736	*/
		5737	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
		5738	{
		5739	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5740
		5741	htim->State = HAL_TIM_STATE_READY;
		5742
		5743	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5744	htim->PeriodElapsedCallback(htim);
		5745	#else
		5746	HAL_TIM_PeriodElapsedCallback(htim);
		5747	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5748	}
		5749
		5750	/**
		5751	* @brief TIM DMA Period Elapse half complete callback.
		5752	* @param hdma pointer to DMA handle.
		5753	* @retval None
		5754	*/
		5755	static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
		5756	{
		5757	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5758
		5759	htim->State = HAL_TIM_STATE_READY;
		5760
		5761	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5762	htim->PeriodElapsedHalfCpltCallback(htim);
		5763	#else
		5764	HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
		5765	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5766	}
		5767
		5768	/**
		5769	* @brief TIM DMA Trigger callback.
		5770	* @param hdma pointer to DMA handle.
		5771	* @retval None
		5772	*/
		5773	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
		5774	{
		5775	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5776
		5777	htim->State = HAL_TIM_STATE_READY;
		5778
		5779	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5780	htim->TriggerCallback(htim);
		5781	#else
		5782	HAL_TIM_TriggerCallback(htim);
		5783	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5784	}
		5785
		5786	/**
		5787	* @brief TIM DMA Trigger half complete callback.
		5788	* @param hdma pointer to DMA handle.
		5789	* @retval None
		5790	*/
		5791	static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
		5792	{
		5793	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5794
		5795	htim->State = HAL_TIM_STATE_READY;
		5796
		5797	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5798	htim->TriggerHalfCpltCallback(htim);
		5799	#else
		5800	HAL_TIM_TriggerHalfCpltCallback(htim);
		5801	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5802	}
		5803
		5804	/**
		5805	* @brief Time Base configuration
		5806	* @param TIMx TIM peripheral
		5807	* @param Structure TIM Base configuration structure
		5808	* @retval None
		5809	*/
		5810	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
		5811	{
		5812	uint32_t tmpcr1;
		5813	tmpcr1 = TIMx->CR1;
		5814
		5815	/* Set TIM Time Base Unit parameters ---------------------------------------*/
		5816	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
		5817	{
		5818	/* Select the Counter Mode */
		5819	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
		5820	tmpcr1 \|= Structure->CounterMode;
		5821	}
		5822
		5823	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
		5824	{
		5825	/* Set the clock division */
		5826	tmpcr1 &= ~TIM_CR1_CKD;
		5827	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
		5828	}
		5829
		5830	/* Set the auto-reload preload */
		5831	MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
		5832
		5833	TIMx->CR1 = tmpcr1;
		5834
		5835	/* Set the Autoreload value */
		5836	TIMx->ARR = (uint32_t)Structure->Period ;
		5837
		5838	/* Set the Prescaler value */
		5839	TIMx->PSC = Structure->Prescaler;
		5840
		5841	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
		5842	{
		5843	/* Set the Repetition Counter value */
		5844	TIMx->RCR = Structure->RepetitionCounter;
		5845	}
		5846
		5847	/* Generate an update event to reload the Prescaler
		5848	and the repetition counter (only for advanced timer) value immediately */
		5849	TIMx->EGR = TIM_EGR_UG;
		5850	}
		5851
		5852	/**
		5853	* @brief Timer Output Compare 1 configuration
		5854	* @param TIMx to select the TIM peripheral
		5855	* @param OC_Config The ouput configuration structure
		5856	* @retval None
		5857	*/
		5858	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		5859	{
		5860	uint32_t tmpccmrx;
		5861	uint32_t tmpccer;
		5862	uint32_t tmpcr2;
		5863
		5864	/* Disable the Channel 1: Reset the CC1E Bit */
		5865	TIMx->CCER &= ~TIM_CCER_CC1E;
		5866
		5867	/* Get the TIMx CCER register value */
		5868	tmpccer = TIMx->CCER;
		5869	/* Get the TIMx CR2 register value */
		5870	tmpcr2 = TIMx->CR2;
		5871
		5872	/* Get the TIMx CCMR1 register value */
		5873	tmpccmrx = TIMx->CCMR1;
		5874
		5875	/* Reset the Output Compare Mode Bits */
		5876	tmpccmrx &= ~TIM_CCMR1_OC1M;
		5877	tmpccmrx &= ~TIM_CCMR1_CC1S;
		5878	/* Select the Output Compare Mode */
		5879	tmpccmrx \|= OC_Config->OCMode;
		5880
		5881	/* Reset the Output Polarity level */
		5882	tmpccer &= ~TIM_CCER_CC1P;
		5883	/* Set the Output Compare Polarity */
		5884	tmpccer \|= OC_Config->OCPolarity;
		5885
		5886	if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
		5887	{
		5888	/* Check parameters */
		5889	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		5890
		5891	/* Reset the Output N Polarity level */
		5892	tmpccer &= ~TIM_CCER_CC1NP;
		5893	/* Set the Output N Polarity */
		5894	tmpccer \|= OC_Config->OCNPolarity;
		5895	/* Reset the Output N State */
		5896	tmpccer &= ~TIM_CCER_CC1NE;
		5897	}
		5898
		5899	if (IS_TIM_BREAK_INSTANCE(TIMx))
		5900	{
		5901	/* Check parameters */
		5902	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		5903	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		5904
		5905	/* Reset the Output Compare and Output Compare N IDLE State */
		5906	tmpcr2 &= ~TIM_CR2_OIS1;
		5907	tmpcr2 &= ~TIM_CR2_OIS1N;
		5908	/* Set the Output Idle state */
		5909	tmpcr2 \|= OC_Config->OCIdleState;
		5910	/* Set the Output N Idle state */
		5911	tmpcr2 \|= OC_Config->OCNIdleState;
		5912	}
		5913
		5914	/* Write to TIMx CR2 */
		5915	TIMx->CR2 = tmpcr2;
		5916
		5917	/* Write to TIMx CCMR1 */
		5918	TIMx->CCMR1 = tmpccmrx;
		5919
		5920	/* Set the Capture Compare Register value */
		5921	TIMx->CCR1 = OC_Config->Pulse;
		5922
		5923	/* Write to TIMx CCER */
		5924	TIMx->CCER = tmpccer;
		5925	}
		5926
		5927	/**
		5928	* @brief Timer Output Compare 2 configuration
		5929	* @param TIMx to select the TIM peripheral
		5930	* @param OC_Config The ouput configuration structure
		5931	* @retval None
		5932	*/
		5933	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		5934	{
		5935	uint32_t tmpccmrx;
		5936	uint32_t tmpccer;
		5937	uint32_t tmpcr2;
		5938
		5939	/* Disable the Channel 2: Reset the CC2E Bit */
		5940	TIMx->CCER &= ~TIM_CCER_CC2E;
		5941
		5942	/* Get the TIMx CCER register value */
		5943	tmpccer = TIMx->CCER;
		5944	/* Get the TIMx CR2 register value */
		5945	tmpcr2 = TIMx->CR2;
		5946
		5947	/* Get the TIMx CCMR1 register value */
		5948	tmpccmrx = TIMx->CCMR1;
		5949
		5950	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		5951	tmpccmrx &= ~TIM_CCMR1_OC2M;
		5952	tmpccmrx &= ~TIM_CCMR1_CC2S;
		5953
		5954	/* Select the Output Compare Mode */
		5955	tmpccmrx \|= (OC_Config->OCMode << 8U);
		5956
		5957	/* Reset the Output Polarity level */
		5958	tmpccer &= ~TIM_CCER_CC2P;
		5959	/* Set the Output Compare Polarity */
		5960	tmpccer \|= (OC_Config->OCPolarity << 4U);
		5961
		5962	if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
		5963	{
		5964	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		5965
		5966	/* Reset the Output N Polarity level */
		5967	tmpccer &= ~TIM_CCER_CC2NP;
		5968	/* Set the Output N Polarity */
		5969	tmpccer \|= (OC_Config->OCNPolarity << 4U);
		5970	/* Reset the Output N State */
		5971	tmpccer &= ~TIM_CCER_CC2NE;
		5972
		5973	}
		5974
		5975	if (IS_TIM_BREAK_INSTANCE(TIMx))
		5976	{
		5977	/* Check parameters */
		5978	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		5979	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		5980
		5981	/* Reset the Output Compare and Output Compare N IDLE State */
		5982	tmpcr2 &= ~TIM_CR2_OIS2;
		5983	tmpcr2 &= ~TIM_CR2_OIS2N;
		5984	/* Set the Output Idle state */
		5985	tmpcr2 \|= (OC_Config->OCIdleState << 2U);
		5986	/* Set the Output N Idle state */
		5987	tmpcr2 \|= (OC_Config->OCNIdleState << 2U);
		5988	}
		5989
		5990	/* Write to TIMx CR2 */
		5991	TIMx->CR2 = tmpcr2;
		5992
		5993	/* Write to TIMx CCMR1 */
		5994	TIMx->CCMR1 = tmpccmrx;
		5995
		5996	/* Set the Capture Compare Register value */
		5997	TIMx->CCR2 = OC_Config->Pulse;
		5998
		5999	/* Write to TIMx CCER */
		6000	TIMx->CCER = tmpccer;
		6001	}
		6002
		6003	/**
		6004	* @brief Timer Output Compare 3 configuration
		6005	* @param TIMx to select the TIM peripheral
		6006	* @param OC_Config The ouput configuration structure
		6007	* @retval None
		6008	*/
		6009	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		6010	{
		6011	uint32_t tmpccmrx;
		6012	uint32_t tmpccer;
		6013	uint32_t tmpcr2;
		6014
		6015	/* Disable the Channel 3: Reset the CC2E Bit */
		6016	TIMx->CCER &= ~TIM_CCER_CC3E;
		6017
		6018	/* Get the TIMx CCER register value */
		6019	tmpccer = TIMx->CCER;
		6020	/* Get the TIMx CR2 register value */
		6021	tmpcr2 = TIMx->CR2;
		6022
		6023	/* Get the TIMx CCMR2 register value */
		6024	tmpccmrx = TIMx->CCMR2;
		6025
		6026	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		6027	tmpccmrx &= ~TIM_CCMR2_OC3M;
		6028	tmpccmrx &= ~TIM_CCMR2_CC3S;
		6029	/* Select the Output Compare Mode */
		6030	tmpccmrx \|= OC_Config->OCMode;
		6031
		6032	/* Reset the Output Polarity level */
		6033	tmpccer &= ~TIM_CCER_CC3P;
		6034	/* Set the Output Compare Polarity */
		6035	tmpccer \|= (OC_Config->OCPolarity << 8U);
		6036
		6037	if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
		6038	{
		6039	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		6040
		6041	/* Reset the Output N Polarity level */
		6042	tmpccer &= ~TIM_CCER_CC3NP;
		6043	/* Set the Output N Polarity */
		6044	tmpccer \|= (OC_Config->OCNPolarity << 8U);
		6045	/* Reset the Output N State */
		6046	tmpccer &= ~TIM_CCER_CC3NE;
		6047	}
		6048
		6049	if (IS_TIM_BREAK_INSTANCE(TIMx))
		6050	{
		6051	/* Check parameters */
		6052	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		6053	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		6054
		6055	/* Reset the Output Compare and Output Compare N IDLE State */
		6056	tmpcr2 &= ~TIM_CR2_OIS3;
		6057	tmpcr2 &= ~TIM_CR2_OIS3N;
		6058	/* Set the Output Idle state */
		6059	tmpcr2 \|= (OC_Config->OCIdleState << 4U);
		6060	/* Set the Output N Idle state */
		6061	tmpcr2 \|= (OC_Config->OCNIdleState << 4U);
		6062	}
		6063
		6064	/* Write to TIMx CR2 */
		6065	TIMx->CR2 = tmpcr2;
		6066
		6067	/* Write to TIMx CCMR2 */
		6068	TIMx->CCMR2 = tmpccmrx;
		6069
		6070	/* Set the Capture Compare Register value */
		6071	TIMx->CCR3 = OC_Config->Pulse;
		6072
		6073	/* Write to TIMx CCER */
		6074	TIMx->CCER = tmpccer;
		6075	}
		6076
		6077	/**
		6078	* @brief Timer Output Compare 4 configuration
		6079	* @param TIMx to select the TIM peripheral
		6080	* @param OC_Config The ouput configuration structure
		6081	* @retval None
		6082	*/
		6083	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		6084	{
		6085	uint32_t tmpccmrx;
		6086	uint32_t tmpccer;
		6087	uint32_t tmpcr2;
		6088
		6089	/* Disable the Channel 4: Reset the CC4E Bit */
		6090	TIMx->CCER &= ~TIM_CCER_CC4E;
		6091
		6092	/* Get the TIMx CCER register value */
		6093	tmpccer = TIMx->CCER;
		6094	/* Get the TIMx CR2 register value */
		6095	tmpcr2 = TIMx->CR2;
		6096
		6097	/* Get the TIMx CCMR2 register value */
		6098	tmpccmrx = TIMx->CCMR2;
		6099
		6100	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		6101	tmpccmrx &= ~TIM_CCMR2_OC4M;
		6102	tmpccmrx &= ~TIM_CCMR2_CC4S;
		6103
		6104	/* Select the Output Compare Mode */
		6105	tmpccmrx \|= (OC_Config->OCMode << 8U);
		6106
		6107	/* Reset the Output Polarity level */
		6108	tmpccer &= ~TIM_CCER_CC4P;
		6109	/* Set the Output Compare Polarity */
		6110	tmpccer \|= (OC_Config->OCPolarity << 12U);
		6111
		6112	if (IS_TIM_BREAK_INSTANCE(TIMx))
		6113	{
		6114	/* Check parameters */
		6115	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		6116
		6117	/* Reset the Output Compare IDLE State */
		6118	tmpcr2 &= ~TIM_CR2_OIS4;
		6119
		6120	/* Set the Output Idle state */
		6121	tmpcr2 \|= (OC_Config->OCIdleState << 6U);
		6122	}
		6123
		6124	/* Write to TIMx CR2 */
		6125	TIMx->CR2 = tmpcr2;
		6126
		6127	/* Write to TIMx CCMR2 */
		6128	TIMx->CCMR2 = tmpccmrx;
		6129
		6130	/* Set the Capture Compare Register value */
		6131	TIMx->CCR4 = OC_Config->Pulse;
		6132
		6133	/* Write to TIMx CCER */
		6134	TIMx->CCER = tmpccer;
		6135	}
		6136
		6137	/**
		6138	* @brief Slave Timer configuration function
		6139	* @param htim TIM handle
		6140	* @param sSlaveConfig Slave timer configuration
		6141	* @retval None
		6142	*/
		6143	static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
		6144	TIM_SlaveConfigTypeDef *sSlaveConfig)
		6145	{
		6146	uint32_t tmpsmcr;
		6147	uint32_t tmpccmr1;
		6148	uint32_t tmpccer;
		6149
		6150	/* Get the TIMx SMCR register value */
		6151	tmpsmcr = htim->Instance->SMCR;
		6152
		6153	/* Reset the Trigger Selection Bits */
		6154	tmpsmcr &= ~TIM_SMCR_TS;
		6155	/* Set the Input Trigger source */
		6156	tmpsmcr \|= sSlaveConfig->InputTrigger;
		6157
		6158	/* Reset the slave mode Bits */
		6159	tmpsmcr &= ~TIM_SMCR_SMS;
		6160	/* Set the slave mode */
		6161	tmpsmcr \|= sSlaveConfig->SlaveMode;
		6162
		6163	/* Write to TIMx SMCR */
		6164	htim->Instance->SMCR = tmpsmcr;
		6165
		6166	/* Configure the trigger prescaler, filter, and polarity */
		6167	switch (sSlaveConfig->InputTrigger)
		6168	{
		6169	case TIM_TS_ETRF:
		6170	{
		6171	/* Check the parameters */
		6172	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
		6173	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
		6174	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		6175	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6176	/* Configure the ETR Trigger source */
		6177	TIM_ETR_SetConfig(htim->Instance,
		6178	sSlaveConfig->TriggerPrescaler,
		6179	sSlaveConfig->TriggerPolarity,
		6180	sSlaveConfig->TriggerFilter);
		6181	break;
		6182	}
		6183
		6184	case TIM_TS_TI1F_ED:
		6185	{
		6186	/* Check the parameters */
		6187	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		6188	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6189
		6190	if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
		6191	{
		6192	return HAL_ERROR;
		6193	}
		6194
		6195	/* Disable the Channel 1: Reset the CC1E Bit */
		6196	tmpccer = htim->Instance->CCER;
		6197	htim->Instance->CCER &= ~TIM_CCER_CC1E;
		6198	tmpccmr1 = htim->Instance->CCMR1;
		6199
		6200	/* Set the filter */
		6201	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		6202	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4U);
		6203
		6204	/* Write to TIMx CCMR1 and CCER registers */
		6205	htim->Instance->CCMR1 = tmpccmr1;
		6206	htim->Instance->CCER = tmpccer;
		6207	break;
		6208	}
		6209
		6210	case TIM_TS_TI1FP1:
		6211	{
		6212	/* Check the parameters */
		6213	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		6214	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		6215	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6216
		6217	/* Configure TI1 Filter and Polarity */
		6218	TIM_TI1_ConfigInputStage(htim->Instance,
		6219	sSlaveConfig->TriggerPolarity,
		6220	sSlaveConfig->TriggerFilter);
		6221	break;
		6222	}
		6223
		6224	case TIM_TS_TI2FP2:
		6225	{
		6226	/* Check the parameters */
		6227	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		6228	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		6229	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6230
		6231	/* Configure TI2 Filter and Polarity */
		6232	TIM_TI2_ConfigInputStage(htim->Instance,
		6233	sSlaveConfig->TriggerPolarity,
		6234	sSlaveConfig->TriggerFilter);
		6235	break;
		6236	}
		6237
		6238	case TIM_TS_ITR0:
		6239	case TIM_TS_ITR1:
		6240	case TIM_TS_ITR2:
		6241	case TIM_TS_ITR3:
		6242	{
		6243	/* Check the parameter */
		6244	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		6245	break;
		6246	}
		6247
		6248	default:
		6249	break;
		6250	}
		6251	return HAL_OK;
		6252	}
		6253
		6254	/**
		6255	* @brief Configure the TI1 as Input.
		6256	* @param TIMx to select the TIM peripheral.
		6257	* @param TIM_ICPolarity The Input Polarity.
		6258	* This parameter can be one of the following values:
		6259	* @arg TIM_ICPOLARITY_RISING
		6260	* @arg TIM_ICPOLARITY_FALLING
		6261	* @arg TIM_ICPOLARITY_BOTHEDGE
		6262	* @param TIM_ICSelection specifies the input to be used.
		6263	* This parameter can be one of the following values:
		6264	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
		6265	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
		6266	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
		6267	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6268	* This parameter must be a value between 0x00 and 0x0F.
		6269	* @retval None
		6270	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
		6271	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
		6272	* protected against un-initialized filter and polarity values.
		6273	*/
		6274	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6275	uint32_t TIM_ICFilter)
		6276	{
		6277	uint32_t tmpccmr1;
		6278	uint32_t tmpccer;
		6279
		6280	/* Disable the Channel 1: Reset the CC1E Bit */
		6281	TIMx->CCER &= ~TIM_CCER_CC1E;
		6282	tmpccmr1 = TIMx->CCMR1;
		6283	tmpccer = TIMx->CCER;
		6284
		6285	/* Select the Input */
		6286	if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
		6287	{
		6288	tmpccmr1 &= ~TIM_CCMR1_CC1S;
		6289	tmpccmr1 \|= TIM_ICSelection;
		6290	}
		6291	else
		6292	{
		6293	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
		6294	}
		6295
		6296	/* Set the filter */
		6297	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		6298	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
		6299
		6300	/* Select the Polarity and set the CC1E Bit */
		6301	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
		6302	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
		6303
		6304	/* Write to TIMx CCMR1 and CCER registers */
		6305	TIMx->CCMR1 = tmpccmr1;
		6306	TIMx->CCER = tmpccer;
		6307	}
		6308
		6309	/**
		6310	* @brief Configure the Polarity and Filter for TI1.
		6311	* @param TIMx to select the TIM peripheral.
		6312	* @param TIM_ICPolarity The Input Polarity.
		6313	* This parameter can be one of the following values:
		6314	* @arg TIM_ICPOLARITY_RISING
		6315	* @arg TIM_ICPOLARITY_FALLING
		6316	* @arg TIM_ICPOLARITY_BOTHEDGE
		6317	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6318	* This parameter must be a value between 0x00 and 0x0F.
		6319	* @retval None
		6320	*/
		6321	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
		6322	{
		6323	uint32_t tmpccmr1;
		6324	uint32_t tmpccer;
		6325
		6326	/* Disable the Channel 1: Reset the CC1E Bit */
		6327	tmpccer = TIMx->CCER;
		6328	TIMx->CCER &= ~TIM_CCER_CC1E;
		6329	tmpccmr1 = TIMx->CCMR1;
		6330
		6331	/* Set the filter */
		6332	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		6333	tmpccmr1 \|= (TIM_ICFilter << 4U);
		6334
		6335	/* Select the Polarity and set the CC1E Bit */
		6336	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
		6337	tmpccer \|= TIM_ICPolarity;
		6338
		6339	/* Write to TIMx CCMR1 and CCER registers */
		6340	TIMx->CCMR1 = tmpccmr1;
		6341	TIMx->CCER = tmpccer;
		6342	}
		6343
		6344	/**
		6345	* @brief Configure the TI2 as Input.
		6346	* @param TIMx to select the TIM peripheral
		6347	* @param TIM_ICPolarity The Input Polarity.
		6348	* This parameter can be one of the following values:
		6349	* @arg TIM_ICPOLARITY_RISING
		6350	* @arg TIM_ICPOLARITY_FALLING
		6351	* @arg TIM_ICPOLARITY_BOTHEDGE
		6352	* @param TIM_ICSelection specifies the input to be used.
		6353	* This parameter can be one of the following values:
		6354	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
		6355	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
		6356	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
		6357	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6358	* This parameter must be a value between 0x00 and 0x0F.
		6359	* @retval None
		6360	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
		6361	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
		6362	* protected against un-initialized filter and polarity values.
		6363	*/
		6364	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6365	uint32_t TIM_ICFilter)
		6366	{
		6367	uint32_t tmpccmr1;
		6368	uint32_t tmpccer;
		6369
		6370	/* Disable the Channel 2: Reset the CC2E Bit */
		6371	TIMx->CCER &= ~TIM_CCER_CC2E;
		6372	tmpccmr1 = TIMx->CCMR1;
		6373	tmpccer = TIMx->CCER;
		6374
		6375	/* Select the Input */
		6376	tmpccmr1 &= ~TIM_CCMR1_CC2S;
		6377	tmpccmr1 \|= (TIM_ICSelection << 8U);
		6378
		6379	/* Set the filter */
		6380	tmpccmr1 &= ~TIM_CCMR1_IC2F;
		6381	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
		6382
		6383	/* Select the Polarity and set the CC2E Bit */
		6384	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
		6385	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
		6386
		6387	/* Write to TIMx CCMR1 and CCER registers */
		6388	TIMx->CCMR1 = tmpccmr1 ;
		6389	TIMx->CCER = tmpccer;
		6390	}
		6391
		6392	/**
		6393	* @brief Configure the Polarity and Filter for TI2.
		6394	* @param TIMx to select the TIM peripheral.
		6395	* @param TIM_ICPolarity The Input Polarity.
		6396	* This parameter can be one of the following values:
		6397	* @arg TIM_ICPOLARITY_RISING
		6398	* @arg TIM_ICPOLARITY_FALLING
		6399	* @arg TIM_ICPOLARITY_BOTHEDGE
		6400	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6401	* This parameter must be a value between 0x00 and 0x0F.
		6402	* @retval None
		6403	*/
		6404	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
		6405	{
		6406	uint32_t tmpccmr1;
		6407	uint32_t tmpccer;
		6408
		6409	/* Disable the Channel 2: Reset the CC2E Bit */
		6410	TIMx->CCER &= ~TIM_CCER_CC2E;
		6411	tmpccmr1 = TIMx->CCMR1;
		6412	tmpccer = TIMx->CCER;
		6413
		6414	/* Set the filter */
		6415	tmpccmr1 &= ~TIM_CCMR1_IC2F;
		6416	tmpccmr1 \|= (TIM_ICFilter << 12U);
		6417
		6418	/* Select the Polarity and set the CC2E Bit */
		6419	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
		6420	tmpccer \|= (TIM_ICPolarity << 4U);
		6421
		6422	/* Write to TIMx CCMR1 and CCER registers */
		6423	TIMx->CCMR1 = tmpccmr1 ;
		6424	TIMx->CCER = tmpccer;
		6425	}
		6426
		6427	/**
		6428	* @brief Configure the TI3 as Input.
		6429	* @param TIMx to select the TIM peripheral
		6430	* @param TIM_ICPolarity The Input Polarity.
		6431	* This parameter can be one of the following values:
		6432	* @arg TIM_ICPOLARITY_RISING
		6433	* @arg TIM_ICPOLARITY_FALLING
		6434	* @param TIM_ICSelection specifies the input to be used.
		6435	* This parameter can be one of the following values:
		6436	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
		6437	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
		6438	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
		6439	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6440	* This parameter must be a value between 0x00 and 0x0F.
		6441	* @retval None
		6442	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
		6443	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
		6444	* protected against un-initialized filter and polarity values.
		6445	*/
		6446	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6447	uint32_t TIM_ICFilter)
		6448	{
		6449	uint32_t tmpccmr2;
		6450	uint32_t tmpccer;
		6451
		6452	/* Disable the Channel 3: Reset the CC3E Bit */
		6453	TIMx->CCER &= ~TIM_CCER_CC3E;
		6454	tmpccmr2 = TIMx->CCMR2;
		6455	tmpccer = TIMx->CCER;
		6456
		6457	/* Select the Input */
		6458	tmpccmr2 &= ~TIM_CCMR2_CC3S;
		6459	tmpccmr2 \|= TIM_ICSelection;
		6460
		6461	/* Set the filter */
		6462	tmpccmr2 &= ~TIM_CCMR2_IC3F;
		6463	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
		6464
		6465	/* Select the Polarity and set the CC3E Bit */
		6466	tmpccer &= ~(TIM_CCER_CC3P);
		6467	tmpccer \|= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
		6468
		6469	/* Write to TIMx CCMR2 and CCER registers */
		6470	TIMx->CCMR2 = tmpccmr2;
		6471	TIMx->CCER = tmpccer;
		6472	}
		6473
		6474	/**
		6475	* @brief Configure the TI4 as Input.
		6476	* @param TIMx to select the TIM peripheral
		6477	* @param TIM_ICPolarity The Input Polarity.
		6478	* This parameter can be one of the following values:
		6479	* @arg TIM_ICPOLARITY_RISING
		6480	* @arg TIM_ICPOLARITY_FALLING
		6481	* @param TIM_ICSelection specifies the input to be used.
		6482	* This parameter can be one of the following values:
		6483	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
		6484	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
		6485	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
		6486	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6487	* This parameter must be a value between 0x00 and 0x0F.
		6488	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
		6489	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
		6490	* protected against un-initialized filter and polarity values.
		6491	* @retval None
		6492	*/
		6493	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6494	uint32_t TIM_ICFilter)
		6495	{
		6496	uint32_t tmpccmr2;
		6497	uint32_t tmpccer;
		6498
		6499	/* Disable the Channel 4: Reset the CC4E Bit */
		6500	TIMx->CCER &= ~TIM_CCER_CC4E;
		6501	tmpccmr2 = TIMx->CCMR2;
		6502	tmpccer = TIMx->CCER;
		6503
		6504	/* Select the Input */
		6505	tmpccmr2 &= ~TIM_CCMR2_CC4S;
		6506	tmpccmr2 \|= (TIM_ICSelection << 8U);
		6507
		6508	/* Set the filter */
		6509	tmpccmr2 &= ~TIM_CCMR2_IC4F;
		6510	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
		6511
		6512	/* Select the Polarity and set the CC4E Bit */
		6513	tmpccer &= ~(TIM_CCER_CC4P);
		6514	tmpccer \|= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
		6515
		6516	/* Write to TIMx CCMR2 and CCER registers */
		6517	TIMx->CCMR2 = tmpccmr2;
		6518	TIMx->CCER = tmpccer ;
		6519	}
		6520
		6521	/**
		6522	* @brief Selects the Input Trigger source
		6523	* @param TIMx to select the TIM peripheral
		6524	* @param InputTriggerSource The Input Trigger source.
		6525	* This parameter can be one of the following values:
		6526	* @arg TIM_TS_ITR0: Internal Trigger 0
		6527	* @arg TIM_TS_ITR1: Internal Trigger 1
		6528	* @arg TIM_TS_ITR2: Internal Trigger 2
		6529	* @arg TIM_TS_ITR3: Internal Trigger 3
		6530	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
		6531	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
		6532	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
		6533	* @arg TIM_TS_ETRF: External Trigger input
		6534	* @retval None
		6535	*/
		6536	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
		6537	{
		6538	uint32_t tmpsmcr;
		6539
		6540	/* Get the TIMx SMCR register value */
		6541	tmpsmcr = TIMx->SMCR;
		6542	/* Reset the TS Bits */
		6543	tmpsmcr &= ~TIM_SMCR_TS;
		6544	/* Set the Input Trigger source and the slave mode*/
		6545	tmpsmcr \|= (InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1);
		6546	/* Write to TIMx SMCR */
		6547	TIMx->SMCR = tmpsmcr;
		6548	}
		6549	/**
		6550	* @brief Configures the TIMx External Trigger (ETR).
		6551	* @param TIMx to select the TIM peripheral
		6552	* @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
		6553	* This parameter can be one of the following values:
		6554	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
		6555	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
		6556	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
		6557	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
		6558	* @param TIM_ExtTRGPolarity The external Trigger Polarity.
		6559	* This parameter can be one of the following values:
		6560	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
		6561	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
		6562	* @param ExtTRGFilter External Trigger Filter.
		6563	* This parameter must be a value between 0x00 and 0x0F
		6564	* @retval None
		6565	*/
		6566	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
		6567	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
		6568	{
		6569	uint32_t tmpsmcr;
		6570
		6571	tmpsmcr = TIMx->SMCR;
		6572
		6573	/* Reset the ETR Bits */
		6574	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		6575
		6576	/* Set the Prescaler, the Filter value and the Polarity */
		6577	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8U)));
		6578
		6579	/* Write to TIMx SMCR */
		6580	TIMx->SMCR = tmpsmcr;
		6581	}
		6582
		6583	/**
		6584	* @brief Enables or disables the TIM Capture Compare Channel x.
		6585	* @param TIMx to select the TIM peripheral
		6586	* @param Channel specifies the TIM Channel
		6587	* This parameter can be one of the following values:
		6588	* @arg TIM_CHANNEL_1: TIM Channel 1
		6589	* @arg TIM_CHANNEL_2: TIM Channel 2
		6590	* @arg TIM_CHANNEL_3: TIM Channel 3
		6591	* @arg TIM_CHANNEL_4: TIM Channel 4
		6592	* @param ChannelState specifies the TIM Channel CCxE bit new state.
		6593	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
		6594	* @retval None
		6595	*/
		6596	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
		6597	{
		6598	uint32_t tmp;
		6599
		6600	/* Check the parameters */
		6601	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
		6602	assert_param(IS_TIM_CHANNELS(Channel));
		6603
		6604	tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
		6605
		6606	/* Reset the CCxE Bit */
		6607	TIMx->CCER &= ~tmp;
		6608
		6609	/* Set or reset the CCxE Bit */
		6610	TIMx->CCER \|= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
		6611	}
		6612
		6613	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		6614	/**
		6615	* @brief Reset interrupt callbacks to the legacy weak callbacks.
		6616	* @param htim pointer to a TIM_HandleTypeDef structure that contains
		6617	* the configuration information for TIM module.
		6618	* @retval None
		6619	*/
		6620	void TIM_ResetCallback(TIM_HandleTypeDef *htim)
		6621	{
		6622	/* Reset the TIM callback to the legacy weak callbacks */
		6623	htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
		6624	htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
		6625	htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
		6626	htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
		6627	htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
		6628	htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
		6629	htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
		6630	htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
		6631	htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
		6632	htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
		6633	htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
		6634	htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
		6635	htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
		6636	}
		6637	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		6638
		6639	/**
		6640	* @}
		6641	*/
		6642
		6643	#endif /* HAL_TIM_MODULE_ENABLED */
		6644	/**
		6645	* @}
		6646	*/
		6647
		6648	/**
		6649	* @}
		6650	*/
		6651	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c – Rev 2