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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_tim.c
		4	* @author MCD Application Team
		5	* @version V1.0.1
		6	* @date 31-July-2015
		7	* @brief TIM HAL module driver
		8	* This file provides firmware functions to manage the following
		9	* functionalities of the Timer (TIM) peripheral:
		10	* + Time Base Initialization
		11	* + Time Base Start
		12	* + Time Base Start Interruption
		13	* + Time Base Start DMA
		14	* + Time Output Compare/PWM Initialization
		15	* + Time Output Compare/PWM Channel Configuration
		16	* + Time Output Compare/PWM Start
		17	* + Time Output Compare/PWM Start Interruption
		18	* + Time Output Compare/PWM Start DMA
		19	* + Time Input Capture Initialization
		20	* + Time Input Capture Channel Configuration
		21	* + Time Input Capture Start
		22	* + Time Input Capture Start Interruption
		23	* + Time Input Capture Start DMA
		24	* + Time One Pulse Initialization
		25	* + Time One Pulse Channel Configuration
		26	* + Time One Pulse Start
		27	* + Time Encoder Interface Initialization
		28	* + Time Encoder Interface Start
		29	* + Time Encoder Interface Start Interruption
		30	* + Time Encoder Interface Start DMA
		31	* + Commutation Event configuration with Interruption and DMA
		32	* + Time OCRef clear configuration
		33	* + Time External Clock configuration
		34	@verbatim
		35	==============================================================================
		36	##### TIMER Generic features #####
		37	==============================================================================
		38	[..] The Timer features include:
		39	(#) 16-bit up, down, up/down auto-reload counter.
		40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
		41	counter clock frequency either by any factor between 1 and 65536.
		42	(#) Up to 4 independent channels for:
		43	(++) Input Capture
		44	(++) Output Compare
		45	(++) PWM generation (Edge and Center-aligned Mode)
		46	(++) One-pulse mode output
		47
		48	##### How to use this driver #####
		49	==============================================================================
		50	[..]
		51	(#) Initialize the TIM low level resources by implementing the following functions
		52	depending from feature used :
		53	(++) Time Base : HAL_TIM_Base_MspInit()
		54	(++) Input Capture : HAL_TIM_IC_MspInit()
		55	(++) Output Compare : HAL_TIM_OC_MspInit()
		56	(++) PWM generation : HAL_TIM_PWM_MspInit()
		57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
		58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
		59
		60	(#) Initialize the TIM low level resources :
		61	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
		62	(##) TIM pins configuration
		63	(+++) Enable the clock for the TIM GPIOs using the following function:
		64	__HAL_GPIOx_CLK_ENABLE();
		65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
		66
		67	(#) The external Clock can be configured, if needed (the default clock is the
		68	internal clock from the APBx), using the following function:
		69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
		70	any start function.
		71
		72	(#) Configure the TIM in the desired functioning mode using one of the
		73	Initialization function of this driver:
		74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
		75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
		76	Output Compare signal.
		77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
		78	PWM signal.
		79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
		80	external signal.
		81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
		82	in One Pulse Mode.
		83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
		84
		85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
		86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
		87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
		88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
		89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
		90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
		91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
		92
		93	(#) The DMA Burst is managed with the two following functions:
		94	HAL_TIM_DMABurst_WriteStart()
		95	HAL_TIM_DMABurst_ReadStart()
		96
		97	@endverbatim
		98	******************************************************************************
		99	* @attention
		100	*
		101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
		102	*
		103	* Redistribution and use in source and binary forms, with or without modification,
		104	* are permitted provided that the following conditions are met:
		105	* 1. Redistributions of source code must retain the above copyright notice,
		106	* this list of conditions and the following disclaimer.
		107	* 2. Redistributions in binary form must reproduce the above copyright notice,
		108	* this list of conditions and the following disclaimer in the documentation
		109	* and/or other materials provided with the distribution.
		110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		111	* may be used to endorse or promote products derived from this software
		112	* without specific prior written permission.
		113	*
		114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		124	*
		125	******************************************************************************
		126	*/
		127
		128	/* Includes ------------------------------------------------------------------*/
		129	#include "stm32f1xx_hal.h"
		130
		131	/** @addtogroup STM32F1xx_HAL_Driver
		132	* @{
		133	*/
		134
		135	/** @defgroup TIM TIM
		136	* @brief TIM HAL module driver
		137	* @{
		138	*/
		139
		140	#ifdef HAL_TIM_MODULE_ENABLED
		141
		142	/* Private typedef -----------------------------------------------------------*/
		143	/* Private define ------------------------------------------------------------*/
		144	/* Private macro -------------------------------------------------------------*/
		145	/* Private variables ---------------------------------------------------------*/
		146	/* Private function prototypes -----------------------------------------------*/
		147	/** @defgroup TIM_Private_Functions TIM Private Functions
		148	* @{
		149	*/
		150	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		151	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		152	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		153	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
		154	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		155	uint32_t TIM_ICFilter);
		156	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
		157	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		158	uint32_t TIM_ICFilter);
		159	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		160	uint32_t TIM_ICFilter);
		161	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
		162	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
		163	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
		164	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
		165	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
		166	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
		167	TIM_SlaveConfigTypeDef * sSlaveConfig);
		168
		169	/**
		170	* @}
		171	*/
		172
		173	/* Exported functions ---------------------------------------------------------*/
		174
		175	/** @defgroup TIM_Exported_Functions TIM Exported Functions
		176	* @{
		177	*/
		178
		179	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
		180	* @brief Time Base functions
		181	*
		182	@verbatim
		183	==============================================================================
		184	##### Time Base functions #####
		185	==============================================================================
		186	[..]
		187	This section provides functions allowing to:
		188	(+) Initialize and configure the TIM base.
		189	(+) De-initialize the TIM base.
		190	(+) Start the Time Base.
		191	(+) Stop the Time Base.
		192	(+) Start the Time Base and enable interrupt.
		193	(+) Stop the Time Base and disable interrupt.
		194	(+) Start the Time Base and enable DMA transfer.
		195	(+) Stop the Time Base and disable DMA transfer.
		196
		197	@endverbatim
		198	* @{
		199	*/
		200	/**
		201	* @brief Initializes the TIM Time base Unit according to the specified
		202	* parameters in the TIM_HandleTypeDef and create the associated handle.
		203	* @param htim : TIM Base handle
		204	* @retval HAL status
		205	*/
		206	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
		207	{
		208	/* Check the TIM handle allocation */
		209	if(htim == NULL)
		210	{
		211	return HAL_ERROR;
		212	}
		213
		214	/* Check the parameters */
		215	assert_param(IS_TIM_INSTANCE(htim->Instance));
		216	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		217	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		218
		219	if(htim->State == HAL_TIM_STATE_RESET)
		220	{
		221	/* Allocate lock resource and initialize it */
		222	htim->Lock = HAL_UNLOCKED;
		223
		224	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		225	HAL_TIM_Base_MspInit(htim);
		226	}
		227
		228	/* Set the TIM state */
		229	htim->State= HAL_TIM_STATE_BUSY;
		230
		231	/* Set the Time Base configuration */
		232	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		233
		234	/* Initialize the TIM state*/
		235	htim->State= HAL_TIM_STATE_READY;
		236
		237	return HAL_OK;
		238	}
		239
		240	/**
		241	* @brief DeInitializes the TIM Base peripheral
		242	* @param htim : TIM Base handle
		243	* @retval HAL status
		244	*/
		245	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
		246	{
		247	/* Check the parameters */
		248	assert_param(IS_TIM_INSTANCE(htim->Instance));
		249
		250	htim->State = HAL_TIM_STATE_BUSY;
		251
		252	/* Disable the TIM Peripheral Clock */
		253	__HAL_TIM_DISABLE(htim);
		254
		255	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		256	HAL_TIM_Base_MspDeInit(htim);
		257
		258	/* Change TIM state */
		259	htim->State = HAL_TIM_STATE_RESET;
		260
		261	/* Release Lock */
		262	__HAL_UNLOCK(htim);
		263
		264	return HAL_OK;
		265	}
		266
		267	/**
		268	* @brief Initializes the TIM Base MSP.
		269	* @param htim : TIM handle
		270	* @retval None
		271	*/
		272	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
		273	{
		274	/* NOTE : This function Should not be modified, when the callback is needed,
		275	the HAL_TIM_Base_MspInit could be implemented in the user file
		276	*/
		277	}
		278
		279	/**
		280	* @brief DeInitializes TIM Base MSP.
		281	* @param htim : TIM handle
		282	* @retval None
		283	*/
		284	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
		285	{
		286	/* NOTE : This function Should not be modified, when the callback is needed,
		287	the HAL_TIM_Base_MspDeInit could be implemented in the user file
		288	*/
		289	}
		290
		291
		292	/**
		293	* @brief Starts the TIM Base generation.
		294	* @param htim : TIM handle
		295	* @retval HAL status
		296	*/
		297	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
		298	{
		299	/* Check the parameters */
		300	assert_param(IS_TIM_INSTANCE(htim->Instance));
		301
		302	/* Set the TIM state */
		303	htim->State= HAL_TIM_STATE_BUSY;
		304
		305	/* Enable the Peripheral */
		306	__HAL_TIM_ENABLE(htim);
		307
		308	/* Change the TIM state*/
		309	htim->State= HAL_TIM_STATE_READY;
		310
		311	/* Return function status */
		312	return HAL_OK;
		313	}
		314
		315	/**
		316	* @brief Stops the TIM Base generation.
		317	* @param htim : TIM handle
		318	* @retval HAL status
		319	*/
		320	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
		321	{
		322	/* Check the parameters */
		323	assert_param(IS_TIM_INSTANCE(htim->Instance));
		324
		325	/* Set the TIM state */
		326	htim->State= HAL_TIM_STATE_BUSY;
		327
		328	/* Disable the Peripheral */
		329	__HAL_TIM_DISABLE(htim);
		330
		331	/* Change the TIM state*/
		332	htim->State= HAL_TIM_STATE_READY;
		333
		334	/* Return function status */
		335	return HAL_OK;
		336	}
		337
		338	/**
		339	* @brief Starts the TIM Base generation in interrupt mode.
		340	* @param htim : TIM handle
		341	* @retval HAL status
		342	*/
		343	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
		344	{
		345	/* Check the parameters */
		346	assert_param(IS_TIM_INSTANCE(htim->Instance));
		347
		348	/* Enable the TIM Update interrupt */
		349	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
		350
		351	/* Enable the Peripheral */
		352	__HAL_TIM_ENABLE(htim);
		353
		354	/* Return function status */
		355	return HAL_OK;
		356	}
		357
		358	/**
		359	* @brief Stops the TIM Base generation in interrupt mode.
		360	* @param htim : TIM handle
		361	* @retval HAL status
		362	*/
		363	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
		364	{
		365	/* Check the parameters */
		366	assert_param(IS_TIM_INSTANCE(htim->Instance));
		367	/* Disable the TIM Update interrupt */
		368	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
		369
		370	/* Disable the Peripheral */
		371	__HAL_TIM_DISABLE(htim);
		372
		373	/* Return function status */
		374	return HAL_OK;
		375	}
		376
		377	/**
		378	* @brief Starts the TIM Base generation in DMA mode.
		379	* @param htim : TIM handle
		380	* @param pData : The source Buffer address.
		381	* @param Length : The length of data to be transferred from memory to peripheral.
		382	* @retval HAL status
		383	*/
		384	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
		385	{
		386	/* Check the parameters */
		387	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
		388
		389	if((htim->State == HAL_TIM_STATE_BUSY))
		390	{
		391	return HAL_BUSY;
		392	}
		393	else if((htim->State == HAL_TIM_STATE_READY))
		394	{
		395	if((pData == 0 ) && (Length > 0))
		396	{
		397	return HAL_ERROR;
		398	}
		399	else
		400	{
		401	htim->State = HAL_TIM_STATE_BUSY;
		402	}
		403	}
		404	/* Set the DMA Period elapsed callback */
		405	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		406
		407	/* Set the DMA error callback */
		408	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		409
		410	/* Enable the DMA channel */
		411	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
		412
		413	/* Enable the TIM Update DMA request */
		414	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
		415
		416	/* Enable the Peripheral */
		417	__HAL_TIM_ENABLE(htim);
		418
		419	/* Return function status */
		420	return HAL_OK;
		421	}
		422
		423	/**
		424	* @brief Stops the TIM Base generation in DMA mode.
		425	* @param htim : TIM handle
		426	* @retval HAL status
		427	*/
		428	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
		429	{
		430	/* Check the parameters */
		431	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
		432
		433	/* Disable the TIM Update DMA request */
		434	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
		435
		436	/* Disable the Peripheral */
		437	__HAL_TIM_DISABLE(htim);
		438
		439	/* Change the htim state */
		440	htim->State = HAL_TIM_STATE_READY;
		441
		442	/* Return function status */
		443	return HAL_OK;
		444	}
		445
		446	/**
		447	* @}
		448	*/
		449
		450	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
		451	* @brief Time Output Compare functions
		452	*
		453	@verbatim
		454	==============================================================================
		455	##### Time Output Compare functions #####
		456	==============================================================================
		457	[..]
		458	This section provides functions allowing to:
		459	(+) Initialize and configure the TIM Output Compare.
		460	(+) De-initialize the TIM Output Compare.
		461	(+) Start the Time Output Compare.
		462	(+) Stop the Time Output Compare.
		463	(+) Start the Time Output Compare and enable interrupt.
		464	(+) Stop the Time Output Compare and disable interrupt.
		465	(+) Start the Time Output Compare and enable DMA transfer.
		466	(+) Stop the Time Output Compare and disable DMA transfer.
		467
		468	@endverbatim
		469	* @{
		470	*/
		471	/**
		472	* @brief Initializes the TIM Output Compare according to the specified
		473	* parameters in the TIM_HandleTypeDef and create the associated handle.
		474	* @param htim : TIM Output Compare handle
		475	* @retval HAL status
		476	*/
		477	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
		478	{
		479	/* Check the TIM handle allocation */
		480	if(htim == NULL)
		481	{
		482	return HAL_ERROR;
		483	}
		484
		485	/* Check the parameters */
		486	assert_param(IS_TIM_INSTANCE(htim->Instance));
		487	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		488	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		489
		490	if(htim->State == HAL_TIM_STATE_RESET)
		491	{
		492	/* Allocate lock resource and initialize it */
		493	htim->Lock = HAL_UNLOCKED;
		494
		495	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		496	HAL_TIM_OC_MspInit(htim);
		497	}
		498
		499	/* Set the TIM state */
		500	htim->State= HAL_TIM_STATE_BUSY;
		501
		502	/* Init the base time for the Output Compare */
		503	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		504
		505	/* Initialize the TIM state*/
		506	htim->State= HAL_TIM_STATE_READY;
		507
		508	return HAL_OK;
		509	}
		510
		511	/**
		512	* @brief DeInitializes the TIM peripheral
		513	* @param htim : TIM Output Compare handle
		514	* @retval HAL status
		515	*/
		516	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
		517	{
		518	/* Check the parameters */
		519	assert_param(IS_TIM_INSTANCE(htim->Instance));
		520
		521	htim->State = HAL_TIM_STATE_BUSY;
		522
		523	/* Disable the TIM Peripheral Clock */
		524	__HAL_TIM_DISABLE(htim);
		525
		526	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		527	HAL_TIM_OC_MspDeInit(htim);
		528
		529	/* Change TIM state */
		530	htim->State = HAL_TIM_STATE_RESET;
		531
		532	/* Release Lock */
		533	__HAL_UNLOCK(htim);
		534
		535	return HAL_OK;
		536	}
		537
		538	/**
		539	* @brief Initializes the TIM Output Compare MSP.
		540	* @param htim : TIM handle
		541	* @retval None
		542	*/
		543	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
		544	{
		545	/* NOTE : This function Should not be modified, when the callback is needed,
		546	the HAL_TIM_OC_MspInit could be implemented in the user file
		547	*/
		548	}
		549
		550	/**
		551	* @brief DeInitializes TIM Output Compare MSP.
		552	* @param htim : TIM handle
		553	* @retval None
		554	*/
		555	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
		556	{
		557	/* NOTE : This function Should not be modified, when the callback is needed,
		558	the HAL_TIM_OC_MspDeInit could be implemented in the user file
		559	*/
		560	}
		561
		562	/**
		563	* @brief Starts the TIM Output Compare signal generation.
		564	* @param htim : TIM Output Compare handle
		565	* @param Channel : TIM Channel to be enabled
		566	* This parameter can be one of the following values:
		567	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		568	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		569	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		570	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		571	* @retval HAL status
		572	*/
		573	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		574	{
		575	/* Check the parameters */
		576	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		577
		578	/* Enable the Output compare channel */
		579	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		580
		581	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		582	{
		583	/* Enable the main output */
		584	__HAL_TIM_MOE_ENABLE(htim);
		585	}
		586
		587	/* Enable the Peripheral */
		588	__HAL_TIM_ENABLE(htim);
		589
		590	/* Return function status */
		591	return HAL_OK;
		592	}
		593
		594	/**
		595	* @brief Stops the TIM Output Compare signal generation.
		596	* @param htim : TIM handle
		597	* @param Channel : TIM Channel to be disabled
		598	* This parameter can be one of the following values:
		599	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		600	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		601	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		602	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		603	* @retval HAL status
		604	*/
		605	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		606	{
		607	/* Check the parameters */
		608	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		609
		610	/* Disable the Output compare channel */
		611	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		612
		613	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		614	{
		615	/* Disable the Main Ouput */
		616	__HAL_TIM_MOE_DISABLE(htim);
		617	}
		618
		619	/* Disable the Peripheral */
		620	__HAL_TIM_DISABLE(htim);
		621
		622	/* Return function status */
		623	return HAL_OK;
		624	}
		625
		626	/**
		627	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
		628	* @param htim : TIM OC handle
		629	* @param Channel : TIM Channel to be enabled
		630	* This parameter can be one of the following values:
		631	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		632	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		633	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		634	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		635	* @retval HAL status
		636	*/
		637	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		638	{
		639	/* Check the parameters */
		640	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		641
		642	switch (Channel)
		643	{
		644	case TIM_CHANNEL_1:
		645	{
		646	/* Enable the TIM Capture/Compare 1 interrupt */
		647	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		648	}
		649	break;
		650
		651	case TIM_CHANNEL_2:
		652	{
		653	/* Enable the TIM Capture/Compare 2 interrupt */
		654	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		655	}
		656	break;
		657
		658	case TIM_CHANNEL_3:
		659	{
		660	/* Enable the TIM Capture/Compare 3 interrupt */
		661	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		662	}
		663	break;
		664
		665	case TIM_CHANNEL_4:
		666	{
		667	/* Enable the TIM Capture/Compare 4 interrupt */
		668	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		669	}
		670	break;
		671
		672	default:
		673	break;
		674	}
		675
		676	/* Enable the Output compare channel */
		677	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		678
		679	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		680	{
		681	/* Enable the main output */
		682	__HAL_TIM_MOE_ENABLE(htim);
		683	}
		684
		685	/* Enable the Peripheral */
		686	__HAL_TIM_ENABLE(htim);
		687
		688	/* Return function status */
		689	return HAL_OK;
		690	}
		691
		692	/**
		693	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
		694	* @param htim : TIM Output Compare handle
		695	* @param Channel : TIM Channel to be disabled
		696	* This parameter can be one of the following values:
		697	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		698	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		699	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		700	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		701	* @retval HAL status
		702	*/
		703	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		704	{
		705	/* Check the parameters */
		706	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		707
		708	switch (Channel)
		709	{
		710	case TIM_CHANNEL_1:
		711	{
		712	/* Disable the TIM Capture/Compare 1 interrupt */
		713	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		714	}
		715	break;
		716
		717	case TIM_CHANNEL_2:
		718	{
		719	/* Disable the TIM Capture/Compare 2 interrupt */
		720	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		721	}
		722	break;
		723
		724	case TIM_CHANNEL_3:
		725	{
		726	/* Disable the TIM Capture/Compare 3 interrupt */
		727	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		728	}
		729	break;
		730
		731	case TIM_CHANNEL_4:
		732	{
		733	/* Disable the TIM Capture/Compare 4 interrupt */
		734	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		735	}
		736	break;
		737
		738	default:
		739	break;
		740	}
		741
		742	/* Disable the Output compare channel */
		743	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		744
		745	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		746	{
		747	/* Disable the Main Ouput */
		748	__HAL_TIM_MOE_DISABLE(htim);
		749	}
		750
		751	/* Disable the Peripheral */
		752	__HAL_TIM_DISABLE(htim);
		753
		754	/* Return function status */
		755	return HAL_OK;
		756	}
		757
		758	/**
		759	* @brief Starts the TIM Output Compare signal generation in DMA mode.
		760	* @param htim : TIM Output Compare handle
		761	* @param Channel : TIM Channel to be enabled
		762	* This parameter can be one of the following values:
		763	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		764	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		765	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		766	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		767	* @param pData : The source Buffer address.
		768	* @param Length : The length of data to be transferred from memory to TIM peripheral
		769	* @retval HAL status
		770	*/
		771	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		772	{
		773	/* Check the parameters */
		774	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		775
		776	if((htim->State == HAL_TIM_STATE_BUSY))
		777	{
		778	return HAL_BUSY;
		779	}
		780	else if((htim->State == HAL_TIM_STATE_READY))
		781	{
		782	if(((uint32_t)pData == 0 ) && (Length > 0))
		783	{
		784	return HAL_ERROR;
		785	}
		786	else
		787	{
		788	htim->State = HAL_TIM_STATE_BUSY;
		789	}
		790	}
		791	switch (Channel)
		792	{
		793	case TIM_CHANNEL_1:
		794	{
		795	/* Set the DMA Period elapsed callback */
		796	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		797
		798	/* Set the DMA error callback */
		799	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		800
		801	/* Enable the DMA channel */
		802	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
		803
		804	/* Enable the TIM Capture/Compare 1 DMA request */
		805	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		806	}
		807	break;
		808
		809	case TIM_CHANNEL_2:
		810	{
		811	/* Set the DMA Period elapsed callback */
		812	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		813
		814	/* Set the DMA error callback */
		815	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		816
		817	/* Enable the DMA channel */
		818	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
		819
		820	/* Enable the TIM Capture/Compare 2 DMA request */
		821	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		822	}
		823	break;
		824
		825	case TIM_CHANNEL_3:
		826	{
		827	/* Set the DMA Period elapsed callback */
		828	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		829
		830	/* Set the DMA error callback */
		831	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		832
		833	/* Enable the DMA channel */
		834	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
		835
		836	/* Enable the TIM Capture/Compare 3 DMA request */
		837	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		838	}
		839	break;
		840
		841	case TIM_CHANNEL_4:
		842	{
		843	/* Set the DMA Period elapsed callback */
		844	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		845
		846	/* Set the DMA error callback */
		847	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		848
		849	/* Enable the DMA channel */
		850	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
		851
		852	/* Enable the TIM Capture/Compare 4 DMA request */
		853	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		854	}
		855	break;
		856
		857	default:
		858	break;
		859	}
		860
		861	/* Enable the Output compare channel */
		862	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		863
		864	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		865	{
		866	/* Enable the main output */
		867	__HAL_TIM_MOE_ENABLE(htim);
		868	}
		869
		870	/* Enable the Peripheral */
		871	__HAL_TIM_ENABLE(htim);
		872
		873	/* Return function status */
		874	return HAL_OK;
		875	}
		876
		877	/**
		878	* @brief Stops the TIM Output Compare signal generation in DMA mode.
		879	* @param htim : TIM Output Compare handle
		880	* @param Channel : TIM Channel to be disabled
		881	* This parameter can be one of the following values:
		882	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		883	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		884	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		885	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		886	* @retval HAL status
		887	*/
		888	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		889	{
		890	/* Check the parameters */
		891	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		892
		893	switch (Channel)
		894	{
		895	case TIM_CHANNEL_1:
		896	{
		897	/* Disable the TIM Capture/Compare 1 DMA request */
		898	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		899	}
		900	break;
		901
		902	case TIM_CHANNEL_2:
		903	{
		904	/* Disable the TIM Capture/Compare 2 DMA request */
		905	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		906	}
		907	break;
		908
		909	case TIM_CHANNEL_3:
		910	{
		911	/* Disable the TIM Capture/Compare 3 DMA request */
		912	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		913	}
		914	break;
		915
		916	case TIM_CHANNEL_4:
		917	{
		918	/* Disable the TIM Capture/Compare 4 interrupt */
		919	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		920	}
		921	break;
		922
		923	default:
		924	break;
		925	}
		926
		927	/* Disable the Output compare channel */
		928	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		929
		930	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		931	{
		932	/* Disable the Main Ouput */
		933	__HAL_TIM_MOE_DISABLE(htim);
		934	}
		935
		936	/* Disable the Peripheral */
		937	__HAL_TIM_DISABLE(htim);
		938
		939	/* Change the htim state */
		940	htim->State = HAL_TIM_STATE_READY;
		941
		942	/* Return function status */
		943	return HAL_OK;
		944	}
		945
		946	/**
		947	* @}
		948	*/
		949
		950	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
		951	* @brief Time PWM functions
		952	*
		953	@verbatim
		954	==============================================================================
		955	##### Time PWM functions #####
		956	==============================================================================
		957	[..]
		958	This section provides functions allowing to:
		959	(+) Initialize and configure the TIM PWM.
		960	(+) De-initialize the TIM PWM.
		961	(+) Start the Time PWM.
		962	(+) Stop the Time PWM.
		963	(+) Start the Time PWM and enable interrupt.
		964	(+) Stop the Time PWM and disable interrupt.
		965	(+) Start the Time PWM and enable DMA transfer.
		966	(+) Stop the Time PWM and disable DMA transfer.
		967
		968	@endverbatim
		969	* @{
		970	*/
		971	/**
		972	* @brief Initializes the TIM PWM Time Base according to the specified
		973	* parameters in the TIM_HandleTypeDef and create the associated handle.
		974	* @param htim : TIM handle
		975	* @retval HAL status
		976	*/
		977	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
		978	{
		979	/* Check the TIM handle allocation */
		980	if(htim == NULL)
		981	{
		982	return HAL_ERROR;
		983	}
		984
		985	/* Check the parameters */
		986	assert_param(IS_TIM_INSTANCE(htim->Instance));
		987	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		988	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		989
		990	if(htim->State == HAL_TIM_STATE_RESET)
		991	{
		992	/* Allocate lock resource and initialize it */
		993	htim->Lock = HAL_UNLOCKED;
		994
		995	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		996	HAL_TIM_PWM_MspInit(htim);
		997	}
		998
		999	/* Set the TIM state */
		1000	htim->State= HAL_TIM_STATE_BUSY;
		1001
		1002	/* Init the base time for the PWM */
		1003	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1004
		1005	/* Initialize the TIM state*/
		1006	htim->State= HAL_TIM_STATE_READY;
		1007
		1008	return HAL_OK;
		1009	}
		1010
		1011	/**
		1012	* @brief DeInitializes the TIM peripheral
		1013	* @param htim : TIM handle
		1014	* @retval HAL status
		1015	*/
		1016	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
		1017	{
		1018	/* Check the parameters */
		1019	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1020
		1021	htim->State = HAL_TIM_STATE_BUSY;
		1022
		1023	/* Disable the TIM Peripheral Clock */
		1024	__HAL_TIM_DISABLE(htim);
		1025
		1026	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		1027	HAL_TIM_PWM_MspDeInit(htim);
		1028
		1029	/* Change TIM state */
		1030	htim->State = HAL_TIM_STATE_RESET;
		1031
		1032	/* Release Lock */
		1033	__HAL_UNLOCK(htim);
		1034
		1035	return HAL_OK;
		1036	}
		1037
		1038	/**
		1039	* @brief Initializes the TIM PWM MSP.
		1040	* @param htim : TIM handle
		1041	* @retval None
		1042	*/
		1043	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
		1044	{
		1045	/* NOTE : This function Should not be modified, when the callback is needed,
		1046	the HAL_TIM_PWM_MspInit could be implemented in the user file
		1047	*/
		1048	}
		1049
		1050	/**
		1051	* @brief DeInitializes TIM PWM MSP.
		1052	* @param htim : TIM handle
		1053	* @retval None
		1054	*/
		1055	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
		1056	{
		1057	/* NOTE : This function Should not be modified, when the callback is needed,
		1058	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
		1059	*/
		1060	}
		1061
		1062	/**
		1063	* @brief Starts the PWM signal generation.
		1064	* @param htim : TIM handle
		1065	* @param Channel : TIM Channels to be enabled
		1066	* This parameter can be one of the following values:
		1067	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1068	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1069	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1070	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1071	* @retval HAL status
		1072	*/
		1073	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		1074	{
		1075	/* Check the parameters */
		1076	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1077
		1078	/* Enable the Capture compare channel */
		1079	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1080
		1081	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1082	{
		1083	/* Enable the main output */
		1084	__HAL_TIM_MOE_ENABLE(htim);
		1085	}
		1086
		1087	/* Enable the Peripheral */
		1088	__HAL_TIM_ENABLE(htim);
		1089
		1090	/* Return function status */
		1091	return HAL_OK;
		1092	}
		1093
		1094	/**
		1095	* @brief Stops the PWM signal generation.
		1096	* @param htim : TIM handle
		1097	* @param Channel : TIM Channels to be disabled
		1098	* This parameter can be one of the following values:
		1099	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1100	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1101	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1102	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1103	* @retval HAL status
		1104	*/
		1105	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		1106	{
		1107	/* Check the parameters */
		1108	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1109
		1110	/* Disable the Capture compare channel */
		1111	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1112
		1113	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1114	{
		1115	/* Disable the Main Ouput */
		1116	__HAL_TIM_MOE_DISABLE(htim);
		1117	}
		1118
		1119	/* Disable the Peripheral */
		1120	__HAL_TIM_DISABLE(htim);
		1121
		1122	/* Change the htim state */
		1123	htim->State = HAL_TIM_STATE_READY;
		1124
		1125	/* Return function status */
		1126	return HAL_OK;
		1127	}
		1128
		1129	/**
		1130	* @brief Starts the PWM signal generation in interrupt mode.
		1131	* @param htim : TIM handle
		1132	* @param Channel : TIM Channel to be disabled
		1133	* This parameter can be one of the following values:
		1134	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1135	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1136	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1137	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1138	* @retval HAL status
		1139	*/
		1140	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1141	{
		1142	/* Check the parameters */
		1143	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1144
		1145	switch (Channel)
		1146	{
		1147	case TIM_CHANNEL_1:
		1148	{
		1149	/* Enable the TIM Capture/Compare 1 interrupt */
		1150	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		1151	}
		1152	break;
		1153
		1154	case TIM_CHANNEL_2:
		1155	{
		1156	/* Enable the TIM Capture/Compare 2 interrupt */
		1157	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		1158	}
		1159	break;
		1160
		1161	case TIM_CHANNEL_3:
		1162	{
		1163	/* Enable the TIM Capture/Compare 3 interrupt */
		1164	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		1165	}
		1166	break;
		1167
		1168	case TIM_CHANNEL_4:
		1169	{
		1170	/* Enable the TIM Capture/Compare 4 interrupt */
		1171	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		1172	}
		1173	break;
		1174
		1175	default:
		1176	break;
		1177	}
		1178
		1179	/* Enable the Capture compare channel */
		1180	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1181
		1182	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1183	{
		1184	/* Enable the main output */
		1185	__HAL_TIM_MOE_ENABLE(htim);
		1186	}
		1187
		1188	/* Enable the Peripheral */
		1189	__HAL_TIM_ENABLE(htim);
		1190
		1191	/* Return function status */
		1192	return HAL_OK;
		1193	}
		1194
		1195	/**
		1196	* @brief Stops the PWM signal generation in interrupt mode.
		1197	* @param htim : TIM handle
		1198	* @param Channel : TIM Channels to be disabled
		1199	* This parameter can be one of the following values:
		1200	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1201	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1202	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1203	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1204	* @retval HAL status
		1205	*/
		1206	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
		1207	{
		1208	/* Check the parameters */
		1209	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1210
		1211	switch (Channel)
		1212	{
		1213	case TIM_CHANNEL_1:
		1214	{
		1215	/* Disable the TIM Capture/Compare 1 interrupt */
		1216	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		1217	}
		1218	break;
		1219
		1220	case TIM_CHANNEL_2:
		1221	{
		1222	/* Disable the TIM Capture/Compare 2 interrupt */
		1223	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		1224	}
		1225	break;
		1226
		1227	case TIM_CHANNEL_3:
		1228	{
		1229	/* Disable the TIM Capture/Compare 3 interrupt */
		1230	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		1231	}
		1232	break;
		1233
		1234	case TIM_CHANNEL_4:
		1235	{
		1236	/* Disable the TIM Capture/Compare 4 interrupt */
		1237	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		1238	}
		1239	break;
		1240
		1241	default:
		1242	break;
		1243	}
		1244
		1245	/* Disable the Capture compare channel */
		1246	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1247
		1248	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1249	{
		1250	/* Disable the Main Ouput */
		1251	__HAL_TIM_MOE_DISABLE(htim);
		1252	}
		1253
		1254	/* Disable the Peripheral */
		1255	__HAL_TIM_DISABLE(htim);
		1256
		1257	/* Return function status */
		1258	return HAL_OK;
		1259	}
		1260
		1261	/**
		1262	* @brief Starts the TIM PWM signal generation in DMA mode.
		1263	* @param htim : TIM handle
		1264	* @param Channel : TIM Channels to be enabled
		1265	* This parameter can be one of the following values:
		1266	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1267	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1268	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1269	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1270	* @param pData : The source Buffer address.
		1271	* @param Length : The length of data to be transferred from memory to TIM peripheral
		1272	* @retval HAL status
		1273	*/
		1274	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		1275	{
		1276	/* Check the parameters */
		1277	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1278
		1279	if((htim->State == HAL_TIM_STATE_BUSY))
		1280	{
		1281	return HAL_BUSY;
		1282	}
		1283	else if((htim->State == HAL_TIM_STATE_READY))
		1284	{
		1285	if(((uint32_t)pData == 0 ) && (Length > 0))
		1286	{
		1287	return HAL_ERROR;
		1288	}
		1289	else
		1290	{
		1291	htim->State = HAL_TIM_STATE_BUSY;
		1292	}
		1293	}
		1294	switch (Channel)
		1295	{
		1296	case TIM_CHANNEL_1:
		1297	{
		1298	/* Set the DMA Period elapsed callback */
		1299	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1300
		1301	/* Set the DMA error callback */
		1302	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		1303
		1304	/* Enable the DMA channel */
		1305	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
		1306
		1307	/* Enable the TIM Capture/Compare 1 DMA request */
		1308	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		1309	}
		1310	break;
		1311
		1312	case TIM_CHANNEL_2:
		1313	{
		1314	/* Set the DMA Period elapsed callback */
		1315	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1316
		1317	/* Set the DMA error callback */
		1318	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		1319
		1320	/* Enable the DMA channel */
		1321	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
		1322
		1323	/* Enable the TIM Capture/Compare 2 DMA request */
		1324	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		1325	}
		1326	break;
		1327
		1328	case TIM_CHANNEL_3:
		1329	{
		1330	/* Set the DMA Period elapsed callback */
		1331	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1332
		1333	/* Set the DMA error callback */
		1334	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		1335
		1336	/* Enable the DMA channel */
		1337	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
		1338
		1339	/* Enable the TIM Output Capture/Compare 3 request */
		1340	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		1341	}
		1342	break;
		1343
		1344	case TIM_CHANNEL_4:
		1345	{
		1346	/* Set the DMA Period elapsed callback */
		1347	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1348
		1349	/* Set the DMA error callback */
		1350	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		1351
		1352	/* Enable the DMA channel */
		1353	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
		1354
		1355	/* Enable the TIM Capture/Compare 4 DMA request */
		1356	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		1357	}
		1358	break;
		1359
		1360	default:
		1361	break;
		1362	}
		1363
		1364	/* Enable the Capture compare channel */
		1365	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1366
		1367	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1368	{
		1369	/* Enable the main output */
		1370	__HAL_TIM_MOE_ENABLE(htim);
		1371	}
		1372
		1373	/* Enable the Peripheral */
		1374	__HAL_TIM_ENABLE(htim);
		1375
		1376	/* Return function status */
		1377	return HAL_OK;
		1378	}
		1379
		1380	/**
		1381	* @brief Stops the TIM PWM signal generation in DMA mode.
		1382	* @param htim : TIM handle
		1383	* @param Channel : TIM Channels to be disabled
		1384	* This parameter can be one of the following values:
		1385	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1386	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1387	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1388	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1389	* @retval HAL status
		1390	*/
		1391	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		1392	{
		1393	/* Check the parameters */
		1394	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1395
		1396	switch (Channel)
		1397	{
		1398	case TIM_CHANNEL_1:
		1399	{
		1400	/* Disable the TIM Capture/Compare 1 DMA request */
		1401	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		1402	}
		1403	break;
		1404
		1405	case TIM_CHANNEL_2:
		1406	{
		1407	/* Disable the TIM Capture/Compare 2 DMA request */
		1408	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		1409	}
		1410	break;
		1411
		1412	case TIM_CHANNEL_3:
		1413	{
		1414	/* Disable the TIM Capture/Compare 3 DMA request */
		1415	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		1416	}
		1417	break;
		1418
		1419	case TIM_CHANNEL_4:
		1420	{
		1421	/* Disable the TIM Capture/Compare 4 interrupt */
		1422	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		1423	}
		1424	break;
		1425
		1426	default:
		1427	break;
		1428	}
		1429
		1430	/* Disable the Capture compare channel */
		1431	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1432
		1433	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1434	{
		1435	/* Disable the Main Ouput */
		1436	__HAL_TIM_MOE_DISABLE(htim);
		1437	}
		1438
		1439	/* Disable the Peripheral */
		1440	__HAL_TIM_DISABLE(htim);
		1441
		1442	/* Change the htim state */
		1443	htim->State = HAL_TIM_STATE_READY;
		1444
		1445	/* Return function status */
		1446	return HAL_OK;
		1447	}
		1448
		1449	/**
		1450	* @}
		1451	*/
		1452
		1453	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
		1454	* @brief Time Input Capture functions
		1455	*
		1456	@verbatim
		1457	==============================================================================
		1458	##### Time Input Capture functions #####
		1459	==============================================================================
		1460	[..]
		1461	This section provides functions allowing to:
		1462	(+) Initialize and configure the TIM Input Capture.
		1463	(+) De-initialize the TIM Input Capture.
		1464	(+) Start the Time Input Capture.
		1465	(+) Stop the Time Input Capture.
		1466	(+) Start the Time Input Capture and enable interrupt.
		1467	(+) Stop the Time Input Capture and disable interrupt.
		1468	(+) Start the Time Input Capture and enable DMA transfer.
		1469	(+) Stop the Time Input Capture and disable DMA transfer.
		1470
		1471	@endverbatim
		1472	* @{
		1473	*/
		1474	/**
		1475	* @brief Initializes the TIM Input Capture Time base according to the specified
		1476	* parameters in the TIM_HandleTypeDef and create the associated handle.
		1477	* @param htim : TIM Input Capture handle
		1478	* @retval HAL status
		1479	*/
		1480	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
		1481	{
		1482	/* Check the TIM handle allocation */
		1483	if(htim == NULL)
		1484	{
		1485	return HAL_ERROR;
		1486	}
		1487
		1488	/* Check the parameters */
		1489	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1490	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		1491	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		1492
		1493	if(htim->State == HAL_TIM_STATE_RESET)
		1494	{
		1495	/* Allocate lock resource and initialize it */
		1496	htim->Lock = HAL_UNLOCKED;
		1497
		1498	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		1499	HAL_TIM_IC_MspInit(htim);
		1500	}
		1501
		1502	/* Set the TIM state */
		1503	htim->State= HAL_TIM_STATE_BUSY;
		1504
		1505	/* Init the base time for the input capture */
		1506	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1507
		1508	/* Initialize the TIM state*/
		1509	htim->State= HAL_TIM_STATE_READY;
		1510
		1511	return HAL_OK;
		1512	}
		1513
		1514	/**
		1515	* @brief DeInitializes the TIM peripheral
		1516	* @param htim : TIM Input Capture handle
		1517	* @retval HAL status
		1518	*/
		1519	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
		1520	{
		1521	/* Check the parameters */
		1522	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1523
		1524	htim->State = HAL_TIM_STATE_BUSY;
		1525
		1526	/* Disable the TIM Peripheral Clock */
		1527	__HAL_TIM_DISABLE(htim);
		1528
		1529	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		1530	HAL_TIM_IC_MspDeInit(htim);
		1531
		1532	/* Change TIM state */
		1533	htim->State = HAL_TIM_STATE_RESET;
		1534
		1535	/* Release Lock */
		1536	__HAL_UNLOCK(htim);
		1537
		1538	return HAL_OK;
		1539	}
		1540
		1541	/**
		1542	* @brief Initializes the TIM Input Capture MSP.
		1543	* @param htim : TIM handle
		1544	* @retval None
		1545	*/
		1546	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
		1547	{
		1548	/* NOTE : This function Should not be modified, when the callback is needed,
		1549	the HAL_TIM_IC_MspInit could be implemented in the user file
		1550	*/
		1551	}
		1552
		1553	/**
		1554	* @brief DeInitializes TIM Input Capture MSP.
		1555	* @param htim : TIM handle
		1556	* @retval None
		1557	*/
		1558	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
		1559	{
		1560	/* NOTE : This function Should not be modified, when the callback is needed,
		1561	the HAL_TIM_IC_MspDeInit could be implemented in the user file
		1562	*/
		1563	}
		1564
		1565	/**
		1566	* @brief Starts the TIM Input Capture measurement.
		1567	* @param htim : TIM Input Capture handle
		1568	* @param Channel : TIM Channels to be enabled
		1569	* This parameter can be one of the following values:
		1570	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1571	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1572	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1573	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1574	* @retval HAL status
		1575	*/
		1576	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
		1577	{
		1578	/* Check the parameters */
		1579	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1580
		1581	/* Enable the Input Capture channel */
		1582	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1583
		1584	/* Enable the Peripheral */
		1585	__HAL_TIM_ENABLE(htim);
		1586
		1587	/* Return function status */
		1588	return HAL_OK;
		1589	}
		1590
		1591	/**
		1592	* @brief Stops the TIM Input Capture measurement.
		1593	* @param htim : TIM handle
		1594	* @param Channel : TIM Channels to be disabled
		1595	* This parameter can be one of the following values:
		1596	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1597	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1598	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1599	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1600	* @retval HAL status
		1601	*/
		1602	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		1603	{
		1604	/* Check the parameters */
		1605	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1606
		1607	/* Disable the Input Capture channel */
		1608	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1609
		1610	/* Disable the Peripheral */
		1611	__HAL_TIM_DISABLE(htim);
		1612
		1613	/* Return function status */
		1614	return HAL_OK;
		1615	}
		1616
		1617	/**
		1618	* @brief Starts the TIM Input Capture measurement in interrupt mode.
		1619	* @param htim : TIM Input Capture handle
		1620	* @param Channel : TIM Channels to be enabled
		1621	* This parameter can be one of the following values:
		1622	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1623	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1624	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1625	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1626	* @retval HAL status
		1627	*/
		1628	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
		1629	{
		1630	/* Check the parameters */
		1631	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1632
		1633	switch (Channel)
		1634	{
		1635	case TIM_CHANNEL_1:
		1636	{
		1637	/* Enable the TIM Capture/Compare 1 interrupt */
		1638	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		1639	}
		1640	break;
		1641
		1642	case TIM_CHANNEL_2:
		1643	{
		1644	/* Enable the TIM Capture/Compare 2 interrupt */
		1645	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		1646	}
		1647	break;
		1648
		1649	case TIM_CHANNEL_3:
		1650	{
		1651	/* Enable the TIM Capture/Compare 3 interrupt */
		1652	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		1653	}
		1654	break;
		1655
		1656	case TIM_CHANNEL_4:
		1657	{
		1658	/* Enable the TIM Capture/Compare 4 interrupt */
		1659	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		1660	}
		1661	break;
		1662
		1663	default:
		1664	break;
		1665	}
		1666	/* Enable the Input Capture channel */
		1667	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1668
		1669	/* Enable the Peripheral */
		1670	__HAL_TIM_ENABLE(htim);
		1671
		1672	/* Return function status */
		1673	return HAL_OK;
		1674	}
		1675
		1676	/**
		1677	* @brief Stops the TIM Input Capture measurement in interrupt mode.
		1678	* @param htim : TIM handle
		1679	* @param Channel : TIM Channels to be disabled
		1680	* This parameter can be one of the following values:
		1681	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1682	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1683	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1684	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1685	* @retval HAL status
		1686	*/
		1687	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1688	{
		1689	/* Check the parameters */
		1690	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1691
		1692	switch (Channel)
		1693	{
		1694	case TIM_CHANNEL_1:
		1695	{
		1696	/* Disable the TIM Capture/Compare 1 interrupt */
		1697	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		1698	}
		1699	break;
		1700
		1701	case TIM_CHANNEL_2:
		1702	{
		1703	/* Disable the TIM Capture/Compare 2 interrupt */
		1704	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		1705	}
		1706	break;
		1707
		1708	case TIM_CHANNEL_3:
		1709	{
		1710	/* Disable the TIM Capture/Compare 3 interrupt */
		1711	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		1712	}
		1713	break;
		1714
		1715	case TIM_CHANNEL_4:
		1716	{
		1717	/* Disable the TIM Capture/Compare 4 interrupt */
		1718	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		1719	}
		1720	break;
		1721
		1722	default:
		1723	break;
		1724	}
		1725
		1726	/* Disable the Input Capture channel */
		1727	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1728
		1729	/* Disable the Peripheral */
		1730	__HAL_TIM_DISABLE(htim);
		1731
		1732	/* Return function status */
		1733	return HAL_OK;
		1734	}
		1735
		1736	/**
		1737	* @brief Starts the TIM Input Capture measurement in DMA mode.
		1738	* @param htim : TIM Input Capture handle
		1739	* @param Channel : TIM Channels to be enabled
		1740	* This parameter can be one of the following values:
		1741	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1742	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1743	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1744	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1745	* @param pData : The destination Buffer address.
		1746	* @param Length : The length of data to be transferred from TIM peripheral to memory.
		1747	* @retval HAL status
		1748	*/
		1749	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		1750	{
		1751	/* Check the parameters */
		1752	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1753	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		1754
		1755	if((htim->State == HAL_TIM_STATE_BUSY))
		1756	{
		1757	return HAL_BUSY;
		1758	}
		1759	else if((htim->State == HAL_TIM_STATE_READY))
		1760	{
		1761	if((pData == 0 ) && (Length > 0))
		1762	{
		1763	return HAL_ERROR;
		1764	}
		1765	else
		1766	{
		1767	htim->State = HAL_TIM_STATE_BUSY;
		1768	}
		1769	}
		1770
		1771	switch (Channel)
		1772	{
		1773	case TIM_CHANNEL_1:
		1774	{
		1775	/* Set the DMA Period elapsed callback */
		1776	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		1777
		1778	/* Set the DMA error callback */
		1779	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		1780
		1781	/* Enable the DMA channel */
		1782	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
		1783
		1784	/* Enable the TIM Capture/Compare 1 DMA request */
		1785	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		1786	}
		1787	break;
		1788
		1789	case TIM_CHANNEL_2:
		1790	{
		1791	/* Set the DMA Period elapsed callback */
		1792	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		1793
		1794	/* Set the DMA error callback */
		1795	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		1796
		1797	/* Enable the DMA channel */
		1798	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
		1799
		1800	/* Enable the TIM Capture/Compare 2 DMA request */
		1801	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		1802	}
		1803	break;
		1804
		1805	case TIM_CHANNEL_3:
		1806	{
		1807	/* Set the DMA Period elapsed callback */
		1808	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
		1809
		1810	/* Set the DMA error callback */
		1811	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		1812
		1813	/* Enable the DMA channel */
		1814	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
		1815
		1816	/* Enable the TIM Capture/Compare 3 DMA request */
		1817	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		1818	}
		1819	break;
		1820
		1821	case TIM_CHANNEL_4:
		1822	{
		1823	/* Set the DMA Period elapsed callback */
		1824	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
		1825
		1826	/* Set the DMA error callback */
		1827	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		1828
		1829	/* Enable the DMA channel */
		1830	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
		1831
		1832	/* Enable the TIM Capture/Compare 4 DMA request */
		1833	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		1834	}
		1835	break;
		1836
		1837	default:
		1838	break;
		1839	}
		1840
		1841	/* Enable the Input Capture channel */
		1842	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1843
		1844	/* Enable the Peripheral */
		1845	__HAL_TIM_ENABLE(htim);
		1846
		1847	/* Return function status */
		1848	return HAL_OK;
		1849	}
		1850
		1851	/**
		1852	* @brief Stops the TIM Input Capture measurement in DMA mode.
		1853	* @param htim : TIM Input Capture handle
		1854	* @param Channel : TIM Channels to be disabled
		1855	* This parameter can be one of the following values:
		1856	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1857	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1858	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1859	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1860	* @retval HAL status
		1861	*/
		1862	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		1863	{
		1864	/* Check the parameters */
		1865	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1866	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		1867
		1868	switch (Channel)
		1869	{
		1870	case TIM_CHANNEL_1:
		1871	{
		1872	/* Disable the TIM Capture/Compare 1 DMA request */
		1873	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		1874	}
		1875	break;
		1876
		1877	case TIM_CHANNEL_2:
		1878	{
		1879	/* Disable the TIM Capture/Compare 2 DMA request */
		1880	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		1881	}
		1882	break;
		1883
		1884	case TIM_CHANNEL_3:
		1885	{
		1886	/* Disable the TIM Capture/Compare 3 DMA request */
		1887	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		1888	}
		1889	break;
		1890
		1891	case TIM_CHANNEL_4:
		1892	{
		1893	/* Disable the TIM Capture/Compare 4 DMA request */
		1894	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		1895	}
		1896	break;
		1897
		1898	default:
		1899	break;
		1900	}
		1901
		1902	/* Disable the Input Capture channel */
		1903	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1904
		1905	/* Disable the Peripheral */
		1906	__HAL_TIM_DISABLE(htim);
		1907
		1908	/* Change the htim state */
		1909	htim->State = HAL_TIM_STATE_READY;
		1910
		1911	/* Return function status */
		1912	return HAL_OK;
		1913	}
		1914	/**
		1915	* @}
		1916	*/
		1917
		1918	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
		1919	* @brief Time One Pulse functions
		1920	*
		1921	@verbatim
		1922	==============================================================================
		1923	##### Time One Pulse functions #####
		1924	==============================================================================
		1925	[..]
		1926	This section provides functions allowing to:
		1927	(+) Initialize and configure the TIM One Pulse.
		1928	(+) De-initialize the TIM One Pulse.
		1929	(+) Start the Time One Pulse.
		1930	(+) Stop the Time One Pulse.
		1931	(+) Start the Time One Pulse and enable interrupt.
		1932	(+) Stop the Time One Pulse and disable interrupt.
		1933	(+) Start the Time One Pulse and enable DMA transfer.
		1934	(+) Stop the Time One Pulse and disable DMA transfer.
		1935
		1936	@endverbatim
		1937	* @{
		1938	*/
		1939	/**
		1940	* @brief Initializes the TIM One Pulse Time Base according to the specified
		1941	* parameters in the TIM_HandleTypeDef and create the associated handle.
		1942	* @param htim : TIM OnePulse handle
		1943	* @param OnePulseMode : Select the One pulse mode.
		1944	* This parameter can be one of the following values:
		1945	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
		1946	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
		1947	* @retval HAL status
		1948	*/
		1949	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
		1950	{
		1951	/* Check the TIM handle allocation */
		1952	if(htim == NULL)
		1953	{
		1954	return HAL_ERROR;
		1955	}
		1956
		1957	/* Check the parameters */
		1958	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1959	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		1960	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		1961	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
		1962
		1963	if(htim->State == HAL_TIM_STATE_RESET)
		1964	{
		1965	/* Allocate lock resource and initialize it */
		1966	htim->Lock = HAL_UNLOCKED;
		1967
		1968	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		1969	HAL_TIM_OnePulse_MspInit(htim);
		1970	}
		1971
		1972	/* Set the TIM state */
		1973	htim->State= HAL_TIM_STATE_BUSY;
		1974
		1975	/* Configure the Time base in the One Pulse Mode */
		1976	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1977
		1978	/* Reset the OPM Bit */
		1979	htim->Instance->CR1 &= ~TIM_CR1_OPM;
		1980
		1981	/* Configure the OPM Mode */
		1982	htim->Instance->CR1 \|= OnePulseMode;
		1983
		1984	/* Initialize the TIM state*/
		1985	htim->State= HAL_TIM_STATE_READY;
		1986
		1987	return HAL_OK;
		1988	}
		1989
		1990	/**
		1991	* @brief DeInitializes the TIM One Pulse
		1992	* @param htim : TIM One Pulse handle
		1993	* @retval HAL status
		1994	*/
		1995	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
		1996	{
		1997	/* Check the parameters */
		1998	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1999
		2000	htim->State = HAL_TIM_STATE_BUSY;
		2001
		2002	/* Disable the TIM Peripheral Clock */
		2003	__HAL_TIM_DISABLE(htim);
		2004
		2005	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		2006	HAL_TIM_OnePulse_MspDeInit(htim);
		2007
		2008	/* Change TIM state */
		2009	htim->State = HAL_TIM_STATE_RESET;
		2010
		2011	/* Release Lock */
		2012	__HAL_UNLOCK(htim);
		2013
		2014	return HAL_OK;
		2015	}
		2016
		2017	/**
		2018	* @brief Initializes the TIM One Pulse MSP.
		2019	* @param htim : TIM handle
		2020	* @retval None
		2021	*/
		2022	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
		2023	{
		2024	/* NOTE : This function Should not be modified, when the callback is needed,
		2025	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
		2026	*/
		2027	}
		2028
		2029	/**
		2030	* @brief DeInitializes TIM One Pulse MSP.
		2031	* @param htim : TIM handle
		2032	* @retval None
		2033	*/
		2034	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
		2035	{
		2036	/* NOTE : This function Should not be modified, when the callback is needed,
		2037	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
		2038	*/
		2039	}
		2040
		2041	/**
		2042	* @brief Starts the TIM One Pulse signal generation.
		2043	* @param htim : TIM One Pulse handle
		2044	* @param OutputChannel : TIM Channels to be enabled
		2045	* This parameter can be one of the following values:
		2046	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2047	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2048	* @retval HAL status
		2049	*/
		2050	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2051	{
		2052	/* Enable the Capture compare and the Input Capture channels
		2053	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2054	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2055	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2056	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
		2057
		2058	No need to enable the counter, it's enabled automatically by hardware
		2059	(the counter starts in response to a stimulus and generate a pulse */
		2060
		2061	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2062	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2063
		2064	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2065	{
		2066	/* Enable the main output */
		2067	__HAL_TIM_MOE_ENABLE(htim);
		2068	}
		2069
		2070	/* Return function status */
		2071	return HAL_OK;
		2072	}
		2073
		2074	/**
		2075	* @brief Stops the TIM One Pulse signal generation.
		2076	* @param htim : TIM One Pulse handle
		2077	* @param OutputChannel : TIM Channels to be disable
		2078	* This parameter can be one of the following values:
		2079	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2080	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2081	* @retval HAL status
		2082	*/
		2083	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2084	{
		2085	/* Disable the Capture compare and the Input Capture channels
		2086	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2087	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2088	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2089	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
		2090
		2091	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2092	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2093
		2094	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2095	{
		2096	/* Disable the Main Ouput */
		2097	__HAL_TIM_MOE_DISABLE(htim);
		2098	}
		2099
		2100	/* Disable the Peripheral */
		2101	__HAL_TIM_DISABLE(htim);
		2102
		2103	/* Return function status */
		2104	return HAL_OK;
		2105	}
		2106
		2107	/**
		2108	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
		2109	* @param htim : TIM One Pulse handle
		2110	* @param OutputChannel : TIM Channels to be enabled
		2111	* This parameter can be one of the following values:
		2112	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2113	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2114	* @retval HAL status
		2115	*/
		2116	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2117	{
		2118	/* Enable the Capture compare and the Input Capture channels
		2119	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2120	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2121	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2122	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
		2123
		2124	No need to enable the counter, it's enabled automatically by hardware
		2125	(the counter starts in response to a stimulus and generate a pulse */
		2126
		2127	/* Enable the TIM Capture/Compare 1 interrupt */
		2128	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2129
		2130	/* Enable the TIM Capture/Compare 2 interrupt */
		2131	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2132
		2133	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2134	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2135
		2136	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2137	{
		2138	/* Enable the main output */
		2139	__HAL_TIM_MOE_ENABLE(htim);
		2140	}
		2141
		2142	/* Return function status */
		2143	return HAL_OK;
		2144	}
		2145
		2146	/**
		2147	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
		2148	* @param htim : TIM One Pulse handle
		2149	* @param OutputChannel : TIM Channels to be enabled
		2150	* This parameter can be one of the following values:
		2151	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2152	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2153	* @retval HAL status
		2154	*/
		2155	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2156	{
		2157	/* Disable the TIM Capture/Compare 1 interrupt */
		2158	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2159
		2160	/* Disable the TIM Capture/Compare 2 interrupt */
		2161	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2162
		2163	/* Disable the Capture compare and the Input Capture channels
		2164	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2165	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2166	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2167	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
		2168	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2169	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2170
		2171	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2172	{
		2173	/* Disable the Main Ouput */
		2174	__HAL_TIM_MOE_DISABLE(htim);
		2175	}
		2176
		2177	/* Disable the Peripheral */
		2178	__HAL_TIM_DISABLE(htim);
		2179
		2180	/* Return function status */
		2181	return HAL_OK;
		2182	}
		2183
		2184	/**
		2185	* @}
		2186	*/
		2187
		2188	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
		2189	* @brief Time Encoder functions
		2190	*
		2191	@verbatim
		2192	==============================================================================
		2193	##### Time Encoder functions #####
		2194	==============================================================================
		2195	[..]
		2196	This section provides functions allowing to:
		2197	(+) Initialize and configure the TIM Encoder.
		2198	(+) De-initialize the TIM Encoder.
		2199	(+) Start the Time Encoder.
		2200	(+) Stop the Time Encoder.
		2201	(+) Start the Time Encoder and enable interrupt.
		2202	(+) Stop the Time Encoder and disable interrupt.
		2203	(+) Start the Time Encoder and enable DMA transfer.
		2204	(+) Stop the Time Encoder and disable DMA transfer.
		2205
		2206	@endverbatim
		2207	* @{
		2208	*/
		2209	/**
		2210	* @brief Initializes the TIM Encoder Interface and create the associated handle.
		2211	* @param htim : TIM Encoder Interface handle
		2212	* @param sConfig : TIM Encoder Interface configuration structure
		2213	* @retval HAL status
		2214	*/
		2215	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
		2216	{
		2217	uint32_t tmpsmcr = 0;
		2218	uint32_t tmpccmr1 = 0;
		2219	uint32_t tmpccer = 0;
		2220
		2221	/* Check the TIM handle allocation */
		2222	if(htim == NULL)
		2223	{
		2224	return HAL_ERROR;
		2225	}
		2226
		2227	/* Check the parameters */
		2228	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2229	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
		2230	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
		2231	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
		2232	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
		2233	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
		2234	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
		2235	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
		2236	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
		2237	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
		2238
		2239	if(htim->State == HAL_TIM_STATE_RESET)
		2240	{
		2241	/* Allocate lock resource and initialize it */
		2242	htim->Lock = HAL_UNLOCKED;
		2243
		2244	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		2245	HAL_TIM_Encoder_MspInit(htim);
		2246	}
		2247
		2248	/* Set the TIM state */
		2249	htim->State= HAL_TIM_STATE_BUSY;
		2250
		2251	/* Reset the SMS bits */
		2252	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		2253
		2254	/* Configure the Time base in the Encoder Mode */
		2255	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		2256
		2257	/* Get the TIMx SMCR register value */
		2258	tmpsmcr = htim->Instance->SMCR;
		2259
		2260	/* Get the TIMx CCMR1 register value */
		2261	tmpccmr1 = htim->Instance->CCMR1;
		2262
		2263	/* Get the TIMx CCER register value */
		2264	tmpccer = htim->Instance->CCER;
		2265
		2266	/* Set the encoder Mode */
		2267	tmpsmcr \|= sConfig->EncoderMode;
		2268
		2269	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
		2270	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
		2271	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
		2272
		2273	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
		2274	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
		2275	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
		2276	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
		2277	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
		2278
		2279	/* Set the TI1 and the TI2 Polarities */
		2280	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
		2281	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
		2282	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
		2283
		2284	/* Write to TIMx SMCR */
		2285	htim->Instance->SMCR = tmpsmcr;
		2286
		2287	/* Write to TIMx CCMR1 */
		2288	htim->Instance->CCMR1 = tmpccmr1;
		2289
		2290	/* Write to TIMx CCER */
		2291	htim->Instance->CCER = tmpccer;
		2292
		2293	/* Initialize the TIM state*/
		2294	htim->State= HAL_TIM_STATE_READY;
		2295
		2296	return HAL_OK;
		2297	}
		2298
		2299
		2300	/**
		2301	* @brief DeInitializes the TIM Encoder interface
		2302	* @param htim : TIM Encoder handle
		2303	* @retval HAL status
		2304	*/
		2305	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
		2306	{
		2307	/* Check the parameters */
		2308	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2309
		2310	htim->State = HAL_TIM_STATE_BUSY;
		2311
		2312	/* Disable the TIM Peripheral Clock */
		2313	__HAL_TIM_DISABLE(htim);
		2314
		2315	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		2316	HAL_TIM_Encoder_MspDeInit(htim);
		2317
		2318	/* Change TIM state */
		2319	htim->State = HAL_TIM_STATE_RESET;
		2320
		2321	/* Release Lock */
		2322	__HAL_UNLOCK(htim);
		2323
		2324	return HAL_OK;
		2325	}
		2326
		2327	/**
		2328	* @brief Initializes the TIM Encoder Interface MSP.
		2329	* @param htim : TIM handle
		2330	* @retval None
		2331	*/
		2332	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
		2333	{
		2334	/* NOTE : This function Should not be modified, when the callback is needed,
		2335	the HAL_TIM_Encoder_MspInit could be implemented in the user file
		2336	*/
		2337	}
		2338
		2339	/**
		2340	* @brief DeInitializes TIM Encoder Interface MSP.
		2341	* @param htim : TIM handle
		2342	* @retval None
		2343	*/
		2344	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
		2345	{
		2346	/* NOTE : This function Should not be modified, when the callback is needed,
		2347	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
		2348	*/
		2349	}
		2350
		2351	/**
		2352	* @brief Starts the TIM Encoder Interface.
		2353	* @param htim : TIM Encoder Interface handle
		2354	* @param Channel : TIM Channels to be enabled
		2355	* This parameter can be one of the following values:
		2356	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2357	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2358	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2359	* @retval HAL status
		2360	*/
		2361	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		2362	{
		2363	/* Check the parameters */
		2364	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2365
		2366	/* Enable the encoder interface channels */
		2367	switch (Channel)
		2368	{
		2369	case TIM_CHANNEL_1:
		2370	{
		2371	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2372	break;
		2373	}
		2374	case TIM_CHANNEL_2:
		2375	{
		2376	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2377	break;
		2378	}
		2379	default :
		2380	{
		2381	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2382	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2383	break;
		2384	}
		2385	}
		2386	/* Enable the Peripheral */
		2387	__HAL_TIM_ENABLE(htim);
		2388
		2389	/* Return function status */
		2390	return HAL_OK;
		2391	}
		2392
		2393	/**
		2394	* @brief Stops the TIM Encoder Interface.
		2395	* @param htim : TIM Encoder Interface handle
		2396	* @param Channel : TIM Channels to be disabled
		2397	* This parameter can be one of the following values:
		2398	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2399	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2400	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2401	* @retval HAL status
		2402	*/
		2403	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		2404	{
		2405	/* Check the parameters */
		2406	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2407
		2408	/* Disable the Input Capture channels 1 and 2
		2409	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2410	switch (Channel)
		2411	{
		2412	case TIM_CHANNEL_1:
		2413	{
		2414	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2415	break;
		2416	}
		2417	case TIM_CHANNEL_2:
		2418	{
		2419	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2420	break;
		2421	}
		2422	default :
		2423	{
		2424	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2425	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2426	break;
		2427	}
		2428	}
		2429
		2430	/* Disable the Peripheral */
		2431	__HAL_TIM_DISABLE(htim);
		2432
		2433	/* Return function status */
		2434	return HAL_OK;
		2435	}
		2436
		2437	/**
		2438	* @brief Starts the TIM Encoder Interface in interrupt mode.
		2439	* @param htim : TIM Encoder Interface handle
		2440	* @param Channel : TIM Channels to be enabled
		2441	* This parameter can be one of the following values:
		2442	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2443	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2444	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2445	* @retval HAL status
		2446	*/
		2447	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		2448	{
		2449	/* Check the parameters */
		2450	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2451
		2452	/* Enable the encoder interface channels */
		2453	/* Enable the capture compare Interrupts 1 and/or 2 */
		2454	switch (Channel)
		2455	{
		2456	case TIM_CHANNEL_1:
		2457	{
		2458	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2459	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2460	break;
		2461	}
		2462	case TIM_CHANNEL_2:
		2463	{
		2464	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2465	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2466	break;
		2467	}
		2468	default :
		2469	{
		2470	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2471	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2472	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2473	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2474	break;
		2475	}
		2476	}
		2477
		2478	/* Enable the Peripheral */
		2479	__HAL_TIM_ENABLE(htim);
		2480
		2481	/* Return function status */
		2482	return HAL_OK;
		2483	}
		2484
		2485	/**
		2486	* @brief Stops the TIM Encoder Interface in interrupt mode.
		2487	* @param htim : TIM Encoder Interface handle
		2488	* @param Channel : TIM Channels to be disabled
		2489	* This parameter can be one of the following values:
		2490	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2491	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2492	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2493	* @retval HAL status
		2494	*/
		2495	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		2496	{
		2497	/* Check the parameters */
		2498	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2499
		2500	/* Disable the Input Capture channels 1 and 2
		2501	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2502	if(Channel == TIM_CHANNEL_1)
		2503	{
		2504	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2505
		2506	/* Disable the capture compare Interrupts 1 */
		2507	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2508	}
		2509	else if(Channel == TIM_CHANNEL_2)
		2510	{
		2511	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2512
		2513	/* Disable the capture compare Interrupts 2 */
		2514	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2515	}
		2516	else
		2517	{
		2518	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2519	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2520
		2521	/* Disable the capture compare Interrupts 1 and 2 */
		2522	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2523	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2524	}
		2525
		2526	/* Disable the Peripheral */
		2527	__HAL_TIM_DISABLE(htim);
		2528
		2529	/* Change the htim state */
		2530	htim->State = HAL_TIM_STATE_READY;
		2531
		2532	/* Return function status */
		2533	return HAL_OK;
		2534	}
		2535
		2536	/**
		2537	* @brief Starts the TIM Encoder Interface in DMA mode.
		2538	* @param htim : TIM Encoder Interface handle
		2539	* @param Channel : TIM Channels to be enabled
		2540	* This parameter can be one of the following values:
		2541	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2542	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2543	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2544	* @param pData1 : The destination Buffer address for IC1.
		2545	* @param pData2 : The destination Buffer address for IC2.
		2546	* @param Length : The length of data to be transferred from TIM peripheral to memory.
		2547	* @retval HAL status
		2548	*/
		2549	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
		2550	{
		2551	/* Check the parameters */
		2552	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2553
		2554	if((htim->State == HAL_TIM_STATE_BUSY))
		2555	{
		2556	return HAL_BUSY;
		2557	}
		2558	else if((htim->State == HAL_TIM_STATE_READY))
		2559	{
		2560	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
		2561	{
		2562	return HAL_ERROR;
		2563	}
		2564	else
		2565	{
		2566	htim->State = HAL_TIM_STATE_BUSY;
		2567	}
		2568	}
		2569
		2570	switch (Channel)
		2571	{
		2572	case TIM_CHANNEL_1:
		2573	{
		2574	/* Set the DMA Period elapsed callback */
		2575	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		2576
		2577	/* Set the DMA error callback */
		2578	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		2579
		2580	/* Enable the DMA channel */
		2581	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
		2582
		2583	/* Enable the TIM Input Capture DMA request */
		2584	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		2585
		2586	/* Enable the Peripheral */
		2587	__HAL_TIM_ENABLE(htim);
		2588
		2589	/* Enable the Capture compare channel */
		2590	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2591	}
		2592	break;
		2593
		2594	case TIM_CHANNEL_2:
		2595	{
		2596	/* Set the DMA Period elapsed callback */
		2597	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		2598
		2599	/* Set the DMA error callback */
		2600	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
		2601	/* Enable the DMA channel */
		2602	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
		2603
		2604	/* Enable the TIM Input Capture DMA request */
		2605	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		2606
		2607	/* Enable the Peripheral */
		2608	__HAL_TIM_ENABLE(htim);
		2609
		2610	/* Enable the Capture compare channel */
		2611	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2612	}
		2613	break;
		2614
		2615	case TIM_CHANNEL_ALL:
		2616	{
		2617	/* Set the DMA Period elapsed callback */
		2618	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		2619
		2620	/* Set the DMA error callback */
		2621	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		2622
		2623	/* Enable the DMA channel */
		2624	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
		2625
		2626	/* Set the DMA Period elapsed callback */
		2627	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		2628
		2629	/* Set the DMA error callback */
		2630	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		2631
		2632	/* Enable the DMA channel */
		2633	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
		2634
		2635	/* Enable the Peripheral */
		2636	__HAL_TIM_ENABLE(htim);
		2637
		2638	/* Enable the Capture compare channel */
		2639	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2640	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2641
		2642	/* Enable the TIM Input Capture DMA request */
		2643	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		2644	/* Enable the TIM Input Capture DMA request */
		2645	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		2646	}
		2647	break;
		2648
		2649	default:
		2650	break;
		2651	}
		2652	/* Return function status */
		2653	return HAL_OK;
		2654	}
		2655
		2656	/**
		2657	* @brief Stops the TIM Encoder Interface in DMA mode.
		2658	* @param htim : TIM Encoder Interface handle
		2659	* @param Channel : TIM Channels to be enabled
		2660	* This parameter can be one of the following values:
		2661	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2662	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2663	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2664	* @retval HAL status
		2665	*/
		2666	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		2667	{
		2668	/* Check the parameters */
		2669	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2670
		2671	/* Disable the Input Capture channels 1 and 2
		2672	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2673	if(Channel == TIM_CHANNEL_1)
		2674	{
		2675	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2676
		2677	/* Disable the capture compare DMA Request 1 */
		2678	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		2679	}
		2680	else if(Channel == TIM_CHANNEL_2)
		2681	{
		2682	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2683
		2684	/* Disable the capture compare DMA Request 2 */
		2685	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		2686	}
		2687	else
		2688	{
		2689	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2690	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2691
		2692	/* Disable the capture compare DMA Request 1 and 2 */
		2693	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		2694	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		2695	}
		2696
		2697	/* Disable the Peripheral */
		2698	__HAL_TIM_DISABLE(htim);
		2699
		2700	/* Change the htim state */
		2701	htim->State = HAL_TIM_STATE_READY;
		2702
		2703	/* Return function status */
		2704	return HAL_OK;
		2705	}
		2706
		2707	/**
		2708	* @}
		2709	*/
		2710	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		2711	* @brief IRQ handler management
		2712	*
		2713	@verbatim
		2714	==============================================================================
		2715	##### IRQ handler management #####
		2716	==============================================================================
		2717	[..]
		2718	This section provides Timer IRQ handler function.
		2719
		2720	@endverbatim
		2721	* @{
		2722	*/
		2723	/**
		2724	* @brief This function handles TIM interrupts requests.
		2725	* @param htim : TIM handle
		2726	* @retval None
		2727	*/
		2728	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
		2729	{
		2730	/* Capture compare 1 event */
		2731	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
		2732	{
		2733	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
		2734	{
		2735	{
		2736	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
		2737	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		2738
		2739	/* Input capture event */
		2740	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
		2741	{
		2742	HAL_TIM_IC_CaptureCallback(htim);
		2743	}
		2744	/* Output compare event */
		2745	else
		2746	{
		2747	HAL_TIM_OC_DelayElapsedCallback(htim);
		2748	HAL_TIM_PWM_PulseFinishedCallback(htim);
		2749	}
		2750	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		2751	}
		2752	}
		2753	}
		2754	/* Capture compare 2 event */
		2755	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
		2756	{
		2757	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
		2758	{
		2759	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
		2760	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		2761	/* Input capture event */
		2762	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
		2763	{
		2764	HAL_TIM_IC_CaptureCallback(htim);
		2765	}
		2766	/* Output compare event */
		2767	else
		2768	{
		2769	HAL_TIM_OC_DelayElapsedCallback(htim);
		2770	HAL_TIM_PWM_PulseFinishedCallback(htim);
		2771	}
		2772	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		2773	}
		2774	}
		2775	/* Capture compare 3 event */
		2776	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
		2777	{
		2778	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
		2779	{
		2780	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
		2781	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		2782	/* Input capture event */
		2783	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
		2784	{
		2785	HAL_TIM_IC_CaptureCallback(htim);
		2786	}
		2787	/* Output compare event */
		2788	else
		2789	{
		2790	HAL_TIM_OC_DelayElapsedCallback(htim);
		2791	HAL_TIM_PWM_PulseFinishedCallback(htim);
		2792	}
		2793	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		2794	}
		2795	}
		2796	/* Capture compare 4 event */
		2797	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
		2798	{
		2799	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
		2800	{
		2801	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
		2802	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		2803	/* Input capture event */
		2804	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
		2805	{
		2806	HAL_TIM_IC_CaptureCallback(htim);
		2807	}
		2808	/* Output compare event */
		2809	else
		2810	{
		2811	HAL_TIM_OC_DelayElapsedCallback(htim);
		2812	HAL_TIM_PWM_PulseFinishedCallback(htim);
		2813	}
		2814	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		2815	}
		2816	}
		2817	/* TIM Update event */
		2818	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
		2819	{
		2820	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
		2821	{
		2822	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
		2823	HAL_TIM_PeriodElapsedCallback(htim);
		2824	}
		2825	}
		2826	/* TIM Break input event */
		2827	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
		2828	{
		2829	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
		2830	{
		2831	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
		2832	HAL_TIMEx_BreakCallback(htim);
		2833	}
		2834	}
		2835	/* TIM Trigger detection event */
		2836	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
		2837	{
		2838	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
		2839	{
		2840	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
		2841	HAL_TIM_TriggerCallback(htim);
		2842	}
		2843	}
		2844	/* TIM commutation event */
		2845	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
		2846	{
		2847	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
		2848	{
		2849	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
		2850	HAL_TIMEx_CommutationCallback(htim);
		2851	}
		2852	}
		2853	}
		2854
		2855	/**
		2856	* @}
		2857	*/
		2858
		2859	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
		2860	* @brief Peripheral Control functions
		2861	*
		2862	@verbatim
		2863	==============================================================================
		2864	##### Peripheral Control functions #####
		2865	==============================================================================
		2866	[..]
		2867	This section provides functions allowing to:
		2868	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
		2869	(+) Configure External Clock source.
		2870	(+) Configure Complementary channels, break features and dead time.
		2871	(+) Configure Master and the Slave synchronization.
		2872	(+) Configure the DMA Burst Mode.
		2873
		2874	@endverbatim
		2875	* @{
		2876	*/
		2877
		2878	/**
		2879	* @brief Initializes the TIM Output Compare Channels according to the specified
		2880	* parameters in the TIM_OC_InitTypeDef.
		2881	* @param htim : TIM Output Compare handle
		2882	* @param sConfig : TIM Output Compare configuration structure
		2883	* @param Channel : TIM Channels to be enabled
		2884	* This parameter can be one of the following values:
		2885	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2886	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2887	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		2888	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		2889	* @retval HAL status
		2890	*/
		2891	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
		2892	{
		2893	/* Check the parameters */
		2894	assert_param(IS_TIM_CHANNELS(Channel));
		2895	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
		2896	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
		2897	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
		2898	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
		2899	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
		2900
		2901	/* Check input state */
		2902	__HAL_LOCK(htim);
		2903
		2904	htim->State = HAL_TIM_STATE_BUSY;
		2905
		2906	switch (Channel)
		2907	{
		2908	case TIM_CHANNEL_1:
		2909	{
		2910	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		2911	/* Configure the TIM Channel 1 in Output Compare */
		2912	TIM_OC1_SetConfig(htim->Instance, sConfig);
		2913	}
		2914	break;
		2915
		2916	case TIM_CHANNEL_2:
		2917	{
		2918	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2919	/* Configure the TIM Channel 2 in Output Compare */
		2920	TIM_OC2_SetConfig(htim->Instance, sConfig);
		2921	}
		2922	break;
		2923
		2924	case TIM_CHANNEL_3:
		2925	{
		2926	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		2927	/* Configure the TIM Channel 3 in Output Compare */
		2928	TIM_OC3_SetConfig(htim->Instance, sConfig);
		2929	}
		2930	break;
		2931
		2932	case TIM_CHANNEL_4:
		2933	{
		2934	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		2935	/* Configure the TIM Channel 4 in Output Compare */
		2936	TIM_OC4_SetConfig(htim->Instance, sConfig);
		2937	}
		2938	break;
		2939
		2940	default:
		2941	break;
		2942	}
		2943	htim->State = HAL_TIM_STATE_READY;
		2944
		2945	__HAL_UNLOCK(htim);
		2946
		2947	return HAL_OK;
		2948	}
		2949
		2950	/**
		2951	* @brief Initializes the TIM Input Capture Channels according to the specified
		2952	* parameters in the TIM_IC_InitTypeDef.
		2953	* @param htim : TIM IC handle
		2954	* @param sConfig : TIM Input Capture configuration structure
		2955	* @param Channel : TIM Channels to be enabled
		2956	* This parameter can be one of the following values:
		2957	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2958	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2959	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		2960	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		2961	* @retval HAL status
		2962	*/
		2963	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
		2964	{
		2965	/* Check the parameters */
		2966	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		2967	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
		2968	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
		2969	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
		2970	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
		2971
		2972	__HAL_LOCK(htim);
		2973
		2974	htim->State = HAL_TIM_STATE_BUSY;
		2975
		2976	if (Channel == TIM_CHANNEL_1)
		2977	{
		2978	/* TI1 Configuration */
		2979	TIM_TI1_SetConfig(htim->Instance,
		2980	sConfig->ICPolarity,
		2981	sConfig->ICSelection,
		2982	sConfig->ICFilter);
		2983
		2984	/* Reset the IC1PSC Bits */
		2985	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
		2986
		2987	/* Set the IC1PSC value */
		2988	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
		2989	}
		2990	else if (Channel == TIM_CHANNEL_2)
		2991	{
		2992	/* TI2 Configuration */
		2993	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2994
		2995	TIM_TI2_SetConfig(htim->Instance,
		2996	sConfig->ICPolarity,
		2997	sConfig->ICSelection,
		2998	sConfig->ICFilter);
		2999
		3000	/* Reset the IC2PSC Bits */
		3001	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
		3002
		3003	/* Set the IC2PSC value */
		3004	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
		3005	}
		3006	else if (Channel == TIM_CHANNEL_3)
		3007	{
		3008	/* TI3 Configuration */
		3009	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3010
		3011	TIM_TI3_SetConfig(htim->Instance,
		3012	sConfig->ICPolarity,
		3013	sConfig->ICSelection,
		3014	sConfig->ICFilter);
		3015
		3016	/* Reset the IC3PSC Bits */
		3017	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
		3018
		3019	/* Set the IC3PSC value */
		3020	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
		3021	}
		3022	else
		3023	{
		3024	/* TI4 Configuration */
		3025	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3026
		3027	TIM_TI4_SetConfig(htim->Instance,
		3028	sConfig->ICPolarity,
		3029	sConfig->ICSelection,
		3030	sConfig->ICFilter);
		3031
		3032	/* Reset the IC4PSC Bits */
		3033	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
		3034
		3035	/* Set the IC4PSC value */
		3036	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
		3037	}
		3038
		3039	htim->State = HAL_TIM_STATE_READY;
		3040
		3041	__HAL_UNLOCK(htim);
		3042
		3043	return HAL_OK;
		3044	}
		3045
		3046	/**
		3047	* @brief Initializes the TIM PWM channels according to the specified
		3048	* parameters in the TIM_OC_InitTypeDef.
		3049	* @param htim : TIM handle
		3050	* @param sConfig : TIM PWM configuration structure
		3051	* @param Channel : TIM Channels to be enabled
		3052	* This parameter can be one of the following values:
		3053	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3054	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3055	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3056	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3057	* @retval HAL status
		3058	*/
		3059	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
		3060	{
		3061	__HAL_LOCK(htim);
		3062
		3063	/* Check the parameters */
		3064	assert_param(IS_TIM_CHANNELS(Channel));
		3065	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
		3066	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
		3067	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
		3068	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
		3069	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
		3070	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
		3071
		3072	htim->State = HAL_TIM_STATE_BUSY;
		3073
		3074	switch (Channel)
		3075	{
		3076	case TIM_CHANNEL_1:
		3077	{
		3078	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3079	/* Configure the Channel 1 in PWM mode */
		3080	TIM_OC1_SetConfig(htim->Instance, sConfig);
		3081
		3082	/* Set the Preload enable bit for channel1 */
		3083	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
		3084
		3085	/* Configure the Output Fast mode */
		3086	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
		3087	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
		3088	}
		3089	break;
		3090
		3091	case TIM_CHANNEL_2:
		3092	{
		3093	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3094	/* Configure the Channel 2 in PWM mode */
		3095	TIM_OC2_SetConfig(htim->Instance, sConfig);
		3096
		3097	/* Set the Preload enable bit for channel2 */
		3098	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
		3099
		3100	/* Configure the Output Fast mode */
		3101	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
		3102	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
		3103	}
		3104	break;
		3105
		3106	case TIM_CHANNEL_3:
		3107	{
		3108	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3109	/* Configure the Channel 3 in PWM mode */
		3110	TIM_OC3_SetConfig(htim->Instance, sConfig);
		3111
		3112	/* Set the Preload enable bit for channel3 */
		3113	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
		3114
		3115	/* Configure the Output Fast mode */
		3116	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
		3117	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
		3118	}
		3119	break;
		3120
		3121	case TIM_CHANNEL_4:
		3122	{
		3123	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3124	/* Configure the Channel 4 in PWM mode */
		3125	TIM_OC4_SetConfig(htim->Instance, sConfig);
		3126
		3127	/* Set the Preload enable bit for channel4 */
		3128	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
		3129
		3130	/* Configure the Output Fast mode */
		3131	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
		3132	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
		3133	}
		3134	break;
		3135
		3136	default:
		3137	break;
		3138	}
		3139
		3140	htim->State = HAL_TIM_STATE_READY;
		3141
		3142	__HAL_UNLOCK(htim);
		3143
		3144	return HAL_OK;
		3145	}
		3146
		3147	/**
		3148	* @brief Initializes the TIM One Pulse Channels according to the specified
		3149	* parameters in the TIM_OnePulse_InitTypeDef.
		3150	* @param htim : TIM One Pulse handle
		3151	* @param sConfig : TIM One Pulse configuration structure
		3152	* @param OutputChannel : TIM Channels to be enabled
		3153	* This parameter can be one of the following values:
		3154	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3155	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3156	* @param InputChannel : TIM Channels to be enabled
		3157	* This parameter can be one of the following values:
		3158	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3159	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3160	* @retval HAL status
		3161	*/
		3162	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
		3163	{
		3164	TIM_OC_InitTypeDef temp1;
		3165
		3166	/* Check the parameters */
		3167	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
		3168	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
		3169
		3170	if(OutputChannel != InputChannel)
		3171	{
		3172	__HAL_LOCK(htim);
		3173
		3174	htim->State = HAL_TIM_STATE_BUSY;
		3175
		3176	/* Extract the Ouput compare configuration from sConfig structure */
		3177	temp1.OCMode = sConfig->OCMode;
		3178	temp1.Pulse = sConfig->Pulse;
		3179	temp1.OCPolarity = sConfig->OCPolarity;
		3180	temp1.OCNPolarity = sConfig->OCNPolarity;
		3181	temp1.OCIdleState = sConfig->OCIdleState;
		3182	temp1.OCNIdleState = sConfig->OCNIdleState;
		3183
		3184	switch (OutputChannel)
		3185	{
		3186	case TIM_CHANNEL_1:
		3187	{
		3188	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3189
		3190	TIM_OC1_SetConfig(htim->Instance, &temp1);
		3191	}
		3192	break;
		3193	case TIM_CHANNEL_2:
		3194	{
		3195	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3196
		3197	TIM_OC2_SetConfig(htim->Instance, &temp1);
		3198	}
		3199	break;
		3200	default:
		3201	break;
		3202	}
		3203	switch (InputChannel)
		3204	{
		3205	case TIM_CHANNEL_1:
		3206	{
		3207	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3208
		3209	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
		3210	sConfig->ICSelection, sConfig->ICFilter);
		3211
		3212	/* Reset the IC1PSC Bits */
		3213	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
		3214
		3215	/* Select the Trigger source */
		3216	htim->Instance->SMCR &= ~TIM_SMCR_TS;
		3217	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
		3218
		3219	/* Select the Slave Mode */
		3220	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3221	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
		3222	}
		3223	break;
		3224	case TIM_CHANNEL_2:
		3225	{
		3226	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3227
		3228	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
		3229	sConfig->ICSelection, sConfig->ICFilter);
		3230
		3231	/* Reset the IC2PSC Bits */
		3232	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
		3233
		3234	/* Select the Trigger source */
		3235	htim->Instance->SMCR &= ~TIM_SMCR_TS;
		3236	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
		3237
		3238	/* Select the Slave Mode */
		3239	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3240	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
		3241	}
		3242	break;
		3243
		3244	default:
		3245	break;
		3246	}
		3247
		3248	htim->State = HAL_TIM_STATE_READY;
		3249
		3250	__HAL_UNLOCK(htim);
		3251
		3252	return HAL_OK;
		3253	}
		3254	else
		3255	{
		3256	return HAL_ERROR;
		3257	}
		3258	}
		3259
		3260	/**
		3261	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
		3262	* @param htim : TIM handle
		3263	* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
		3264	* This parameter can be one of the following values:
		3265	* @arg TIM_DMABASE_CR1
		3266	* @arg TIM_DMABASE_CR2
		3267	* @arg TIM_DMABASE_SMCR
		3268	* @arg TIM_DMABASE_DIER
		3269	* @arg TIM_DMABASE_SR
		3270	* @arg TIM_DMABASE_EGR
		3271	* @arg TIM_DMABASE_CCMR1
		3272	* @arg TIM_DMABASE_CCMR2
		3273	* @arg TIM_DMABASE_CCER
		3274	* @arg TIM_DMABASE_CNT
		3275	* @arg TIM_DMABASE_PSC
		3276	* @arg TIM_DMABASE_ARR
		3277	* @arg TIM_DMABASE_RCR
		3278	* @arg TIM_DMABASE_CCR1
		3279	* @arg TIM_DMABASE_CCR2
		3280	* @arg TIM_DMABASE_CCR3
		3281	* @arg TIM_DMABASE_CCR4
		3282	* @arg TIM_DMABASE_BDTR
		3283	* @arg TIM_DMABASE_DCR
		3284	* @param BurstRequestSrc : TIM DMA Request sources
		3285	* This parameter can be one of the following values:
		3286	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		3287	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		3288	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		3289	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		3290	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		3291	* @arg TIM_DMA_COM: TIM Commutation DMA source
		3292	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		3293	* @param BurstBuffer : The Buffer address.
		3294	* @param BurstLength : DMA Burst length. This parameter can be one value
		3295	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		3296	* @retval HAL status
		3297	*/
		3298	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
		3299	uint32_t* BurstBuffer, uint32_t BurstLength)
		3300	{
		3301	/* Check the parameters */
		3302	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
		3303	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
		3304	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3305	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
		3306
		3307	if((htim->State == HAL_TIM_STATE_BUSY))
		3308	{
		3309	return HAL_BUSY;
		3310	}
		3311	else if((htim->State == HAL_TIM_STATE_READY))
		3312	{
		3313	if((BurstBuffer == 0 ) && (BurstLength > 0))
		3314	{
		3315	return HAL_ERROR;
		3316	}
		3317	else
		3318	{
		3319	htim->State = HAL_TIM_STATE_BUSY;
		3320	}
		3321	}
		3322	switch(BurstRequestSrc)
		3323	{
		3324	case TIM_DMA_UPDATE:
		3325	{
		3326	/* Set the DMA Period elapsed callback */
		3327	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		3328
		3329	/* Set the DMA error callback */
		3330	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		3331
		3332	/* Enable the DMA channel */
		3333	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3334	}
		3335	break;
		3336	case TIM_DMA_CC1:
		3337	{
		3338	/* Set the DMA Period elapsed callback */
		3339	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3340
		3341	/* Set the DMA error callback */
		3342	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3343
		3344	/* Enable the DMA channel */
		3345	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3346	}
		3347	break;
		3348	case TIM_DMA_CC2:
		3349	{
		3350	/* Set the DMA Period elapsed callback */
		3351	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3352
		3353	/* Set the DMA error callback */
		3354	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		3355
		3356	/* Enable the DMA channel */
		3357	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3358	}
		3359	break;
		3360	case TIM_DMA_CC3:
		3361	{
		3362	/* Set the DMA Period elapsed callback */
		3363	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3364
		3365	/* Set the DMA error callback */
		3366	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		3367
		3368	/* Enable the DMA channel */
		3369	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3370	}
		3371	break;
		3372	case TIM_DMA_CC4:
		3373	{
		3374	/* Set the DMA Period elapsed callback */
		3375	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3376
		3377	/* Set the DMA error callback */
		3378	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		3379
		3380	/* Enable the DMA channel */
		3381	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3382	}
		3383	break;
		3384	case TIM_DMA_COM:
		3385	{
		3386	/* Set the DMA Period elapsed callback */
		3387	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
		3388
		3389	/* Set the DMA error callback */
		3390	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
		3391
		3392	/* Enable the DMA channel */
		3393	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3394	}
		3395	break;
		3396	case TIM_DMA_TRIGGER:
		3397	{
		3398	/* Set the DMA Period elapsed callback */
		3399	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
		3400
		3401	/* Set the DMA error callback */
		3402	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
		3403
		3404	/* Enable the DMA channel */
		3405	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
		3406	}
		3407	break;
		3408	default:
		3409	break;
		3410	}
		3411	/* configure the DMA Burst Mode */
		3412	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
		3413
		3414	/* Enable the TIM DMA Request */
		3415	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
		3416
		3417	htim->State = HAL_TIM_STATE_READY;
		3418
		3419	/* Return function status */
		3420	return HAL_OK;
		3421	}
		3422
		3423	/**
		3424	* @brief Stops the TIM DMA Burst mode
		3425	* @param htim : TIM handle
		3426	* @param BurstRequestSrc : TIM DMA Request sources to disable
		3427	* @retval HAL status
		3428	*/
		3429	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
		3430	{
		3431	/* Check the parameters */
		3432	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3433
		3434	/* Abort the DMA transfer (at least disable the DMA channel) */
		3435	switch(BurstRequestSrc)
		3436	{
		3437	case TIM_DMA_UPDATE:
		3438	{
		3439	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
		3440	}
		3441	break;
		3442	case TIM_DMA_CC1:
		3443	{
		3444	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
		3445	}
		3446	break;
		3447	case TIM_DMA_CC2:
		3448	{
		3449	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
		3450	}
		3451	break;
		3452	case TIM_DMA_CC3:
		3453	{
		3454	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
		3455	}
		3456	break;
		3457	case TIM_DMA_CC4:
		3458	{
		3459	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
		3460	}
		3461	break;
		3462	case TIM_DMA_COM:
		3463	{
		3464	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
		3465	}
		3466	break;
		3467	case TIM_DMA_TRIGGER:
		3468	{
		3469	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
		3470	}
		3471	break;
		3472	default:
		3473	break;
		3474	}
		3475
		3476	/* Disable the TIM Update DMA request */
		3477	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
		3478
		3479	/* Return function status */
		3480	return HAL_OK;
		3481	}
		3482
		3483	/**
		3484	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
		3485	* @param htim : TIM handle
		3486	* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
		3487	* This parameter can be one of the following values:
		3488	* @arg TIM_DMABASE_CR1
		3489	* @arg TIM_DMABASE_CR2
		3490	* @arg TIM_DMABASE_SMCR
		3491	* @arg TIM_DMABASE_DIER
		3492	* @arg TIM_DMABASE_SR
		3493	* @arg TIM_DMABASE_EGR
		3494	* @arg TIM_DMABASE_CCMR1
		3495	* @arg TIM_DMABASE_CCMR2
		3496	* @arg TIM_DMABASE_CCER
		3497	* @arg TIM_DMABASE_CNT
		3498	* @arg TIM_DMABASE_PSC
		3499	* @arg TIM_DMABASE_ARR
		3500	* @arg TIM_DMABASE_RCR
		3501	* @arg TIM_DMABASE_CCR1
		3502	* @arg TIM_DMABASE_CCR2
		3503	* @arg TIM_DMABASE_CCR3
		3504	* @arg TIM_DMABASE_CCR4
		3505	* @arg TIM_DMABASE_BDTR
		3506	* @arg TIM_DMABASE_DCR
		3507	* @param BurstRequestSrc : TIM DMA Request sources
		3508	* This parameter can be one of the following values:
		3509	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		3510	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		3511	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		3512	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		3513	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		3514	* @arg TIM_DMA_COM: TIM Commutation DMA source
		3515	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		3516	* @param BurstBuffer : The Buffer address.
		3517	* @param BurstLength : DMA Burst length. This parameter can be one value
		3518	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		3519	* @retval HAL status
		3520	*/
		3521	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
		3522	uint32_t *BurstBuffer, uint32_t BurstLength)
		3523	{
		3524	/* Check the parameters */
		3525	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
		3526	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
		3527	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3528	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
		3529
		3530	if((htim->State == HAL_TIM_STATE_BUSY))
		3531	{
		3532	return HAL_BUSY;
		3533	}
		3534	else if((htim->State == HAL_TIM_STATE_READY))
		3535	{
		3536	if((BurstBuffer == 0 ) && (BurstLength > 0))
		3537	{
		3538	return HAL_ERROR;
		3539	}
		3540	else
		3541	{
		3542	htim->State = HAL_TIM_STATE_BUSY;
		3543	}
		3544	}
		3545	switch(BurstRequestSrc)
		3546	{
		3547	case TIM_DMA_UPDATE:
		3548	{
		3549	/* Set the DMA Period elapsed callback */
		3550	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		3551
		3552	/* Set the DMA error callback */
		3553	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		3554
		3555	/* Enable the DMA channel */
		3556	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3557	}
		3558	break;
		3559	case TIM_DMA_CC1:
		3560	{
		3561	/* Set the DMA Period elapsed callback */
		3562	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		3563
		3564	/* Set the DMA error callback */
		3565	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3566
		3567	/* Enable the DMA channel */
		3568	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3569	}
		3570	break;
		3571	case TIM_DMA_CC2:
		3572	{
		3573	/* Set the DMA Period elapsed callback */
		3574	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		3575
		3576	/* Set the DMA error callback */
		3577	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		3578
		3579	/* Enable the DMA channel */
		3580	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3581	}
		3582	break;
		3583	case TIM_DMA_CC3:
		3584	{
		3585	/* Set the DMA Period elapsed callback */
		3586	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
		3587
		3588	/* Set the DMA error callback */
		3589	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		3590
		3591	/* Enable the DMA channel */
		3592	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3593	}
		3594	break;
		3595	case TIM_DMA_CC4:
		3596	{
		3597	/* Set the DMA Period elapsed callback */
		3598	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
		3599
		3600	/* Set the DMA error callback */
		3601	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		3602
		3603	/* Enable the DMA channel */
		3604	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3605	}
		3606	break;
		3607	case TIM_DMA_COM:
		3608	{
		3609	/* Set the DMA Period elapsed callback */
		3610	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
		3611
		3612	/* Set the DMA error callback */
		3613	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
		3614
		3615	/* Enable the DMA channel */
		3616	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3617	}
		3618	break;
		3619	case TIM_DMA_TRIGGER:
		3620	{
		3621	/* Set the DMA Period elapsed callback */
		3622	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
		3623
		3624	/* Set the DMA error callback */
		3625	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
		3626
		3627	/* Enable the DMA channel */
		3628	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
		3629	}
		3630	break;
		3631	default:
		3632	break;
		3633	}
		3634
		3635	/* configure the DMA Burst Mode */
		3636	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
		3637
		3638	/* Enable the TIM DMA Request */
		3639	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
		3640
		3641	htim->State = HAL_TIM_STATE_READY;
		3642
		3643	/* Return function status */
		3644	return HAL_OK;
		3645	}
		3646
		3647	/**
		3648	* @brief Stop the DMA burst reading
		3649	* @param htim : TIM handle
		3650	* @param BurstRequestSrc : TIM DMA Request sources to disable.
		3651	* @retval HAL status
		3652	*/
		3653	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
		3654	{
		3655	/* Check the parameters */
		3656	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3657
		3658	/* Abort the DMA transfer (at least disable the DMA channel) */
		3659	switch(BurstRequestSrc)
		3660	{
		3661	case TIM_DMA_UPDATE:
		3662	{
		3663	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
		3664	}
		3665	break;
		3666	case TIM_DMA_CC1:
		3667	{
		3668	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
		3669	}
		3670	break;
		3671	case TIM_DMA_CC2:
		3672	{
		3673	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
		3674	}
		3675	break;
		3676	case TIM_DMA_CC3:
		3677	{
		3678	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
		3679	}
		3680	break;
		3681	case TIM_DMA_CC4:
		3682	{
		3683	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
		3684	}
		3685	break;
		3686	case TIM_DMA_COM:
		3687	{
		3688	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
		3689	}
		3690	break;
		3691	case TIM_DMA_TRIGGER:
		3692	{
		3693	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
		3694	}
		3695	break;
		3696	default:
		3697	break;
		3698	}
		3699
		3700	/* Disable the TIM Update DMA request */
		3701	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
		3702
		3703	/* Return function status */
		3704	return HAL_OK;
		3705	}
		3706
		3707	/**
		3708	* @brief Generate a software event
		3709	* @param htim : TIM handle
		3710	* @param EventSource : specifies the event source.
		3711	* This parameter can be one of the following values:
		3712	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
		3713	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
		3714	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
		3715	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
		3716	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
		3717	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
		3718	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
		3719	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
		3720	* @note TIM6 and TIM7 can only generate an update event.
		3721	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
		3722	* @retval HAL status
		3723	*/
		3724
		3725	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
		3726	{
		3727	/* Check the parameters */
		3728	assert_param(IS_TIM_INSTANCE(htim->Instance));
		3729	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
		3730
		3731	/* Process Locked */
		3732	__HAL_LOCK(htim);
		3733
		3734	/* Change the TIM state */
		3735	htim->State = HAL_TIM_STATE_BUSY;
		3736
		3737	/* Set the event sources */
		3738	htim->Instance->EGR = EventSource;
		3739
		3740	/* Change the TIM state */
		3741	htim->State = HAL_TIM_STATE_READY;
		3742
		3743	__HAL_UNLOCK(htim);
		3744
		3745	/* Return function status */
		3746	return HAL_OK;
		3747	}
		3748
		3749	/**
		3750	* @brief Configures the OCRef clear feature
		3751	* @param htim : TIM handle
		3752	* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
		3753	* contains the OCREF clear feature and parameters for the TIM peripheral.
		3754	* @param Channel : specifies the TIM Channel
		3755	* This parameter can be one of the following values:
		3756	* @arg TIM_CHANNEL_1: TIM Channel 1
		3757	* @arg TIM_CHANNEL_2: TIM Channel 2
		3758	* @arg TIM_CHANNEL_3: TIM Channel 3
		3759	* @arg TIM_CHANNEL_4: TIM Channel 4
		3760	* @retval HAL status
		3761	*/
		3762	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
		3763	{
		3764	uint32_t tmpsmcr = 0;
		3765
		3766	/* Check the parameters */
		3767	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
		3768	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
		3769	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
		3770	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
		3771	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
		3772
		3773	/* Process Locked */
		3774	__HAL_LOCK(htim);
		3775
		3776	htim->State = HAL_TIM_STATE_BUSY;
		3777
		3778	switch (sClearInputConfig->ClearInputSource)
		3779	{
		3780	case TIM_CLEARINPUTSOURCE_NONE:
		3781	{
		3782	/* Clear the OCREF clear selection bit */
		3783	tmpsmcr &= ~TIM_SMCR_OCCS;
		3784
		3785	/* Clear the ETR Bits */
		3786	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		3787
		3788	/* Set TIMx_SMCR */
		3789	htim->Instance->SMCR = tmpsmcr;
		3790	}
		3791	break;
		3792
		3793	case TIM_CLEARINPUTSOURCE_ETR:
		3794	{
		3795	TIM_ETR_SetConfig(htim->Instance,
		3796	sClearInputConfig->ClearInputPrescaler,
		3797	sClearInputConfig->ClearInputPolarity,
		3798	sClearInputConfig->ClearInputFilter);
		3799
		3800	/* Set the OCREF clear selection bit */
		3801	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
		3802	}
		3803	break;
		3804	default:
		3805	break;
		3806	}
		3807
		3808	switch (Channel)
		3809	{
		3810	case TIM_CHANNEL_1:
		3811	{
		3812	if(sClearInputConfig->ClearInputState != RESET)
		3813	{
		3814	/* Enable the Ocref clear feature for Channel 1 */
		3815	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
		3816	}
		3817	else
		3818	{
		3819	/* Disable the Ocref clear feature for Channel 1 */
		3820	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
		3821	}
		3822	}
		3823	break;
		3824	case TIM_CHANNEL_2:
		3825	{
		3826	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3827	if(sClearInputConfig->ClearInputState != RESET)
		3828	{
		3829	/* Enable the Ocref clear feature for Channel 2 */
		3830	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
		3831	}
		3832	else
		3833	{
		3834	/* Disable the Ocref clear feature for Channel 2 */
		3835	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
		3836	}
		3837	}
		3838	break;
		3839	case TIM_CHANNEL_3:
		3840	{
		3841	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3842	if(sClearInputConfig->ClearInputState != RESET)
		3843	{
		3844	/* Enable the Ocref clear feature for Channel 3 */
		3845	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
		3846	}
		3847	else
		3848	{
		3849	/* Disable the Ocref clear feature for Channel 3 */
		3850	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
		3851	}
		3852	}
		3853	break;
		3854	case TIM_CHANNEL_4:
		3855	{
		3856	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3857	if(sClearInputConfig->ClearInputState != RESET)
		3858	{
		3859	/* Enable the Ocref clear feature for Channel 4 */
		3860	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
		3861	}
		3862	else
		3863	{
		3864	/* Disable the Ocref clear feature for Channel 4 */
		3865	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
		3866	}
		3867	}
		3868	break;
		3869	default:
		3870	break;
		3871	}
		3872
		3873	htim->State = HAL_TIM_STATE_READY;
		3874
		3875	__HAL_UNLOCK(htim);
		3876
		3877	return HAL_OK;
		3878	}
		3879
		3880	/**
		3881	* @brief Configures the clock source to be used
		3882	* @param htim : TIM handle
		3883	* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
		3884	* contains the clock source information for the TIM peripheral.
		3885	* @retval HAL status
		3886	*/
		3887	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
		3888	{
		3889	uint32_t tmpsmcr = 0;
		3890
		3891	/* Process Locked */
		3892	__HAL_LOCK(htim);
		3893
		3894	htim->State = HAL_TIM_STATE_BUSY;
		3895
		3896	/* Check the parameters */
		3897	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
		3898	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		3899	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
		3900	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		3901
		3902	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
		3903	tmpsmcr = htim->Instance->SMCR;
		3904	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
		3905	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		3906	htim->Instance->SMCR = tmpsmcr;
		3907
		3908	switch (sClockSourceConfig->ClockSource)
		3909	{
		3910	case TIM_CLOCKSOURCE_INTERNAL:
		3911	{
		3912	assert_param(IS_TIM_INSTANCE(htim->Instance));
		3913	/* Disable slave mode to clock the prescaler directly with the internal clock */
		3914	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3915	}
		3916	break;
		3917
		3918	case TIM_CLOCKSOURCE_ETRMODE1:
		3919	{
		3920	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
		3921	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
		3922
		3923	/* Configure the ETR Clock source */
		3924	TIM_ETR_SetConfig(htim->Instance,
		3925	sClockSourceConfig->ClockPrescaler,
		3926	sClockSourceConfig->ClockPolarity,
		3927	sClockSourceConfig->ClockFilter);
		3928	/* Get the TIMx SMCR register value */
		3929	tmpsmcr = htim->Instance->SMCR;
		3930	/* Reset the SMS and TS Bits */
		3931	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
		3932	/* Select the External clock mode1 and the ETRF trigger */
		3933	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
		3934	/* Write to TIMx SMCR */
		3935	htim->Instance->SMCR = tmpsmcr;
		3936	}
		3937	break;
		3938
		3939	case TIM_CLOCKSOURCE_ETRMODE2:
		3940	{
		3941	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
		3942	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
		3943
		3944	/* Configure the ETR Clock source */
		3945	TIM_ETR_SetConfig(htim->Instance,
		3946	sClockSourceConfig->ClockPrescaler,
		3947	sClockSourceConfig->ClockPolarity,
		3948	sClockSourceConfig->ClockFilter);
		3949	/* Enable the External clock mode2 */
		3950	htim->Instance->SMCR \|= TIM_SMCR_ECE;
		3951	}
		3952	break;
		3953
		3954	case TIM_CLOCKSOURCE_TI1:
		3955	{
		3956	/* Check whether or not the timer instance supports external clock mode 1 */
		3957	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		3958
		3959	TIM_TI1_ConfigInputStage(htim->Instance,
		3960	sClockSourceConfig->ClockPolarity,
		3961	sClockSourceConfig->ClockFilter);
		3962	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
		3963	}
		3964	break;
		3965	case TIM_CLOCKSOURCE_TI2:
		3966	{
		3967	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
		3968	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		3969
		3970	TIM_TI2_ConfigInputStage(htim->Instance,
		3971	sClockSourceConfig->ClockPolarity,
		3972	sClockSourceConfig->ClockFilter);
		3973	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
		3974	}
		3975	break;
		3976	case TIM_CLOCKSOURCE_TI1ED:
		3977	{
		3978	/* Check whether or not the timer instance supports external clock mode 1 */
		3979	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		3980
		3981	TIM_TI1_ConfigInputStage(htim->Instance,
		3982	sClockSourceConfig->ClockPolarity,
		3983	sClockSourceConfig->ClockFilter);
		3984	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
		3985	}
		3986	break;
		3987	case TIM_CLOCKSOURCE_ITR0:
		3988	{
		3989	/* Check whether or not the timer instance supports external clock mode 1 */
		3990	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
		3991
		3992	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
		3993	}
		3994	break;
		3995	case TIM_CLOCKSOURCE_ITR1:
		3996	{
		3997	/* Check whether or not the timer instance supports external clock mode 1 */
		3998	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
		3999
		4000	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
		4001	}
		4002	break;
		4003	case TIM_CLOCKSOURCE_ITR2:
		4004	{
		4005	/* Check whether or not the timer instance supports external clock mode 1 */
		4006	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
		4007
		4008	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
		4009	}
		4010	break;
		4011	case TIM_CLOCKSOURCE_ITR3:
		4012	{
		4013	/* Check whether or not the timer instance supports external clock mode 1 */
		4014	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
		4015
		4016	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
		4017	}
		4018	break;
		4019
		4020	default:
		4021	break;
		4022	}
		4023	htim->State = HAL_TIM_STATE_READY;
		4024
		4025	__HAL_UNLOCK(htim);
		4026
		4027	return HAL_OK;
		4028	}
		4029
		4030	/**
		4031	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
		4032	* or a XOR combination between CH1_input, CH2_input & CH3_input
		4033	* @param htim : TIM handle.
		4034	* @param TI1_Selection : Indicate whether or not channel 1 is connected to the
		4035	* output of a XOR gate.
		4036	* This parameter can be one of the following values:
		4037	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
		4038	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
		4039	* pins are connected to the TI1 input (XOR combination)
		4040	* @retval HAL status
		4041	*/
		4042	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
		4043	{
		4044	uint32_t tmpcr2 = 0;
		4045
		4046	/* Check the parameters */
		4047	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
		4048	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
		4049
		4050	/* Get the TIMx CR2 register value */
		4051	tmpcr2 = htim->Instance->CR2;
		4052
		4053	/* Reset the TI1 selection */
		4054	tmpcr2 &= ~TIM_CR2_TI1S;
		4055
		4056	/* Set the the TI1 selection */
		4057	tmpcr2 \|= TI1_Selection;
		4058
		4059	/* Write to TIMxCR2 */
		4060	htim->Instance->CR2 = tmpcr2;
		4061
		4062	return HAL_OK;
		4063	}
		4064
		4065	/**
		4066	* @brief Configures the TIM in Slave mode
		4067	* @param htim : TIM handle.
		4068	* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
		4069	* contains the selected trigger (internal trigger input, filtered
		4070	* timer input or external trigger input) and the ) and the Slave
		4071	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
		4072	* @retval HAL status
		4073	*/
		4074	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
		4075	{
		4076	/* Check the parameters */
		4077	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
		4078	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
		4079	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
		4080
		4081	__HAL_LOCK(htim);
		4082
		4083	htim->State = HAL_TIM_STATE_BUSY;
		4084
		4085	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
		4086
		4087	/* Disable Trigger Interrupt */
		4088	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
		4089
		4090	/* Disable Trigger DMA request */
		4091	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
		4092
		4093	htim->State = HAL_TIM_STATE_READY;
		4094
		4095	__HAL_UNLOCK(htim);
		4096
		4097	return HAL_OK;
		4098	}
		4099
		4100	/**
		4101	* @brief Configures the TIM in Slave mode in interrupt mode
		4102	* @param htim: TIM handle.
		4103	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
		4104	* contains the selected trigger (internal trigger input, filtered
		4105	* timer input or external trigger input) and the ) and the Slave
		4106	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
		4107	* @retval HAL status
		4108	*/
		4109	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
		4110	TIM_SlaveConfigTypeDef * sSlaveConfig)
		4111	{
		4112	/* Check the parameters */
		4113	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
		4114	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
		4115	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
		4116
		4117	__HAL_LOCK(htim);
		4118
		4119	htim->State = HAL_TIM_STATE_BUSY;
		4120
		4121	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
		4122
		4123	/* Enable Trigger Interrupt */
		4124	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
		4125
		4126	/* Disable Trigger DMA request */
		4127	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
		4128
		4129	htim->State = HAL_TIM_STATE_READY;
		4130
		4131	__HAL_UNLOCK(htim);
		4132
		4133	return HAL_OK;
		4134	}
		4135
		4136	/**
		4137	* @brief Read the captured value from Capture Compare unit
		4138	* @param htim : TIM handle.
		4139	* @param Channel : TIM Channels to be enabled
		4140	* This parameter can be one of the following values:
		4141	* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
		4142	* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
		4143	* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
		4144	* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
		4145	* @retval Captured value
		4146	*/
		4147	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
		4148	{
		4149	uint32_t tmpreg = 0;
		4150
		4151	__HAL_LOCK(htim);
		4152
		4153	switch (Channel)
		4154	{
		4155	case TIM_CHANNEL_1:
		4156	{
		4157	/* Check the parameters */
		4158	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		4159
		4160	/* Return the capture 1 value */
		4161	tmpreg = htim->Instance->CCR1;
		4162
		4163	break;
		4164	}
		4165	case TIM_CHANNEL_2:
		4166	{
		4167	/* Check the parameters */
		4168	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4169
		4170	/* Return the capture 2 value */
		4171	tmpreg = htim->Instance->CCR2;
		4172
		4173	break;
		4174	}
		4175
		4176	case TIM_CHANNEL_3:
		4177	{
		4178	/* Check the parameters */
		4179	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		4180
		4181	/* Return the capture 3 value */
		4182	tmpreg = htim->Instance->CCR3;
		4183
		4184	break;
		4185	}
		4186
		4187	case TIM_CHANNEL_4:
		4188	{
		4189	/* Check the parameters */
		4190	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		4191
		4192	/* Return the capture 4 value */
		4193	tmpreg = htim->Instance->CCR4;
		4194
		4195	break;
		4196	}
		4197
		4198	default:
		4199	break;
		4200	}
		4201
		4202	__HAL_UNLOCK(htim);
		4203	return tmpreg;
		4204	}
		4205
		4206	/**
		4207	* @}
		4208	*/
		4209
		4210	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		4211	* @brief TIM Callbacks functions
		4212	*
		4213	@verbatim
		4214	==============================================================================
		4215	##### TIM Callbacks functions #####
		4216	==============================================================================
		4217	[..]
		4218	This section provides TIM callback functions:
		4219	(+) Timer Period elapsed callback
		4220	(+) Timer Output Compare callback
		4221	(+) Timer Input capture callback
		4222	(+) Timer Trigger callback
		4223	(+) Timer Error callback
		4224
		4225	@endverbatim
		4226	* @{
		4227	*/
		4228
		4229	/**
		4230	* @brief Period elapsed callback in non blocking mode
		4231	* @param htim : TIM handle
		4232	* @retval None
		4233	*/
		4234	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
		4235	{
		4236	/* NOTE : This function Should not be modified, when the callback is needed,
		4237	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
		4238	*/
		4239
		4240	}
		4241	/**
		4242	* @brief Output Compare callback in non blocking mode
		4243	* @param htim : TIM OC handle
		4244	* @retval None
		4245	*/
		4246	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
		4247	{
		4248	/* NOTE : This function Should not be modified, when the callback is needed,
		4249	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
		4250	*/
		4251	}
		4252	/**
		4253	* @brief Input Capture callback in non blocking mode
		4254	* @param htim : TIM IC handle
		4255	* @retval None
		4256	*/
		4257	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
		4258	{
		4259	/* NOTE : This function Should not be modified, when the callback is needed,
		4260	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
		4261	*/
		4262	}
		4263
		4264	/**
		4265	* @brief PWM Pulse finished callback in non blocking mode
		4266	* @param htim : TIM handle
		4267	* @retval None
		4268	*/
		4269	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
		4270	{
		4271	/* NOTE : This function Should not be modified, when the callback is needed,
		4272	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
		4273	*/
		4274	}
		4275
		4276	/**
		4277	* @brief Hall Trigger detection callback in non blocking mode
		4278	* @param htim : TIM handle
		4279	* @retval None
		4280	*/
		4281	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
		4282	{
		4283	/* NOTE : This function Should not be modified, when the callback is needed,
		4284	the HAL_TIM_TriggerCallback could be implemented in the user file
		4285	*/
		4286	}
		4287
		4288	/**
		4289	* @brief Timer error callback in non blocking mode
		4290	* @param htim : TIM handle
		4291	* @retval None
		4292	*/
		4293	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
		4294	{
		4295	/* NOTE : This function Should not be modified, when the callback is needed,
		4296	the HAL_TIM_ErrorCallback could be implemented in the user file
		4297	*/
		4298	}
		4299
		4300	/**
		4301	* @}
		4302	*/
		4303
		4304	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
		4305	* @brief Peripheral State functions
		4306	*
		4307	@verbatim
		4308	==============================================================================
		4309	##### Peripheral State functions #####
		4310	==============================================================================
		4311	[..]
		4312	This subsection permit to get in run-time the status of the peripheral
		4313	and the data flow.
		4314
		4315	@endverbatim
		4316	* @{
		4317	*/
		4318
		4319	/**
		4320	* @brief Return the TIM Base state
		4321	* @param htim : TIM Base handle
		4322	* @retval HAL state
		4323	*/
		4324	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
		4325	{
		4326	return htim->State;
		4327	}
		4328
		4329	/**
		4330	* @brief Return the TIM OC state
		4331	* @param htim : TIM Ouput Compare handle
		4332	* @retval HAL state
		4333	*/
		4334	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
		4335	{
		4336	return htim->State;
		4337	}
		4338
		4339	/**
		4340	* @brief Return the TIM PWM state
		4341	* @param htim : TIM handle
		4342	* @retval HAL state
		4343	*/
		4344	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
		4345	{
		4346	return htim->State;
		4347	}
		4348
		4349	/**
		4350	* @brief Return the TIM Input Capture state
		4351	* @param htim : TIM IC handle
		4352	* @retval HAL state
		4353	*/
		4354	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
		4355	{
		4356	return htim->State;
		4357	}
		4358
		4359	/**
		4360	* @brief Return the TIM One Pulse Mode state
		4361	* @param htim : TIM OPM handle
		4362	* @retval HAL state
		4363	*/
		4364	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
		4365	{
		4366	return htim->State;
		4367	}
		4368
		4369	/**
		4370	* @brief Return the TIM Encoder Mode state
		4371	* @param htim : TIM Encoder handle
		4372	* @retval HAL state
		4373	*/
		4374	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
		4375	{
		4376	return htim->State;
		4377	}
		4378
		4379	/**
		4380	* @}
		4381	*/
		4382
		4383	/**
		4384	* @}
		4385	*/
		4386
		4387	/** @addtogroup TIM_Private_Functions
		4388	* @{
		4389	*/
		4390
		4391	/**
		4392	* @brief TIM DMA error callback
		4393	* @param hdma : pointer to DMA handle.
		4394	* @retval None
		4395	*/
		4396	void TIM_DMAError(DMA_HandleTypeDef *hdma)
		4397	{
		4398	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		4399
		4400	htim->State= HAL_TIM_STATE_READY;
		4401
		4402	HAL_TIM_ErrorCallback(htim);
		4403	}
		4404
		4405	/**
		4406	* @brief TIM DMA Delay Pulse complete callback.
		4407	* @param hdma : pointer to DMA handle.
		4408	* @retval None
		4409	*/
		4410	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
		4411	{
		4412	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		4413
		4414	htim->State= HAL_TIM_STATE_READY;
		4415
		4416	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		4417	{
		4418	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		4419	}
		4420	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		4421	{
		4422	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		4423	}
		4424	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		4425	{
		4426	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		4427	}
		4428	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		4429	{
		4430	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		4431	}
		4432
		4433	HAL_TIM_PWM_PulseFinishedCallback(htim);
		4434
		4435	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		4436	}
		4437	/**
		4438	* @brief TIM DMA Capture complete callback.
		4439	* @param hdma : pointer to DMA handle.
		4440	* @retval None
		4441	*/
		4442	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
		4443	{
		4444	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		4445
		4446	htim->State= HAL_TIM_STATE_READY;
		4447
		4448	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		4449	{
		4450	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		4451	}
		4452	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		4453	{
		4454	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		4455	}
		4456	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		4457	{
		4458	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		4459	}
		4460	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		4461	{
		4462	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		4463	}
		4464
		4465	HAL_TIM_IC_CaptureCallback(htim);
		4466
		4467	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		4468	}
		4469
		4470	/**
		4471	* @brief TIM DMA Period Elapse complete callback.
		4472	* @param hdma : pointer to DMA handle.
		4473	* @retval None
		4474	*/
		4475	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
		4476	{
		4477	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		4478
		4479	htim->State= HAL_TIM_STATE_READY;
		4480
		4481	HAL_TIM_PeriodElapsedCallback(htim);
		4482	}
		4483
		4484	/**
		4485	* @brief TIM DMA Trigger callback.
		4486	* @param hdma : pointer to DMA handle.
		4487	* @retval None
		4488	*/
		4489	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
		4490	{
		4491	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		4492
		4493	htim->State= HAL_TIM_STATE_READY;
		4494
		4495	HAL_TIM_TriggerCallback(htim);
		4496	}
		4497
		4498	/**
		4499	* @brief Time Base configuration
		4500	* @param TIMx : TIM periheral
		4501	* @param Structure : TIM Base configuration structure
		4502	* @retval None
		4503	*/
		4504	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
		4505	{
		4506	uint32_t tmpcr1 = 0;
		4507	tmpcr1 = TIMx->CR1;
		4508
		4509	/* Set TIM Time Base Unit parameters ---------------------------------------*/
		4510	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
		4511	{
		4512	/* Select the Counter Mode */
		4513	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
		4514	tmpcr1 \|= Structure->CounterMode;
		4515	}
		4516
		4517	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
		4518	{
		4519	/* Set the clock division */
		4520	tmpcr1 &= ~TIM_CR1_CKD;
		4521	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
		4522	}
		4523
		4524	TIMx->CR1 = tmpcr1;
		4525
		4526	/* Set the Autoreload value */
		4527	TIMx->ARR = (uint32_t)Structure->Period ;
		4528
		4529	/* Set the Prescaler value */
		4530	TIMx->PSC = (uint32_t)Structure->Prescaler;
		4531
		4532	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
		4533	{
		4534	/* Set the Repetition Counter value */
		4535	TIMx->RCR = Structure->RepetitionCounter;
		4536	}
		4537
		4538	/* Generate an update event to reload the Prescaler
		4539	and the repetition counter(only for TIM1 and TIM8) value immediatly */
		4540	TIMx->EGR = TIM_EGR_UG;
		4541	}
		4542
		4543	/**
		4544	* @brief Time Ouput Compare 1 configuration
		4545	* @param TIMx to select the TIM peripheral
		4546	* @param OC_Config : The ouput configuration structure
		4547	* @retval None
		4548	*/
		4549	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		4550	{
		4551	uint32_t tmpccmrx = 0;
		4552	uint32_t tmpccer = 0;
		4553	uint32_t tmpcr2 = 0;
		4554
		4555	/* Disable the Channel 1: Reset the CC1E Bit */
		4556	TIMx->CCER &= ~TIM_CCER_CC1E;
		4557
		4558	/* Get the TIMx CCER register value */
		4559	tmpccer = TIMx->CCER;
		4560	/* Get the TIMx CR2 register value */
		4561	tmpcr2 = TIMx->CR2;
		4562
		4563	/* Get the TIMx CCMR1 register value */
		4564	tmpccmrx = TIMx->CCMR1;
		4565
		4566	/* Reset the Output Compare Mode Bits */
		4567	tmpccmrx &= ~TIM_CCMR1_OC1M;
		4568	tmpccmrx &= ~TIM_CCMR1_CC1S;
		4569	/* Select the Output Compare Mode */
		4570	tmpccmrx \|= OC_Config->OCMode;
		4571
		4572	/* Reset the Output Polarity level */
		4573	tmpccer &= ~TIM_CCER_CC1P;
		4574	/* Set the Output Compare Polarity */
		4575	tmpccer \|= OC_Config->OCPolarity;
		4576
		4577	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
		4578	{
		4579	/* Check parameters */
		4580	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		4581
		4582	/* Reset the Output N Polarity level */
		4583	tmpccer &= ~TIM_CCER_CC1NP;
		4584	/* Set the Output N Polarity */
		4585	tmpccer \|= OC_Config->OCNPolarity;
		4586	/* Reset the Output N State */
		4587	tmpccer &= ~TIM_CCER_CC1NE;
		4588	}
		4589
		4590	if(IS_TIM_BREAK_INSTANCE(TIMx))
		4591	{
		4592	/* Check parameters */
		4593	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		4594	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		4595
		4596	/* Reset the Output Compare and Output Compare N IDLE State */
		4597	tmpcr2 &= ~TIM_CR2_OIS1;
		4598	tmpcr2 &= ~TIM_CR2_OIS1N;
		4599	/* Set the Output Idle state */
		4600	tmpcr2 \|= OC_Config->OCIdleState;
		4601	/* Set the Output N Idle state */
		4602	tmpcr2 \|= OC_Config->OCNIdleState;
		4603	}
		4604	/* Write to TIMx CR2 */
		4605	TIMx->CR2 = tmpcr2;
		4606
		4607	/* Write to TIMx CCMR1 */
		4608	TIMx->CCMR1 = tmpccmrx;
		4609
		4610	/* Set the Capture Compare Register value */
		4611	TIMx->CCR1 = OC_Config->Pulse;
		4612
		4613	/* Write to TIMx CCER */
		4614	TIMx->CCER = tmpccer;
		4615	}
		4616
		4617	/**
		4618	* @brief Time Ouput Compare 2 configuration
		4619	* @param TIMx to select the TIM peripheral
		4620	* @param OC_Config : The ouput configuration structure
		4621	* @retval None
		4622	*/
		4623	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		4624	{
		4625	uint32_t tmpccmrx = 0;
		4626	uint32_t tmpccer = 0;
		4627	uint32_t tmpcr2 = 0;
		4628
		4629	/* Disable the Channel 2: Reset the CC2E Bit */
		4630	TIMx->CCER &= ~TIM_CCER_CC2E;
		4631
		4632	/* Get the TIMx CCER register value */
		4633	tmpccer = TIMx->CCER;
		4634	/* Get the TIMx CR2 register value */
		4635	tmpcr2 = TIMx->CR2;
		4636
		4637	/* Get the TIMx CCMR1 register value */
		4638	tmpccmrx = TIMx->CCMR1;
		4639
		4640	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		4641	tmpccmrx &= ~TIM_CCMR1_OC2M;
		4642	tmpccmrx &= ~TIM_CCMR1_CC2S;
		4643
		4644	/* Select the Output Compare Mode */
		4645	tmpccmrx \|= (OC_Config->OCMode << 8);
		4646
		4647	/* Reset the Output Polarity level */
		4648	tmpccer &= ~TIM_CCER_CC2P;
		4649	/* Set the Output Compare Polarity */
		4650	tmpccer \|= (OC_Config->OCPolarity << 4);
		4651
		4652	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
		4653	{
		4654	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		4655	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		4656	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		4657
		4658	/* Reset the Output N Polarity level */
		4659	tmpccer &= ~TIM_CCER_CC2NP;
		4660	/* Set the Output N Polarity */
		4661	tmpccer \|= (OC_Config->OCNPolarity << 4);
		4662	/* Reset the Output N State */
		4663	tmpccer &= ~TIM_CCER_CC2NE;
		4664
		4665	}
		4666
		4667	if(IS_TIM_BREAK_INSTANCE(TIMx))
		4668	{
		4669	/* Check parameters */
		4670	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		4671	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		4672
		4673	/* Reset the Output Compare and Output Compare N IDLE State */
		4674	tmpcr2 &= ~TIM_CR2_OIS2;
		4675	tmpcr2 &= ~TIM_CR2_OIS2N;
		4676	/* Set the Output Idle state */
		4677	tmpcr2 \|= (OC_Config->OCIdleState << 2);
		4678	/* Set the Output N Idle state */
		4679	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
		4680	}
		4681
		4682	/* Write to TIMx CR2 */
		4683	TIMx->CR2 = tmpcr2;
		4684
		4685	/* Write to TIMx CCMR1 */
		4686	TIMx->CCMR1 = tmpccmrx;
		4687
		4688	/* Set the Capture Compare Register value */
		4689	TIMx->CCR2 = OC_Config->Pulse;
		4690
		4691	/* Write to TIMx CCER */
		4692	TIMx->CCER = tmpccer;
		4693	}
		4694
		4695	/**
		4696	* @brief Time Ouput Compare 3 configuration
		4697	* @param TIMx to select the TIM peripheral
		4698	* @param OC_Config : The ouput configuration structure
		4699	* @retval None
		4700	*/
		4701	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		4702	{
		4703	uint32_t tmpccmrx = 0;
		4704	uint32_t tmpccer = 0;
		4705	uint32_t tmpcr2 = 0;
		4706
		4707	/* Disable the Channel 3: Reset the CC2E Bit */
		4708	TIMx->CCER &= ~TIM_CCER_CC3E;
		4709
		4710	/* Get the TIMx CCER register value */
		4711	tmpccer = TIMx->CCER;
		4712	/* Get the TIMx CR2 register value */
		4713	tmpcr2 = TIMx->CR2;
		4714
		4715	/* Get the TIMx CCMR2 register value */
		4716	tmpccmrx = TIMx->CCMR2;
		4717
		4718	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		4719	tmpccmrx &= ~TIM_CCMR2_OC3M;
		4720	tmpccmrx &= ~TIM_CCMR2_CC3S;
		4721	/* Select the Output Compare Mode */
		4722	tmpccmrx \|= OC_Config->OCMode;
		4723
		4724	/* Reset the Output Polarity level */
		4725	tmpccer &= ~TIM_CCER_CC3P;
		4726	/* Set the Output Compare Polarity */
		4727	tmpccer \|= (OC_Config->OCPolarity << 8);
		4728
		4729	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
		4730	{
		4731	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		4732	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		4733	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		4734
		4735	/* Reset the Output N Polarity level */
		4736	tmpccer &= ~TIM_CCER_CC3NP;
		4737	/* Set the Output N Polarity */
		4738	tmpccer \|= (OC_Config->OCNPolarity << 8);
		4739	/* Reset the Output N State */
		4740	tmpccer &= ~TIM_CCER_CC3NE;
		4741	}
		4742
		4743	if(IS_TIM_BREAK_INSTANCE(TIMx))
		4744	{
		4745	/* Check parameters */
		4746	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		4747	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		4748
		4749	/* Reset the Output Compare and Output Compare N IDLE State */
		4750	tmpcr2 &= ~TIM_CR2_OIS3;
		4751	tmpcr2 &= ~TIM_CR2_OIS3N;
		4752	/* Set the Output Idle state */
		4753	tmpcr2 \|= (OC_Config->OCIdleState << 4);
		4754	/* Set the Output N Idle state */
		4755	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
		4756	}
		4757
		4758	/* Write to TIMx CR2 */
		4759	TIMx->CR2 = tmpcr2;
		4760
		4761	/* Write to TIMx CCMR2 */
		4762	TIMx->CCMR2 = tmpccmrx;
		4763
		4764	/* Set the Capture Compare Register value */
		4765	TIMx->CCR3 = OC_Config->Pulse;
		4766
		4767	/* Write to TIMx CCER */
		4768	TIMx->CCER = tmpccer;
		4769	}
		4770
		4771	/**
		4772	* @brief Time Ouput Compare 4 configuration
		4773	* @param TIMx to select the TIM peripheral
		4774	* @param OC_Config : The ouput configuration structure
		4775	* @retval None
		4776	*/
		4777	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		4778	{
		4779	uint32_t tmpccmrx = 0;
		4780	uint32_t tmpccer = 0;
		4781	uint32_t tmpcr2 = 0;
		4782
		4783	/* Disable the Channel 4: Reset the CC4E Bit */
		4784	TIMx->CCER &= ~TIM_CCER_CC4E;
		4785
		4786	/* Get the TIMx CCER register value */
		4787	tmpccer = TIMx->CCER;
		4788	/* Get the TIMx CR2 register value */
		4789	tmpcr2 = TIMx->CR2;
		4790
		4791	/* Get the TIMx CCMR2 register value */
		4792	tmpccmrx = TIMx->CCMR2;
		4793
		4794	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		4795	tmpccmrx &= ~TIM_CCMR2_OC4M;
		4796	tmpccmrx &= ~TIM_CCMR2_CC4S;
		4797
		4798	/* Select the Output Compare Mode */
		4799	tmpccmrx \|= (OC_Config->OCMode << 8);
		4800
		4801	/* Reset the Output Polarity level */
		4802	tmpccer &= ~TIM_CCER_CC4P;
		4803	/* Set the Output Compare Polarity */
		4804	tmpccer \|= (OC_Config->OCPolarity << 12);
		4805
		4806	if(IS_TIM_BREAK_INSTANCE(TIMx))
		4807	{
		4808	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		4809
		4810	/* Reset the Output Compare IDLE State */
		4811	tmpcr2 &= ~TIM_CR2_OIS4;
		4812	/* Set the Output Idle state */
		4813	tmpcr2 \|= (OC_Config->OCIdleState << 6);
		4814	}
		4815
		4816	/* Write to TIMx CR2 */
		4817	TIMx->CR2 = tmpcr2;
		4818
		4819	/* Write to TIMx CCMR2 */
		4820	TIMx->CCMR2 = tmpccmrx;
		4821
		4822	/* Set the Capture Compare Register value */
		4823	TIMx->CCR4 = OC_Config->Pulse;
		4824
		4825	/* Write to TIMx CCER */
		4826	TIMx->CCER = tmpccer;
		4827	}
		4828
		4829
		4830	/**
		4831	* @brief Time Slave configuration
		4832	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
		4833	* the configuration information for TIM module.
		4834	* @param sSlaveConfig: The slave configuration structure
		4835	* @retval None
		4836	*/
		4837	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
		4838	TIM_SlaveConfigTypeDef * sSlaveConfig)
		4839	{
		4840	uint32_t tmpsmcr = 0;
		4841	uint32_t tmpccmr1 = 0;
		4842	uint32_t tmpccer = 0;
		4843
		4844	/* Get the TIMx SMCR register value */
		4845	tmpsmcr = htim->Instance->SMCR;
		4846
		4847	/* Reset the Trigger Selection Bits */
		4848	tmpsmcr &= ~TIM_SMCR_TS;
		4849	/* Set the Input Trigger source */
		4850	tmpsmcr \|= sSlaveConfig->InputTrigger;
		4851
		4852	/* Reset the slave mode Bits */
		4853	tmpsmcr &= ~TIM_SMCR_SMS;
		4854	/* Set the slave mode */
		4855	tmpsmcr \|= sSlaveConfig->SlaveMode;
		4856
		4857	/* Write to TIMx SMCR */
		4858	htim->Instance->SMCR = tmpsmcr;
		4859
		4860	/* Configure the trigger prescaler, filter, and polarity */
		4861	switch (sSlaveConfig->InputTrigger)
		4862	{
		4863	case TIM_TS_ETRF:
		4864	{
		4865	/* Check the parameters */
		4866	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
		4867	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
		4868	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		4869	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		4870	/* Configure the ETR Trigger source */
		4871	TIM_ETR_SetConfig(htim->Instance,
		4872	sSlaveConfig->TriggerPrescaler,
		4873	sSlaveConfig->TriggerPolarity,
		4874	sSlaveConfig->TriggerFilter);
		4875	}
		4876	break;
		4877
		4878	case TIM_TS_TI1F_ED:
		4879	{
		4880	/* Check the parameters */
		4881	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		4882	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		4883
		4884	/* Disable the Channel 1: Reset the CC1E Bit */
		4885	tmpccer = htim->Instance->CCER;
		4886	htim->Instance->CCER &= ~TIM_CCER_CC1E;
		4887	tmpccmr1 = htim->Instance->CCMR1;
		4888
		4889	/* Set the filter */
		4890	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		4891	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
		4892
		4893	/* Write to TIMx CCMR1 and CCER registers */
		4894	htim->Instance->CCMR1 = tmpccmr1;
		4895	htim->Instance->CCER = tmpccer;
		4896
		4897	}
		4898	break;
		4899
		4900	case TIM_TS_TI1FP1:
		4901	{
		4902	/* Check the parameters */
		4903	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		4904	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		4905	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		4906
		4907	/* Configure TI1 Filter and Polarity */
		4908	TIM_TI1_ConfigInputStage(htim->Instance,
		4909	sSlaveConfig->TriggerPolarity,
		4910	sSlaveConfig->TriggerFilter);
		4911	}
		4912	break;
		4913
		4914	case TIM_TS_TI2FP2:
		4915	{
		4916	/* Check the parameters */
		4917	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4918	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		4919	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		4920
		4921	/* Configure TI2 Filter and Polarity */
		4922	TIM_TI2_ConfigInputStage(htim->Instance,
		4923	sSlaveConfig->TriggerPolarity,
		4924	sSlaveConfig->TriggerFilter);
		4925	}
		4926	break;
		4927
		4928	case TIM_TS_ITR0:
		4929	{
		4930	/* Check the parameter */
		4931	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4932	}
		4933	break;
		4934
		4935	case TIM_TS_ITR1:
		4936	{
		4937	/* Check the parameter */
		4938	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4939	}
		4940	break;
		4941
		4942	case TIM_TS_ITR2:
		4943	{
		4944	/* Check the parameter */
		4945	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4946	}
		4947	break;
		4948
		4949	case TIM_TS_ITR3:
		4950	{
		4951	/* Check the parameter */
		4952	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4953	}
		4954	break;
		4955
		4956	default:
		4957	break;
		4958	}
		4959	}
		4960
		4961	/**
		4962	* @brief Configure the TI1 as Input.
		4963	* @param TIMx to select the TIM peripheral.
		4964	* @param TIM_ICPolarity : The Input Polarity.
		4965	* This parameter can be one of the following values:
		4966	* @arg TIM_ICPOLARITY_RISING
		4967	* @arg TIM_ICPOLARITY_FALLING
		4968	* @arg TIM_ICPOLARITY_BOTHEDGE
		4969	* @param TIM_ICSelection : specifies the input to be used.
		4970	* This parameter can be one of the following values:
		4971	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
		4972	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
		4973	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
		4974	* @param TIM_ICFilter : Specifies the Input Capture Filter.
		4975	* This parameter must be a value between 0x00 and 0x0F.
		4976	* @retval None
		4977	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
		4978	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
		4979	* protected against un-initialized filter and polarity values.
		4980	*/
		4981	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		4982	uint32_t TIM_ICFilter)
		4983	{
		4984	uint32_t tmpccmr1 = 0;
		4985	uint32_t tmpccer = 0;
		4986
		4987	/* Disable the Channel 1: Reset the CC1E Bit */
		4988	TIMx->CCER &= ~TIM_CCER_CC1E;
		4989	tmpccmr1 = TIMx->CCMR1;
		4990	tmpccer = TIMx->CCER;
		4991
		4992	/* Select the Input */
		4993	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
		4994	{
		4995	tmpccmr1 &= ~TIM_CCMR1_CC1S;
		4996	tmpccmr1 \|= TIM_ICSelection;
		4997	}
		4998	else
		4999	{
		5000	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
		5001	}
		5002
		5003	/* Set the filter */
		5004	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		5005	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
		5006
		5007	/* Select the Polarity and set the CC1E Bit */
		5008	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
		5009	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
		5010
		5011	/* Write to TIMx CCMR1 and CCER registers */
		5012	TIMx->CCMR1 = tmpccmr1;
		5013	TIMx->CCER = tmpccer;
		5014	}
		5015
		5016	/**
		5017	* @brief Configure the Polarity and Filter for TI1.
		5018	* @param TIMx to select the TIM peripheral.
		5019	* @param TIM_ICPolarity : The Input Polarity.
		5020	* This parameter can be one of the following values:
		5021	* @arg TIM_ICPOLARITY_RISING
		5022	* @arg TIM_ICPOLARITY_FALLING
		5023	* @arg TIM_ICPOLARITY_BOTHEDGE
		5024	* @param TIM_ICFilter : Specifies the Input Capture Filter.
		5025	* This parameter must be a value between 0x00 and 0x0F.
		5026	* @retval None
		5027	*/
		5028	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
		5029	{
		5030	uint32_t tmpccmr1 = 0;
		5031	uint32_t tmpccer = 0;
		5032
		5033	/* Disable the Channel 1: Reset the CC1E Bit */
		5034	tmpccer = TIMx->CCER;
		5035	TIMx->CCER &= ~TIM_CCER_CC1E;
		5036	tmpccmr1 = TIMx->CCMR1;
		5037
		5038	/* Set the filter */
		5039	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		5040	tmpccmr1 \|= (TIM_ICFilter << 4);
		5041
		5042	/* Select the Polarity and set the CC1E Bit */
		5043	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
		5044	tmpccer \|= TIM_ICPolarity;
		5045
		5046	/* Write to TIMx CCMR1 and CCER registers */
		5047	TIMx->CCMR1 = tmpccmr1;
		5048	TIMx->CCER = tmpccer;
		5049	}
		5050
		5051	/**
		5052	* @brief Configure the TI2 as Input.
		5053	* @param TIMx to select the TIM peripheral
		5054	* @param TIM_ICPolarity : The Input Polarity.
		5055	* This parameter can be one of the following values:
		5056	* @arg TIM_ICPOLARITY_RISING
		5057	* @arg TIM_ICPOLARITY_FALLING
		5058	* @arg TIM_ICPOLARITY_BOTHEDGE
		5059	* @param TIM_ICSelection : specifies the input to be used.
		5060	* This parameter can be one of the following values:
		5061	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
		5062	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
		5063	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
		5064	* @param TIM_ICFilter : Specifies the Input Capture Filter.
		5065	* This parameter must be a value between 0x00 and 0x0F.
		5066	* @retval None
		5067	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
		5068	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
		5069	* protected against un-initialized filter and polarity values.
		5070	*/
		5071	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		5072	uint32_t TIM_ICFilter)
		5073	{
		5074	uint32_t tmpccmr1 = 0;
		5075	uint32_t tmpccer = 0;
		5076
		5077	/* Disable the Channel 2: Reset the CC2E Bit */
		5078	TIMx->CCER &= ~TIM_CCER_CC2E;
		5079	tmpccmr1 = TIMx->CCMR1;
		5080	tmpccer = TIMx->CCER;
		5081
		5082	/* Select the Input */
		5083	tmpccmr1 &= ~TIM_CCMR1_CC2S;
		5084	tmpccmr1 \|= (TIM_ICSelection << 8);
		5085
		5086	/* Set the filter */
		5087	tmpccmr1 &= ~TIM_CCMR1_IC2F;
		5088	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
		5089
		5090	/* Select the Polarity and set the CC2E Bit */
		5091	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
		5092	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
		5093
		5094	/* Write to TIMx CCMR1 and CCER registers */
		5095	TIMx->CCMR1 = tmpccmr1 ;
		5096	TIMx->CCER = tmpccer;
		5097	}
		5098
		5099	/**
		5100	* @brief Configure the Polarity and Filter for TI2.
		5101	* @param TIMx to select the TIM peripheral.
		5102	* @param TIM_ICPolarity : The Input Polarity.
		5103	* This parameter can be one of the following values:
		5104	* @arg TIM_ICPOLARITY_RISING
		5105	* @arg TIM_ICPOLARITY_FALLING
		5106	* @arg TIM_ICPOLARITY_BOTHEDGE
		5107	* @param TIM_ICFilter : Specifies the Input Capture Filter.
		5108	* This parameter must be a value between 0x00 and 0x0F.
		5109	* @retval None
		5110	*/
		5111	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
		5112	{
		5113	uint32_t tmpccmr1 = 0;
		5114	uint32_t tmpccer = 0;
		5115
		5116	/* Disable the Channel 2: Reset the CC2E Bit */
		5117	TIMx->CCER &= ~TIM_CCER_CC2E;
		5118	tmpccmr1 = TIMx->CCMR1;
		5119	tmpccer = TIMx->CCER;
		5120
		5121	/* Set the filter */
		5122	tmpccmr1 &= ~TIM_CCMR1_IC2F;
		5123	tmpccmr1 \|= (TIM_ICFilter << 12);
		5124
		5125	/* Select the Polarity and set the CC2E Bit */
		5126	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
		5127	tmpccer \|= (TIM_ICPolarity << 4);
		5128
		5129	/* Write to TIMx CCMR1 and CCER registers */
		5130	TIMx->CCMR1 = tmpccmr1 ;
		5131	TIMx->CCER = tmpccer;
		5132	}
		5133
		5134	/**
		5135	* @brief Configure the TI3 as Input.
		5136	* @param TIMx to select the TIM peripheral
		5137	* @param TIM_ICPolarity : The Input Polarity.
		5138	* This parameter can be one of the following values:
		5139	* @arg TIM_ICPOLARITY_RISING
		5140	* @arg TIM_ICPOLARITY_FALLING
		5141	* @arg TIM_ICPOLARITY_BOTHEDGE
		5142	* @param TIM_ICSelection : specifies the input to be used.
		5143	* This parameter can be one of the following values:
		5144	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
		5145	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
		5146	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
		5147	* @param TIM_ICFilter : Specifies the Input Capture Filter.
		5148	* This parameter must be a value between 0x00 and 0x0F.
		5149	* @retval None
		5150	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
		5151	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
		5152	* protected against un-initialized filter and polarity values.
		5153	*/
		5154	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		5155	uint32_t TIM_ICFilter)
		5156	{
		5157	uint32_t tmpccmr2 = 0;
		5158	uint32_t tmpccer = 0;
		5159
		5160	/* Disable the Channel 3: Reset the CC3E Bit */
		5161	TIMx->CCER &= ~TIM_CCER_CC3E;
		5162	tmpccmr2 = TIMx->CCMR2;
		5163	tmpccer = TIMx->CCER;
		5164
		5165	/* Select the Input */
		5166	tmpccmr2 &= ~TIM_CCMR2_CC3S;
		5167	tmpccmr2 \|= TIM_ICSelection;
		5168
		5169	/* Set the filter */
		5170	tmpccmr2 &= ~TIM_CCMR2_IC3F;
		5171	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
		5172
		5173	/* Select the Polarity and set the CC3E Bit */
		5174	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
		5175	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
		5176
		5177	/* Write to TIMx CCMR2 and CCER registers */
		5178	TIMx->CCMR2 = tmpccmr2;
		5179	TIMx->CCER = tmpccer;
		5180	}
		5181
		5182	/**
		5183	* @brief Configure the TI4 as Input.
		5184	* @param TIMx to select the TIM peripheral
		5185	* @param TIM_ICPolarity : The Input Polarity.
		5186	* This parameter can be one of the following values:
		5187	* @arg TIM_ICPOLARITY_RISING
		5188	* @arg TIM_ICPOLARITY_FALLING
		5189	* @arg TIM_ICPOLARITY_BOTHEDGE
		5190	* @param TIM_ICSelection : specifies the input to be used.
		5191	* This parameter can be one of the following values:
		5192	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
		5193	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
		5194	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
		5195	* @param TIM_ICFilter : Specifies the Input Capture Filter.
		5196	* This parameter must be a value between 0x00 and 0x0F.
		5197	* @retval None
		5198	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
		5199	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
		5200	* protected against un-initialized filter and polarity values.
		5201	*/
		5202	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		5203	uint32_t TIM_ICFilter)
		5204	{
		5205	uint32_t tmpccmr2 = 0;
		5206	uint32_t tmpccer = 0;
		5207
		5208	/* Disable the Channel 4: Reset the CC4E Bit */
		5209	TIMx->CCER &= ~TIM_CCER_CC4E;
		5210	tmpccmr2 = TIMx->CCMR2;
		5211	tmpccer = TIMx->CCER;
		5212
		5213	/* Select the Input */
		5214	tmpccmr2 &= ~TIM_CCMR2_CC4S;
		5215	tmpccmr2 \|= (TIM_ICSelection << 8);
		5216
		5217	/* Set the filter */
		5218	tmpccmr2 &= ~TIM_CCMR2_IC4F;
		5219	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
		5220
		5221	/* Select the Polarity and set the CC4E Bit */
		5222	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
		5223	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
		5224
		5225	/* Write to TIMx CCMR2 and CCER registers */
		5226	TIMx->CCMR2 = tmpccmr2;
		5227	TIMx->CCER = tmpccer ;
		5228	}
		5229
		5230	/**
		5231	* @brief Selects the Input Trigger source
		5232	* @param TIMx to select the TIM peripheral
		5233	* @param InputTriggerSource : The Input Trigger source.
		5234	* This parameter can be one of the following values:
		5235	* @arg TIM_TS_ITR0 : Internal Trigger 0
		5236	* @arg TIM_TS_ITR1 : Internal Trigger 1
		5237	* @arg TIM_TS_ITR2 : Internal Trigger 2
		5238	* @arg TIM_TS_ITR3 : Internal Trigger 3
		5239	* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
		5240	* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
		5241	* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
		5242	* @arg TIM_TS_ETRF : External Trigger input
		5243	* @retval None
		5244	*/
		5245	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
		5246	{
		5247	uint32_t tmpsmcr = 0;
		5248
		5249	/* Get the TIMx SMCR register value */
		5250	tmpsmcr = TIMx->SMCR;
		5251	/* Reset the TS Bits */
		5252	tmpsmcr &= ~TIM_SMCR_TS;
		5253	/* Set the Input Trigger source and the slave mode*/
		5254	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
		5255	/* Write to TIMx SMCR */
		5256	TIMx->SMCR = tmpsmcr;
		5257	}
		5258	/**
		5259	* @brief Configures the TIMx External Trigger (ETR).
		5260	* @param TIMx to select the TIM peripheral
		5261	* @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
		5262	* This parameter can be one of the following values:
		5263	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
		5264	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
		5265	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
		5266	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
		5267	* @param TIM_ExtTRGPolarity : The external Trigger Polarity.
		5268	* This parameter can be one of the following values:
		5269	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
		5270	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
		5271	* @param ExtTRGFilter : External Trigger Filter.
		5272	* This parameter must be a value between 0x00 and 0x0F
		5273	* @retval None
		5274	*/
		5275	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
		5276	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
		5277	{
		5278	uint32_t tmpsmcr = 0;
		5279
		5280	tmpsmcr = TIMx->SMCR;
		5281
		5282	/* Reset the ETR Bits */
		5283	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		5284
		5285	/* Set the Prescaler, the Filter value and the Polarity */
		5286	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
		5287
		5288	/* Write to TIMx SMCR */
		5289	TIMx->SMCR = tmpsmcr;
		5290	}
		5291
		5292	/**
		5293	* @brief Enables or disables the TIM Capture Compare Channel x.
		5294	* @param TIMx to select the TIM peripheral
		5295	* @param Channel : specifies the TIM Channel
		5296	* This parameter can be one of the following values:
		5297	* @arg TIM_CHANNEL_1: TIM Channel 1
		5298	* @arg TIM_CHANNEL_2: TIM Channel 2
		5299	* @arg TIM_CHANNEL_3: TIM Channel 3
		5300	* @arg TIM_CHANNEL_4: TIM Channel 4
		5301	* @param ChannelState : specifies the TIM Channel CCxE bit new state.
		5302	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
		5303	* @retval None
		5304	*/
		5305	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
		5306	{
		5307	uint32_t tmp = 0;
		5308
		5309	/* Check the parameters */
		5310	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
		5311	assert_param(IS_TIM_CHANNELS(Channel));
		5312
		5313	tmp = TIM_CCER_CC1E << Channel;
		5314
		5315	/* Reset the CCxE Bit */
		5316	TIMx->CCER &= ~tmp;
		5317
		5318	/* Set or reset the CCxE Bit */
		5319	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
		5320	}
		5321
		5322	/**
		5323	* @}
		5324	*/
		5325
		5326	#endif /* HAL_TIM_MODULE_ENABLED */
		5327	/**
		5328	* @}
		5329	*/
		5330
		5331	/**
		5332	* @}
		5333	*/
		5334	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c – Rev 2