WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_sram.c
		4	* @author MCD Application Team
		5	* @brief SRAM HAL module driver.
9	mjames	6	* This file provides a generic firmware to drive SRAM memories
2	mjames	7	* mounted as external device.
9	mjames	8	*
2	mjames	9	@verbatim
		10	==============================================================================
		11	##### How to use this driver #####
9	mjames	12	==============================================================================
2	mjames	13	[..]
9	mjames	14	This driver is a generic layered driver which contains a set of APIs used to
		15	control SRAM memories. It uses the FSMC layer functions to interface
		16	with SRAM devices.
2	mjames	17	The following sequence should be followed to configure the FSMC to interface
9	mjames	18	with SRAM/PSRAM memories:
		19
2	mjames	20	(#) Declare a SRAM_HandleTypeDef handle structure, for example:
9	mjames	21	SRAM_HandleTypeDef hsram; and:
		22
		23	(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
2	mjames	24	values of the structure member.
9	mjames	25
		26	(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
		27	base register instance for NOR or SRAM device
		28
2	mjames	29	(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
9	mjames	30	base register instance for NOR or SRAM extended mode
		31
		32	(#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
2	mjames	33	mode timings; for example:
		34	FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
		35	and fill its fields with the allowed values of the structure member.
9	mjames	36
2	mjames	37	(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
		38	performs the following sequence:
9	mjames	39
2	mjames	40	(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
9	mjames	41	(##) Control register configuration using the FSMC NORSRAM interface function
2	mjames	42	FSMC_NORSRAM_Init()
9	mjames	43	(##) Timing register configuration using the FSMC NORSRAM interface function
2	mjames	44	FSMC_NORSRAM_Timing_Init()
9	mjames	45	(##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
2	mjames	46	FSMC_NORSRAM_Extended_Timing_Init()
9	mjames	47	(##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
2	mjames	48
9	mjames	49	(#) At this stage you can perform read/write accesses from/to the memory connected
2	mjames	50	to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
		51	following APIs:
		52	(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
		53	(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
9	mjames	54
2	mjames	55	(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
9	mjames	56	HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
		57
2	mjames	58	(#) You can continuously monitor the SRAM device HAL state by calling the function
9	mjames	59	HAL_SRAM_GetState()
		60
		61	* Callback registration *
		62	=============================================
		63	[..]
		64	The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
		65	allows the user to configure dynamically the driver callbacks.
		66
		67	Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
		68	it allows to register following callbacks:
		69	(+) MspInitCallback : SRAM MspInit.
		70	(+) MspDeInitCallback : SRAM MspDeInit.
		71	This function takes as parameters the HAL peripheral handle, the Callback ID
		72	and a pointer to the user callback function.
		73
		74	Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
		75	weak (surcharged) function. It allows to reset following callbacks:
		76	(+) MspInitCallback : SRAM MspInit.
		77	(+) MspDeInitCallback : SRAM MspDeInit.
		78	This function) takes as parameters the HAL peripheral handle and the Callback ID.
		79
		80	By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
		81	all callbacks are reset to the corresponding legacy weak (surcharged) functions.
		82	Exception done for MspInit and MspDeInit callbacks that are respectively
		83	reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
		84	and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
		85	If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
		86	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
		87
		88	Callbacks can be registered/unregistered in READY state only.
		89	Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
		90	in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
		91	during the Init/DeInit.
		92	In that case first register the MspInit/MspDeInit user callbacks
		93	using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
		94	or @ref HAL_SRAM_Init function.
		95
		96	When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
		97	not defined, the callback registering feature is not available
		98	and weak (surcharged) callbacks are used.
		99
2	mjames	100	@endverbatim
		101	******************************************************************************
		102	* @attention
		103	*
9	mjames	104	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		105	* All rights reserved.</center></h2>
2	mjames	106	*
9	mjames	107	* This software component is licensed by ST under BSD 3-Clause license,
		108	* the "License"; You may not use this file except in compliance with the
		109	* License. You may obtain a copy of the License at:
		110	* opensource.org/licenses/BSD-3-Clause
2	mjames	111	*
		112	******************************************************************************
9	mjames	113	*/
2	mjames	114
		115	/* Includes ------------------------------------------------------------------*/
		116	#include "stm32f1xx_hal.h"
		117
9	mjames	118	#if defined FSMC_BANK1
		119
2	mjames	120	/** @addtogroup STM32F1xx_HAL_Driver
		121	* @{
		122	*/
		123
		124	#ifdef HAL_SRAM_MODULE_ENABLED
		125
		126	/** @defgroup SRAM SRAM
		127	* @brief SRAM driver modules
		128	* @{
		129	*/
9	mjames	130
		131	/**
		132	@cond 0
		133	*/
2	mjames	134	/* Private typedef -----------------------------------------------------------*/
		135	/* Private define ------------------------------------------------------------*/
9	mjames	136	/* Private macro -------------------------------------------------------------*/
2	mjames	137	/* Private variables ---------------------------------------------------------*/
		138	/* Private function prototypes -----------------------------------------------*/
9	mjames	139	static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
		140	static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
		141	static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
		142	/**
		143	@endcond
		144	*/
		145
2	mjames	146	/* Exported functions --------------------------------------------------------*/
		147
		148	/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
		149	* @{
		150	*/
		151
9	mjames	152	/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
2	mjames	153	* @brief Initialization and Configuration functions.
		154	*
9	mjames	155	@verbatim
2	mjames	156	==============================================================================
		157	##### SRAM Initialization and de_initialization functions #####
		158	==============================================================================
		159	[..] This section provides functions allowing to initialize/de-initialize
		160	the SRAM memory
9	mjames	161
2	mjames	162	@endverbatim
		163	* @{
		164	*/
		165
		166	/**
		167	* @brief Performs the SRAM device initialization sequence
9	mjames	168	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	169	* the configuration information for SRAM module.
9	mjames	170	* @param Timing Pointer to SRAM control timing structure
		171	* @param ExtTiming Pointer to SRAM extended mode timing structure
2	mjames	172	* @retval HAL status
		173	*/
9	mjames	174	HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef hsram, FSMC_NORSRAM_TimingTypeDef Timing,
		175	FSMC_NORSRAM_TimingTypeDef *ExtTiming)
		176	{
2	mjames	177	/* Check the SRAM handle parameter */
9	mjames	178	if ((hsram == NULL) \|\| (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
2	mjames	179	{
9	mjames	180	return HAL_ERROR;
2	mjames	181	}
9	mjames	182
		183	if (hsram->State == HAL_SRAM_STATE_RESET)
		184	{
2	mjames	185	/* Allocate lock resource and initialize it */
		186	hsram->Lock = HAL_UNLOCKED;
9	mjames	187
		188	#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
		189	if (hsram->MspInitCallback == NULL)
		190	{
		191	hsram->MspInitCallback = HAL_SRAM_MspInit;
		192	}
		193	hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
		194	hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
		195
		196	/* Init the low level hardware */
		197	hsram->MspInitCallback(hsram);
		198	#else
2	mjames	199	/* Initialize the low level hardware (MSP) */
		200	HAL_SRAM_MspInit(hsram);
9	mjames	201	#endif
2	mjames	202	}
9	mjames	203
2	mjames	204	/* Initialize SRAM control Interface */
9	mjames	205	(void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
2	mjames	206
		207	/* Initialize SRAM timing Interface */
9	mjames	208	(void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
2	mjames	209
		210	/* Initialize SRAM extended mode timing Interface */
9	mjames	211	(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
		212	hsram->Init.ExtendedMode);
		213
2	mjames	214	/* Enable the NORSRAM device */
9	mjames	215	__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
		216
		217	/* Initialize the SRAM controller state */
		218	hsram->State = HAL_SRAM_STATE_READY;
		219
2	mjames	220	return HAL_OK;
		221	}
		222
		223	/**
		224	* @brief Performs the SRAM device De-initialization sequence.
9	mjames	225	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	226	* the configuration information for SRAM module.
		227	* @retval HAL status
		228	*/
9	mjames	229	HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
		230	{
		231	#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
		232	if (hsram->MspDeInitCallback == NULL)
		233	{
		234	hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
		235	}
		236
		237	/* DeInit the low level hardware */
		238	hsram->MspDeInitCallback(hsram);
		239	#else
2	mjames	240	/* De-Initialize the low level hardware (MSP) */
		241	HAL_SRAM_MspDeInit(hsram);
9	mjames	242	#endif
		243
2	mjames	244	/* Configure the SRAM registers with their reset values */
9	mjames	245	(void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
2	mjames	246
9	mjames	247	/* Reset the SRAM controller state */
2	mjames	248	hsram->State = HAL_SRAM_STATE_RESET;
9	mjames	249
2	mjames	250	/* Release Lock */
		251	__HAL_UNLOCK(hsram);
		252
		253	return HAL_OK;
		254	}
		255
		256	/**
		257	* @brief SRAM MSP Init.
9	mjames	258	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	259	* the configuration information for SRAM module.
		260	* @retval None
		261	*/
		262	__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
		263	{
		264	/* Prevent unused argument(s) compilation warning */
		265	UNUSED(hsram);
9	mjames	266
2	mjames	267	/* NOTE : This function Should not be modified, when the callback is needed,
		268	the HAL_SRAM_MspInit could be implemented in the user file
9	mjames	269	*/
2	mjames	270	}
		271
		272	/**
		273	* @brief SRAM MSP DeInit.
9	mjames	274	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	275	* the configuration information for SRAM module.
		276	* @retval None
		277	*/
		278	__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
		279	{
		280	/* Prevent unused argument(s) compilation warning */
		281	UNUSED(hsram);
9	mjames	282
2	mjames	283	/* NOTE : This function Should not be modified, when the callback is needed,
		284	the HAL_SRAM_MspDeInit could be implemented in the user file
9	mjames	285	*/
2	mjames	286	}
		287
		288	/**
		289	* @brief DMA transfer complete callback.
9	mjames	290	* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	291	* the configuration information for SRAM module.
		292	* @retval None
		293	*/
		294	__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
		295	{
		296	/* Prevent unused argument(s) compilation warning */
		297	UNUSED(hdma);
9	mjames	298
2	mjames	299	/* NOTE : This function Should not be modified, when the callback is needed,
		300	the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
9	mjames	301	*/
2	mjames	302	}
		303
		304	/**
		305	* @brief DMA transfer complete error callback.
9	mjames	306	* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	307	* the configuration information for SRAM module.
		308	* @retval None
		309	*/
		310	__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
		311	{
		312	/* Prevent unused argument(s) compilation warning */
		313	UNUSED(hdma);
9	mjames	314
2	mjames	315	/* NOTE : This function Should not be modified, when the callback is needed,
		316	the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
9	mjames	317	*/
2	mjames	318	}
		319
		320	/**
		321	* @}
		322	*/
		323
9	mjames	324	/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
		325	* @brief Input Output and memory control functions
2	mjames	326	*
9	mjames	327	@verbatim
2	mjames	328	==============================================================================
		329	##### SRAM Input and Output functions #####
		330	==============================================================================
9	mjames	331	[..]
2	mjames	332	This section provides functions allowing to use and control the SRAM memory
9	mjames	333
2	mjames	334	@endverbatim
		335	* @{
		336	*/
		337
		338	/**
9	mjames	339	* @brief Reads 8-bit buffer from SRAM memory.
		340	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	341	* the configuration information for SRAM module.
9	mjames	342	* @param pAddress Pointer to read start address
		343	* @param pDstBuffer Pointer to destination buffer
		344	* @param BufferSize Size of the buffer to read from memory
2	mjames	345	* @retval HAL status
		346	*/
9	mjames	347	HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint8_t *pDstBuffer,
		348	uint32_t BufferSize)
2	mjames	349	{
9	mjames	350	uint32_t size;
		351	__IO uint8_t psramaddress = (uint8_t )pAddress;
		352	uint8_t *pdestbuff = pDstBuffer;
		353	HAL_SRAM_StateTypeDef state = hsram->State;
		354
		355	/* Check the SRAM controller state */
		356	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_PROTECTED))
2	mjames	357	{
9	mjames	358	/* Process Locked */
		359	__HAL_LOCK(hsram);
		360
		361	/* Update the SRAM controller state */
		362	hsram->State = HAL_SRAM_STATE_BUSY;
		363
		364	/* Read data from memory */
		365	for (size = BufferSize; size != 0U; size--)
		366	{
		367	pdestbuff = psramaddress;
		368	pdestbuff++;
		369	psramaddress++;
		370	}
		371
		372	/* Update the SRAM controller state */
		373	hsram->State = state;
		374
		375	/* Process unlocked */
		376	__HAL_UNLOCK(hsram);
2	mjames	377	}
9	mjames	378	else
		379	{
		380	return HAL_ERROR;
		381	}
2	mjames	382
9	mjames	383	return HAL_OK;
2	mjames	384	}
		385
		386	/**
9	mjames	387	* @brief Writes 8-bit buffer to SRAM memory.
		388	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	389	* the configuration information for SRAM module.
9	mjames	390	* @param pAddress Pointer to write start address
		391	* @param pSrcBuffer Pointer to source buffer to write
		392	* @param BufferSize Size of the buffer to write to memory
2	mjames	393	* @retval HAL status
		394	*/
9	mjames	395	HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint8_t *pSrcBuffer,
		396	uint32_t BufferSize)
2	mjames	397	{
9	mjames	398	uint32_t size;
		399	__IO uint8_t psramaddress = (uint8_t )pAddress;
		400	uint8_t *psrcbuff = pSrcBuffer;
		401
2	mjames	402	/* Check the SRAM controller state */
9	mjames	403	if (hsram->State == HAL_SRAM_STATE_READY)
2	mjames	404	{
9	mjames	405	/* Process Locked */
		406	__HAL_LOCK(hsram);
		407
		408	/* Update the SRAM controller state */
		409	hsram->State = HAL_SRAM_STATE_BUSY;
		410
		411	/* Write data to memory */
		412	for (size = BufferSize; size != 0U; size--)
		413	{
		414	psramaddress = psrcbuff;
		415	psrcbuff++;
		416	psramaddress++;
		417	}
		418
		419	/* Update the SRAM controller state */
		420	hsram->State = HAL_SRAM_STATE_READY;
		421
		422	/* Process unlocked */
		423	__HAL_UNLOCK(hsram);
2	mjames	424	}
9	mjames	425	else
2	mjames	426	{
9	mjames	427	return HAL_ERROR;
		428	}
2	mjames	429
9	mjames	430	return HAL_OK;
2	mjames	431	}
		432
		433	/**
9	mjames	434	* @brief Reads 16-bit buffer from SRAM memory.
		435	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	436	* the configuration information for SRAM module.
9	mjames	437	* @param pAddress Pointer to read start address
		438	* @param pDstBuffer Pointer to destination buffer
		439	* @param BufferSize Size of the buffer to read from memory
2	mjames	440	* @retval HAL status
		441	*/
9	mjames	442	HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint16_t *pDstBuffer,
		443	uint32_t BufferSize)
2	mjames	444	{
9	mjames	445	uint32_t size;
		446	__IO uint32_t *psramaddress = pAddress;
		447	uint16_t *pdestbuff = pDstBuffer;
		448	uint8_t limit;
		449	HAL_SRAM_StateTypeDef state = hsram->State;
		450
		451	/* Check the SRAM controller state */
		452	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_PROTECTED))
2	mjames	453	{
9	mjames	454	/* Process Locked */
		455	__HAL_LOCK(hsram);
		456
		457	/* Update the SRAM controller state */
		458	hsram->State = HAL_SRAM_STATE_BUSY;
		459
		460	/* Check if the size is a 32-bits multiple */
		461	limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
		462
		463	/* Read data from memory */
		464	for (size = BufferSize; size != limit; size -= 2U)
		465	{
		466	pdestbuff = (uint16_t)((psramaddress) & 0x0000FFFFU);
		467	pdestbuff++;
		468	pdestbuff = (uint16_t)(((psramaddress) & 0xFFFF0000U) >> 16U);
		469	pdestbuff++;
		470	psramaddress++;
		471	}
		472
		473	/* Read last 16-bits if size is not 32-bits multiple */
		474	if (limit != 0U)
		475	{
		476	pdestbuff = (uint16_t)((psramaddress) & 0x0000FFFFU);
		477	}
		478
		479	/* Update the SRAM controller state */
		480	hsram->State = state;
		481
		482	/* Process unlocked */
		483	__HAL_UNLOCK(hsram);
2	mjames	484	}
9	mjames	485	else
		486	{
		487	return HAL_ERROR;
		488	}
2	mjames	489
9	mjames	490	return HAL_OK;
2	mjames	491	}
		492
		493	/**
9	mjames	494	* @brief Writes 16-bit buffer to SRAM memory.
		495	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	496	* the configuration information for SRAM module.
9	mjames	497	* @param pAddress Pointer to write start address
		498	* @param pSrcBuffer Pointer to source buffer to write
		499	* @param BufferSize Size of the buffer to write to memory
2	mjames	500	* @retval HAL status
		501	*/
9	mjames	502	HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint16_t *pSrcBuffer,
		503	uint32_t BufferSize)
2	mjames	504	{
9	mjames	505	uint32_t size;
		506	__IO uint32_t *psramaddress = pAddress;
		507	uint16_t *psrcbuff = pSrcBuffer;
		508	uint8_t limit;
		509
2	mjames	510	/* Check the SRAM controller state */
9	mjames	511	if (hsram->State == HAL_SRAM_STATE_READY)
2	mjames	512	{
9	mjames	513	/* Process Locked */
		514	__HAL_LOCK(hsram);
		515
		516	/* Update the SRAM controller state */
		517	hsram->State = HAL_SRAM_STATE_BUSY;
		518
		519	/* Check if the size is a 32-bits multiple */
		520	limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
		521
		522	/* Write data to memory */
		523	for (size = BufferSize; size != limit; size -= 2U)
		524	{
		525	psramaddress = (uint32_t)(psrcbuff);
		526	psrcbuff++;
		527	psramaddress \|= ((uint32_t)(psrcbuff) << 16U);
		528	psrcbuff++;
		529	psramaddress++;
		530	}
		531
		532	/* Write last 16-bits if size is not 32-bits multiple */
		533	if (limit != 0U)
		534	{
		535	psramaddress = ((uint32_t)(psrcbuff) & 0x0000FFFFU) \| ((*psramaddress) & 0xFFFF0000U);
		536	}
		537
		538	/* Update the SRAM controller state */
		539	hsram->State = HAL_SRAM_STATE_READY;
		540
		541	/* Process unlocked */
		542	__HAL_UNLOCK(hsram);
2	mjames	543	}
9	mjames	544	else
2	mjames	545	{
9	mjames	546	return HAL_ERROR;
		547	}
2	mjames	548
9	mjames	549	return HAL_OK;
2	mjames	550	}
		551
		552	/**
9	mjames	553	* @brief Reads 32-bit buffer from SRAM memory.
		554	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	555	* the configuration information for SRAM module.
9	mjames	556	* @param pAddress Pointer to read start address
		557	* @param pDstBuffer Pointer to destination buffer
		558	* @param BufferSize Size of the buffer to read from memory
2	mjames	559	* @retval HAL status
		560	*/
9	mjames	561	HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pDstBuffer,
		562	uint32_t BufferSize)
2	mjames	563	{
9	mjames	564	uint32_t size;
		565	__IO uint32_t *psramaddress = pAddress;
		566	uint32_t *pdestbuff = pDstBuffer;
		567	HAL_SRAM_StateTypeDef state = hsram->State;
		568
		569	/* Check the SRAM controller state */
		570	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_PROTECTED))
2	mjames	571	{
9	mjames	572	/* Process Locked */
		573	__HAL_LOCK(hsram);
		574
		575	/* Update the SRAM controller state */
		576	hsram->State = HAL_SRAM_STATE_BUSY;
		577
		578	/* Read data from memory */
		579	for (size = BufferSize; size != 0U; size--)
		580	{
		581	pdestbuff = psramaddress;
		582	pdestbuff++;
		583	psramaddress++;
		584	}
		585
		586	/* Update the SRAM controller state */
		587	hsram->State = state;
		588
		589	/* Process unlocked */
		590	__HAL_UNLOCK(hsram);
2	mjames	591	}
9	mjames	592	else
		593	{
		594	return HAL_ERROR;
		595	}
2	mjames	596
9	mjames	597	return HAL_OK;
2	mjames	598	}
		599
		600	/**
9	mjames	601	* @brief Writes 32-bit buffer to SRAM memory.
		602	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	603	* the configuration information for SRAM module.
9	mjames	604	* @param pAddress Pointer to write start address
		605	* @param pSrcBuffer Pointer to source buffer to write
		606	* @param BufferSize Size of the buffer to write to memory
2	mjames	607	* @retval HAL status
		608	*/
9	mjames	609	HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pSrcBuffer,
		610	uint32_t BufferSize)
2	mjames	611	{
9	mjames	612	uint32_t size;
		613	__IO uint32_t *psramaddress = pAddress;
		614	uint32_t *psrcbuff = pSrcBuffer;
		615
2	mjames	616	/* Check the SRAM controller state */
9	mjames	617	if (hsram->State == HAL_SRAM_STATE_READY)
2	mjames	618	{
9	mjames	619	/* Process Locked */
		620	__HAL_LOCK(hsram);
		621
		622	/* Update the SRAM controller state */
		623	hsram->State = HAL_SRAM_STATE_BUSY;
		624
		625	/* Write data to memory */
		626	for (size = BufferSize; size != 0U; size--)
		627	{
		628	psramaddress = psrcbuff;
		629	psrcbuff++;
		630	psramaddress++;
		631	}
		632
		633	/* Update the SRAM controller state */
		634	hsram->State = HAL_SRAM_STATE_READY;
		635
		636	/* Process unlocked */
		637	__HAL_UNLOCK(hsram);
2	mjames	638	}
9	mjames	639	else
2	mjames	640	{
9	mjames	641	return HAL_ERROR;
		642	}
2	mjames	643
9	mjames	644	return HAL_OK;
2	mjames	645	}
		646
		647	/**
		648	* @brief Reads a Words data from the SRAM memory using DMA transfer.
9	mjames	649	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	650	* the configuration information for SRAM module.
9	mjames	651	* @param pAddress Pointer to read start address
		652	* @param pDstBuffer Pointer to destination buffer
		653	* @param BufferSize Size of the buffer to read from memory
2	mjames	654	* @retval HAL status
		655	*/
9	mjames	656	HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pDstBuffer,
		657	uint32_t BufferSize)
2	mjames	658	{
9	mjames	659	HAL_StatusTypeDef status;
		660	HAL_SRAM_StateTypeDef state = hsram->State;
2	mjames	661
9	mjames	662	/* Check the SRAM controller state */
		663	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_PROTECTED))
		664	{
		665	/* Process Locked */
		666	__HAL_LOCK(hsram);
		667
		668	/* Update the SRAM controller state */
		669	hsram->State = HAL_SRAM_STATE_BUSY;
		670
		671	/* Configure DMA user callbacks */
		672	if (state == HAL_SRAM_STATE_READY)
		673	{
		674	hsram->hdma->XferCpltCallback = SRAM_DMACplt;
		675	}
		676	else
		677	{
		678	hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
		679	}
		680	hsram->hdma->XferErrorCallback = SRAM_DMAError;
		681
		682	/* Enable the DMA Stream */
		683	status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
		684
		685	/* Process unlocked */
		686	__HAL_UNLOCK(hsram);
		687	}
		688	else
		689	{
		690	status = HAL_ERROR;
		691	}
		692
		693	return status;
2	mjames	694	}
		695
		696	/**
		697	* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
9	mjames	698	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	699	* the configuration information for SRAM module.
9	mjames	700	* @param pAddress Pointer to write start address
		701	* @param pSrcBuffer Pointer to source buffer to write
		702	* @param BufferSize Size of the buffer to write to memory
2	mjames	703	* @retval HAL status
		704	*/
9	mjames	705	HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pSrcBuffer,
		706	uint32_t BufferSize)
2	mjames	707	{
9	mjames	708	HAL_StatusTypeDef status;
		709
2	mjames	710	/* Check the SRAM controller state */
9	mjames	711	if (hsram->State == HAL_SRAM_STATE_READY)
2	mjames	712	{
9	mjames	713	/* Process Locked */
		714	__HAL_LOCK(hsram);
		715
		716	/* Update the SRAM controller state */
		717	hsram->State = HAL_SRAM_STATE_BUSY;
		718
		719	/* Configure DMA user callbacks */
		720	hsram->hdma->XferCpltCallback = SRAM_DMACplt;
		721	hsram->hdma->XferErrorCallback = SRAM_DMAError;
		722
		723	/* Enable the DMA Stream */
		724	status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
		725
		726	/* Process unlocked */
		727	__HAL_UNLOCK(hsram);
2	mjames	728	}
9	mjames	729	else
		730	{
		731	status = HAL_ERROR;
		732	}
		733
		734	return status;
		735	}
		736
		737	#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
		738	/**
		739	* @brief Register a User SRAM Callback
		740	* To be used instead of the weak (surcharged) predefined callback
		741	* @param hsram : SRAM handle
		742	* @param CallbackId : ID of the callback to be registered
		743	* This parameter can be one of the following values:
		744	* @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
		745	* @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
		746	* @param pCallback : pointer to the Callback function
		747	* @retval status
		748	*/
		749	HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
		750	pSRAM_CallbackTypeDef pCallback)
		751	{
		752	HAL_StatusTypeDef status = HAL_OK;
		753	HAL_SRAM_StateTypeDef state;
		754
		755	if (pCallback == NULL)
		756	{
		757	return HAL_ERROR;
		758	}
		759
		760	/* Process locked */
2	mjames	761	__HAL_LOCK(hsram);
		762
9	mjames	763	state = hsram->State;
		764	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_RESET) \|\| (state == HAL_SRAM_STATE_PROTECTED))
		765	{
		766	switch (CallbackId)
		767	{
		768	case HAL_SRAM_MSP_INIT_CB_ID :
		769	hsram->MspInitCallback = pCallback;
		770	break;
		771	case HAL_SRAM_MSP_DEINIT_CB_ID :
		772	hsram->MspDeInitCallback = pCallback;
		773	break;
		774	default :
		775	/* update return status */
		776	status = HAL_ERROR;
		777	break;
		778	}
		779	}
		780	else
		781	{
		782	/* update return status */
		783	status = HAL_ERROR;
		784	}
		785
		786	/* Release Lock */
		787	__HAL_UNLOCK(hsram);
		788	return status;
2	mjames	789	}
		790
		791	/**
9	mjames	792	* @brief Unregister a User SRAM Callback
		793	* SRAM Callback is redirected to the weak (surcharged) predefined callback
		794	* @param hsram : SRAM handle
		795	* @param CallbackId : ID of the callback to be unregistered
		796	* This parameter can be one of the following values:
		797	* @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
		798	* @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
		799	* @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
		800	* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
		801	* @retval status
		802	*/
		803	HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
		804	{
		805	HAL_StatusTypeDef status = HAL_OK;
		806	HAL_SRAM_StateTypeDef state;
		807
		808	/* Process locked */
		809	__HAL_LOCK(hsram);
		810
		811	state = hsram->State;
		812	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_PROTECTED))
		813	{
		814	switch (CallbackId)
		815	{
		816	case HAL_SRAM_MSP_INIT_CB_ID :
		817	hsram->MspInitCallback = HAL_SRAM_MspInit;
		818	break;
		819	case HAL_SRAM_MSP_DEINIT_CB_ID :
		820	hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
		821	break;
		822	case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
		823	hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
		824	break;
		825	case HAL_SRAM_DMA_XFER_ERR_CB_ID :
		826	hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
		827	break;
		828	default :
		829	/* update return status */
		830	status = HAL_ERROR;
		831	break;
		832	}
		833	}
		834	else if (state == HAL_SRAM_STATE_RESET)
		835	{
		836	switch (CallbackId)
		837	{
		838	case HAL_SRAM_MSP_INIT_CB_ID :
		839	hsram->MspInitCallback = HAL_SRAM_MspInit;
		840	break;
		841	case HAL_SRAM_MSP_DEINIT_CB_ID :
		842	hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
		843	break;
		844	default :
		845	/* update return status */
		846	status = HAL_ERROR;
		847	break;
		848	}
		849	}
		850	else
		851	{
		852	/* update return status */
		853	status = HAL_ERROR;
		854	}
		855
		856	/* Release Lock */
		857	__HAL_UNLOCK(hsram);
		858	return status;
		859	}
		860
		861	/**
		862	* @brief Register a User SRAM Callback for DMA transfers
		863	* To be used instead of the weak (surcharged) predefined callback
		864	* @param hsram : SRAM handle
		865	* @param CallbackId : ID of the callback to be registered
		866	* This parameter can be one of the following values:
		867	* @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
		868	* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
		869	* @param pCallback : pointer to the Callback function
		870	* @retval status
		871	*/
		872	HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
		873	pSRAM_DmaCallbackTypeDef pCallback)
		874	{
		875	HAL_StatusTypeDef status = HAL_OK;
		876	HAL_SRAM_StateTypeDef state;
		877
		878	if (pCallback == NULL)
		879	{
		880	return HAL_ERROR;
		881	}
		882
		883	/* Process locked */
		884	__HAL_LOCK(hsram);
		885
		886	state = hsram->State;
		887	if ((state == HAL_SRAM_STATE_READY) \|\| (state == HAL_SRAM_STATE_PROTECTED))
		888	{
		889	switch (CallbackId)
		890	{
		891	case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
		892	hsram->DmaXferCpltCallback = pCallback;
		893	break;
		894	case HAL_SRAM_DMA_XFER_ERR_CB_ID :
		895	hsram->DmaXferErrorCallback = pCallback;
		896	break;
		897	default :
		898	/* update return status */
		899	status = HAL_ERROR;
		900	break;
		901	}
		902	}
		903	else
		904	{
		905	/* update return status */
		906	status = HAL_ERROR;
		907	}
		908
		909	/* Release Lock */
		910	__HAL_UNLOCK(hsram);
		911	return status;
		912	}
		913	#endif
		914
		915	/**
2	mjames	916	* @}
		917	*/
9	mjames	918
		919	/** @defgroup SRAM_Exported_Functions_Group3 Control functions
		920	* @brief Control functions
		921	*
		922	@verbatim
2	mjames	923	==============================================================================
		924	##### SRAM Control functions #####
9	mjames	925	==============================================================================
2	mjames	926	[..]
		927	This subsection provides a set of functions allowing to control dynamically
		928	the SRAM interface.
		929
		930	@endverbatim
		931	* @{
		932	*/
9	mjames	933
2	mjames	934	/**
		935	* @brief Enables dynamically SRAM write operation.
9	mjames	936	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	937	* the configuration information for SRAM module.
		938	* @retval HAL status
		939	*/
		940	HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
		941	{
9	mjames	942	/* Check the SRAM controller state */
		943	if (hsram->State == HAL_SRAM_STATE_PROTECTED)
		944	{
		945	/* Process Locked */
		946	__HAL_LOCK(hsram);
2	mjames	947
9	mjames	948	/* Update the SRAM controller state */
		949	hsram->State = HAL_SRAM_STATE_BUSY;
		950
		951	/* Enable write operation */
		952	(void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
		953
		954	/* Update the SRAM controller state */
		955	hsram->State = HAL_SRAM_STATE_READY;
		956
		957	/* Process unlocked */
		958	__HAL_UNLOCK(hsram);
		959	}
		960	else
		961	{
		962	return HAL_ERROR;
		963	}
		964
		965	return HAL_OK;
2	mjames	966	}
		967
		968	/**
		969	* @brief Disables dynamically SRAM write operation.
9	mjames	970	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	971	* the configuration information for SRAM module.
		972	* @retval HAL status
		973	*/
		974	HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
		975	{
9	mjames	976	/* Check the SRAM controller state */
		977	if (hsram->State == HAL_SRAM_STATE_READY)
		978	{
		979	/* Process Locked */
		980	__HAL_LOCK(hsram);
2	mjames	981
9	mjames	982	/* Update the SRAM controller state */
		983	hsram->State = HAL_SRAM_STATE_BUSY;
		984
		985	/* Disable write operation */
		986	(void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
		987
		988	/* Update the SRAM controller state */
		989	hsram->State = HAL_SRAM_STATE_PROTECTED;
		990
		991	/* Process unlocked */
		992	__HAL_UNLOCK(hsram);
		993	}
		994	else
		995	{
		996	return HAL_ERROR;
		997	}
		998
		999	return HAL_OK;
2	mjames	1000	}
		1001
		1002	/**
		1003	* @}
		1004	*/
		1005
9	mjames	1006	/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
		1007	* @brief Peripheral State functions
		1008	*
		1009	@verbatim
2	mjames	1010	==============================================================================
		1011	##### SRAM State functions #####
9	mjames	1012	==============================================================================
2	mjames	1013	[..]
9	mjames	1014	This subsection permits to get in run-time the status of the SRAM controller
2	mjames	1015	and the data flow.
		1016
		1017	@endverbatim
		1018	* @{
		1019	*/
9	mjames	1020
2	mjames	1021	/**
		1022	* @brief Returns the SRAM controller state
9	mjames	1023	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
2	mjames	1024	* the configuration information for SRAM module.
		1025	* @retval HAL state
		1026	*/
		1027	HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
		1028	{
		1029	return hsram->State;
		1030	}
		1031
		1032	/**
		1033	* @}
		1034	*/
		1035
		1036	/**
		1037	* @}
		1038	*/
		1039
		1040	/**
9	mjames	1041	@cond 0
		1042	*/
		1043	/**
		1044	* @brief DMA SRAM process complete callback.
		1045	* @param hdma : DMA handle
		1046	* @retval None
		1047	*/
		1048	static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
		1049	{
		1050	SRAM_HandleTypeDef hsram = (SRAM_HandleTypeDef )(hdma->Parent);
		1051
		1052	/* Disable the DMA channel */
		1053	__HAL_DMA_DISABLE(hdma);
		1054
		1055	/* Update the SRAM controller state */
		1056	hsram->State = HAL_SRAM_STATE_READY;
		1057
		1058	#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
		1059	hsram->DmaXferCpltCallback(hdma);
		1060	#else
		1061	HAL_SRAM_DMA_XferCpltCallback(hdma);
		1062	#endif
		1063	}
		1064
		1065	/**
		1066	* @brief DMA SRAM process complete callback.
		1067	* @param hdma : DMA handle
		1068	* @retval None
		1069	*/
		1070	static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
		1071	{
		1072	SRAM_HandleTypeDef hsram = (SRAM_HandleTypeDef )(hdma->Parent);
		1073
		1074	/* Disable the DMA channel */
		1075	__HAL_DMA_DISABLE(hdma);
		1076
		1077	/* Update the SRAM controller state */
		1078	hsram->State = HAL_SRAM_STATE_PROTECTED;
		1079
		1080	#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
		1081	hsram->DmaXferCpltCallback(hdma);
		1082	#else
		1083	HAL_SRAM_DMA_XferCpltCallback(hdma);
		1084	#endif
		1085	}
		1086
		1087	/**
		1088	* @brief DMA SRAM error callback.
		1089	* @param hdma : DMA handle
		1090	* @retval None
		1091	*/
		1092	static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
		1093	{
		1094	SRAM_HandleTypeDef hsram = (SRAM_HandleTypeDef )(hdma->Parent);
		1095
		1096	/* Disable the DMA channel */
		1097	__HAL_DMA_DISABLE(hdma);
		1098
		1099	/* Update the SRAM controller state */
		1100	hsram->State = HAL_SRAM_STATE_ERROR;
		1101
		1102	#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
		1103	hsram->DmaXferErrorCallback(hdma);
		1104	#else
		1105	HAL_SRAM_DMA_XferErrorCallback(hdma);
		1106	#endif
		1107	}
		1108	/**
		1109	@endcond
		1110	*/
		1111
		1112	/**
2	mjames	1113	* @}
		1114	*/
9	mjames	1115
2	mjames	1116	#endif /* HAL_SRAM_MODULE_ENABLED */
		1117
		1118	/**
		1119	* @}
		1120	*/
		1121
9	mjames	1122	#endif /* FSMC_BANK1 */
		1123
2	mjames	1124	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c – Rev 9