WebSVN – dashGPS – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_spi.c
		4	* @author MCD Application Team
		5	* @brief SPI HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
		8	* + Initialization and de-initialization functions
		9	* + IO operation functions
		10	* + Peripheral Control functions
		11	* + Peripheral State functions
		12	*
		13	@verbatim
		14	==============================================================================
		15	##### How to use this driver #####
		16	==============================================================================
		17	[..]
		18	The SPI HAL driver can be used as follows:
		19
		20	(#) Declare a SPI_HandleTypeDef handle structure, for example:
		21	SPI_HandleTypeDef hspi;
		22
		23	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
		24	(##) Enable the SPIx interface clock
		25	(##) SPI pins configuration
		26	(+++) Enable the clock for the SPI GPIOs
		27	(+++) Configure these SPI pins as alternate function push-pull
		28	(##) NVIC configuration if you need to use interrupt process
		29	(+++) Configure the SPIx interrupt priority
		30	(+++) Enable the NVIC SPI IRQ handle
		31	(##) DMA Configuration if you need to use DMA process
		32	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
		33	(+++) Enable the DMAx clock
		34	(+++) Configure the DMA handle parameters
		35	(+++) Configure the DMA Tx or Rx Stream/Channel
		36	(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
		37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
		38
		39	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
		40	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
		41
		42	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
		43	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
		44	by calling the customized HAL_SPI_MspInit() API.
		45	[..]
		46	Circular mode restriction:
		47	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
		48	(##) Master 2Lines RxOnly
		49	(##) Master 1Line Rx
		50	(#) The CRC feature is not managed when the DMA circular mode is enabled
		51	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
		52	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
		53	[..]
		54	Master Receive mode restriction:
		55	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
		56	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
		57	does not initiate a new transfer the following procedure has to be respected:
		58	(##) HAL_SPI_DeInit()
		59	(##) HAL_SPI_Init()
		60	[..]
		61	Callback registration:
		62
		63	(#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
		64	allows the user to configure dynamically the driver callbacks.
		65	Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
		66
		67	Function HAL_SPI_RegisterCallback() allows to register following callbacks:
		68	(++) TxCpltCallback : SPI Tx Completed callback
		69	(++) RxCpltCallback : SPI Rx Completed callback
		70	(++) TxRxCpltCallback : SPI TxRx Completed callback
		71	(++) TxHalfCpltCallback : SPI Tx Half Completed callback
		72	(++) RxHalfCpltCallback : SPI Rx Half Completed callback
		73	(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
		74	(++) ErrorCallback : SPI Error callback
		75	(++) AbortCpltCallback : SPI Abort callback
		76	(++) MspInitCallback : SPI Msp Init callback
		77	(++) MspDeInitCallback : SPI Msp DeInit callback
		78	This function takes as parameters the HAL peripheral handle, the Callback ID
		79	and a pointer to the user callback function.
		80
		81
		82	(#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
		83	weak function.
		84	HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
		85	and the Callback ID.
		86	This function allows to reset following callbacks:
		87	(++) TxCpltCallback : SPI Tx Completed callback
		88	(++) RxCpltCallback : SPI Rx Completed callback
		89	(++) TxRxCpltCallback : SPI TxRx Completed callback
		90	(++) TxHalfCpltCallback : SPI Tx Half Completed callback
		91	(++) RxHalfCpltCallback : SPI Rx Half Completed callback
		92	(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
		93	(++) ErrorCallback : SPI Error callback
		94	(++) AbortCpltCallback : SPI Abort callback
		95	(++) MspInitCallback : SPI Msp Init callback
		96	(++) MspDeInitCallback : SPI Msp DeInit callback
		97
		98	[..]
		99	By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
		100	all callbacks are set to the corresponding weak functions:
		101	examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
		102	Exception done for MspInit and MspDeInit functions that are
		103	reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
		104	these callbacks are null (not registered beforehand).
		105	If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
		106	keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
		107
		108	[..]
		109	Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
		110	Exception done MspInit/MspDeInit functions that can be registered/unregistered
		111	in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
		112	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
		113	Then, the user first registers the MspInit/MspDeInit user callbacks
		114	using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
		115	or HAL_SPI_Init() function.
		116
		117	[..]
		118	When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
		119	not defined, the callback registering feature is not available
		120	and weak (surcharged) callbacks are used.
		121
		122	[..]
		123	Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
		124	the following table resume the max SPI frequency reached with data size 8bits/16bits,
		125	according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
		126
		127	@endverbatim
		128
		129	Additional table :
		130
		131	DataSize = SPI_DATASIZE_8BIT:
		132	+----------------------------------------------------------------------------------------------+
		133	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		134	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
		135	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		136	\|==============================================================================================\|
		137	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		138	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		139	\| / \| Interrupt \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
		140	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		141	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		142	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		143	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
		144	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		145	\| R \| Interrupt \| Fpclk/8 \| Fpclk/8 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
		146	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		147	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
		148	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		149	\| \| Polling \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
		150	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		151	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
		152	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		153	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
		154	+----------------------------------------------------------------------------------------------+
		155
		156	DataSize = SPI_DATASIZE_16BIT:
		157	+----------------------------------------------------------------------------------------------+
		158	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		159	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
		160	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		161	\|==============================================================================================\|
		162	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		163	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		164	\| / \| Interrupt \| Fpclk/4 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
		165	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		166	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		167	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		168	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/32 \| Fpclk/2 \|
		169	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		170	\| R \| Interrupt \| Fpclk/4 \| Fpclk/4 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
		171	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		172	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
		173	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		174	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/32 \|
		175	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		176	\| T \| Interrupt \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
		177	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		178	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
		179	+----------------------------------------------------------------------------------------------+
		180	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
		181	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
		182	@note
		183	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
		184	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
		185	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
		186
		187	******************************************************************************
		188	* @attention
		189	*
		190	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		191	* All rights reserved.</center></h2>
		192	*
		193	* This software component is licensed by ST under BSD 3-Clause license,
		194	* the "License"; You may not use this file except in compliance with the
		195	* License. You may obtain a copy of the License at:
		196	* opensource.org/licenses/BSD-3-Clause
		197	*
		198	******************************************************************************
		199	*/
		200
		201	/* Includes ------------------------------------------------------------------*/
		202	#include "stm32f1xx_hal.h"
		203
		204	/** @addtogroup STM32F1xx_HAL_Driver
		205	* @{
		206	*/
		207
		208	/** @defgroup SPI SPI
		209	* @brief SPI HAL module driver
		210	* @{
		211	*/
		212	#ifdef HAL_SPI_MODULE_ENABLED
		213
		214	/* Private typedef -----------------------------------------------------------*/
		215	/* Private defines -----------------------------------------------------------*/
		216	#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE)
		217	/* CRC WORKAOUND FEATURE: Variable used to determine if device is impacted by implementation
		218	* of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround
		219	* has to be applied, are:
		220	* - STM32F101CDE/STM32F103CDE
		221	* - Revision ID : Z
		222	* - SPI2
		223	* - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
		224	* the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
		225	* + If the value is 0, the complete data transfer is successful.
		226	* + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
		227	* If CRCERR is found reset, the complete data transfer is considered successful.
		228	*
		229	* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
		230	* CRC errors wrongly detected
		231	*/
		232	/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode
		233	* Revision ID information is only available in Debug mode, so Workaround could not be implemented
		234	* to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
		235	* So, in case of Revison Z F101 or F103 devices, below define should be assigned to 1.
		236	*/
		237	#define USE_SPI_CRC_ERROR_WORKAROUND 0U
		238	#endif
		239	/** @defgroup SPI_Private_Constants SPI Private Constants
		240	* @{
		241	*/
		242	#define SPI_DEFAULT_TIMEOUT 100U
		243	/**
		244	* @}
		245	*/
		246
		247	/* Private macros ------------------------------------------------------------*/
		248	/* Private variables ---------------------------------------------------------*/
		249	/* Private function prototypes -----------------------------------------------*/
		250	/** @defgroup SPI_Private_Functions SPI Private Functions
		251	* @{
		252	*/
		253	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
		254	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
		255	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		256	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
		257	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
		258	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		259	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
		260	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
		261	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
		262	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
		263	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
		264	uint32_t Timeout, uint32_t Tickstart);
		265	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		266	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		267	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		268	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		269	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		270	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		271	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		272	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		273	#if (USE_SPI_CRC != 0U)
		274	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		275	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		276	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		277	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		278	#endif /* USE_SPI_CRC */
		279	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
		280	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
		281	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
		282	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
		283	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
		284	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		285	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		286	/**
		287	* @}
		288	*/
		289
		290	/* Exported functions --------------------------------------------------------*/
		291	/** @defgroup SPI_Exported_Functions SPI Exported Functions
		292	* @{
		293	*/
		294
		295	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
		296	* @brief Initialization and Configuration functions
		297	*
		298	@verbatim
		299	===============================================================================
		300	##### Initialization and de-initialization functions #####
		301	===============================================================================
		302	[..] This subsection provides a set of functions allowing to initialize and
		303	de-initialize the SPIx peripheral:
		304
		305	(+) User must implement HAL_SPI_MspInit() function in which he configures
		306	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
		307
		308	(+) Call the function HAL_SPI_Init() to configure the selected device with
		309	the selected configuration:
		310	(++) Mode
		311	(++) Direction
		312	(++) Data Size
		313	(++) Clock Polarity and Phase
		314	(++) NSS Management
		315	(++) BaudRate Prescaler
		316	(++) FirstBit
		317	(++) TIMode
		318	(++) CRC Calculation
		319	(++) CRC Polynomial if CRC enabled
		320
		321	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
		322	of the selected SPIx peripheral.
		323
		324	@endverbatim
		325	* @{
		326	*/
		327
		328	/**
		329	* @brief Initialize the SPI according to the specified parameters
		330	* in the SPI_InitTypeDef and initialize the associated handle.
		331	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		332	* the configuration information for SPI module.
		333	* @retval HAL status
		334	*/
		335	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
		336	{
		337	/* Check the SPI handle allocation */
		338	if (hspi == NULL)
		339	{
		340	return HAL_ERROR;
		341	}
		342
		343	/* Check the parameters */
		344	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		345	assert_param(IS_SPI_MODE(hspi->Init.Mode));
		346	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
		347	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
		348	assert_param(IS_SPI_NSS(hspi->Init.NSS));
		349	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
		350	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
		351	/* TI mode is not supported on this device.
		352	TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
		353	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
		354	if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
		355	{
		356	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
		357	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
		358	}
		359	#if (USE_SPI_CRC != 0U)
		360	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
		361	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		362	{
		363	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
		364	}
		365	#else
		366	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
		367	#endif /* USE_SPI_CRC */
		368
		369	if (hspi->State == HAL_SPI_STATE_RESET)
		370	{
		371	/* Allocate lock resource and initialize it */
		372	hspi->Lock = HAL_UNLOCKED;
		373
		374	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		375	/* Init the SPI Callback settings */
		376	hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
		377	hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
		378	hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
		379	hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
		380	hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
		381	hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
		382	hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
		383	hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
		384
		385	if (hspi->MspInitCallback == NULL)
		386	{
		387	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		388	}
		389
		390	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		391	hspi->MspInitCallback(hspi);
		392	#else
		393	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		394	HAL_SPI_MspInit(hspi);
		395	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		396	}
		397
		398	hspi->State = HAL_SPI_STATE_BUSY;
		399
		400	/* Disable the selected SPI peripheral */
		401	__HAL_SPI_DISABLE(hspi);
		402
		403	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
		404	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
		405	Communication speed, First bit and CRC calculation state */
		406	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
		407	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
		408	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation));
		409
		410	/* Configure : NSS management */
		411	WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
		412
		413	#if (USE_SPI_CRC != 0U)
		414	/---------------------------- SPIx CRCPOLY Configuration ------------------/
		415	/* Configure : CRC Polynomial */
		416	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		417	{
		418	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
		419	}
		420	#endif /* USE_SPI_CRC */
		421
		422	#if defined(SPI_I2SCFGR_I2SMOD)
		423	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
		424	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
		425	#endif /* SPI_I2SCFGR_I2SMOD */
		426
		427	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		428	hspi->State = HAL_SPI_STATE_READY;
		429
		430	return HAL_OK;
		431	}
		432
		433	/**
		434	* @brief De-Initialize the SPI peripheral.
		435	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		436	* the configuration information for SPI module.
		437	* @retval HAL status
		438	*/
		439	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
		440	{
		441	/* Check the SPI handle allocation */
		442	if (hspi == NULL)
		443	{
		444	return HAL_ERROR;
		445	}
		446
		447	/* Check SPI Instance parameter */
		448	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		449
		450	hspi->State = HAL_SPI_STATE_BUSY;
		451
		452	/* Disable the SPI Peripheral Clock */
		453	__HAL_SPI_DISABLE(hspi);
		454
		455	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		456	if (hspi->MspDeInitCallback == NULL)
		457	{
		458	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		459	}
		460
		461	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		462	hspi->MspDeInitCallback(hspi);
		463	#else
		464	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		465	HAL_SPI_MspDeInit(hspi);
		466	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		467
		468	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		469	hspi->State = HAL_SPI_STATE_RESET;
		470
		471	/* Release Lock */
		472	__HAL_UNLOCK(hspi);
		473
		474	return HAL_OK;
		475	}
		476
		477	/**
		478	* @brief Initialize the SPI MSP.
		479	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		480	* the configuration information for SPI module.
		481	* @retval None
		482	*/
		483	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
		484	{
		485	/* Prevent unused argument(s) compilation warning */
		486	UNUSED(hspi);
		487
		488	/* NOTE : This function should not be modified, when the callback is needed,
		489	the HAL_SPI_MspInit should be implemented in the user file
		490	*/
		491	}
		492
		493	/**
		494	* @brief De-Initialize the SPI MSP.
		495	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		496	* the configuration information for SPI module.
		497	* @retval None
		498	*/
		499	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
		500	{
		501	/* Prevent unused argument(s) compilation warning */
		502	UNUSED(hspi);
		503
		504	/* NOTE : This function should not be modified, when the callback is needed,
		505	the HAL_SPI_MspDeInit should be implemented in the user file
		506	*/
		507	}
		508
		509	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		510	/**
		511	* @brief Register a User SPI Callback
		512	* To be used instead of the weak predefined callback
		513	* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
		514	* the configuration information for the specified SPI.
		515	* @param CallbackID ID of the callback to be registered
		516	* @param pCallback pointer to the Callback function
		517	* @retval HAL status
		518	*/
		519	HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
		520	pSPI_CallbackTypeDef pCallback)
		521	{
		522	HAL_StatusTypeDef status = HAL_OK;
		523
		524	if (pCallback == NULL)
		525	{
		526	/* Update the error code */
		527	hspi->ErrorCode \|= HAL_SPI_ERROR_INVALID_CALLBACK;
		528
		529	return HAL_ERROR;
		530	}
		531	/* Process locked */
		532	__HAL_LOCK(hspi);
		533
		534	if (HAL_SPI_STATE_READY == hspi->State)
		535	{
		536	switch (CallbackID)
		537	{
		538	case HAL_SPI_TX_COMPLETE_CB_ID :
		539	hspi->TxCpltCallback = pCallback;
		540	break;
		541
		542	case HAL_SPI_RX_COMPLETE_CB_ID :
		543	hspi->RxCpltCallback = pCallback;
		544	break;
		545
		546	case HAL_SPI_TX_RX_COMPLETE_CB_ID :
		547	hspi->TxRxCpltCallback = pCallback;
		548	break;
		549
		550	case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
		551	hspi->TxHalfCpltCallback = pCallback;
		552	break;
		553
		554	case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
		555	hspi->RxHalfCpltCallback = pCallback;
		556	break;
		557
		558	case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
		559	hspi->TxRxHalfCpltCallback = pCallback;
		560	break;
		561
		562	case HAL_SPI_ERROR_CB_ID :
		563	hspi->ErrorCallback = pCallback;
		564	break;
		565
		566	case HAL_SPI_ABORT_CB_ID :
		567	hspi->AbortCpltCallback = pCallback;
		568	break;
		569
		570	case HAL_SPI_MSPINIT_CB_ID :
		571	hspi->MspInitCallback = pCallback;
		572	break;
		573
		574	case HAL_SPI_MSPDEINIT_CB_ID :
		575	hspi->MspDeInitCallback = pCallback;
		576	break;
		577
		578	default :
		579	/* Update the error code */
		580	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		581
		582	/* Return error status */
		583	status = HAL_ERROR;
		584	break;
		585	}
		586	}
		587	else if (HAL_SPI_STATE_RESET == hspi->State)
		588	{
		589	switch (CallbackID)
		590	{
		591	case HAL_SPI_MSPINIT_CB_ID :
		592	hspi->MspInitCallback = pCallback;
		593	break;
		594
		595	case HAL_SPI_MSPDEINIT_CB_ID :
		596	hspi->MspDeInitCallback = pCallback;
		597	break;
		598
		599	default :
		600	/* Update the error code */
		601	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		602
		603	/* Return error status */
		604	status = HAL_ERROR;
		605	break;
		606	}
		607	}
		608	else
		609	{
		610	/* Update the error code */
		611	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		612
		613	/* Return error status */
		614	status = HAL_ERROR;
		615	}
		616
		617	/* Release Lock */
		618	__HAL_UNLOCK(hspi);
		619	return status;
		620	}
		621
		622	/**
		623	* @brief Unregister an SPI Callback
		624	* SPI callback is redirected to the weak predefined callback
		625	* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
		626	* the configuration information for the specified SPI.
		627	* @param CallbackID ID of the callback to be unregistered
		628	* @retval HAL status
		629	*/
		630	HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
		631	{
		632	HAL_StatusTypeDef status = HAL_OK;
		633
		634	/* Process locked */
		635	__HAL_LOCK(hspi);
		636
		637	if (HAL_SPI_STATE_READY == hspi->State)
		638	{
		639	switch (CallbackID)
		640	{
		641	case HAL_SPI_TX_COMPLETE_CB_ID :
		642	hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
		643	break;
		644
		645	case HAL_SPI_RX_COMPLETE_CB_ID :
		646	hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
		647	break;
		648
		649	case HAL_SPI_TX_RX_COMPLETE_CB_ID :
		650	hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
		651	break;
		652
		653	case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
		654	hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
		655	break;
		656
		657	case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
		658	hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
		659	break;
		660
		661	case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
		662	hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
		663	break;
		664
		665	case HAL_SPI_ERROR_CB_ID :
		666	hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
		667	break;
		668
		669	case HAL_SPI_ABORT_CB_ID :
		670	hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
		671	break;
		672
		673	case HAL_SPI_MSPINIT_CB_ID :
		674	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		675	break;
		676
		677	case HAL_SPI_MSPDEINIT_CB_ID :
		678	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		679	break;
		680
		681	default :
		682	/* Update the error code */
		683	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		684
		685	/* Return error status */
		686	status = HAL_ERROR;
		687	break;
		688	}
		689	}
		690	else if (HAL_SPI_STATE_RESET == hspi->State)
		691	{
		692	switch (CallbackID)
		693	{
		694	case HAL_SPI_MSPINIT_CB_ID :
		695	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		696	break;
		697
		698	case HAL_SPI_MSPDEINIT_CB_ID :
		699	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		700	break;
		701
		702	default :
		703	/* Update the error code */
		704	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		705
		706	/* Return error status */
		707	status = HAL_ERROR;
		708	break;
		709	}
		710	}
		711	else
		712	{
		713	/* Update the error code */
		714	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		715
		716	/* Return error status */
		717	status = HAL_ERROR;
		718	}
		719
		720	/* Release Lock */
		721	__HAL_UNLOCK(hspi);
		722	return status;
		723	}
		724	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		725	/**
		726	* @}
		727	*/
		728
		729	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
		730	* @brief Data transfers functions
		731	*
		732	@verbatim
		733	==============================================================================
		734	##### IO operation functions #####
		735	===============================================================================
		736	[..]
		737	This subsection provides a set of functions allowing to manage the SPI
		738	data transfers.
		739
		740	[..] The SPI supports master and slave mode :
		741
		742	(#) There are two modes of transfer:
		743	(++) Blocking mode: The communication is performed in polling mode.
		744	The HAL status of all data processing is returned by the same function
		745	after finishing transfer.
		746	(++) No-Blocking mode: The communication is performed using Interrupts
		747	or DMA, These APIs return the HAL status.
		748	The end of the data processing will be indicated through the
		749	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
		750	using DMA mode.
		751	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
		752	will be executed respectively at the end of the transmit or Receive process
		753	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
		754
		755	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
		756	exist for 1Line (simplex) and 2Lines (full duplex) modes.
		757
		758	@endverbatim
		759	* @{
		760	*/
		761
		762	/**
		763	* @brief Transmit an amount of data in blocking mode.
		764	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		765	* the configuration information for SPI module.
		766	* @param pData pointer to data buffer
		767	* @param Size amount of data to be sent
		768	* @param Timeout Timeout duration
		769	* @retval HAL status
		770	*/
		771	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		772	{
		773	uint32_t tickstart;
		774	HAL_StatusTypeDef errorcode = HAL_OK;
		775	uint16_t initial_TxXferCount;
		776
		777	/* Check Direction parameter */
		778	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		779
		780	/* Process Locked */
		781	__HAL_LOCK(hspi);
		782
		783	/* Init tickstart for timeout management*/
		784	tickstart = HAL_GetTick();
		785	initial_TxXferCount = Size;
		786
		787	if (hspi->State != HAL_SPI_STATE_READY)
		788	{
		789	errorcode = HAL_BUSY;
		790	goto error;
		791	}
		792
		793	if ((pData == NULL) \|\| (Size == 0U))
		794	{
		795	errorcode = HAL_ERROR;
		796	goto error;
		797	}
		798
		799	/* Set the transaction information */
		800	hspi->State = HAL_SPI_STATE_BUSY_TX;
		801	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		802	hspi->pTxBuffPtr = (uint8_t *)pData;
		803	hspi->TxXferSize = Size;
		804	hspi->TxXferCount = Size;
		805
		806	/Init field not used in handle to zero /
		807	hspi->pRxBuffPtr = (uint8_t *)NULL;
		808	hspi->RxXferSize = 0U;
		809	hspi->RxXferCount = 0U;
		810	hspi->TxISR = NULL;
		811	hspi->RxISR = NULL;
		812
		813	/* Configure communication direction : 1Line */
		814	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		815	{
		816	SPI_1LINE_TX(hspi);
		817	}
		818
		819	#if (USE_SPI_CRC != 0U)
		820	/* Reset CRC Calculation */
		821	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		822	{
		823	SPI_RESET_CRC(hspi);
		824	}
		825	#endif /* USE_SPI_CRC */
		826
		827	/* Check if the SPI is already enabled */
		828	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		829	{
		830	/* Enable SPI peripheral */
		831	__HAL_SPI_ENABLE(hspi);
		832	}
		833
		834	/* Transmit data in 16 Bit mode */
		835	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		836	{
		837	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		838	{
		839	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		840	hspi->pTxBuffPtr += sizeof(uint16_t);
		841	hspi->TxXferCount--;
		842	}
		843	/* Transmit data in 16 Bit mode */
		844	while (hspi->TxXferCount > 0U)
		845	{
		846	/* Wait until TXE flag is set to send data */
		847	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		848	{
		849	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		850	hspi->pTxBuffPtr += sizeof(uint16_t);
		851	hspi->TxXferCount--;
		852	}
		853	else
		854	{
		855	/* Timeout management */
		856	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		857	{
		858	errorcode = HAL_TIMEOUT;
		859	goto error;
		860	}
		861	}
		862	}
		863	}
		864	/* Transmit data in 8 Bit mode */
		865	else
		866	{
		867	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		868	{
		869	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		870	hspi->pTxBuffPtr += sizeof(uint8_t);
		871	hspi->TxXferCount--;
		872	}
		873	while (hspi->TxXferCount > 0U)
		874	{
		875	/* Wait until TXE flag is set to send data */
		876	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		877	{
		878	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		879	hspi->pTxBuffPtr += sizeof(uint8_t);
		880	hspi->TxXferCount--;
		881	}
		882	else
		883	{
		884	/* Timeout management */
		885	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		886	{
		887	errorcode = HAL_TIMEOUT;
		888	goto error;
		889	}
		890	}
		891	}
		892	}
		893	#if (USE_SPI_CRC != 0U)
		894	/* Enable CRC Transmission */
		895	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		896	{
		897	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		898	}
		899	#endif /* USE_SPI_CRC */
		900
		901	/* Check the end of the transaction */
		902	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		903	{
		904	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		905	}
		906
		907	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		908	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		909	{
		910	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		911	}
		912
		913	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		914	{
		915	errorcode = HAL_ERROR;
		916	}
		917
		918	error:
		919	hspi->State = HAL_SPI_STATE_READY;
		920	/* Process Unlocked */
		921	__HAL_UNLOCK(hspi);
		922	return errorcode;
		923	}
		924
		925	/**
		926	* @brief Receive an amount of data in blocking mode.
		927	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		928	* the configuration information for SPI module.
		929	* @param pData pointer to data buffer
		930	* @param Size amount of data to be received
		931	* @param Timeout Timeout duration
		932	* @retval HAL status
		933	*/
		934	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		935	{
		936	uint32_t tickstart;
		937	HAL_StatusTypeDef errorcode = HAL_OK;
		938
		939	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
		940	{
		941	hspi->State = HAL_SPI_STATE_BUSY_RX;
		942	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		943	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
		944	}
		945
		946	/* Process Locked */
		947	__HAL_LOCK(hspi);
		948
		949	/* Init tickstart for timeout management*/
		950	tickstart = HAL_GetTick();
		951
		952	if (hspi->State != HAL_SPI_STATE_READY)
		953	{
		954	errorcode = HAL_BUSY;
		955	goto error;
		956	}
		957
		958	if ((pData == NULL) \|\| (Size == 0U))
		959	{
		960	errorcode = HAL_ERROR;
		961	goto error;
		962	}
		963
		964	/* Set the transaction information */
		965	hspi->State = HAL_SPI_STATE_BUSY_RX;
		966	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		967	hspi->pRxBuffPtr = (uint8_t *)pData;
		968	hspi->RxXferSize = Size;
		969	hspi->RxXferCount = Size;
		970
		971	/Init field not used in handle to zero /
		972	hspi->pTxBuffPtr = (uint8_t *)NULL;
		973	hspi->TxXferSize = 0U;
		974	hspi->TxXferCount = 0U;
		975	hspi->RxISR = NULL;
		976	hspi->TxISR = NULL;
		977
		978	#if (USE_SPI_CRC != 0U)
		979	/* Reset CRC Calculation */
		980	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		981	{
		982	SPI_RESET_CRC(hspi);
		983	/* this is done to handle the CRCNEXT before the latest data */
		984	hspi->RxXferCount--;
		985	}
		986	#endif /* USE_SPI_CRC */
		987
		988	/* Configure communication direction: 1Line */
		989	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		990	{
		991	SPI_1LINE_RX(hspi);
		992	}
		993
		994	/* Check if the SPI is already enabled */
		995	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		996	{
		997	/* Enable SPI peripheral */
		998	__HAL_SPI_ENABLE(hspi);
		999	}
		1000
		1001	/* Receive data in 8 Bit mode */
		1002	if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
		1003	{
		1004	/* Transfer loop */
		1005	while (hspi->RxXferCount > 0U)
		1006	{
		1007	/* Check the RXNE flag */
		1008	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		1009	{
		1010	/* read the received data */
		1011	(* (uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t *)&hspi->Instance->DR;
		1012	hspi->pRxBuffPtr += sizeof(uint8_t);
		1013	hspi->RxXferCount--;
		1014	}
		1015	else
		1016	{
		1017	/* Timeout management */
		1018	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		1019	{
		1020	errorcode = HAL_TIMEOUT;
		1021	goto error;
		1022	}
		1023	}
		1024	}
		1025	}
		1026	else
		1027	{
		1028	/* Transfer loop */
		1029	while (hspi->RxXferCount > 0U)
		1030	{
		1031	/* Check the RXNE flag */
		1032	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		1033	{
		1034	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1035	hspi->pRxBuffPtr += sizeof(uint16_t);
		1036	hspi->RxXferCount--;
		1037	}
		1038	else
		1039	{
		1040	/* Timeout management */
		1041	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		1042	{
		1043	errorcode = HAL_TIMEOUT;
		1044	goto error;
		1045	}
		1046	}
		1047	}
		1048	}
		1049
		1050	#if (USE_SPI_CRC != 0U)
		1051	/* Handle the CRC Transmission */
		1052	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1053	{
		1054	/* freeze the CRC before the latest data */
		1055	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1056
		1057	/* Check if CRCNEXT is well reseted by hardware */
		1058	if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
		1059	{
		1060	/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
		1061	CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1062	}
		1063	/* Read the latest data */
		1064	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1065	{
		1066	/* the latest data has not been received */
		1067	errorcode = HAL_TIMEOUT;
		1068	goto error;
		1069	}
		1070
		1071	/* Receive last data in 16 Bit mode */
		1072	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		1073	{
		1074	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1075	}
		1076	/* Receive last data in 8 Bit mode */
		1077	else
		1078	{
		1079	((uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t )&hspi->Instance->DR;
		1080	}
		1081
		1082	/* Wait the CRC data */
		1083	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1084	{
		1085	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1086	errorcode = HAL_TIMEOUT;
		1087	goto error;
		1088	}
		1089
		1090	/* Read CRC to Flush DR and RXNE flag */
		1091	READ_REG(hspi->Instance->DR);
		1092	}
		1093	#endif /* USE_SPI_CRC */
		1094
		1095	/* Check the end of the transaction */
		1096	if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		1097	{
		1098	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1099	}
		1100
		1101	#if (USE_SPI_CRC != 0U)
		1102	/* Check if CRC error occurred */
		1103	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		1104	{
		1105	/* Check if CRC error is valid or not (workaround to be applied or not) */
		1106	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		1107	{
		1108	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1109
		1110	/* Reset CRC Calculation */
		1111	SPI_RESET_CRC(hspi);
		1112	}
		1113	else
		1114	{
		1115	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1116	}
		1117	}
		1118	#endif /* USE_SPI_CRC */
		1119
		1120	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		1121	{
		1122	errorcode = HAL_ERROR;
		1123	}
		1124
		1125	error :
		1126	hspi->State = HAL_SPI_STATE_READY;
		1127	__HAL_UNLOCK(hspi);
		1128	return errorcode;
		1129	}
		1130
		1131	/**
		1132	* @brief Transmit and Receive an amount of data in blocking mode.
		1133	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1134	* the configuration information for SPI module.
		1135	* @param pTxData pointer to transmission data buffer
		1136	* @param pRxData pointer to reception data buffer
		1137	* @param Size amount of data to be sent and received
		1138	* @param Timeout Timeout duration
		1139	* @retval HAL status
		1140	*/
		1141	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
		1142	uint32_t Timeout)
		1143	{
		1144	uint16_t initial_TxXferCount;
		1145	uint32_t tmp_mode;
		1146	HAL_SPI_StateTypeDef tmp_state;
		1147	uint32_t tickstart;
		1148
		1149	/* Variable used to alternate Rx and Tx during transfer */
		1150	uint32_t txallowed = 1U;
		1151	HAL_StatusTypeDef errorcode = HAL_OK;
		1152
		1153	/* Check Direction parameter */
		1154	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1155
		1156	/* Process Locked */
		1157	__HAL_LOCK(hspi);
		1158
		1159	/* Init tickstart for timeout management*/
		1160	tickstart = HAL_GetTick();
		1161
		1162	/* Init temporary variables */
		1163	tmp_state = hspi->State;
		1164	tmp_mode = hspi->Init.Mode;
		1165	initial_TxXferCount = Size;
		1166
		1167	if (!((tmp_state == HAL_SPI_STATE_READY) \|\| \
		1168	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1169	{
		1170	errorcode = HAL_BUSY;
		1171	goto error;
		1172	}
		1173
		1174	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1175	{
		1176	errorcode = HAL_ERROR;
		1177	goto error;
		1178	}
		1179
		1180	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1181	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1182	{
		1183	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1184	}
		1185
		1186	/* Set the transaction information */
		1187	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1188	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1189	hspi->RxXferCount = Size;
		1190	hspi->RxXferSize = Size;
		1191	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1192	hspi->TxXferCount = Size;
		1193	hspi->TxXferSize = Size;
		1194
		1195	/Init field not used in handle to zero /
		1196	hspi->RxISR = NULL;
		1197	hspi->TxISR = NULL;
		1198
		1199	#if (USE_SPI_CRC != 0U)
		1200	/* Reset CRC Calculation */
		1201	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1202	{
		1203	SPI_RESET_CRC(hspi);
		1204	}
		1205	#endif /* USE_SPI_CRC */
		1206
		1207	/* Check if the SPI is already enabled */
		1208	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1209	{
		1210	/* Enable SPI peripheral */
		1211	__HAL_SPI_ENABLE(hspi);
		1212	}
		1213
		1214	/* Transmit and Receive data in 16 Bit mode */
		1215	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		1216	{
		1217	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		1218	{
		1219	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1220	hspi->pTxBuffPtr += sizeof(uint16_t);
		1221	hspi->TxXferCount--;
		1222	}
		1223	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		1224	{
		1225	/* Check TXE flag */
		1226	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
		1227	{
		1228	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1229	hspi->pTxBuffPtr += sizeof(uint16_t);
		1230	hspi->TxXferCount--;
		1231	/* Next Data is a reception (Rx). Tx not allowed */
		1232	txallowed = 0U;
		1233
		1234	#if (USE_SPI_CRC != 0U)
		1235	/* Enable CRC Transmission */
		1236	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		1237	{
		1238	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1239	}
		1240	#endif /* USE_SPI_CRC */
		1241	}
		1242
		1243	/* Check RXNE flag */
		1244	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
		1245	{
		1246	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1247	hspi->pRxBuffPtr += sizeof(uint16_t);
		1248	hspi->RxXferCount--;
		1249	/* Next Data is a Transmission (Tx). Tx is allowed */
		1250	txallowed = 1U;
		1251	}
		1252	if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
		1253	{
		1254	errorcode = HAL_TIMEOUT;
		1255	goto error;
		1256	}
		1257	}
		1258	}
		1259	/* Transmit and Receive data in 8 Bit mode */
		1260	else
		1261	{
		1262	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		1263	{
		1264	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		1265	hspi->pTxBuffPtr += sizeof(uint8_t);
		1266	hspi->TxXferCount--;
		1267	}
		1268	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		1269	{
		1270	/* Check TXE flag */
		1271	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
		1272	{
		1273	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		1274	hspi->pTxBuffPtr++;
		1275	hspi->TxXferCount--;
		1276	/* Next Data is a reception (Rx). Tx not allowed */
		1277	txallowed = 0U;
		1278
		1279	#if (USE_SPI_CRC != 0U)
		1280	/* Enable CRC Transmission */
		1281	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		1282	{
		1283	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1284	}
		1285	#endif /* USE_SPI_CRC */
		1286	}
		1287
		1288	/* Wait until RXNE flag is reset */
		1289	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
		1290	{
		1291	((uint8_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
		1292	hspi->pRxBuffPtr++;
		1293	hspi->RxXferCount--;
		1294	/* Next Data is a Transmission (Tx). Tx is allowed */
		1295	txallowed = 1U;
		1296	}
		1297	if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) \|\| (Timeout == 0U))
		1298	{
		1299	errorcode = HAL_TIMEOUT;
		1300	goto error;
		1301	}
		1302	}
		1303	}
		1304
		1305	#if (USE_SPI_CRC != 0U)
		1306	/* Read CRC from DR to close CRC calculation process */
		1307	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1308	{
		1309	/* Wait until TXE flag */
		1310	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1311	{
		1312	/* Error on the CRC reception */
		1313	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1314	errorcode = HAL_TIMEOUT;
		1315	goto error;
		1316	}
		1317	/* Read CRC */
		1318	READ_REG(hspi->Instance->DR);
		1319	}
		1320
		1321	/* Check if CRC error occurred */
		1322	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		1323	{
		1324	/* Check if CRC error is valid or not (workaround to be applied or not) */
		1325	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		1326	{
		1327	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1328
		1329	/* Reset CRC Calculation */
		1330	SPI_RESET_CRC(hspi);
		1331
		1332	errorcode = HAL_ERROR;
		1333	}
		1334	else
		1335	{
		1336	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1337	}
		1338	}
		1339	#endif /* USE_SPI_CRC */
		1340
		1341	/* Check the end of the transaction */
		1342	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		1343	{
		1344	errorcode = HAL_ERROR;
		1345	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1346	goto error;
		1347	}
		1348
		1349	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		1350	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		1351	{
		1352	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1353	}
		1354
		1355	error :
		1356	hspi->State = HAL_SPI_STATE_READY;
		1357	__HAL_UNLOCK(hspi);
		1358	return errorcode;
		1359	}
		1360
		1361	/**
		1362	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
		1363	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1364	* the configuration information for SPI module.
		1365	* @param pData pointer to data buffer
		1366	* @param Size amount of data to be sent
		1367	* @retval HAL status
		1368	*/
		1369	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1370	{
		1371	HAL_StatusTypeDef errorcode = HAL_OK;
		1372
		1373	/* Check Direction parameter */
		1374	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1375
		1376	/* Process Locked */
		1377	__HAL_LOCK(hspi);
		1378
		1379	if ((pData == NULL) \|\| (Size == 0U))
		1380	{
		1381	errorcode = HAL_ERROR;
		1382	goto error;
		1383	}
		1384
		1385	if (hspi->State != HAL_SPI_STATE_READY)
		1386	{
		1387	errorcode = HAL_BUSY;
		1388	goto error;
		1389	}
		1390
		1391	/* Set the transaction information */
		1392	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1393	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1394	hspi->pTxBuffPtr = (uint8_t *)pData;
		1395	hspi->TxXferSize = Size;
		1396	hspi->TxXferCount = Size;
		1397
		1398	/* Init field not used in handle to zero */
		1399	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1400	hspi->RxXferSize = 0U;
		1401	hspi->RxXferCount = 0U;
		1402	hspi->RxISR = NULL;
		1403
		1404	/* Set the function for IT treatment */
		1405	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1406	{
		1407	hspi->TxISR = SPI_TxISR_16BIT;
		1408	}
		1409	else
		1410	{
		1411	hspi->TxISR = SPI_TxISR_8BIT;
		1412	}
		1413
		1414	/* Configure communication direction : 1Line */
		1415	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1416	{
		1417	SPI_1LINE_TX(hspi);
		1418	}
		1419
		1420	#if (USE_SPI_CRC != 0U)
		1421	/* Reset CRC Calculation */
		1422	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1423	{
		1424	SPI_RESET_CRC(hspi);
		1425	}
		1426	#endif /* USE_SPI_CRC */
		1427
		1428	/* Enable TXE and ERR interrupt */
		1429	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		1430
		1431
		1432	/* Check if the SPI is already enabled */
		1433	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1434	{
		1435	/* Enable SPI peripheral */
		1436	__HAL_SPI_ENABLE(hspi);
		1437	}
		1438
		1439	error :
		1440	__HAL_UNLOCK(hspi);
		1441	return errorcode;
		1442	}
		1443
		1444	/**
		1445	* @brief Receive an amount of data in non-blocking mode with Interrupt.
		1446	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1447	* the configuration information for SPI module.
		1448	* @param pData pointer to data buffer
		1449	* @param Size amount of data to be sent
		1450	* @retval HAL status
		1451	*/
		1452	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1453	{
		1454	HAL_StatusTypeDef errorcode = HAL_OK;
		1455
		1456	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1457	{
		1458	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1459	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1460	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
		1461	}
		1462
		1463	/* Process Locked */
		1464	__HAL_LOCK(hspi);
		1465
		1466	if (hspi->State != HAL_SPI_STATE_READY)
		1467	{
		1468	errorcode = HAL_BUSY;
		1469	goto error;
		1470	}
		1471
		1472	if ((pData == NULL) \|\| (Size == 0U))
		1473	{
		1474	errorcode = HAL_ERROR;
		1475	goto error;
		1476	}
		1477
		1478	/* Set the transaction information */
		1479	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1480	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1481	hspi->pRxBuffPtr = (uint8_t *)pData;
		1482	hspi->RxXferSize = Size;
		1483	hspi->RxXferCount = Size;
		1484
		1485	/* Init field not used in handle to zero */
		1486	hspi->pTxBuffPtr = (uint8_t *)NULL;
		1487	hspi->TxXferSize = 0U;
		1488	hspi->TxXferCount = 0U;
		1489	hspi->TxISR = NULL;
		1490
		1491	/* Set the function for IT treatment */
		1492	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1493	{
		1494	hspi->RxISR = SPI_RxISR_16BIT;
		1495	}
		1496	else
		1497	{
		1498	hspi->RxISR = SPI_RxISR_8BIT;
		1499	}
		1500
		1501	/* Configure communication direction : 1Line */
		1502	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1503	{
		1504	SPI_1LINE_RX(hspi);
		1505	}
		1506
		1507	#if (USE_SPI_CRC != 0U)
		1508	/* Reset CRC Calculation */
		1509	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1510	{
		1511	SPI_RESET_CRC(hspi);
		1512	}
		1513	#endif /* USE_SPI_CRC */
		1514
		1515	/* Enable TXE and ERR interrupt */
		1516	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		1517
		1518	/* Note : The SPI must be enabled after unlocking current process
		1519	to avoid the risk of SPI interrupt handle execution before current
		1520	process unlock */
		1521
		1522	/* Check if the SPI is already enabled */
		1523	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1524	{
		1525	/* Enable SPI peripheral */
		1526	__HAL_SPI_ENABLE(hspi);
		1527	}
		1528
		1529	error :
		1530	/* Process Unlocked */
		1531	__HAL_UNLOCK(hspi);
		1532	return errorcode;
		1533	}
		1534
		1535	/**
		1536	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
		1537	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1538	* the configuration information for SPI module.
		1539	* @param pTxData pointer to transmission data buffer
		1540	* @param pRxData pointer to reception data buffer
		1541	* @param Size amount of data to be sent and received
		1542	* @retval HAL status
		1543	*/
		1544	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
		1545	{
		1546	uint32_t tmp_mode;
		1547	HAL_SPI_StateTypeDef tmp_state;
		1548	HAL_StatusTypeDef errorcode = HAL_OK;
		1549
		1550	/* Check Direction parameter */
		1551	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1552
		1553	/* Process locked */
		1554	__HAL_LOCK(hspi);
		1555
		1556	/* Init temporary variables */
		1557	tmp_state = hspi->State;
		1558	tmp_mode = hspi->Init.Mode;
		1559
		1560	if (!((tmp_state == HAL_SPI_STATE_READY) \|\| \
		1561	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1562	{
		1563	errorcode = HAL_BUSY;
		1564	goto error;
		1565	}
		1566
		1567	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1568	{
		1569	errorcode = HAL_ERROR;
		1570	goto error;
		1571	}
		1572
		1573	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1574	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1575	{
		1576	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1577	}
		1578
		1579	/* Set the transaction information */
		1580	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1581	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1582	hspi->TxXferSize = Size;
		1583	hspi->TxXferCount = Size;
		1584	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1585	hspi->RxXferSize = Size;
		1586	hspi->RxXferCount = Size;
		1587
		1588	/* Set the function for IT treatment */
		1589	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1590	{
		1591	hspi->RxISR = SPI_2linesRxISR_16BIT;
		1592	hspi->TxISR = SPI_2linesTxISR_16BIT;
		1593	}
		1594	else
		1595	{
		1596	hspi->RxISR = SPI_2linesRxISR_8BIT;
		1597	hspi->TxISR = SPI_2linesTxISR_8BIT;
		1598	}
		1599
		1600	#if (USE_SPI_CRC != 0U)
		1601	/* Reset CRC Calculation */
		1602	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1603	{
		1604	SPI_RESET_CRC(hspi);
		1605	}
		1606	#endif /* USE_SPI_CRC */
		1607
		1608	/* Enable TXE, RXNE and ERR interrupt */
		1609	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		1610
		1611	/* Check if the SPI is already enabled */
		1612	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1613	{
		1614	/* Enable SPI peripheral */
		1615	__HAL_SPI_ENABLE(hspi);
		1616	}
		1617
		1618	error :
		1619	/* Process Unlocked */
		1620	__HAL_UNLOCK(hspi);
		1621	return errorcode;
		1622	}
		1623
		1624	/**
		1625	* @brief Transmit an amount of data in non-blocking mode with DMA.
		1626	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1627	* the configuration information for SPI module.
		1628	* @param pData pointer to data buffer
		1629	* @param Size amount of data to be sent
		1630	* @retval HAL status
		1631	*/
		1632	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1633	{
		1634	HAL_StatusTypeDef errorcode = HAL_OK;
		1635
		1636	/* Check tx dma handle */
		1637	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1638
		1639	/* Check Direction parameter */
		1640	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1641
		1642	/* Process Locked */
		1643	__HAL_LOCK(hspi);
		1644
		1645	if (hspi->State != HAL_SPI_STATE_READY)
		1646	{
		1647	errorcode = HAL_BUSY;
		1648	goto error;
		1649	}
		1650
		1651	if ((pData == NULL) \|\| (Size == 0U))
		1652	{
		1653	errorcode = HAL_ERROR;
		1654	goto error;
		1655	}
		1656
		1657	/* Set the transaction information */
		1658	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1659	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1660	hspi->pTxBuffPtr = (uint8_t *)pData;
		1661	hspi->TxXferSize = Size;
		1662	hspi->TxXferCount = Size;
		1663
		1664	/* Init field not used in handle to zero */
		1665	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1666	hspi->TxISR = NULL;
		1667	hspi->RxISR = NULL;
		1668	hspi->RxXferSize = 0U;
		1669	hspi->RxXferCount = 0U;
		1670
		1671	/* Configure communication direction : 1Line */
		1672	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1673	{
		1674	SPI_1LINE_TX(hspi);
		1675	}
		1676
		1677	#if (USE_SPI_CRC != 0U)
		1678	/* Reset CRC Calculation */
		1679	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1680	{
		1681	SPI_RESET_CRC(hspi);
		1682	}
		1683	#endif /* USE_SPI_CRC */
		1684
		1685	/* Set the SPI TxDMA Half transfer complete callback */
		1686	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
		1687
		1688	/* Set the SPI TxDMA transfer complete callback */
		1689	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
		1690
		1691	/* Set the DMA error callback */
		1692	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
		1693
		1694	/* Set the DMA AbortCpltCallback */
		1695	hspi->hdmatx->XferAbortCallback = NULL;
		1696
		1697	/* Enable the Tx DMA Stream/Channel */
		1698	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
		1699	hspi->TxXferCount))
		1700	{
		1701	/* Update SPI error code */
		1702	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1703	errorcode = HAL_ERROR;
		1704
		1705	hspi->State = HAL_SPI_STATE_READY;
		1706	goto error;
		1707	}
		1708
		1709	/* Check if the SPI is already enabled */
		1710	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1711	{
		1712	/* Enable SPI peripheral */
		1713	__HAL_SPI_ENABLE(hspi);
		1714	}
		1715
		1716	/* Enable the SPI Error Interrupt Bit */
		1717	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		1718
		1719	/* Enable Tx DMA Request */
		1720	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		1721
		1722	error :
		1723	/* Process Unlocked */
		1724	__HAL_UNLOCK(hspi);
		1725	return errorcode;
		1726	}
		1727
		1728	/**
		1729	* @brief Receive an amount of data in non-blocking mode with DMA.
		1730	* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
		1731	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1732	* the configuration information for SPI module.
		1733	* @param pData pointer to data buffer
		1734	* @note When the CRC feature is enabled the pData Length must be Size + 1.
		1735	* @param Size amount of data to be sent
		1736	* @retval HAL status
		1737	*/
		1738	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1739	{
		1740	HAL_StatusTypeDef errorcode = HAL_OK;
		1741
		1742	/* Check rx dma handle */
		1743	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
		1744
		1745	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1746	{
		1747	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1748
		1749	/* Check tx dma handle */
		1750	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1751
		1752	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1753	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
		1754	}
		1755
		1756	/* Process Locked */
		1757	__HAL_LOCK(hspi);
		1758
		1759	if (hspi->State != HAL_SPI_STATE_READY)
		1760	{
		1761	errorcode = HAL_BUSY;
		1762	goto error;
		1763	}
		1764
		1765	if ((pData == NULL) \|\| (Size == 0U))
		1766	{
		1767	errorcode = HAL_ERROR;
		1768	goto error;
		1769	}
		1770
		1771	/* Set the transaction information */
		1772	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1773	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1774	hspi->pRxBuffPtr = (uint8_t *)pData;
		1775	hspi->RxXferSize = Size;
		1776	hspi->RxXferCount = Size;
		1777
		1778	/Init field not used in handle to zero /
		1779	hspi->RxISR = NULL;
		1780	hspi->TxISR = NULL;
		1781	hspi->TxXferSize = 0U;
		1782	hspi->TxXferCount = 0U;
		1783
		1784	/* Configure communication direction : 1Line */
		1785	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1786	{
		1787	SPI_1LINE_RX(hspi);
		1788	}
		1789
		1790	#if (USE_SPI_CRC != 0U)
		1791	/* Reset CRC Calculation */
		1792	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1793	{
		1794	SPI_RESET_CRC(hspi);
		1795	}
		1796	#endif /* USE_SPI_CRC */
		1797
		1798	/* Set the SPI RxDMA Half transfer complete callback */
		1799	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		1800
		1801	/* Set the SPI Rx DMA transfer complete callback */
		1802	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		1803
		1804	/* Set the DMA error callback */
		1805	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		1806
		1807	/* Set the DMA AbortCpltCallback */
		1808	hspi->hdmarx->XferAbortCallback = NULL;
		1809
		1810	/* Enable the Rx DMA Stream/Channel */
		1811	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
		1812	hspi->RxXferCount))
		1813	{
		1814	/* Update SPI error code */
		1815	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1816	errorcode = HAL_ERROR;
		1817
		1818	hspi->State = HAL_SPI_STATE_READY;
		1819	goto error;
		1820	}
		1821
		1822	/* Check if the SPI is already enabled */
		1823	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1824	{
		1825	/* Enable SPI peripheral */
		1826	__HAL_SPI_ENABLE(hspi);
		1827	}
		1828
		1829	/* Enable the SPI Error Interrupt Bit */
		1830	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		1831
		1832	/* Enable Rx DMA Request */
		1833	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		1834
		1835	error:
		1836	/* Process Unlocked */
		1837	__HAL_UNLOCK(hspi);
		1838	return errorcode;
		1839	}
		1840
		1841	/**
		1842	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
		1843	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1844	* the configuration information for SPI module.
		1845	* @param pTxData pointer to transmission data buffer
		1846	* @param pRxData pointer to reception data buffer
		1847	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
		1848	* @param Size amount of data to be sent
		1849	* @retval HAL status
		1850	*/
		1851	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
		1852	uint16_t Size)
		1853	{
		1854	uint32_t tmp_mode;
		1855	HAL_SPI_StateTypeDef tmp_state;
		1856	HAL_StatusTypeDef errorcode = HAL_OK;
		1857
		1858	/* Check rx & tx dma handles */
		1859	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
		1860	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1861
		1862	/* Check Direction parameter */
		1863	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1864
		1865	/* Process locked */
		1866	__HAL_LOCK(hspi);
		1867
		1868	/* Init temporary variables */
		1869	tmp_state = hspi->State;
		1870	tmp_mode = hspi->Init.Mode;
		1871
		1872	if (!((tmp_state == HAL_SPI_STATE_READY) \|\|
		1873	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1874	{
		1875	errorcode = HAL_BUSY;
		1876	goto error;
		1877	}
		1878
		1879	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1880	{
		1881	errorcode = HAL_ERROR;
		1882	goto error;
		1883	}
		1884
		1885	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1886	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1887	{
		1888	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1889	}
		1890
		1891	/* Set the transaction information */
		1892	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1893	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1894	hspi->TxXferSize = Size;
		1895	hspi->TxXferCount = Size;
		1896	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1897	hspi->RxXferSize = Size;
		1898	hspi->RxXferCount = Size;
		1899
		1900	/* Init field not used in handle to zero */
		1901	hspi->RxISR = NULL;
		1902	hspi->TxISR = NULL;
		1903
		1904	#if (USE_SPI_CRC != 0U)
		1905	/* Reset CRC Calculation */
		1906	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1907	{
		1908	SPI_RESET_CRC(hspi);
		1909	}
		1910	#endif /* USE_SPI_CRC */
		1911
		1912	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
		1913	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
		1914	{
		1915	/* Set the SPI Rx DMA Half transfer complete callback */
		1916	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		1917	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		1918	}
		1919	else
		1920	{
		1921	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
		1922	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
		1923	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
		1924	}
		1925
		1926	/* Set the DMA error callback */
		1927	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		1928
		1929	/* Set the DMA AbortCpltCallback */
		1930	hspi->hdmarx->XferAbortCallback = NULL;
		1931
		1932	/* Enable the Rx DMA Stream/Channel */
		1933	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
		1934	hspi->RxXferCount))
		1935	{
		1936	/* Update SPI error code */
		1937	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1938	errorcode = HAL_ERROR;
		1939
		1940	hspi->State = HAL_SPI_STATE_READY;
		1941	goto error;
		1942	}
		1943
		1944	/* Enable Rx DMA Request */
		1945	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		1946
		1947	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
		1948	is performed in DMA reception complete callback */
		1949	hspi->hdmatx->XferHalfCpltCallback = NULL;
		1950	hspi->hdmatx->XferCpltCallback = NULL;
		1951	hspi->hdmatx->XferErrorCallback = NULL;
		1952	hspi->hdmatx->XferAbortCallback = NULL;
		1953
		1954	/* Enable the Tx DMA Stream/Channel */
		1955	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
		1956	hspi->TxXferCount))
		1957	{
		1958	/* Update SPI error code */
		1959	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1960	errorcode = HAL_ERROR;
		1961
		1962	hspi->State = HAL_SPI_STATE_READY;
		1963	goto error;
		1964	}
		1965
		1966	/* Check if the SPI is already enabled */
		1967	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1968	{
		1969	/* Enable SPI peripheral */
		1970	__HAL_SPI_ENABLE(hspi);
		1971	}
		1972	/* Enable the SPI Error Interrupt Bit */
		1973	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		1974
		1975	/* Enable Tx DMA Request */
		1976	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		1977
		1978	error :
		1979	/* Process Unlocked */
		1980	__HAL_UNLOCK(hspi);
		1981	return errorcode;
		1982	}
		1983
		1984	/**
		1985	* @brief Abort ongoing transfer (blocking mode).
		1986	* @param hspi SPI handle.
		1987	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		1988	* started in Interrupt or DMA mode.
		1989	* This procedure performs following operations :
		1990	* - Disable SPI Interrupts (depending of transfer direction)
		1991	* - Disable the DMA transfer in the peripheral register (if enabled)
		1992	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
		1993	* - Set handle State to READY
		1994	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
		1995	* @retval HAL status
		1996	*/
		1997	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
		1998	{
		1999	HAL_StatusTypeDef errorcode;
		2000	__IO uint32_t count;
		2001	__IO uint32_t resetcount;
		2002
		2003	/* Initialized local variable */
		2004	errorcode = HAL_OK;
		2005	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2006	count = resetcount;
		2007
		2008	/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
		2009	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		2010
		2011	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		2012	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		2013	{
		2014	hspi->TxISR = SPI_AbortTx_ISR;
		2015	/* Wait HAL_SPI_STATE_ABORT state */
		2016	do
		2017	{
		2018	if (count == 0U)
		2019	{
		2020	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2021	break;
		2022	}
		2023	count--;
		2024	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2025	/* Reset Timeout Counter */
		2026	count = resetcount;
		2027	}
		2028
		2029	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		2030	{
		2031	hspi->RxISR = SPI_AbortRx_ISR;
		2032	/* Wait HAL_SPI_STATE_ABORT state */
		2033	do
		2034	{
		2035	if (count == 0U)
		2036	{
		2037	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2038	break;
		2039	}
		2040	count--;
		2041	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2042	/* Reset Timeout Counter */
		2043	count = resetcount;
		2044	}
		2045
		2046	/* Disable the SPI DMA Tx request if enabled */
		2047	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2048	{
		2049	/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
		2050	if (hspi->hdmatx != NULL)
		2051	{
		2052	/* Set the SPI DMA Abort callback :
		2053	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		2054	hspi->hdmatx->XferAbortCallback = NULL;
		2055
		2056	/* Abort DMA Tx Handle linked to SPI Peripheral */
		2057	if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
		2058	{
		2059	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2060	}
		2061
		2062	/* Disable Tx DMA Request */
		2063	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
		2064
		2065	/* Wait until TXE flag is set */
		2066	do
		2067	{
		2068	if (count == 0U)
		2069	{
		2070	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2071	break;
		2072	}
		2073	count--;
		2074	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		2075	}
		2076	}
		2077
		2078	/* Disable the SPI DMA Rx request if enabled */
		2079	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2080	{
		2081	/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
		2082	if (hspi->hdmarx != NULL)
		2083	{
		2084	/* Set the SPI DMA Abort callback :
		2085	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		2086	hspi->hdmarx->XferAbortCallback = NULL;
		2087
		2088	/* Abort DMA Rx Handle linked to SPI Peripheral */
		2089	if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
		2090	{
		2091	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2092	}
		2093
		2094	/* Disable peripheral */
		2095	__HAL_SPI_DISABLE(hspi);
		2096
		2097	/* Disable Rx DMA Request */
		2098	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
		2099	}
		2100	}
		2101	/* Reset Tx and Rx transfer counters */
		2102	hspi->RxXferCount = 0U;
		2103	hspi->TxXferCount = 0U;
		2104
		2105	/* Check error during Abort procedure */
		2106	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
		2107	{
		2108	/* return HAL_Error in case of error during Abort procedure */
		2109	errorcode = HAL_ERROR;
		2110	}
		2111	else
		2112	{
		2113	/* Reset errorCode */
		2114	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2115	}
		2116
		2117	/* Clear the Error flags in the SR register */
		2118	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2119
		2120	/* Restore hspi->state to ready */
		2121	hspi->State = HAL_SPI_STATE_READY;
		2122
		2123	return errorcode;
		2124	}
		2125
		2126	/**
		2127	* @brief Abort ongoing transfer (Interrupt mode).
		2128	* @param hspi SPI handle.
		2129	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		2130	* started in Interrupt or DMA mode.
		2131	* This procedure performs following operations :
		2132	* - Disable SPI Interrupts (depending of transfer direction)
		2133	* - Disable the DMA transfer in the peripheral register (if enabled)
		2134	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
		2135	* - Set handle State to READY
		2136	* - At abort completion, call user abort complete callback
		2137	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
		2138	* considered as completed only when user abort complete callback is executed (not when exiting function).
		2139	* @retval HAL status
		2140	*/
		2141	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
		2142	{
		2143	HAL_StatusTypeDef errorcode;
		2144	uint32_t abortcplt ;
		2145	__IO uint32_t count;
		2146	__IO uint32_t resetcount;
		2147
		2148	/* Initialized local variable */
		2149	errorcode = HAL_OK;
		2150	abortcplt = 1U;
		2151	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2152	count = resetcount;
		2153
		2154	/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
		2155	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		2156
		2157	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
		2158	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		2159	{
		2160	hspi->TxISR = SPI_AbortTx_ISR;
		2161	/* Wait HAL_SPI_STATE_ABORT state */
		2162	do
		2163	{
		2164	if (count == 0U)
		2165	{
		2166	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2167	break;
		2168	}
		2169	count--;
		2170	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2171	/* Reset Timeout Counter */
		2172	count = resetcount;
		2173	}
		2174
		2175	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		2176	{
		2177	hspi->RxISR = SPI_AbortRx_ISR;
		2178	/* Wait HAL_SPI_STATE_ABORT state */
		2179	do
		2180	{
		2181	if (count == 0U)
		2182	{
		2183	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2184	break;
		2185	}
		2186	count--;
		2187	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2188	/* Reset Timeout Counter */
		2189	count = resetcount;
		2190	}
		2191
		2192	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
		2193	before any call to DMA Abort functions */
		2194	/* DMA Tx Handle is valid */
		2195	if (hspi->hdmatx != NULL)
		2196	{
		2197	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
		2198	Otherwise, set it to NULL */
		2199	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2200	{
		2201	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
		2202	}
		2203	else
		2204	{
		2205	hspi->hdmatx->XferAbortCallback = NULL;
		2206	}
		2207	}
		2208	/* DMA Rx Handle is valid */
		2209	if (hspi->hdmarx != NULL)
		2210	{
		2211	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
		2212	Otherwise, set it to NULL */
		2213	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2214	{
		2215	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
		2216	}
		2217	else
		2218	{
		2219	hspi->hdmarx->XferAbortCallback = NULL;
		2220	}
		2221	}
		2222
		2223	/* Disable the SPI DMA Tx request if enabled */
		2224	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2225	{
		2226	/* Abort the SPI DMA Tx Stream/Channel */
		2227	if (hspi->hdmatx != NULL)
		2228	{
		2229	/* Abort DMA Tx Handle linked to SPI Peripheral */
		2230	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
		2231	{
		2232	hspi->hdmatx->XferAbortCallback = NULL;
		2233	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2234	}
		2235	else
		2236	{
		2237	abortcplt = 0U;
		2238	}
		2239	}
		2240	}
		2241	/* Disable the SPI DMA Rx request if enabled */
		2242	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2243	{
		2244	/* Abort the SPI DMA Rx Stream/Channel */
		2245	if (hspi->hdmarx != NULL)
		2246	{
		2247	/* Abort DMA Rx Handle linked to SPI Peripheral */
		2248	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
		2249	{
		2250	hspi->hdmarx->XferAbortCallback = NULL;
		2251	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2252	}
		2253	else
		2254	{
		2255	abortcplt = 0U;
		2256	}
		2257	}
		2258	}
		2259
		2260	if (abortcplt == 1U)
		2261	{
		2262	/* Reset Tx and Rx transfer counters */
		2263	hspi->RxXferCount = 0U;
		2264	hspi->TxXferCount = 0U;
		2265
		2266	/* Check error during Abort procedure */
		2267	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
		2268	{
		2269	/* return HAL_Error in case of error during Abort procedure */
		2270	errorcode = HAL_ERROR;
		2271	}
		2272	else
		2273	{
		2274	/* Reset errorCode */
		2275	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2276	}
		2277
		2278	/* Clear the Error flags in the SR register */
		2279	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2280
		2281	/* Restore hspi->State to Ready */
		2282	hspi->State = HAL_SPI_STATE_READY;
		2283
		2284	/* As no DMA to be aborted, call directly user Abort complete callback */
		2285	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2286	hspi->AbortCpltCallback(hspi);
		2287	#else
		2288	HAL_SPI_AbortCpltCallback(hspi);
		2289	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2290	}
		2291
		2292	return errorcode;
		2293	}
		2294
		2295	/**
		2296	* @brief Pause the DMA Transfer.
		2297	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2298	* the configuration information for the specified SPI module.
		2299	* @retval HAL status
		2300	*/
		2301	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
		2302	{
		2303	/* Process Locked */
		2304	__HAL_LOCK(hspi);
		2305
		2306	/* Disable the SPI DMA Tx & Rx requests */
		2307	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2308
		2309	/* Process Unlocked */
		2310	__HAL_UNLOCK(hspi);
		2311
		2312	return HAL_OK;
		2313	}
		2314
		2315	/**
		2316	* @brief Resume the DMA Transfer.
		2317	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2318	* the configuration information for the specified SPI module.
		2319	* @retval HAL status
		2320	*/
		2321	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
		2322	{
		2323	/* Process Locked */
		2324	__HAL_LOCK(hspi);
		2325
		2326	/* Enable the SPI DMA Tx & Rx requests */
		2327	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2328
		2329	/* Process Unlocked */
		2330	__HAL_UNLOCK(hspi);
		2331
		2332	return HAL_OK;
		2333	}
		2334
		2335	/**
		2336	* @brief Stop the DMA Transfer.
		2337	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2338	* the configuration information for the specified SPI module.
		2339	* @retval HAL status
		2340	*/
		2341	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
		2342	{
		2343	HAL_StatusTypeDef errorcode = HAL_OK;
		2344	/* The Lock is not implemented on this API to allow the user application
		2345	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
		2346	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
		2347	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
		2348	*/
		2349
		2350	/* Abort the SPI DMA tx Stream/Channel */
		2351	if (hspi->hdmatx != NULL)
		2352	{
		2353	if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
		2354	{
		2355	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2356	errorcode = HAL_ERROR;
		2357	}
		2358	}
		2359	/* Abort the SPI DMA rx Stream/Channel */
		2360	if (hspi->hdmarx != NULL)
		2361	{
		2362	if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
		2363	{
		2364	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2365	errorcode = HAL_ERROR;
		2366	}
		2367	}
		2368
		2369	/* Disable the SPI DMA Tx & Rx requests */
		2370	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2371	hspi->State = HAL_SPI_STATE_READY;
		2372	return errorcode;
		2373	}
		2374
		2375	/**
		2376	* @brief Handle SPI interrupt request.
		2377	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2378	* the configuration information for the specified SPI module.
		2379	* @retval None
		2380	*/
		2381	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
		2382	{
		2383	uint32_t itsource = hspi->Instance->CR2;
		2384	uint32_t itflag = hspi->Instance->SR;
		2385
		2386	/* SPI in mode Receiver ----------------------------------------------------*/
		2387	if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
		2388	(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
		2389	{
		2390	hspi->RxISR(hspi);
		2391	return;
		2392	}
		2393
		2394	/* SPI in mode Transmitter -------------------------------------------------*/
		2395	if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
		2396	{
		2397	hspi->TxISR(hspi);
		2398	return;
		2399	}
		2400
		2401	/* SPI in Error Treatment --------------------------------------------------*/
		2402	if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) \|\| (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
		2403	&& (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
		2404	{
		2405	/* SPI Overrun error interrupt occurred ----------------------------------*/
		2406	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
		2407	{
		2408	if (hspi->State != HAL_SPI_STATE_BUSY_TX)
		2409	{
		2410	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
		2411	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2412	}
		2413	else
		2414	{
		2415	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2416	return;
		2417	}
		2418	}
		2419
		2420	/* SPI Mode Fault error interrupt occurred -------------------------------*/
		2421	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
		2422	{
		2423	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
		2424	__HAL_SPI_CLEAR_MODFFLAG(hspi);
		2425	}
		2426
		2427	/* SPI Frame error interrupt occurred ------------------------------------*/
		2428
		2429	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2430	{
		2431	/* Disable all interrupts */
		2432	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
		2433
		2434	hspi->State = HAL_SPI_STATE_READY;
		2435	/* Disable the SPI DMA requests if enabled */
		2436	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
		2437	{
		2438	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
		2439
		2440	/* Abort the SPI DMA Rx channel */
		2441	if (hspi->hdmarx != NULL)
		2442	{
		2443	/* Set the SPI DMA Abort callback :
		2444	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2445	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
		2446	if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
		2447	{
		2448	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2449	}
		2450	}
		2451	/* Abort the SPI DMA Tx channel */
		2452	if (hspi->hdmatx != NULL)
		2453	{
		2454	/* Set the SPI DMA Abort callback :
		2455	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2456	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
		2457	if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
		2458	{
		2459	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2460	}
		2461	}
		2462	}
		2463	else
		2464	{
		2465	/* Call user error callback */
		2466	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2467	hspi->ErrorCallback(hspi);
		2468	#else
		2469	HAL_SPI_ErrorCallback(hspi);
		2470	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2471	}
		2472	}
		2473	return;
		2474	}
		2475	}
		2476
		2477	/**
		2478	* @brief Tx Transfer completed callback.
		2479	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2480	* the configuration information for SPI module.
		2481	* @retval None
		2482	*/
		2483	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
		2484	{
		2485	/* Prevent unused argument(s) compilation warning */
		2486	UNUSED(hspi);
		2487
		2488	/* NOTE : This function should not be modified, when the callback is needed,
		2489	the HAL_SPI_TxCpltCallback should be implemented in the user file
		2490	*/
		2491	}
		2492
		2493	/**
		2494	* @brief Rx Transfer completed callback.
		2495	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2496	* the configuration information for SPI module.
		2497	* @retval None
		2498	*/
		2499	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
		2500	{
		2501	/* Prevent unused argument(s) compilation warning */
		2502	UNUSED(hspi);
		2503
		2504	/* NOTE : This function should not be modified, when the callback is needed,
		2505	the HAL_SPI_RxCpltCallback should be implemented in the user file
		2506	*/
		2507	}
		2508
		2509	/**
		2510	* @brief Tx and Rx Transfer completed callback.
		2511	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2512	* the configuration information for SPI module.
		2513	* @retval None
		2514	*/
		2515	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
		2516	{
		2517	/* Prevent unused argument(s) compilation warning */
		2518	UNUSED(hspi);
		2519
		2520	/* NOTE : This function should not be modified, when the callback is needed,
		2521	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
		2522	*/
		2523	}
		2524
		2525	/**
		2526	* @brief Tx Half Transfer completed callback.
		2527	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2528	* the configuration information for SPI module.
		2529	* @retval None
		2530	*/
		2531	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2532	{
		2533	/* Prevent unused argument(s) compilation warning */
		2534	UNUSED(hspi);
		2535
		2536	/* NOTE : This function should not be modified, when the callback is needed,
		2537	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
		2538	*/
		2539	}
		2540
		2541	/**
		2542	* @brief Rx Half Transfer completed callback.
		2543	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2544	* the configuration information for SPI module.
		2545	* @retval None
		2546	*/
		2547	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2548	{
		2549	/* Prevent unused argument(s) compilation warning */
		2550	UNUSED(hspi);
		2551
		2552	/* NOTE : This function should not be modified, when the callback is needed,
		2553	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
		2554	*/
		2555	}
		2556
		2557	/**
		2558	* @brief Tx and Rx Half Transfer callback.
		2559	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2560	* the configuration information for SPI module.
		2561	* @retval None
		2562	*/
		2563	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2564	{
		2565	/* Prevent unused argument(s) compilation warning */
		2566	UNUSED(hspi);
		2567
		2568	/* NOTE : This function should not be modified, when the callback is needed,
		2569	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
		2570	*/
		2571	}
		2572
		2573	/**
		2574	* @brief SPI error callback.
		2575	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2576	* the configuration information for SPI module.
		2577	* @retval None
		2578	*/
		2579	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
		2580	{
		2581	/* Prevent unused argument(s) compilation warning */
		2582	UNUSED(hspi);
		2583
		2584	/* NOTE : This function should not be modified, when the callback is needed,
		2585	the HAL_SPI_ErrorCallback should be implemented in the user file
		2586	*/
		2587	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
		2588	and user can use HAL_SPI_GetError() API to check the latest error occurred
		2589	*/
		2590	}
		2591
		2592	/**
		2593	* @brief SPI Abort Complete callback.
		2594	* @param hspi SPI handle.
		2595	* @retval None
		2596	*/
		2597	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
		2598	{
		2599	/* Prevent unused argument(s) compilation warning */
		2600	UNUSED(hspi);
		2601
		2602	/* NOTE : This function should not be modified, when the callback is needed,
		2603	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
		2604	*/
		2605	}
		2606
		2607	/**
		2608	* @}
		2609	*/
		2610
		2611	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
		2612	* @brief SPI control functions
		2613	*
		2614	@verbatim
		2615	===============================================================================
		2616	##### Peripheral State and Errors functions #####
		2617	===============================================================================
		2618	[..]
		2619	This subsection provides a set of functions allowing to control the SPI.
		2620	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
		2621	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
		2622	@endverbatim
		2623	* @{
		2624	*/
		2625
		2626	/**
		2627	* @brief Return the SPI handle state.
		2628	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2629	* the configuration information for SPI module.
		2630	* @retval SPI state
		2631	*/
		2632	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
		2633	{
		2634	/* Return SPI handle state */
		2635	return hspi->State;
		2636	}
		2637
		2638	/**
		2639	* @brief Return the SPI error code.
		2640	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2641	* the configuration information for SPI module.
		2642	* @retval SPI error code in bitmap format
		2643	*/
		2644	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
		2645	{
		2646	/* Return SPI ErrorCode */
		2647	return hspi->ErrorCode;
		2648	}
		2649
		2650	/**
		2651	* @}
		2652	*/
		2653
		2654	/**
		2655	* @}
		2656	*/
		2657
		2658	/** @addtogroup SPI_Private_Functions
		2659	* @brief Private functions
		2660	* @{
		2661	*/
		2662
		2663	/**
		2664	* @brief DMA SPI transmit process complete callback.
		2665	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2666	* the configuration information for the specified DMA module.
		2667	* @retval None
		2668	*/
		2669	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
		2670	{
		2671	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2672	uint32_t tickstart;
		2673
		2674	/* Init tickstart for timeout management*/
		2675	tickstart = HAL_GetTick();
		2676
		2677	/* DMA Normal Mode */
		2678	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2679	{
		2680	/* Disable ERR interrupt */
		2681	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		2682
		2683	/* Disable Tx DMA Request */
		2684	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		2685
		2686	/* Check the end of the transaction */
		2687	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2688	{
		2689	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2690	}
		2691
		2692	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
		2693	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		2694	{
		2695	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2696	}
		2697
		2698	hspi->TxXferCount = 0U;
		2699	hspi->State = HAL_SPI_STATE_READY;
		2700
		2701	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2702	{
		2703	/* Call user error callback */
		2704	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2705	hspi->ErrorCallback(hspi);
		2706	#else
		2707	HAL_SPI_ErrorCallback(hspi);
		2708	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2709	return;
		2710	}
		2711	}
		2712	/* Call user Tx complete callback */
		2713	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2714	hspi->TxCpltCallback(hspi);
		2715	#else
		2716	HAL_SPI_TxCpltCallback(hspi);
		2717	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2718	}
		2719
		2720	/**
		2721	* @brief DMA SPI receive process complete callback.
		2722	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2723	* the configuration information for the specified DMA module.
		2724	* @retval None
		2725	*/
		2726	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
		2727	{
		2728	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2729	uint32_t tickstart;
		2730
		2731	/* Init tickstart for timeout management*/
		2732	tickstart = HAL_GetTick();
		2733
		2734	/* DMA Normal Mode */
		2735	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2736	{
		2737	/* Disable ERR interrupt */
		2738	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		2739
		2740	#if (USE_SPI_CRC != 0U)
		2741	/* CRC handling */
		2742	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2743	{
		2744	/* Wait until RXNE flag */
		2745	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2746	{
		2747	/* Error on the CRC reception */
		2748	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2749	}
		2750	/* Read CRC */
		2751	READ_REG(hspi->Instance->DR);
		2752	}
		2753	#endif /* USE_SPI_CRC */
		2754
		2755	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
		2756	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2757
		2758	/* Check the end of the transaction */
		2759	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2760	{
		2761	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		2762	}
		2763
		2764	hspi->RxXferCount = 0U;
		2765	hspi->State = HAL_SPI_STATE_READY;
		2766
		2767	#if (USE_SPI_CRC != 0U)
		2768	/* Check if CRC error occurred */
		2769	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		2770	{
		2771	/* Check if CRC error is valid or not (workaround to be applied or not) */
		2772	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		2773	{
		2774	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2775
		2776	/* Reset CRC Calculation */
		2777	SPI_RESET_CRC(hspi);
		2778	}
		2779	else
		2780	{
		2781	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		2782	}
		2783	}
		2784	#endif /* USE_SPI_CRC */
		2785
		2786	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2787	{
		2788	/* Call user error callback */
		2789	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2790	hspi->ErrorCallback(hspi);
		2791	#else
		2792	HAL_SPI_ErrorCallback(hspi);
		2793	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2794	return;
		2795	}
		2796	}
		2797	/* Call user Rx complete callback */
		2798	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2799	hspi->RxCpltCallback(hspi);
		2800	#else
		2801	HAL_SPI_RxCpltCallback(hspi);
		2802	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2803	}
		2804
		2805	/**
		2806	* @brief DMA SPI transmit receive process complete callback.
		2807	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2808	* the configuration information for the specified DMA module.
		2809	* @retval None
		2810	*/
		2811	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		2812	{
		2813	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2814	uint32_t tickstart;
		2815
		2816	/* Init tickstart for timeout management*/
		2817	tickstart = HAL_GetTick();
		2818
		2819	/* DMA Normal Mode */
		2820	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2821	{
		2822	/* Disable ERR interrupt */
		2823	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		2824
		2825	#if (USE_SPI_CRC != 0U)
		2826	/* CRC handling */
		2827	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2828	{
		2829	/* Wait the CRC data */
		2830	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2831	{
		2832	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2833	}
		2834	/* Read CRC to Flush DR and RXNE flag */
		2835	READ_REG(hspi->Instance->DR);
		2836	}
		2837	#endif /* USE_SPI_CRC */
		2838
		2839	/* Check the end of the transaction */
		2840	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2841	{
		2842	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2843	}
		2844
		2845	/* Disable Rx/Tx DMA Request */
		2846	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2847
		2848	hspi->TxXferCount = 0U;
		2849	hspi->RxXferCount = 0U;
		2850	hspi->State = HAL_SPI_STATE_READY;
		2851
		2852	#if (USE_SPI_CRC != 0U)
		2853	/* Check if CRC error occurred */
		2854	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		2855	{
		2856	/* Check if CRC error is valid or not (workaround to be applied or not) */
		2857	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		2858	{
		2859	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2860
		2861	/* Reset CRC Calculation */
		2862	SPI_RESET_CRC(hspi);
		2863	}
		2864	else
		2865	{
		2866	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		2867	}
		2868	}
		2869	#endif /* USE_SPI_CRC */
		2870
		2871	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2872	{
		2873	/* Call user error callback */
		2874	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2875	hspi->ErrorCallback(hspi);
		2876	#else
		2877	HAL_SPI_ErrorCallback(hspi);
		2878	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2879	return;
		2880	}
		2881	}
		2882	/* Call user TxRx complete callback */
		2883	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2884	hspi->TxRxCpltCallback(hspi);
		2885	#else
		2886	HAL_SPI_TxRxCpltCallback(hspi);
		2887	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2888	}
		2889
		2890	/**
		2891	* @brief DMA SPI half transmit process complete callback.
		2892	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2893	* the configuration information for the specified DMA module.
		2894	* @retval None
		2895	*/
		2896	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
		2897	{
		2898	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2899
		2900	/* Call user Tx half complete callback */
		2901	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2902	hspi->TxHalfCpltCallback(hspi);
		2903	#else
		2904	HAL_SPI_TxHalfCpltCallback(hspi);
		2905	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2906	}
		2907
		2908	/**
		2909	* @brief DMA SPI half receive process complete callback
		2910	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2911	* the configuration information for the specified DMA module.
		2912	* @retval None
		2913	*/
		2914	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
		2915	{
		2916	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2917
		2918	/* Call user Rx half complete callback */
		2919	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2920	hspi->RxHalfCpltCallback(hspi);
		2921	#else
		2922	HAL_SPI_RxHalfCpltCallback(hspi);
		2923	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2924	}
		2925
		2926	/**
		2927	* @brief DMA SPI half transmit receive process complete callback.
		2928	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2929	* the configuration information for the specified DMA module.
		2930	* @retval None
		2931	*/
		2932	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		2933	{
		2934	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2935
		2936	/* Call user TxRx half complete callback */
		2937	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2938	hspi->TxRxHalfCpltCallback(hspi);
		2939	#else
		2940	HAL_SPI_TxRxHalfCpltCallback(hspi);
		2941	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2942	}
		2943
		2944	/**
		2945	* @brief DMA SPI communication error callback.
		2946	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2947	* the configuration information for the specified DMA module.
		2948	* @retval None
		2949	*/
		2950	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
		2951	{
		2952	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2953
		2954	/* Stop the disable DMA transfer on SPI side */
		2955	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2956
		2957	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2958	hspi->State = HAL_SPI_STATE_READY;
		2959	/* Call user error callback */
		2960	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2961	hspi->ErrorCallback(hspi);
		2962	#else
		2963	HAL_SPI_ErrorCallback(hspi);
		2964	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2965	}
		2966
		2967	/**
		2968	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
		2969	* (To be called at end of DMA Abort procedure following error occurrence).
		2970	* @param hdma DMA handle.
		2971	* @retval None
		2972	*/
		2973	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
		2974	{
		2975	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2976	hspi->RxXferCount = 0U;
		2977	hspi->TxXferCount = 0U;
		2978
		2979	/* Call user error callback */
		2980	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2981	hspi->ErrorCallback(hspi);
		2982	#else
		2983	HAL_SPI_ErrorCallback(hspi);
		2984	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2985	}
		2986
		2987	/**
		2988	* @brief DMA SPI Tx communication abort callback, when initiated by user
		2989	* (To be called at end of DMA Tx Abort procedure following user abort request).
		2990	* @note When this callback is executed, User Abort complete call back is called only if no
		2991	* Abort still ongoing for Rx DMA Handle.
		2992	* @param hdma DMA handle.
		2993	* @retval None
		2994	*/
		2995	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
		2996	{
		2997	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2998	__IO uint32_t count;
		2999
		3000	hspi->hdmatx->XferAbortCallback = NULL;
		3001	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3002
		3003	/* Disable Tx DMA Request */
		3004	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		3005
		3006	/* Wait until TXE flag is set */
		3007	do
		3008	{
		3009	if (count == 0U)
		3010	{
		3011	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		3012	break;
		3013	}
		3014	count--;
		3015	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3016
		3017	/* Check if an Abort process is still ongoing */
		3018	if (hspi->hdmarx != NULL)
		3019	{
		3020	if (hspi->hdmarx->XferAbortCallback != NULL)
		3021	{
		3022	return;
		3023	}
		3024	}
		3025
		3026	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
		3027	hspi->RxXferCount = 0U;
		3028	hspi->TxXferCount = 0U;
		3029
		3030	/* Check no error during Abort procedure */
		3031	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
		3032	{
		3033	/* Reset errorCode */
		3034	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		3035	}
		3036
		3037	/* Clear the Error flags in the SR register */
		3038	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3039
		3040	/* Restore hspi->State to Ready */
		3041	hspi->State = HAL_SPI_STATE_READY;
		3042
		3043	/* Call user Abort complete callback */
		3044	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3045	hspi->AbortCpltCallback(hspi);
		3046	#else
		3047	HAL_SPI_AbortCpltCallback(hspi);
		3048	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3049	}
		3050
		3051	/**
		3052	* @brief DMA SPI Rx communication abort callback, when initiated by user
		3053	* (To be called at end of DMA Rx Abort procedure following user abort request).
		3054	* @note When this callback is executed, User Abort complete call back is called only if no
		3055	* Abort still ongoing for Tx DMA Handle.
		3056	* @param hdma DMA handle.
		3057	* @retval None
		3058	*/
		3059	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
		3060	{
		3061	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3062
		3063	/* Disable SPI Peripheral */
		3064	__HAL_SPI_DISABLE(hspi);
		3065
		3066	hspi->hdmarx->XferAbortCallback = NULL;
		3067
		3068	/* Disable Rx DMA Request */
		3069	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		3070
		3071	/* Check Busy flag */
		3072	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3073	{
		3074	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		3075	}
		3076
		3077	/* Check if an Abort process is still ongoing */
		3078	if (hspi->hdmatx != NULL)
		3079	{
		3080	if (hspi->hdmatx->XferAbortCallback != NULL)
		3081	{
		3082	return;
		3083	}
		3084	}
		3085
		3086	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
		3087	hspi->RxXferCount = 0U;
		3088	hspi->TxXferCount = 0U;
		3089
		3090	/* Check no error during Abort procedure */
		3091	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
		3092	{
		3093	/* Reset errorCode */
		3094	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		3095	}
		3096
		3097	/* Clear the Error flags in the SR register */
		3098	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3099
		3100	/* Restore hspi->State to Ready */
		3101	hspi->State = HAL_SPI_STATE_READY;
		3102
		3103	/* Call user Abort complete callback */
		3104	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3105	hspi->AbortCpltCallback(hspi);
		3106	#else
		3107	HAL_SPI_AbortCpltCallback(hspi);
		3108	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3109	}
		3110
		3111	/**
		3112	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		3113	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3114	* the configuration information for SPI module.
		3115	* @retval None
		3116	*/
		3117	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3118	{
		3119	/* Receive data in 8bit mode */
		3120	hspi->pRxBuffPtr = ((__IO uint8_t *)&hspi->Instance->DR);
		3121	hspi->pRxBuffPtr++;
		3122	hspi->RxXferCount--;
		3123
		3124	/* Check end of the reception */
		3125	if (hspi->RxXferCount == 0U)
		3126	{
		3127	#if (USE_SPI_CRC != 0U)
		3128	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3129	{
		3130	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
		3131	return;
		3132	}
		3133	#endif /* USE_SPI_CRC */
		3134
		3135	/* Disable RXNE and ERR interrupt */
		3136	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3137
		3138	if (hspi->TxXferCount == 0U)
		3139	{
		3140	SPI_CloseRxTx_ISR(hspi);
		3141	}
		3142	}
		3143	}
		3144
		3145	#if (USE_SPI_CRC != 0U)
		3146	/**
		3147	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		3148	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3149	* the configuration information for SPI module.
		3150	* @retval None
		3151	*/
		3152	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		3153	{
		3154	/* Read 8bit CRC to flush Data Regsiter */
		3155	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3156
		3157	/* Disable RXNE and ERR interrupt */
		3158	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3159
		3160	if (hspi->TxXferCount == 0U)
		3161	{
		3162	SPI_CloseRxTx_ISR(hspi);
		3163	}
		3164	}
		3165	#endif /* USE_SPI_CRC */
		3166
		3167	/**
		3168	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
		3169	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3170	* the configuration information for SPI module.
		3171	* @retval None
		3172	*/
		3173	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3174	{
		3175	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		3176	hspi->pTxBuffPtr++;
		3177	hspi->TxXferCount--;
		3178
		3179	/* Check the end of the transmission */
		3180	if (hspi->TxXferCount == 0U)
		3181	{
		3182	#if (USE_SPI_CRC != 0U)
		3183	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3184	{
		3185	/* Set CRC Next Bit to send CRC */
		3186	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3187	/* Disable TXE interrupt */
		3188	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3189	return;
		3190	}
		3191	#endif /* USE_SPI_CRC */
		3192
		3193	/* Disable TXE interrupt */
		3194	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3195
		3196	if (hspi->RxXferCount == 0U)
		3197	{
		3198	SPI_CloseRxTx_ISR(hspi);
		3199	}
		3200	}
		3201	}
		3202
		3203	/**
		3204	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
		3205	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3206	* the configuration information for SPI module.
		3207	* @retval None
		3208	*/
		3209	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3210	{
		3211	/* Receive data in 16 Bit mode */
		3212	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3213	hspi->pRxBuffPtr += sizeof(uint16_t);
		3214	hspi->RxXferCount--;
		3215
		3216	if (hspi->RxXferCount == 0U)
		3217	{
		3218	#if (USE_SPI_CRC != 0U)
		3219	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3220	{
		3221	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
		3222	return;
		3223	}
		3224	#endif /* USE_SPI_CRC */
		3225
		3226	/* Disable RXNE interrupt */
		3227	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		3228
		3229	if (hspi->TxXferCount == 0U)
		3230	{
		3231	SPI_CloseRxTx_ISR(hspi);
		3232	}
		3233	}
		3234	}
		3235
		3236	#if (USE_SPI_CRC != 0U)
		3237	/**
		3238	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
		3239	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3240	* the configuration information for SPI module.
		3241	* @retval None
		3242	*/
		3243	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		3244	{
		3245	/* Read 16bit CRC to flush Data Regsiter */
		3246	READ_REG(hspi->Instance->DR);
		3247
		3248	/* Disable RXNE interrupt */
		3249	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		3250
		3251	SPI_CloseRxTx_ISR(hspi);
		3252	}
		3253	#endif /* USE_SPI_CRC */
		3254
		3255	/**
		3256	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
		3257	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3258	* the configuration information for SPI module.
		3259	* @retval None
		3260	*/
		3261	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3262	{
		3263	/* Transmit data in 16 Bit mode */
		3264	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3265	hspi->pTxBuffPtr += sizeof(uint16_t);
		3266	hspi->TxXferCount--;
		3267
		3268	/* Enable CRC Transmission */
		3269	if (hspi->TxXferCount == 0U)
		3270	{
		3271	#if (USE_SPI_CRC != 0U)
		3272	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3273	{
		3274	/* Set CRC Next Bit to send CRC */
		3275	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3276	/* Disable TXE interrupt */
		3277	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3278	return;
		3279	}
		3280	#endif /* USE_SPI_CRC */
		3281
		3282	/* Disable TXE interrupt */
		3283	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3284
		3285	if (hspi->RxXferCount == 0U)
		3286	{
		3287	SPI_CloseRxTx_ISR(hspi);
		3288	}
		3289	}
		3290	}
		3291
		3292	#if (USE_SPI_CRC != 0U)
		3293	/**
		3294	* @brief Manage the CRC 8-bit receive in Interrupt context.
		3295	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3296	* the configuration information for SPI module.
		3297	* @retval None
		3298	*/
		3299	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		3300	{
		3301	/* Read 8bit CRC to flush Data Register */
		3302	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3303
		3304	SPI_CloseRx_ISR(hspi);
		3305	}
		3306	#endif /* USE_SPI_CRC */
		3307
		3308	/**
		3309	* @brief Manage the receive 8-bit in Interrupt context.
		3310	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3311	* the configuration information for SPI module.
		3312	* @retval None
		3313	*/
		3314	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3315	{
		3316	hspi->pRxBuffPtr = ((__IO uint8_t *)&hspi->Instance->DR);
		3317	hspi->pRxBuffPtr++;
		3318	hspi->RxXferCount--;
		3319
		3320	#if (USE_SPI_CRC != 0U)
		3321	/* Enable CRC Transmission */
		3322	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		3323	{
		3324	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3325	}
		3326	/* Check if CRCNEXT is well reseted by hardware */
		3327	if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
		3328	{
		3329	/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
		3330	CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3331	}
		3332
		3333	#endif /* USE_SPI_CRC */
		3334
		3335	if (hspi->RxXferCount == 0U)
		3336	{
		3337	#if (USE_SPI_CRC != 0U)
		3338	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3339	{
		3340	hspi->RxISR = SPI_RxISR_8BITCRC;
		3341	return;
		3342	}
		3343	#endif /* USE_SPI_CRC */
		3344	SPI_CloseRx_ISR(hspi);
		3345	}
		3346	}
		3347
		3348	#if (USE_SPI_CRC != 0U)
		3349	/**
		3350	* @brief Manage the CRC 16-bit receive in Interrupt context.
		3351	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3352	* the configuration information for SPI module.
		3353	* @retval None
		3354	*/
		3355	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		3356	{
		3357	/* Read 16bit CRC to flush Data Register */
		3358	READ_REG(hspi->Instance->DR);
		3359
		3360	/* Disable RXNE and ERR interrupt */
		3361	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3362
		3363	SPI_CloseRx_ISR(hspi);
		3364	}
		3365	#endif /* USE_SPI_CRC */
		3366
		3367	/**
		3368	* @brief Manage the 16-bit receive in Interrupt context.
		3369	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3370	* the configuration information for SPI module.
		3371	* @retval None
		3372	*/
		3373	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3374	{
		3375	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3376	hspi->pRxBuffPtr += sizeof(uint16_t);
		3377	hspi->RxXferCount--;
		3378
		3379	#if (USE_SPI_CRC != 0U)
		3380	/* Enable CRC Transmission */
		3381	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		3382	{
		3383	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3384	}
		3385	/* Check if CRCNEXT is well reseted by hardware */
		3386	if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
		3387	{
		3388	/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
		3389	CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3390	}
		3391
		3392	#endif /* USE_SPI_CRC */
		3393
		3394	if (hspi->RxXferCount == 0U)
		3395	{
		3396	#if (USE_SPI_CRC != 0U)
		3397	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3398	{
		3399	hspi->RxISR = SPI_RxISR_16BITCRC;
		3400	return;
		3401	}
		3402	#endif /* USE_SPI_CRC */
		3403	SPI_CloseRx_ISR(hspi);
		3404	}
		3405	}
		3406
		3407	/**
		3408	* @brief Handle the data 8-bit transmit in Interrupt mode.
		3409	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3410	* the configuration information for SPI module.
		3411	* @retval None
		3412	*/
		3413	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3414	{
		3415	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		3416	hspi->pTxBuffPtr++;
		3417	hspi->TxXferCount--;
		3418
		3419	if (hspi->TxXferCount == 0U)
		3420	{
		3421	#if (USE_SPI_CRC != 0U)
		3422	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3423	{
		3424	/* Enable CRC Transmission */
		3425	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3426	}
		3427	#endif /* USE_SPI_CRC */
		3428	SPI_CloseTx_ISR(hspi);
		3429	}
		3430	}
		3431
		3432	/**
		3433	* @brief Handle the data 16-bit transmit in Interrupt mode.
		3434	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3435	* the configuration information for SPI module.
		3436	* @retval None
		3437	*/
		3438	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3439	{
		3440	/* Transmit data in 16 Bit mode */
		3441	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3442	hspi->pTxBuffPtr += sizeof(uint16_t);
		3443	hspi->TxXferCount--;
		3444
		3445	if (hspi->TxXferCount == 0U)
		3446	{
		3447	#if (USE_SPI_CRC != 0U)
		3448	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3449	{
		3450	/* Enable CRC Transmission */
		3451	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3452	}
		3453	#endif /* USE_SPI_CRC */
		3454	SPI_CloseTx_ISR(hspi);
		3455	}
		3456	}
		3457
		3458	/**
		3459	* @brief Handle SPI Communication Timeout.
		3460	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3461	* the configuration information for SPI module.
		3462	* @param Flag SPI flag to check
		3463	* @param State flag state to check
		3464	* @param Timeout Timeout duration
		3465	* @param Tickstart tick start value
		3466	* @retval HAL status
		3467	*/
		3468	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
		3469	uint32_t Timeout, uint32_t Tickstart)
		3470	{
		3471	while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
		3472	{
		3473	if (Timeout != HAL_MAX_DELAY)
		3474	{
		3475	if (((HAL_GetTick() - Tickstart) >= Timeout) \|\| (Timeout == 0U))
		3476	{
		3477	/* Disable the SPI and reset the CRC: the CRC value should be cleared
		3478	on both master and slave sides in order to resynchronize the master
		3479	and slave for their respective CRC calculation */
		3480
		3481	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
		3482	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		3483
		3484	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3485	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3486	{
		3487	/* Disable SPI peripheral */
		3488	__HAL_SPI_DISABLE(hspi);
		3489	}
		3490
		3491	/* Reset CRC Calculation */
		3492	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3493	{
		3494	SPI_RESET_CRC(hspi);
		3495	}
		3496
		3497	hspi->State = HAL_SPI_STATE_READY;
		3498
		3499	/* Process Unlocked */
		3500	__HAL_UNLOCK(hspi);
		3501
		3502	return HAL_TIMEOUT;
		3503	}
		3504	}
		3505	}
		3506
		3507	return HAL_OK;
		3508	}
		3509
		3510	/**
		3511	* @brief Handle the check of the RX transaction complete.
		3512	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3513	* the configuration information for SPI module.
		3514	* @param Timeout Timeout duration
		3515	* @param Tickstart tick start value
		3516	* @retval HAL status
		3517	*/
		3518	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		3519	{
		3520	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3521	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3522	{
		3523	/* Disable SPI peripheral */
		3524	__HAL_SPI_DISABLE(hspi);
		3525	}
		3526
		3527	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
		3528	{
		3529	/* Wait the RXNE reset */
		3530	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
		3531	{
		3532	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3533	return HAL_TIMEOUT;
		3534	}
		3535	}
		3536	else
		3537	{
		3538	/* Control the BSY flag */
		3539	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		3540	{
		3541	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3542	return HAL_TIMEOUT;
		3543	}
		3544	}
		3545	return HAL_OK;
		3546	}
		3547
		3548	/**
		3549	* @brief Handle the check of the RXTX or TX transaction complete.
		3550	* @param hspi SPI handle
		3551	* @param Timeout Timeout duration
		3552	* @param Tickstart tick start value
		3553	* @retval HAL status
		3554	*/
		3555	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		3556	{
		3557	/* Control the BSY flag */
		3558	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		3559	{
		3560	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3561	return HAL_TIMEOUT;
		3562	}
		3563	return HAL_OK;
		3564	}
		3565
		3566	/**
		3567	* @brief Handle the end of the RXTX transaction.
		3568	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3569	* the configuration information for SPI module.
		3570	* @retval None
		3571	*/
		3572	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
		3573	{
		3574	uint32_t tickstart;
		3575	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3576
		3577	/* Init tickstart for timeout managment*/
		3578	tickstart = HAL_GetTick();
		3579
		3580	/* Disable ERR interrupt */
		3581	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		3582
		3583	/* Wait until TXE flag is set */
		3584	do
		3585	{
		3586	if (count == 0U)
		3587	{
		3588	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3589	break;
		3590	}
		3591	count--;
		3592	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3593
		3594	/* Check the end of the transaction */
		3595	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3596	{
		3597	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3598	}
		3599
		3600	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3601	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3602	{
		3603	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3604	}
		3605
		3606	#if (USE_SPI_CRC != 0U)
		3607	/* Check if CRC error occurred */
		3608	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		3609	{
		3610	/* Check if CRC error is valid or not (workaround to be applied or not) */
		3611	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		3612	{
		3613	hspi->State = HAL_SPI_STATE_READY;
		3614	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3615
		3616	/* Reset CRC Calculation */
		3617	SPI_RESET_CRC(hspi);
		3618
		3619	/* Call user error callback */
		3620	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3621	hspi->ErrorCallback(hspi);
		3622	#else
		3623	HAL_SPI_ErrorCallback(hspi);
		3624	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3625	}
		3626	else
		3627	{
		3628	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3629	}
		3630	}
		3631	else
		3632	{
		3633	#endif /* USE_SPI_CRC */
		3634	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		3635	{
		3636	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
		3637	{
		3638	hspi->State = HAL_SPI_STATE_READY;
		3639	/* Call user Rx complete callback */
		3640	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3641	hspi->RxCpltCallback(hspi);
		3642	#else
		3643	HAL_SPI_RxCpltCallback(hspi);
		3644	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3645	}
		3646	else
		3647	{
		3648	hspi->State = HAL_SPI_STATE_READY;
		3649	/* Call user TxRx complete callback */
		3650	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3651	hspi->TxRxCpltCallback(hspi);
		3652	#else
		3653	HAL_SPI_TxRxCpltCallback(hspi);
		3654	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3655	}
		3656	}
		3657	else
		3658	{
		3659	hspi->State = HAL_SPI_STATE_READY;
		3660	/* Call user error callback */
		3661	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3662	hspi->ErrorCallback(hspi);
		3663	#else
		3664	HAL_SPI_ErrorCallback(hspi);
		3665	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3666	}
		3667	#if (USE_SPI_CRC != 0U)
		3668	}
		3669	#endif /* USE_SPI_CRC */
		3670	}
		3671
		3672	/**
		3673	* @brief Handle the end of the RX transaction.
		3674	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3675	* the configuration information for SPI module.
		3676	* @retval None
		3677	*/
		3678	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
		3679	{
		3680	/* Disable RXNE and ERR interrupt */
		3681	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3682
		3683	/* Check the end of the transaction */
		3684	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3685	{
		3686	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3687	}
		3688
		3689	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3690	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3691	{
		3692	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3693	}
		3694	hspi->State = HAL_SPI_STATE_READY;
		3695
		3696	#if (USE_SPI_CRC != 0U)
		3697	/* Check if CRC error occurred */
		3698	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		3699	{
		3700	/* Check if CRC error is valid or not (workaround to be applied or not) */
		3701	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		3702	{
		3703	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3704
		3705	/* Reset CRC Calculation */
		3706	SPI_RESET_CRC(hspi);
		3707
		3708	/* Call user error callback */
		3709	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3710	hspi->ErrorCallback(hspi);
		3711	#else
		3712	HAL_SPI_ErrorCallback(hspi);
		3713	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3714	}
		3715	else
		3716	{
		3717	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3718	}
		3719	}
		3720	else
		3721	{
		3722	#endif /* USE_SPI_CRC */
		3723	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		3724	{
		3725	/* Call user Rx complete callback */
		3726	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3727	hspi->RxCpltCallback(hspi);
		3728	#else
		3729	HAL_SPI_RxCpltCallback(hspi);
		3730	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3731	}
		3732	else
		3733	{
		3734	/* Call user error callback */
		3735	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3736	hspi->ErrorCallback(hspi);
		3737	#else
		3738	HAL_SPI_ErrorCallback(hspi);
		3739	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3740	}
		3741	#if (USE_SPI_CRC != 0U)
		3742	}
		3743	#endif /* USE_SPI_CRC */
		3744	}
		3745
		3746	/**
		3747	* @brief Handle the end of the TX transaction.
		3748	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3749	* the configuration information for SPI module.
		3750	* @retval None
		3751	*/
		3752	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
		3753	{
		3754	uint32_t tickstart;
		3755	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3756
		3757	/* Init tickstart for timeout management*/
		3758	tickstart = HAL_GetTick();
		3759
		3760	/* Wait until TXE flag is set */
		3761	do
		3762	{
		3763	if (count == 0U)
		3764	{
		3765	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3766	break;
		3767	}
		3768	count--;
		3769	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3770
		3771	/* Disable TXE and ERR interrupt */
		3772	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		3773
		3774	/* Check the end of the transaction */
		3775	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3776	{
		3777	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3778	}
		3779
		3780	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3781	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3782	{
		3783	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3784	}
		3785
		3786	hspi->State = HAL_SPI_STATE_READY;
		3787	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		3788	{
		3789	/* Call user error callback */
		3790	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3791	hspi->ErrorCallback(hspi);
		3792	#else
		3793	HAL_SPI_ErrorCallback(hspi);
		3794	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3795	}
		3796	else
		3797	{
		3798	/* Call user Rx complete callback */
		3799	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3800	hspi->TxCpltCallback(hspi);
		3801	#else
		3802	HAL_SPI_TxCpltCallback(hspi);
		3803	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3804	}
		3805	}
		3806
		3807	/**
		3808	* @brief Handle abort a Rx transaction.
		3809	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3810	* the configuration information for SPI module.
		3811	* @retval None
		3812	*/
		3813	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
		3814	{
		3815	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3816
		3817	/* Wait until TXE flag is set */
		3818	do
		3819	{
		3820	if (count == 0U)
		3821	{
		3822	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		3823	break;
		3824	}
		3825	count--;
		3826	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3827
		3828	/* Disable SPI Peripheral */
		3829	__HAL_SPI_DISABLE(hspi);
		3830
		3831	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		3832	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
		3833
		3834	/* Read CRC to flush Data Register */
		3835	READ_REG(hspi->Instance->DR);
		3836
		3837	hspi->State = HAL_SPI_STATE_ABORT;
		3838	}
		3839
		3840	/**
		3841	* @brief Handle abort a Tx or Rx/Tx transaction.
		3842	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3843	* the configuration information for SPI module.
		3844	* @retval None
		3845	*/
		3846	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
		3847	{
		3848	/* Disable TXEIE interrupt */
		3849	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
		3850
		3851	/* Disable SPI Peripheral */
		3852	__HAL_SPI_DISABLE(hspi);
		3853
		3854	hspi->State = HAL_SPI_STATE_ABORT;
		3855	}
		3856
		3857	#if (USE_SPI_CRC != 0U)
		3858	/**
		3859	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
		3860	* according to SPI instance, Device type, and revision ID.
		3861	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3862	* the configuration information for SPI module.
		3863	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
		3864	*/
		3865	uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
		3866	{
		3867	#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
		3868	/* Check how to handle this CRC error (workaround to be applied or not) */
		3869	/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
		3870	if(hspi->Instance == SPI2)
		3871	{
		3872	if(hspi->Instance->RXCRCR == 0U)
		3873	{
		3874	return (SPI_INVALID_CRC_ERROR);
		3875	}
		3876	}
		3877	#endif
		3878	/* Prevent unused argument(s) compilation warning */
		3879	UNUSED(hspi);
		3880
		3881	return (SPI_VALID_CRC_ERROR);
		3882	}
		3883	#endif /* USE_SPI_CRC */
		3884	/**
		3885	* @}
		3886	*/
		3887
		3888	#endif /* HAL_SPI_MODULE_ENABLED */
		3889
		3890	/**
		3891	* @}
		3892	*/
		3893
		3894	/**
		3895	* @}
		3896	*/
		3897
		3898	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories dashGPS

(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c – Rev 2