WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_spi.c
		4	* @author MCD Application Team
		5	* @brief SPI HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
		8	* + Initialization and de-initialization functions
		9	* + IO operation functions
		10	* + Peripheral Control functions
		11	* + Peripheral State functions
		12	*
		13	@verbatim
		14	==============================================================================
		15	##### How to use this driver #####
		16	==============================================================================
		17	[..]
		18	The SPI HAL driver can be used as follows:
		19
		20	(#) Declare a SPI_HandleTypeDef handle structure, for example:
		21	SPI_HandleTypeDef hspi;
		22
		23	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
		24	(##) Enable the SPIx interface clock
		25	(##) SPI pins configuration
		26	(+++) Enable the clock for the SPI GPIOs
		27	(+++) Configure these SPI pins as alternate function push-pull
		28	(##) NVIC configuration if you need to use interrupt process
		29	(+++) Configure the SPIx interrupt priority
		30	(+++) Enable the NVIC SPI IRQ handle
		31	(##) DMA Configuration if you need to use DMA process
		32	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
		33	(+++) Enable the DMAx clock
		34	(+++) Configure the DMA handle parameters
		35	(+++) Configure the DMA Tx or Rx Channel
		36	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
		37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
		38
		39	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
		40	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
		41
		42	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
		43	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
		44	by calling the customized HAL_SPI_MspInit() API.
		45	[..]
		46	Circular mode restriction:
		47	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
		48	(##) Master 2Lines RxOnly
		49	(##) Master 1Line Rx
		50	(#) The CRC feature is not managed when the DMA circular mode is enabled
		51	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
		52	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
		53	[..]
		54	Master Receive mode restriction:
		55	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
		56	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
		57	does not initiate a new transfer the following procedure has to be respected:
		58	(##) HAL_SPI_DeInit()
		59	(##) HAL_SPI_Init()
		60
		61	@endverbatim
		62
		63	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
		64	the following tables resume the max SPI frequency reached with data size 8bits/16bits,
		65	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
		66
		67	DataSize = SPI_DATASIZE_8BIT:
		68	+--------------------------------------------------------------------------------------------------+
		69	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		70	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
		71	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		72	\|==================================================================================================\|
		73	\| T \| Polling \| fPCLK/2 \| fPCLK/16 \| NA \| NA \| NA \| NA \|
		74	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		75	\| / \| Interrupt \| fPCLK/8 \| fPCLK/32 \| NA \| NA \| NA \| NA \|
		76	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		77	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
		78	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
		79	\| \| Polling \| fPCLK/4 \| fPCLK/8 \| fPCLK/8 \| fPCLK/16 \| fPCLK/64 \| fPCLK/2 \|
		80	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		81	\| R \| Interrupt \| fPCLK/8 \| fPCLK/16 \| fPCLK/32 \| fPCLK/16 \| fPCLK/64 \| fPCLK/4 \|
		82	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		83	\| \| DMA \| fPCLK/2 \| fPCLK/16 \| fPCLK/8 \| fPCLK/16 \| fPCLK/64 \| fPCLK/2 \|
		84	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
		85	\| \| Polling \| fPCLK/2 \| fPCLK/2 \| NA \| NA \| fPCLK/2 \| fPCLK/32 \|
		86	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		87	\| T \| Interrupt \| fPCLK/8 \| fPCLK/16 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
		88	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		89	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/32 \|
		90	+--------------------------------------------------------------------------------------------------+
		91
		92	DataSize = SPI_DATASIZE_16BIT:
		93	+--------------------------------------------------------------------------------------------------+
		94	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		95	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
		96	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		97	\|==================================================================================================\|
		98	\| T \| Polling \| fPCLK/4 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
		99	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		100	\| / \| Interrupt \| fPCLK/8 \| fPCLK/16 \| NA \| NA \| NA \| NA \|
		101	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		102	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
		103	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
		104	\| \| Polling \| fPCLK/4 \| fPCLK/8 \| fPCLK/4 \| fPCLK/8 \| fPCLK/64 \| fPCLK/2 \|
		105	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		106	\| R \| Interrupt \| fPCLK/8 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/4 \|
		107	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		108	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/16 \| fPCLK/64 \| fPCLK/2 \|
		109	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
		110	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/4 \| fPCLK/8 \|
		111	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		112	\| T \| Interrupt \| fPCLK/4 \| fPCLK/8 \| NA \| NA \| fPCLK/4 \| fPCLK/4 \|
		113	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
		114	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| NA \| NA \| fPCLK/4 \| fPCLK/8 \|
		115	+--------------------------------------------------------------------------------------------------+
		116	[..]
		117	(@) The max SPI frequency depend on SPI data size (8bits, 16bits),
		118	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
		119	(@)
		120	(+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
		121	(+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
		122	(+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
		123	******************************************************************************
		124	* @attention
		125	*
		126	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
		127	*
		128	* Redistribution and use in source and binary forms, with or without modification,
		129	* are permitted provided that the following conditions are met:
		130	* 1. Redistributions of source code must retain the above copyright notice,
		131	* this list of conditions and the following disclaimer.
		132	* 2. Redistributions in binary form must reproduce the above copyright notice,
		133	* this list of conditions and the following disclaimer in the documentation
		134	* and/or other materials provided with the distribution.
		135	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		136	* may be used to endorse or promote products derived from this software
		137	* without specific prior written permission.
		138	*
		139	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		140	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		141	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		142	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		143	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		144	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		145	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		146	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		147	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		148	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		149	*
		150	******************************************************************************
		151	*/
		152
		153	/* Includes ------------------------------------------------------------------*/
		154	#include "stm32f1xx_hal.h"
		155
		156	/** @addtogroup STM32F1xx_HAL_Driver
		157	* @{
		158	*/
		159	/** @defgroup SPI SPI
		160	* @brief SPI HAL module driver
		161	* @{
		162	*/
		163	#ifdef HAL_SPI_MODULE_ENABLED
		164
		165	/* Private typedef -----------------------------------------------------------*/
		166	/* Private defines -----------------------------------------------------------*/
		167	/** @defgroup SPI_Private_Constants SPI Private Constants
		168	* @{
		169	*/
		170	#define SPI_DEFAULT_TIMEOUT 100U
		171	/**
		172	* @}
		173	*/
		174
		175	/* Private macros ------------------------------------------------------------*/
		176	/* Private variables ---------------------------------------------------------*/
		177	/* Private function prototypes -----------------------------------------------*/
		178	/** @addtogroup SPI_Private_Functions
		179	* @{
		180	*/
		181	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
		182	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
		183	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		184	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
		185	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
		186	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		187	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
		188	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
		189	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
		190	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
		191	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
		192	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		193	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		194	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		195	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		196	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		197	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		198	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		199	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		200	#if (USE_SPI_CRC != 0U)
		201	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		202	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		203	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		204	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		205	#endif /* USE_SPI_CRC */
		206	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
		207	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
		208	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
		209	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
		210	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
		211	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		212	/**
		213	* @}
		214	*/
		215
		216	/* Exported functions --------------------------------------------------------*/
		217	/** @defgroup SPI_Exported_Functions SPI Exported Functions
		218	* @{
		219	*/
		220
		221	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
		222	* @brief Initialization and Configuration functions
		223	*
		224	@verbatim
		225	===============================================================================
		226	##### Initialization and de-initialization functions #####
		227	===============================================================================
		228	[..] This subsection provides a set of functions allowing to initialize and
		229	de-initialize the SPIx peripheral:
		230
		231	(+) User must implement HAL_SPI_MspInit() function in which he configures
		232	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
		233
		234	(+) Call the function HAL_SPI_Init() to configure the selected device with
		235	the selected configuration:
		236	(++) Mode
		237	(++) Direction
		238	(++) Data Size
		239	(++) Clock Polarity and Phase
		240	(++) NSS Management
		241	(++) BaudRate Prescaler
		242	(++) FirstBit
		243	(++) TIMode
		244	(++) CRC Calculation
		245	(++) CRC Polynomial if CRC enabled
		246
		247	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
		248	of the selected SPIx peripheral.
		249
		250	@endverbatim
		251	* @{
		252	*/
		253
		254	/**
		255	* @brief Initialize the SPI according to the specified parameters
		256	* in the SPI_InitTypeDef and initialize the associated handle.
		257	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		258	* the configuration information for SPI module.
		259	* @retval HAL status
		260	*/
		261	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
		262	{
		263	/* Check the SPI handle allocation */
		264	if(hspi == NULL)
		265	{
		266	return HAL_ERROR;
		267	}
		268
		269	/* Check the parameters */
		270	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		271	assert_param(IS_SPI_MODE(hspi->Init.Mode));
		272	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
		273	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
		274	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
		275	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
		276	assert_param(IS_SPI_NSS(hspi->Init.NSS));
		277	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
		278	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
		279
		280	#if (USE_SPI_CRC != 0U)
		281	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
		282	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		283	{
		284	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
		285	}
		286	#else
		287	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
		288	#endif /* USE_SPI_CRC */
		289
		290	if(hspi->State == HAL_SPI_STATE_RESET)
		291	{
		292	/* Allocate lock resource and initialize it */
		293	hspi->Lock = HAL_UNLOCKED;
		294
		295	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		296	HAL_SPI_MspInit(hspi);
		297	}
		298
		299	hspi->State = HAL_SPI_STATE_BUSY;
		300
		301	/* Disable the selected SPI peripheral */
		302	__HAL_SPI_DISABLE(hspi);
		303
		304	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
		305	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
		306	Communication speed, First bit and CRC calculation state */
		307	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
		308	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
		309	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
		310
		311	/* Configure : NSS management */
		312	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
		313
		314	#if (USE_SPI_CRC != 0U)
		315	/---------------------------- SPIx CRCPOLY Configuration ------------------/
		316	/* Configure : CRC Polynomial */
		317	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		318	{
		319	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
		320	}
		321	#endif /* USE_SPI_CRC */
		322
		323	#if defined(SPI_I2SCFGR_I2SMOD)
		324	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
		325	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
		326	#endif /* SPI_I2SCFGR_I2SMOD */
		327
		328	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		329	hspi->State = HAL_SPI_STATE_READY;
		330
		331	return HAL_OK;
		332	}
		333
		334	/**
		335	* @brief De Initialize the SPI peripheral.
		336	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		337	* the configuration information for SPI module.
		338	* @retval HAL status
		339	*/
		340	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
		341	{
		342	/* Check the SPI handle allocation */
		343	if(hspi == NULL)
		344	{
		345	return HAL_ERROR;
		346	}
		347
		348	/* Check SPI Instance parameter */
		349	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		350
		351	hspi->State = HAL_SPI_STATE_BUSY;
		352
		353	/* Disable the SPI Peripheral Clock */
		354	__HAL_SPI_DISABLE(hspi);
		355
		356	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		357	HAL_SPI_MspDeInit(hspi);
		358
		359	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		360	hspi->State = HAL_SPI_STATE_RESET;
		361
		362	/* Release Lock */
		363	__HAL_UNLOCK(hspi);
		364
		365	return HAL_OK;
		366	}
		367
		368	/**
		369	* @brief Initialize the SPI MSP.
		370	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		371	* the configuration information for SPI module.
		372	* @retval None
		373	*/
		374	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
		375	{
		376	/* Prevent unused argument(s) compilation warning */
		377	UNUSED(hspi);
		378	/* NOTE : This function should not be modified, when the callback is needed,
		379	the HAL_SPI_MspInit should be implemented in the user file
		380	*/
		381	}
		382
		383	/**
		384	* @brief De-Initialize the SPI MSP.
		385	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		386	* the configuration information for SPI module.
		387	* @retval None
		388	*/
		389	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
		390	{
		391	/* Prevent unused argument(s) compilation warning */
		392	UNUSED(hspi);
		393	/* NOTE : This function should not be modified, when the callback is needed,
		394	the HAL_SPI_MspDeInit should be implemented in the user file
		395	*/
		396	}
		397
		398	/**
		399	* @}
		400	*/
		401
		402	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
		403	* @brief Data transfers functions
		404	*
		405	@verbatim
		406	==============================================================================
		407	##### IO operation functions #####
		408	===============================================================================
		409	[..]
		410	This subsection provides a set of functions allowing to manage the SPI
		411	data transfers.
		412
		413	[..] The SPI supports master and slave mode :
		414
		415	(#) There are two modes of transfer:
		416	(++) Blocking mode: The communication is performed in polling mode.
		417	The HAL status of all data processing is returned by the same function
		418	after finishing transfer.
		419	(++) No-Blocking mode: The communication is performed using Interrupts
		420	or DMA, These APIs return the HAL status.
		421	The end of the data processing will be indicated through the
		422	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
		423	using DMA mode.
		424	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
		425	will be executed respectively at the end of the transmit or Receive process
		426	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
		427
		428	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
		429	exist for 1Line (simplex) and 2Lines (full duplex) modes.
		430
		431	@endverbatim
		432	* @{
		433	*/
		434
		435	/**
		436	* @brief Transmit an amount of data in blocking mode.
		437	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		438	* the configuration information for SPI module.
		439	* @param pData: pointer to data buffer
		440	* @param Size: amount of data to be sent
		441	* @param Timeout: Timeout duration
		442	* @retval HAL status
		443	*/
		444	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		445	{
		446	uint32_t tickstart = 0U;
		447	HAL_StatusTypeDef errorcode = HAL_OK;
		448
		449	/* Check Direction parameter */
		450	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		451
		452	/* Process Locked */
		453	__HAL_LOCK(hspi);
		454
		455	/* Init tickstart for timeout management*/
		456	tickstart = HAL_GetTick();
		457
		458	if(hspi->State != HAL_SPI_STATE_READY)
		459	{
		460	errorcode = HAL_BUSY;
		461	goto error;
		462	}
		463
		464	if((pData == NULL ) \|\| (Size == 0U))
		465	{
		466	errorcode = HAL_ERROR;
		467	goto error;
		468	}
		469
		470	/* Set the transaction information */
		471	hspi->State = HAL_SPI_STATE_BUSY_TX;
		472	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		473	hspi->pTxBuffPtr = (uint8_t *)pData;
		474	hspi->TxXferSize = Size;
		475	hspi->TxXferCount = Size;
		476
		477	/Init field not used in handle to zero /
		478	hspi->pRxBuffPtr = (uint8_t *)NULL;
		479	hspi->RxXferSize = 0U;
		480	hspi->RxXferCount = 0U;
		481	hspi->TxISR = NULL;
		482	hspi->RxISR = NULL;
		483
		484	/* Configure communication direction : 1Line */
		485	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
		486	{
		487	SPI_1LINE_TX(hspi);
		488	}
		489
		490	#if (USE_SPI_CRC != 0U)
		491	/* Reset CRC Calculation */
		492	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		493	{
		494	SPI_RESET_CRC(hspi);
		495	}
		496	#endif /* USE_SPI_CRC */
		497
		498	/* Check if the SPI is already enabled */
		499	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		500	{
		501	/* Enable SPI peripheral */
		502	__HAL_SPI_ENABLE(hspi);
		503	}
		504
		505	/* Transmit data in 16 Bit mode */
		506	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		507	{
		508	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
		509	{
		510	hspi->Instance->DR = ((uint16_t )pData);
		511	pData += sizeof(uint16_t);
		512	hspi->TxXferCount--;
		513	}
		514	/* Transmit data in 16 Bit mode */
		515	while (hspi->TxXferCount > 0U)
		516	{
		517	/* Wait until TXE flag is set to send data */
		518	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		519	{
		520	hspi->Instance->DR = ((uint16_t )pData);
		521	pData += sizeof(uint16_t);
		522	hspi->TxXferCount--;
		523	}
		524	else
		525	{
		526	/* Timeout management */
		527	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
		528	{
		529	errorcode = HAL_TIMEOUT;
		530	goto error;
		531	}
		532	}
		533	}
		534	}
		535	/* Transmit data in 8 Bit mode */
		536	else
		537	{
		538	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
		539	{
		540	((__IO uint8_t)&hspi->Instance->DR) = (*pData);
		541	pData += sizeof(uint8_t);
		542	hspi->TxXferCount--;
		543	}
		544	while (hspi->TxXferCount > 0U)
		545	{
		546	/* Wait until TXE flag is set to send data */
		547	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		548	{
		549	((__IO uint8_t)&hspi->Instance->DR) = (*pData);
		550	pData += sizeof(uint8_t);
		551	hspi->TxXferCount--;
		552	}
		553	else
		554	{
		555	/* Timeout management */
		556	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
		557	{
		558	errorcode = HAL_TIMEOUT;
		559	goto error;
		560	}
		561	}
		562	}
		563	}
		564
		565	/* Wait until TXE flag */
		566	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
		567	{
		568	errorcode = HAL_TIMEOUT;
		569	goto error;
		570	}
		571
		572	/* Check Busy flag */
		573	if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
		574	{
		575	errorcode = HAL_ERROR;
		576	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		577	goto error;
		578	}
		579
		580	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		581	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
		582	{
		583	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		584	}
		585	#if (USE_SPI_CRC != 0U)
		586	/* Enable CRC Transmission */
		587	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		588	{
		589	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		590	}
		591	#endif /* USE_SPI_CRC */
		592
		593	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		594	{
		595	errorcode = HAL_ERROR;
		596	}
		597
		598	error:
		599	hspi->State = HAL_SPI_STATE_READY;
		600	/* Process Unlocked */
		601	__HAL_UNLOCK(hspi);
		602	return errorcode;
		603	}
		604
		605	/**
		606	* @brief Receive an amount of data in blocking mode.
		607	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		608	* the configuration information for SPI module.
		609	* @param pData: pointer to data buffer
		610	* @param Size: amount of data to be received
		611	* @param Timeout: Timeout duration
		612	* @retval HAL status
		613	*/
		614	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		615	{
		616	#if (USE_SPI_CRC != 0U)
		617	__IO uint16_t tmpreg = 0U;
		618	#endif /* USE_SPI_CRC */
		619	uint32_t tickstart = 0U;
		620	HAL_StatusTypeDef errorcode = HAL_OK;
		621
		622	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
		623	{
		624	hspi->State = HAL_SPI_STATE_BUSY_RX;
		625	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		626	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
		627	}
		628
		629	/* Process Locked */
		630	__HAL_LOCK(hspi);
		631
		632	/* Init tickstart for timeout management*/
		633	tickstart = HAL_GetTick();
		634
		635	if(hspi->State != HAL_SPI_STATE_READY)
		636	{
		637	errorcode = HAL_BUSY;
		638	goto error;
		639	}
		640
		641	if((pData == NULL ) \|\| (Size == 0U))
		642	{
		643	errorcode = HAL_ERROR;
		644	goto error;
		645	}
		646
		647	/* Set the transaction information */
		648	hspi->State = HAL_SPI_STATE_BUSY_RX;
		649	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		650	hspi->pRxBuffPtr = (uint8_t *)pData;
		651	hspi->RxXferSize = Size;
		652	hspi->RxXferCount = Size;
		653
		654	/Init field not used in handle to zero /
		655	hspi->pTxBuffPtr = (uint8_t *)NULL;
		656	hspi->TxXferSize = 0U;
		657	hspi->TxXferCount = 0U;
		658	hspi->RxISR = NULL;
		659	hspi->TxISR = NULL;
		660
		661	#if (USE_SPI_CRC != 0U)
		662	/* Reset CRC Calculation */
		663	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		664	{
		665	SPI_RESET_CRC(hspi);
		666	/* this is done to handle the CRCNEXT before the latest data */
		667	hspi->RxXferCount--;
		668	}
		669	#endif /* USE_SPI_CRC */
		670
		671	/* Configure communication direction: 1Line */
		672	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
		673	{
		674	SPI_1LINE_RX(hspi);
		675	}
		676
		677	/* Check if the SPI is already enabled */
		678	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		679	{
		680	/* Enable SPI peripheral */
		681	__HAL_SPI_ENABLE(hspi);
		682	}
		683
		684	/* Receive data in 8 Bit mode */
		685	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
		686	{
		687	/* Transfer loop */
		688	while(hspi->RxXferCount > 0U)
		689	{
		690	/* Check the RXNE flag */
		691	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		692	{
		693	/* read the received data */
		694	(* (uint8_t )pData)= (__IO uint8_t *)&hspi->Instance->DR;
		695	pData += sizeof(uint8_t);
		696	hspi->RxXferCount--;
		697	}
		698	else
		699	{
		700	/* Timeout management */
		701	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
		702	{
		703	errorcode = HAL_TIMEOUT;
		704	goto error;
		705	}
		706	}
		707	}
		708	}
		709	else
		710	{
		711	/* Transfer loop */
		712	while(hspi->RxXferCount > 0U)
		713	{
		714	/* Check the RXNE flag */
		715	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		716	{
		717	((uint16_t)pData) = hspi->Instance->DR;
		718	pData += sizeof(uint16_t);
		719	hspi->RxXferCount--;
		720	}
		721	else
		722	{
		723	/* Timeout management */
		724	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
		725	{
		726	errorcode = HAL_TIMEOUT;
		727	goto error;
		728	}
		729	}
		730	}
		731	}
		732
		733	#if (USE_SPI_CRC != 0U)
		734	/* Handle the CRC Transmission */
		735	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		736	{
		737	/* freeze the CRC before the latest data */
		738	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		739
		740	/* Read the latest data */
		741	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		742	{
		743	/* the latest data has not been received */
		744	errorcode = HAL_TIMEOUT;
		745	goto error;
		746	}
		747
		748	/* Receive last data in 16 Bit mode */
		749	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		750	{
		751	((uint16_t)pData) = hspi->Instance->DR;
		752	}
		753	/* Receive last data in 8 Bit mode */
		754	else
		755	{
		756	((uint8_t )pData) = (__IO uint8_t )&hspi->Instance->DR;
		757	}
		758
		759	/* Wait the CRC data */
		760	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		761	{
		762	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		763	errorcode = HAL_TIMEOUT;
		764	goto error;
		765	}
		766
		767	/* Read CRC to Flush DR and RXNE flag */
		768	tmpreg = hspi->Instance->DR;
		769	/* To avoid GCC warning */
		770	UNUSED(tmpreg);
		771	}
		772	#endif /* USE_SPI_CRC */
		773
		774	/* Check the end of the transaction */
		775	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		776	{
		777	/* Disable SPI peripheral */
		778	__HAL_SPI_DISABLE(hspi);
		779	}
		780
		781	#if (USE_SPI_CRC != 0U)
		782	/* Check if CRC error occurred */
		783	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		784	{
		785	/* Check if CRC error is valid or not (workaround to be applied or not) */
		786	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		787	{
		788	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		789
		790	/* Reset CRC Calculation */
		791	SPI_RESET_CRC(hspi);
		792	}
		793	else
		794	{
		795	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		796	}
		797	}
		798	#endif /* USE_SPI_CRC */
		799
		800	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		801	{
		802	errorcode = HAL_ERROR;
		803	}
		804
		805	error :
		806	hspi->State = HAL_SPI_STATE_READY;
		807	__HAL_UNLOCK(hspi);
		808	return errorcode;
		809	}
		810
		811	/**
		812	* @brief Transmit and Receive an amount of data in blocking mode.
		813	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		814	* the configuration information for SPI module.
		815	* @param pTxData: pointer to transmission data buffer
		816	* @param pRxData: pointer to reception data buffer
		817	* @param Size: amount of data to be sent and received
		818	* @param Timeout: Timeout duration
		819	* @retval HAL status
		820	*/
		821	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
		822	{
		823	uint32_t tmp = 0U, tmp1 = 0U;
		824	#if (USE_SPI_CRC != 0U)
		825	__IO uint16_t tmpreg1 = 0U;
		826	#endif /* USE_SPI_CRC */
		827	uint32_t tickstart = 0U;
		828	/* Variable used to alternate Rx and Tx during transfer */
		829	uint32_t txallowed = 1U;
		830	HAL_StatusTypeDef errorcode = HAL_OK;
		831
		832	/* Check Direction parameter */
		833	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		834
		835	/* Process Locked */
		836	__HAL_LOCK(hspi);
		837
		838	/* Init tickstart for timeout management*/
		839	tickstart = HAL_GetTick();
		840
		841	tmp = hspi->State;
		842	tmp1 = hspi->Init.Mode;
		843
		844	if(!((tmp == HAL_SPI_STATE_READY) \|\| \
		845	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
		846	{
		847	errorcode = HAL_BUSY;
		848	goto error;
		849	}
		850
		851	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		852	{
		853	errorcode = HAL_ERROR;
		854	goto error;
		855	}
		856
		857	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		858	if(hspi->State == HAL_SPI_STATE_READY)
		859	{
		860	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		861	}
		862
		863	/* Set the transaction information */
		864	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		865	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		866	hspi->RxXferCount = Size;
		867	hspi->RxXferSize = Size;
		868	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		869	hspi->TxXferCount = Size;
		870	hspi->TxXferSize = Size;
		871
		872	/Init field not used in handle to zero /
		873	hspi->RxISR = NULL;
		874	hspi->TxISR = NULL;
		875
		876	#if (USE_SPI_CRC != 0U)
		877	/* Reset CRC Calculation */
		878	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		879	{
		880	SPI_RESET_CRC(hspi);
		881	}
		882	#endif /* USE_SPI_CRC */
		883
		884	/* Check if the SPI is already enabled */
		885	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		886	{
		887	/* Enable SPI peripheral */
		888	__HAL_SPI_ENABLE(hspi);
		889	}
		890
		891	/* Transmit and Receive data in 16 Bit mode */
		892	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		893	{
		894	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
		895	{
		896	hspi->Instance->DR = ((uint16_t )pTxData);
		897	pTxData += sizeof(uint16_t);
		898	hspi->TxXferCount--;
		899	}
		900	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		901	{
		902	/* Check TXE flag */
		903	if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
		904	{
		905	hspi->Instance->DR = ((uint16_t )pTxData);
		906	pTxData += sizeof(uint16_t);
		907	hspi->TxXferCount--;
		908	/* Next Data is a reception (Rx). Tx not allowed */
		909	txallowed = 0U;
		910
		911	#if (USE_SPI_CRC != 0U)
		912	/* Enable CRC Transmission */
		913	if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		914	{
		915	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		916	}
		917	#endif /* USE_SPI_CRC */
		918	}
		919
		920	/* Check RXNE flag */
		921	if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
		922	{
		923	((uint16_t )pRxData) = hspi->Instance->DR;
		924	pRxData += sizeof(uint16_t);
		925	hspi->RxXferCount--;
		926	/* Next Data is a Transmission (Tx). Tx is allowed */
		927	txallowed = 1U;
		928	}
		929	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
		930	{
		931	errorcode = HAL_TIMEOUT;
		932	goto error;
		933	}
		934	}
		935	}
		936	/* Transmit and Receive data in 8 Bit mode */
		937	else
		938	{
		939	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
		940	{
		941	((__IO uint8_t)&hspi->Instance->DR) = (*pTxData);
		942	pTxData += sizeof(uint8_t);
		943	hspi->TxXferCount--;
		944	}
		945	while((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		946	{
		947	/* check TXE flag */
		948	if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
		949	{
		950	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
		951	hspi->TxXferCount--;
		952	/* Next Data is a reception (Rx). Tx not allowed */
		953	txallowed = 0U;
		954
		955	#if (USE_SPI_CRC != 0U)
		956	/* Enable CRC Transmission */
		957	if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		958	{
		959	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		960	}
		961	#endif /* USE_SPI_CRC */
		962	}
		963
		964	/* Wait until RXNE flag is reset */
		965	if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
		966	{
		967	((uint8_t )pRxData++) = hspi->Instance->DR;
		968	hspi->RxXferCount--;
		969	/* Next Data is a Transmission (Tx). Tx is allowed */
		970	txallowed = 1U;
		971	}
		972	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
		973	{
		974	errorcode = HAL_TIMEOUT;
		975	goto error;
		976	}
		977	}
		978	}
		979
		980	#if (USE_SPI_CRC != 0U)
		981	/* Read CRC from DR to close CRC calculation process */
		982	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		983	{
		984	/* Wait until TXE flag */
		985	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		986	{
		987	/* Error on the CRC reception */
		988	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		989	errorcode = HAL_TIMEOUT;
		990	goto error;
		991	}
		992	/* Read CRC */
		993	tmpreg1 = hspi->Instance->DR;
		994	/* To avoid GCC warning */
		995	UNUSED(tmpreg1);
		996	}
		997
		998	/* Check if CRC error occurred */
		999	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		1000	{
		1001	/* Check if CRC error is valid or not (workaround to be applied or not) */
		1002	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		1003	{
		1004	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1005
		1006	/* Reset CRC Calculation */
		1007	SPI_RESET_CRC(hspi);
		1008
		1009	errorcode = HAL_ERROR;
		1010	}
		1011	else
		1012	{
		1013	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1014	}
		1015	}
		1016	#endif /* USE_SPI_CRC */
		1017
		1018	/* Wait until TXE flag */
		1019	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
		1020	{
		1021	errorcode = HAL_TIMEOUT;
		1022	goto error;
		1023	}
		1024
		1025	/* Check Busy flag */
		1026	if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
		1027	{
		1028	errorcode = HAL_ERROR;
		1029	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1030	goto error;
		1031	}
		1032
		1033	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		1034	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
		1035	{
		1036	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1037	}
		1038
		1039	error :
		1040	hspi->State = HAL_SPI_STATE_READY;
		1041	__HAL_UNLOCK(hspi);
		1042	return errorcode;
		1043	}
		1044
		1045	/**
		1046	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
		1047	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1048	* the configuration information for SPI module.
		1049	* @param pData: pointer to data buffer
		1050	* @param Size: amount of data to be sent
		1051	* @retval HAL status
		1052	*/
		1053	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1054	{
		1055	HAL_StatusTypeDef errorcode = HAL_OK;
		1056
		1057	/* Check Direction parameter */
		1058	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1059
		1060	/* Process Locked */
		1061	__HAL_LOCK(hspi);
		1062
		1063	if((pData == NULL) \|\| (Size == 0U))
		1064	{
		1065	errorcode = HAL_ERROR;
		1066	goto error;
		1067	}
		1068
		1069	if(hspi->State != HAL_SPI_STATE_READY)
		1070	{
		1071	errorcode = HAL_BUSY;
		1072	goto error;
		1073	}
		1074
		1075	/* Set the transaction information */
		1076	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1077	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1078	hspi->pTxBuffPtr = (uint8_t *)pData;
		1079	hspi->TxXferSize = Size;
		1080	hspi->TxXferCount = Size;
		1081
		1082	/* Init field not used in handle to zero */
		1083	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1084	hspi->RxXferSize = 0U;
		1085	hspi->RxXferCount = 0U;
		1086	hspi->RxISR = NULL;
		1087
		1088	/* Set the function for IT treatment */
		1089	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
		1090	{
		1091	hspi->TxISR = SPI_TxISR_16BIT;
		1092	}
		1093	else
		1094	{
		1095	hspi->TxISR = SPI_TxISR_8BIT;
		1096	}
		1097
		1098	/* Configure communication direction : 1Line */
		1099	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1100	{
		1101	SPI_1LINE_TX(hspi);
		1102	}
		1103
		1104	#if (USE_SPI_CRC != 0U)
		1105	/* Reset CRC Calculation */
		1106	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1107	{
		1108	SPI_RESET_CRC(hspi);
		1109	}
		1110	#endif /* USE_SPI_CRC */
		1111
		1112	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		1113	{
		1114	/* Enable TXE interrupt */
		1115	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
		1116	}
		1117	else
		1118	{
		1119	/* Enable TXE and ERR interrupt */
		1120	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		1121	}
		1122
		1123	/* Check if the SPI is already enabled */
		1124	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		1125	{
		1126	/* Enable SPI peripheral */
		1127	__HAL_SPI_ENABLE(hspi);
		1128	}
		1129
		1130	error :
		1131	__HAL_UNLOCK(hspi);
		1132	return errorcode;
		1133	}
		1134
		1135	/**
		1136	* @brief Receive an amount of data in non-blocking mode with Interrupt.
		1137	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1138	* the configuration information for SPI module.
		1139	* @param pData: pointer to data buffer
		1140	* @param Size: amount of data to be sent
		1141	* @retval HAL status
		1142	*/
		1143	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1144	{
		1145	HAL_StatusTypeDef errorcode = HAL_OK;
		1146
		1147	if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1148	{
		1149	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1150	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1151	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
		1152	}
		1153
		1154	/* Process Locked */
		1155	__HAL_LOCK(hspi);
		1156
		1157	if(hspi->State != HAL_SPI_STATE_READY)
		1158	{
		1159	errorcode = HAL_BUSY;
		1160	goto error;
		1161	}
		1162
		1163	if((pData == NULL) \|\| (Size == 0U))
		1164	{
		1165	errorcode = HAL_ERROR;
		1166	goto error;
		1167	}
		1168
		1169	/* Set the transaction information */
		1170	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1171	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1172	hspi->pRxBuffPtr = (uint8_t *)pData;
		1173	hspi->RxXferSize = Size;
		1174	hspi->RxXferCount = Size;
		1175
		1176	/* Init field not used in handle to zero */
		1177	hspi->pTxBuffPtr = (uint8_t *)NULL;
		1178	hspi->TxXferSize = 0U;
		1179	hspi->TxXferCount = 0U;
		1180	hspi->TxISR = NULL;
		1181
		1182	/* Set the function for IT treatment */
		1183	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
		1184	{
		1185	hspi->RxISR = SPI_RxISR_16BIT;
		1186	}
		1187	else
		1188	{
		1189	hspi->RxISR = SPI_RxISR_8BIT;
		1190	}
		1191
		1192	/* Configure communication direction : 1Line */
		1193	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1194	{
		1195	SPI_1LINE_RX(hspi);
		1196	}
		1197
		1198	#if (USE_SPI_CRC != 0U)
		1199	/* Reset CRC Calculation */
		1200	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1201	{
		1202	SPI_RESET_CRC(hspi);
		1203	}
		1204	#endif /* USE_SPI_CRC */
		1205
		1206	/* Enable TXE and ERR interrupt */
		1207	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		1208
		1209	/* Note : The SPI must be enabled after unlocking current process
		1210	to avoid the risk of SPI interrupt handle execution before current
		1211	process unlock */
		1212
		1213	/* Check if the SPI is already enabled */
		1214	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		1215	{
		1216	/* Enable SPI peripheral */
		1217	__HAL_SPI_ENABLE(hspi);
		1218	}
		1219
		1220	error :
		1221	/* Process Unlocked */
		1222	__HAL_UNLOCK(hspi);
		1223	return errorcode;
		1224	}
		1225
		1226	/**
		1227	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
		1228	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1229	* the configuration information for SPI module.
		1230	* @param pTxData: pointer to transmission data buffer
		1231	* @param pRxData: pointer to reception data buffer
		1232	* @param Size: amount of data to be sent and received
		1233	* @retval HAL status
		1234	*/
		1235	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
		1236	{
		1237	uint32_t tmp = 0U, tmp1 = 0U;
		1238	HAL_StatusTypeDef errorcode = HAL_OK;
		1239
		1240	/* Check Direction parameter */
		1241	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1242
		1243	/* Process locked */
		1244	__HAL_LOCK(hspi);
		1245
		1246	tmp = hspi->State;
		1247	tmp1 = hspi->Init.Mode;
		1248
		1249	if(!((tmp == HAL_SPI_STATE_READY) \|\| \
		1250	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
		1251	{
		1252	errorcode = HAL_BUSY;
		1253	goto error;
		1254	}
		1255
		1256	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0U))
		1257	{
		1258	errorcode = HAL_ERROR;
		1259	goto error;
		1260	}
		1261
		1262	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1263	if(hspi->State == HAL_SPI_STATE_READY)
		1264	{
		1265	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1266	}
		1267
		1268	/* Set the transaction information */
		1269	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1270	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1271	hspi->TxXferSize = Size;
		1272	hspi->TxXferCount = Size;
		1273	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1274	hspi->RxXferSize = Size;
		1275	hspi->RxXferCount = Size;
		1276
		1277	/* Set the function for IT treatment */
		1278	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
		1279	{
		1280	hspi->RxISR = SPI_2linesRxISR_16BIT;
		1281	hspi->TxISR = SPI_2linesTxISR_16BIT;
		1282	}
		1283	else
		1284	{
		1285	hspi->RxISR = SPI_2linesRxISR_8BIT;
		1286	hspi->TxISR = SPI_2linesTxISR_8BIT;
		1287	}
		1288
		1289	#if (USE_SPI_CRC != 0U)
		1290	/* Reset CRC Calculation */
		1291	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1292	{
		1293	SPI_RESET_CRC(hspi);
		1294	}
		1295	#endif /* USE_SPI_CRC */
		1296
		1297	/* Enable TXE, RXNE and ERR interrupt */
		1298	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		1299
		1300	/* Check if the SPI is already enabled */
		1301	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		1302	{
		1303	/* Enable SPI peripheral */
		1304	__HAL_SPI_ENABLE(hspi);
		1305	}
		1306
		1307	error :
		1308	/* Process Unlocked */
		1309	__HAL_UNLOCK(hspi);
		1310	return errorcode;
		1311	}
		1312
		1313	/**
		1314	* @brief Transmit an amount of data in non-blocking mode with DMA.
		1315	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1316	* the configuration information for SPI module.
		1317	* @param pData: pointer to data buffer
		1318	* @param Size: amount of data to be sent
		1319	* @retval HAL status
		1320	*/
		1321	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1322	{
		1323	HAL_StatusTypeDef errorcode = HAL_OK;
		1324
		1325	/* Check Direction parameter */
		1326	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1327
		1328	/* Process Locked */
		1329	__HAL_LOCK(hspi);
		1330
		1331	if(hspi->State != HAL_SPI_STATE_READY)
		1332	{
		1333	errorcode = HAL_BUSY;
		1334	goto error;
		1335	}
		1336
		1337	if((pData == NULL) \|\| (Size == 0U))
		1338	{
		1339	errorcode = HAL_ERROR;
		1340	goto error;
		1341	}
		1342
		1343	/* Set the transaction information */
		1344	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1345	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1346	hspi->pTxBuffPtr = (uint8_t *)pData;
		1347	hspi->TxXferSize = Size;
		1348	hspi->TxXferCount = Size;
		1349
		1350	/* Init field not used in handle to zero */
		1351	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1352	hspi->TxISR = NULL;
		1353	hspi->RxISR = NULL;
		1354	hspi->RxXferSize = 0U;
		1355	hspi->RxXferCount = 0U;
		1356
		1357	/* Configure communication direction : 1Line */
		1358	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1359	{
		1360	SPI_1LINE_TX(hspi);
		1361	}
		1362
		1363	#if (USE_SPI_CRC != 0U)
		1364	/* Reset CRC Calculation */
		1365	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1366	{
		1367	SPI_RESET_CRC(hspi);
		1368	}
		1369	#endif /* USE_SPI_CRC */
		1370
		1371	/* Set the SPI TxDMA Half transfer complete callback */
		1372	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
		1373
		1374	/* Set the SPI TxDMA transfer complete callback */
		1375	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
		1376
		1377	/* Set the DMA error callback */
		1378	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
		1379
		1380	/* Set the DMA AbortCpltCallback */
		1381	hspi->hdmatx->XferAbortCallback = NULL;
		1382
		1383	/* Enable the Tx DMA Stream */
		1384	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
		1385
		1386	/* Check if the SPI is already enabled */
		1387	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		1388	{
		1389	/* Enable SPI peripheral */
		1390	__HAL_SPI_ENABLE(hspi);
		1391	}
		1392
		1393	/* Enable the SPI Error Interrupt Bit */
		1394	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		1395
		1396	/* Enable Tx DMA Request */
		1397	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		1398
		1399	error :
		1400	/* Process Unlocked */
		1401	__HAL_UNLOCK(hspi);
		1402	return errorcode;
		1403	}
		1404
		1405	/**
		1406	* @brief Receive an amount of data in non-blocking mode with DMA.
		1407	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1408	* the configuration information for SPI module.
		1409	* @param pData: pointer to data buffer
		1410	* @note When the CRC feature is enabled the pData Length must be Size + 1.
		1411	* @param Size: amount of data to be sent
		1412	* @retval HAL status
		1413	*/
		1414	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1415	{
		1416	HAL_StatusTypeDef errorcode = HAL_OK;
		1417
		1418	if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
		1419	{
		1420	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1421	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1422	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
		1423	}
		1424
		1425	/* Process Locked */
		1426	__HAL_LOCK(hspi);
		1427
		1428	if(hspi->State != HAL_SPI_STATE_READY)
		1429	{
		1430	errorcode = HAL_BUSY;
		1431	goto error;
		1432	}
		1433
		1434	if((pData == NULL) \|\| (Size == 0U))
		1435	{
		1436	errorcode = HAL_ERROR;
		1437	goto error;
		1438	}
		1439
		1440	/* Set the transaction information */
		1441	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1442	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1443	hspi->pRxBuffPtr = (uint8_t *)pData;
		1444	hspi->RxXferSize = Size;
		1445	hspi->RxXferCount = Size;
		1446
		1447	/Init field not used in handle to zero /
		1448	hspi->RxISR = NULL;
		1449	hspi->TxISR = NULL;
		1450	hspi->TxXferSize = 0U;
		1451	hspi->TxXferCount = 0U;
		1452
		1453	/* Configure communication direction : 1Line */
		1454	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1455	{
		1456	SPI_1LINE_RX(hspi);
		1457	}
		1458
		1459	#if (USE_SPI_CRC != 0U)
		1460	/* Reset CRC Calculation */
		1461	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1462	{
		1463	SPI_RESET_CRC(hspi);
		1464	}
		1465	#endif /* USE_SPI_CRC */
		1466
		1467	/* Set the SPI RxDMA Half transfer complete callback */
		1468	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		1469
		1470	/* Set the SPI Rx DMA transfer complete callback */
		1471	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		1472
		1473	/* Set the DMA error callback */
		1474	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		1475
		1476	/* Set the DMA AbortCpltCallback */
		1477	hspi->hdmarx->XferAbortCallback = NULL;
		1478
		1479	/* Enable the Rx DMA Stream */
		1480	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
		1481
		1482	/* Check if the SPI is already enabled */
		1483	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		1484	{
		1485	/* Enable SPI peripheral */
		1486	__HAL_SPI_ENABLE(hspi);
		1487	}
		1488
		1489	/* Enable the SPI Error Interrupt Bit */
		1490	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		1491
		1492	/* Enable Rx DMA Request */
		1493	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		1494
		1495	error:
		1496	/* Process Unlocked */
		1497	__HAL_UNLOCK(hspi);
		1498	return errorcode;
		1499	}
		1500
		1501	/**
		1502	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
		1503	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1504	* the configuration information for SPI module.
		1505	* @param pTxData: pointer to transmission data buffer
		1506	* @param pRxData: pointer to reception data buffer
		1507	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
		1508	* @param Size: amount of data to be sent
		1509	* @retval HAL status
		1510	*/
		1511	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
		1512	{
		1513	uint32_t tmp = 0U, tmp1 = 0U;
		1514	HAL_StatusTypeDef errorcode = HAL_OK;
		1515
		1516	/* Check Direction parameter */
		1517	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1518
		1519	/* Process locked */
		1520	__HAL_LOCK(hspi);
		1521
		1522	tmp = hspi->State;
		1523	tmp1 = hspi->Init.Mode;
		1524	if(!((tmp == HAL_SPI_STATE_READY) \|\|
		1525	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
		1526	{
		1527	errorcode = HAL_BUSY;
		1528	goto error;
		1529	}
		1530
		1531	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0U))
		1532	{
		1533	errorcode = HAL_ERROR;
		1534	goto error;
		1535	}
		1536
		1537	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1538	if(hspi->State == HAL_SPI_STATE_READY)
		1539	{
		1540	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1541	}
		1542
		1543	/* Set the transaction information */
		1544	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1545	hspi->pTxBuffPtr = (uint8_t*)pTxData;
		1546	hspi->TxXferSize = Size;
		1547	hspi->TxXferCount = Size;
		1548	hspi->pRxBuffPtr = (uint8_t*)pRxData;
		1549	hspi->RxXferSize = Size;
		1550	hspi->RxXferCount = Size;
		1551
		1552	/* Init field not used in handle to zero */
		1553	hspi->RxISR = NULL;
		1554	hspi->TxISR = NULL;
		1555
		1556	#if (USE_SPI_CRC != 0U)
		1557	/* Reset CRC Calculation */
		1558	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1559	{
		1560	SPI_RESET_CRC(hspi);
		1561	}
		1562	#endif /* USE_SPI_CRC */
		1563
		1564	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
		1565	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
		1566	{
		1567	/* Set the SPI Rx DMA Half transfer complete callback */
		1568	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		1569	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		1570	}
		1571	else
		1572	{
		1573	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
		1574	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
		1575	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
		1576	}
		1577
		1578	/* Set the DMA error callback */
		1579	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		1580
		1581	/* Set the DMA AbortCpltCallback */
		1582	hspi->hdmarx->XferAbortCallback = NULL;
		1583
		1584	/* Enable the Rx DMA Stream */
		1585	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
		1586
		1587	/* Enable Rx DMA Request */
		1588	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		1589
		1590	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
		1591	is performed in DMA reception complete callback */
		1592	hspi->hdmatx->XferHalfCpltCallback = NULL;
		1593	hspi->hdmatx->XferCpltCallback = NULL;
		1594	hspi->hdmatx->XferErrorCallback = NULL;
		1595	hspi->hdmatx->XferAbortCallback = NULL;
		1596
		1597	/* Enable the Tx DMA Stream */
		1598	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
		1599
		1600	/* Check if the SPI is already enabled */
		1601	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
		1602	{
		1603	/* Enable SPI peripheral */
		1604	__HAL_SPI_ENABLE(hspi);
		1605	}
		1606	/* Enable the SPI Error Interrupt Bit */
		1607	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		1608
		1609	/* Enable Tx DMA Request */
		1610	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		1611
		1612	error :
		1613	/* Process Unlocked */
		1614	__HAL_UNLOCK(hspi);
		1615	return errorcode;
		1616	}
		1617
		1618	/**
		1619	* @brief Abort ongoing transfer (blocking mode).
		1620	* @param hspi SPI handle.
		1621	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		1622	* started in Interrupt or DMA mode.
		1623	* This procedure performs following operations :
		1624	* - Disable SPI Interrupts (depending of transfer direction)
		1625	* - Disable the DMA transfer in the peripheral register (if enabled)
		1626	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
		1627	* - Set handle State to READY
		1628	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
		1629	* @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
		1630	* before starting new SPI receive process.
		1631	* @retval HAL status
		1632	*/
		1633	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
		1634	{
		1635	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		1636
		1637	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		1638	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		1639	{
		1640	hspi->TxISR = SPI_AbortTx_ISR;
		1641	}
		1642
		1643	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		1644	{
		1645	hspi->RxISR = SPI_AbortRx_ISR;
		1646	}
		1647
		1648	/* Clear ERRIE interrupts in case of DMA Mode */
		1649	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		1650
		1651	/* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
		1652	if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
		1653	{
		1654	/* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
		1655	if(hspi->hdmatx != NULL)
		1656	{
		1657	/* Set the SPI DMA Abort callback :
		1658	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		1659	hspi->hdmatx->XferAbortCallback = NULL;
		1660
		1661	/* Abort DMA Tx Handle linked to SPI Peripheral */
		1662	HAL_DMA_Abort(hspi->hdmatx);
		1663
		1664	/* Disable Tx DMA Request */
		1665	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
		1666
		1667	/* Wait until TXE flag is set */
		1668	do
		1669	{
		1670	if(count-- == 0U)
		1671	{
		1672	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		1673	break;
		1674	}
		1675	}
		1676	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		1677	}
		1678	/* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
		1679	if(hspi->hdmarx != NULL)
		1680	{
		1681	/* Set the SPI DMA Abort callback :
		1682	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		1683	hspi->hdmarx->XferAbortCallback = NULL;
		1684
		1685	/* Abort DMA Rx Handle linked to SPI Peripheral */
		1686	HAL_DMA_Abort(hspi->hdmarx);
		1687
		1688	/* Disable peripheral */
		1689	__HAL_SPI_DISABLE(hspi);
		1690
		1691	/* Disable Rx DMA Request */
		1692	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
		1693
		1694	}
		1695	}
		1696	/* Reset Tx and Rx transfer counters */
		1697	hspi->RxXferCount = 0U;
		1698	hspi->TxXferCount = 0U;
		1699
		1700	/* Reset errorCode */
		1701	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1702
		1703	/* Clear the Error flags in the SR register */
		1704	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1705
		1706	/* Restore hspi->state to ready */
		1707	hspi->State = HAL_SPI_STATE_READY;
		1708
		1709	return HAL_OK;
		1710	}
		1711
		1712	/**
		1713	* @brief Abort ongoing transfer (Interrupt mode).
		1714	* @param hspi SPI handle.
		1715	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		1716	* started in Interrupt or DMA mode.
		1717	* This procedure performs following operations :
		1718	* - Disable SPI Interrupts (depending of transfer direction)
		1719	* - Disable the DMA transfer in the peripheral register (if enabled)
		1720	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
		1721	* - Set handle State to READY
		1722	* - At abort completion, call user abort complete callback
		1723	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
		1724	* considered as completed only when user abort complete callback is executed (not when exiting function).
		1725	* @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
		1726	* before starting new SPI receive process.
		1727	* @retval HAL status
		1728	*/
		1729	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
		1730	{
		1731	uint32_t abortcplt;
		1732
		1733	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
		1734	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		1735	{
		1736	hspi->TxISR = SPI_AbortTx_ISR;
		1737	}
		1738
		1739	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		1740	{
		1741	hspi->RxISR = SPI_AbortRx_ISR;
		1742	}
		1743
		1744	/* Clear ERRIE interrupts in case of DMA Mode */
		1745	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		1746
		1747	abortcplt = 1U;
		1748
		1749	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
		1750	before any call to DMA Abort functions */
		1751	/* DMA Tx Handle is valid */
		1752	if(hspi->hdmatx != NULL)
		1753	{
		1754	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
		1755	Otherwise, set it to NULL */
		1756	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		1757	{
		1758	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
		1759	}
		1760	else
		1761	{
		1762	hspi->hdmatx->XferAbortCallback = NULL;
		1763	}
		1764	}
		1765	/* DMA Rx Handle is valid */
		1766	if(hspi->hdmarx != NULL)
		1767	{
		1768	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
		1769	Otherwise, set it to NULL */
		1770	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		1771	{
		1772	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
		1773	}
		1774	else
		1775	{
		1776	hspi->hdmarx->XferAbortCallback = NULL;
		1777	}
		1778	}
		1779
		1780	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
		1781	if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
		1782	{
		1783	/* Abort the SPI DMA Tx channel */
		1784	if(hspi->hdmatx != NULL)
		1785	{
		1786	/* Abort DMA Tx Handle linked to SPI Peripheral */
		1787	if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
		1788	{
		1789	hspi->hdmatx->XferAbortCallback = NULL;
		1790	}
		1791	else
		1792	{
		1793	abortcplt = 0U;
		1794	}
		1795	}
		1796	/* Abort the SPI DMA Rx channel */
		1797	if(hspi->hdmarx != NULL)
		1798	{
		1799	/* Abort DMA Rx Handle linked to SPI Peripheral */
		1800	if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
		1801	{
		1802	hspi->hdmarx->XferAbortCallback = NULL;
		1803	abortcplt = 1U;
		1804	}
		1805	else
		1806	{
		1807	abortcplt = 0U;
		1808	}
		1809	}
		1810	}
		1811
		1812	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
		1813	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		1814	{
		1815	/* Abort the SPI DMA Tx channel */
		1816	if(hspi->hdmatx != NULL)
		1817	{
		1818	/* Abort DMA Tx Handle linked to SPI Peripheral */
		1819	if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
		1820	{
		1821	hspi->hdmatx->XferAbortCallback = NULL;
		1822	}
		1823	else
		1824	{
		1825	abortcplt = 0U;
		1826	}
		1827	}
		1828	}
		1829	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
		1830	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		1831	{
		1832	/* Abort the SPI DMA Rx channel */
		1833	if(hspi->hdmarx != NULL)
		1834	{
		1835	/* Abort DMA Rx Handle linked to SPI Peripheral */
		1836	if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
		1837	{
		1838	hspi->hdmarx->XferAbortCallback = NULL;
		1839	}
		1840	else
		1841	{
		1842	abortcplt = 0U;
		1843	}
		1844	}
		1845	}
		1846
		1847	if(abortcplt == 1U)
		1848	{
		1849	/* Reset Tx and Rx transfer counters */
		1850	hspi->RxXferCount = 0U;
		1851	hspi->TxXferCount = 0U;
		1852
		1853	/* Reset errorCode */
		1854	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1855
		1856	/* Clear the Error flags in the SR register */
		1857	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1858
		1859	/* Restore hspi->State to Ready */
		1860	hspi->State = HAL_SPI_STATE_READY;
		1861
		1862	/* As no DMA to be aborted, call directly user Abort complete callback */
		1863	HAL_SPI_AbortCpltCallback(hspi);
		1864	}
		1865	return HAL_OK;
		1866	}
		1867
		1868	/**
		1869	* @brief Pause the DMA Transfer.
		1870	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1871	* the configuration information for the specified SPI module.
		1872	* @retval HAL status
		1873	*/
		1874	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
		1875	{
		1876	/* Process Locked */
		1877	__HAL_LOCK(hspi);
		1878
		1879	/* Disable the SPI DMA Tx & Rx requests */
		1880	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		1881
		1882	/* Process Unlocked */
		1883	__HAL_UNLOCK(hspi);
		1884
		1885	return HAL_OK;
		1886	}
		1887
		1888	/**
		1889	* @brief Resume the DMA Transfer.
		1890	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1891	* the configuration information for the specified SPI module.
		1892	* @retval HAL status
		1893	*/
		1894	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
		1895	{
		1896	/* Process Locked */
		1897	__HAL_LOCK(hspi);
		1898
		1899	/* Enable the SPI DMA Tx & Rx requests */
		1900	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		1901
		1902	/* Process Unlocked */
		1903	__HAL_UNLOCK(hspi);
		1904
		1905	return HAL_OK;
		1906	}
		1907
		1908	/**
		1909	* @brief Stop the DMA Transfer.
		1910	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1911	* the configuration information for the specified SPI module.
		1912	* @retval HAL status
		1913	*/
		1914	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
		1915	{
		1916	/* The Lock is not implemented on this API to allow the user application
		1917	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
		1918	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
		1919	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
		1920	*/
		1921
		1922	/* Abort the SPI DMA tx Stream */
		1923	if(hspi->hdmatx != NULL)
		1924	{
		1925	HAL_DMA_Abort(hspi->hdmatx);
		1926	}
		1927	/* Abort the SPI DMA rx Stream */
		1928	if(hspi->hdmarx != NULL)
		1929	{
		1930	HAL_DMA_Abort(hspi->hdmarx);
		1931	}
		1932
		1933	/* Disable the SPI DMA Tx & Rx requests */
		1934	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		1935	hspi->State = HAL_SPI_STATE_READY;
		1936	return HAL_OK;
		1937	}
		1938
		1939	/**
		1940	* @brief Handle SPI interrupt request.
		1941	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		1942	* the configuration information for the specified SPI module.
		1943	* @retval None
		1944	*/
		1945	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
		1946	{
		1947	uint32_t itsource = hspi->Instance->CR2;
		1948	uint32_t itflag = hspi->Instance->SR;
		1949
		1950	/* SPI in mode Receiver ----------------------------------------------------*/
		1951	if(((itflag & SPI_FLAG_OVR) == RESET) &&
		1952	((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
		1953	{
		1954	hspi->RxISR(hspi);
		1955	return;
		1956	}
		1957
		1958	/* SPI in mode Transmitter -------------------------------------------------*/
		1959	if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
		1960	{
		1961	hspi->TxISR(hspi);
		1962	return;
		1963	}
		1964
		1965	/* SPI in Error Treatment --------------------------------------------------*/
		1966	if(((itflag & (SPI_FLAG_MODF \| SPI_FLAG_OVR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
		1967	{
		1968	/* SPI Overrun error interrupt occurred ----------------------------------*/
		1969	if((itflag & SPI_FLAG_OVR) != RESET)
		1970	{
		1971	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
		1972	{
		1973	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
		1974	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1975	}
		1976	else
		1977	{
		1978	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1979	return;
		1980	}
		1981	}
		1982
		1983	/* SPI Mode Fault error interrupt occurred -------------------------------*/
		1984	if((itflag & SPI_FLAG_MODF) != RESET)
		1985	{
		1986	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
		1987	__HAL_SPI_CLEAR_MODFFLAG(hspi);
		1988	}
		1989
		1990	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		1991	{
		1992	/* Disable all interrupts */
		1993	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
		1994
		1995	hspi->State = HAL_SPI_STATE_READY;
		1996	/* Disable the SPI DMA requests if enabled */
		1997	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))\|\|(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
		1998	{
		1999	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
		2000
		2001	/* Abort the SPI DMA Rx channel */
		2002	if(hspi->hdmarx != NULL)
		2003	{
		2004	/* Set the SPI DMA Abort callback :
		2005	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2006	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
		2007	HAL_DMA_Abort_IT(hspi->hdmarx);
		2008	}
		2009	/* Abort the SPI DMA Tx channel */
		2010	if(hspi->hdmatx != NULL)
		2011	{
		2012	/* Set the SPI DMA Abort callback :
		2013	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2014	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
		2015	HAL_DMA_Abort_IT(hspi->hdmatx);
		2016	}
		2017	}
		2018	else
		2019	{
		2020	/* Call user error callback */
		2021	HAL_SPI_ErrorCallback(hspi);
		2022	}
		2023	}
		2024	return;
		2025	}
		2026	}
		2027
		2028	/**
		2029	* @brief Tx Transfer completed callback.
		2030	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2031	* the configuration information for SPI module.
		2032	* @retval None
		2033	*/
		2034	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
		2035	{
		2036	/* Prevent unused argument(s) compilation warning */
		2037	UNUSED(hspi);
		2038	/* NOTE : This function should not be modified, when the callback is needed,
		2039	the HAL_SPI_TxCpltCallback should be implemented in the user file
		2040	*/
		2041	}
		2042
		2043	/**
		2044	* @brief Rx Transfer completed callback.
		2045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2046	* the configuration information for SPI module.
		2047	* @retval None
		2048	*/
		2049	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
		2050	{
		2051	/* Prevent unused argument(s) compilation warning */
		2052	UNUSED(hspi);
		2053	/* NOTE : This function should not be modified, when the callback is needed,
		2054	the HAL_SPI_RxCpltCallback should be implemented in the user file
		2055	*/
		2056	}
		2057
		2058	/**
		2059	* @brief Tx and Rx Transfer completed callback.
		2060	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2061	* the configuration information for SPI module.
		2062	* @retval None
		2063	*/
		2064	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
		2065	{
		2066	/* Prevent unused argument(s) compilation warning */
		2067	UNUSED(hspi);
		2068	/* NOTE : This function should not be modified, when the callback is needed,
		2069	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
		2070	*/
		2071	}
		2072
		2073	/**
		2074	* @brief Tx Half Transfer completed callback.
		2075	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2076	* the configuration information for SPI module.
		2077	* @retval None
		2078	*/
		2079	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2080	{
		2081	/* Prevent unused argument(s) compilation warning */
		2082	UNUSED(hspi);
		2083	/* NOTE : This function should not be modified, when the callback is needed,
		2084	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
		2085	*/
		2086	}
		2087
		2088	/**
		2089	* @brief Rx Half Transfer completed callback.
		2090	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2091	* the configuration information for SPI module.
		2092	* @retval None
		2093	*/
		2094	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2095	{
		2096	/* Prevent unused argument(s) compilation warning */
		2097	UNUSED(hspi);
		2098	/* NOTE : This function should not be modified, when the callback is needed,
		2099	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
		2100	*/
		2101	}
		2102
		2103	/**
		2104	* @brief Tx and Rx Half Transfer callback.
		2105	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2106	* the configuration information for SPI module.
		2107	* @retval None
		2108	*/
		2109	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2110	{
		2111	/* Prevent unused argument(s) compilation warning */
		2112	UNUSED(hspi);
		2113	/* NOTE : This function should not be modified, when the callback is needed,
		2114	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
		2115	*/
		2116	}
		2117
		2118	/**
		2119	* @brief SPI error callback.
		2120	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2121	* the configuration information for SPI module.
		2122	* @retval None
		2123	*/
		2124	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
		2125	{
		2126	/* Prevent unused argument(s) compilation warning */
		2127	UNUSED(hspi);
		2128	/* NOTE : This function should not be modified, when the callback is needed,
		2129	the HAL_SPI_ErrorCallback should be implemented in the user file
		2130	*/
		2131	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
		2132	and user can use HAL_SPI_GetError() API to check the latest error occurred
		2133	*/
		2134	}
		2135
		2136	/**
		2137	* @brief SPI Abort Complete callback.
		2138	* @param hspi SPI handle.
		2139	* @retval None
		2140	*/
		2141	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
		2142	{
		2143	/* Prevent unused argument(s) compilation warning */
		2144	UNUSED(hspi);
		2145
		2146	/* NOTE : This function should not be modified, when the callback is needed,
		2147	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
		2148	*/
		2149	}
		2150
		2151	/**
		2152	* @}
		2153	*/
		2154
		2155	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
		2156	* @brief SPI control functions
		2157	*
		2158	@verbatim
		2159	===============================================================================
		2160	##### Peripheral State and Errors functions #####
		2161	===============================================================================
		2162	[..]
		2163	This subsection provides a set of functions allowing to control the SPI.
		2164	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
		2165	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
		2166	@endverbatim
		2167	* @{
		2168	*/
		2169
		2170	/**
		2171	* @brief Return the SPI handle state.
		2172	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2173	* the configuration information for SPI module.
		2174	* @retval SPI state
		2175	*/
		2176	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
		2177	{
		2178	/* Return SPI handle state */
		2179	return hspi->State;
		2180	}
		2181
		2182	/**
		2183	* @brief Return the SPI error code.
		2184	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2185	* the configuration information for SPI module.
		2186	* @retval SPI error code in bitmap format
		2187	*/
		2188	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
		2189	{
		2190	/* Return SPI ErrorCode */
		2191	return hspi->ErrorCode;
		2192	}
		2193
		2194	/**
		2195	* @}
		2196	*/
		2197
		2198	/**
		2199	* @}
		2200	*/
		2201
		2202	/** @addtogroup SPI_Private_Functions
		2203	* @brief Private functions
		2204	* @{
		2205	*/
		2206
		2207	/**
		2208	* @brief DMA SPI transmit process complete callback.
		2209	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2210	* the configuration information for the specified DMA module.
		2211	* @retval None
		2212	*/
		2213	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
		2214	{
		2215	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2216	uint32_t tickstart = 0U;
		2217
		2218	/* Init tickstart for timeout managment*/
		2219	tickstart = HAL_GetTick();
		2220
		2221	/* DMA Normal Mode */
		2222	if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2223	{
		2224	/* Disable Tx DMA Request */
		2225	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		2226
		2227	/* Check the end of the transaction */
		2228	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2229	{
		2230	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2231	}
		2232
		2233	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
		2234	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
		2235	{
		2236	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2237	}
		2238
		2239	hspi->TxXferCount = 0U;
		2240	hspi->State = HAL_SPI_STATE_READY;
		2241
		2242	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2243	{
		2244	HAL_SPI_ErrorCallback(hspi);
		2245	return;
		2246	}
		2247	}
		2248	HAL_SPI_TxCpltCallback(hspi);
		2249	}
		2250
		2251	/**
		2252	* @brief DMA SPI receive process complete callback.
		2253	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2254	* the configuration information for the specified DMA module.
		2255	* @retval None
		2256	*/
		2257	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
		2258	{
		2259	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2260	#if (USE_SPI_CRC != 0U)
		2261	uint32_t tickstart = 0U;
		2262	__IO uint16_t tmpreg = 0U;
		2263
		2264	/* Init tickstart for timeout management*/
		2265	tickstart = HAL_GetTick();
		2266	#endif /* USE_SPI_CRC */
		2267
		2268	if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2269	{
		2270	#if (USE_SPI_CRC != 0U)
		2271	/* CRC handling */
		2272	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2273	{
		2274	/* Wait until RXNE flag */
		2275	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2276	{
		2277	/* Error on the CRC reception */
		2278	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2279	}
		2280	/* Read CRC */
		2281	tmpreg = hspi->Instance->DR;
		2282	/* To avoid GCC warning */
		2283	UNUSED(tmpreg);
		2284	}
		2285	#endif /* USE_SPI_CRC */
		2286
		2287	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
		2288	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2289
		2290	/* Check the end of the transaction */
		2291	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		2292	{
		2293	/* Disable SPI peripheral */
		2294	__HAL_SPI_DISABLE(hspi);
		2295	}
		2296
		2297	hspi->RxXferCount = 0U;
		2298	hspi->State = HAL_SPI_STATE_READY;
		2299
		2300	#if (USE_SPI_CRC != 0U)
		2301	/* Check if CRC error occurred */
		2302	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		2303	{
		2304	/* Check if CRC error is valid or not (workaround to be applied or not) */
		2305	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		2306	{
		2307	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2308
		2309	/* Reset CRC Calculation */
		2310	SPI_RESET_CRC(hspi);
		2311	}
		2312	else
		2313	{
		2314	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		2315	}
		2316	}
		2317	#endif /* USE_SPI_CRC */
		2318
		2319	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2320	{
		2321	HAL_SPI_ErrorCallback(hspi);
		2322	return;
		2323	}
		2324	}
		2325	HAL_SPI_RxCpltCallback(hspi);
		2326	}
		2327
		2328	/**
		2329	* @brief DMA SPI transmit receive process complete callback.
		2330	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2331	* the configuration information for the specified DMA module.
		2332	* @retval None
		2333	*/
		2334	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		2335	{
		2336	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2337	uint32_t tickstart = 0U;
		2338	#if (USE_SPI_CRC != 0U)
		2339	__IO int16_t tmpreg = 0U;
		2340	#endif /* USE_SPI_CRC */
		2341	/* Init tickstart for timeout management*/
		2342	tickstart = HAL_GetTick();
		2343
		2344	if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2345	{
		2346	#if (USE_SPI_CRC != 0U)
		2347	/* CRC handling */
		2348	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2349	{
		2350	/* Wait the CRC data */
		2351	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2352	{
		2353	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2354	}
		2355	/* Read CRC to Flush DR and RXNE flag */
		2356	tmpreg = hspi->Instance->DR;
		2357	/* To avoid GCC warning */
		2358	UNUSED(tmpreg);
		2359	}
		2360	#endif /* USE_SPI_CRC */
		2361	/* Check the end of the transaction */
		2362	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2363	{
		2364	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2365	}
		2366
		2367	/* Disable Rx/Tx DMA Request */
		2368	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2369
		2370	hspi->TxXferCount = 0U;
		2371	hspi->RxXferCount = 0U;
		2372	hspi->State = HAL_SPI_STATE_READY;
		2373
		2374	#if (USE_SPI_CRC != 0U)
		2375	/* Check if CRC error occurred */
		2376	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		2377	{
		2378	/* Check if CRC error is valid or not (workaround to be applied or not) */
		2379	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		2380	{
		2381	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2382
		2383	/* Reset CRC Calculation */
		2384	SPI_RESET_CRC(hspi);
		2385	}
		2386	else
		2387	{
		2388	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		2389	}
		2390	}
		2391	#endif /* USE_SPI_CRC */
		2392
		2393	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2394	{
		2395	HAL_SPI_ErrorCallback(hspi);
		2396	return;
		2397	}
		2398	}
		2399	HAL_SPI_TxRxCpltCallback(hspi);
		2400	}
		2401
		2402	/**
		2403	* @brief DMA SPI half transmit process complete callback.
		2404	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2405	* the configuration information for the specified DMA module.
		2406	* @retval None
		2407	*/
		2408	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
		2409	{
		2410	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2411
		2412	HAL_SPI_TxHalfCpltCallback(hspi);
		2413	}
		2414
		2415	/**
		2416	* @brief DMA SPI half receive process complete callback
		2417	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2418	* the configuration information for the specified DMA module.
		2419	* @retval None
		2420	*/
		2421	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
		2422	{
		2423	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2424
		2425	HAL_SPI_RxHalfCpltCallback(hspi);
		2426	}
		2427
		2428	/**
		2429	* @brief DMA SPI half transmit receive process complete callback.
		2430	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2431	* the configuration information for the specified DMA module.
		2432	* @retval None
		2433	*/
		2434	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		2435	{
		2436	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2437
		2438	HAL_SPI_TxRxHalfCpltCallback(hspi);
		2439	}
		2440
		2441	/**
		2442	* @brief DMA SPI communication error callback.
		2443	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
		2444	* the configuration information for the specified DMA module.
		2445	* @retval None
		2446	*/
		2447	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
		2448	{
		2449	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2450
		2451	/* Stop the disable DMA transfer on SPI side */
		2452	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2453
		2454	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2455	hspi->State = HAL_SPI_STATE_READY;
		2456	HAL_SPI_ErrorCallback(hspi);
		2457	}
		2458
		2459	/**
		2460	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
		2461	* (To be called at end of DMA Abort procedure following error occurrence).
		2462	* @param hdma DMA handle.
		2463	* @retval None
		2464	*/
		2465	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
		2466	{
		2467	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2468	hspi->RxXferCount = 0U;
		2469	hspi->TxXferCount = 0U;
		2470
		2471	HAL_SPI_ErrorCallback(hspi);
		2472	}
		2473
		2474	/**
		2475	* @brief DMA SPI Tx communication abort callback, when initiated by user
		2476	* (To be called at end of DMA Tx Abort procedure following user abort request).
		2477	* @note When this callback is executed, User Abort complete call back is called only if no
		2478	* Abort still ongoing for Rx DMA Handle.
		2479	* @param hdma DMA handle.
		2480	* @retval None
		2481	*/
		2482	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
		2483	{
		2484	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2485	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2486
		2487	hspi->hdmatx->XferAbortCallback = NULL;
		2488
		2489	/* Disable Tx DMA Request */
		2490	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
		2491
		2492	/* Wait until TXE flag is set */
		2493	do
		2494	{
		2495	if(count-- == 0U)
		2496	{
		2497	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2498	break;
		2499	}
		2500	}
		2501	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		2502
		2503	/* Check if an Abort process is still ongoing */
		2504	if(hspi->hdmarx != NULL)
		2505	{
		2506	if(hspi->hdmarx->XferAbortCallback != NULL)
		2507	{
		2508	return;
		2509	}
		2510	}
		2511
		2512	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
		2513	hspi->RxXferCount = 0U;
		2514	hspi->TxXferCount = 0U;
		2515
		2516	/* Reset errorCode */
		2517	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2518
		2519	/* Restore hspi->State to Ready */
		2520	hspi->State = HAL_SPI_STATE_READY;
		2521
		2522	/* Call user Abort complete callback */
		2523	HAL_SPI_AbortCpltCallback(hspi);
		2524	}
		2525
		2526	/**
		2527	* @brief DMA SPI Rx communication abort callback, when initiated by user
		2528	* (To be called at end of DMA Rx Abort procedure following user abort request).
		2529	* @note When this callback is executed, User Abort complete call back is called only if no
		2530	* Abort still ongoing for Tx DMA Handle.
		2531	* @param hdma DMA handle.
		2532	* @retval None
		2533	*/
		2534	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
		2535	{
		2536	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2537
		2538	/* Disable SPI Peripheral */
		2539	__HAL_SPI_DISABLE(hspi);
		2540
		2541	hspi->hdmarx->XferAbortCallback = NULL;
		2542
		2543	/* Disable Rx DMA Request */
		2544	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		2545
		2546	/* Check if an Abort process is still ongoing */
		2547	if(hspi->hdmatx != NULL)
		2548	{
		2549	if(hspi->hdmatx->XferAbortCallback != NULL)
		2550	{
		2551	return;
		2552	}
		2553	}
		2554
		2555	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
		2556	hspi->RxXferCount = 0U;
		2557	hspi->TxXferCount = 0U;
		2558
		2559	/* Reset errorCode */
		2560	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2561
		2562	/* Clear the Error flags in the SR register */
		2563	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2564
		2565	/* Restore hspi->State to Ready */
		2566	hspi->State = HAL_SPI_STATE_READY;
		2567
		2568	/* Call user Abort complete callback */
		2569	HAL_SPI_AbortCpltCallback(hspi);
		2570	}
		2571
		2572	/**
		2573	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		2574	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2575	* the configuration information for SPI module.
		2576	* @retval None
		2577	*/
		2578	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		2579	{
		2580	/* Receive data in 8bit mode */
		2581	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
		2582	hspi->RxXferCount--;
		2583
		2584	/* check end of the reception */
		2585	if(hspi->RxXferCount == 0U)
		2586	{
		2587	#if (USE_SPI_CRC != 0U)
		2588	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2589	{
		2590	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
		2591	return;
		2592	}
		2593	#endif /* USE_SPI_CRC */
		2594
		2595	/* Disable RXNE interrupt */
		2596	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		2597
		2598	if(hspi->TxXferCount == 0U)
		2599	{
		2600	SPI_CloseRxTx_ISR(hspi);
		2601	}
		2602	}
		2603	}
		2604
		2605	#if (USE_SPI_CRC != 0U)
		2606	/**
		2607	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		2608	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2609	* the configuration information for SPI module.
		2610	* @retval None
		2611	*/
		2612	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		2613	{
		2614	__IO uint8_t tmpreg = 0U;
		2615
		2616	/* Read data register to flush CRC */
		2617	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
		2618
		2619	/* To avoid GCC warning */
		2620
		2621	UNUSED(tmpreg);
		2622
		2623	/* Disable RXNE interrupt */
		2624	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		2625
		2626	if(hspi->TxXferCount == 0U)
		2627	{
		2628	SPI_CloseRxTx_ISR(hspi);
		2629	}
		2630	}
		2631	#endif /* USE_SPI_CRC */
		2632
		2633	/**
		2634	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
		2635	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2636	* the configuration information for SPI module.
		2637	* @retval None
		2638	*/
		2639	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		2640	{
		2641	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
		2642	hspi->TxXferCount--;
		2643
		2644	/* check the end of the transmission */
		2645	if(hspi->TxXferCount == 0U)
		2646	{
		2647	#if (USE_SPI_CRC != 0U)
		2648	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2649	{
		2650	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		2651	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		2652	return;
		2653	}
		2654	#endif /* USE_SPI_CRC */
		2655
		2656	/* Disable TXE interrupt */
		2657	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		2658
		2659	if(hspi->RxXferCount == 0U)
		2660	{
		2661	SPI_CloseRxTx_ISR(hspi);
		2662	}
		2663	}
		2664	}
		2665
		2666	/**
		2667	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
		2668	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2669	* the configuration information for SPI module.
		2670	* @retval None
		2671	*/
		2672	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		2673	{
		2674	/* Receive data in 16 Bit mode */
		2675	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
		2676	hspi->pRxBuffPtr += sizeof(uint16_t);
		2677	hspi->RxXferCount--;
		2678
		2679	if(hspi->RxXferCount == 0U)
		2680	{
		2681	#if (USE_SPI_CRC != 0U)
		2682	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2683	{
		2684	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
		2685	return;
		2686	}
		2687	#endif /* USE_SPI_CRC */
		2688
		2689	/* Disable RXNE interrupt */
		2690	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		2691
		2692	if(hspi->TxXferCount == 0U)
		2693	{
		2694	SPI_CloseRxTx_ISR(hspi);
		2695	}
		2696	}
		2697	}
		2698
		2699	#if (USE_SPI_CRC != 0U)
		2700	/**
		2701	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
		2702	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2703	* the configuration information for SPI module.
		2704	* @retval None
		2705	*/
		2706	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		2707	{
		2708	/* Receive data in 16 Bit mode */
		2709	__IO uint16_t tmpreg = 0U;
		2710
		2711	/* Read data register to flush CRC */
		2712	tmpreg = hspi->Instance->DR;
		2713
		2714	/* To avoid GCC warning */
		2715	UNUSED(tmpreg);
		2716
		2717	/* Disable RXNE interrupt */
		2718	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		2719
		2720	SPI_CloseRxTx_ISR(hspi);
		2721	}
		2722	#endif /* USE_SPI_CRC */
		2723
		2724	/**
		2725	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
		2726	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2727	* the configuration information for SPI module.
		2728	* @retval None
		2729	*/
		2730	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		2731	{
		2732	/* Transmit data in 16 Bit mode */
		2733	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		2734	hspi->pTxBuffPtr += sizeof(uint16_t);
		2735	hspi->TxXferCount--;
		2736
		2737	/* Enable CRC Transmission */
		2738	if(hspi->TxXferCount == 0U)
		2739	{
		2740	#if (USE_SPI_CRC != 0U)
		2741	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2742	{
		2743	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		2744	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		2745	return;
		2746	}
		2747	#endif /* USE_SPI_CRC */
		2748
		2749	/* Disable TXE interrupt */
		2750	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		2751
		2752	if(hspi->RxXferCount == 0U)
		2753	{
		2754	SPI_CloseRxTx_ISR(hspi);
		2755	}
		2756	}
		2757	}
		2758
		2759	#if (USE_SPI_CRC != 0U)
		2760	/**
		2761	* @brief Manage the CRC 8-bit receive in Interrupt context.
		2762	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2763	* the configuration information for SPI module.
		2764	* @retval None
		2765	*/
		2766	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		2767	{
		2768	__IO uint8_t tmpreg = 0U;
		2769
		2770	/* Read data register to flush CRC */
		2771	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
		2772
		2773	/* To avoid GCC warning */
		2774	UNUSED(tmpreg);
		2775
		2776	SPI_CloseRx_ISR(hspi);
		2777	}
		2778	#endif /* USE_SPI_CRC */
		2779
		2780	/**
		2781	* @brief Manage the receive 8-bit in Interrupt context.
		2782	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2783	* the configuration information for SPI module.
		2784	* @retval None
		2785	*/
		2786	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		2787	{
		2788	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
		2789	hspi->RxXferCount--;
		2790
		2791	#if (USE_SPI_CRC != 0U)
		2792	/* Enable CRC Transmission */
		2793	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		2794	{
		2795	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		2796	}
		2797	#endif /* USE_SPI_CRC */
		2798
		2799	if(hspi->RxXferCount == 0U)
		2800	{
		2801	#if (USE_SPI_CRC != 0U)
		2802	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2803	{
		2804	hspi->RxISR = SPI_RxISR_8BITCRC;
		2805	return;
		2806	}
		2807	#endif /* USE_SPI_CRC */
		2808	SPI_CloseRx_ISR(hspi);
		2809	}
		2810	}
		2811
		2812	#if (USE_SPI_CRC != 0U)
		2813	/**
		2814	* @brief Manage the CRC 16-bit receive in Interrupt context.
		2815	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2816	* the configuration information for SPI module.
		2817	* @retval None
		2818	*/
		2819	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		2820	{
		2821	__IO uint16_t tmpreg = 0U;
		2822
		2823	/* Read data register to flush CRC */
		2824	tmpreg = hspi->Instance->DR;
		2825
		2826	/* To avoid GCC warning */
		2827	UNUSED(tmpreg);
		2828
		2829	/* Disable RXNE and ERR interrupt */
		2830	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		2831
		2832	SPI_CloseRx_ISR(hspi);
		2833	}
		2834	#endif /* USE_SPI_CRC */
		2835
		2836	/**
		2837	* @brief Manage the 16-bit receive in Interrupt context.
		2838	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2839	* the configuration information for SPI module.
		2840	* @retval None
		2841	*/
		2842	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		2843	{
		2844	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
		2845	hspi->pRxBuffPtr += sizeof(uint16_t);
		2846	hspi->RxXferCount--;
		2847
		2848	#if (USE_SPI_CRC != 0U)
		2849	/* Enable CRC Transmission */
		2850	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		2851	{
		2852	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		2853	}
		2854	#endif /* USE_SPI_CRC */
		2855
		2856	if(hspi->RxXferCount == 0U)
		2857	{
		2858	#if (USE_SPI_CRC != 0U)
		2859	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2860	{
		2861	hspi->RxISR = SPI_RxISR_16BITCRC;
		2862	return;
		2863	}
		2864	#endif /* USE_SPI_CRC */
		2865	SPI_CloseRx_ISR(hspi);
		2866	}
		2867	}
		2868
		2869	/**
		2870	* @brief Handle the data 8-bit transmit in Interrupt mode.
		2871	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2872	* the configuration information for SPI module.
		2873	* @retval None
		2874	*/
		2875	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		2876	{
		2877	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
		2878	hspi->TxXferCount--;
		2879
		2880	if(hspi->TxXferCount == 0U)
		2881	{
		2882	#if (USE_SPI_CRC != 0U)
		2883	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2884	{
		2885	/* Enable CRC Transmission */
		2886	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		2887	}
		2888	#endif /* USE_SPI_CRC */
		2889	SPI_CloseTx_ISR(hspi);
		2890	}
		2891	}
		2892
		2893	/**
		2894	* @brief Handle the data 16-bit transmit in Interrupt mode.
		2895	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2896	* the configuration information for SPI module.
		2897	* @retval None
		2898	*/
		2899	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		2900	{
		2901	/* Transmit data in 16 Bit mode */
		2902	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		2903	hspi->pTxBuffPtr += sizeof(uint16_t);
		2904	hspi->TxXferCount--;
		2905
		2906	if(hspi->TxXferCount == 0U)
		2907	{
		2908	#if (USE_SPI_CRC != 0U)
		2909	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2910	{
		2911	/* Enable CRC Transmission */
		2912	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		2913	}
		2914	#endif /* USE_SPI_CRC */
		2915	SPI_CloseTx_ISR(hspi);
		2916	}
		2917	}
		2918
		2919	/**
		2920	* @brief Handle SPI Communication Timeout.
		2921	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2922	* the configuration information for SPI module.
		2923	* @param Flag: SPI flag to check
		2924	* @param State: flag state to check
		2925	* @param Timeout: Timeout duration
		2926	* @param Tickstart: tick start value
		2927	* @retval HAL status
		2928	*/
		2929	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
		2930	{
		2931	while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
		2932	{
		2933	if(Timeout != HAL_MAX_DELAY)
		2934	{
		2935	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) >= Timeout))
		2936	{
		2937	/* Disable the SPI and reset the CRC: the CRC value should be cleared
		2938	on both master and slave sides in order to resynchronize the master
		2939	and slave for their respective CRC calculation */
		2940
		2941	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
		2942	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		2943
		2944	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		2945	{
		2946	/* Disable SPI peripheral */
		2947	__HAL_SPI_DISABLE(hspi);
		2948	}
		2949
		2950	/* Reset CRC Calculation */
		2951	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2952	{
		2953	SPI_RESET_CRC(hspi);
		2954	}
		2955
		2956	hspi->State= HAL_SPI_STATE_READY;
		2957
		2958	/* Process Unlocked */
		2959	__HAL_UNLOCK(hspi);
		2960
		2961	return HAL_TIMEOUT;
		2962	}
		2963	}
		2964	}
		2965
		2966	return HAL_OK;
		2967	}
		2968	/**
		2969	* @brief Handle to check BSY flag before start a new transaction.
		2970	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2971	* the configuration information for SPI module.
		2972	* @param Timeout: Timeout duration
		2973	* @param Tickstart: tick start value
		2974	* @retval HAL status
		2975	*/
		2976	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		2977	{
		2978	/* Control the BSY flag */
		2979	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		2980	{
		2981	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2982	return HAL_TIMEOUT;
		2983	}
		2984	return HAL_OK;
		2985	}
		2986
		2987	/**
		2988	* @brief Handle the end of the RXTX transaction.
		2989	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		2990	* the configuration information for SPI module.
		2991	* @retval None
		2992	*/
		2993	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
		2994	{
		2995	uint32_t tickstart = 0U;
		2996	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2997	/* Init tickstart for timeout managment*/
		2998	tickstart = HAL_GetTick();
		2999
		3000	/* Disable ERR interrupt */
		3001	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		3002
		3003	/* Wait until TXE flag is set */
		3004	do
		3005	{
		3006	if(count-- == 0U)
		3007	{
		3008	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3009	break;
		3010	}
		3011	}
		3012	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3013
		3014	/* Check the end of the transaction */
		3015	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
		3016	{
		3017	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3018	}
		3019
		3020	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3021	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3022	{
		3023	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3024	}
		3025
		3026	#if (USE_SPI_CRC != 0U)
		3027	/* Check if CRC error occurred */
		3028	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		3029	{
		3030	/* Check if CRC error is valid or not (workaround to be applied or not) */
		3031	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		3032	{
		3033	hspi->State = HAL_SPI_STATE_READY;
		3034	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3035
		3036	/* Reset CRC Calculation */
		3037	SPI_RESET_CRC(hspi);
		3038
		3039	HAL_SPI_ErrorCallback(hspi);
		3040	}
		3041	else
		3042	{
		3043	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3044	}
		3045	}
		3046	else
		3047	{
		3048	#endif /* USE_SPI_CRC */
		3049	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		3050	{
		3051	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
		3052	{
		3053	hspi->State = HAL_SPI_STATE_READY;
		3054	HAL_SPI_RxCpltCallback(hspi);
		3055	}
		3056	else
		3057	{
		3058	hspi->State = HAL_SPI_STATE_READY;
		3059	HAL_SPI_TxRxCpltCallback(hspi);
		3060	}
		3061	}
		3062	else
		3063	{
		3064	hspi->State = HAL_SPI_STATE_READY;
		3065	HAL_SPI_ErrorCallback(hspi);
		3066	}
		3067	#if (USE_SPI_CRC != 0U)
		3068	}
		3069	#endif /* USE_SPI_CRC */
		3070	}
		3071
		3072	/**
		3073	* @brief Handle the end of the RX transaction.
		3074	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3075	* the configuration information for SPI module.
		3076	* @retval None
		3077	*/
		3078	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
		3079	{
		3080	/* Disable RXNE and ERR interrupt */
		3081	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3082
		3083	/* Check the end of the transaction */
		3084	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3085	{
		3086	/* Disable SPI peripheral */
		3087	__HAL_SPI_DISABLE(hspi);
		3088	}
		3089
		3090	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3091	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3092	{
		3093	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3094	}
		3095	hspi->State = HAL_SPI_STATE_READY;
		3096
		3097	#if (USE_SPI_CRC != 0U)
		3098	/* Check if CRC error occurred */
		3099	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		3100	{
		3101	/* Check if CRC error is valid or not (workaround to be applied or not) */
		3102	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		3103	{
		3104	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3105
		3106	/* Reset CRC Calculation */
		3107	SPI_RESET_CRC(hspi);
		3108
		3109	HAL_SPI_ErrorCallback(hspi);
		3110	}
		3111	else
		3112	{
		3113	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3114	}
		3115	}
		3116	else
		3117	{
		3118	#endif /* USE_SPI_CRC */
		3119	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		3120	{
		3121	HAL_SPI_RxCpltCallback(hspi);
		3122	}
		3123	else
		3124	{
		3125	HAL_SPI_ErrorCallback(hspi);
		3126	}
		3127	#if (USE_SPI_CRC != 0U)
		3128	}
		3129	#endif /* USE_SPI_CRC */
		3130	}
		3131
		3132	/**
		3133	* @brief Handle the end of the TX transaction.
		3134	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3135	* the configuration information for SPI module.
		3136	* @retval None
		3137	*/
		3138	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
		3139	{
		3140	uint32_t tickstart = 0U;
		3141	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3142
		3143	/* Init tickstart for timeout management*/
		3144	tickstart = HAL_GetTick();
		3145
		3146	/* Wait until TXE flag is set */
		3147	do
		3148	{
		3149	if(count-- == 0U)
		3150	{
		3151	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3152	break;
		3153	}
		3154	}
		3155	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3156
		3157	/* Disable TXE and ERR interrupt */
		3158	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		3159
		3160	/* Check Busy flag */
		3161	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3162	{
		3163	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3164	}
		3165
		3166	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3167	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3168	{
		3169	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3170	}
		3171
		3172	hspi->State = HAL_SPI_STATE_READY;
		3173	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		3174	{
		3175	HAL_SPI_ErrorCallback(hspi);
		3176	}
		3177	else
		3178	{
		3179	HAL_SPI_TxCpltCallback(hspi);
		3180	}
		3181	}
		3182
		3183	/**
		3184	* @}
		3185	*/
		3186
		3187	/**
		3188	* @brief Handle abort a Tx or Rx transaction.
		3189	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3190	* the configuration information for SPI module.
		3191	* @retval None
		3192	*/
		3193	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
		3194	{
		3195	__IO uint32_t tmpreg = 0U;
		3196	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3197
		3198	/* Wait until TXE flag is set */
		3199	do
		3200	{
		3201	if(count-- == 0U)
		3202	{
		3203	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3204	break;
		3205	}
		3206	}
		3207	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3208
		3209	/* Disable SPI Peripheral */
		3210	__HAL_SPI_DISABLE(hspi);
		3211
		3212	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		3213	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
		3214
		3215	/* Flush DR Register */
		3216	tmpreg = ((__IO uint32_t )&hspi->Instance->DR);
		3217
		3218	/* To avoid GCC warning */
		3219	UNUSED(tmpreg);
		3220	}
		3221
		3222	/**
		3223	* @brief Handle abort a Tx or Rx transaction.
		3224	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3225	* the configuration information for SPI module.
		3226	* @retval None
		3227	*/
		3228	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
		3229	{
		3230	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		3231	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
		3232
		3233	/* Disable SPI Peripheral */
		3234	__HAL_SPI_DISABLE(hspi);
		3235	}
		3236
		3237	/**
		3238	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
		3239	* according to SPI instance, Device type, and revision ID.
		3240	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3241	* the configuration information for SPI module.
		3242	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
		3243	*/
		3244	__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
		3245	{
		3246	/* Prevent unused argument(s) compilation warning */
		3247	UNUSED(hspi);
		3248
		3249	return (SPI_VALID_CRC_ERROR);
		3250	}
		3251	/**
		3252	* @}
		3253	*/
		3254	#endif /* HAL_SPI_MODULE_ENABLED */
		3255
		3256	/**
		3257	* @}
		3258	*/
		3259
		3260	/**
		3261	* @}
		3262	*/
		3263
		3264	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories LedShow

(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c – Rev 2