WebSVN – EDIS_Ignition – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c

Rev	Author	Line No.	Line
18	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_spi.c
		4	* @author MCD Application Team
		5	* @brief SPI HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
		8	* + Initialization and de-initialization functions
		9	* + IO operation functions
		10	* + Peripheral Control functions
		11	* + Peripheral State functions
		12	******************************************************************************
		13	* @attention
		14	*
		15	* Copyright (c) 2016 STMicroelectronics.
		16	* All rights reserved.
		17	*
		18	* This software is licensed under terms that can be found in the LICENSE file
		19	* in the root directory of this software component.
		20	* If no LICENSE file comes with this software, it is provided AS-IS.
		21	*
		22	******************************************************************************
		23	@verbatim
		24	==============================================================================
		25	##### How to use this driver #####
		26	==============================================================================
		27	[..]
		28	The SPI HAL driver can be used as follows:
		29
		30	(#) Declare a SPI_HandleTypeDef handle structure, for example:
		31	SPI_HandleTypeDef hspi;
		32
		33	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
		34	(##) Enable the SPIx interface clock
		35	(##) SPI pins configuration
		36	(+++) Enable the clock for the SPI GPIOs
		37	(+++) Configure these SPI pins as alternate function push-pull
		38	(##) NVIC configuration if you need to use interrupt process
		39	(+++) Configure the SPIx interrupt priority
		40	(+++) Enable the NVIC SPI IRQ handle
		41	(##) DMA Configuration if you need to use DMA process
		42	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
		43	(+++) Enable the DMAx clock
		44	(+++) Configure the DMA handle parameters
		45	(+++) Configure the DMA Tx or Rx Stream/Channel
		46	(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
		47	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
		48
		49	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
		50	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
		51
		52	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
		53	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
		54	by calling the customized HAL_SPI_MspInit() API.
		55	[..]
		56	Circular mode restriction:
		57	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
		58	(##) Master 2Lines RxOnly
		59	(##) Master 1Line Rx
		60	(#) The CRC feature is not managed when the DMA circular mode is enabled
		61	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
		62	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
		63	[..]
		64	Master Receive mode restriction:
		65	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
		66	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
		67	does not initiate a new transfer the following procedure has to be respected:
		68	(##) HAL_SPI_DeInit()
		69	(##) HAL_SPI_Init()
		70	[..]
		71	Callback registration:
		72
		73	(#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
		74	allows the user to configure dynamically the driver callbacks.
		75	Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
		76
		77	Function HAL_SPI_RegisterCallback() allows to register following callbacks:
		78	(++) TxCpltCallback : SPI Tx Completed callback
		79	(++) RxCpltCallback : SPI Rx Completed callback
		80	(++) TxRxCpltCallback : SPI TxRx Completed callback
		81	(++) TxHalfCpltCallback : SPI Tx Half Completed callback
		82	(++) RxHalfCpltCallback : SPI Rx Half Completed callback
		83	(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
		84	(++) ErrorCallback : SPI Error callback
		85	(++) AbortCpltCallback : SPI Abort callback
		86	(++) MspInitCallback : SPI Msp Init callback
		87	(++) MspDeInitCallback : SPI Msp DeInit callback
		88	This function takes as parameters the HAL peripheral handle, the Callback ID
		89	and a pointer to the user callback function.
		90
		91
		92	(#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
		93	weak function.
		94	HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
		95	and the Callback ID.
		96	This function allows to reset following callbacks:
		97	(++) TxCpltCallback : SPI Tx Completed callback
		98	(++) RxCpltCallback : SPI Rx Completed callback
		99	(++) TxRxCpltCallback : SPI TxRx Completed callback
		100	(++) TxHalfCpltCallback : SPI Tx Half Completed callback
		101	(++) RxHalfCpltCallback : SPI Rx Half Completed callback
		102	(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
		103	(++) ErrorCallback : SPI Error callback
		104	(++) AbortCpltCallback : SPI Abort callback
		105	(++) MspInitCallback : SPI Msp Init callback
		106	(++) MspDeInitCallback : SPI Msp DeInit callback
		107
		108	[..]
		109	By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
		110	all callbacks are set to the corresponding weak functions:
		111	examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
		112	Exception done for MspInit and MspDeInit functions that are
		113	reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
		114	these callbacks are null (not registered beforehand).
		115	If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
		116	keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
		117
		118	[..]
		119	Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
		120	Exception done MspInit/MspDeInit functions that can be registered/unregistered
		121	in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
		122	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
		123	Then, the user first registers the MspInit/MspDeInit user callbacks
		124	using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
		125	or HAL_SPI_Init() function.
		126
		127	[..]
		128	When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
		129	not defined, the callback registering feature is not available
		130	and weak (surcharged) callbacks are used.
		131
		132	[..]
		133	Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
		134	the following table resume the max SPI frequency reached with data size 8bits/16bits,
		135	according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
		136
		137	@endverbatim
		138
		139	Additional table :
		140
		141	DataSize = SPI_DATASIZE_8BIT:
		142	+----------------------------------------------------------------------------------------------+
		143	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		144	\| Process \| Transfer mode \|---------------------\|----------------------\|----------------------\|
		145	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		146	\|==============================================================================================\|
		147	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		148	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		149	\| / \| Interrupt \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
		150	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		151	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		152	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		153	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
		154	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		155	\| R \| Interrupt \| Fpclk/8 \| Fpclk/8 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
		156	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		157	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
		158	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		159	\| \| Polling \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
		160	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		161	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
		162	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		163	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
		164	+----------------------------------------------------------------------------------------------+
		165
		166	DataSize = SPI_DATASIZE_16BIT:
		167	+----------------------------------------------------------------------------------------------+
		168	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		169	\| Process \| Transfer mode \|---------------------\|----------------------\|----------------------\|
		170	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		171	\|==============================================================================================\|
		172	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		173	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		174	\| / \| Interrupt \| Fpclk/4 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
		175	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		176	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		177	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		178	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/32 \| Fpclk/2 \|
		179	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		180	\| R \| Interrupt \| Fpclk/4 \| Fpclk/4 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
		181	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		182	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
		183	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		184	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/32 \|
		185	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		186	\| T \| Interrupt \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
		187	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		188	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
		189	+----------------------------------------------------------------------------------------------+
		190	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
		191	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
		192	@note
		193	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
		194	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
		195	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
		196
		197	*/
		198
		199	/* Includes ------------------------------------------------------------------*/
		200	#include "stm32f1xx_hal.h"
		201
		202	/** @addtogroup STM32F1xx_HAL_Driver
		203	* @{
		204	*/
		205
		206	/** @defgroup SPI SPI
		207	* @brief SPI HAL module driver
		208	* @{
		209	*/
		210	#ifdef HAL_SPI_MODULE_ENABLED
		211
		212	/* Private typedef -----------------------------------------------------------*/
		213	/* Private defines -----------------------------------------------------------*/
		214	#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE)
		215	/* CRC WORKAROUND FEATURE: Variable used to determine if device is impacted by implementation
		216	* of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround
		217	* has to be applied, are:
		218	* - STM32F101CDE/STM32F103CDE
		219	* - Revision ID : Z
		220	* - SPI2
		221	* - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
		222	* the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
		223	* + If the value is 0, the complete data transfer is successful.
		224	* + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
		225	* If CRCERR is found reset, the complete data transfer is considered successful.
		226	*
		227	* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
		228	* CRC errors wrongly detected
		229	*/
		230	/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode
		231	* Revision ID information is only available in Debug mode, so Workaround could not be implemented
		232	* to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
		233	* So, in case of Revision Z F101 or F103 devices, below define should be assigned to 1.
		234	*/
		235	#define USE_SPI_CRC_ERROR_WORKAROUND 0U
		236	#endif /* USE_SPI_CRC */
		237	/** @defgroup SPI_Private_Constants SPI Private Constants
		238	* @{
		239	*/
		240	#define SPI_DEFAULT_TIMEOUT 100U
		241	/**
		242	* @}
		243	*/
		244
		245	/* Private macros ------------------------------------------------------------*/
		246	/* Private variables ---------------------------------------------------------*/
		247	/* Private function prototypes -----------------------------------------------*/
		248	/** @defgroup SPI_Private_Functions SPI Private Functions
		249	* @{
		250	*/
		251	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
		252	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
		253	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		254	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
		255	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
		256	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		257	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
		258	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
		259	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
		260	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
		261	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
		262	uint32_t Timeout, uint32_t Tickstart);
		263	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		264	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		265	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		266	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		267	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		268	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		269	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		270	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		271	#if (USE_SPI_CRC != 0U)
		272	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		273	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		274	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		275	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		276	#endif /* USE_SPI_CRC */
		277	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
		278	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
		279	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
		280	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
		281	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
		282	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		283	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		284	/**
		285	* @}
		286	*/
		287
		288	/* Exported functions --------------------------------------------------------*/
		289	/** @defgroup SPI_Exported_Functions SPI Exported Functions
		290	* @{
		291	*/
		292
		293	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
		294	* @brief Initialization and Configuration functions
		295	*
		296	@verbatim
		297	===============================================================================
		298	##### Initialization and de-initialization functions #####
		299	===============================================================================
		300	[..] This subsection provides a set of functions allowing to initialize and
		301	de-initialize the SPIx peripheral:
		302
		303	(+) User must implement HAL_SPI_MspInit() function in which he configures
		304	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
		305
		306	(+) Call the function HAL_SPI_Init() to configure the selected device with
		307	the selected configuration:
		308	(++) Mode
		309	(++) Direction
		310	(++) Data Size
		311	(++) Clock Polarity and Phase
		312	(++) NSS Management
		313	(++) BaudRate Prescaler
		314	(++) FirstBit
		315	(++) TIMode
		316	(++) CRC Calculation
		317	(++) CRC Polynomial if CRC enabled
		318
		319	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
		320	of the selected SPIx peripheral.
		321
		322	@endverbatim
		323	* @{
		324	*/
		325
		326	/**
		327	* @brief Initialize the SPI according to the specified parameters
		328	* in the SPI_InitTypeDef and initialize the associated handle.
		329	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		330	* the configuration information for SPI module.
		331	* @retval HAL status
		332	*/
		333	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
		334	{
		335	/* Check the SPI handle allocation */
		336	if (hspi == NULL)
		337	{
		338	return HAL_ERROR;
		339	}
		340
		341	/* Check the parameters */
		342	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		343	assert_param(IS_SPI_MODE(hspi->Init.Mode));
		344	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
		345	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
		346	assert_param(IS_SPI_NSS(hspi->Init.NSS));
		347	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
		348	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
		349	/* TI mode is not supported on this device.
		350	TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
		351	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
		352	if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
		353	{
		354	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
		355	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
		356
		357	if (hspi->Init.Mode == SPI_MODE_MASTER)
		358	{
		359	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
		360	}
		361	else
		362	{
		363	/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
		364	hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
		365	}
		366	}
		367	else
		368	{
		369	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
		370
		371	/* Force polarity and phase to TI protocaol requirements */
		372	hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
		373	hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
		374	}
		375	#if (USE_SPI_CRC != 0U)
		376	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
		377	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		378	{
		379	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
		380	}
		381	#else
		382	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
		383	#endif /* USE_SPI_CRC */
		384
		385	if (hspi->State == HAL_SPI_STATE_RESET)
		386	{
		387	/* Allocate lock resource and initialize it */
		388	hspi->Lock = HAL_UNLOCKED;
		389
		390	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		391	/* Init the SPI Callback settings */
		392	hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
		393	hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
		394	hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
		395	hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
		396	hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
		397	hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
		398	hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
		399	hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
		400
		401	if (hspi->MspInitCallback == NULL)
		402	{
		403	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		404	}
		405
		406	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		407	hspi->MspInitCallback(hspi);
		408	#else
		409	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		410	HAL_SPI_MspInit(hspi);
		411	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		412	}
		413
		414	hspi->State = HAL_SPI_STATE_BUSY;
		415
		416	/* Disable the selected SPI peripheral */
		417	__HAL_SPI_DISABLE(hspi);
		418
		419	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
		420	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
		421	Communication speed, First bit and CRC calculation state */
		422	WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR \| SPI_CR1_SSI)) \|
		423	(hspi->Init.Direction & (SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE)) \|
		424	(hspi->Init.DataSize & SPI_CR1_DFF) \|
		425	(hspi->Init.CLKPolarity & SPI_CR1_CPOL) \|
		426	(hspi->Init.CLKPhase & SPI_CR1_CPHA) \|
		427	(hspi->Init.NSS & SPI_CR1_SSM) \|
		428	(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) \|
		429	(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) \|
		430	(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
		431
		432	/* Configure : NSS management */
		433	WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
		434
		435	#if (USE_SPI_CRC != 0U)
		436	/---------------------------- SPIx CRCPOLY Configuration ------------------/
		437	/* Configure : CRC Polynomial */
		438	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		439	{
		440	WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
		441	}
		442	#endif /* USE_SPI_CRC */
		443
		444	#if defined(SPI_I2SCFGR_I2SMOD)
		445	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
		446	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
		447	#endif /* SPI_I2SCFGR_I2SMOD */
		448
		449	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		450	hspi->State = HAL_SPI_STATE_READY;
		451
		452	return HAL_OK;
		453	}
		454
		455	/**
		456	* @brief De-Initialize the SPI peripheral.
		457	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		458	* the configuration information for SPI module.
		459	* @retval HAL status
		460	*/
		461	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
		462	{
		463	/* Check the SPI handle allocation */
		464	if (hspi == NULL)
		465	{
		466	return HAL_ERROR;
		467	}
		468
		469	/* Check SPI Instance parameter */
		470	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		471
		472	hspi->State = HAL_SPI_STATE_BUSY;
		473
		474	/* Disable the SPI Peripheral Clock */
		475	__HAL_SPI_DISABLE(hspi);
		476
		477	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		478	if (hspi->MspDeInitCallback == NULL)
		479	{
		480	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		481	}
		482
		483	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		484	hspi->MspDeInitCallback(hspi);
		485	#else
		486	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		487	HAL_SPI_MspDeInit(hspi);
		488	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		489
		490	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		491	hspi->State = HAL_SPI_STATE_RESET;
		492
		493	/* Release Lock */
		494	__HAL_UNLOCK(hspi);
		495
		496	return HAL_OK;
		497	}
		498
		499	/**
		500	* @brief Initialize the SPI MSP.
		501	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		502	* the configuration information for SPI module.
		503	* @retval None
		504	*/
		505	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
		506	{
		507	/* Prevent unused argument(s) compilation warning */
		508	UNUSED(hspi);
		509
		510	/* NOTE : This function should not be modified, when the callback is needed,
		511	the HAL_SPI_MspInit should be implemented in the user file
		512	*/
		513	}
		514
		515	/**
		516	* @brief De-Initialize the SPI MSP.
		517	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		518	* the configuration information for SPI module.
		519	* @retval None
		520	*/
		521	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
		522	{
		523	/* Prevent unused argument(s) compilation warning */
		524	UNUSED(hspi);
		525
		526	/* NOTE : This function should not be modified, when the callback is needed,
		527	the HAL_SPI_MspDeInit should be implemented in the user file
		528	*/
		529	}
		530
		531	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		532	/**
		533	* @brief Register a User SPI Callback
		534	* To be used instead of the weak predefined callback
		535	* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
		536	* the configuration information for the specified SPI.
		537	* @param CallbackID ID of the callback to be registered
		538	* @param pCallback pointer to the Callback function
		539	* @retval HAL status
		540	*/
		541	HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
		542	pSPI_CallbackTypeDef pCallback)
		543	{
		544	HAL_StatusTypeDef status = HAL_OK;
		545
		546	if (pCallback == NULL)
		547	{
		548	/* Update the error code */
		549	hspi->ErrorCode \|= HAL_SPI_ERROR_INVALID_CALLBACK;
		550
		551	return HAL_ERROR;
		552	}
		553	/* Process locked */
		554	__HAL_LOCK(hspi);
		555
		556	if (HAL_SPI_STATE_READY == hspi->State)
		557	{
		558	switch (CallbackID)
		559	{
		560	case HAL_SPI_TX_COMPLETE_CB_ID :
		561	hspi->TxCpltCallback = pCallback;
		562	break;
		563
		564	case HAL_SPI_RX_COMPLETE_CB_ID :
		565	hspi->RxCpltCallback = pCallback;
		566	break;
		567
		568	case HAL_SPI_TX_RX_COMPLETE_CB_ID :
		569	hspi->TxRxCpltCallback = pCallback;
		570	break;
		571
		572	case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
		573	hspi->TxHalfCpltCallback = pCallback;
		574	break;
		575
		576	case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
		577	hspi->RxHalfCpltCallback = pCallback;
		578	break;
		579
		580	case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
		581	hspi->TxRxHalfCpltCallback = pCallback;
		582	break;
		583
		584	case HAL_SPI_ERROR_CB_ID :
		585	hspi->ErrorCallback = pCallback;
		586	break;
		587
		588	case HAL_SPI_ABORT_CB_ID :
		589	hspi->AbortCpltCallback = pCallback;
		590	break;
		591
		592	case HAL_SPI_MSPINIT_CB_ID :
		593	hspi->MspInitCallback = pCallback;
		594	break;
		595
		596	case HAL_SPI_MSPDEINIT_CB_ID :
		597	hspi->MspDeInitCallback = pCallback;
		598	break;
		599
		600	default :
		601	/* Update the error code */
		602	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		603
		604	/* Return error status */
		605	status = HAL_ERROR;
		606	break;
		607	}
		608	}
		609	else if (HAL_SPI_STATE_RESET == hspi->State)
		610	{
		611	switch (CallbackID)
		612	{
		613	case HAL_SPI_MSPINIT_CB_ID :
		614	hspi->MspInitCallback = pCallback;
		615	break;
		616
		617	case HAL_SPI_MSPDEINIT_CB_ID :
		618	hspi->MspDeInitCallback = pCallback;
		619	break;
		620
		621	default :
		622	/* Update the error code */
		623	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		624
		625	/* Return error status */
		626	status = HAL_ERROR;
		627	break;
		628	}
		629	}
		630	else
		631	{
		632	/* Update the error code */
		633	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		634
		635	/* Return error status */
		636	status = HAL_ERROR;
		637	}
		638
		639	/* Release Lock */
		640	__HAL_UNLOCK(hspi);
		641	return status;
		642	}
		643
		644	/**
		645	* @brief Unregister an SPI Callback
		646	* SPI callback is redirected to the weak predefined callback
		647	* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
		648	* the configuration information for the specified SPI.
		649	* @param CallbackID ID of the callback to be unregistered
		650	* @retval HAL status
		651	*/
		652	HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
		653	{
		654	HAL_StatusTypeDef status = HAL_OK;
		655
		656	/* Process locked */
		657	__HAL_LOCK(hspi);
		658
		659	if (HAL_SPI_STATE_READY == hspi->State)
		660	{
		661	switch (CallbackID)
		662	{
		663	case HAL_SPI_TX_COMPLETE_CB_ID :
		664	hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
		665	break;
		666
		667	case HAL_SPI_RX_COMPLETE_CB_ID :
		668	hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
		669	break;
		670
		671	case HAL_SPI_TX_RX_COMPLETE_CB_ID :
		672	hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
		673	break;
		674
		675	case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
		676	hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
		677	break;
		678
		679	case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
		680	hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
		681	break;
		682
		683	case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
		684	hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
		685	break;
		686
		687	case HAL_SPI_ERROR_CB_ID :
		688	hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
		689	break;
		690
		691	case HAL_SPI_ABORT_CB_ID :
		692	hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
		693	break;
		694
		695	case HAL_SPI_MSPINIT_CB_ID :
		696	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		697	break;
		698
		699	case HAL_SPI_MSPDEINIT_CB_ID :
		700	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		701	break;
		702
		703	default :
		704	/* Update the error code */
		705	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		706
		707	/* Return error status */
		708	status = HAL_ERROR;
		709	break;
		710	}
		711	}
		712	else if (HAL_SPI_STATE_RESET == hspi->State)
		713	{
		714	switch (CallbackID)
		715	{
		716	case HAL_SPI_MSPINIT_CB_ID :
		717	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		718	break;
		719
		720	case HAL_SPI_MSPDEINIT_CB_ID :
		721	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		722	break;
		723
		724	default :
		725	/* Update the error code */
		726	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		727
		728	/* Return error status */
		729	status = HAL_ERROR;
		730	break;
		731	}
		732	}
		733	else
		734	{
		735	/* Update the error code */
		736	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		737
		738	/* Return error status */
		739	status = HAL_ERROR;
		740	}
		741
		742	/* Release Lock */
		743	__HAL_UNLOCK(hspi);
		744	return status;
		745	}
		746	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		747	/**
		748	* @}
		749	*/
		750
		751	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
		752	* @brief Data transfers functions
		753	*
		754	@verbatim
		755	==============================================================================
		756	##### IO operation functions #####
		757	===============================================================================
		758	[..]
		759	This subsection provides a set of functions allowing to manage the SPI
		760	data transfers.
		761
		762	[..] The SPI supports master and slave mode :
		763
		764	(#) There are two modes of transfer:
		765	(++) Blocking mode: The communication is performed in polling mode.
		766	The HAL status of all data processing is returned by the same function
		767	after finishing transfer.
		768	(++) No-Blocking mode: The communication is performed using Interrupts
		769	or DMA, These APIs return the HAL status.
		770	The end of the data processing will be indicated through the
		771	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
		772	using DMA mode.
		773	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
		774	will be executed respectively at the end of the transmit or Receive process
		775	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
		776
		777	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
		778	exist for 1Line (simplex) and 2Lines (full duplex) modes.
		779
		780	@endverbatim
		781	* @{
		782	*/
		783
		784	/**
		785	* @brief Transmit an amount of data in blocking mode.
		786	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		787	* the configuration information for SPI module.
		788	* @param pData pointer to data buffer
		789	* @param Size amount of data to be sent
		790	* @param Timeout Timeout duration
		791	* @retval HAL status
		792	*/
		793	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		794	{
		795	uint32_t tickstart;
		796	HAL_StatusTypeDef errorcode = HAL_OK;
		797	uint16_t initial_TxXferCount;
		798
		799	/* Check Direction parameter */
		800	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		801
		802	/* Process Locked */
		803	__HAL_LOCK(hspi);
		804
		805	/* Init tickstart for timeout management*/
		806	tickstart = HAL_GetTick();
		807	initial_TxXferCount = Size;
		808
		809	if (hspi->State != HAL_SPI_STATE_READY)
		810	{
		811	errorcode = HAL_BUSY;
		812	goto error;
		813	}
		814
		815	if ((pData == NULL) \|\| (Size == 0U))
		816	{
		817	errorcode = HAL_ERROR;
		818	goto error;
		819	}
		820
		821	/* Set the transaction information */
		822	hspi->State = HAL_SPI_STATE_BUSY_TX;
		823	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		824	hspi->pTxBuffPtr = (uint8_t *)pData;
		825	hspi->TxXferSize = Size;
		826	hspi->TxXferCount = Size;
		827
		828	/Init field not used in handle to zero /
		829	hspi->pRxBuffPtr = (uint8_t *)NULL;
		830	hspi->RxXferSize = 0U;
		831	hspi->RxXferCount = 0U;
		832	hspi->TxISR = NULL;
		833	hspi->RxISR = NULL;
		834
		835	/* Configure communication direction : 1Line */
		836	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		837	{
		838	/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
		839	__HAL_SPI_DISABLE(hspi);
		840	SPI_1LINE_TX(hspi);
		841	}
		842
		843	#if (USE_SPI_CRC != 0U)
		844	/* Reset CRC Calculation */
		845	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		846	{
		847	SPI_RESET_CRC(hspi);
		848	}
		849	#endif /* USE_SPI_CRC */
		850
		851	/* Check if the SPI is already enabled */
		852	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		853	{
		854	/* Enable SPI peripheral */
		855	__HAL_SPI_ENABLE(hspi);
		856	}
		857
		858	/* Transmit data in 16 Bit mode */
		859	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		860	{
		861	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		862	{
		863	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		864	hspi->pTxBuffPtr += sizeof(uint16_t);
		865	hspi->TxXferCount--;
		866	}
		867	/* Transmit data in 16 Bit mode */
		868	while (hspi->TxXferCount > 0U)
		869	{
		870	/* Wait until TXE flag is set to send data */
		871	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		872	{
		873	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		874	hspi->pTxBuffPtr += sizeof(uint16_t);
		875	hspi->TxXferCount--;
		876	}
		877	else
		878	{
		879	/* Timeout management */
		880	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		881	{
		882	errorcode = HAL_TIMEOUT;
		883	hspi->State = HAL_SPI_STATE_READY;
		884	goto error;
		885	}
		886	}
		887	}
		888	}
		889	/* Transmit data in 8 Bit mode */
		890	else
		891	{
		892	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		893	{
		894	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		895	hspi->pTxBuffPtr += sizeof(uint8_t);
		896	hspi->TxXferCount--;
		897	}
		898	while (hspi->TxXferCount > 0U)
		899	{
		900	/* Wait until TXE flag is set to send data */
		901	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		902	{
		903	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		904	hspi->pTxBuffPtr += sizeof(uint8_t);
		905	hspi->TxXferCount--;
		906	}
		907	else
		908	{
		909	/* Timeout management */
		910	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		911	{
		912	errorcode = HAL_TIMEOUT;
		913	hspi->State = HAL_SPI_STATE_READY;
		914	goto error;
		915	}
		916	}
		917	}
		918	}
		919	#if (USE_SPI_CRC != 0U)
		920	/* Enable CRC Transmission */
		921	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		922	{
		923	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		924	}
		925	#endif /* USE_SPI_CRC */
		926
		927	/* Check the end of the transaction */
		928	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		929	{
		930	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		931	}
		932
		933	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		934	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		935	{
		936	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		937	}
		938
		939	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		940	{
		941	errorcode = HAL_ERROR;
		942	}
		943	else
		944	{
		945	hspi->State = HAL_SPI_STATE_READY;
		946	}
		947
		948	error:
		949	/* Process Unlocked */
		950	__HAL_UNLOCK(hspi);
		951	return errorcode;
		952	}
		953
		954	/**
		955	* @brief Receive an amount of data in blocking mode.
		956	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		957	* the configuration information for SPI module.
		958	* @param pData pointer to data buffer
		959	* @param Size amount of data to be received
		960	* @param Timeout Timeout duration
		961	* @retval HAL status
		962	*/
		963	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		964	{
		965	#if (USE_SPI_CRC != 0U)
		966	__IO uint32_t tmpreg = 0U;
		967	#endif /* USE_SPI_CRC */
		968	uint32_t tickstart;
		969	HAL_StatusTypeDef errorcode = HAL_OK;
		970
		971	if (hspi->State != HAL_SPI_STATE_READY)
		972	{
		973	errorcode = HAL_BUSY;
		974	goto error;
		975	}
		976
		977	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
		978	{
		979	hspi->State = HAL_SPI_STATE_BUSY_RX;
		980	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		981	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
		982	}
		983
		984	/* Process Locked */
		985	__HAL_LOCK(hspi);
		986
		987	/* Init tickstart for timeout management*/
		988	tickstart = HAL_GetTick();
		989
		990	if ((pData == NULL) \|\| (Size == 0U))
		991	{
		992	errorcode = HAL_ERROR;
		993	goto error;
		994	}
		995
		996	/* Set the transaction information */
		997	hspi->State = HAL_SPI_STATE_BUSY_RX;
		998	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		999	hspi->pRxBuffPtr = (uint8_t *)pData;
		1000	hspi->RxXferSize = Size;
		1001	hspi->RxXferCount = Size;
		1002
		1003	/Init field not used in handle to zero /
		1004	hspi->pTxBuffPtr = (uint8_t *)NULL;
		1005	hspi->TxXferSize = 0U;
		1006	hspi->TxXferCount = 0U;
		1007	hspi->RxISR = NULL;
		1008	hspi->TxISR = NULL;
		1009
		1010	#if (USE_SPI_CRC != 0U)
		1011	/* Reset CRC Calculation */
		1012	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1013	{
		1014	SPI_RESET_CRC(hspi);
		1015	/* this is done to handle the CRCNEXT before the latest data */
		1016	hspi->RxXferCount--;
		1017	}
		1018	#endif /* USE_SPI_CRC */
		1019
		1020	/* Configure communication direction: 1Line */
		1021	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1022	{
		1023	/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
		1024	__HAL_SPI_DISABLE(hspi);
		1025	SPI_1LINE_RX(hspi);
		1026	}
		1027
		1028	/* Check if the SPI is already enabled */
		1029	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1030	{
		1031	/* Enable SPI peripheral */
		1032	__HAL_SPI_ENABLE(hspi);
		1033	}
		1034
		1035	/* Receive data in 8 Bit mode */
		1036	if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
		1037	{
		1038	/* Transfer loop */
		1039	while (hspi->RxXferCount > 0U)
		1040	{
		1041	/* Check the RXNE flag */
		1042	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		1043	{
		1044	/* read the received data */
		1045	(* (uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t *)&hspi->Instance->DR;
		1046	hspi->pRxBuffPtr += sizeof(uint8_t);
		1047	hspi->RxXferCount--;
		1048	}
		1049	else
		1050	{
		1051	/* Timeout management */
		1052	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		1053	{
		1054	errorcode = HAL_TIMEOUT;
		1055	hspi->State = HAL_SPI_STATE_READY;
		1056	goto error;
		1057	}
		1058	}
		1059	}
		1060	}
		1061	else
		1062	{
		1063	/* Transfer loop */
		1064	while (hspi->RxXferCount > 0U)
		1065	{
		1066	/* Check the RXNE flag */
		1067	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		1068	{
		1069	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1070	hspi->pRxBuffPtr += sizeof(uint16_t);
		1071	hspi->RxXferCount--;
		1072	}
		1073	else
		1074	{
		1075	/* Timeout management */
		1076	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		1077	{
		1078	errorcode = HAL_TIMEOUT;
		1079	hspi->State = HAL_SPI_STATE_READY;
		1080	goto error;
		1081	}
		1082	}
		1083	}
		1084	}
		1085
		1086	#if (USE_SPI_CRC != 0U)
		1087	/* Handle the CRC Transmission */
		1088	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1089	{
		1090	/* freeze the CRC before the latest data */
		1091	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1092
		1093	/* Check if CRCNEXT is well reset by hardware */
		1094	if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
		1095	{
		1096	/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
		1097	CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1098	}
		1099	/* Read the latest data */
		1100	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1101	{
		1102	/* the latest data has not been received */
		1103	errorcode = HAL_TIMEOUT;
		1104	goto error;
		1105	}
		1106
		1107	/* Receive last data in 16 Bit mode */
		1108	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		1109	{
		1110	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1111	}
		1112	/* Receive last data in 8 Bit mode */
		1113	else
		1114	{
		1115	((uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t )&hspi->Instance->DR;
		1116	}
		1117
		1118	/* Wait the CRC data */
		1119	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1120	{
		1121	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1122	errorcode = HAL_TIMEOUT;
		1123	goto error;
		1124	}
		1125
		1126	/* Read CRC to Flush DR and RXNE flag */
		1127	tmpreg = READ_REG(hspi->Instance->DR);
		1128	/* To avoid GCC warning */
		1129	UNUSED(tmpreg);
		1130	}
		1131	#endif /* USE_SPI_CRC */
		1132
		1133	/* Check the end of the transaction */
		1134	if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		1135	{
		1136	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1137	}
		1138
		1139	#if (USE_SPI_CRC != 0U)
		1140	/* Check if CRC error occurred */
		1141	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		1142	{
		1143	/* Check if CRC error is valid or not (workaround to be applied or not) */
		1144	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		1145	{
		1146	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1147
		1148	/* Reset CRC Calculation */
		1149	SPI_RESET_CRC(hspi);
		1150	}
		1151	else
		1152	{
		1153	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1154	}
		1155	}
		1156	#endif /* USE_SPI_CRC */
		1157
		1158	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		1159	{
		1160	errorcode = HAL_ERROR;
		1161	}
		1162	else
		1163	{
		1164	hspi->State = HAL_SPI_STATE_READY;
		1165	}
		1166
		1167	error :
		1168	__HAL_UNLOCK(hspi);
		1169	return errorcode;
		1170	}
		1171
		1172	/**
		1173	* @brief Transmit and Receive an amount of data in blocking mode.
		1174	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1175	* the configuration information for SPI module.
		1176	* @param pTxData pointer to transmission data buffer
		1177	* @param pRxData pointer to reception data buffer
		1178	* @param Size amount of data to be sent and received
		1179	* @param Timeout Timeout duration
		1180	* @retval HAL status
		1181	*/
		1182	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
		1183	uint32_t Timeout)
		1184	{
		1185	uint16_t initial_TxXferCount;
		1186	uint32_t tmp_mode;
		1187	HAL_SPI_StateTypeDef tmp_state;
		1188	uint32_t tickstart;
		1189	#if (USE_SPI_CRC != 0U)
		1190	__IO uint32_t tmpreg = 0U;
		1191	#endif /* USE_SPI_CRC */
		1192
		1193	/* Variable used to alternate Rx and Tx during transfer */
		1194	uint32_t txallowed = 1U;
		1195	HAL_StatusTypeDef errorcode = HAL_OK;
		1196
		1197	/* Check Direction parameter */
		1198	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1199
		1200	/* Process Locked */
		1201	__HAL_LOCK(hspi);
		1202
		1203	/* Init tickstart for timeout management*/
		1204	tickstart = HAL_GetTick();
		1205
		1206	/* Init temporary variables */
		1207	tmp_state = hspi->State;
		1208	tmp_mode = hspi->Init.Mode;
		1209	initial_TxXferCount = Size;
		1210
		1211	if (!((tmp_state == HAL_SPI_STATE_READY) \|\| \
		1212	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1213	{
		1214	errorcode = HAL_BUSY;
		1215	goto error;
		1216	}
		1217
		1218	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1219	{
		1220	errorcode = HAL_ERROR;
		1221	goto error;
		1222	}
		1223
		1224	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1225	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1226	{
		1227	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1228	}
		1229
		1230	/* Set the transaction information */
		1231	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1232	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1233	hspi->RxXferCount = Size;
		1234	hspi->RxXferSize = Size;
		1235	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1236	hspi->TxXferCount = Size;
		1237	hspi->TxXferSize = Size;
		1238
		1239	/Init field not used in handle to zero /
		1240	hspi->RxISR = NULL;
		1241	hspi->TxISR = NULL;
		1242
		1243	#if (USE_SPI_CRC != 0U)
		1244	/* Reset CRC Calculation */
		1245	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1246	{
		1247	SPI_RESET_CRC(hspi);
		1248	}
		1249	#endif /* USE_SPI_CRC */
		1250
		1251	/* Check if the SPI is already enabled */
		1252	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1253	{
		1254	/* Enable SPI peripheral */
		1255	__HAL_SPI_ENABLE(hspi);
		1256	}
		1257
		1258	/* Transmit and Receive data in 16 Bit mode */
		1259	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		1260	{
		1261	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		1262	{
		1263	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1264	hspi->pTxBuffPtr += sizeof(uint16_t);
		1265	hspi->TxXferCount--;
		1266	}
		1267	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		1268	{
		1269	/* Check TXE flag */
		1270	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
		1271	{
		1272	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1273	hspi->pTxBuffPtr += sizeof(uint16_t);
		1274	hspi->TxXferCount--;
		1275	/* Next Data is a reception (Rx). Tx not allowed */
		1276	txallowed = 0U;
		1277
		1278	#if (USE_SPI_CRC != 0U)
		1279	/* Enable CRC Transmission */
		1280	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		1281	{
		1282	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1283	}
		1284	#endif /* USE_SPI_CRC */
		1285	}
		1286
		1287	/* Check RXNE flag */
		1288	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
		1289	{
		1290	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1291	hspi->pRxBuffPtr += sizeof(uint16_t);
		1292	hspi->RxXferCount--;
		1293	/* Next Data is a Transmission (Tx). Tx is allowed */
		1294	txallowed = 1U;
		1295	}
		1296	if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
		1297	{
		1298	errorcode = HAL_TIMEOUT;
		1299	hspi->State = HAL_SPI_STATE_READY;
		1300	goto error;
		1301	}
		1302	}
		1303	}
		1304	/* Transmit and Receive data in 8 Bit mode */
		1305	else
		1306	{
		1307	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		1308	{
		1309	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		1310	hspi->pTxBuffPtr += sizeof(uint8_t);
		1311	hspi->TxXferCount--;
		1312	}
		1313	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		1314	{
		1315	/* Check TXE flag */
		1316	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
		1317	{
		1318	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		1319	hspi->pTxBuffPtr++;
		1320	hspi->TxXferCount--;
		1321	/* Next Data is a reception (Rx). Tx not allowed */
		1322	txallowed = 0U;
		1323
		1324	#if (USE_SPI_CRC != 0U)
		1325	/* Enable CRC Transmission */
		1326	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		1327	{
		1328	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1329	}
		1330	#endif /* USE_SPI_CRC */
		1331	}
		1332
		1333	/* Wait until RXNE flag is reset */
		1334	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
		1335	{
		1336	((uint8_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
		1337	hspi->pRxBuffPtr++;
		1338	hspi->RxXferCount--;
		1339	/* Next Data is a Transmission (Tx). Tx is allowed */
		1340	txallowed = 1U;
		1341	}
		1342	if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) \|\| (Timeout == 0U))
		1343	{
		1344	errorcode = HAL_TIMEOUT;
		1345	hspi->State = HAL_SPI_STATE_READY;
		1346	goto error;
		1347	}
		1348	}
		1349	}
		1350
		1351	#if (USE_SPI_CRC != 0U)
		1352	/* Read CRC from DR to close CRC calculation process */
		1353	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1354	{
		1355	/* Wait until TXE flag */
		1356	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1357	{
		1358	/* Error on the CRC reception */
		1359	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1360	errorcode = HAL_TIMEOUT;
		1361	goto error;
		1362	}
		1363	/* Read CRC */
		1364	tmpreg = READ_REG(hspi->Instance->DR);
		1365	/* To avoid GCC warning */
		1366	UNUSED(tmpreg);
		1367	}
		1368
		1369	/* Check if CRC error occurred */
		1370	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		1371	{
		1372	/* Check if CRC error is valid or not (workaround to be applied or not) */
		1373	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		1374	{
		1375	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1376
		1377	/* Reset CRC Calculation */
		1378	SPI_RESET_CRC(hspi);
		1379
		1380	errorcode = HAL_ERROR;
		1381	}
		1382	else
		1383	{
		1384	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1385	}
		1386	}
		1387	#endif /* USE_SPI_CRC */
		1388
		1389	/* Check the end of the transaction */
		1390	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		1391	{
		1392	errorcode = HAL_ERROR;
		1393	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1394	goto error;
		1395	}
		1396
		1397	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		1398	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		1399	{
		1400	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		1401	}
		1402
		1403	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		1404	{
		1405	errorcode = HAL_ERROR;
		1406	}
		1407	else
		1408	{
		1409	hspi->State = HAL_SPI_STATE_READY;
		1410	}
		1411
		1412	error :
		1413	__HAL_UNLOCK(hspi);
		1414	return errorcode;
		1415	}
		1416
		1417	/**
		1418	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
		1419	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1420	* the configuration information for SPI module.
		1421	* @param pData pointer to data buffer
		1422	* @param Size amount of data to be sent
		1423	* @retval HAL status
		1424	*/
		1425	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1426	{
		1427	HAL_StatusTypeDef errorcode = HAL_OK;
		1428
		1429	/* Check Direction parameter */
		1430	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1431
		1432	/* Process Locked */
		1433	__HAL_LOCK(hspi);
		1434
		1435	if ((pData == NULL) \|\| (Size == 0U))
		1436	{
		1437	errorcode = HAL_ERROR;
		1438	goto error;
		1439	}
		1440
		1441	if (hspi->State != HAL_SPI_STATE_READY)
		1442	{
		1443	errorcode = HAL_BUSY;
		1444	goto error;
		1445	}
		1446
		1447	/* Set the transaction information */
		1448	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1449	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1450	hspi->pTxBuffPtr = (uint8_t *)pData;
		1451	hspi->TxXferSize = Size;
		1452	hspi->TxXferCount = Size;
		1453
		1454	/* Init field not used in handle to zero */
		1455	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1456	hspi->RxXferSize = 0U;
		1457	hspi->RxXferCount = 0U;
		1458	hspi->RxISR = NULL;
		1459
		1460	/* Set the function for IT treatment */
		1461	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1462	{
		1463	hspi->TxISR = SPI_TxISR_16BIT;
		1464	}
		1465	else
		1466	{
		1467	hspi->TxISR = SPI_TxISR_8BIT;
		1468	}
		1469
		1470	/* Configure communication direction : 1Line */
		1471	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1472	{
		1473	/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
		1474	__HAL_SPI_DISABLE(hspi);
		1475	SPI_1LINE_TX(hspi);
		1476	}
		1477
		1478	#if (USE_SPI_CRC != 0U)
		1479	/* Reset CRC Calculation */
		1480	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1481	{
		1482	SPI_RESET_CRC(hspi);
		1483	}
		1484	#endif /* USE_SPI_CRC */
		1485
		1486	/* Enable TXE and ERR interrupt */
		1487	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		1488
		1489
		1490	/* Check if the SPI is already enabled */
		1491	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1492	{
		1493	/* Enable SPI peripheral */
		1494	__HAL_SPI_ENABLE(hspi);
		1495	}
		1496
		1497	error :
		1498	__HAL_UNLOCK(hspi);
		1499	return errorcode;
		1500	}
		1501
		1502	/**
		1503	* @brief Receive an amount of data in non-blocking mode with Interrupt.
		1504	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1505	* the configuration information for SPI module.
		1506	* @param pData pointer to data buffer
		1507	* @param Size amount of data to be sent
		1508	* @retval HAL status
		1509	*/
		1510	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1511	{
		1512	HAL_StatusTypeDef errorcode = HAL_OK;
		1513
		1514
		1515	if (hspi->State != HAL_SPI_STATE_READY)
		1516	{
		1517	errorcode = HAL_BUSY;
		1518	goto error;
		1519	}
		1520
		1521	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1522	{
		1523	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1524	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1525	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
		1526	}
		1527
		1528	/* Process Locked */
		1529	__HAL_LOCK(hspi);
		1530
		1531	if ((pData == NULL) \|\| (Size == 0U))
		1532	{
		1533	errorcode = HAL_ERROR;
		1534	goto error;
		1535	}
		1536
		1537	/* Set the transaction information */
		1538	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1539	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1540	hspi->pRxBuffPtr = (uint8_t *)pData;
		1541	hspi->RxXferSize = Size;
		1542	hspi->RxXferCount = Size;
		1543
		1544	/* Init field not used in handle to zero */
		1545	hspi->pTxBuffPtr = (uint8_t *)NULL;
		1546	hspi->TxXferSize = 0U;
		1547	hspi->TxXferCount = 0U;
		1548	hspi->TxISR = NULL;
		1549
		1550	/* Set the function for IT treatment */
		1551	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1552	{
		1553	hspi->RxISR = SPI_RxISR_16BIT;
		1554	}
		1555	else
		1556	{
		1557	hspi->RxISR = SPI_RxISR_8BIT;
		1558	}
		1559
		1560	/* Configure communication direction : 1Line */
		1561	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1562	{
		1563	/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
		1564	__HAL_SPI_DISABLE(hspi);
		1565	SPI_1LINE_RX(hspi);
		1566	}
		1567
		1568	#if (USE_SPI_CRC != 0U)
		1569	/* Reset CRC Calculation */
		1570	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1571	{
		1572	SPI_RESET_CRC(hspi);
		1573	}
		1574	#endif /* USE_SPI_CRC */
		1575
		1576	/* Enable TXE and ERR interrupt */
		1577	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		1578
		1579	/* Note : The SPI must be enabled after unlocking current process
		1580	to avoid the risk of SPI interrupt handle execution before current
		1581	process unlock */
		1582
		1583	/* Check if the SPI is already enabled */
		1584	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1585	{
		1586	/* Enable SPI peripheral */
		1587	__HAL_SPI_ENABLE(hspi);
		1588	}
		1589
		1590	error :
		1591	/* Process Unlocked */
		1592	__HAL_UNLOCK(hspi);
		1593	return errorcode;
		1594	}
		1595
		1596	/**
		1597	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
		1598	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1599	* the configuration information for SPI module.
		1600	* @param pTxData pointer to transmission data buffer
		1601	* @param pRxData pointer to reception data buffer
		1602	* @param Size amount of data to be sent and received
		1603	* @retval HAL status
		1604	*/
		1605	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
		1606	{
		1607	uint32_t tmp_mode;
		1608	HAL_SPI_StateTypeDef tmp_state;
		1609	HAL_StatusTypeDef errorcode = HAL_OK;
		1610
		1611	/* Check Direction parameter */
		1612	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1613
		1614	/* Process locked */
		1615	__HAL_LOCK(hspi);
		1616
		1617	/* Init temporary variables */
		1618	tmp_state = hspi->State;
		1619	tmp_mode = hspi->Init.Mode;
		1620
		1621	if (!((tmp_state == HAL_SPI_STATE_READY) \|\| \
		1622	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1623	{
		1624	errorcode = HAL_BUSY;
		1625	goto error;
		1626	}
		1627
		1628	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1629	{
		1630	errorcode = HAL_ERROR;
		1631	goto error;
		1632	}
		1633
		1634	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1635	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1636	{
		1637	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1638	}
		1639
		1640	/* Set the transaction information */
		1641	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1642	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1643	hspi->TxXferSize = Size;
		1644	hspi->TxXferCount = Size;
		1645	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1646	hspi->RxXferSize = Size;
		1647	hspi->RxXferCount = Size;
		1648
		1649	/* Set the function for IT treatment */
		1650	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1651	{
		1652	hspi->RxISR = SPI_2linesRxISR_16BIT;
		1653	hspi->TxISR = SPI_2linesTxISR_16BIT;
		1654	}
		1655	else
		1656	{
		1657	hspi->RxISR = SPI_2linesRxISR_8BIT;
		1658	hspi->TxISR = SPI_2linesTxISR_8BIT;
		1659	}
		1660
		1661	#if (USE_SPI_CRC != 0U)
		1662	/* Reset CRC Calculation */
		1663	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1664	{
		1665	SPI_RESET_CRC(hspi);
		1666	}
		1667	#endif /* USE_SPI_CRC */
		1668
		1669	/* Enable TXE, RXNE and ERR interrupt */
		1670	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		1671
		1672	/* Check if the SPI is already enabled */
		1673	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1674	{
		1675	/* Enable SPI peripheral */
		1676	__HAL_SPI_ENABLE(hspi);
		1677	}
		1678
		1679	error :
		1680	/* Process Unlocked */
		1681	__HAL_UNLOCK(hspi);
		1682	return errorcode;
		1683	}
		1684
		1685	/**
		1686	* @brief Transmit an amount of data in non-blocking mode with DMA.
		1687	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1688	* the configuration information for SPI module.
		1689	* @param pData pointer to data buffer
		1690	* @param Size amount of data to be sent
		1691	* @retval HAL status
		1692	*/
		1693	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1694	{
		1695	HAL_StatusTypeDef errorcode = HAL_OK;
		1696
		1697	/* Check tx dma handle */
		1698	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1699
		1700	/* Check Direction parameter */
		1701	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1702
		1703	/* Process Locked */
		1704	__HAL_LOCK(hspi);
		1705
		1706	if (hspi->State != HAL_SPI_STATE_READY)
		1707	{
		1708	errorcode = HAL_BUSY;
		1709	goto error;
		1710	}
		1711
		1712	if ((pData == NULL) \|\| (Size == 0U))
		1713	{
		1714	errorcode = HAL_ERROR;
		1715	goto error;
		1716	}
		1717
		1718	/* Set the transaction information */
		1719	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1720	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1721	hspi->pTxBuffPtr = (uint8_t *)pData;
		1722	hspi->TxXferSize = Size;
		1723	hspi->TxXferCount = Size;
		1724
		1725	/* Init field not used in handle to zero */
		1726	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1727	hspi->TxISR = NULL;
		1728	hspi->RxISR = NULL;
		1729	hspi->RxXferSize = 0U;
		1730	hspi->RxXferCount = 0U;
		1731
		1732	/* Configure communication direction : 1Line */
		1733	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1734	{
		1735	/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
		1736	__HAL_SPI_DISABLE(hspi);
		1737	SPI_1LINE_TX(hspi);
		1738	}
		1739
		1740	#if (USE_SPI_CRC != 0U)
		1741	/* Reset CRC Calculation */
		1742	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1743	{
		1744	SPI_RESET_CRC(hspi);
		1745	}
		1746	#endif /* USE_SPI_CRC */
		1747
		1748	/* Set the SPI TxDMA Half transfer complete callback */
		1749	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
		1750
		1751	/* Set the SPI TxDMA transfer complete callback */
		1752	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
		1753
		1754	/* Set the DMA error callback */
		1755	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
		1756
		1757	/* Set the DMA AbortCpltCallback */
		1758	hspi->hdmatx->XferAbortCallback = NULL;
		1759
		1760	/* Enable the Tx DMA Stream/Channel */
		1761	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
		1762	hspi->TxXferCount))
		1763	{
		1764	/* Update SPI error code */
		1765	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1766	errorcode = HAL_ERROR;
		1767
		1768	goto error;
		1769	}
		1770
		1771	/* Check if the SPI is already enabled */
		1772	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1773	{
		1774	/* Enable SPI peripheral */
		1775	__HAL_SPI_ENABLE(hspi);
		1776	}
		1777
		1778	/* Enable the SPI Error Interrupt Bit */
		1779	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		1780
		1781	/* Enable Tx DMA Request */
		1782	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		1783
		1784	error :
		1785	/* Process Unlocked */
		1786	__HAL_UNLOCK(hspi);
		1787	return errorcode;
		1788	}
		1789
		1790	/**
		1791	* @brief Receive an amount of data in non-blocking mode with DMA.
		1792	* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
		1793	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1794	* the configuration information for SPI module.
		1795	* @param pData pointer to data buffer
		1796	* @note When the CRC feature is enabled the pData Length must be Size + 1.
		1797	* @param Size amount of data to be sent
		1798	* @retval HAL status
		1799	*/
		1800	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1801	{
		1802	HAL_StatusTypeDef errorcode = HAL_OK;
		1803
		1804	/* Check rx dma handle */
		1805	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
		1806
		1807	if (hspi->State != HAL_SPI_STATE_READY)
		1808	{
		1809	errorcode = HAL_BUSY;
		1810	goto error;
		1811	}
		1812
		1813	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1814	{
		1815	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1816
		1817	/* Check tx dma handle */
		1818	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1819
		1820	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1821	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
		1822	}
		1823
		1824	/* Process Locked */
		1825	__HAL_LOCK(hspi);
		1826
		1827	if ((pData == NULL) \|\| (Size == 0U))
		1828	{
		1829	errorcode = HAL_ERROR;
		1830	goto error;
		1831	}
		1832
		1833	/* Set the transaction information */
		1834	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1835	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1836	hspi->pRxBuffPtr = (uint8_t *)pData;
		1837	hspi->RxXferSize = Size;
		1838	hspi->RxXferCount = Size;
		1839
		1840	/Init field not used in handle to zero /
		1841	hspi->RxISR = NULL;
		1842	hspi->TxISR = NULL;
		1843	hspi->TxXferSize = 0U;
		1844	hspi->TxXferCount = 0U;
		1845
		1846	/* Configure communication direction : 1Line */
		1847	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1848	{
		1849	/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
		1850	__HAL_SPI_DISABLE(hspi);
		1851	SPI_1LINE_RX(hspi);
		1852	}
		1853
		1854	#if (USE_SPI_CRC != 0U)
		1855	/* Reset CRC Calculation */
		1856	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1857	{
		1858	SPI_RESET_CRC(hspi);
		1859	}
		1860	#endif /* USE_SPI_CRC */
		1861
		1862	/* Set the SPI RxDMA Half transfer complete callback */
		1863	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		1864
		1865	/* Set the SPI Rx DMA transfer complete callback */
		1866	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		1867
		1868	/* Set the DMA error callback */
		1869	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		1870
		1871	/* Set the DMA AbortCpltCallback */
		1872	hspi->hdmarx->XferAbortCallback = NULL;
		1873
		1874	/* Enable the Rx DMA Stream/Channel */
		1875	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
		1876	hspi->RxXferCount))
		1877	{
		1878	/* Update SPI error code */
		1879	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1880	errorcode = HAL_ERROR;
		1881
		1882	goto error;
		1883	}
		1884
		1885	/* Check if the SPI is already enabled */
		1886	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1887	{
		1888	/* Enable SPI peripheral */
		1889	__HAL_SPI_ENABLE(hspi);
		1890	}
		1891
		1892	/* Enable the SPI Error Interrupt Bit */
		1893	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		1894
		1895	/* Enable Rx DMA Request */
		1896	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		1897
		1898	error:
		1899	/* Process Unlocked */
		1900	__HAL_UNLOCK(hspi);
		1901	return errorcode;
		1902	}
		1903
		1904	/**
		1905	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
		1906	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1907	* the configuration information for SPI module.
		1908	* @param pTxData pointer to transmission data buffer
		1909	* @param pRxData pointer to reception data buffer
		1910	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
		1911	* @param Size amount of data to be sent
		1912	* @retval HAL status
		1913	*/
		1914	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
		1915	uint16_t Size)
		1916	{
		1917	uint32_t tmp_mode;
		1918	HAL_SPI_StateTypeDef tmp_state;
		1919	HAL_StatusTypeDef errorcode = HAL_OK;
		1920
		1921	/* Check rx & tx dma handles */
		1922	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
		1923	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1924
		1925	/* Check Direction parameter */
		1926	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1927
		1928	/* Process locked */
		1929	__HAL_LOCK(hspi);
		1930
		1931	/* Init temporary variables */
		1932	tmp_state = hspi->State;
		1933	tmp_mode = hspi->Init.Mode;
		1934
		1935	if (!((tmp_state == HAL_SPI_STATE_READY) \|\|
		1936	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1937	{
		1938	errorcode = HAL_BUSY;
		1939	goto error;
		1940	}
		1941
		1942	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1943	{
		1944	errorcode = HAL_ERROR;
		1945	goto error;
		1946	}
		1947
		1948	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1949	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1950	{
		1951	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1952	}
		1953
		1954	/* Set the transaction information */
		1955	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1956	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1957	hspi->TxXferSize = Size;
		1958	hspi->TxXferCount = Size;
		1959	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1960	hspi->RxXferSize = Size;
		1961	hspi->RxXferCount = Size;
		1962
		1963	/* Init field not used in handle to zero */
		1964	hspi->RxISR = NULL;
		1965	hspi->TxISR = NULL;
		1966
		1967	#if (USE_SPI_CRC != 0U)
		1968	/* Reset CRC Calculation */
		1969	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1970	{
		1971	SPI_RESET_CRC(hspi);
		1972	}
		1973	#endif /* USE_SPI_CRC */
		1974
		1975	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
		1976	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
		1977	{
		1978	/* Set the SPI Rx DMA Half transfer complete callback */
		1979	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		1980	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		1981	}
		1982	else
		1983	{
		1984	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
		1985	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
		1986	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
		1987	}
		1988
		1989	/* Set the DMA error callback */
		1990	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		1991
		1992	/* Set the DMA AbortCpltCallback */
		1993	hspi->hdmarx->XferAbortCallback = NULL;
		1994
		1995	/* Enable the Rx DMA Stream/Channel */
		1996	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
		1997	hspi->RxXferCount))
		1998	{
		1999	/* Update SPI error code */
		2000	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2001	errorcode = HAL_ERROR;
		2002
		2003	goto error;
		2004	}
		2005
		2006	/* Enable Rx DMA Request */
		2007	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		2008
		2009	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
		2010	is performed in DMA reception complete callback */
		2011	hspi->hdmatx->XferHalfCpltCallback = NULL;
		2012	hspi->hdmatx->XferCpltCallback = NULL;
		2013	hspi->hdmatx->XferErrorCallback = NULL;
		2014	hspi->hdmatx->XferAbortCallback = NULL;
		2015
		2016	/* Enable the Tx DMA Stream/Channel */
		2017	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
		2018	hspi->TxXferCount))
		2019	{
		2020	/* Update SPI error code */
		2021	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2022	errorcode = HAL_ERROR;
		2023
		2024	goto error;
		2025	}
		2026
		2027	/* Check if the SPI is already enabled */
		2028	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		2029	{
		2030	/* Enable SPI peripheral */
		2031	__HAL_SPI_ENABLE(hspi);
		2032	}
		2033	/* Enable the SPI Error Interrupt Bit */
		2034	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		2035
		2036	/* Enable Tx DMA Request */
		2037	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		2038
		2039	error :
		2040	/* Process Unlocked */
		2041	__HAL_UNLOCK(hspi);
		2042	return errorcode;
		2043	}
		2044
		2045	/**
		2046	* @brief Abort ongoing transfer (blocking mode).
		2047	* @param hspi SPI handle.
		2048	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		2049	* started in Interrupt or DMA mode.
		2050	* This procedure performs following operations :
		2051	* - Disable SPI Interrupts (depending of transfer direction)
		2052	* - Disable the DMA transfer in the peripheral register (if enabled)
		2053	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
		2054	* - Set handle State to READY
		2055	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
		2056	* @retval HAL status
		2057	*/
		2058	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
		2059	{
		2060	HAL_StatusTypeDef errorcode;
		2061	__IO uint32_t count;
		2062	__IO uint32_t resetcount;
		2063
		2064	/* Initialized local variable */
		2065	errorcode = HAL_OK;
		2066	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2067	count = resetcount;
		2068
		2069	/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
		2070	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		2071
		2072	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		2073	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		2074	{
		2075	hspi->TxISR = SPI_AbortTx_ISR;
		2076	/* Wait HAL_SPI_STATE_ABORT state */
		2077	do
		2078	{
		2079	if (count == 0U)
		2080	{
		2081	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2082	break;
		2083	}
		2084	count--;
		2085	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2086	/* Reset Timeout Counter */
		2087	count = resetcount;
		2088	}
		2089
		2090	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		2091	{
		2092	hspi->RxISR = SPI_AbortRx_ISR;
		2093	/* Wait HAL_SPI_STATE_ABORT state */
		2094	do
		2095	{
		2096	if (count == 0U)
		2097	{
		2098	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2099	break;
		2100	}
		2101	count--;
		2102	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2103	/* Reset Timeout Counter */
		2104	count = resetcount;
		2105	}
		2106
		2107	/* Disable the SPI DMA Tx request if enabled */
		2108	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2109	{
		2110	/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
		2111	if (hspi->hdmatx != NULL)
		2112	{
		2113	/* Set the SPI DMA Abort callback :
		2114	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		2115	hspi->hdmatx->XferAbortCallback = NULL;
		2116
		2117	/* Abort DMA Tx Handle linked to SPI Peripheral */
		2118	if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
		2119	{
		2120	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2121	}
		2122
		2123	/* Disable Tx DMA Request */
		2124	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
		2125
		2126	/* Wait until TXE flag is set */
		2127	do
		2128	{
		2129	if (count == 0U)
		2130	{
		2131	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2132	break;
		2133	}
		2134	count--;
		2135	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		2136	}
		2137	}
		2138
		2139	/* Disable the SPI DMA Rx request if enabled */
		2140	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2141	{
		2142	/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
		2143	if (hspi->hdmarx != NULL)
		2144	{
		2145	/* Set the SPI DMA Abort callback :
		2146	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		2147	hspi->hdmarx->XferAbortCallback = NULL;
		2148
		2149	/* Abort DMA Rx Handle linked to SPI Peripheral */
		2150	if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
		2151	{
		2152	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2153	}
		2154
		2155	/* Disable peripheral */
		2156	__HAL_SPI_DISABLE(hspi);
		2157
		2158	/* Disable Rx DMA Request */
		2159	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
		2160	}
		2161	}
		2162	/* Reset Tx and Rx transfer counters */
		2163	hspi->RxXferCount = 0U;
		2164	hspi->TxXferCount = 0U;
		2165
		2166	/* Check error during Abort procedure */
		2167	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
		2168	{
		2169	/* return HAL_Error in case of error during Abort procedure */
		2170	errorcode = HAL_ERROR;
		2171	}
		2172	else
		2173	{
		2174	/* Reset errorCode */
		2175	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2176	}
		2177
		2178	/* Clear the Error flags in the SR register */
		2179	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2180
		2181	/* Restore hspi->state to ready */
		2182	hspi->State = HAL_SPI_STATE_READY;
		2183
		2184	return errorcode;
		2185	}
		2186
		2187	/**
		2188	* @brief Abort ongoing transfer (Interrupt mode).
		2189	* @param hspi SPI handle.
		2190	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		2191	* started in Interrupt or DMA mode.
		2192	* This procedure performs following operations :
		2193	* - Disable SPI Interrupts (depending of transfer direction)
		2194	* - Disable the DMA transfer in the peripheral register (if enabled)
		2195	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
		2196	* - Set handle State to READY
		2197	* - At abort completion, call user abort complete callback
		2198	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
		2199	* considered as completed only when user abort complete callback is executed (not when exiting function).
		2200	* @retval HAL status
		2201	*/
		2202	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
		2203	{
		2204	HAL_StatusTypeDef errorcode;
		2205	uint32_t abortcplt ;
		2206	__IO uint32_t count;
		2207	__IO uint32_t resetcount;
		2208
		2209	/* Initialized local variable */
		2210	errorcode = HAL_OK;
		2211	abortcplt = 1U;
		2212	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2213	count = resetcount;
		2214
		2215	/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
		2216	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		2217
		2218	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
		2219	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		2220	{
		2221	hspi->TxISR = SPI_AbortTx_ISR;
		2222	/* Wait HAL_SPI_STATE_ABORT state */
		2223	do
		2224	{
		2225	if (count == 0U)
		2226	{
		2227	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2228	break;
		2229	}
		2230	count--;
		2231	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2232	/* Reset Timeout Counter */
		2233	count = resetcount;
		2234	}
		2235
		2236	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		2237	{
		2238	hspi->RxISR = SPI_AbortRx_ISR;
		2239	/* Wait HAL_SPI_STATE_ABORT state */
		2240	do
		2241	{
		2242	if (count == 0U)
		2243	{
		2244	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2245	break;
		2246	}
		2247	count--;
		2248	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2249	/* Reset Timeout Counter */
		2250	count = resetcount;
		2251	}
		2252
		2253	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
		2254	before any call to DMA Abort functions */
		2255	/* DMA Tx Handle is valid */
		2256	if (hspi->hdmatx != NULL)
		2257	{
		2258	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
		2259	Otherwise, set it to NULL */
		2260	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2261	{
		2262	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
		2263	}
		2264	else
		2265	{
		2266	hspi->hdmatx->XferAbortCallback = NULL;
		2267	}
		2268	}
		2269	/* DMA Rx Handle is valid */
		2270	if (hspi->hdmarx != NULL)
		2271	{
		2272	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
		2273	Otherwise, set it to NULL */
		2274	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2275	{
		2276	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
		2277	}
		2278	else
		2279	{
		2280	hspi->hdmarx->XferAbortCallback = NULL;
		2281	}
		2282	}
		2283
		2284	/* Disable the SPI DMA Tx request if enabled */
		2285	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2286	{
		2287	/* Abort the SPI DMA Tx Stream/Channel */
		2288	if (hspi->hdmatx != NULL)
		2289	{
		2290	/* Abort DMA Tx Handle linked to SPI Peripheral */
		2291	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
		2292	{
		2293	hspi->hdmatx->XferAbortCallback = NULL;
		2294	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2295	}
		2296	else
		2297	{
		2298	abortcplt = 0U;
		2299	}
		2300	}
		2301	}
		2302	/* Disable the SPI DMA Rx request if enabled */
		2303	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2304	{
		2305	/* Abort the SPI DMA Rx Stream/Channel */
		2306	if (hspi->hdmarx != NULL)
		2307	{
		2308	/* Abort DMA Rx Handle linked to SPI Peripheral */
		2309	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
		2310	{
		2311	hspi->hdmarx->XferAbortCallback = NULL;
		2312	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2313	}
		2314	else
		2315	{
		2316	abortcplt = 0U;
		2317	}
		2318	}
		2319	}
		2320
		2321	if (abortcplt == 1U)
		2322	{
		2323	/* Reset Tx and Rx transfer counters */
		2324	hspi->RxXferCount = 0U;
		2325	hspi->TxXferCount = 0U;
		2326
		2327	/* Check error during Abort procedure */
		2328	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
		2329	{
		2330	/* return HAL_Error in case of error during Abort procedure */
		2331	errorcode = HAL_ERROR;
		2332	}
		2333	else
		2334	{
		2335	/* Reset errorCode */
		2336	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2337	}
		2338
		2339	/* Clear the Error flags in the SR register */
		2340	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2341
		2342	/* Restore hspi->State to Ready */
		2343	hspi->State = HAL_SPI_STATE_READY;
		2344
		2345	/* As no DMA to be aborted, call directly user Abort complete callback */
		2346	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2347	hspi->AbortCpltCallback(hspi);
		2348	#else
		2349	HAL_SPI_AbortCpltCallback(hspi);
		2350	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2351	}
		2352
		2353	return errorcode;
		2354	}
		2355
		2356	/**
		2357	* @brief Pause the DMA Transfer.
		2358	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2359	* the configuration information for the specified SPI module.
		2360	* @retval HAL status
		2361	*/
		2362	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
		2363	{
		2364	/* Process Locked */
		2365	__HAL_LOCK(hspi);
		2366
		2367	/* Disable the SPI DMA Tx & Rx requests */
		2368	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2369
		2370	/* Process Unlocked */
		2371	__HAL_UNLOCK(hspi);
		2372
		2373	return HAL_OK;
		2374	}
		2375
		2376	/**
		2377	* @brief Resume the DMA Transfer.
		2378	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2379	* the configuration information for the specified SPI module.
		2380	* @retval HAL status
		2381	*/
		2382	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
		2383	{
		2384	/* Process Locked */
		2385	__HAL_LOCK(hspi);
		2386
		2387	/* Enable the SPI DMA Tx & Rx requests */
		2388	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2389
		2390	/* Process Unlocked */
		2391	__HAL_UNLOCK(hspi);
		2392
		2393	return HAL_OK;
		2394	}
		2395
		2396	/**
		2397	* @brief Stop the DMA Transfer.
		2398	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2399	* the configuration information for the specified SPI module.
		2400	* @retval HAL status
		2401	*/
		2402	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
		2403	{
		2404	HAL_StatusTypeDef errorcode = HAL_OK;
		2405	/* The Lock is not implemented on this API to allow the user application
		2406	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
		2407	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
		2408	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
		2409	*/
		2410
		2411	/* Abort the SPI DMA tx Stream/Channel */
		2412	if (hspi->hdmatx != NULL)
		2413	{
		2414	if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
		2415	{
		2416	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2417	errorcode = HAL_ERROR;
		2418	}
		2419	}
		2420	/* Abort the SPI DMA rx Stream/Channel */
		2421	if (hspi->hdmarx != NULL)
		2422	{
		2423	if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
		2424	{
		2425	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2426	errorcode = HAL_ERROR;
		2427	}
		2428	}
		2429
		2430	/* Disable the SPI DMA Tx & Rx requests */
		2431	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2432	hspi->State = HAL_SPI_STATE_READY;
		2433	return errorcode;
		2434	}
		2435
		2436	/**
		2437	* @brief Handle SPI interrupt request.
		2438	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2439	* the configuration information for the specified SPI module.
		2440	* @retval None
		2441	*/
		2442	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
		2443	{
		2444	uint32_t itsource = hspi->Instance->CR2;
		2445	uint32_t itflag = hspi->Instance->SR;
		2446
		2447	/* SPI in mode Receiver ----------------------------------------------------*/
		2448	if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
		2449	(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
		2450	{
		2451	hspi->RxISR(hspi);
		2452	return;
		2453	}
		2454
		2455	/* SPI in mode Transmitter -------------------------------------------------*/
		2456	if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
		2457	{
		2458	hspi->TxISR(hspi);
		2459	return;
		2460	}
		2461
		2462	/* SPI in Error Treatment --------------------------------------------------*/
		2463	if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) \|\| (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
		2464	&& (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
		2465	{
		2466	/* SPI Overrun error interrupt occurred ----------------------------------*/
		2467	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
		2468	{
		2469	if (hspi->State != HAL_SPI_STATE_BUSY_TX)
		2470	{
		2471	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
		2472	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2473	}
		2474	else
		2475	{
		2476	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2477	return;
		2478	}
		2479	}
		2480
		2481	/* SPI Mode Fault error interrupt occurred -------------------------------*/
		2482	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
		2483	{
		2484	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
		2485	__HAL_SPI_CLEAR_MODFFLAG(hspi);
		2486	}
		2487
		2488	/* SPI Frame error interrupt occurred ------------------------------------*/
		2489
		2490	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2491	{
		2492	/* Disable all interrupts */
		2493	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
		2494
		2495	hspi->State = HAL_SPI_STATE_READY;
		2496	/* Disable the SPI DMA requests if enabled */
		2497	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
		2498	{
		2499	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
		2500
		2501	/* Abort the SPI DMA Rx channel */
		2502	if (hspi->hdmarx != NULL)
		2503	{
		2504	/* Set the SPI DMA Abort callback :
		2505	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2506	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
		2507	if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
		2508	{
		2509	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2510	}
		2511	}
		2512	/* Abort the SPI DMA Tx channel */
		2513	if (hspi->hdmatx != NULL)
		2514	{
		2515	/* Set the SPI DMA Abort callback :
		2516	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2517	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
		2518	if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
		2519	{
		2520	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2521	}
		2522	}
		2523	}
		2524	else
		2525	{
		2526	/* Call user error callback */
		2527	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2528	hspi->ErrorCallback(hspi);
		2529	#else
		2530	HAL_SPI_ErrorCallback(hspi);
		2531	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2532	}
		2533	}
		2534	return;
		2535	}
		2536	}
		2537
		2538	/**
		2539	* @brief Tx Transfer completed callback.
		2540	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2541	* the configuration information for SPI module.
		2542	* @retval None
		2543	*/
		2544	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
		2545	{
		2546	/* Prevent unused argument(s) compilation warning */
		2547	UNUSED(hspi);
		2548
		2549	/* NOTE : This function should not be modified, when the callback is needed,
		2550	the HAL_SPI_TxCpltCallback should be implemented in the user file
		2551	*/
		2552	}
		2553
		2554	/**
		2555	* @brief Rx Transfer completed callback.
		2556	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2557	* the configuration information for SPI module.
		2558	* @retval None
		2559	*/
		2560	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
		2561	{
		2562	/* Prevent unused argument(s) compilation warning */
		2563	UNUSED(hspi);
		2564
		2565	/* NOTE : This function should not be modified, when the callback is needed,
		2566	the HAL_SPI_RxCpltCallback should be implemented in the user file
		2567	*/
		2568	}
		2569
		2570	/**
		2571	* @brief Tx and Rx Transfer completed callback.
		2572	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2573	* the configuration information for SPI module.
		2574	* @retval None
		2575	*/
		2576	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
		2577	{
		2578	/* Prevent unused argument(s) compilation warning */
		2579	UNUSED(hspi);
		2580
		2581	/* NOTE : This function should not be modified, when the callback is needed,
		2582	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
		2583	*/
		2584	}
		2585
		2586	/**
		2587	* @brief Tx Half Transfer completed callback.
		2588	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2589	* the configuration information for SPI module.
		2590	* @retval None
		2591	*/
		2592	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2593	{
		2594	/* Prevent unused argument(s) compilation warning */
		2595	UNUSED(hspi);
		2596
		2597	/* NOTE : This function should not be modified, when the callback is needed,
		2598	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
		2599	*/
		2600	}
		2601
		2602	/**
		2603	* @brief Rx Half Transfer completed callback.
		2604	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2605	* the configuration information for SPI module.
		2606	* @retval None
		2607	*/
		2608	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2609	{
		2610	/* Prevent unused argument(s) compilation warning */
		2611	UNUSED(hspi);
		2612
		2613	/* NOTE : This function should not be modified, when the callback is needed,
		2614	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
		2615	*/
		2616	}
		2617
		2618	/**
		2619	* @brief Tx and Rx Half Transfer callback.
		2620	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2621	* the configuration information for SPI module.
		2622	* @retval None
		2623	*/
		2624	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2625	{
		2626	/* Prevent unused argument(s) compilation warning */
		2627	UNUSED(hspi);
		2628
		2629	/* NOTE : This function should not be modified, when the callback is needed,
		2630	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
		2631	*/
		2632	}
		2633
		2634	/**
		2635	* @brief SPI error callback.
		2636	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2637	* the configuration information for SPI module.
		2638	* @retval None
		2639	*/
		2640	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
		2641	{
		2642	/* Prevent unused argument(s) compilation warning */
		2643	UNUSED(hspi);
		2644
		2645	/* NOTE : This function should not be modified, when the callback is needed,
		2646	the HAL_SPI_ErrorCallback should be implemented in the user file
		2647	*/
		2648	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
		2649	and user can use HAL_SPI_GetError() API to check the latest error occurred
		2650	*/
		2651	}
		2652
		2653	/**
		2654	* @brief SPI Abort Complete callback.
		2655	* @param hspi SPI handle.
		2656	* @retval None
		2657	*/
		2658	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
		2659	{
		2660	/* Prevent unused argument(s) compilation warning */
		2661	UNUSED(hspi);
		2662
		2663	/* NOTE : This function should not be modified, when the callback is needed,
		2664	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
		2665	*/
		2666	}
		2667
		2668	/**
		2669	* @}
		2670	*/
		2671
		2672	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
		2673	* @brief SPI control functions
		2674	*
		2675	@verbatim
		2676	===============================================================================
		2677	##### Peripheral State and Errors functions #####
		2678	===============================================================================
		2679	[..]
		2680	This subsection provides a set of functions allowing to control the SPI.
		2681	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
		2682	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
		2683	@endverbatim
		2684	* @{
		2685	*/
		2686
		2687	/**
		2688	* @brief Return the SPI handle state.
		2689	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2690	* the configuration information for SPI module.
		2691	* @retval SPI state
		2692	*/
		2693	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
		2694	{
		2695	/* Return SPI handle state */
		2696	return hspi->State;
		2697	}
		2698
		2699	/**
		2700	* @brief Return the SPI error code.
		2701	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2702	* the configuration information for SPI module.
		2703	* @retval SPI error code in bitmap format
		2704	*/
		2705	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
		2706	{
		2707	/* Return SPI ErrorCode */
		2708	return hspi->ErrorCode;
		2709	}
		2710
		2711	/**
		2712	* @}
		2713	*/
		2714
		2715	/**
		2716	* @}
		2717	*/
		2718
		2719	/** @addtogroup SPI_Private_Functions
		2720	* @brief Private functions
		2721	* @{
		2722	*/
		2723
		2724	/**
		2725	* @brief DMA SPI transmit process complete callback.
		2726	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2727	* the configuration information for the specified DMA module.
		2728	* @retval None
		2729	*/
		2730	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
		2731	{
		2732	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2733	uint32_t tickstart;
		2734
		2735	/* Init tickstart for timeout management*/
		2736	tickstart = HAL_GetTick();
		2737
		2738	/* DMA Normal Mode */
		2739	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2740	{
		2741	/* Disable ERR interrupt */
		2742	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		2743
		2744	/* Disable Tx DMA Request */
		2745	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		2746
		2747	/* Check the end of the transaction */
		2748	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2749	{
		2750	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2751	}
		2752
		2753	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
		2754	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		2755	{
		2756	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2757	}
		2758
		2759	hspi->TxXferCount = 0U;
		2760	hspi->State = HAL_SPI_STATE_READY;
		2761
		2762	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2763	{
		2764	/* Call user error callback */
		2765	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2766	hspi->ErrorCallback(hspi);
		2767	#else
		2768	HAL_SPI_ErrorCallback(hspi);
		2769	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2770	return;
		2771	}
		2772	}
		2773	/* Call user Tx complete callback */
		2774	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2775	hspi->TxCpltCallback(hspi);
		2776	#else
		2777	HAL_SPI_TxCpltCallback(hspi);
		2778	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2779	}
		2780
		2781	/**
		2782	* @brief DMA SPI receive process complete callback.
		2783	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2784	* the configuration information for the specified DMA module.
		2785	* @retval None
		2786	*/
		2787	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
		2788	{
		2789	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2790	uint32_t tickstart;
		2791	#if (USE_SPI_CRC != 0U)
		2792	__IO uint32_t tmpreg = 0U;
		2793	#endif /* USE_SPI_CRC */
		2794
		2795	/* Init tickstart for timeout management*/
		2796	tickstart = HAL_GetTick();
		2797
		2798	/* DMA Normal Mode */
		2799	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2800	{
		2801	/* Disable ERR interrupt */
		2802	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		2803
		2804	#if (USE_SPI_CRC != 0U)
		2805	/* CRC handling */
		2806	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2807	{
		2808	/* Wait until RXNE flag */
		2809	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2810	{
		2811	/* Error on the CRC reception */
		2812	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2813	}
		2814	/* Read CRC */
		2815	tmpreg = READ_REG(hspi->Instance->DR);
		2816	/* To avoid GCC warning */
		2817	UNUSED(tmpreg);
		2818	}
		2819	#endif /* USE_SPI_CRC */
		2820
		2821	/* Check if we are in Master RX 2 line mode */
		2822	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		2823	{
		2824	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
		2825	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2826	}
		2827	else
		2828	{
		2829	/* Normal case */
		2830	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		2831	}
		2832
		2833	/* Check the end of the transaction */
		2834	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2835	{
		2836	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		2837	}
		2838
		2839	hspi->RxXferCount = 0U;
		2840	hspi->State = HAL_SPI_STATE_READY;
		2841
		2842	#if (USE_SPI_CRC != 0U)
		2843	/* Check if CRC error occurred */
		2844	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		2845	{
		2846	/* Check if CRC error is valid or not (workaround to be applied or not) */
		2847	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		2848	{
		2849	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2850
		2851	/* Reset CRC Calculation */
		2852	SPI_RESET_CRC(hspi);
		2853	}
		2854	else
		2855	{
		2856	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		2857	}
		2858	}
		2859	#endif /* USE_SPI_CRC */
		2860
		2861	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2862	{
		2863	/* Call user error callback */
		2864	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2865	hspi->ErrorCallback(hspi);
		2866	#else
		2867	HAL_SPI_ErrorCallback(hspi);
		2868	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2869	return;
		2870	}
		2871	}
		2872	/* Call user Rx complete callback */
		2873	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2874	hspi->RxCpltCallback(hspi);
		2875	#else
		2876	HAL_SPI_RxCpltCallback(hspi);
		2877	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2878	}
		2879
		2880	/**
		2881	* @brief DMA SPI transmit receive process complete callback.
		2882	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2883	* the configuration information for the specified DMA module.
		2884	* @retval None
		2885	*/
		2886	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		2887	{
		2888	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2889	uint32_t tickstart;
		2890	#if (USE_SPI_CRC != 0U)
		2891	__IO uint32_t tmpreg = 0U;
		2892	#endif /* USE_SPI_CRC */
		2893
		2894	/* Init tickstart for timeout management*/
		2895	tickstart = HAL_GetTick();
		2896
		2897	/* DMA Normal Mode */
		2898	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		2899	{
		2900	/* Disable ERR interrupt */
		2901	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		2902
		2903	#if (USE_SPI_CRC != 0U)
		2904	/* CRC handling */
		2905	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2906	{
		2907	/* Wait the CRC data */
		2908	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2909	{
		2910	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2911	}
		2912	/* Read CRC to Flush DR and RXNE flag */
		2913	tmpreg = READ_REG(hspi->Instance->DR);
		2914	/* To avoid GCC warning */
		2915	UNUSED(tmpreg);
		2916	}
		2917	#endif /* USE_SPI_CRC */
		2918
		2919	/* Check the end of the transaction */
		2920	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		2921	{
		2922	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		2923	}
		2924
		2925	/* Disable Rx/Tx DMA Request */
		2926	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2927
		2928	hspi->TxXferCount = 0U;
		2929	hspi->RxXferCount = 0U;
		2930	hspi->State = HAL_SPI_STATE_READY;
		2931
		2932	#if (USE_SPI_CRC != 0U)
		2933	/* Check if CRC error occurred */
		2934	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		2935	{
		2936	/* Check if CRC error is valid or not (workaround to be applied or not) */
		2937	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		2938	{
		2939	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		2940
		2941	/* Reset CRC Calculation */
		2942	SPI_RESET_CRC(hspi);
		2943	}
		2944	else
		2945	{
		2946	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		2947	}
		2948	}
		2949	#endif /* USE_SPI_CRC */
		2950
		2951	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2952	{
		2953	/* Call user error callback */
		2954	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2955	hspi->ErrorCallback(hspi);
		2956	#else
		2957	HAL_SPI_ErrorCallback(hspi);
		2958	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2959	return;
		2960	}
		2961	}
		2962	/* Call user TxRx complete callback */
		2963	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2964	hspi->TxRxCpltCallback(hspi);
		2965	#else
		2966	HAL_SPI_TxRxCpltCallback(hspi);
		2967	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2968	}
		2969
		2970	/**
		2971	* @brief DMA SPI half transmit process complete callback.
		2972	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2973	* the configuration information for the specified DMA module.
		2974	* @retval None
		2975	*/
		2976	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
		2977	{
		2978	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2979
		2980	/* Call user Tx half complete callback */
		2981	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2982	hspi->TxHalfCpltCallback(hspi);
		2983	#else
		2984	HAL_SPI_TxHalfCpltCallback(hspi);
		2985	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2986	}
		2987
		2988	/**
		2989	* @brief DMA SPI half receive process complete callback
		2990	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		2991	* the configuration information for the specified DMA module.
		2992	* @retval None
		2993	*/
		2994	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
		2995	{
		2996	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		2997
		2998	/* Call user Rx half complete callback */
		2999	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3000	hspi->RxHalfCpltCallback(hspi);
		3001	#else
		3002	HAL_SPI_RxHalfCpltCallback(hspi);
		3003	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3004	}
		3005
		3006	/**
		3007	* @brief DMA SPI half transmit receive process complete callback.
		3008	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3009	* the configuration information for the specified DMA module.
		3010	* @retval None
		3011	*/
		3012	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		3013	{
		3014	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3015
		3016	/* Call user TxRx half complete callback */
		3017	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3018	hspi->TxRxHalfCpltCallback(hspi);
		3019	#else
		3020	HAL_SPI_TxRxHalfCpltCallback(hspi);
		3021	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3022	}
		3023
		3024	/**
		3025	* @brief DMA SPI communication error callback.
		3026	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3027	* the configuration information for the specified DMA module.
		3028	* @retval None
		3029	*/
		3030	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
		3031	{
		3032	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3033
		3034	/* Stop the disable DMA transfer on SPI side */
		3035	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		3036
		3037	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		3038	hspi->State = HAL_SPI_STATE_READY;
		3039	/* Call user error callback */
		3040	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3041	hspi->ErrorCallback(hspi);
		3042	#else
		3043	HAL_SPI_ErrorCallback(hspi);
		3044	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3045	}
		3046
		3047	/**
		3048	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
		3049	* (To be called at end of DMA Abort procedure following error occurrence).
		3050	* @param hdma DMA handle.
		3051	* @retval None
		3052	*/
		3053	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
		3054	{
		3055	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3056	hspi->RxXferCount = 0U;
		3057	hspi->TxXferCount = 0U;
		3058
		3059	/* Call user error callback */
		3060	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3061	hspi->ErrorCallback(hspi);
		3062	#else
		3063	HAL_SPI_ErrorCallback(hspi);
		3064	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3065	}
		3066
		3067	/**
		3068	* @brief DMA SPI Tx communication abort callback, when initiated by user
		3069	* (To be called at end of DMA Tx Abort procedure following user abort request).
		3070	* @note When this callback is executed, User Abort complete call back is called only if no
		3071	* Abort still ongoing for Rx DMA Handle.
		3072	* @param hdma DMA handle.
		3073	* @retval None
		3074	*/
		3075	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
		3076	{
		3077	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3078	__IO uint32_t count;
		3079
		3080	hspi->hdmatx->XferAbortCallback = NULL;
		3081	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3082
		3083	/* Disable Tx DMA Request */
		3084	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		3085
		3086	/* Wait until TXE flag is set */
		3087	do
		3088	{
		3089	if (count == 0U)
		3090	{
		3091	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		3092	break;
		3093	}
		3094	count--;
		3095	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3096
		3097	/* Check if an Abort process is still ongoing */
		3098	if (hspi->hdmarx != NULL)
		3099	{
		3100	if (hspi->hdmarx->XferAbortCallback != NULL)
		3101	{
		3102	return;
		3103	}
		3104	}
		3105
		3106	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
		3107	hspi->RxXferCount = 0U;
		3108	hspi->TxXferCount = 0U;
		3109
		3110	/* Check no error during Abort procedure */
		3111	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
		3112	{
		3113	/* Reset errorCode */
		3114	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		3115	}
		3116
		3117	/* Clear the Error flags in the SR register */
		3118	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3119
		3120	/* Restore hspi->State to Ready */
		3121	hspi->State = HAL_SPI_STATE_READY;
		3122
		3123	/* Call user Abort complete callback */
		3124	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3125	hspi->AbortCpltCallback(hspi);
		3126	#else
		3127	HAL_SPI_AbortCpltCallback(hspi);
		3128	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3129	}
		3130
		3131	/**
		3132	* @brief DMA SPI Rx communication abort callback, when initiated by user
		3133	* (To be called at end of DMA Rx Abort procedure following user abort request).
		3134	* @note When this callback is executed, User Abort complete call back is called only if no
		3135	* Abort still ongoing for Tx DMA Handle.
		3136	* @param hdma DMA handle.
		3137	* @retval None
		3138	*/
		3139	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
		3140	{
		3141	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3142
		3143	/* Disable SPI Peripheral */
		3144	__HAL_SPI_DISABLE(hspi);
		3145
		3146	hspi->hdmarx->XferAbortCallback = NULL;
		3147
		3148	/* Disable Rx DMA Request */
		3149	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		3150
		3151	/* Check Busy flag */
		3152	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3153	{
		3154	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		3155	}
		3156
		3157	/* Check if an Abort process is still ongoing */
		3158	if (hspi->hdmatx != NULL)
		3159	{
		3160	if (hspi->hdmatx->XferAbortCallback != NULL)
		3161	{
		3162	return;
		3163	}
		3164	}
		3165
		3166	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
		3167	hspi->RxXferCount = 0U;
		3168	hspi->TxXferCount = 0U;
		3169
		3170	/* Check no error during Abort procedure */
		3171	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
		3172	{
		3173	/* Reset errorCode */
		3174	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		3175	}
		3176
		3177	/* Clear the Error flags in the SR register */
		3178	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3179
		3180	/* Restore hspi->State to Ready */
		3181	hspi->State = HAL_SPI_STATE_READY;
		3182
		3183	/* Call user Abort complete callback */
		3184	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3185	hspi->AbortCpltCallback(hspi);
		3186	#else
		3187	HAL_SPI_AbortCpltCallback(hspi);
		3188	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3189	}
		3190
		3191	/**
		3192	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		3193	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3194	* the configuration information for SPI module.
		3195	* @retval None
		3196	*/
		3197	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3198	{
		3199	/* Receive data in 8bit mode */
		3200	hspi->pRxBuffPtr = ((__IO uint8_t *)&hspi->Instance->DR);
		3201	hspi->pRxBuffPtr++;
		3202	hspi->RxXferCount--;
		3203
		3204	/* Check end of the reception */
		3205	if (hspi->RxXferCount == 0U)
		3206	{
		3207	#if (USE_SPI_CRC != 0U)
		3208	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3209	{
		3210	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
		3211	return;
		3212	}
		3213	#endif /* USE_SPI_CRC */
		3214
		3215	/* Disable RXNE and ERR interrupt */
		3216	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3217
		3218	if (hspi->TxXferCount == 0U)
		3219	{
		3220	SPI_CloseRxTx_ISR(hspi);
		3221	}
		3222	}
		3223	}
		3224
		3225	#if (USE_SPI_CRC != 0U)
		3226	/**
		3227	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		3228	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3229	* the configuration information for SPI module.
		3230	* @retval None
		3231	*/
		3232	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		3233	{
		3234	__IO uint8_t *ptmpreg8;
		3235	__IO uint8_t tmpreg8 = 0;
		3236
		3237	/* Initialize the 8bit temporary pointer */
		3238	ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
		3239	/* Read 8bit CRC to flush Data Register */
		3240	tmpreg8 = *ptmpreg8;
		3241	/* To avoid GCC warning */
		3242	UNUSED(tmpreg8);
		3243
		3244	/* Disable RXNE and ERR interrupt */
		3245	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3246
		3247	if (hspi->TxXferCount == 0U)
		3248	{
		3249	SPI_CloseRxTx_ISR(hspi);
		3250	}
		3251	}
		3252	#endif /* USE_SPI_CRC */
		3253
		3254	/**
		3255	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
		3256	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3257	* the configuration information for SPI module.
		3258	* @retval None
		3259	*/
		3260	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3261	{
		3262	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		3263	hspi->pTxBuffPtr++;
		3264	hspi->TxXferCount--;
		3265
		3266	/* Check the end of the transmission */
		3267	if (hspi->TxXferCount == 0U)
		3268	{
		3269	#if (USE_SPI_CRC != 0U)
		3270	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3271	{
		3272	/* Set CRC Next Bit to send CRC */
		3273	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3274	/* Disable TXE interrupt */
		3275	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3276	return;
		3277	}
		3278	#endif /* USE_SPI_CRC */
		3279
		3280	/* Disable TXE interrupt */
		3281	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3282
		3283	if (hspi->RxXferCount == 0U)
		3284	{
		3285	SPI_CloseRxTx_ISR(hspi);
		3286	}
		3287	}
		3288	}
		3289
		3290	/**
		3291	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
		3292	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3293	* the configuration information for SPI module.
		3294	* @retval None
		3295	*/
		3296	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3297	{
		3298	/* Receive data in 16 Bit mode */
		3299	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3300	hspi->pRxBuffPtr += sizeof(uint16_t);
		3301	hspi->RxXferCount--;
		3302
		3303	if (hspi->RxXferCount == 0U)
		3304	{
		3305	#if (USE_SPI_CRC != 0U)
		3306	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3307	{
		3308	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
		3309	return;
		3310	}
		3311	#endif /* USE_SPI_CRC */
		3312
		3313	/* Disable RXNE interrupt */
		3314	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		3315
		3316	if (hspi->TxXferCount == 0U)
		3317	{
		3318	SPI_CloseRxTx_ISR(hspi);
		3319	}
		3320	}
		3321	}
		3322
		3323	#if (USE_SPI_CRC != 0U)
		3324	/**
		3325	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
		3326	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3327	* the configuration information for SPI module.
		3328	* @retval None
		3329	*/
		3330	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		3331	{
		3332	__IO uint32_t tmpreg = 0U;
		3333
		3334	/* Read 16bit CRC to flush Data Register */
		3335	tmpreg = READ_REG(hspi->Instance->DR);
		3336	/* To avoid GCC warning */
		3337	UNUSED(tmpreg);
		3338
		3339	/* Disable RXNE interrupt */
		3340	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		3341
		3342	SPI_CloseRxTx_ISR(hspi);
		3343	}
		3344	#endif /* USE_SPI_CRC */
		3345
		3346	/**
		3347	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
		3348	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3349	* the configuration information for SPI module.
		3350	* @retval None
		3351	*/
		3352	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3353	{
		3354	/* Transmit data in 16 Bit mode */
		3355	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3356	hspi->pTxBuffPtr += sizeof(uint16_t);
		3357	hspi->TxXferCount--;
		3358
		3359	/* Enable CRC Transmission */
		3360	if (hspi->TxXferCount == 0U)
		3361	{
		3362	#if (USE_SPI_CRC != 0U)
		3363	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3364	{
		3365	/* Set CRC Next Bit to send CRC */
		3366	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3367	/* Disable TXE interrupt */
		3368	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3369	return;
		3370	}
		3371	#endif /* USE_SPI_CRC */
		3372
		3373	/* Disable TXE interrupt */
		3374	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3375
		3376	if (hspi->RxXferCount == 0U)
		3377	{
		3378	SPI_CloseRxTx_ISR(hspi);
		3379	}
		3380	}
		3381	}
		3382
		3383	#if (USE_SPI_CRC != 0U)
		3384	/**
		3385	* @brief Manage the CRC 8-bit receive in Interrupt context.
		3386	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3387	* the configuration information for SPI module.
		3388	* @retval None
		3389	*/
		3390	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		3391	{
		3392	__IO uint8_t *ptmpreg8;
		3393	__IO uint8_t tmpreg8 = 0;
		3394
		3395	/* Initialize the 8bit temporary pointer */
		3396	ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
		3397	/* Read 8bit CRC to flush Data Register */
		3398	tmpreg8 = *ptmpreg8;
		3399	/* To avoid GCC warning */
		3400	UNUSED(tmpreg8);
		3401
		3402	SPI_CloseRx_ISR(hspi);
		3403	}
		3404	#endif /* USE_SPI_CRC */
		3405
		3406	/**
		3407	* @brief Manage the receive 8-bit in Interrupt context.
		3408	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3409	* the configuration information for SPI module.
		3410	* @retval None
		3411	*/
		3412	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3413	{
		3414	hspi->pRxBuffPtr = ((__IO uint8_t *)&hspi->Instance->DR);
		3415	hspi->pRxBuffPtr++;
		3416	hspi->RxXferCount--;
		3417
		3418	#if (USE_SPI_CRC != 0U)
		3419	/* Enable CRC Transmission */
		3420	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		3421	{
		3422	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3423	}
		3424	/* Check if CRCNEXT is well reset by hardware */
		3425	if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
		3426	{
		3427	/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
		3428	CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3429	}
		3430
		3431	#endif /* USE_SPI_CRC */
		3432
		3433	if (hspi->RxXferCount == 0U)
		3434	{
		3435	#if (USE_SPI_CRC != 0U)
		3436	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3437	{
		3438	hspi->RxISR = SPI_RxISR_8BITCRC;
		3439	return;
		3440	}
		3441	#endif /* USE_SPI_CRC */
		3442	SPI_CloseRx_ISR(hspi);
		3443	}
		3444	}
		3445
		3446	#if (USE_SPI_CRC != 0U)
		3447	/**
		3448	* @brief Manage the CRC 16-bit receive in Interrupt context.
		3449	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3450	* the configuration information for SPI module.
		3451	* @retval None
		3452	*/
		3453	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		3454	{
		3455	__IO uint32_t tmpreg = 0U;
		3456
		3457	/* Read 16bit CRC to flush Data Register */
		3458	tmpreg = READ_REG(hspi->Instance->DR);
		3459	/* To avoid GCC warning */
		3460	UNUSED(tmpreg);
		3461
		3462	/* Disable RXNE and ERR interrupt */
		3463	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3464
		3465	SPI_CloseRx_ISR(hspi);
		3466	}
		3467	#endif /* USE_SPI_CRC */
		3468
		3469	/**
		3470	* @brief Manage the 16-bit receive in Interrupt context.
		3471	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3472	* the configuration information for SPI module.
		3473	* @retval None
		3474	*/
		3475	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3476	{
		3477	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3478	hspi->pRxBuffPtr += sizeof(uint16_t);
		3479	hspi->RxXferCount--;
		3480
		3481	#if (USE_SPI_CRC != 0U)
		3482	/* Enable CRC Transmission */
		3483	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		3484	{
		3485	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3486	}
		3487	/* Check if CRCNEXT is well reset by hardware */
		3488	if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
		3489	{
		3490	/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
		3491	CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3492	}
		3493
		3494	#endif /* USE_SPI_CRC */
		3495
		3496	if (hspi->RxXferCount == 0U)
		3497	{
		3498	#if (USE_SPI_CRC != 0U)
		3499	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3500	{
		3501	hspi->RxISR = SPI_RxISR_16BITCRC;
		3502	return;
		3503	}
		3504	#endif /* USE_SPI_CRC */
		3505	SPI_CloseRx_ISR(hspi);
		3506	}
		3507	}
		3508
		3509	/**
		3510	* @brief Handle the data 8-bit transmit in Interrupt mode.
		3511	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3512	* the configuration information for SPI module.
		3513	* @retval None
		3514	*/
		3515	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3516	{
		3517	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		3518	hspi->pTxBuffPtr++;
		3519	hspi->TxXferCount--;
		3520
		3521	if (hspi->TxXferCount == 0U)
		3522	{
		3523	#if (USE_SPI_CRC != 0U)
		3524	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3525	{
		3526	/* Enable CRC Transmission */
		3527	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3528	}
		3529	#endif /* USE_SPI_CRC */
		3530	SPI_CloseTx_ISR(hspi);
		3531	}
		3532	}
		3533
		3534	/**
		3535	* @brief Handle the data 16-bit transmit in Interrupt mode.
		3536	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3537	* the configuration information for SPI module.
		3538	* @retval None
		3539	*/
		3540	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3541	{
		3542	/* Transmit data in 16 Bit mode */
		3543	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3544	hspi->pTxBuffPtr += sizeof(uint16_t);
		3545	hspi->TxXferCount--;
		3546
		3547	if (hspi->TxXferCount == 0U)
		3548	{
		3549	#if (USE_SPI_CRC != 0U)
		3550	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3551	{
		3552	/* Enable CRC Transmission */
		3553	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3554	}
		3555	#endif /* USE_SPI_CRC */
		3556	SPI_CloseTx_ISR(hspi);
		3557	}
		3558	}
		3559
		3560	/**
		3561	* @brief Handle SPI Communication Timeout.
		3562	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3563	* the configuration information for SPI module.
		3564	* @param Flag SPI flag to check
		3565	* @param State flag state to check
		3566	* @param Timeout Timeout duration
		3567	* @param Tickstart tick start value
		3568	* @retval HAL status
		3569	*/
		3570	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
		3571	uint32_t Timeout, uint32_t Tickstart)
		3572	{
		3573	__IO uint32_t count;
		3574	uint32_t tmp_timeout;
		3575	uint32_t tmp_tickstart;
		3576
		3577	/* Adjust Timeout value in case of end of transfer */
		3578	tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
		3579	tmp_tickstart = HAL_GetTick();
		3580
		3581	/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
		3582	count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
		3583
		3584	while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
		3585	{
		3586	if (Timeout != HAL_MAX_DELAY)
		3587	{
		3588	if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) \|\| (tmp_timeout == 0U))
		3589	{
		3590	/* Disable the SPI and reset the CRC: the CRC value should be cleared
		3591	on both master and slave sides in order to resynchronize the master
		3592	and slave for their respective CRC calculation */
		3593
		3594	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
		3595	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		3596
		3597	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3598	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3599	{
		3600	/* Disable SPI peripheral */
		3601	__HAL_SPI_DISABLE(hspi);
		3602	}
		3603
		3604	/* Reset CRC Calculation */
		3605	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3606	{
		3607	SPI_RESET_CRC(hspi);
		3608	}
		3609
		3610	hspi->State = HAL_SPI_STATE_READY;
		3611
		3612	/* Process Unlocked */
		3613	__HAL_UNLOCK(hspi);
		3614
		3615	return HAL_TIMEOUT;
		3616	}
		3617	/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
		3618	if (count == 0U)
		3619	{
		3620	tmp_timeout = 0U;
		3621	}
		3622	count--;
		3623	}
		3624	}
		3625
		3626	return HAL_OK;
		3627	}
		3628
		3629	/**
		3630	* @brief Handle the check of the RX transaction complete.
		3631	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3632	* the configuration information for SPI module.
		3633	* @param Timeout Timeout duration
		3634	* @param Tickstart tick start value
		3635	* @retval HAL status
		3636	*/
		3637	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		3638	{
		3639	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3640	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3641	{
		3642	/* Disable SPI peripheral */
		3643	__HAL_SPI_DISABLE(hspi);
		3644	}
		3645
		3646	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
		3647	{
		3648	/* Wait the RXNE reset */
		3649	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
		3650	{
		3651	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3652	return HAL_TIMEOUT;
		3653	}
		3654	}
		3655	else
		3656	{
		3657	/* Control the BSY flag */
		3658	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		3659	{
		3660	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3661	return HAL_TIMEOUT;
		3662	}
		3663	}
		3664	return HAL_OK;
		3665	}
		3666
		3667	/**
		3668	* @brief Handle the check of the RXTX or TX transaction complete.
		3669	* @param hspi SPI handle
		3670	* @param Timeout Timeout duration
		3671	* @param Tickstart tick start value
		3672	* @retval HAL status
		3673	*/
		3674	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		3675	{
		3676	/* Control the BSY flag */
		3677	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		3678	{
		3679	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3680	return HAL_TIMEOUT;
		3681	}
		3682	return HAL_OK;
		3683	}
		3684
		3685	/**
		3686	* @brief Handle the end of the RXTX transaction.
		3687	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3688	* the configuration information for SPI module.
		3689	* @retval None
		3690	*/
		3691	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
		3692	{
		3693	uint32_t tickstart;
		3694	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3695
		3696	/* Init tickstart for timeout management */
		3697	tickstart = HAL_GetTick();
		3698
		3699	/* Disable ERR interrupt */
		3700	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		3701
		3702	/* Wait until TXE flag is set */
		3703	do
		3704	{
		3705	if (count == 0U)
		3706	{
		3707	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3708	break;
		3709	}
		3710	count--;
		3711	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3712
		3713	/* Check the end of the transaction */
		3714	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3715	{
		3716	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3717	}
		3718
		3719	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3720	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3721	{
		3722	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3723	}
		3724
		3725	#if (USE_SPI_CRC != 0U)
		3726	/* Check if CRC error occurred */
		3727	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		3728	{
		3729	/* Check if CRC error is valid or not (workaround to be applied or not) */
		3730	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		3731	{
		3732	hspi->State = HAL_SPI_STATE_READY;
		3733	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3734
		3735	/* Reset CRC Calculation */
		3736	SPI_RESET_CRC(hspi);
		3737
		3738	/* Call user error callback */
		3739	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3740	hspi->ErrorCallback(hspi);
		3741	#else
		3742	HAL_SPI_ErrorCallback(hspi);
		3743	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3744	}
		3745	else
		3746	{
		3747	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3748	}
		3749	}
		3750	else
		3751	{
		3752	#endif /* USE_SPI_CRC */
		3753	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		3754	{
		3755	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
		3756	{
		3757	hspi->State = HAL_SPI_STATE_READY;
		3758	/* Call user Rx complete callback */
		3759	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3760	hspi->RxCpltCallback(hspi);
		3761	#else
		3762	HAL_SPI_RxCpltCallback(hspi);
		3763	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3764	}
		3765	else
		3766	{
		3767	hspi->State = HAL_SPI_STATE_READY;
		3768	/* Call user TxRx complete callback */
		3769	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3770	hspi->TxRxCpltCallback(hspi);
		3771	#else
		3772	HAL_SPI_TxRxCpltCallback(hspi);
		3773	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3774	}
		3775	}
		3776	else
		3777	{
		3778	hspi->State = HAL_SPI_STATE_READY;
		3779	/* Call user error callback */
		3780	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3781	hspi->ErrorCallback(hspi);
		3782	#else
		3783	HAL_SPI_ErrorCallback(hspi);
		3784	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3785	}
		3786	#if (USE_SPI_CRC != 0U)
		3787	}
		3788	#endif /* USE_SPI_CRC */
		3789	}
		3790
		3791	/**
		3792	* @brief Handle the end of the RX transaction.
		3793	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3794	* the configuration information for SPI module.
		3795	* @retval None
		3796	*/
		3797	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
		3798	{
		3799	/* Disable RXNE and ERR interrupt */
		3800	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3801
		3802	/* Check the end of the transaction */
		3803	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3804	{
		3805	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3806	}
		3807
		3808	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3809	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3810	{
		3811	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3812	}
		3813	hspi->State = HAL_SPI_STATE_READY;
		3814
		3815	#if (USE_SPI_CRC != 0U)
		3816	/* Check if CRC error occurred */
		3817	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		3818	{
		3819	/* Check if CRC error is valid or not (workaround to be applied or not) */
		3820	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
		3821	{
		3822	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3823
		3824	/* Reset CRC Calculation */
		3825	SPI_RESET_CRC(hspi);
		3826
		3827	/* Call user error callback */
		3828	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3829	hspi->ErrorCallback(hspi);
		3830	#else
		3831	HAL_SPI_ErrorCallback(hspi);
		3832	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3833	}
		3834	else
		3835	{
		3836	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3837	}
		3838	}
		3839	else
		3840	{
		3841	#endif /* USE_SPI_CRC */
		3842	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		3843	{
		3844	/* Call user Rx complete callback */
		3845	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3846	hspi->RxCpltCallback(hspi);
		3847	#else
		3848	HAL_SPI_RxCpltCallback(hspi);
		3849	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3850	}
		3851	else
		3852	{
		3853	/* Call user error callback */
		3854	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3855	hspi->ErrorCallback(hspi);
		3856	#else
		3857	HAL_SPI_ErrorCallback(hspi);
		3858	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3859	}
		3860	#if (USE_SPI_CRC != 0U)
		3861	}
		3862	#endif /* USE_SPI_CRC */
		3863	}
		3864
		3865	/**
		3866	* @brief Handle the end of the TX transaction.
		3867	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3868	* the configuration information for SPI module.
		3869	* @retval None
		3870	*/
		3871	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
		3872	{
		3873	uint32_t tickstart;
		3874	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3875
		3876	/* Init tickstart for timeout management*/
		3877	tickstart = HAL_GetTick();
		3878
		3879	/* Wait until TXE flag is set */
		3880	do
		3881	{
		3882	if (count == 0U)
		3883	{
		3884	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3885	break;
		3886	}
		3887	count--;
		3888	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3889
		3890	/* Disable TXE and ERR interrupt */
		3891	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		3892
		3893	/* Check the end of the transaction */
		3894	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3895	{
		3896	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3897	}
		3898
		3899	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		3900	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3901	{
		3902	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3903	}
		3904
		3905	hspi->State = HAL_SPI_STATE_READY;
		3906	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		3907	{
		3908	/* Call user error callback */
		3909	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3910	hspi->ErrorCallback(hspi);
		3911	#else
		3912	HAL_SPI_ErrorCallback(hspi);
		3913	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3914	}
		3915	else
		3916	{
		3917	/* Call user Rx complete callback */
		3918	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3919	hspi->TxCpltCallback(hspi);
		3920	#else
		3921	HAL_SPI_TxCpltCallback(hspi);
		3922	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3923	}
		3924	}
		3925
		3926	/**
		3927	* @brief Handle abort a Rx transaction.
		3928	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3929	* the configuration information for SPI module.
		3930	* @retval None
		3931	*/
		3932	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
		3933	{
		3934	__IO uint32_t tmpreg = 0U;
		3935	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		3936
		3937	/* Wait until TXE flag is set */
		3938	do
		3939	{
		3940	if (count == 0U)
		3941	{
		3942	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		3943	break;
		3944	}
		3945	count--;
		3946	} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
		3947
		3948	/* Disable SPI Peripheral */
		3949	__HAL_SPI_DISABLE(hspi);
		3950
		3951	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		3952	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
		3953
		3954	/* Flush Data Register by a blank read */
		3955	tmpreg = READ_REG(hspi->Instance->DR);
		3956	/* To avoid GCC warning */
		3957	UNUSED(tmpreg);
		3958
		3959	hspi->State = HAL_SPI_STATE_ABORT;
		3960	}
		3961
		3962	/**
		3963	* @brief Handle abort a Tx or Rx/Tx transaction.
		3964	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3965	* the configuration information for SPI module.
		3966	* @retval None
		3967	*/
		3968	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
		3969	{
		3970	/* Disable TXEIE interrupt */
		3971	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
		3972
		3973	/* Disable SPI Peripheral */
		3974	__HAL_SPI_DISABLE(hspi);
		3975
		3976	hspi->State = HAL_SPI_STATE_ABORT;
		3977	}
		3978
		3979	#if (USE_SPI_CRC != 0U)
		3980	/**
		3981	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
		3982	* according to SPI instance, Device type, and revision ID.
		3983	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
		3984	* the configuration information for SPI module.
		3985	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
		3986	*/
		3987	uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
		3988	{
		3989	#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
		3990	/* Check how to handle this CRC error (workaround to be applied or not) */
		3991	/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
		3992	if (hspi->Instance == SPI2)
		3993	{
		3994	if (hspi->Instance->RXCRCR == 0U)
		3995	{
		3996	return (SPI_INVALID_CRC_ERROR);
		3997	}
		3998	}
		3999	#endif /* USE_SPI_CRC_ERROR_WORKAROUND */
		4000	/* Prevent unused argument(s) compilation warning */
		4001	UNUSED(hspi);
		4002
		4003	return (SPI_VALID_CRC_ERROR);
		4004	}
		4005	#endif /* USE_SPI_CRC */
		4006	/**
		4007	* @}
		4008	*/
		4009
		4010	#endif /* HAL_SPI_MODULE_ENABLED */
		4011
		4012	/**
		4013	* @}
		4014	*/
		4015
		4016	/**
		4017	* @}
		4018	*/
		4019

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c – Rev 18